Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.59 97.84 93.81 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2855
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T2768 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3318660333 Jul 10 06:37:59 PM PDT 24 Jul 10 06:38:03 PM PDT 24 28949909 ps
T2769 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4242883300 Jul 10 06:38:05 PM PDT 24 Jul 10 06:38:11 PM PDT 24 233757397 ps
T258 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3852466088 Jul 10 06:38:17 PM PDT 24 Jul 10 06:38:22 PM PDT 24 76708787 ps
T263 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3852278037 Jul 10 06:37:58 PM PDT 24 Jul 10 06:38:02 PM PDT 24 47030044 ps
T2770 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.309970815 Jul 10 06:38:17 PM PDT 24 Jul 10 06:38:24 PM PDT 24 89484599 ps
T278 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2811598326 Jul 10 06:38:13 PM PDT 24 Jul 10 06:38:18 PM PDT 24 238011407 ps
T2771 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3978876749 Jul 10 06:38:07 PM PDT 24 Jul 10 06:38:14 PM PDT 24 91674369 ps
T238 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1393576550 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:25 PM PDT 24 281710260 ps
T279 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2697656900 Jul 10 06:37:28 PM PDT 24 Jul 10 06:37:40 PM PDT 24 872234763 ps
T2772 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1450647308 Jul 10 06:37:32 PM PDT 24 Jul 10 06:37:38 PM PDT 24 84827927 ps
T2773 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2664431046 Jul 10 06:38:06 PM PDT 24 Jul 10 06:38:15 PM PDT 24 273329472 ps
T299 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3280309053 Jul 10 06:37:49 PM PDT 24 Jul 10 06:37:58 PM PDT 24 721201296 ps
T2774 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3777278899 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:23 PM PDT 24 45942200 ps
T259 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.825916971 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:24 PM PDT 24 72902465 ps
T2775 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.376026336 Jul 10 06:38:14 PM PDT 24 Jul 10 06:38:19 PM PDT 24 54218091 ps
T2776 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1323239801 Jul 10 06:38:20 PM PDT 24 Jul 10 06:38:25 PM PDT 24 55910879 ps
T2777 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2503127168 Jul 10 06:38:14 PM PDT 24 Jul 10 06:38:20 PM PDT 24 92729336 ps
T2778 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1442017 Jul 10 06:38:19 PM PDT 24 Jul 10 06:38:24 PM PDT 24 53483378 ps
T2779 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.403968418 Jul 10 06:37:36 PM PDT 24 Jul 10 06:37:42 PM PDT 24 170453153 ps
T2780 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.799355219 Jul 10 06:37:35 PM PDT 24 Jul 10 06:37:43 PM PDT 24 695247596 ps
T2781 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.835780221 Jul 10 06:38:23 PM PDT 24 Jul 10 06:38:29 PM PDT 24 89403301 ps
T2782 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1997551173 Jul 10 06:38:13 PM PDT 24 Jul 10 06:38:18 PM PDT 24 266066461 ps
T2783 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.359936982 Jul 10 06:37:50 PM PDT 24 Jul 10 06:37:54 PM PDT 24 41357707 ps
T2784 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.775040020 Jul 10 06:38:14 PM PDT 24 Jul 10 06:38:19 PM PDT 24 71649171 ps
T2785 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3067294909 Jul 10 06:38:12 PM PDT 24 Jul 10 06:38:17 PM PDT 24 87905965 ps
T280 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1633347080 Jul 10 06:38:11 PM PDT 24 Jul 10 06:38:15 PM PDT 24 120728151 ps
T2786 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2512664472 Jul 10 06:37:57 PM PDT 24 Jul 10 06:38:02 PM PDT 24 153726518 ps
T2787 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.526688174 Jul 10 06:37:41 PM PDT 24 Jul 10 06:37:54 PM PDT 24 1276719057 ps
T2788 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1600692777 Jul 10 06:38:02 PM PDT 24 Jul 10 06:38:08 PM PDT 24 79865580 ps
T2789 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1295059614 Jul 10 06:38:25 PM PDT 24 Jul 10 06:38:34 PM PDT 24 109165210 ps
T2790 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1081706021 Jul 10 06:38:26 PM PDT 24 Jul 10 06:38:33 PM PDT 24 38481945 ps
T260 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3855491125 Jul 10 06:37:41 PM PDT 24 Jul 10 06:37:47 PM PDT 24 159096323 ps
T2791 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3477986819 Jul 10 06:38:25 PM PDT 24 Jul 10 06:38:31 PM PDT 24 63312595 ps
T2792 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.394079409 Jul 10 06:37:35 PM PDT 24 Jul 10 06:37:41 PM PDT 24 90409789 ps
T2793 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1062316396 Jul 10 06:37:31 PM PDT 24 Jul 10 06:37:38 PM PDT 24 129549157 ps
T2794 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.617518635 Jul 10 06:38:20 PM PDT 24 Jul 10 06:38:25 PM PDT 24 28256741 ps
T2795 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1992371840 Jul 10 06:38:28 PM PDT 24 Jul 10 06:38:35 PM PDT 24 38521347 ps
T2796 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2300108687 Jul 10 06:37:36 PM PDT 24 Jul 10 06:37:41 PM PDT 24 34818289 ps
T285 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.140623366 Jul 10 06:38:04 PM PDT 24 Jul 10 06:38:15 PM PDT 24 1301639994 ps
T2797 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3852549552 Jul 10 06:38:05 PM PDT 24 Jul 10 06:38:11 PM PDT 24 159416851 ps
T2798 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3352282930 Jul 10 06:37:58 PM PDT 24 Jul 10 06:38:02 PM PDT 24 44902071 ps
T261 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3737010617 Jul 10 06:37:53 PM PDT 24 Jul 10 06:37:56 PM PDT 24 63547574 ps
T2799 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3478231809 Jul 10 06:37:34 PM PDT 24 Jul 10 06:37:43 PM PDT 24 696564235 ps
T2800 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.876805238 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:23 PM PDT 24 76338135 ps
T2801 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4001903200 Jul 10 06:38:23 PM PDT 24 Jul 10 06:38:30 PM PDT 24 43111552 ps
T306 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.859621074 Jul 10 06:38:14 PM PDT 24 Jul 10 06:38:24 PM PDT 24 1180139061 ps
T2802 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3689722588 Jul 10 06:38:03 PM PDT 24 Jul 10 06:38:10 PM PDT 24 148426075 ps
T304 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.4179026950 Jul 10 06:37:59 PM PDT 24 Jul 10 06:38:07 PM PDT 24 631838400 ps
T2803 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3877380068 Jul 10 06:38:19 PM PDT 24 Jul 10 06:38:24 PM PDT 24 108309909 ps
T2804 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2044795517 Jul 10 06:38:24 PM PDT 24 Jul 10 06:38:31 PM PDT 24 45949317 ps
T2805 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.928644700 Jul 10 06:38:20 PM PDT 24 Jul 10 06:38:25 PM PDT 24 40744626 ps
T2806 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.741923495 Jul 10 06:38:27 PM PDT 24 Jul 10 06:38:33 PM PDT 24 38431693 ps
T2807 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3033982385 Jul 10 06:37:32 PM PDT 24 Jul 10 06:37:38 PM PDT 24 46540013 ps
T2808 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.267867547 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:24 PM PDT 24 45911070 ps
T2809 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2886152502 Jul 10 06:38:13 PM PDT 24 Jul 10 06:38:19 PM PDT 24 206761557 ps
T262 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1953287850 Jul 10 06:37:35 PM PDT 24 Jul 10 06:37:40 PM PDT 24 138062633 ps
T2810 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2660643223 Jul 10 06:37:41 PM PDT 24 Jul 10 06:37:48 PM PDT 24 373353797 ps
T2811 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4208966267 Jul 10 06:38:02 PM PDT 24 Jul 10 06:38:08 PM PDT 24 90078005 ps
T2812 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1899481463 Jul 10 06:38:22 PM PDT 24 Jul 10 06:38:28 PM PDT 24 54630541 ps
T2813 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4092817959 Jul 10 06:37:59 PM PDT 24 Jul 10 06:38:04 PM PDT 24 38069015 ps
T2814 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1814031989 Jul 10 06:37:29 PM PDT 24 Jul 10 06:37:37 PM PDT 24 111827513 ps
T2815 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.469431372 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:24 PM PDT 24 134774394 ps
T2816 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3715404950 Jul 10 06:37:50 PM PDT 24 Jul 10 06:37:55 PM PDT 24 104866757 ps
T2817 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1284716620 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:23 PM PDT 24 83810939 ps
T2818 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1312079875 Jul 10 06:38:11 PM PDT 24 Jul 10 06:38:15 PM PDT 24 61484071 ps
T2819 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1955900837 Jul 10 06:38:21 PM PDT 24 Jul 10 06:38:26 PM PDT 24 43934688 ps
T2820 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1181447942 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:25 PM PDT 24 126570572 ps
T2821 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.724070624 Jul 10 06:38:11 PM PDT 24 Jul 10 06:38:15 PM PDT 24 79911415 ps
T2822 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3566802760 Jul 10 06:37:35 PM PDT 24 Jul 10 06:37:40 PM PDT 24 99141726 ps
T305 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3833091863 Jul 10 06:38:06 PM PDT 24 Jul 10 06:38:14 PM PDT 24 385147833 ps
T2823 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.571143595 Jul 10 06:38:12 PM PDT 24 Jul 10 06:38:16 PM PDT 24 231684163 ps
T2824 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.543975114 Jul 10 06:38:04 PM PDT 24 Jul 10 06:38:12 PM PDT 24 255557027 ps
T2825 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2763287862 Jul 10 06:38:14 PM PDT 24 Jul 10 06:38:18 PM PDT 24 59585002 ps
T2826 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2005396039 Jul 10 06:37:43 PM PDT 24 Jul 10 06:37:46 PM PDT 24 52142574 ps
T2827 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1002786380 Jul 10 06:37:59 PM PDT 24 Jul 10 06:38:06 PM PDT 24 547876333 ps
T2828 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3416106942 Jul 10 06:38:21 PM PDT 24 Jul 10 06:38:26 PM PDT 24 64119917 ps
T2829 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.792138306 Jul 10 06:37:51 PM PDT 24 Jul 10 06:37:57 PM PDT 24 142850453 ps
T2830 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2208575691 Jul 10 06:38:18 PM PDT 24 Jul 10 06:38:24 PM PDT 24 52959594 ps
T2831 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1383183173 Jul 10 06:38:06 PM PDT 24 Jul 10 06:38:13 PM PDT 24 69182238 ps
T2832 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2507589271 Jul 10 06:38:14 PM PDT 24 Jul 10 06:38:19 PM PDT 24 45903130 ps
T301 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.674428961 Jul 10 06:38:20 PM PDT 24 Jul 10 06:38:27 PM PDT 24 315079271 ps
T2833 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1087128604 Jul 10 06:37:58 PM PDT 24 Jul 10 06:38:03 PM PDT 24 74068981 ps
T2834 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1731176618 Jul 10 06:37:52 PM PDT 24 Jul 10 06:38:00 PM PDT 24 701616972 ps
T2835 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1981820450 Jul 10 06:38:06 PM PDT 24 Jul 10 06:38:13 PM PDT 24 79999678 ps
T2836 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1100037115 Jul 10 06:37:31 PM PDT 24 Jul 10 06:37:40 PM PDT 24 301615831 ps
T2837 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3019579383 Jul 10 06:38:04 PM PDT 24 Jul 10 06:38:11 PM PDT 24 188970923 ps
T2838 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2159125768 Jul 10 06:38:05 PM PDT 24 Jul 10 06:38:12 PM PDT 24 241340879 ps
T2839 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2763474768 Jul 10 06:38:03 PM PDT 24 Jul 10 06:38:10 PM PDT 24 111852981 ps
T2840 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3043277127 Jul 10 06:38:25 PM PDT 24 Jul 10 06:38:32 PM PDT 24 92661393 ps
T2841 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2704272352 Jul 10 06:37:28 PM PDT 24 Jul 10 06:37:38 PM PDT 24 167798872 ps
T2842 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3221994404 Jul 10 06:37:42 PM PDT 24 Jul 10 06:37:48 PM PDT 24 622970697 ps
T2843 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2566603693 Jul 10 06:38:21 PM PDT 24 Jul 10 06:38:28 PM PDT 24 458810067 ps
T2844 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2912195848 Jul 10 06:37:48 PM PDT 24 Jul 10 06:37:53 PM PDT 24 88101188 ps
T2845 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2430278743 Jul 10 06:38:06 PM PDT 24 Jul 10 06:38:12 PM PDT 24 43898036 ps
T2846 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.729146989 Jul 10 06:37:41 PM PDT 24 Jul 10 06:37:46 PM PDT 24 157942736 ps
T2847 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.328525408 Jul 10 06:37:31 PM PDT 24 Jul 10 06:37:42 PM PDT 24 834309812 ps
T2848 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4073578898 Jul 10 06:37:51 PM PDT 24 Jul 10 06:37:56 PM PDT 24 133268102 ps
T2849 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1314022616 Jul 10 06:37:36 PM PDT 24 Jul 10 06:37:45 PM PDT 24 717686089 ps
T2850 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2700881436 Jul 10 06:37:50 PM PDT 24 Jul 10 06:37:55 PM PDT 24 75059576 ps
T2851 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1861039960 Jul 10 06:38:22 PM PDT 24 Jul 10 06:38:28 PM PDT 24 78649354 ps
T302 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4121192383 Jul 10 06:38:19 PM PDT 24 Jul 10 06:38:26 PM PDT 24 371200993 ps
T2852 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2956276406 Jul 10 06:37:30 PM PDT 24 Jul 10 06:37:38 PM PDT 24 107458952 ps
T2853 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.311977411 Jul 10 06:37:50 PM PDT 24 Jul 10 06:37:57 PM PDT 24 297298649 ps
T2854 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3702285250 Jul 10 06:38:19 PM PDT 24 Jul 10 06:38:25 PM PDT 24 60448763 ps
T2855 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4193604870 Jul 10 06:37:29 PM PDT 24 Jul 10 06:37:36 PM PDT 24 133936835 ps

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2012470084
Short name T31
Test name
Test status
Simulation time 175935877 ps
CPU time 1.8 seconds
Started Jul 10 06:40:47 PM PDT 24
Finished Jul 10 06:40:54 PM PDT 24
Peak memory 206588 kb
Host smart-90cf17b5-c665-4410-85d5-f746b6b76bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20124
70084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2012470084
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3325405872
Short name T7
Test name
Test status
Simulation time 23342579405 ps
CPU time 24.68 seconds
Started Jul 10 06:43:32 PM PDT 24
Finished Jul 10 06:44:03 PM PDT 24
Peak memory 206652 kb
Host smart-51106cee-4082-42ce-8523-d1be6ad41fd3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3325405872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.3325405872
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.720634986
Short name T202
Test name
Test status
Simulation time 38499596 ps
CPU time 0.67 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:38:32 PM PDT 24
Peak memory 205984 kb
Host smart-bdec3e79-43e9-4422-9429-b6b4d8a33c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=720634986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.720634986
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3120554816
Short name T19
Test name
Test status
Simulation time 837005810 ps
CPU time 2.2 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206588 kb
Host smart-462af630-cf38-4332-835f-e66a2201e0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31205
54816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3120554816
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1781562261
Short name T1
Test name
Test status
Simulation time 520388378 ps
CPU time 1.52 seconds
Started Jul 10 06:42:24 PM PDT 24
Finished Jul 10 06:42:31 PM PDT 24
Peak memory 206408 kb
Host smart-a9ba380a-c896-454d-9b70-8acbb65fd137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17815
62261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1781562261
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.820979602
Short name T198
Test name
Test status
Simulation time 615060791 ps
CPU time 4.35 seconds
Started Jul 10 06:38:14 PM PDT 24
Finished Jul 10 06:38:22 PM PDT 24
Peak memory 206364 kb
Host smart-4bf331a5-c87a-4193-a81f-5f502146e6f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=820979602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.820979602
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1353135581
Short name T283
Test name
Test status
Simulation time 45707769 ps
CPU time 0.7 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 206012 kb
Host smart-d926f23b-805f-49f5-aad4-cd59f901ab4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1353135581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1353135581
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.562044763
Short name T321
Test name
Test status
Simulation time 202877116 ps
CPU time 0.89 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:31 PM PDT 24
Peak memory 206392 kb
Host smart-f61ca4ed-36a0-4e6b-b08d-0ecdd959d5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56204
4763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.562044763
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.4290334926
Short name T4
Test name
Test status
Simulation time 3606157312 ps
CPU time 26.75 seconds
Started Jul 10 06:41:18 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206684 kb
Host smart-c7e03a52-819c-4ab3-85fb-7154e833edc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42903
34926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.4290334926
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2645538180
Short name T39
Test name
Test status
Simulation time 143261152 ps
CPU time 0.76 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:41:27 PM PDT 24
Peak memory 206388 kb
Host smart-08abec14-3061-44a0-8df9-15de420144e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26455
38180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2645538180
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2200296386
Short name T41
Test name
Test status
Simulation time 5146451910 ps
CPU time 37.51 seconds
Started Jul 10 06:45:43 PM PDT 24
Finished Jul 10 06:46:26 PM PDT 24
Peak memory 206656 kb
Host smart-288d342e-05cf-4098-b62a-caf8d26f4204
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2200296386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2200296386
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.549034206
Short name T112
Test name
Test status
Simulation time 275693800 ps
CPU time 1.09 seconds
Started Jul 10 06:38:26 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206384 kb
Host smart-4829128e-c6cf-48c2-9441-8a0e69e1abc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54903
4206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.549034206
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3539472061
Short name T27
Test name
Test status
Simulation time 207664654 ps
CPU time 0.87 seconds
Started Jul 10 06:39:09 PM PDT 24
Finished Jul 10 06:39:15 PM PDT 24
Peak memory 206400 kb
Host smart-969e7f83-d319-4c70-9848-46777df5b33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35394
72061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3539472061
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1515719607
Short name T191
Test name
Test status
Simulation time 1479715643 ps
CPU time 2.68 seconds
Started Jul 10 06:39:57 PM PDT 24
Finished Jul 10 06:40:04 PM PDT 24
Peak memory 225268 kb
Host smart-bcb780d1-be90-4d57-a025-c43d1cfd5174
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1515719607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1515719607
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2066020203
Short name T224
Test name
Test status
Simulation time 157239608 ps
CPU time 3.3 seconds
Started Jul 10 06:38:12 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 221964 kb
Host smart-38d7f1fd-b5cc-4e7e-8401-b66e90737ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2066020203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2066020203
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2477264734
Short name T47
Test name
Test status
Simulation time 13385847241 ps
CPU time 13.06 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:36 PM PDT 24
Peak memory 206420 kb
Host smart-eeb21563-e75d-464f-8a07-10bfcd733cde
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2477264734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2477264734
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2398422511
Short name T24
Test name
Test status
Simulation time 50300703 ps
CPU time 0.67 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206372 kb
Host smart-7812c6d9-7fc2-4372-a72f-aebd37150832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23984
22511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2398422511
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3619742614
Short name T286
Test name
Test status
Simulation time 35970130 ps
CPU time 0.69 seconds
Started Jul 10 06:38:20 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 206000 kb
Host smart-d1808a0d-ec25-4656-be48-f65067844a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3619742614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3619742614
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3541622126
Short name T249
Test name
Test status
Simulation time 188031968 ps
CPU time 2.05 seconds
Started Jul 10 06:37:35 PM PDT 24
Finished Jul 10 06:37:41 PM PDT 24
Peak memory 206288 kb
Host smart-afa6d7f1-37a9-453b-8a2f-d140a41f391a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3541622126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3541622126
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1376458723
Short name T82
Test name
Test status
Simulation time 321902176 ps
CPU time 1.08 seconds
Started Jul 10 06:38:41 PM PDT 24
Finished Jul 10 06:38:47 PM PDT 24
Peak memory 206552 kb
Host smart-30656715-5270-4f7c-a12a-b0f07a7474b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764
58723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1376458723
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1544081889
Short name T50
Test name
Test status
Simulation time 271673181 ps
CPU time 1.08 seconds
Started Jul 10 06:47:06 PM PDT 24
Finished Jul 10 06:47:11 PM PDT 24
Peak memory 206376 kb
Host smart-af3e46bc-a14e-458f-ab2b-0a72fa363186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15440
81889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1544081889
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2540062705
Short name T44
Test name
Test status
Simulation time 15643549589 ps
CPU time 426.44 seconds
Started Jul 10 06:39:38 PM PDT 24
Finished Jul 10 06:46:45 PM PDT 24
Peak memory 206756 kb
Host smart-297c6344-fc25-423a-a417-cfa9a2521d84
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2540062705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2540062705
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2496025550
Short name T48
Test name
Test status
Simulation time 20170654476 ps
CPU time 20.45 seconds
Started Jul 10 06:38:49 PM PDT 24
Finished Jul 10 06:39:14 PM PDT 24
Peak memory 206432 kb
Host smart-e68ad2ef-3cf1-4a0c-bb8c-1bb06963fe25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
25550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2496025550
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.893798141
Short name T297
Test name
Test status
Simulation time 55659236 ps
CPU time 0.68 seconds
Started Jul 10 06:38:21 PM PDT 24
Finished Jul 10 06:38:27 PM PDT 24
Peak memory 206000 kb
Host smart-bd1ed730-d873-406a-a502-7244d5267000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=893798141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.893798141
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1443778628
Short name T76
Test name
Test status
Simulation time 141573593 ps
CPU time 0.77 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206404 kb
Host smart-4a52667d-a093-49b6-9b94-52492624ca1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14437
78628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1443778628
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2523270996
Short name T161
Test name
Test status
Simulation time 7699516082 ps
CPU time 126.87 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:42:13 PM PDT 24
Peak memory 206704 kb
Host smart-90412b8f-4ea1-4a52-9c8b-138906968b9e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2523270996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2523270996
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3506052609
Short name T104
Test name
Test status
Simulation time 12831337867 ps
CPU time 323.94 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:45:22 PM PDT 24
Peak memory 206728 kb
Host smart-1586ea0e-6d68-4a77-8313-34361050ce4e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3506052609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3506052609
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3172738929
Short name T240
Test name
Test status
Simulation time 822182802 ps
CPU time 4.79 seconds
Started Jul 10 06:37:30 PM PDT 24
Finished Jul 10 06:37:41 PM PDT 24
Peak memory 206364 kb
Host smart-54209c9a-bdd0-44d6-9926-b8933f1d2d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3172738929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3172738929
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3236154160
Short name T294
Test name
Test status
Simulation time 41313732 ps
CPU time 0.69 seconds
Started Jul 10 06:38:21 PM PDT 24
Finished Jul 10 06:38:27 PM PDT 24
Peak memory 206004 kb
Host smart-c1c1f8e6-5506-4b71-ac77-e4b2e4f96080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3236154160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3236154160
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3332005470
Short name T459
Test name
Test status
Simulation time 204624237 ps
CPU time 0.91 seconds
Started Jul 10 06:38:40 PM PDT 24
Finished Jul 10 06:38:46 PM PDT 24
Peak memory 206384 kb
Host smart-1bf2512b-c3b0-443b-b1f2-f12dc1c4ec03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33320
05470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3332005470
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.1048048358
Short name T55
Test name
Test status
Simulation time 300120363 ps
CPU time 1.07 seconds
Started Jul 10 06:38:49 PM PDT 24
Finished Jul 10 06:38:55 PM PDT 24
Peak memory 206380 kb
Host smart-cb840d65-7da1-49ec-8f23-f73f91309a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10480
48358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1048048358
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3221550578
Short name T159
Test name
Test status
Simulation time 213032845 ps
CPU time 0.89 seconds
Started Jul 10 06:38:30 PM PDT 24
Finished Jul 10 06:38:38 PM PDT 24
Peak memory 206396 kb
Host smart-021a0aca-4720-4a4a-a52a-f7339e3462cb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3221550578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3221550578
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3426160667
Short name T73
Test name
Test status
Simulation time 503367055 ps
CPU time 1.48 seconds
Started Jul 10 06:38:26 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206380 kb
Host smart-58e25b91-87c8-48a9-8868-1034156dd9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34261
60667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3426160667
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3363558645
Short name T109
Test name
Test status
Simulation time 1146526834 ps
CPU time 2.44 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:43:01 PM PDT 24
Peak memory 206576 kb
Host smart-dac5f431-4cb8-4e12-8413-16395fa85fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33635
58645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3363558645
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3456074325
Short name T2763
Test name
Test status
Simulation time 41384570 ps
CPU time 0.72 seconds
Started Jul 10 06:38:05 PM PDT 24
Finished Jul 10 06:38:11 PM PDT 24
Peak memory 206004 kb
Host smart-9bcf1e48-6a28-41b8-9982-009554e34d2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3456074325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3456074325
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.184119299
Short name T303
Test name
Test status
Simulation time 309540585 ps
CPU time 2.41 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 206352 kb
Host smart-805b09af-5d6e-4337-86f4-17fe79fe6080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=184119299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.184119299
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.515464312
Short name T187
Test name
Test status
Simulation time 38047587 ps
CPU time 0.72 seconds
Started Jul 10 06:41:13 PM PDT 24
Finished Jul 10 06:41:20 PM PDT 24
Peak memory 206432 kb
Host smart-480d26ba-0fa3-4073-a52a-d1e712e0431c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=515464312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.515464312
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.24491320
Short name T672
Test name
Test status
Simulation time 3585889672 ps
CPU time 4.5 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:32 PM PDT 24
Peak memory 206608 kb
Host smart-472c46ba-ff4c-47c9-b4f1-c3f725bc607e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=24491320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.24491320
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2593776378
Short name T95
Test name
Test status
Simulation time 14362940478 ps
CPU time 27.44 seconds
Started Jul 10 06:46:44 PM PDT 24
Finished Jul 10 06:47:13 PM PDT 24
Peak memory 206684 kb
Host smart-d4071e88-4e42-40ab-bfb5-367754f9c30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25937
76378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2593776378
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1393576550
Short name T238
Test name
Test status
Simulation time 281710260 ps
CPU time 2.57 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 206384 kb
Host smart-fdab2e0b-1f53-43c0-a65f-7cee3f4712aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1393576550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1393576550
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1298367469
Short name T264
Test name
Test status
Simulation time 52669421 ps
CPU time 0.8 seconds
Started Jul 10 06:37:28 PM PDT 24
Finished Jul 10 06:37:36 PM PDT 24
Peak memory 206072 kb
Host smart-faa4148b-74a3-4d73-81ec-61a5f462b30e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1298367469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1298367469
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.2324173717
Short name T90
Test name
Test status
Simulation time 132459601 ps
CPU time 0.73 seconds
Started Jul 10 06:38:26 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206372 kb
Host smart-441bbde8-32e2-4c6e-958f-9a66961ab62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23241
73717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.2324173717
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3475628905
Short name T43
Test name
Test status
Simulation time 10491823067 ps
CPU time 72.67 seconds
Started Jul 10 06:42:07 PM PDT 24
Finished Jul 10 06:43:23 PM PDT 24
Peak memory 206724 kb
Host smart-4e23e1c6-662d-413e-8ef8-9f800a62a244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34756
28905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3475628905
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3833091863
Short name T305
Test name
Test status
Simulation time 385147833 ps
CPU time 2.65 seconds
Started Jul 10 06:38:06 PM PDT 24
Finished Jul 10 06:38:14 PM PDT 24
Peak memory 206392 kb
Host smart-e01503d1-c68c-4ce0-ae82-9123abdc5972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3833091863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3833091863
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1457370486
Short name T298
Test name
Test status
Simulation time 1452281953 ps
CPU time 6 seconds
Started Jul 10 06:38:12 PM PDT 24
Finished Jul 10 06:38:20 PM PDT 24
Peak memory 206384 kb
Host smart-2cc11d48-fc2c-4c66-b183-261ffdd15248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1457370486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1457370486
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2664431046
Short name T2773
Test name
Test status
Simulation time 273329472 ps
CPU time 3.5 seconds
Started Jul 10 06:38:06 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 222564 kb
Host smart-94dd39fe-f13e-451a-a005-f6b426d4dc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2664431046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2664431046
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2560890343
Short name T189
Test name
Test status
Simulation time 13305891945 ps
CPU time 95.27 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:41:04 PM PDT 24
Peak memory 206648 kb
Host smart-ed88d105-155d-4d86-9c01-e4824ea51baf
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2560890343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2560890343
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.953712775
Short name T108
Test name
Test status
Simulation time 8407669745 ps
CPU time 248.95 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:48:44 PM PDT 24
Peak memory 206668 kb
Host smart-3f00654a-a949-459f-8f75-a4be3eb6bad6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=953712775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.953712775
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1419202762
Short name T470
Test name
Test status
Simulation time 150434822 ps
CPU time 0.79 seconds
Started Jul 10 06:41:15 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206404 kb
Host smart-93f1e0a1-5147-4cbb-a2c0-79ecd22929ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14192
02762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1419202762
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2229933666
Short name T307
Test name
Test status
Simulation time 156981570 ps
CPU time 0.77 seconds
Started Jul 10 06:38:59 PM PDT 24
Finished Jul 10 06:39:03 PM PDT 24
Peak memory 206380 kb
Host smart-222c64cb-2fc9-4f6e-be03-b8ecfb22bb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22299
33666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2229933666
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2992760556
Short name T69
Test name
Test status
Simulation time 132643098 ps
CPU time 0.81 seconds
Started Jul 10 06:39:37 PM PDT 24
Finished Jul 10 06:39:39 PM PDT 24
Peak memory 206372 kb
Host smart-4616b215-c6ab-4423-9137-4396f342ada3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29927
60556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2992760556
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.4199323821
Short name T172
Test name
Test status
Simulation time 4972812765 ps
CPU time 35.51 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:41:25 PM PDT 24
Peak memory 206644 kb
Host smart-e0f30afe-a0b4-4032-be55-655e333b6bed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4199323821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.4199323821
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.1659391369
Short name T60
Test name
Test status
Simulation time 167502065 ps
CPU time 0.83 seconds
Started Jul 10 06:38:29 PM PDT 24
Finished Jul 10 06:38:36 PM PDT 24
Peak memory 206400 kb
Host smart-a058867f-471d-4695-a0b2-b0f352348686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16593
91369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1659391369
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.2986279052
Short name T70
Test name
Test status
Simulation time 4163071237 ps
CPU time 9.26 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:38:41 PM PDT 24
Peak memory 206704 kb
Host smart-2d46ff4c-25d0-4809-9497-f7a6a69c7bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29862
79052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.2986279052
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2625445178
Short name T71
Test name
Test status
Simulation time 190126258 ps
CPU time 0.84 seconds
Started Jul 10 06:38:37 PM PDT 24
Finished Jul 10 06:38:42 PM PDT 24
Peak memory 206372 kb
Host smart-9863bc4e-bf3d-49ec-af8b-b3de46c10622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26254
45178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2625445178
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.4029539615
Short name T2543
Test name
Test status
Simulation time 184658783 ps
CPU time 0.82 seconds
Started Jul 10 06:38:48 PM PDT 24
Finished Jul 10 06:38:53 PM PDT 24
Peak memory 206376 kb
Host smart-15ebb75a-e12c-479e-811b-751411f68737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40295
39615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.4029539615
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.217681504
Short name T52
Test name
Test status
Simulation time 199717082 ps
CPU time 0.89 seconds
Started Jul 10 06:38:59 PM PDT 24
Finished Jul 10 06:39:03 PM PDT 24
Peak memory 206376 kb
Host smart-163aeae1-0f21-4a9b-b16a-6f1ad5dbdad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21768
1504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.217681504
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2567308623
Short name T541
Test name
Test status
Simulation time 32883595 ps
CPU time 0.65 seconds
Started Jul 10 06:41:53 PM PDT 24
Finished Jul 10 06:41:57 PM PDT 24
Peak memory 206368 kb
Host smart-60a94214-89e0-4f0d-8973-155b34611c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25673
08623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2567308623
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2122945353
Short name T167
Test name
Test status
Simulation time 10420258419 ps
CPU time 284.12 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206688 kb
Host smart-1d7f84c6-68a3-4e1d-9add-383e83e32d1c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2122945353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2122945353
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.609061421
Short name T125
Test name
Test status
Simulation time 240426122 ps
CPU time 0.91 seconds
Started Jul 10 06:38:35 PM PDT 24
Finished Jul 10 06:38:41 PM PDT 24
Peak memory 206376 kb
Host smart-753391b9-35be-4f97-9796-339610044dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60906
1421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.609061421
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.210027899
Short name T56
Test name
Test status
Simulation time 429319414 ps
CPU time 1.26 seconds
Started Jul 10 06:38:48 PM PDT 24
Finished Jul 10 06:38:53 PM PDT 24
Peak memory 206396 kb
Host smart-9581a65d-d087-47fb-acd9-592f6d1f69d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21002
7899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.210027899
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2366317495
Short name T129
Test name
Test status
Simulation time 174741868 ps
CPU time 0.82 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206380 kb
Host smart-ed84a72e-421f-4d2d-aecd-78d4642213f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23663
17495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2366317495
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1288867073
Short name T1789
Test name
Test status
Simulation time 200566165 ps
CPU time 0.86 seconds
Started Jul 10 06:41:30 PM PDT 24
Finished Jul 10 06:41:37 PM PDT 24
Peak memory 206364 kb
Host smart-6a618ef8-34b0-4ad3-9899-f76857810fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12888
67073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1288867073
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.898635310
Short name T2556
Test name
Test status
Simulation time 232303760 ps
CPU time 0.85 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206376 kb
Host smart-ee527b04-d263-4fa5-a651-1ee85022ef21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89863
5310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.898635310
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3972312535
Short name T141
Test name
Test status
Simulation time 189993815 ps
CPU time 0.88 seconds
Started Jul 10 06:41:59 PM PDT 24
Finished Jul 10 06:42:03 PM PDT 24
Peak memory 206320 kb
Host smart-bae3c682-97c4-4528-b0b6-ccd5faadfaaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39723
12535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3972312535
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1987997238
Short name T354
Test name
Test status
Simulation time 7444576637 ps
CPU time 71.57 seconds
Started Jul 10 06:42:03 PM PDT 24
Finished Jul 10 06:43:16 PM PDT 24
Peak memory 206692 kb
Host smart-b6ee4c41-dc83-4917-9c96-6daaf4a0ddad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19879
97238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1987997238
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3023191850
Short name T2612
Test name
Test status
Simulation time 203680775 ps
CPU time 0.87 seconds
Started Jul 10 06:42:33 PM PDT 24
Finished Jul 10 06:42:37 PM PDT 24
Peak memory 206388 kb
Host smart-feab92cc-8a2c-44a3-b67d-53b09199df7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30231
91850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3023191850
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3215476685
Short name T144
Test name
Test status
Simulation time 213859252 ps
CPU time 0.89 seconds
Started Jul 10 06:42:56 PM PDT 24
Finished Jul 10 06:43:01 PM PDT 24
Peak memory 206388 kb
Host smart-50980cbf-2807-4fd3-8f83-9859f75ab856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
76685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3215476685
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3082416452
Short name T25
Test name
Test status
Simulation time 219296480 ps
CPU time 0.91 seconds
Started Jul 10 06:43:49 PM PDT 24
Finished Jul 10 06:43:55 PM PDT 24
Peak memory 206384 kb
Host smart-84db1408-76d6-4e73-a6c9-c773e95f9b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30824
16452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3082416452
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3493675699
Short name T131
Test name
Test status
Simulation time 235299050 ps
CPU time 0.86 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:27 PM PDT 24
Peak memory 206384 kb
Host smart-a51b70b9-11b9-466e-8af2-fe2de7a1da05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34936
75699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3493675699
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.908655284
Short name T119
Test name
Test status
Simulation time 208018565 ps
CPU time 0.86 seconds
Started Jul 10 06:46:27 PM PDT 24
Finished Jul 10 06:46:31 PM PDT 24
Peak memory 206308 kb
Host smart-0a0fcec7-16e7-419c-89bb-07b53b921f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90865
5284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.908655284
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2536071781
Short name T147
Test name
Test status
Simulation time 202887460 ps
CPU time 0.86 seconds
Started Jul 10 06:47:16 PM PDT 24
Finished Jul 10 06:47:19 PM PDT 24
Peak memory 206364 kb
Host smart-3451d224-54ff-4eb2-9c2b-e858cb300b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25360
71781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2536071781
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.638287151
Short name T2756
Test name
Test status
Simulation time 301949889 ps
CPU time 3.13 seconds
Started Jul 10 06:37:31 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 206336 kb
Host smart-a8b089d8-5ae8-4514-8c52-845b220e5a3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=638287151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.638287151
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.328525408
Short name T2847
Test name
Test status
Simulation time 834309812 ps
CPU time 4.95 seconds
Started Jul 10 06:37:31 PM PDT 24
Finished Jul 10 06:37:42 PM PDT 24
Peak memory 206240 kb
Host smart-9628b7e8-bc3c-426d-b4ed-488d0a5c6c86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=328525408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.328525408
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1814031989
Short name T2814
Test name
Test status
Simulation time 111827513 ps
CPU time 0.86 seconds
Started Jul 10 06:37:29 PM PDT 24
Finished Jul 10 06:37:37 PM PDT 24
Peak memory 206008 kb
Host smart-f56db6b2-82b6-42ff-9f04-8d201152df2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1814031989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1814031989
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2956276406
Short name T2852
Test name
Test status
Simulation time 107458952 ps
CPU time 2.44 seconds
Started Jul 10 06:37:30 PM PDT 24
Finished Jul 10 06:37:38 PM PDT 24
Peak memory 214544 kb
Host smart-d8e21fa1-1c4c-4b9e-a0a3-2d6f6c136190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956276406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2956276406
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1892479288
Short name T293
Test name
Test status
Simulation time 48717956 ps
CPU time 0.7 seconds
Started Jul 10 06:37:30 PM PDT 24
Finished Jul 10 06:37:37 PM PDT 24
Peak memory 206008 kb
Host smart-214e3eb2-d25c-4992-bb8a-c62f365fcff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1892479288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1892479288
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2704272352
Short name T2841
Test name
Test status
Simulation time 167798872 ps
CPU time 2.29 seconds
Started Jul 10 06:37:28 PM PDT 24
Finished Jul 10 06:37:38 PM PDT 24
Peak memory 214484 kb
Host smart-763e56e6-80b4-4d39-b63b-5eaff3572e97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2704272352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2704272352
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.32144053
Short name T2755
Test name
Test status
Simulation time 90999474 ps
CPU time 2.38 seconds
Started Jul 10 06:37:31 PM PDT 24
Finished Jul 10 06:37:39 PM PDT 24
Peak memory 206256 kb
Host smart-5271b483-aa1a-463b-828d-a1a3e6802f93
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=32144053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.32144053
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1450647308
Short name T2772
Test name
Test status
Simulation time 84827927 ps
CPU time 1.12 seconds
Started Jul 10 06:37:32 PM PDT 24
Finished Jul 10 06:37:38 PM PDT 24
Peak memory 206376 kb
Host smart-41fedcf1-f879-4718-a3dc-b1aae18a9006
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1450647308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1450647308
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1100037115
Short name T2836
Test name
Test status
Simulation time 301615831 ps
CPU time 3.29 seconds
Started Jul 10 06:37:31 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 206724 kb
Host smart-271e15db-c0e8-4643-8888-180ec1e72d10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1100037115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1100037115
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1314022616
Short name T2849
Test name
Test status
Simulation time 717686089 ps
CPU time 4.63 seconds
Started Jul 10 06:37:36 PM PDT 24
Finished Jul 10 06:37:45 PM PDT 24
Peak memory 206256 kb
Host smart-58224336-d53d-48c8-a362-a0aedee844dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1314022616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1314022616
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4193604870
Short name T2855
Test name
Test status
Simulation time 133936835 ps
CPU time 0.97 seconds
Started Jul 10 06:37:29 PM PDT 24
Finished Jul 10 06:37:36 PM PDT 24
Peak memory 206056 kb
Host smart-25f5d2c2-9276-44d5-8582-63a9228e69ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4193604870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4193604870
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2652450855
Short name T196
Test name
Test status
Simulation time 109697413 ps
CPU time 1.4 seconds
Started Jul 10 06:37:37 PM PDT 24
Finished Jul 10 06:37:43 PM PDT 24
Peak memory 214536 kb
Host smart-67b1544a-e79d-49ed-9431-ca98edec51c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652450855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2652450855
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3116619507
Short name T256
Test name
Test status
Simulation time 134457072 ps
CPU time 1.11 seconds
Started Jul 10 06:37:36 PM PDT 24
Finished Jul 10 06:37:42 PM PDT 24
Peak memory 206300 kb
Host smart-9d4b9178-0a40-4c31-9678-bfc68f4ce1cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3116619507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3116619507
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3033982385
Short name T2807
Test name
Test status
Simulation time 46540013 ps
CPU time 0.64 seconds
Started Jul 10 06:37:32 PM PDT 24
Finished Jul 10 06:37:38 PM PDT 24
Peak memory 206028 kb
Host smart-cfc10b07-6f91-402b-9a93-d317de4cf663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3033982385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3033982385
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2688753681
Short name T251
Test name
Test status
Simulation time 114479244 ps
CPU time 1.42 seconds
Started Jul 10 06:37:30 PM PDT 24
Finished Jul 10 06:37:37 PM PDT 24
Peak memory 214460 kb
Host smart-26a57542-a7c2-446d-a1f8-56cd91da13d8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2688753681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2688753681
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3426392732
Short name T2759
Test name
Test status
Simulation time 372140423 ps
CPU time 2.79 seconds
Started Jul 10 06:37:31 PM PDT 24
Finished Jul 10 06:37:39 PM PDT 24
Peak memory 206232 kb
Host smart-22645928-5301-4c16-b81a-bc561b747ecd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3426392732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3426392732
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2955662496
Short name T266
Test name
Test status
Simulation time 68431632 ps
CPU time 1.06 seconds
Started Jul 10 06:37:34 PM PDT 24
Finished Jul 10 06:37:39 PM PDT 24
Peak memory 206324 kb
Host smart-43e3d9ad-d294-4d49-a8e5-2695953b613d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2955662496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2955662496
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1062316396
Short name T2793
Test name
Test status
Simulation time 129549157 ps
CPU time 1.8 seconds
Started Jul 10 06:37:31 PM PDT 24
Finished Jul 10 06:37:38 PM PDT 24
Peak memory 221988 kb
Host smart-a16423aa-0bd3-4452-8c78-d26ec9721055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1062316396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1062316396
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2697656900
Short name T279
Test name
Test status
Simulation time 872234763 ps
CPU time 5.04 seconds
Started Jul 10 06:37:28 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 206328 kb
Host smart-4c72a075-dd83-423a-a7ba-684d3d4887a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2697656900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2697656900
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3978876749
Short name T2771
Test name
Test status
Simulation time 91674369 ps
CPU time 1.82 seconds
Started Jul 10 06:38:07 PM PDT 24
Finished Jul 10 06:38:14 PM PDT 24
Peak memory 214556 kb
Host smart-ed0c6d27-aafe-4ad5-9768-c70f686f687d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978876749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3978876749
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1397070202
Short name T253
Test name
Test status
Simulation time 47899456 ps
CPU time 0.94 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:17 PM PDT 24
Peak memory 205892 kb
Host smart-e2604058-7ed3-428a-917f-0560f61a3bbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1397070202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1397070202
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4242883300
Short name T2769
Test name
Test status
Simulation time 233757397 ps
CPU time 1.62 seconds
Started Jul 10 06:38:05 PM PDT 24
Finished Jul 10 06:38:11 PM PDT 24
Peak memory 206296 kb
Host smart-e76e3dac-1ff0-418d-81b5-142dd8e9b3d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4242883300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.4242883300
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2814208406
Short name T228
Test name
Test status
Simulation time 95299743 ps
CPU time 2.48 seconds
Started Jul 10 06:38:06 PM PDT 24
Finished Jul 10 06:38:13 PM PDT 24
Peak memory 222632 kb
Host smart-4b116d2b-2608-4ded-b736-7337b40d8857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2814208406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2814208406
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.654862631
Short name T300
Test name
Test status
Simulation time 812682373 ps
CPU time 4.79 seconds
Started Jul 10 06:38:05 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 206396 kb
Host smart-bc6f398f-dad8-407a-aaaf-78830b21a48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=654862631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.654862631
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1383183173
Short name T2831
Test name
Test status
Simulation time 69182238 ps
CPU time 1.75 seconds
Started Jul 10 06:38:06 PM PDT 24
Finished Jul 10 06:38:13 PM PDT 24
Peak memory 214548 kb
Host smart-7fd042fa-bcc7-4d1c-bac4-c69d7be2ab81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383183173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1383183173
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.609907862
Short name T221
Test name
Test status
Simulation time 142430017 ps
CPU time 0.95 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:17 PM PDT 24
Peak memory 205488 kb
Host smart-54b74ea7-871d-4275-a72f-a64da82b1018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=609907862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.609907862
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2430278743
Short name T2845
Test name
Test status
Simulation time 43898036 ps
CPU time 0.71 seconds
Started Jul 10 06:38:06 PM PDT 24
Finished Jul 10 06:38:12 PM PDT 24
Peak memory 205888 kb
Host smart-46d4e292-7976-47a1-9547-8743aaac88e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2430278743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2430278743
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3019579383
Short name T2837
Test name
Test status
Simulation time 188970923 ps
CPU time 1.66 seconds
Started Jul 10 06:38:04 PM PDT 24
Finished Jul 10 06:38:11 PM PDT 24
Peak memory 206284 kb
Host smart-fa2a6db2-2db6-43ae-86b8-812bb711f09e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3019579383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3019579383
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.571143595
Short name T2823
Test name
Test status
Simulation time 231684163 ps
CPU time 1.8 seconds
Started Jul 10 06:38:12 PM PDT 24
Finished Jul 10 06:38:16 PM PDT 24
Peak memory 218820 kb
Host smart-72caabec-8270-4fb9-a685-7ab3f84a9811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571143595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.571143595
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2507589271
Short name T2832
Test name
Test status
Simulation time 45903130 ps
CPU time 0.85 seconds
Started Jul 10 06:38:14 PM PDT 24
Finished Jul 10 06:38:19 PM PDT 24
Peak memory 206088 kb
Host smart-6787465c-9144-4abd-b877-312374237e10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2507589271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2507589271
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.376026336
Short name T2775
Test name
Test status
Simulation time 54218091 ps
CPU time 0.7 seconds
Started Jul 10 06:38:14 PM PDT 24
Finished Jul 10 06:38:19 PM PDT 24
Peak memory 206000 kb
Host smart-b3486dd6-49cb-4ec0-8c2c-c73ec254eb63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=376026336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.376026336
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1997551173
Short name T2782
Test name
Test status
Simulation time 266066461 ps
CPU time 1.6 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 206360 kb
Host smart-bcf5aeda-886a-46f2-bff7-117d70634a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997551173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1997551173
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2669809660
Short name T233
Test name
Test status
Simulation time 108307796 ps
CPU time 1.62 seconds
Started Jul 10 06:38:06 PM PDT 24
Finished Jul 10 06:38:13 PM PDT 24
Peak memory 221976 kb
Host smart-f548ddd6-9bec-4d5b-b30f-7af9e346c19a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2669809660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2669809660
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.140623366
Short name T285
Test name
Test status
Simulation time 1301639994 ps
CPU time 5.8 seconds
Started Jul 10 06:38:04 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 206296 kb
Host smart-142d4569-3662-45f3-bf8d-47696bb0960a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=140623366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.140623366
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1633347080
Short name T280
Test name
Test status
Simulation time 120728151 ps
CPU time 1.26 seconds
Started Jul 10 06:38:11 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 214548 kb
Host smart-cf6789e3-ce24-4f89-ac58-f09d185ced60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633347080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1633347080
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2763287862
Short name T2825
Test name
Test status
Simulation time 59585002 ps
CPU time 0.93 seconds
Started Jul 10 06:38:14 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 206224 kb
Host smart-30e62076-6bdc-40a8-9f70-20d4cddbf4a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2763287862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2763287862
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2367535705
Short name T288
Test name
Test status
Simulation time 34207358 ps
CPU time 0.65 seconds
Started Jul 10 06:38:11 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 206000 kb
Host smart-e8e0d17c-660b-4e7b-8b05-547273830c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2367535705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2367535705
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2540845977
Short name T267
Test name
Test status
Simulation time 106175355 ps
CPU time 1.2 seconds
Started Jul 10 06:38:12 PM PDT 24
Finished Jul 10 06:38:17 PM PDT 24
Peak memory 206540 kb
Host smart-3513d00b-9846-475f-afb8-edc77b3b9c83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2540845977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2540845977
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2886152502
Short name T2809
Test name
Test status
Simulation time 206761557 ps
CPU time 2.25 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:19 PM PDT 24
Peak memory 214624 kb
Host smart-fb6ed47b-6ac3-42b6-8c21-9e080fd832ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2886152502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2886152502
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2304050924
Short name T194
Test name
Test status
Simulation time 191860657 ps
CPU time 1.29 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:17 PM PDT 24
Peak memory 216156 kb
Host smart-3d447d27-cd29-470e-853f-fd92579e959d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304050924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2304050924
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2325512948
Short name T255
Test name
Test status
Simulation time 81824142 ps
CPU time 1.03 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:17 PM PDT 24
Peak memory 206248 kb
Host smart-85473794-c961-4b3b-a6d0-28e99b37b635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2325512948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2325512948
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.949721390
Short name T296
Test name
Test status
Simulation time 41628385 ps
CPU time 0.69 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:23 PM PDT 24
Peak memory 206020 kb
Host smart-d4bd4d1b-152f-4696-8179-33b7c83267e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=949721390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.949721390
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3067294909
Short name T2785
Test name
Test status
Simulation time 87905965 ps
CPU time 1.14 seconds
Started Jul 10 06:38:12 PM PDT 24
Finished Jul 10 06:38:17 PM PDT 24
Peak memory 206332 kb
Host smart-7b5e29c8-d9b9-4804-9ebc-349ddcb18153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3067294909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3067294909
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2811598326
Short name T278
Test name
Test status
Simulation time 238011407 ps
CPU time 1.86 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 214612 kb
Host smart-0c68a47d-f66c-4ee9-ada6-abbfbe0c5962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811598326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2811598326
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.724070624
Short name T2821
Test name
Test status
Simulation time 79911415 ps
CPU time 0.9 seconds
Started Jul 10 06:38:11 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 206068 kb
Host smart-926c160e-f305-44a4-8d24-082374f18982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=724070624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.724070624
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1312079875
Short name T2818
Test name
Test status
Simulation time 61484071 ps
CPU time 0.74 seconds
Started Jul 10 06:38:11 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 206004 kb
Host smart-77c40740-7ec2-4c32-97ee-bedf3ab31ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1312079875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1312079875
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1614938048
Short name T277
Test name
Test status
Simulation time 455217950 ps
CPU time 2.18 seconds
Started Jul 10 06:38:13 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 206380 kb
Host smart-978a3ef2-76e4-4e9a-bb08-a76759770705
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1614938048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1614938048
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.775040020
Short name T2784
Test name
Test status
Simulation time 71649171 ps
CPU time 2.09 seconds
Started Jul 10 06:38:14 PM PDT 24
Finished Jul 10 06:38:19 PM PDT 24
Peak memory 214616 kb
Host smart-1b6a1b25-d56d-469a-a059-04dd758f461c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=775040020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.775040020
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.859621074
Short name T306
Test name
Test status
Simulation time 1180139061 ps
CPU time 5.28 seconds
Started Jul 10 06:38:14 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 206332 kb
Host smart-d9ee7303-5444-438c-b868-a22206883490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=859621074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.859621074
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1181447942
Short name T2820
Test name
Test status
Simulation time 126570572 ps
CPU time 2.62 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 214648 kb
Host smart-07755eb7-065d-4512-90bb-33a368a54c7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181447942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1181447942
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3210626089
Short name T254
Test name
Test status
Simulation time 47227996 ps
CPU time 0.96 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 206260 kb
Host smart-3ab50c43-0865-48f6-b1cf-b548430d9ae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3210626089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3210626089
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3424695133
Short name T2764
Test name
Test status
Simulation time 116781332 ps
CPU time 1.08 seconds
Started Jul 10 06:38:22 PM PDT 24
Finished Jul 10 06:38:29 PM PDT 24
Peak memory 206384 kb
Host smart-1b1fcb2e-5f5d-4014-9bd7-75a4c6faff50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3424695133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3424695133
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2503127168
Short name T2777
Test name
Test status
Simulation time 92729336 ps
CPU time 1.86 seconds
Started Jul 10 06:38:14 PM PDT 24
Finished Jul 10 06:38:20 PM PDT 24
Peak memory 222364 kb
Host smart-56c77b94-666e-4060-ac8c-4bf23dfcc697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2503127168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2503127168
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3877380068
Short name T2803
Test name
Test status
Simulation time 108309909 ps
CPU time 1.26 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 216352 kb
Host smart-23b38a0d-29d8-464a-b32f-8d3a0afd2521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877380068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3877380068
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.825916971
Short name T259
Test name
Test status
Simulation time 72902465 ps
CPU time 0.95 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 206252 kb
Host smart-7d23fa4f-827c-48cc-a3c8-27e37a4c3537
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=825916971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.825916971
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1284716620
Short name T2817
Test name
Test status
Simulation time 83810939 ps
CPU time 0.72 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:23 PM PDT 24
Peak memory 205988 kb
Host smart-4086b654-46ae-47f2-a336-e9f4534dfc0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284716620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1284716620
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2208575691
Short name T2830
Test name
Test status
Simulation time 52959594 ps
CPU time 1.05 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 206376 kb
Host smart-f3c8a17c-74ce-46a1-b19c-c64a4cf5b0a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2208575691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2208575691
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.469431372
Short name T2815
Test name
Test status
Simulation time 134774394 ps
CPU time 1.9 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 221988 kb
Host smart-509a1f0f-8909-451c-8bc5-bd9bf6ad259e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=469431372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.469431372
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4121192383
Short name T302
Test name
Test status
Simulation time 371200993 ps
CPU time 2.42 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:26 PM PDT 24
Peak memory 206340 kb
Host smart-17b9ccff-4ce8-4492-b4f8-78282a95742e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4121192383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.4121192383
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2013032254
Short name T231
Test name
Test status
Simulation time 129232147 ps
CPU time 2.93 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:26 PM PDT 24
Peak memory 214544 kb
Host smart-60d1b397-c166-4b12-b149-a0c6562d7b22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013032254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2013032254
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3852466088
Short name T258
Test name
Test status
Simulation time 76708787 ps
CPU time 0.84 seconds
Started Jul 10 06:38:17 PM PDT 24
Finished Jul 10 06:38:22 PM PDT 24
Peak memory 206036 kb
Host smart-d3f9440f-de26-4748-a857-8494917a4fbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3852466088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3852466088
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.799708911
Short name T206
Test name
Test status
Simulation time 60361890 ps
CPU time 0.67 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:23 PM PDT 24
Peak memory 206028 kb
Host smart-fbc89575-fc74-4b03-84f9-e2cee2032041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=799708911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.799708911
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1948138101
Short name T197
Test name
Test status
Simulation time 130019953 ps
CPU time 1.39 seconds
Started Jul 10 06:38:21 PM PDT 24
Finished Jul 10 06:38:28 PM PDT 24
Peak memory 206312 kb
Host smart-ee0d7bb4-f884-4732-94de-f076f8867fbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1948138101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1948138101
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1295059614
Short name T2789
Test name
Test status
Simulation time 109165210 ps
CPU time 2.08 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:38:34 PM PDT 24
Peak memory 222048 kb
Host smart-1d238312-6b1e-40d5-b767-1725c3a23cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1295059614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1295059614
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.674428961
Short name T301
Test name
Test status
Simulation time 315079271 ps
CPU time 2.51 seconds
Started Jul 10 06:38:20 PM PDT 24
Finished Jul 10 06:38:27 PM PDT 24
Peak memory 206340 kb
Host smart-4b9f0010-2b9e-4c57-8a72-9e4681e0d9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=674428961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.674428961
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.309970815
Short name T2770
Test name
Test status
Simulation time 89484599 ps
CPU time 2.01 seconds
Started Jul 10 06:38:17 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 214528 kb
Host smart-4475525e-acca-4297-9f74-e5e87d4fb020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309970815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.309970815
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.267867547
Short name T2808
Test name
Test status
Simulation time 45911070 ps
CPU time 0.85 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 206056 kb
Host smart-b729150c-e246-497e-8fa0-a1a127d95688
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=267867547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.267867547
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1955900837
Short name T2819
Test name
Test status
Simulation time 43934688 ps
CPU time 0.67 seconds
Started Jul 10 06:38:21 PM PDT 24
Finished Jul 10 06:38:26 PM PDT 24
Peak memory 206004 kb
Host smart-25999a30-7cfb-4bf4-882c-aea7ff64690e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1955900837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1955900837
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2566603693
Short name T2843
Test name
Test status
Simulation time 458810067 ps
CPU time 1.78 seconds
Started Jul 10 06:38:21 PM PDT 24
Finished Jul 10 06:38:28 PM PDT 24
Peak memory 206320 kb
Host smart-d16afa73-36bb-443c-97c4-56484cdae76e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2566603693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2566603693
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.312044776
Short name T235
Test name
Test status
Simulation time 53470022 ps
CPU time 1.43 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 206364 kb
Host smart-68b6942a-4f00-42d0-93f0-f8abe039cae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=312044776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.312044776
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1933333954
Short name T2760
Test name
Test status
Simulation time 123096722 ps
CPU time 3.02 seconds
Started Jul 10 06:37:38 PM PDT 24
Finished Jul 10 06:37:46 PM PDT 24
Peak memory 206328 kb
Host smart-e5c404b0-1887-428a-b0dc-76d1179daf40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1933333954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1933333954
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2856317964
Short name T252
Test name
Test status
Simulation time 985834515 ps
CPU time 5.49 seconds
Started Jul 10 06:37:35 PM PDT 24
Finished Jul 10 06:37:45 PM PDT 24
Peak memory 206248 kb
Host smart-bacf66df-8020-447f-ae76-0c8124af5093
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2856317964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2856317964
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2958255450
Short name T2766
Test name
Test status
Simulation time 105827274 ps
CPU time 0.96 seconds
Started Jul 10 06:37:36 PM PDT 24
Finished Jul 10 06:37:42 PM PDT 24
Peak memory 206056 kb
Host smart-056af781-f771-41cf-9885-26c0ee673663
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2958255450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2958255450
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.394079409
Short name T2792
Test name
Test status
Simulation time 90409789 ps
CPU time 1.24 seconds
Started Jul 10 06:37:35 PM PDT 24
Finished Jul 10 06:37:41 PM PDT 24
Peak memory 214600 kb
Host smart-809c3317-4f4f-4aec-a936-51ce2565380a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394079409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.394079409
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2300108687
Short name T2796
Test name
Test status
Simulation time 34818289 ps
CPU time 0.82 seconds
Started Jul 10 06:37:36 PM PDT 24
Finished Jul 10 06:37:41 PM PDT 24
Peak memory 206040 kb
Host smart-b84a83e9-38e7-4210-bf2e-402fbd968ec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2300108687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2300108687
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3566802760
Short name T2822
Test name
Test status
Simulation time 99141726 ps
CPU time 0.77 seconds
Started Jul 10 06:37:35 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 205996 kb
Host smart-8908444c-896c-4f20-a7e3-f623f861c989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3566802760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3566802760
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1953287850
Short name T262
Test name
Test status
Simulation time 138062633 ps
CPU time 1.5 seconds
Started Jul 10 06:37:35 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 214456 kb
Host smart-e30945dd-45c8-407a-a08a-a8fb55536ea4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1953287850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1953287850
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3478231809
Short name T2799
Test name
Test status
Simulation time 696564235 ps
CPU time 4.61 seconds
Started Jul 10 06:37:34 PM PDT 24
Finished Jul 10 06:37:43 PM PDT 24
Peak memory 206216 kb
Host smart-3b5c9018-377a-44be-af4a-17e8019b2b8c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3478231809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3478231809
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.403968418
Short name T2779
Test name
Test status
Simulation time 170453153 ps
CPU time 1.66 seconds
Started Jul 10 06:37:36 PM PDT 24
Finished Jul 10 06:37:42 PM PDT 24
Peak memory 206388 kb
Host smart-8383cdd7-d85f-4704-adef-ca0d36d44538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=403968418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.403968418
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1891032602
Short name T281
Test name
Test status
Simulation time 320986077 ps
CPU time 3.5 seconds
Started Jul 10 06:37:37 PM PDT 24
Finished Jul 10 06:37:45 PM PDT 24
Peak memory 214632 kb
Host smart-2aafb130-cb7b-46e8-886b-8255651dd361
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1891032602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1891032602
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3563526283
Short name T2767
Test name
Test status
Simulation time 761758095 ps
CPU time 2.86 seconds
Started Jul 10 06:37:36 PM PDT 24
Finished Jul 10 06:37:43 PM PDT 24
Peak memory 206360 kb
Host smart-10f156a0-e479-472b-ab7e-3be368b8eb42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3563526283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3563526283
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3777278899
Short name T2774
Test name
Test status
Simulation time 45942200 ps
CPU time 0.7 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:23 PM PDT 24
Peak memory 206188 kb
Host smart-63b8eff7-4059-4d95-932a-4bebf87d4f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3777278899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3777278899
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4001903200
Short name T2801
Test name
Test status
Simulation time 43111552 ps
CPU time 0.65 seconds
Started Jul 10 06:38:23 PM PDT 24
Finished Jul 10 06:38:30 PM PDT 24
Peak memory 206048 kb
Host smart-6c4e5902-84a0-4dea-9442-563b39c2be54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4001903200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4001903200
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2220456135
Short name T2765
Test name
Test status
Simulation time 35782802 ps
CPU time 0.66 seconds
Started Jul 10 06:38:20 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 205988 kb
Host smart-d6c4a18c-d71a-4a88-b2e5-3a3ee7b2d79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2220456135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2220456135
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3702285250
Short name T2854
Test name
Test status
Simulation time 60448763 ps
CPU time 0.7 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 206012 kb
Host smart-ddf322c0-9053-471c-9beb-5d81abd7700f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3702285250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3702285250
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3043277127
Short name T2840
Test name
Test status
Simulation time 92661393 ps
CPU time 0.75 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:38:32 PM PDT 24
Peak memory 205644 kb
Host smart-3f681071-19c6-4ff4-a430-4efb60c02a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3043277127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3043277127
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1899481463
Short name T2812
Test name
Test status
Simulation time 54630541 ps
CPU time 0.68 seconds
Started Jul 10 06:38:22 PM PDT 24
Finished Jul 10 06:38:28 PM PDT 24
Peak memory 206004 kb
Host smart-d497e556-cc74-4ef0-969f-e30742e44393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1899481463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1899481463
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1442017
Short name T2778
Test name
Test status
Simulation time 53483378 ps
CPU time 0.7 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 205956 kb
Host smart-00530dcd-d46d-4fcb-9560-22f80d71fd7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1442017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1442017
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3165625205
Short name T295
Test name
Test status
Simulation time 67436591 ps
CPU time 0.73 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:23 PM PDT 24
Peak memory 206048 kb
Host smart-5f526c2d-a4e7-41da-a75c-3220816136aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3165625205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3165625205
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1861039960
Short name T2851
Test name
Test status
Simulation time 78649354 ps
CPU time 0.72 seconds
Started Jul 10 06:38:22 PM PDT 24
Finished Jul 10 06:38:28 PM PDT 24
Peak memory 206028 kb
Host smart-09382395-c49f-4144-8042-2ebaefe44bfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1861039960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1861039960
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2660643223
Short name T2810
Test name
Test status
Simulation time 373353797 ps
CPU time 3.49 seconds
Started Jul 10 06:37:41 PM PDT 24
Finished Jul 10 06:37:48 PM PDT 24
Peak memory 206268 kb
Host smart-a43aa726-561a-4e84-8169-b97367bc7c08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2660643223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2660643223
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.526688174
Short name T2787
Test name
Test status
Simulation time 1276719057 ps
CPU time 9.52 seconds
Started Jul 10 06:37:41 PM PDT 24
Finished Jul 10 06:37:54 PM PDT 24
Peak memory 206216 kb
Host smart-8c070400-de54-47bd-9437-63aa9c4bb07b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=526688174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.526688174
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1616646591
Short name T2757
Test name
Test status
Simulation time 64839978 ps
CPU time 0.82 seconds
Started Jul 10 06:37:43 PM PDT 24
Finished Jul 10 06:37:46 PM PDT 24
Peak memory 206040 kb
Host smart-819673c0-121b-4888-98c1-195cea582246
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1616646591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1616646591
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3432533713
Short name T232
Test name
Test status
Simulation time 193383549 ps
CPU time 1.5 seconds
Started Jul 10 06:37:43 PM PDT 24
Finished Jul 10 06:37:47 PM PDT 24
Peak memory 214736 kb
Host smart-81a403a5-e9da-48ae-9f51-1562418c5052
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432533713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3432533713
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2005396039
Short name T2826
Test name
Test status
Simulation time 52142574 ps
CPU time 0.81 seconds
Started Jul 10 06:37:43 PM PDT 24
Finished Jul 10 06:37:46 PM PDT 24
Peak memory 206056 kb
Host smart-983625d3-6db0-4f15-ad65-fb93c2967c39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2005396039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2005396039
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.331923345
Short name T203
Test name
Test status
Simulation time 28616729 ps
CPU time 0.67 seconds
Started Jul 10 06:37:37 PM PDT 24
Finished Jul 10 06:37:42 PM PDT 24
Peak memory 206216 kb
Host smart-5ca66401-df1a-47f0-80e8-6f104524321b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331923345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.331923345
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3267407211
Short name T250
Test name
Test status
Simulation time 131053163 ps
CPU time 1.42 seconds
Started Jul 10 06:37:35 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 214508 kb
Host smart-e3f56dc4-01d3-402b-9141-28649c94ef28
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3267407211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3267407211
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.655433303
Short name T2762
Test name
Test status
Simulation time 274404603 ps
CPU time 2.58 seconds
Started Jul 10 06:37:36 PM PDT 24
Finished Jul 10 06:37:43 PM PDT 24
Peak memory 206212 kb
Host smart-1cff9ca0-818f-45e0-b3b1-6a9caa0cc1cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=655433303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.655433303
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.729146989
Short name T2846
Test name
Test status
Simulation time 157942736 ps
CPU time 1.29 seconds
Started Jul 10 06:37:41 PM PDT 24
Finished Jul 10 06:37:46 PM PDT 24
Peak memory 206384 kb
Host smart-eee2d309-617a-4674-bc44-11939f5a591a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=729146989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.729146989
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2361644619
Short name T229
Test name
Test status
Simulation time 108569477 ps
CPU time 2.68 seconds
Started Jul 10 06:37:35 PM PDT 24
Finished Jul 10 06:37:41 PM PDT 24
Peak memory 214580 kb
Host smart-f137133c-36d2-4871-8138-8a13d26f10f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2361644619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2361644619
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.799355219
Short name T2780
Test name
Test status
Simulation time 695247596 ps
CPU time 4.28 seconds
Started Jul 10 06:37:35 PM PDT 24
Finished Jul 10 06:37:43 PM PDT 24
Peak memory 206324 kb
Host smart-1cf870ed-092b-4b2f-b913-20270f49d908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=799355219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.799355219
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.928644700
Short name T2805
Test name
Test status
Simulation time 40744626 ps
CPU time 0.67 seconds
Started Jul 10 06:38:20 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 205984 kb
Host smart-d6a54406-762d-40ae-9d9f-e55c6cd2a76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=928644700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.928644700
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2044795517
Short name T2804
Test name
Test status
Simulation time 45949317 ps
CPU time 0.67 seconds
Started Jul 10 06:38:24 PM PDT 24
Finished Jul 10 06:38:31 PM PDT 24
Peak memory 206016 kb
Host smart-48d8a4c2-e659-4de8-ba3c-ac3037caeb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2044795517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2044795517
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1323239801
Short name T2776
Test name
Test status
Simulation time 55910879 ps
CPU time 0.67 seconds
Started Jul 10 06:38:20 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 206012 kb
Host smart-21cd996b-2104-4211-80fc-4c2f6994614c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1323239801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1323239801
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.876805238
Short name T2800
Test name
Test status
Simulation time 76338135 ps
CPU time 0.71 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:23 PM PDT 24
Peak memory 206012 kb
Host smart-af490b57-a79f-4303-a88a-3dfbef23f649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=876805238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.876805238
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.987915585
Short name T284
Test name
Test status
Simulation time 58543925 ps
CPU time 0.67 seconds
Started Jul 10 06:38:18 PM PDT 24
Finished Jul 10 06:38:23 PM PDT 24
Peak memory 206012 kb
Host smart-769417d2-cf4d-4b6c-8556-0b9bbe4d30aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=987915585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.987915585
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4073499775
Short name T201
Test name
Test status
Simulation time 45413049 ps
CPU time 0.66 seconds
Started Jul 10 06:38:17 PM PDT 24
Finished Jul 10 06:38:23 PM PDT 24
Peak memory 205980 kb
Host smart-fe8f6013-9ee1-4a0f-8344-e447e10e68ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4073499775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4073499775
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.617518635
Short name T2794
Test name
Test status
Simulation time 28256741 ps
CPU time 0.79 seconds
Started Jul 10 06:38:20 PM PDT 24
Finished Jul 10 06:38:25 PM PDT 24
Peak memory 206000 kb
Host smart-941fc24f-930d-450b-8664-d8a8cc16e4e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=617518635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.617518635
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.311977411
Short name T2853
Test name
Test status
Simulation time 297298649 ps
CPU time 3.58 seconds
Started Jul 10 06:37:50 PM PDT 24
Finished Jul 10 06:37:57 PM PDT 24
Peak memory 206216 kb
Host smart-cd7b9846-bec3-4773-86b2-aa97d8614fc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=311977411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.311977411
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1731176618
Short name T2834
Test name
Test status
Simulation time 701616972 ps
CPU time 4.46 seconds
Started Jul 10 06:37:52 PM PDT 24
Finished Jul 10 06:38:00 PM PDT 24
Peak memory 206256 kb
Host smart-f5de2f7f-3299-443e-adaa-781bb85575e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1731176618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1731176618
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2912195848
Short name T2844
Test name
Test status
Simulation time 88101188 ps
CPU time 0.92 seconds
Started Jul 10 06:37:48 PM PDT 24
Finished Jul 10 06:37:53 PM PDT 24
Peak memory 205976 kb
Host smart-3ffe5288-2795-459c-b511-d10773cf3c11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2912195848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2912195848
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2700881436
Short name T2850
Test name
Test status
Simulation time 75059576 ps
CPU time 1.2 seconds
Started Jul 10 06:37:50 PM PDT 24
Finished Jul 10 06:37:55 PM PDT 24
Peak memory 214552 kb
Host smart-7707425d-a559-48c1-a5ec-47d7edc3e61a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700881436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2700881436
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3737010617
Short name T261
Test name
Test status
Simulation time 63547574 ps
CPU time 0.88 seconds
Started Jul 10 06:37:53 PM PDT 24
Finished Jul 10 06:37:56 PM PDT 24
Peak memory 206236 kb
Host smart-c4735ce2-a5a9-4b89-be27-d51e196facb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3737010617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3737010617
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3932336675
Short name T292
Test name
Test status
Simulation time 56794945 ps
CPU time 0.66 seconds
Started Jul 10 06:37:42 PM PDT 24
Finished Jul 10 06:37:46 PM PDT 24
Peak memory 206000 kb
Host smart-dfbbd95b-a13d-4d5c-b5da-2d3da423dc2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3932336675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3932336675
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3855491125
Short name T260
Test name
Test status
Simulation time 159096323 ps
CPU time 2.29 seconds
Started Jul 10 06:37:41 PM PDT 24
Finished Jul 10 06:37:47 PM PDT 24
Peak memory 214452 kb
Host smart-d0335d93-b61c-4aae-8a2f-4f771d8e9fa7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3855491125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3855491125
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2768733292
Short name T2758
Test name
Test status
Simulation time 162028875 ps
CPU time 4.19 seconds
Started Jul 10 06:37:41 PM PDT 24
Finished Jul 10 06:37:48 PM PDT 24
Peak memory 206208 kb
Host smart-9a4b6a3b-bffe-4ea8-acb0-ca87be214528
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2768733292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2768733292
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4073578898
Short name T2848
Test name
Test status
Simulation time 133268102 ps
CPU time 1.22 seconds
Started Jul 10 06:37:51 PM PDT 24
Finished Jul 10 06:37:56 PM PDT 24
Peak memory 206308 kb
Host smart-09562ca0-43e2-41ec-81c2-7c83815d754d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4073578898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.4073578898
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3345228406
Short name T195
Test name
Test status
Simulation time 134303844 ps
CPU time 1.73 seconds
Started Jul 10 06:37:42 PM PDT 24
Finished Jul 10 06:37:47 PM PDT 24
Peak memory 214568 kb
Host smart-8859dc6c-c92c-44b0-9f09-bd3aa584fe78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3345228406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3345228406
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3221994404
Short name T2842
Test name
Test status
Simulation time 622970697 ps
CPU time 2.69 seconds
Started Jul 10 06:37:42 PM PDT 24
Finished Jul 10 06:37:48 PM PDT 24
Peak memory 206360 kb
Host smart-65ca422f-8fc0-4aec-b076-ede5bb1f75a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3221994404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3221994404
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3590593249
Short name T205
Test name
Test status
Simulation time 100525457 ps
CPU time 0.72 seconds
Started Jul 10 06:38:19 PM PDT 24
Finished Jul 10 06:38:24 PM PDT 24
Peak memory 206016 kb
Host smart-1e41e589-9599-4fa6-9db6-04fe5db93fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3590593249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3590593249
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3416106942
Short name T2828
Test name
Test status
Simulation time 64119917 ps
CPU time 0.71 seconds
Started Jul 10 06:38:21 PM PDT 24
Finished Jul 10 06:38:26 PM PDT 24
Peak memory 206004 kb
Host smart-64ec0ef9-9f53-48aa-b219-0e2b517944ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3416106942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3416106942
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.835780221
Short name T2781
Test name
Test status
Simulation time 89403301 ps
CPU time 0.77 seconds
Started Jul 10 06:38:23 PM PDT 24
Finished Jul 10 06:38:29 PM PDT 24
Peak memory 206000 kb
Host smart-d8c38336-bc95-4b1e-a6bb-d96c38359377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=835780221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.835780221
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.970453671
Short name T287
Test name
Test status
Simulation time 43263904 ps
CPU time 0.68 seconds
Started Jul 10 06:38:26 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206012 kb
Host smart-5a70aaf1-063a-4634-9581-50a340dab1f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=970453671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.970453671
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1992371840
Short name T2795
Test name
Test status
Simulation time 38521347 ps
CPU time 0.68 seconds
Started Jul 10 06:38:28 PM PDT 24
Finished Jul 10 06:38:35 PM PDT 24
Peak memory 206020 kb
Host smart-6b40a59f-31c4-4c9a-858d-1e52e4e226b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1992371840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1992371840
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3054175831
Short name T204
Test name
Test status
Simulation time 53028196 ps
CPU time 0.68 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:38:32 PM PDT 24
Peak memory 205996 kb
Host smart-b549a960-b88a-46f9-a662-59935acb76e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3054175831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3054175831
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1081706021
Short name T2790
Test name
Test status
Simulation time 38481945 ps
CPU time 0.68 seconds
Started Jul 10 06:38:26 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206016 kb
Host smart-fbf8aac3-5df7-498d-93cf-413812cc0f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1081706021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1081706021
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3477986819
Short name T2791
Test name
Test status
Simulation time 63312595 ps
CPU time 0.72 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:38:31 PM PDT 24
Peak memory 206000 kb
Host smart-a852f52d-44bc-4cad-9552-ee6c4cbb520b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3477986819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3477986819
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.741923495
Short name T2806
Test name
Test status
Simulation time 38431693 ps
CPU time 0.7 seconds
Started Jul 10 06:38:27 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206000 kb
Host smart-d8e0e10c-c98e-48f8-ad1b-1c2d96aa747c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=741923495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.741923495
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1098949801
Short name T282
Test name
Test status
Simulation time 51127914 ps
CPU time 0.7 seconds
Started Jul 10 06:38:26 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206016 kb
Host smart-245865da-6226-46a7-8183-0e01f925ee38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1098949801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1098949801
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.320209161
Short name T230
Test name
Test status
Simulation time 112354136 ps
CPU time 1.36 seconds
Started Jul 10 06:37:50 PM PDT 24
Finished Jul 10 06:37:55 PM PDT 24
Peak memory 214548 kb
Host smart-712b50c2-11bb-4679-93d5-2935b87cc9f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320209161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.320209161
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.160481414
Short name T257
Test name
Test status
Simulation time 99478959 ps
CPU time 1.05 seconds
Started Jul 10 06:37:51 PM PDT 24
Finished Jul 10 06:37:55 PM PDT 24
Peak memory 206188 kb
Host smart-5daf1a3f-fa9a-40d2-bae9-c422e194220c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=160481414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.160481414
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.359936982
Short name T2783
Test name
Test status
Simulation time 41357707 ps
CPU time 0.66 seconds
Started Jul 10 06:37:50 PM PDT 24
Finished Jul 10 06:37:54 PM PDT 24
Peak memory 206012 kb
Host smart-79b9e8c8-0adb-4ab2-92a1-2e6ef6ed4043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=359936982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.359936982
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3715404950
Short name T2816
Test name
Test status
Simulation time 104866757 ps
CPU time 1.2 seconds
Started Jul 10 06:37:50 PM PDT 24
Finished Jul 10 06:37:55 PM PDT 24
Peak memory 206312 kb
Host smart-5b47ab77-7919-4dd5-aec7-62f27a496340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3715404950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3715404950
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.334780343
Short name T234
Test name
Test status
Simulation time 225017755 ps
CPU time 2.37 seconds
Started Jul 10 06:37:49 PM PDT 24
Finished Jul 10 06:37:56 PM PDT 24
Peak memory 206392 kb
Host smart-ca229fd2-d46b-4871-a3d5-8ab3474e4d17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=334780343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.334780343
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3280309053
Short name T299
Test name
Test status
Simulation time 721201296 ps
CPU time 4.73 seconds
Started Jul 10 06:37:49 PM PDT 24
Finished Jul 10 06:37:58 PM PDT 24
Peak memory 206328 kb
Host smart-a0023b14-cb2f-4244-8a0a-233e3817dcfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3280309053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3280309053
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.305298346
Short name T241
Test name
Test status
Simulation time 98190905 ps
CPU time 1.73 seconds
Started Jul 10 06:37:58 PM PDT 24
Finished Jul 10 06:38:03 PM PDT 24
Peak memory 214524 kb
Host smart-f0376fc5-289a-4835-b3b1-0f6f27a778e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305298346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.305298346
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4208966267
Short name T2811
Test name
Test status
Simulation time 90078005 ps
CPU time 0.86 seconds
Started Jul 10 06:38:02 PM PDT 24
Finished Jul 10 06:38:08 PM PDT 24
Peak memory 206060 kb
Host smart-7d998b10-550c-4204-a0a4-b12642436329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4208966267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4208966267
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4092817959
Short name T2813
Test name
Test status
Simulation time 38069015 ps
CPU time 0.71 seconds
Started Jul 10 06:37:59 PM PDT 24
Finished Jul 10 06:38:04 PM PDT 24
Peak memory 206008 kb
Host smart-3f514b78-b468-462d-9f28-a0f255b9c61f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4092817959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.4092817959
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3689722588
Short name T2802
Test name
Test status
Simulation time 148426075 ps
CPU time 1.32 seconds
Started Jul 10 06:38:03 PM PDT 24
Finished Jul 10 06:38:10 PM PDT 24
Peak memory 206312 kb
Host smart-d7dfed47-c940-4f4b-9999-5b76d85069e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3689722588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3689722588
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.792138306
Short name T2829
Test name
Test status
Simulation time 142850453 ps
CPU time 2.96 seconds
Started Jul 10 06:37:51 PM PDT 24
Finished Jul 10 06:37:57 PM PDT 24
Peak memory 206492 kb
Host smart-9902885b-bbac-489c-90c2-0d38dadca87d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=792138306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.792138306
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1032936243
Short name T225
Test name
Test status
Simulation time 394563063 ps
CPU time 2.58 seconds
Started Jul 10 06:37:51 PM PDT 24
Finished Jul 10 06:37:57 PM PDT 24
Peak memory 206324 kb
Host smart-ff110f0e-27d1-4a2f-9c59-06e546e4a2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1032936243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1032936243
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2871646184
Short name T237
Test name
Test status
Simulation time 173894134 ps
CPU time 1.41 seconds
Started Jul 10 06:38:03 PM PDT 24
Finished Jul 10 06:38:10 PM PDT 24
Peak memory 214548 kb
Host smart-a8b05274-f086-482e-aeb0-7151563f58fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871646184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2871646184
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3852278037
Short name T263
Test name
Test status
Simulation time 47030044 ps
CPU time 0.99 seconds
Started Jul 10 06:37:58 PM PDT 24
Finished Jul 10 06:38:02 PM PDT 24
Peak memory 206236 kb
Host smart-86eb97f1-0cff-430b-93b3-2380d69850c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3852278037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3852278037
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3318660333
Short name T2768
Test name
Test status
Simulation time 28949909 ps
CPU time 0.65 seconds
Started Jul 10 06:37:59 PM PDT 24
Finished Jul 10 06:38:03 PM PDT 24
Peak memory 206016 kb
Host smart-c98a71fb-91dd-4f81-b18a-e77ffaa6756e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3318660333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3318660333
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2763474768
Short name T2839
Test name
Test status
Simulation time 111852981 ps
CPU time 1.1 seconds
Started Jul 10 06:38:03 PM PDT 24
Finished Jul 10 06:38:10 PM PDT 24
Peak memory 206376 kb
Host smart-521aff30-3194-4f62-aa6a-6fae74a69d08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2763474768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2763474768
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3852549552
Short name T2797
Test name
Test status
Simulation time 159416851 ps
CPU time 2.05 seconds
Started Jul 10 06:38:05 PM PDT 24
Finished Jul 10 06:38:11 PM PDT 24
Peak memory 222276 kb
Host smart-78752445-2431-408e-b39c-b7e3ed87b187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3852549552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3852549552
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.4179026950
Short name T304
Test name
Test status
Simulation time 631838400 ps
CPU time 2.81 seconds
Started Jul 10 06:37:59 PM PDT 24
Finished Jul 10 06:38:07 PM PDT 24
Peak memory 206344 kb
Host smart-4eca77c0-2804-40b9-b6c4-8ed239cfdb00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4179026950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.4179026950
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1981820450
Short name T2835
Test name
Test status
Simulation time 79999678 ps
CPU time 1.41 seconds
Started Jul 10 06:38:06 PM PDT 24
Finished Jul 10 06:38:13 PM PDT 24
Peak memory 214468 kb
Host smart-069e0fec-a2a9-44fe-ae96-ff51c848ea1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981820450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1981820450
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1600692777
Short name T2788
Test name
Test status
Simulation time 79865580 ps
CPU time 1.06 seconds
Started Jul 10 06:38:02 PM PDT 24
Finished Jul 10 06:38:08 PM PDT 24
Peak memory 206208 kb
Host smart-de126ce8-5643-4aac-a570-89655db0eaac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1600692777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1600692777
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3352282930
Short name T2798
Test name
Test status
Simulation time 44902071 ps
CPU time 0.71 seconds
Started Jul 10 06:37:58 PM PDT 24
Finished Jul 10 06:38:02 PM PDT 24
Peak memory 206176 kb
Host smart-121203b0-1b77-4b8c-a4e3-a66d143b0b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3352282930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3352282930
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1087128604
Short name T2833
Test name
Test status
Simulation time 74068981 ps
CPU time 1.11 seconds
Started Jul 10 06:37:58 PM PDT 24
Finished Jul 10 06:38:03 PM PDT 24
Peak memory 206264 kb
Host smart-f02e32b8-f8b7-4c7b-8bb3-bdc9953d1d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1087128604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1087128604
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2512664472
Short name T2786
Test name
Test status
Simulation time 153726518 ps
CPU time 1.74 seconds
Started Jul 10 06:37:57 PM PDT 24
Finished Jul 10 06:38:02 PM PDT 24
Peak memory 206384 kb
Host smart-0cfaefd9-4b31-4763-a386-71b43cbdc1e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2512664472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2512664472
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1002786380
Short name T2827
Test name
Test status
Simulation time 547876333 ps
CPU time 2.9 seconds
Started Jul 10 06:37:59 PM PDT 24
Finished Jul 10 06:38:06 PM PDT 24
Peak memory 206312 kb
Host smart-a824b7c5-6146-424c-8f65-a764d07f368a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1002786380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1002786380
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2159125768
Short name T2838
Test name
Test status
Simulation time 241340879 ps
CPU time 1.89 seconds
Started Jul 10 06:38:05 PM PDT 24
Finished Jul 10 06:38:12 PM PDT 24
Peak memory 222692 kb
Host smart-70eadb57-f522-422d-a758-2631725f32fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159125768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2159125768
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.33136573
Short name T268
Test name
Test status
Simulation time 58796280 ps
CPU time 0.89 seconds
Started Jul 10 06:38:04 PM PDT 24
Finished Jul 10 06:38:10 PM PDT 24
Peak memory 206036 kb
Host smart-9dcac03e-b2a0-4744-9e73-939b752c8e6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=33136573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.33136573
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3894491120
Short name T2761
Test name
Test status
Simulation time 58104506 ps
CPU time 0.71 seconds
Started Jul 10 06:38:05 PM PDT 24
Finished Jul 10 06:38:10 PM PDT 24
Peak memory 206000 kb
Host smart-e4f2e600-c488-4540-83cd-a9787d71255c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3894491120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3894491120
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3556640237
Short name T265
Test name
Test status
Simulation time 113197914 ps
CPU time 1.47 seconds
Started Jul 10 06:38:06 PM PDT 24
Finished Jul 10 06:38:12 PM PDT 24
Peak memory 206392 kb
Host smart-708f0c84-207b-4758-9a20-5200a879e8d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3556640237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3556640237
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.543975114
Short name T2824
Test name
Test status
Simulation time 255557027 ps
CPU time 2.9 seconds
Started Jul 10 06:38:04 PM PDT 24
Finished Jul 10 06:38:12 PM PDT 24
Peak memory 206340 kb
Host smart-7375ef85-1671-41e4-8352-ddbe2a425bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=543975114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.543975114
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2132039604
Short name T220
Test name
Test status
Simulation time 997793343 ps
CPU time 4.6 seconds
Started Jul 10 06:38:07 PM PDT 24
Finished Jul 10 06:38:16 PM PDT 24
Peak memory 206376 kb
Host smart-f00770c3-6e24-44b3-a3f9-4c4c3b2b095b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2132039604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2132039604
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2419952534
Short name T968
Test name
Test status
Simulation time 31459397 ps
CPU time 0.69 seconds
Started Jul 10 06:38:48 PM PDT 24
Finished Jul 10 06:38:53 PM PDT 24
Peak memory 206408 kb
Host smart-b0b29b56-ddd0-490a-b8c0-5d768e0c585c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2419952534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2419952534
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.4248826553
Short name T2131
Test name
Test status
Simulation time 3511001920 ps
CPU time 4.06 seconds
Started Jul 10 06:38:26 PM PDT 24
Finished Jul 10 06:38:36 PM PDT 24
Peak memory 206628 kb
Host smart-8523b312-409f-475e-9027-946280fe1b81
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4248826553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.4248826553
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2103133317
Short name T802
Test name
Test status
Simulation time 13342826377 ps
CPU time 12.68 seconds
Started Jul 10 06:38:29 PM PDT 24
Finished Jul 10 06:38:48 PM PDT 24
Peak memory 206464 kb
Host smart-fe9e5316-0dc1-4e81-8fd1-241413754e84
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2103133317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2103133317
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2570691659
Short name T796
Test name
Test status
Simulation time 23430330995 ps
CPU time 23.61 seconds
Started Jul 10 06:38:30 PM PDT 24
Finished Jul 10 06:39:00 PM PDT 24
Peak memory 206660 kb
Host smart-3290467a-3127-4bdb-a2a7-5f23b5a62fc3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2570691659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2570691659
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1206721992
Short name T355
Test name
Test status
Simulation time 148302789 ps
CPU time 0.8 seconds
Started Jul 10 06:38:28 PM PDT 24
Finished Jul 10 06:38:35 PM PDT 24
Peak memory 206384 kb
Host smart-9dc86c92-02cc-45e5-9a16-8a9350ddc698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12067
21992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1206721992
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1698264639
Short name T1509
Test name
Test status
Simulation time 160494062 ps
CPU time 0.79 seconds
Started Jul 10 06:38:27 PM PDT 24
Finished Jul 10 06:38:34 PM PDT 24
Peak memory 206564 kb
Host smart-3b540464-a97e-40eb-baef-ef68b1d530c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16982
64639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1698264639
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2374159257
Short name T1699
Test name
Test status
Simulation time 643081089 ps
CPU time 1.58 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206552 kb
Host smart-d3ec52a3-c85d-4456-8b5c-e11022640ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23741
59257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2374159257
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3470650890
Short name T690
Test name
Test status
Simulation time 11612951595 ps
CPU time 21.56 seconds
Started Jul 10 06:38:27 PM PDT 24
Finished Jul 10 06:38:54 PM PDT 24
Peak memory 206692 kb
Host smart-8f17b982-36f0-4267-a009-3fcd419adba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34706
50890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3470650890
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3697036332
Short name T2008
Test name
Test status
Simulation time 474647832 ps
CPU time 1.4 seconds
Started Jul 10 06:38:27 PM PDT 24
Finished Jul 10 06:38:35 PM PDT 24
Peak memory 206568 kb
Host smart-cf902820-e70a-4025-a3e9-b4579b3df824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36970
36332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3697036332
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3272594812
Short name T1082
Test name
Test status
Simulation time 159896591 ps
CPU time 0.81 seconds
Started Jul 10 06:38:30 PM PDT 24
Finished Jul 10 06:38:37 PM PDT 24
Peak memory 206400 kb
Host smart-49ca3d2b-7a8f-4dee-a30a-e70a0f7c958a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32725
94812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3272594812
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.4283085387
Short name T1827
Test name
Test status
Simulation time 5110557365 ps
CPU time 130.66 seconds
Started Jul 10 06:38:30 PM PDT 24
Finished Jul 10 06:40:47 PM PDT 24
Peak memory 206664 kb
Host smart-e3b96ac0-c55f-469f-b145-4ecd731914a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42830
85387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.4283085387
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.3842103592
Short name T2297
Test name
Test status
Simulation time 56216814 ps
CPU time 0.69 seconds
Started Jul 10 06:38:27 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206364 kb
Host smart-48bf222d-7acd-4daf-8397-fb2f7b0c6e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38421
03592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3842103592
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3869944410
Short name T2141
Test name
Test status
Simulation time 1117113851 ps
CPU time 2.42 seconds
Started Jul 10 06:38:29 PM PDT 24
Finished Jul 10 06:38:38 PM PDT 24
Peak memory 206656 kb
Host smart-14454ae8-d2d4-4566-a5b4-70276f2b8445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38699
44410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3869944410
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3750557282
Short name T1225
Test name
Test status
Simulation time 176200491 ps
CPU time 1.89 seconds
Started Jul 10 06:42:43 PM PDT 24
Finished Jul 10 06:42:49 PM PDT 24
Peak memory 206572 kb
Host smart-c7a137e6-0113-40aa-9adb-3ccb23b38a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37505
57282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3750557282
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2216051531
Short name T576
Test name
Test status
Simulation time 111212992155 ps
CPU time 150.53 seconds
Started Jul 10 06:38:27 PM PDT 24
Finished Jul 10 06:41:04 PM PDT 24
Peak memory 206624 kb
Host smart-5944856d-6aa4-4d23-8603-f952e24d9ab5
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2216051531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2216051531
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.207044352
Short name T2562
Test name
Test status
Simulation time 88351703631 ps
CPU time 117.49 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:40:28 PM PDT 24
Peak memory 206628 kb
Host smart-62a9ecb8-0531-490d-872f-abb6ca00abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207044352 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.207044352
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.445618028
Short name T868
Test name
Test status
Simulation time 90124733287 ps
CPU time 118.85 seconds
Started Jul 10 06:38:25 PM PDT 24
Finished Jul 10 06:40:29 PM PDT 24
Peak memory 206632 kb
Host smart-dd4bb4a8-4c62-4262-ba6e-c09884b60bc4
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=445618028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.445618028
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.886663135
Short name T1354
Test name
Test status
Simulation time 85001976071 ps
CPU time 113.6 seconds
Started Jul 10 06:38:28 PM PDT 24
Finished Jul 10 06:40:28 PM PDT 24
Peak memory 206672 kb
Host smart-20f80f33-4ddc-4510-ac6a-c14a73e6396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886663135 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.886663135
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.1297164962
Short name T1258
Test name
Test status
Simulation time 83155693487 ps
CPU time 111.86 seconds
Started Jul 10 06:38:28 PM PDT 24
Finished Jul 10 06:40:27 PM PDT 24
Peak memory 206668 kb
Host smart-377adacf-ed24-486b-b246-a2cd5c627db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
64962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.1297164962
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2248379929
Short name T2547
Test name
Test status
Simulation time 233638485 ps
CPU time 1.06 seconds
Started Jul 10 06:38:30 PM PDT 24
Finished Jul 10 06:38:38 PM PDT 24
Peak memory 206392 kb
Host smart-47fbf16c-32cf-4d34-893f-dd496eb20091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22483
79929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2248379929
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2668367280
Short name T2310
Test name
Test status
Simulation time 137879658 ps
CPU time 0.76 seconds
Started Jul 10 06:38:27 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206364 kb
Host smart-d1d43dde-6ecd-409c-af25-7ca8f4793a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26683
67280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2668367280
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.4172693924
Short name T1292
Test name
Test status
Simulation time 204555206 ps
CPU time 0.95 seconds
Started Jul 10 06:38:26 PM PDT 24
Finished Jul 10 06:38:33 PM PDT 24
Peak memory 206376 kb
Host smart-5e20d673-5a37-42e4-a5df-8bdf6360be70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41726
93924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.4172693924
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.3362625242
Short name T2175
Test name
Test status
Simulation time 7659286462 ps
CPU time 68.08 seconds
Started Jul 10 06:38:27 PM PDT 24
Finished Jul 10 06:39:41 PM PDT 24
Peak memory 206712 kb
Host smart-bd3c9546-cade-401a-a90c-e2e5bf1514ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33626
25242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.3362625242
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3254692963
Short name T2241
Test name
Test status
Simulation time 175635981 ps
CPU time 0.89 seconds
Started Jul 10 06:38:28 PM PDT 24
Finished Jul 10 06:38:35 PM PDT 24
Peak memory 206400 kb
Host smart-fec0502a-3e25-4267-8921-85760e28481e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32546
92963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3254692963
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.2764729327
Short name T74
Test name
Test status
Simulation time 529960729 ps
CPU time 1.52 seconds
Started Jul 10 06:38:32 PM PDT 24
Finished Jul 10 06:38:39 PM PDT 24
Peak memory 206368 kb
Host smart-2446d1a9-27b0-48c5-b3a6-3c1647b72550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27647
29327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.2764729327
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.3988342403
Short name T2312
Test name
Test status
Simulation time 23333279164 ps
CPU time 28.27 seconds
Started Jul 10 06:38:32 PM PDT 24
Finished Jul 10 06:39:06 PM PDT 24
Peak memory 206416 kb
Host smart-b37ef719-0fee-4b94-b6c7-b44f8792bfe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39883
42403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.3988342403
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1763162314
Short name T1528
Test name
Test status
Simulation time 3298009275 ps
CPU time 3.76 seconds
Started Jul 10 06:38:34 PM PDT 24
Finished Jul 10 06:38:42 PM PDT 24
Peak memory 206440 kb
Host smart-5ae9dbc3-aa97-41ee-a492-b53f34a442ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17631
62314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1763162314
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.942001695
Short name T2335
Test name
Test status
Simulation time 8995242765 ps
CPU time 62.37 seconds
Started Jul 10 06:38:36 PM PDT 24
Finished Jul 10 06:39:43 PM PDT 24
Peak memory 206732 kb
Host smart-1d1bdba0-a05a-4f4d-9248-f986c9819768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94200
1695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.942001695
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.4204922670
Short name T2278
Test name
Test status
Simulation time 5946938475 ps
CPU time 169.13 seconds
Started Jul 10 06:38:33 PM PDT 24
Finished Jul 10 06:41:27 PM PDT 24
Peak memory 206640 kb
Host smart-90a3f900-f670-4d82-b041-e87fb08f34aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4204922670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.4204922670
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1213229569
Short name T2090
Test name
Test status
Simulation time 241291408 ps
CPU time 0.91 seconds
Started Jul 10 06:38:32 PM PDT 24
Finished Jul 10 06:38:38 PM PDT 24
Peak memory 206388 kb
Host smart-6a1db7ed-9c46-45c3-a0a5-137f45b5bb33
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1213229569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1213229569
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.771719278
Short name T2254
Test name
Test status
Simulation time 190356102 ps
CPU time 0.93 seconds
Started Jul 10 06:38:33 PM PDT 24
Finished Jul 10 06:38:39 PM PDT 24
Peak memory 206392 kb
Host smart-d00ccdf4-1033-45b9-a159-df1da0e71d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77171
9278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.771719278
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3100783671
Short name T151
Test name
Test status
Simulation time 4150952360 ps
CPU time 29.3 seconds
Started Jul 10 06:38:34 PM PDT 24
Finished Jul 10 06:39:08 PM PDT 24
Peak memory 206596 kb
Host smart-6a6ee201-a858-41f6-8bcb-722340931f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31007
83671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3100783671
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.979283859
Short name T1727
Test name
Test status
Simulation time 4465495461 ps
CPU time 31.18 seconds
Started Jul 10 06:38:35 PM PDT 24
Finished Jul 10 06:39:11 PM PDT 24
Peak memory 206664 kb
Host smart-6c989c7a-ceef-4aca-9892-bde0b7112458
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=979283859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.979283859
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.74592992
Short name T1269
Test name
Test status
Simulation time 151261705 ps
CPU time 0.8 seconds
Started Jul 10 06:38:37 PM PDT 24
Finished Jul 10 06:38:42 PM PDT 24
Peak memory 206352 kb
Host smart-399a2537-0d68-447a-a90c-527606157cba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=74592992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.74592992
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3894919378
Short name T656
Test name
Test status
Simulation time 142253975 ps
CPU time 0.82 seconds
Started Jul 10 06:38:38 PM PDT 24
Finished Jul 10 06:38:43 PM PDT 24
Peak memory 206384 kb
Host smart-dab120de-f9b3-4952-96c8-d39c632044ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38949
19378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3894919378
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2301562775
Short name T72
Test name
Test status
Simulation time 498172160 ps
CPU time 1.36 seconds
Started Jul 10 06:38:36 PM PDT 24
Finished Jul 10 06:38:42 PM PDT 24
Peak memory 206376 kb
Host smart-f747a449-ffbb-4df8-89b2-4a1bd3cab916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23015
62775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2301562775
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1928676129
Short name T1633
Test name
Test status
Simulation time 154662883 ps
CPU time 0.78 seconds
Started Jul 10 06:38:33 PM PDT 24
Finished Jul 10 06:38:39 PM PDT 24
Peak memory 206376 kb
Host smart-bf879538-cdef-41bc-a1e1-590d83c15c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19286
76129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1928676129
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3199914685
Short name T1884
Test name
Test status
Simulation time 163198152 ps
CPU time 0.83 seconds
Started Jul 10 06:38:35 PM PDT 24
Finished Jul 10 06:38:40 PM PDT 24
Peak memory 206384 kb
Host smart-3a13ec5d-6638-41c8-8538-439ac4daeac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31999
14685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3199914685
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2528754840
Short name T1199
Test name
Test status
Simulation time 179774519 ps
CPU time 0.85 seconds
Started Jul 10 06:38:33 PM PDT 24
Finished Jul 10 06:38:39 PM PDT 24
Peak memory 206324 kb
Host smart-eeebbbf1-5acc-4bd1-beeb-4833bbefcd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25287
54840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2528754840
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3148586772
Short name T2042
Test name
Test status
Simulation time 150751480 ps
CPU time 0.81 seconds
Started Jul 10 06:38:34 PM PDT 24
Finished Jul 10 06:38:39 PM PDT 24
Peak memory 206336 kb
Host smart-60446731-f8f7-492a-a65a-dd3c5e430e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31485
86772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3148586772
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2736202722
Short name T2586
Test name
Test status
Simulation time 166919784 ps
CPU time 0.84 seconds
Started Jul 10 06:38:38 PM PDT 24
Finished Jul 10 06:38:43 PM PDT 24
Peak memory 206368 kb
Host smart-037d60f3-56df-46f6-a306-f39c2e8e88b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27362
02722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2736202722
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.487519571
Short name T199
Test name
Test status
Simulation time 219500169 ps
CPU time 0.96 seconds
Started Jul 10 06:38:33 PM PDT 24
Finished Jul 10 06:38:39 PM PDT 24
Peak memory 206352 kb
Host smart-8b553547-99bf-4863-9b36-ab8c6383b682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48751
9571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.487519571
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3862818792
Short name T565
Test name
Test status
Simulation time 281332144 ps
CPU time 0.98 seconds
Started Jul 10 06:38:32 PM PDT 24
Finished Jul 10 06:38:38 PM PDT 24
Peak memory 206400 kb
Host smart-1582ec96-f078-4a61-82b3-15a4c07b01f1
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3862818792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3862818792
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2639369537
Short name T29
Test name
Test status
Simulation time 201107613 ps
CPU time 1.01 seconds
Started Jul 10 06:38:43 PM PDT 24
Finished Jul 10 06:38:49 PM PDT 24
Peak memory 206368 kb
Host smart-d0ffb0bf-fbe3-4ba9-9810-a8e5ff789bc1
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2639369537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2639369537
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.4020223486
Short name T1609
Test name
Test status
Simulation time 140095754 ps
CPU time 0.75 seconds
Started Jul 10 06:38:40 PM PDT 24
Finished Jul 10 06:38:46 PM PDT 24
Peak memory 206372 kb
Host smart-1c472810-bb50-4c72-9eb7-bd9d33645c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40202
23486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.4020223486
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1592356042
Short name T1030
Test name
Test status
Simulation time 49967464 ps
CPU time 0.65 seconds
Started Jul 10 06:38:40 PM PDT 24
Finished Jul 10 06:38:45 PM PDT 24
Peak memory 206392 kb
Host smart-3f016688-ef88-4349-8b8c-175adf943271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15923
56042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1592356042
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3270317682
Short name T2019
Test name
Test status
Simulation time 11588631740 ps
CPU time 27.47 seconds
Started Jul 10 06:38:40 PM PDT 24
Finished Jul 10 06:39:13 PM PDT 24
Peak memory 206568 kb
Host smart-2cbc824b-4cb3-4210-913a-d5679c6e5dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32703
17682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3270317682
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2482526980
Short name T393
Test name
Test status
Simulation time 218504799 ps
CPU time 0.88 seconds
Started Jul 10 06:38:41 PM PDT 24
Finished Jul 10 06:38:47 PM PDT 24
Peak memory 206392 kb
Host smart-5ca2225f-30ef-434a-8bd5-4054559aefdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24825
26980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2482526980
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1027961702
Short name T2158
Test name
Test status
Simulation time 11370104596 ps
CPU time 60.94 seconds
Started Jul 10 06:38:39 PM PDT 24
Finished Jul 10 06:39:45 PM PDT 24
Peak memory 206652 kb
Host smart-d76ffa45-da5f-4c44-a348-274149129c99
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1027961702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1027961702
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.4287232100
Short name T2522
Test name
Test status
Simulation time 11073334875 ps
CPU time 61.1 seconds
Started Jul 10 06:38:40 PM PDT 24
Finished Jul 10 06:39:47 PM PDT 24
Peak memory 206644 kb
Host smart-a5496196-b9e4-463c-b400-615ee6e2b102
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4287232100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.4287232100
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1604437023
Short name T1877
Test name
Test status
Simulation time 11705081256 ps
CPU time 58.61 seconds
Started Jul 10 06:38:48 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206608 kb
Host smart-a8f0edfc-afbd-46cc-96b1-cfe1f14f5e39
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1604437023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1604437023
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3196745381
Short name T2272
Test name
Test status
Simulation time 197154042 ps
CPU time 0.84 seconds
Started Jul 10 06:38:39 PM PDT 24
Finished Jul 10 06:38:44 PM PDT 24
Peak memory 206372 kb
Host smart-885b8ead-17a1-4f81-a745-cc91f40b7cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31967
45381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3196745381
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.2531004060
Short name T2186
Test name
Test status
Simulation time 159354155 ps
CPU time 0.83 seconds
Started Jul 10 06:38:39 PM PDT 24
Finished Jul 10 06:38:44 PM PDT 24
Peak memory 206380 kb
Host smart-b1945062-40d4-4d74-bc70-b747e1302f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25310
04060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2531004060
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.539127080
Short name T1100
Test name
Test status
Simulation time 161556822 ps
CPU time 0.75 seconds
Started Jul 10 06:38:48 PM PDT 24
Finished Jul 10 06:38:53 PM PDT 24
Peak memory 206388 kb
Host smart-0037cfce-81ab-4d51-856f-e6f2eee1fbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53912
7080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.539127080
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2424601007
Short name T192
Test name
Test status
Simulation time 337041604 ps
CPU time 1.23 seconds
Started Jul 10 06:38:48 PM PDT 24
Finished Jul 10 06:38:54 PM PDT 24
Peak memory 224140 kb
Host smart-1d64c3c7-56ab-47f1-8957-08e3bc94a7ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2424601007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2424601007
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.4280524162
Short name T791
Test name
Test status
Simulation time 195523991 ps
CPU time 0.85 seconds
Started Jul 10 06:38:51 PM PDT 24
Finished Jul 10 06:38:55 PM PDT 24
Peak memory 206376 kb
Host smart-d43e00fc-2826-4ee0-a938-7c47061d5a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42805
24162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.4280524162
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1073128762
Short name T2507
Test name
Test status
Simulation time 155639916 ps
CPU time 0.88 seconds
Started Jul 10 06:38:48 PM PDT 24
Finished Jul 10 06:38:53 PM PDT 24
Peak memory 206384 kb
Host smart-94df121e-6497-4c42-9b03-3d94b7b41d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10731
28762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1073128762
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3966986032
Short name T1123
Test name
Test status
Simulation time 152550373 ps
CPU time 0.82 seconds
Started Jul 10 06:38:47 PM PDT 24
Finished Jul 10 06:38:51 PM PDT 24
Peak memory 206376 kb
Host smart-8bb8b3ff-80e9-48c5-9223-e0c0b3d21034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39669
86032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3966986032
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1812822758
Short name T2479
Test name
Test status
Simulation time 241777389 ps
CPU time 0.96 seconds
Started Jul 10 06:38:49 PM PDT 24
Finished Jul 10 06:38:54 PM PDT 24
Peak memory 206356 kb
Host smart-7def4a31-3c56-4cc9-82b9-07af1ba3700c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
22758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1812822758
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1194165640
Short name T1455
Test name
Test status
Simulation time 6142107593 ps
CPU time 61.1 seconds
Started Jul 10 06:38:49 PM PDT 24
Finished Jul 10 06:39:54 PM PDT 24
Peak memory 206640 kb
Host smart-bacaf7a1-6c71-4980-9c0f-e394fe51518c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1194165640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1194165640
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1044943564
Short name T2261
Test name
Test status
Simulation time 171241538 ps
CPU time 0.8 seconds
Started Jul 10 06:38:46 PM PDT 24
Finished Jul 10 06:38:51 PM PDT 24
Peak memory 206396 kb
Host smart-e57132f7-6bc2-4400-ad14-b86daad1eb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10449
43564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1044943564
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3869724943
Short name T556
Test name
Test status
Simulation time 204107399 ps
CPU time 0.83 seconds
Started Jul 10 06:38:49 PM PDT 24
Finished Jul 10 06:38:54 PM PDT 24
Peak memory 206400 kb
Host smart-edda8dde-91ae-493e-97f9-5b14e8ca57b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
24943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3869724943
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.723193117
Short name T2513
Test name
Test status
Simulation time 1144365124 ps
CPU time 2.59 seconds
Started Jul 10 06:38:49 PM PDT 24
Finished Jul 10 06:38:55 PM PDT 24
Peak memory 206656 kb
Host smart-43edf768-2db6-4cb4-b710-224f64b5d0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72319
3117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.723193117
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3289702020
Short name T2386
Test name
Test status
Simulation time 5505178011 ps
CPU time 154.61 seconds
Started Jul 10 06:38:47 PM PDT 24
Finished Jul 10 06:41:26 PM PDT 24
Peak memory 206676 kb
Host smart-ddb0ab28-2fd1-4e55-978b-21598ff37501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32897
02020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3289702020
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1432603543
Short name T2173
Test name
Test status
Simulation time 15868470568 ps
CPU time 343.27 seconds
Started Jul 10 06:38:50 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206736 kb
Host smart-bb065bc1-aab1-4519-8c84-042a8fd5f0b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1432603543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.1432603543
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1491107953
Short name T1932
Test name
Test status
Simulation time 46296048 ps
CPU time 0.69 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:39:08 PM PDT 24
Peak memory 206396 kb
Host smart-d753af34-3231-4efd-a84b-a81cab289779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1491107953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1491107953
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.544829872
Short name T1616
Test name
Test status
Simulation time 3648860996 ps
CPU time 4.79 seconds
Started Jul 10 06:38:49 PM PDT 24
Finished Jul 10 06:38:58 PM PDT 24
Peak memory 206404 kb
Host smart-fbef6e11-135b-4ffc-a315-44e909c3f75e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=544829872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.544829872
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3860254243
Short name T2552
Test name
Test status
Simulation time 13374969073 ps
CPU time 12.42 seconds
Started Jul 10 06:38:49 PM PDT 24
Finished Jul 10 06:39:06 PM PDT 24
Peak memory 206432 kb
Host smart-3efa0121-e4fe-4fe6-9555-7a4174bc2d0f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3860254243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3860254243
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3453987485
Short name T1067
Test name
Test status
Simulation time 23392828156 ps
CPU time 22.73 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:39:20 PM PDT 24
Peak memory 206460 kb
Host smart-990d49c8-c183-4287-9631-54d46943ae6e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3453987485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.3453987485
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3465550049
Short name T2699
Test name
Test status
Simulation time 153696339 ps
CPU time 0.81 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:38:59 PM PDT 24
Peak memory 206380 kb
Host smart-c5b8b404-7759-474f-a312-88f3e910faa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655
50049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3465550049
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.512382539
Short name T2703
Test name
Test status
Simulation time 148623314 ps
CPU time 0.76 seconds
Started Jul 10 06:38:54 PM PDT 24
Finished Jul 10 06:38:58 PM PDT 24
Peak memory 206360 kb
Host smart-552d2123-c58b-44e2-b5af-3394e0f55efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51238
2539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.512382539
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.570315407
Short name T2253
Test name
Test status
Simulation time 142147130 ps
CPU time 0.75 seconds
Started Jul 10 06:38:57 PM PDT 24
Finished Jul 10 06:39:01 PM PDT 24
Peak memory 206376 kb
Host smart-75ab27eb-459c-436f-b98f-ed89d53320f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57031
5407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.570315407
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2094700057
Short name T1832
Test name
Test status
Simulation time 247786241 ps
CPU time 0.97 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:38:58 PM PDT 24
Peak memory 206372 kb
Host smart-1d444607-1a37-401c-8254-c685cef1f1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20947
00057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2094700057
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.910664727
Short name T2449
Test name
Test status
Simulation time 431459676 ps
CPU time 1.15 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:01 PM PDT 24
Peak memory 206352 kb
Host smart-8a3094f6-ff5e-4563-99fe-5ecf1e1d8c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91066
4727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.910664727
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.313378580
Short name T1995
Test name
Test status
Simulation time 12142917418 ps
CPU time 26.22 seconds
Started Jul 10 06:39:00 PM PDT 24
Finished Jul 10 06:39:30 PM PDT 24
Peak memory 206716 kb
Host smart-828967c7-f862-43dc-b723-d37db58cf19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31337
8580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.313378580
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2805357247
Short name T2049
Test name
Test status
Simulation time 408576890 ps
CPU time 1.2 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:01 PM PDT 24
Peak memory 206396 kb
Host smart-171d6160-f0b4-41ff-aad2-b711b3bb1ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
57247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2805357247
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3565762959
Short name T2389
Test name
Test status
Simulation time 170405896 ps
CPU time 0.86 seconds
Started Jul 10 06:38:57 PM PDT 24
Finished Jul 10 06:39:02 PM PDT 24
Peak memory 206364 kb
Host smart-f6d74caa-4efc-497b-afae-c77bf2610947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35657
62959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3565762959
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3261156127
Short name T654
Test name
Test status
Simulation time 81882975 ps
CPU time 0.7 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:38:59 PM PDT 24
Peak memory 206360 kb
Host smart-0f6e1499-eab5-45ba-a393-126e60c31632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
56127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3261156127
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3131418870
Short name T1507
Test name
Test status
Simulation time 820571155 ps
CPU time 1.9 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:01 PM PDT 24
Peak memory 206616 kb
Host smart-a88e6bbb-b4f3-4332-b420-6c9543603686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31314
18870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3131418870
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3323888029
Short name T1417
Test name
Test status
Simulation time 205515601 ps
CPU time 1.28 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:38:59 PM PDT 24
Peak memory 206556 kb
Host smart-59006682-d27b-43ac-b024-747024230120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33238
88029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3323888029
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.3658058164
Short name T2032
Test name
Test status
Simulation time 81176246647 ps
CPU time 109.7 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:40:49 PM PDT 24
Peak memory 206612 kb
Host smart-5346cb68-475f-4fcf-8458-507aab37c3b8
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3658058164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3658058164
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.372133502
Short name T1406
Test name
Test status
Simulation time 81218989679 ps
CPU time 122.19 seconds
Started Jul 10 06:38:54 PM PDT 24
Finished Jul 10 06:40:58 PM PDT 24
Peak memory 206608 kb
Host smart-b3450d4c-872b-4415-a372-6389233aa882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372133502 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.372133502
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.1259641096
Short name T1127
Test name
Test status
Simulation time 91127682012 ps
CPU time 132.64 seconds
Started Jul 10 06:38:59 PM PDT 24
Finished Jul 10 06:41:15 PM PDT 24
Peak memory 206696 kb
Host smart-38150c32-c10e-464d-a480-e29098a35d97
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1259641096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.1259641096
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.1588619600
Short name T390
Test name
Test status
Simulation time 106053581832 ps
CPU time 161.53 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206664 kb
Host smart-76b92cca-e904-4f2f-80d2-68b00d245904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588619600 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1588619600
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1120218996
Short name T922
Test name
Test status
Simulation time 81180081400 ps
CPU time 112.98 seconds
Started Jul 10 06:38:54 PM PDT 24
Finished Jul 10 06:40:50 PM PDT 24
Peak memory 206700 kb
Host smart-f5f68c37-74f7-44a4-9a67-a92fa62de537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11202
18996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1120218996
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2556911090
Short name T2268
Test name
Test status
Simulation time 188689014 ps
CPU time 0.89 seconds
Started Jul 10 06:38:54 PM PDT 24
Finished Jul 10 06:38:58 PM PDT 24
Peak memory 206364 kb
Host smart-933ad6d5-5a5d-4c51-900b-5472f504d8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25569
11090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2556911090
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1225431794
Short name T984
Test name
Test status
Simulation time 197662250 ps
CPU time 0.84 seconds
Started Jul 10 06:39:01 PM PDT 24
Finished Jul 10 06:39:06 PM PDT 24
Peak memory 206100 kb
Host smart-0d4ba7c9-caf4-4844-908d-e914e5613ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12254
31794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1225431794
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.4158482842
Short name T1709
Test name
Test status
Simulation time 242682830 ps
CPU time 0.92 seconds
Started Jul 10 06:39:01 PM PDT 24
Finished Jul 10 06:39:06 PM PDT 24
Peak memory 206152 kb
Host smart-2ed9d72f-5d49-4442-a52e-41c17cba1c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41584
82842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.4158482842
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2831644968
Short name T761
Test name
Test status
Simulation time 9186933205 ps
CPU time 253.52 seconds
Started Jul 10 06:39:00 PM PDT 24
Finished Jul 10 06:43:18 PM PDT 24
Peak memory 206640 kb
Host smart-422517a2-48f2-4f95-8f54-d9c89167a5be
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2831644968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2831644968
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.2487594962
Short name T813
Test name
Test status
Simulation time 12415779783 ps
CPU time 51.8 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:39:50 PM PDT 24
Peak memory 206620 kb
Host smart-6999d317-8f61-4a5a-84b2-9a68822a6d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24875
94962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.2487594962
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2937928425
Short name T2650
Test name
Test status
Simulation time 244926528 ps
CPU time 0.99 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:01 PM PDT 24
Peak memory 206240 kb
Host smart-5bc2194d-bbe3-4e2a-8592-3a7ad73d4b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
28425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2937928425
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.187781244
Short name T1445
Test name
Test status
Simulation time 23296629780 ps
CPU time 21.2 seconds
Started Jul 10 06:39:00 PM PDT 24
Finished Jul 10 06:39:25 PM PDT 24
Peak memory 206424 kb
Host smart-6aa4d246-3740-42b8-8498-12cd2ee66de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18778
1244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.187781244
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1985399513
Short name T1339
Test name
Test status
Simulation time 3307185822 ps
CPU time 3.48 seconds
Started Jul 10 06:39:01 PM PDT 24
Finished Jul 10 06:39:09 PM PDT 24
Peak memory 206384 kb
Host smart-e46a8cf3-41f7-44a0-915b-3f40c019ae3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19853
99513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1985399513
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.1700840293
Short name T2201
Test name
Test status
Simulation time 11714087689 ps
CPU time 111.64 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206700 kb
Host smart-2875cd79-4296-410b-9efc-3dd9b9005b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17008
40293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1700840293
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2071359057
Short name T1792
Test name
Test status
Simulation time 4981133185 ps
CPU time 131.19 seconds
Started Jul 10 06:38:54 PM PDT 24
Finished Jul 10 06:41:08 PM PDT 24
Peak memory 206628 kb
Host smart-468df093-a401-4ee0-8139-df98dd680fe5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2071359057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2071359057
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3013754476
Short name T535
Test name
Test status
Simulation time 255904077 ps
CPU time 0.98 seconds
Started Jul 10 06:38:59 PM PDT 24
Finished Jul 10 06:39:03 PM PDT 24
Peak memory 206376 kb
Host smart-cd23d57e-80d9-4968-acd6-de5b0d18a2a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3013754476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3013754476
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3309403426
Short name T456
Test name
Test status
Simulation time 187242016 ps
CPU time 0.85 seconds
Started Jul 10 06:38:59 PM PDT 24
Finished Jul 10 06:39:03 PM PDT 24
Peak memory 206384 kb
Host smart-60f7037a-4d9b-43a9-8e45-330fd142ae66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33094
03426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3309403426
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.993263489
Short name T2362
Test name
Test status
Simulation time 3387527597 ps
CPU time 32.72 seconds
Started Jul 10 06:38:54 PM PDT 24
Finished Jul 10 06:39:30 PM PDT 24
Peak memory 206656 kb
Host smart-7c51fdd3-001e-4cd5-9fd1-948b7ac920b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99326
3489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.993263489
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3778013637
Short name T1745
Test name
Test status
Simulation time 8044501578 ps
CPU time 75.22 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:40:15 PM PDT 24
Peak memory 206644 kb
Host smart-e0f97752-d160-417e-9e30-09bf3b4d58cb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3778013637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3778013637
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1321045171
Short name T2466
Test name
Test status
Simulation time 159211382 ps
CPU time 0.81 seconds
Started Jul 10 06:38:57 PM PDT 24
Finished Jul 10 06:39:02 PM PDT 24
Peak memory 206380 kb
Host smart-dc3f49d2-0dfc-40db-8ced-f4876253dc32
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1321045171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1321045171
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1617142335
Short name T2593
Test name
Test status
Simulation time 146462531 ps
CPU time 0.8 seconds
Started Jul 10 06:38:57 PM PDT 24
Finished Jul 10 06:39:02 PM PDT 24
Peak memory 206384 kb
Host smart-27b2b196-2ca5-4635-b595-add86f215b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16171
42335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1617142335
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1226280634
Short name T138
Test name
Test status
Simulation time 199339501 ps
CPU time 0.83 seconds
Started Jul 10 06:39:01 PM PDT 24
Finished Jul 10 06:39:06 PM PDT 24
Peak memory 206232 kb
Host smart-b1f5ecec-7ee1-4234-a766-13abb4017cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12262
80634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1226280634
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3575911369
Short name T88
Test name
Test status
Simulation time 161730019 ps
CPU time 0.83 seconds
Started Jul 10 06:38:53 PM PDT 24
Finished Jul 10 06:38:57 PM PDT 24
Peak memory 206384 kb
Host smart-a7f817d2-a075-496f-a9ac-eae35cbae7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
11369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3575911369
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3495375266
Short name T1364
Test name
Test status
Simulation time 160290088 ps
CPU time 0.82 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:38:59 PM PDT 24
Peak memory 206284 kb
Host smart-1e06eb88-bea2-4d3a-bfdc-78dd439647ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34953
75266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3495375266
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2312965315
Short name T1050
Test name
Test status
Simulation time 150091665 ps
CPU time 0.8 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:00 PM PDT 24
Peak memory 206384 kb
Host smart-69509048-ca72-4ce3-95b0-454a3b6133ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23129
65315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2312965315
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3303389523
Short name T967
Test name
Test status
Simulation time 189834135 ps
CPU time 0.87 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:38:59 PM PDT 24
Peak memory 206392 kb
Host smart-4b7fd79b-3f2e-4892-917a-d15206f436ac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3303389523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3303389523
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.490565029
Short name T1162
Test name
Test status
Simulation time 221223384 ps
CPU time 0.91 seconds
Started Jul 10 06:39:00 PM PDT 24
Finished Jul 10 06:39:05 PM PDT 24
Peak memory 206384 kb
Host smart-d83dce9d-595c-4ec0-bbb1-17df313aba99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49056
5029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.490565029
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1437476934
Short name T1936
Test name
Test status
Simulation time 139343571 ps
CPU time 0.82 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:01 PM PDT 24
Peak memory 206424 kb
Host smart-d59cf12e-1673-4362-9aed-6b705cc0ae66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14374
76934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1437476934
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1222702397
Short name T2074
Test name
Test status
Simulation time 31098681 ps
CPU time 0.66 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:00 PM PDT 24
Peak memory 206384 kb
Host smart-b768b086-069f-4b93-950b-8b8d90da4355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12227
02397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1222702397
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.933463350
Short name T1017
Test name
Test status
Simulation time 20871413121 ps
CPU time 44.1 seconds
Started Jul 10 06:38:59 PM PDT 24
Finished Jul 10 06:39:47 PM PDT 24
Peak memory 206744 kb
Host smart-0b40d19b-4a69-423d-9a4a-82fe52656947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93346
3350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.933463350
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1233956456
Short name T526
Test name
Test status
Simulation time 177378815 ps
CPU time 0.87 seconds
Started Jul 10 06:38:59 PM PDT 24
Finished Jul 10 06:39:04 PM PDT 24
Peak memory 206384 kb
Host smart-0ef5f021-a995-44ef-83d9-6df6d6e97124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12339
56456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1233956456
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.664825488
Short name T2329
Test name
Test status
Simulation time 195017680 ps
CPU time 0.88 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:00 PM PDT 24
Peak memory 206312 kb
Host smart-310c1447-6172-48b5-91a2-172381733f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66482
5488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.664825488
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1032039718
Short name T913
Test name
Test status
Simulation time 11630523748 ps
CPU time 53.49 seconds
Started Jul 10 06:38:56 PM PDT 24
Finished Jul 10 06:39:53 PM PDT 24
Peak memory 206584 kb
Host smart-2e828c04-d03a-4b74-b764-c3937f5ad146
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1032039718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1032039718
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.50560327
Short name T174
Test name
Test status
Simulation time 9542069304 ps
CPU time 66.63 seconds
Started Jul 10 06:39:02 PM PDT 24
Finished Jul 10 06:40:13 PM PDT 24
Peak memory 206768 kb
Host smart-ac947f7b-609a-49b1-a6fe-028f004d3fc1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=50560327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.50560327
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1365209952
Short name T1058
Test name
Test status
Simulation time 16184256031 ps
CPU time 123.96 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:41:12 PM PDT 24
Peak memory 206668 kb
Host smart-df05ac7d-c166-4402-b73e-2ba3044d2558
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1365209952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1365209952
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3684734037
Short name T2459
Test name
Test status
Simulation time 233445211 ps
CPU time 0.93 seconds
Started Jul 10 06:38:55 PM PDT 24
Finished Jul 10 06:38:58 PM PDT 24
Peak memory 206400 kb
Host smart-7ccb29f3-3ea2-4713-ab99-a67b3c68e04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36847
34037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3684734037
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2741150627
Short name T1801
Test name
Test status
Simulation time 179248080 ps
CPU time 0.85 seconds
Started Jul 10 06:38:58 PM PDT 24
Finished Jul 10 06:39:02 PM PDT 24
Peak memory 206380 kb
Host smart-348e4522-8240-413e-8004-075b712b11fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27411
50627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2741150627
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2688413558
Short name T840
Test name
Test status
Simulation time 169184480 ps
CPU time 0.79 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:39:09 PM PDT 24
Peak memory 206368 kb
Host smart-80474b8e-c64f-46c4-b51e-797bab5dc29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26884
13558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2688413558
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2753886595
Short name T78
Test name
Test status
Simulation time 183096222 ps
CPU time 0.83 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:09 PM PDT 24
Peak memory 206392 kb
Host smart-e482f558-8891-4efd-8444-a9e79b0f6207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27538
86595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2753886595
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1043787363
Short name T193
Test name
Test status
Simulation time 243822705 ps
CPU time 1.05 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:10 PM PDT 24
Peak memory 224240 kb
Host smart-85a9d7f1-4c3f-41dc-b7e0-a89b00cba540
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1043787363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1043787363
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.2828236746
Short name T2214
Test name
Test status
Simulation time 386402575 ps
CPU time 1.44 seconds
Started Jul 10 06:39:06 PM PDT 24
Finished Jul 10 06:39:13 PM PDT 24
Peak memory 205892 kb
Host smart-765b99b6-93a2-410f-8c96-7ecd51d8ba12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28282
36746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.2828236746
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3722582410
Short name T2524
Test name
Test status
Simulation time 163386864 ps
CPU time 0.84 seconds
Started Jul 10 06:39:06 PM PDT 24
Finished Jul 10 06:39:12 PM PDT 24
Peak memory 205868 kb
Host smart-4ce59bdc-bba7-4556-9141-76570e902746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37225
82410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3722582410
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.961238078
Short name T435
Test name
Test status
Simulation time 200605567 ps
CPU time 0.82 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:10 PM PDT 24
Peak memory 206392 kb
Host smart-e38cc92c-56fa-4d98-ae32-85206ddd83fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96123
8078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.961238078
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1034075162
Short name T2242
Test name
Test status
Simulation time 152670386 ps
CPU time 0.92 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:09 PM PDT 24
Peak memory 206356 kb
Host smart-1e643bb3-8265-4786-b376-c99287f9828f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340
75162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1034075162
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2295434161
Short name T755
Test name
Test status
Simulation time 191441947 ps
CPU time 0.87 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:09 PM PDT 24
Peak memory 206388 kb
Host smart-ec8b8d6d-a942-426e-bd4b-e8712be2b94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22954
34161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2295434161
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2432935771
Short name T466
Test name
Test status
Simulation time 3598552833 ps
CPU time 106.54 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:40:55 PM PDT 24
Peak memory 206836 kb
Host smart-f0b000ba-e842-479f-bad5-53563dec6007
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2432935771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2432935771
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1351890376
Short name T2096
Test name
Test status
Simulation time 144806934 ps
CPU time 0.79 seconds
Started Jul 10 06:39:02 PM PDT 24
Finished Jul 10 06:39:07 PM PDT 24
Peak memory 206384 kb
Host smart-6674b055-b3e0-4f65-9cf1-5c8a918451b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13518
90376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1351890376
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3882037357
Short name T1982
Test name
Test status
Simulation time 182284320 ps
CPU time 0.79 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:39:09 PM PDT 24
Peak memory 206372 kb
Host smart-9c96632a-340e-436a-903c-729226e1e7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
37357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3882037357
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.826852394
Short name T1731
Test name
Test status
Simulation time 739443290 ps
CPU time 1.74 seconds
Started Jul 10 06:39:02 PM PDT 24
Finished Jul 10 06:39:08 PM PDT 24
Peak memory 206636 kb
Host smart-c423d303-b1e6-4fe7-8b56-e91eb8eda510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82685
2394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.826852394
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.253928163
Short name T210
Test name
Test status
Simulation time 5225214881 ps
CPU time 36.46 seconds
Started Jul 10 06:39:06 PM PDT 24
Finished Jul 10 06:39:48 PM PDT 24
Peak memory 206652 kb
Host smart-19fb28fe-a093-452c-a9c0-bc6868daf823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25392
8163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.253928163
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.238278110
Short name T2521
Test name
Test status
Simulation time 19004233383 ps
CPU time 141.37 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:41:30 PM PDT 24
Peak memory 206696 kb
Host smart-7a58c1fb-8ce8-484e-90d8-515459e46848
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=238278110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.238278110
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1543265549
Short name T2439
Test name
Test status
Simulation time 3615275286 ps
CPU time 4.82 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:41:03 PM PDT 24
Peak memory 206440 kb
Host smart-b809411e-4530-485e-88f8-d22222bb6efe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1543265549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1543265549
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2127928098
Short name T474
Test name
Test status
Simulation time 13387960970 ps
CPU time 12.2 seconds
Started Jul 10 06:40:51 PM PDT 24
Finished Jul 10 06:41:08 PM PDT 24
Peak memory 206460 kb
Host smart-d30e5995-5209-496d-b797-a71a435ddac3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2127928098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2127928098
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3471954910
Short name T807
Test name
Test status
Simulation time 23372125381 ps
CPU time 24.72 seconds
Started Jul 10 06:41:02 PM PDT 24
Finished Jul 10 06:41:33 PM PDT 24
Peak memory 206472 kb
Host smart-1aa99bbb-a66f-45a3-a228-a0c12ef31c73
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3471954910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.3471954910
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2525345912
Short name T2290
Test name
Test status
Simulation time 181160880 ps
CPU time 0.85 seconds
Started Jul 10 06:40:58 PM PDT 24
Finished Jul 10 06:41:04 PM PDT 24
Peak memory 206356 kb
Host smart-240bc20a-2399-46c5-bca5-a6d8896ee12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25253
45912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2525345912
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1459873905
Short name T2541
Test name
Test status
Simulation time 205314450 ps
CPU time 0.89 seconds
Started Jul 10 06:40:58 PM PDT 24
Finished Jul 10 06:41:04 PM PDT 24
Peak memory 206384 kb
Host smart-d26b5748-bbf4-4661-99bb-7323d697cc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14598
73905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1459873905
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3135454775
Short name T2639
Test name
Test status
Simulation time 218468442 ps
CPU time 0.95 seconds
Started Jul 10 06:41:03 PM PDT 24
Finished Jul 10 06:41:10 PM PDT 24
Peak memory 206380 kb
Host smart-0bdb376e-51e6-4f12-ad1f-3e4fc422806e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31354
54775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3135454775
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1864872802
Short name T605
Test name
Test status
Simulation time 1220804608 ps
CPU time 2.71 seconds
Started Jul 10 06:41:00 PM PDT 24
Finished Jul 10 06:41:08 PM PDT 24
Peak memory 206616 kb
Host smart-c1613630-e6bb-4d18-b48e-deee17e1cfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
72802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1864872802
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3781325473
Short name T169
Test name
Test status
Simulation time 23586885587 ps
CPU time 49.82 seconds
Started Jul 10 06:41:01 PM PDT 24
Finished Jul 10 06:41:57 PM PDT 24
Peak memory 206652 kb
Host smart-6e48bcd2-ff40-4ce3-a44a-1d9bae560b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37813
25473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3781325473
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.642211098
Short name T573
Test name
Test status
Simulation time 376648233 ps
CPU time 1.18 seconds
Started Jul 10 06:41:04 PM PDT 24
Finished Jul 10 06:41:12 PM PDT 24
Peak memory 206384 kb
Host smart-ef0d286c-644c-496a-8c1b-fcd172465385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64221
1098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.642211098
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2990777786
Short name T1591
Test name
Test status
Simulation time 159310169 ps
CPU time 0.78 seconds
Started Jul 10 06:41:01 PM PDT 24
Finished Jul 10 06:41:08 PM PDT 24
Peak memory 206328 kb
Host smart-4b90d381-3ebc-4bd7-8f19-35c2f56a0213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29907
77786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2990777786
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3202233927
Short name T365
Test name
Test status
Simulation time 39093875 ps
CPU time 0.68 seconds
Started Jul 10 06:41:02 PM PDT 24
Finished Jul 10 06:41:09 PM PDT 24
Peak memory 206376 kb
Host smart-1d362d12-2658-440a-9a87-da659f285ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
33927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3202233927
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2349485012
Short name T2585
Test name
Test status
Simulation time 959564893 ps
CPU time 2.24 seconds
Started Jul 10 06:41:00 PM PDT 24
Finished Jul 10 06:41:08 PM PDT 24
Peak memory 206580 kb
Host smart-10a7d1d8-09a7-4cf5-b9b5-b0140dd1bfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
85012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2349485012
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1275032435
Short name T1191
Test name
Test status
Simulation time 324217351 ps
CPU time 2.13 seconds
Started Jul 10 06:41:03 PM PDT 24
Finished Jul 10 06:41:12 PM PDT 24
Peak memory 206528 kb
Host smart-6ae7597c-6d3b-4d61-b052-199fabdc9b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12750
32435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1275032435
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3827284200
Short name T620
Test name
Test status
Simulation time 232976360 ps
CPU time 0.9 seconds
Started Jul 10 06:40:59 PM PDT 24
Finished Jul 10 06:41:05 PM PDT 24
Peak memory 206380 kb
Host smart-4acf51c2-b33e-4269-bf41-9ff34574d108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38272
84200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3827284200
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2062264643
Short name T1871
Test name
Test status
Simulation time 140289518 ps
CPU time 0.77 seconds
Started Jul 10 06:40:59 PM PDT 24
Finished Jul 10 06:41:06 PM PDT 24
Peak memory 206376 kb
Host smart-17a2987d-402c-472f-b74a-dcbfed2c3fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
64643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2062264643
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1232004510
Short name T86
Test name
Test status
Simulation time 208680481 ps
CPU time 0.94 seconds
Started Jul 10 06:41:02 PM PDT 24
Finished Jul 10 06:41:09 PM PDT 24
Peak memory 206376 kb
Host smart-c640af01-637a-409e-b576-f38acc977c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12320
04510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1232004510
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.373911561
Short name T1380
Test name
Test status
Simulation time 8301466042 ps
CPU time 78.93 seconds
Started Jul 10 06:41:00 PM PDT 24
Finished Jul 10 06:42:25 PM PDT 24
Peak memory 206656 kb
Host smart-e1402585-1629-4792-9a4e-c87819de53a7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=373911561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.373911561
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1370216998
Short name T823
Test name
Test status
Simulation time 9829584606 ps
CPU time 85.94 seconds
Started Jul 10 06:41:01 PM PDT 24
Finished Jul 10 06:42:33 PM PDT 24
Peak memory 206668 kb
Host smart-725ec922-78ba-495a-b787-aff2016d4d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13702
16998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1370216998
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.500628830
Short name T2478
Test name
Test status
Simulation time 250341070 ps
CPU time 0.95 seconds
Started Jul 10 06:40:59 PM PDT 24
Finished Jul 10 06:41:06 PM PDT 24
Peak memory 206344 kb
Host smart-a5639b6b-28f4-4c3d-bd8d-69ddcfbb2438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50062
8830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.500628830
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1173868773
Short name T209
Test name
Test status
Simulation time 23287751088 ps
CPU time 22.21 seconds
Started Jul 10 06:40:59 PM PDT 24
Finished Jul 10 06:41:27 PM PDT 24
Peak memory 206428 kb
Host smart-07a04343-2d1e-4f7d-9c85-494aa1828a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11738
68773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1173868773
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1087489798
Short name T323
Test name
Test status
Simulation time 3318105379 ps
CPU time 3.98 seconds
Started Jul 10 06:40:59 PM PDT 24
Finished Jul 10 06:41:09 PM PDT 24
Peak memory 206444 kb
Host smart-318e118f-05cf-4717-b033-97a455ed53e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
89798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1087489798
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.968426710
Short name T1163
Test name
Test status
Simulation time 8056677373 ps
CPU time 58.36 seconds
Started Jul 10 06:41:01 PM PDT 24
Finished Jul 10 06:42:06 PM PDT 24
Peak memory 206720 kb
Host smart-172fdd42-5082-4f38-bf4c-af3a78885f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96842
6710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.968426710
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1102706136
Short name T678
Test name
Test status
Simulation time 5379810276 ps
CPU time 40.25 seconds
Started Jul 10 06:40:59 PM PDT 24
Finished Jul 10 06:41:45 PM PDT 24
Peak memory 206680 kb
Host smart-b268ac23-b19d-4b6a-944c-cf966f171d03
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1102706136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1102706136
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.3988120000
Short name T1968
Test name
Test status
Simulation time 242157127 ps
CPU time 0.9 seconds
Started Jul 10 06:40:59 PM PDT 24
Finished Jul 10 06:41:06 PM PDT 24
Peak memory 206304 kb
Host smart-8a0c32dd-1c15-4cfa-bf24-9a20a150eeab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3988120000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.3988120000
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2158992845
Short name T1881
Test name
Test status
Simulation time 228123083 ps
CPU time 0.88 seconds
Started Jul 10 06:41:00 PM PDT 24
Finished Jul 10 06:41:07 PM PDT 24
Peak memory 206364 kb
Host smart-68033d7a-aef6-4ede-9095-1ac7817c9862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21589
92845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2158992845
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1325109437
Short name T918
Test name
Test status
Simulation time 4138960425 ps
CPU time 111.54 seconds
Started Jul 10 06:40:59 PM PDT 24
Finished Jul 10 06:42:57 PM PDT 24
Peak memory 206668 kb
Host smart-00f775b3-53d2-4a2e-a59b-839690529ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13251
09437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1325109437
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.4071770482
Short name T2113
Test name
Test status
Simulation time 6627161920 ps
CPU time 61.3 seconds
Started Jul 10 06:41:04 PM PDT 24
Finished Jul 10 06:42:12 PM PDT 24
Peak memory 206680 kb
Host smart-d19b9002-ba79-4ebc-85f0-a556cd24e4ea
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4071770482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.4071770482
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3944091938
Short name T2130
Test name
Test status
Simulation time 166223392 ps
CPU time 0.92 seconds
Started Jul 10 06:41:01 PM PDT 24
Finished Jul 10 06:41:08 PM PDT 24
Peak memory 206392 kb
Host smart-587bc72c-5b96-4ee2-b80d-d97eba030837
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3944091938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3944091938
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3306722671
Short name T316
Test name
Test status
Simulation time 159386548 ps
CPU time 0.76 seconds
Started Jul 10 06:41:03 PM PDT 24
Finished Jul 10 06:41:11 PM PDT 24
Peak memory 206284 kb
Host smart-81e72b1b-97d4-4214-8ec4-1bfa3281fecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33067
22671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3306722671
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2228890200
Short name T137
Test name
Test status
Simulation time 203423578 ps
CPU time 0.86 seconds
Started Jul 10 06:41:00 PM PDT 24
Finished Jul 10 06:41:07 PM PDT 24
Peak memory 206356 kb
Host smart-4f8e9bd4-eff7-4d03-bd29-f1696b5e6d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22288
90200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2228890200
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2585217782
Short name T1393
Test name
Test status
Simulation time 227621157 ps
CPU time 0.88 seconds
Started Jul 10 06:41:00 PM PDT 24
Finished Jul 10 06:41:06 PM PDT 24
Peak memory 206372 kb
Host smart-fdf71ef3-352e-4d06-81b6-023f35052d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
17782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2585217782
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3978893084
Short name T1772
Test name
Test status
Simulation time 187631757 ps
CPU time 0.85 seconds
Started Jul 10 06:41:11 PM PDT 24
Finished Jul 10 06:41:18 PM PDT 24
Peak memory 206352 kb
Host smart-ab52311b-df36-4a89-b60c-87ddd250c972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39788
93084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3978893084
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2469467718
Short name T2340
Test name
Test status
Simulation time 197059848 ps
CPU time 0.85 seconds
Started Jul 10 06:41:09 PM PDT 24
Finished Jul 10 06:41:16 PM PDT 24
Peak memory 206392 kb
Host smart-bbd3497a-094b-40a8-848c-425db345c762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24694
67718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2469467718
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.781605482
Short name T1176
Test name
Test status
Simulation time 169260254 ps
CPU time 0.83 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:15 PM PDT 24
Peak memory 206380 kb
Host smart-896d9e4d-2390-40e4-bda1-c135c5c8eb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78160
5482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.781605482
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1989758260
Short name T1594
Test name
Test status
Simulation time 214684438 ps
CPU time 0.92 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:14 PM PDT 24
Peak memory 206396 kb
Host smart-2fe0cb73-3791-4ca1-bd7c-6d188a08bd48
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1989758260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1989758260
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1866808085
Short name T1279
Test name
Test status
Simulation time 150306625 ps
CPU time 0.76 seconds
Started Jul 10 06:41:12 PM PDT 24
Finished Jul 10 06:41:19 PM PDT 24
Peak memory 206396 kb
Host smart-376f2702-48f9-4a54-9f68-753854f449c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18668
08085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1866808085
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1945777599
Short name T1305
Test name
Test status
Simulation time 41935231 ps
CPU time 0.7 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:14 PM PDT 24
Peak memory 206376 kb
Host smart-3791d55c-2b49-46a3-8228-037e2faaa886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19457
77599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1945777599
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.952112959
Short name T908
Test name
Test status
Simulation time 17414960224 ps
CPU time 43.16 seconds
Started Jul 10 06:41:10 PM PDT 24
Finished Jul 10 06:42:00 PM PDT 24
Peak memory 214868 kb
Host smart-1ad624f9-bf9c-4513-a247-0a9a9773b2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95211
2959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.952112959
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.974004043
Short name T569
Test name
Test status
Simulation time 192343482 ps
CPU time 0.91 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:15 PM PDT 24
Peak memory 206372 kb
Host smart-113bde0d-6fe7-4c1b-938f-56be78e4b19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97400
4043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.974004043
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3736633275
Short name T593
Test name
Test status
Simulation time 214925262 ps
CPU time 0.98 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:14 PM PDT 24
Peak memory 206372 kb
Host smart-4e118d0c-5ecf-484f-9782-beaffc670998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37366
33275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3736633275
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.658996984
Short name T350
Test name
Test status
Simulation time 195652566 ps
CPU time 0.81 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:14 PM PDT 24
Peak memory 206332 kb
Host smart-8594bb6e-a45a-412e-8c0a-92d714c99efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65899
6984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.658996984
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.420330546
Short name T2633
Test name
Test status
Simulation time 198692061 ps
CPU time 0.83 seconds
Started Jul 10 06:41:08 PM PDT 24
Finished Jul 10 06:41:15 PM PDT 24
Peak memory 206368 kb
Host smart-7196afb8-db6d-49d5-8bf7-13701c2e1ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42033
0546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.420330546
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1056518595
Short name T2532
Test name
Test status
Simulation time 187395246 ps
CPU time 0.88 seconds
Started Jul 10 06:41:09 PM PDT 24
Finished Jul 10 06:41:16 PM PDT 24
Peak memory 206392 kb
Host smart-33b58352-5ecf-4e63-8085-e171b52acf70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10565
18595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1056518595
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1206443153
Short name T703
Test name
Test status
Simulation time 152471482 ps
CPU time 0.78 seconds
Started Jul 10 06:41:08 PM PDT 24
Finished Jul 10 06:41:16 PM PDT 24
Peak memory 206388 kb
Host smart-8916480a-b3c4-49e4-b551-1adcb5a5c7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12064
43153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1206443153
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1006628741
Short name T1958
Test name
Test status
Simulation time 159570174 ps
CPU time 0.77 seconds
Started Jul 10 06:41:10 PM PDT 24
Finished Jul 10 06:41:18 PM PDT 24
Peak memory 206084 kb
Host smart-f6993197-d667-4a0f-b017-7a7c5d7fddc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066
28741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1006628741
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.239450578
Short name T1156
Test name
Test status
Simulation time 272217308 ps
CPU time 0.99 seconds
Started Jul 10 06:41:05 PM PDT 24
Finished Jul 10 06:41:13 PM PDT 24
Peak memory 206376 kb
Host smart-538dfd0b-e42b-4c1d-a19c-deeed3b2a5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23945
0578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.239450578
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3000532240
Short name T2464
Test name
Test status
Simulation time 4468530052 ps
CPU time 44.42 seconds
Started Jul 10 06:41:13 PM PDT 24
Finished Jul 10 06:42:03 PM PDT 24
Peak memory 206628 kb
Host smart-d670b180-0e80-4067-9c5f-c24faa64ce9b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3000532240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3000532240
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3879962329
Short name T2369
Test name
Test status
Simulation time 172565027 ps
CPU time 0.85 seconds
Started Jul 10 06:41:12 PM PDT 24
Finished Jul 10 06:41:19 PM PDT 24
Peak memory 206368 kb
Host smart-8ae9b11a-4be4-42d5-8bbd-2f0a9dd03121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38799
62329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3879962329
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1618186091
Short name T309
Test name
Test status
Simulation time 173527549 ps
CPU time 0.78 seconds
Started Jul 10 06:41:08 PM PDT 24
Finished Jul 10 06:41:15 PM PDT 24
Peak memory 206356 kb
Host smart-2afff446-a6bf-4ffa-8fbe-52c8961ec720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16181
86091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1618186091
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3066765700
Short name T2727
Test name
Test status
Simulation time 1244460743 ps
CPU time 2.82 seconds
Started Jul 10 06:41:08 PM PDT 24
Finished Jul 10 06:41:17 PM PDT 24
Peak memory 206624 kb
Host smart-90cd3bf5-cdb2-4a63-89c9-6d1200bb714e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30667
65700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3066765700
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1204431587
Short name T2388
Test name
Test status
Simulation time 3926918384 ps
CPU time 38.18 seconds
Started Jul 10 06:41:08 PM PDT 24
Finished Jul 10 06:41:53 PM PDT 24
Peak memory 206708 kb
Host smart-8ab48afe-7cb1-4c6c-ab20-c058c22909de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12044
31587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1204431587
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.2545419429
Short name T924
Test name
Test status
Simulation time 47084451 ps
CPU time 0.64 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:41:27 PM PDT 24
Peak memory 206416 kb
Host smart-3db12534-4641-4bbc-9fa5-479cfb6756cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2545419429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.2545419429
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.308289909
Short name T950
Test name
Test status
Simulation time 3654515912 ps
CPU time 4.68 seconds
Started Jul 10 06:41:10 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206712 kb
Host smart-0aea086a-0538-484d-84b7-01274037fcf0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=308289909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.308289909
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1508004962
Short name T1506
Test name
Test status
Simulation time 13402260886 ps
CPU time 12.71 seconds
Started Jul 10 06:41:09 PM PDT 24
Finished Jul 10 06:41:29 PM PDT 24
Peak memory 206448 kb
Host smart-9c84724b-f8e2-4178-8f06-31eecbf98959
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1508004962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1508004962
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3325328514
Short name T1520
Test name
Test status
Simulation time 23363978675 ps
CPU time 23.36 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:36 PM PDT 24
Peak memory 206640 kb
Host smart-3c7a1250-a2f0-4e70-9aba-0f8bcbdb5481
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3325328514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3325328514
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3457258976
Short name T308
Test name
Test status
Simulation time 155910351 ps
CPU time 0.74 seconds
Started Jul 10 06:41:09 PM PDT 24
Finished Jul 10 06:41:16 PM PDT 24
Peak memory 206372 kb
Host smart-a75dab0e-e05f-417b-91c8-13b0941337ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34572
58976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3457258976
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2756338304
Short name T1529
Test name
Test status
Simulation time 169486991 ps
CPU time 0.87 seconds
Started Jul 10 06:41:08 PM PDT 24
Finished Jul 10 06:41:16 PM PDT 24
Peak memory 206392 kb
Host smart-19baa7b9-3407-438a-8ae3-2fa4ede7a24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
38304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2756338304
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.841898128
Short name T1309
Test name
Test status
Simulation time 448994055 ps
CPU time 1.49 seconds
Started Jul 10 06:41:09 PM PDT 24
Finished Jul 10 06:41:17 PM PDT 24
Peak memory 206384 kb
Host smart-8bdc4f0a-6e54-486d-b2f3-bd5ff7c353c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84189
8128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.841898128
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1882961008
Short name T2511
Test name
Test status
Simulation time 811521460 ps
CPU time 1.92 seconds
Started Jul 10 06:41:10 PM PDT 24
Finished Jul 10 06:41:18 PM PDT 24
Peak memory 206616 kb
Host smart-86ffe840-fdf1-4fb2-a83a-bb8fc57f2d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18829
61008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1882961008
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3674771310
Short name T1441
Test name
Test status
Simulation time 8489610197 ps
CPU time 15.79 seconds
Started Jul 10 06:41:08 PM PDT 24
Finished Jul 10 06:41:30 PM PDT 24
Peak memory 206644 kb
Host smart-5c5dfff8-dc88-4592-9282-a726c3757ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747
71310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3674771310
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.322859445
Short name T2601
Test name
Test status
Simulation time 449141758 ps
CPU time 1.33 seconds
Started Jul 10 06:41:10 PM PDT 24
Finished Jul 10 06:41:18 PM PDT 24
Peak memory 206380 kb
Host smart-df6714b1-f385-489f-91ee-d40820cf587f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32285
9445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.322859445
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.305725037
Short name T2615
Test name
Test status
Simulation time 150417085 ps
CPU time 0.82 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:13 PM PDT 24
Peak memory 206404 kb
Host smart-b74e7040-7704-4595-b85b-f757f01aaa17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30572
5037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.305725037
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.768979765
Short name T1851
Test name
Test status
Simulation time 67267180 ps
CPU time 0.67 seconds
Started Jul 10 06:41:08 PM PDT 24
Finished Jul 10 06:41:15 PM PDT 24
Peak memory 206380 kb
Host smart-130fc1a3-9d7b-48d8-8485-1c68143b16b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76897
9765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.768979765
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.29221626
Short name T1233
Test name
Test status
Simulation time 880165483 ps
CPU time 2.35 seconds
Started Jul 10 06:41:09 PM PDT 24
Finished Jul 10 06:41:18 PM PDT 24
Peak memory 206600 kb
Host smart-ea8df8c7-3a79-476f-83be-89f24bcce033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29221
626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.29221626
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1398839078
Short name T1078
Test name
Test status
Simulation time 306620413 ps
CPU time 1.63 seconds
Started Jul 10 06:41:07 PM PDT 24
Finished Jul 10 06:41:15 PM PDT 24
Peak memory 206640 kb
Host smart-6f81a94d-a810-4381-afb5-7c698e5557d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13988
39078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1398839078
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2559778012
Short name T1718
Test name
Test status
Simulation time 206021700 ps
CPU time 0.83 seconds
Started Jul 10 06:41:18 PM PDT 24
Finished Jul 10 06:41:23 PM PDT 24
Peak memory 206356 kb
Host smart-93255c71-07d0-4093-b96f-657d6a329ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25597
78012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2559778012
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1367599501
Short name T685
Test name
Test status
Simulation time 143827179 ps
CPU time 0.75 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206376 kb
Host smart-a4b58365-49a4-4866-9cb3-08bf3176a251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13675
99501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1367599501
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1819535687
Short name T1477
Test name
Test status
Simulation time 163592138 ps
CPU time 0.87 seconds
Started Jul 10 06:41:13 PM PDT 24
Finished Jul 10 06:41:20 PM PDT 24
Peak memory 206376 kb
Host smart-470e1db0-3a25-4923-b79e-44a87ddfeb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
35687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1819535687
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3561493693
Short name T2094
Test name
Test status
Simulation time 183511681 ps
CPU time 0.85 seconds
Started Jul 10 06:41:16 PM PDT 24
Finished Jul 10 06:41:22 PM PDT 24
Peak memory 206372 kb
Host smart-7d107569-a2d5-4572-a76e-a3025cd1da55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35614
93693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3561493693
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.4066812060
Short name T1223
Test name
Test status
Simulation time 23299204343 ps
CPU time 22.45 seconds
Started Jul 10 06:41:16 PM PDT 24
Finished Jul 10 06:41:44 PM PDT 24
Peak memory 206420 kb
Host smart-ced982d7-4b9e-4319-b53d-59ff4dea16c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40668
12060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.4066812060
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2768853588
Short name T1153
Test name
Test status
Simulation time 3313147764 ps
CPU time 3.6 seconds
Started Jul 10 06:41:15 PM PDT 24
Finished Jul 10 06:41:24 PM PDT 24
Peak memory 206428 kb
Host smart-80579a97-9b75-4144-a2b7-6dd363be249f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27688
53588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2768853588
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2676296205
Short name T2506
Test name
Test status
Simulation time 10910306147 ps
CPU time 81.52 seconds
Started Jul 10 06:41:16 PM PDT 24
Finished Jul 10 06:42:43 PM PDT 24
Peak memory 206720 kb
Host smart-0b710118-e105-420d-8e54-d9451cda3a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26762
96205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2676296205
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2118522812
Short name T2620
Test name
Test status
Simulation time 5531226683 ps
CPU time 150.48 seconds
Started Jul 10 06:41:17 PM PDT 24
Finished Jul 10 06:43:52 PM PDT 24
Peak memory 206700 kb
Host smart-a94022f2-bf82-4f04-b5b2-58e2f2bb5642
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2118522812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2118522812
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2458513524
Short name T2568
Test name
Test status
Simulation time 239430215 ps
CPU time 0.93 seconds
Started Jul 10 06:41:17 PM PDT 24
Finished Jul 10 06:41:22 PM PDT 24
Peak memory 206408 kb
Host smart-33c7ae23-5917-4eb0-b8b4-68e5994c3e70
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2458513524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2458513524
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1030129938
Short name T1195
Test name
Test status
Simulation time 202185452 ps
CPU time 0.87 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206392 kb
Host smart-8e21c5e8-38c2-4b16-9525-32275ba8c5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10301
29938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1030129938
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2566436275
Short name T1957
Test name
Test status
Simulation time 6367197013 ps
CPU time 182.8 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206644 kb
Host smart-e86634e9-9362-4742-8f8c-6db3df15980f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25664
36275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2566436275
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.433709988
Short name T677
Test name
Test status
Simulation time 7102609926 ps
CPU time 199.48 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:44:39 PM PDT 24
Peak memory 206596 kb
Host smart-e2854ac6-7a9c-456b-8c86-d8b053e06c40
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=433709988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.433709988
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3428883589
Short name T2279
Test name
Test status
Simulation time 164491098 ps
CPU time 0.81 seconds
Started Jul 10 06:41:15 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206372 kb
Host smart-04189200-c54d-4f2e-85cd-18e98ad430e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3428883589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3428883589
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1293101005
Short name T2566
Test name
Test status
Simulation time 149102280 ps
CPU time 0.78 seconds
Started Jul 10 06:41:16 PM PDT 24
Finished Jul 10 06:41:22 PM PDT 24
Peak memory 206380 kb
Host smart-2fae0365-0a78-4fee-841b-e38cad193b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12931
01005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1293101005
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.4212211401
Short name T1372
Test name
Test status
Simulation time 186726972 ps
CPU time 0.87 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206556 kb
Host smart-9c0e4c06-b71a-4386-8ba3-4edfd5baf1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122
11401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.4212211401
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3800181835
Short name T1795
Test name
Test status
Simulation time 167541411 ps
CPU time 0.79 seconds
Started Jul 10 06:41:18 PM PDT 24
Finished Jul 10 06:41:23 PM PDT 24
Peak memory 206364 kb
Host smart-2a95288d-b9a2-4189-8dce-b0211a1bd6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38001
81835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3800181835
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4191484407
Short name T2317
Test name
Test status
Simulation time 192839350 ps
CPU time 0.93 seconds
Started Jul 10 06:41:18 PM PDT 24
Finished Jul 10 06:41:23 PM PDT 24
Peak memory 206364 kb
Host smart-93e52e69-77fb-4b6a-8ee3-dee04e21a827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41914
84407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4191484407
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3190284441
Short name T178
Test name
Test status
Simulation time 146729250 ps
CPU time 0.77 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206376 kb
Host smart-e109e157-07d1-4e56-a140-2c312d63977b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31902
84441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3190284441
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3907882567
Short name T1385
Test name
Test status
Simulation time 259512211 ps
CPU time 0.94 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206380 kb
Host smart-dabc33fe-69cc-457e-a8c3-df35ad69bf0c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3907882567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3907882567
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.4114360757
Short name T1274
Test name
Test status
Simulation time 28999652 ps
CPU time 0.67 seconds
Started Jul 10 06:41:16 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206368 kb
Host smart-0e2c90c7-ea7e-4a67-a806-6a37931deabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41143
60757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.4114360757
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1246485980
Short name T244
Test name
Test status
Simulation time 11203626388 ps
CPU time 26.38 seconds
Started Jul 10 06:41:19 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206656 kb
Host smart-cd8eaf23-10ea-4445-84c7-17f6ede86c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12464
85980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1246485980
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2681600987
Short name T289
Test name
Test status
Simulation time 168946663 ps
CPU time 0.81 seconds
Started Jul 10 06:41:14 PM PDT 24
Finished Jul 10 06:41:21 PM PDT 24
Peak memory 206376 kb
Host smart-215df275-b88e-4d8a-b47b-724698a3953d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26816
00987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2681600987
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2560909227
Short name T818
Test name
Test status
Simulation time 184954957 ps
CPU time 0.83 seconds
Started Jul 10 06:41:16 PM PDT 24
Finished Jul 10 06:41:22 PM PDT 24
Peak memory 206372 kb
Host smart-f43b456a-288a-4d42-bc55-c19fd32e2e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25609
09227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2560909227
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.1753335313
Short name T2115
Test name
Test status
Simulation time 185497174 ps
CPU time 0.82 seconds
Started Jul 10 06:41:24 PM PDT 24
Finished Jul 10 06:41:28 PM PDT 24
Peak memory 206376 kb
Host smart-3b11fcea-1736-4ec9-83f7-e25276a50846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17533
35313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.1753335313
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.227653839
Short name T1897
Test name
Test status
Simulation time 152814916 ps
CPU time 0.79 seconds
Started Jul 10 06:41:24 PM PDT 24
Finished Jul 10 06:41:28 PM PDT 24
Peak memory 206552 kb
Host smart-fff29d33-fe92-4683-8d5a-6a6ce313757a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22765
3839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.227653839
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.51238322
Short name T2220
Test name
Test status
Simulation time 139868870 ps
CPU time 0.77 seconds
Started Jul 10 06:41:21 PM PDT 24
Finished Jul 10 06:41:25 PM PDT 24
Peak memory 206360 kb
Host smart-97b152e6-efb9-46f1-8d94-8dcfd388176f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51238
322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.51238322
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3392876954
Short name T1643
Test name
Test status
Simulation time 152796050 ps
CPU time 0.76 seconds
Started Jul 10 06:41:22 PM PDT 24
Finished Jul 10 06:41:26 PM PDT 24
Peak memory 206272 kb
Host smart-b0ee8f24-819c-4f5b-8b46-e96b86062cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33928
76954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3392876954
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2570635568
Short name T1464
Test name
Test status
Simulation time 189719610 ps
CPU time 0.82 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:41:27 PM PDT 24
Peak memory 206380 kb
Host smart-a86b98b9-664d-42df-839e-2f5a573a4960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706
35568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2570635568
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.4250248271
Short name T1084
Test name
Test status
Simulation time 232102958 ps
CPU time 0.98 seconds
Started Jul 10 06:41:22 PM PDT 24
Finished Jul 10 06:41:26 PM PDT 24
Peak memory 206356 kb
Host smart-66f64d92-229e-46fc-9e85-00fee0c27ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42502
48271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.4250248271
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.347475088
Short name T665
Test name
Test status
Simulation time 4062047560 ps
CPU time 115.02 seconds
Started Jul 10 06:41:25 PM PDT 24
Finished Jul 10 06:43:25 PM PDT 24
Peak memory 206628 kb
Host smart-68791914-56f5-4b32-b897-005eb6ce9ded
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=347475088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.347475088
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.4130795252
Short name T2453
Test name
Test status
Simulation time 182560935 ps
CPU time 0.82 seconds
Started Jul 10 06:41:22 PM PDT 24
Finished Jul 10 06:41:26 PM PDT 24
Peak memory 206396 kb
Host smart-3514937e-8c8a-4dc3-95c6-75c7dca0bd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41307
95252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.4130795252
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3387943557
Short name T1500
Test name
Test status
Simulation time 170782666 ps
CPU time 0.79 seconds
Started Jul 10 06:41:22 PM PDT 24
Finished Jul 10 06:41:26 PM PDT 24
Peak memory 206376 kb
Host smart-a2a99ea6-67db-43c6-8acf-6fad59fa7ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33879
43557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3387943557
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.2856416845
Short name T542
Test name
Test status
Simulation time 1176955519 ps
CPU time 2.46 seconds
Started Jul 10 06:41:24 PM PDT 24
Finished Jul 10 06:41:30 PM PDT 24
Peak memory 206632 kb
Host smart-17596071-78ae-48f5-acf1-c93d03604404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28564
16845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.2856416845
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3812029444
Short name T1612
Test name
Test status
Simulation time 3863391456 ps
CPU time 30.45 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:41:57 PM PDT 24
Peak memory 206692 kb
Host smart-a94b476f-5ee0-41db-861e-850295c951c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38120
29444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3812029444
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.3756816426
Short name T1949
Test name
Test status
Simulation time 44793645 ps
CPU time 0.72 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:36 PM PDT 24
Peak memory 206440 kb
Host smart-c5c91005-2196-4f28-8212-c0428e66ffcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3756816426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3756816426
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1176226313
Short name T777
Test name
Test status
Simulation time 4111374472 ps
CPU time 4.77 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:41:31 PM PDT 24
Peak memory 206428 kb
Host smart-8744b248-1354-4508-b92c-6a765c0216b9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1176226313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.1176226313
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.788342908
Short name T1840
Test name
Test status
Simulation time 13413972882 ps
CPU time 13.57 seconds
Started Jul 10 06:41:24 PM PDT 24
Finished Jul 10 06:41:41 PM PDT 24
Peak memory 206672 kb
Host smart-b2e0e41d-7c57-4fbe-af6e-239efa0450bd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=788342908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.788342908
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1171870484
Short name T2148
Test name
Test status
Simulation time 23461370277 ps
CPU time 23.69 seconds
Started Jul 10 06:41:32 PM PDT 24
Finished Jul 10 06:42:02 PM PDT 24
Peak memory 206732 kb
Host smart-3261aeb8-efcd-4b73-aa51-74879f766111
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1171870484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1171870484
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.711499949
Short name T809
Test name
Test status
Simulation time 164754922 ps
CPU time 0.79 seconds
Started Jul 10 06:41:32 PM PDT 24
Finished Jul 10 06:41:39 PM PDT 24
Peak memory 206388 kb
Host smart-d2f31fc9-5986-4dc9-899d-976aec4a724a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71149
9949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.711499949
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3197760118
Short name T2437
Test name
Test status
Simulation time 152393924 ps
CPU time 0.76 seconds
Started Jul 10 06:41:28 PM PDT 24
Finished Jul 10 06:41:34 PM PDT 24
Peak memory 206396 kb
Host smart-d5bafd1e-9c16-4f34-b801-4f5f09fc5b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31977
60118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3197760118
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2316565305
Short name T113
Test name
Test status
Simulation time 392525061 ps
CPU time 1.32 seconds
Started Jul 10 06:41:25 PM PDT 24
Finished Jul 10 06:41:31 PM PDT 24
Peak memory 206380 kb
Host smart-93ecf2d3-2c2c-4ce4-8333-8e37b33076a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23165
65305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2316565305
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.965945748
Short name T62
Test name
Test status
Simulation time 490688416 ps
CPU time 1.4 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:41:28 PM PDT 24
Peak memory 206392 kb
Host smart-a860f714-a46b-4eb2-be2f-73d90fa1cc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96594
5748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.965945748
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3901311080
Short name T171
Test name
Test status
Simulation time 22255102336 ps
CPU time 45.62 seconds
Started Jul 10 06:41:24 PM PDT 24
Finished Jul 10 06:42:13 PM PDT 24
Peak memory 206648 kb
Host smart-77e5a664-9388-4a95-8a40-b4a35d8f5f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39013
11080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3901311080
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3907172358
Short name T2734
Test name
Test status
Simulation time 331182217 ps
CPU time 1.2 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:41:28 PM PDT 24
Peak memory 206392 kb
Host smart-abd3be04-ea78-454d-8de5-53b9f022f498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071
72358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3907172358
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_enable.711546533
Short name T821
Test name
Test status
Simulation time 52029887 ps
CPU time 0.67 seconds
Started Jul 10 06:41:26 PM PDT 24
Finished Jul 10 06:41:31 PM PDT 24
Peak memory 206372 kb
Host smart-f3157a8f-a8a4-4733-925c-5dc480c78b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71154
6533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.711546533
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1196485500
Short name T1545
Test name
Test status
Simulation time 1168424907 ps
CPU time 3.02 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:41:29 PM PDT 24
Peak memory 206660 kb
Host smart-dabcba4d-2d58-4e03-933c-50e161ddad4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11964
85500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1196485500
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3459752667
Short name T2544
Test name
Test status
Simulation time 163772674 ps
CPU time 1.53 seconds
Started Jul 10 06:41:25 PM PDT 24
Finished Jul 10 06:41:32 PM PDT 24
Peak memory 206624 kb
Host smart-75da2dfc-d00b-4dc6-88cf-6787bb76516c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34597
52667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3459752667
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.656002129
Short name T2236
Test name
Test status
Simulation time 178474629 ps
CPU time 0.86 seconds
Started Jul 10 06:41:24 PM PDT 24
Finished Jul 10 06:41:28 PM PDT 24
Peak memory 206388 kb
Host smart-ffa9ff48-37de-414e-9a7a-3fbfd0830604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65600
2129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.656002129
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1389437775
Short name T1146
Test name
Test status
Simulation time 183972162 ps
CPU time 0.82 seconds
Started Jul 10 06:41:25 PM PDT 24
Finished Jul 10 06:41:30 PM PDT 24
Peak memory 206376 kb
Host smart-a871cec2-c231-48e3-848c-b423d547295d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13894
37775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1389437775
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2297456310
Short name T1611
Test name
Test status
Simulation time 218339486 ps
CPU time 0.87 seconds
Started Jul 10 06:41:24 PM PDT 24
Finished Jul 10 06:41:28 PM PDT 24
Peak memory 206392 kb
Host smart-17372bc8-594d-411a-a5ff-5d4743326a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22974
56310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2297456310
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1567053737
Short name T2332
Test name
Test status
Simulation time 5751936608 ps
CPU time 39.98 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:42:06 PM PDT 24
Peak memory 206672 kb
Host smart-8c1b294f-25bf-41ad-8783-b3d7ceee0fcd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1567053737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1567053737
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2268090959
Short name T1835
Test name
Test status
Simulation time 4942336131 ps
CPU time 43.7 seconds
Started Jul 10 06:41:23 PM PDT 24
Finished Jul 10 06:42:11 PM PDT 24
Peak memory 206668 kb
Host smart-b3e15822-e6b5-4f19-a213-652b6fc1b7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22680
90959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2268090959
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.4035630882
Short name T430
Test name
Test status
Simulation time 176020360 ps
CPU time 0.84 seconds
Started Jul 10 06:41:22 PM PDT 24
Finished Jul 10 06:41:26 PM PDT 24
Peak memory 206352 kb
Host smart-fac2e07a-8715-4f98-87e4-8c0d68b77f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40356
30882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.4035630882
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1248477932
Short name T1741
Test name
Test status
Simulation time 23259076112 ps
CPU time 26.77 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:42:01 PM PDT 24
Peak memory 206432 kb
Host smart-ab4b9306-0742-41c6-a62b-ad87f215b35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12484
77932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1248477932
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2554655532
Short name T2573
Test name
Test status
Simulation time 3331999485 ps
CPU time 3.75 seconds
Started Jul 10 06:41:31 PM PDT 24
Finished Jul 10 06:41:41 PM PDT 24
Peak memory 206452 kb
Host smart-bc8fa4bc-1c69-416f-ae4b-73cdf6c7a8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25546
55532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2554655532
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2029961447
Short name T979
Test name
Test status
Simulation time 7717972318 ps
CPU time 54.12 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206720 kb
Host smart-8413bbbd-4215-4375-becd-366bc6237c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20299
61447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2029961447
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.681358759
Short name T587
Test name
Test status
Simulation time 6579298899 ps
CPU time 63.16 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:42:38 PM PDT 24
Peak memory 206584 kb
Host smart-554f1d43-b14c-4bb3-be58-5406fde31fdf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=681358759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.681358759
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2044271298
Short name T349
Test name
Test status
Simulation time 244247436 ps
CPU time 0.96 seconds
Started Jul 10 06:41:28 PM PDT 24
Finished Jul 10 06:41:35 PM PDT 24
Peak memory 206376 kb
Host smart-6bd438a3-acfc-477c-bd34-bfa2661371f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2044271298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2044271298
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1107668784
Short name T1524
Test name
Test status
Simulation time 206111159 ps
CPU time 0.83 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:35 PM PDT 24
Peak memory 206404 kb
Host smart-bddf6191-0141-4d30-a930-40480c5b90e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11076
68784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1107668784
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.3004639381
Short name T398
Test name
Test status
Simulation time 7133211510 ps
CPU time 188.86 seconds
Started Jul 10 06:41:28 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 206668 kb
Host smart-297fd607-83f7-40fd-9038-cbe37b4da215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30046
39381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.3004639381
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.2014450625
Short name T1492
Test name
Test status
Simulation time 4496856327 ps
CPU time 122.68 seconds
Started Jul 10 06:41:30 PM PDT 24
Finished Jul 10 06:43:39 PM PDT 24
Peak memory 206640 kb
Host smart-1f3f5ab5-743f-47df-9659-cc2a62bde608
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2014450625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2014450625
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3459860093
Short name T774
Test name
Test status
Simulation time 149260317 ps
CPU time 0.78 seconds
Started Jul 10 06:41:34 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206380 kb
Host smart-7a6a0477-0863-4ecd-9abc-b848fa6a73f0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3459860093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3459860093
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1360599322
Short name T944
Test name
Test status
Simulation time 145911558 ps
CPU time 0.78 seconds
Started Jul 10 06:41:31 PM PDT 24
Finished Jul 10 06:41:39 PM PDT 24
Peak memory 206380 kb
Host smart-f71355a0-c121-4510-9b62-11fb2e01e9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13605
99322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1360599322
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.6070341
Short name T942
Test name
Test status
Simulation time 247683376 ps
CPU time 0.85 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:34 PM PDT 24
Peak memory 206376 kb
Host smart-05ad970f-8e53-4e5f-8495-f06ff1b17a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60703
41 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.6070341
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1584332462
Short name T311
Test name
Test status
Simulation time 208095605 ps
CPU time 0.89 seconds
Started Jul 10 06:41:33 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206388 kb
Host smart-8a3cb04e-211c-4a92-aad5-2c7317f73564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15843
32462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1584332462
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.346143702
Short name T943
Test name
Test status
Simulation time 183766182 ps
CPU time 0.83 seconds
Started Jul 10 06:41:30 PM PDT 24
Finished Jul 10 06:41:37 PM PDT 24
Peak memory 206372 kb
Host smart-1771bdaa-1d57-43eb-8b24-f61e36b974e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34614
3702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.346143702
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1322900159
Short name T1093
Test name
Test status
Simulation time 196779161 ps
CPU time 0.82 seconds
Started Jul 10 06:41:34 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206396 kb
Host smart-09953309-2936-4add-8803-0c00f6a591f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13229
00159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1322900159
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2110730562
Short name T531
Test name
Test status
Simulation time 250006012 ps
CPU time 0.92 seconds
Started Jul 10 06:41:28 PM PDT 24
Finished Jul 10 06:41:35 PM PDT 24
Peak memory 206380 kb
Host smart-0337617b-7109-4533-a595-393bd4c3be15
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2110730562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2110730562
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2658844526
Short name T439
Test name
Test status
Simulation time 145910368 ps
CPU time 0.77 seconds
Started Jul 10 06:41:34 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206392 kb
Host smart-25a38786-7643-4c93-b866-138c1b5da03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26588
44526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2658844526
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1759311346
Short name T1423
Test name
Test status
Simulation time 36772083 ps
CPU time 0.68 seconds
Started Jul 10 06:41:30 PM PDT 24
Finished Jul 10 06:41:36 PM PDT 24
Peak memory 206376 kb
Host smart-8e953d2d-f44f-41ec-916c-cd60247eb682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17593
11346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1759311346
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1539771516
Short name T2665
Test name
Test status
Simulation time 16480424892 ps
CPU time 42.78 seconds
Started Jul 10 06:41:30 PM PDT 24
Finished Jul 10 06:42:18 PM PDT 24
Peak memory 206684 kb
Host smart-1dd1f529-3522-48c2-bc0e-a3aa8f52d161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15397
71516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1539771516
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2527880556
Short name T2143
Test name
Test status
Simulation time 150888263 ps
CPU time 0.81 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:35 PM PDT 24
Peak memory 206376 kb
Host smart-b7288b14-c698-4f5f-8d39-788f21184f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25278
80556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2527880556
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2235269718
Short name T2081
Test name
Test status
Simulation time 260120313 ps
CPU time 0.93 seconds
Started Jul 10 06:41:28 PM PDT 24
Finished Jul 10 06:41:35 PM PDT 24
Peak memory 206372 kb
Host smart-8624afac-d44a-4ee7-8831-52023273233e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22352
69718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2235269718
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.78804723
Short name T2487
Test name
Test status
Simulation time 245797847 ps
CPU time 0.92 seconds
Started Jul 10 06:41:31 PM PDT 24
Finished Jul 10 06:41:38 PM PDT 24
Peak memory 206384 kb
Host smart-b7b99f6e-4234-4ee4-91d1-1bcc813c35f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78804
723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.78804723
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2646914930
Short name T927
Test name
Test status
Simulation time 154546868 ps
CPU time 0.81 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:36 PM PDT 24
Peak memory 206404 kb
Host smart-9a02a336-6d12-4194-a1d0-55573110667c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
14930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2646914930
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3852705966
Short name T1737
Test name
Test status
Simulation time 191407537 ps
CPU time 0.81 seconds
Started Jul 10 06:41:30 PM PDT 24
Finished Jul 10 06:41:37 PM PDT 24
Peak memory 206372 kb
Host smart-e0c696bf-05b0-4626-87e4-1344ebbfe652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38527
05966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3852705966
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.663231490
Short name T381
Test name
Test status
Simulation time 157154508 ps
CPU time 0.75 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:35 PM PDT 24
Peak memory 206400 kb
Host smart-ddedcca3-9efe-4e86-9373-4904c3aa23b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66323
1490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.663231490
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3265916021
Short name T2455
Test name
Test status
Simulation time 199334439 ps
CPU time 0.83 seconds
Started Jul 10 06:41:34 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206388 kb
Host smart-8d996a6a-0d65-448e-8aee-266169e3b8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32659
16021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3265916021
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3545191292
Short name T1514
Test name
Test status
Simulation time 235733586 ps
CPU time 0.97 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:36 PM PDT 24
Peak memory 206372 kb
Host smart-96a2acdd-ae9d-4bfa-b826-f451a5081988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35451
91292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3545191292
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2611224539
Short name T1073
Test name
Test status
Simulation time 5208623172 ps
CPU time 140.55 seconds
Started Jul 10 06:41:28 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206588 kb
Host smart-b320addb-c666-4e11-94de-035972c02fe5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2611224539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2611224539
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1726627317
Short name T1606
Test name
Test status
Simulation time 190767253 ps
CPU time 0.81 seconds
Started Jul 10 06:41:31 PM PDT 24
Finished Jul 10 06:41:39 PM PDT 24
Peak memory 206384 kb
Host smart-6e970753-85a5-48a1-8fa9-b6339ae01216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17266
27317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1726627317
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2836174981
Short name T2425
Test name
Test status
Simulation time 173571303 ps
CPU time 0.79 seconds
Started Jul 10 06:41:31 PM PDT 24
Finished Jul 10 06:41:38 PM PDT 24
Peak memory 206376 kb
Host smart-f6247dcf-eb4c-4d78-aef4-7ed62b9c0ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
74981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2836174981
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3540977977
Short name T1923
Test name
Test status
Simulation time 1088090902 ps
CPU time 2.54 seconds
Started Jul 10 06:41:33 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206628 kb
Host smart-a1a540c2-41f8-4967-b5ff-00acb80fe541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35409
77977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3540977977
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3604610812
Short name T2508
Test name
Test status
Simulation time 7894114182 ps
CPU time 74.21 seconds
Started Jul 10 06:41:33 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206644 kb
Host smart-5b69cf44-5d47-4212-98da-a9bc4ad71d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36046
10812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3604610812
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.4061334537
Short name T1361
Test name
Test status
Simulation time 33503160 ps
CPU time 0.65 seconds
Started Jul 10 06:41:43 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 206404 kb
Host smart-5a63171c-ae06-4f39-afe4-3d2573f4dadc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4061334537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.4061334537
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.1093461479
Short name T2616
Test name
Test status
Simulation time 4074371560 ps
CPU time 4.93 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206468 kb
Host smart-01ceedc4-62dd-4938-903d-d3d32bf8f21f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1093461479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.1093461479
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.750353936
Short name T14
Test name
Test status
Simulation time 13326271946 ps
CPU time 13.59 seconds
Started Jul 10 06:41:28 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 206392 kb
Host smart-1bbcdf19-cdbc-42de-9126-12bafc812c0e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=750353936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.750353936
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1113970583
Short name T1321
Test name
Test status
Simulation time 23335813952 ps
CPU time 23.23 seconds
Started Jul 10 06:41:30 PM PDT 24
Finished Jul 10 06:42:00 PM PDT 24
Peak memory 206464 kb
Host smart-3bddd507-b80f-4e76-bee1-77a2be5ed5ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1113970583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.1113970583
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2637166213
Short name T650
Test name
Test status
Simulation time 169534035 ps
CPU time 0.82 seconds
Started Jul 10 06:41:34 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206384 kb
Host smart-44bd0633-28c5-4d32-8a1d-7c6f57bd908a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26371
66213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2637166213
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3538285502
Short name T683
Test name
Test status
Simulation time 211417473 ps
CPU time 0.83 seconds
Started Jul 10 06:41:29 PM PDT 24
Finished Jul 10 06:41:36 PM PDT 24
Peak memory 206396 kb
Host smart-b8467152-10dc-4e23-a12e-bb7690cf0f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35382
85502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3538285502
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.1301294043
Short name T1043
Test name
Test status
Simulation time 182437175 ps
CPU time 0.84 seconds
Started Jul 10 06:41:30 PM PDT 24
Finished Jul 10 06:41:38 PM PDT 24
Peak memory 206392 kb
Host smart-f12b3f82-4dcd-4f38-9711-d9dee6aea30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13012
94043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1301294043
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.525467433
Short name T1711
Test name
Test status
Simulation time 1029722493 ps
CPU time 2.2 seconds
Started Jul 10 06:41:33 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206584 kb
Host smart-37bae817-b21e-4741-98d7-121a2cfc303a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52546
7433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.525467433
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.4205234530
Short name T610
Test name
Test status
Simulation time 8370264083 ps
CPU time 16.34 seconds
Started Jul 10 06:41:38 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206620 kb
Host smart-c0126d71-0c25-4878-8ee4-74df7f7d2a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42052
34530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.4205234530
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2869982232
Short name T1679
Test name
Test status
Simulation time 473011167 ps
CPU time 1.39 seconds
Started Jul 10 06:41:41 PM PDT 24
Finished Jul 10 06:41:46 PM PDT 24
Peak memory 206384 kb
Host smart-da31e12b-4c61-4f6a-af35-2b7e689826bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
82232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2869982232
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.756053861
Short name T2512
Test name
Test status
Simulation time 141404299 ps
CPU time 0.78 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206380 kb
Host smart-a8396725-9bcc-4088-9975-5a427fa26aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75605
3861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.756053861
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2135937259
Short name T438
Test name
Test status
Simulation time 40347919 ps
CPU time 0.67 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206356 kb
Host smart-b3fd02a0-a85a-445f-b60d-0e79af60ee87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21359
37259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2135937259
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.3470540952
Short name T667
Test name
Test status
Simulation time 853026029 ps
CPU time 2.19 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:44 PM PDT 24
Peak memory 206600 kb
Host smart-73f896b5-b673-43b9-88c5-ac88f5b7d6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34705
40952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3470540952
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3104436683
Short name T1833
Test name
Test status
Simulation time 165621705 ps
CPU time 1.38 seconds
Started Jul 10 06:41:35 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206812 kb
Host smart-f516fcd9-dbd6-436f-ba18-febfae63d693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31044
36683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3104436683
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2918537960
Short name T1645
Test name
Test status
Simulation time 285398550 ps
CPU time 0.9 seconds
Started Jul 10 06:41:36 PM PDT 24
Finished Jul 10 06:41:41 PM PDT 24
Peak memory 206388 kb
Host smart-c3b71251-0f73-41d0-acf2-429b141c3982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29185
37960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2918537960
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2359408498
Short name T1294
Test name
Test status
Simulation time 136378931 ps
CPU time 0.75 seconds
Started Jul 10 06:41:38 PM PDT 24
Finished Jul 10 06:41:43 PM PDT 24
Peak memory 206384 kb
Host smart-46c5a079-01c4-4d74-b659-b94a54a1ea71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23594
08498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2359408498
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.763390098
Short name T1661
Test name
Test status
Simulation time 192494967 ps
CPU time 0.87 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206356 kb
Host smart-80fb2876-643e-4037-b068-1aff9fc6f3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76339
0098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.763390098
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.307128421
Short name T1479
Test name
Test status
Simulation time 4882614796 ps
CPU time 17.3 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206652 kb
Host smart-ac2420ac-c83e-45d5-99ff-581a389755e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30712
8421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.307128421
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1547702869
Short name T2322
Test name
Test status
Simulation time 250230373 ps
CPU time 1 seconds
Started Jul 10 06:41:41 PM PDT 24
Finished Jul 10 06:41:45 PM PDT 24
Peak memory 206392 kb
Host smart-565faf9e-756f-488b-b1ce-15e83838118e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
02869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1547702869
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3735698151
Short name T1683
Test name
Test status
Simulation time 23319282280 ps
CPU time 29.36 seconds
Started Jul 10 06:41:35 PM PDT 24
Finished Jul 10 06:42:10 PM PDT 24
Peak memory 206412 kb
Host smart-19fbfca2-ded1-4a18-9964-2a0d41d65c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37356
98151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3735698151
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2131513591
Short name T1277
Test name
Test status
Simulation time 3338845570 ps
CPU time 3.68 seconds
Started Jul 10 06:41:35 PM PDT 24
Finished Jul 10 06:41:44 PM PDT 24
Peak memory 206416 kb
Host smart-a7461593-97c2-4d33-9be4-77fd7b40b8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21315
13591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2131513591
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.512985543
Short name T1650
Test name
Test status
Simulation time 6220232978 ps
CPU time 174.79 seconds
Started Jul 10 06:41:35 PM PDT 24
Finished Jul 10 06:44:35 PM PDT 24
Peak memory 206752 kb
Host smart-377fe569-b958-49c0-9047-3d2b3b37cf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51298
5543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.512985543
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.564338703
Short name T2363
Test name
Test status
Simulation time 6179884953 ps
CPU time 173.27 seconds
Started Jul 10 06:41:41 PM PDT 24
Finished Jul 10 06:44:38 PM PDT 24
Peak memory 206624 kb
Host smart-27c087c5-a6a1-4a32-829c-c37673d83c77
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=564338703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.564338703
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3444177780
Short name T1542
Test name
Test status
Simulation time 241176544 ps
CPU time 0.95 seconds
Started Jul 10 06:41:36 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206396 kb
Host smart-a3543cdd-190b-4780-80af-23d0dd8d35e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3444177780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3444177780
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1958386090
Short name T2319
Test name
Test status
Simulation time 194465239 ps
CPU time 0.88 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206388 kb
Host smart-e77d671c-a97e-4b75-9aa7-ea95ab2684c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19583
86090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1958386090
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2918282810
Short name T2245
Test name
Test status
Simulation time 5051906696 ps
CPU time 36.99 seconds
Started Jul 10 06:41:43 PM PDT 24
Finished Jul 10 06:42:22 PM PDT 24
Peak memory 206700 kb
Host smart-1f66e1cf-68c9-4712-b3c8-27ee77831e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
82810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2918282810
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2369470724
Short name T1421
Test name
Test status
Simulation time 5090547825 ps
CPU time 132.53 seconds
Started Jul 10 06:41:40 PM PDT 24
Finished Jul 10 06:43:56 PM PDT 24
Peak memory 206624 kb
Host smart-e57418a8-0d35-480d-bf5a-c8579914ddbf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2369470724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2369470724
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.566825191
Short name T1151
Test name
Test status
Simulation time 169654273 ps
CPU time 0.82 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206376 kb
Host smart-ccfffd25-244b-4af5-a53a-63cf60a4c7fc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=566825191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.566825191
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1833358673
Short name T616
Test name
Test status
Simulation time 174025130 ps
CPU time 0.87 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206380 kb
Host smart-b4560745-e3b3-4a34-88eb-6e9c933cb9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
58673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1833358673
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1055886967
Short name T1211
Test name
Test status
Simulation time 177552590 ps
CPU time 0.82 seconds
Started Jul 10 06:41:36 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206368 kb
Host smart-130cf5e2-407e-4f4d-b3f3-9a8c040b3871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10558
86967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1055886967
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1126882206
Short name T1317
Test name
Test status
Simulation time 160119680 ps
CPU time 0.78 seconds
Started Jul 10 06:41:35 PM PDT 24
Finished Jul 10 06:41:41 PM PDT 24
Peak memory 206308 kb
Host smart-53e4a5a4-6298-4f73-9188-d3804b7d9dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11268
82206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1126882206
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.4246491683
Short name T332
Test name
Test status
Simulation time 157960122 ps
CPU time 0.82 seconds
Started Jul 10 06:41:41 PM PDT 24
Finished Jul 10 06:41:45 PM PDT 24
Peak memory 206384 kb
Host smart-e1b73394-725e-4330-ad98-9282c2311c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42464
91683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.4246491683
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1886920899
Short name T182
Test name
Test status
Simulation time 148357715 ps
CPU time 0.77 seconds
Started Jul 10 06:41:38 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206384 kb
Host smart-0c0f030e-79c5-4b8b-9c5d-7f5a1a2aa988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18869
20899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1886920899
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3989459490
Short name T2224
Test name
Test status
Simulation time 181335836 ps
CPU time 0.84 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206364 kb
Host smart-1e67cfe5-35d6-4067-8773-2d2611ffee85
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3989459490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3989459490
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1049880050
Short name T2559
Test name
Test status
Simulation time 162594541 ps
CPU time 0.82 seconds
Started Jul 10 06:41:35 PM PDT 24
Finished Jul 10 06:41:41 PM PDT 24
Peak memory 206392 kb
Host smart-37721a7d-c0ce-4bd2-8a2a-0ecf8d8d41f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10498
80050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1049880050
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1614118762
Short name T1505
Test name
Test status
Simulation time 35786524 ps
CPU time 0.67 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206356 kb
Host smart-dc4289b8-6eb6-4845-8636-43ec4f5e18de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141
18762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1614118762
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.390097228
Short name T1287
Test name
Test status
Simulation time 11366570732 ps
CPU time 24.27 seconds
Started Jul 10 06:41:40 PM PDT 24
Finished Jul 10 06:42:08 PM PDT 24
Peak memory 206728 kb
Host smart-40bd3f15-d5dd-47a1-954d-cfe9f61fdb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39009
7228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.390097228
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2646038433
Short name T2534
Test name
Test status
Simulation time 147334709 ps
CPU time 0.76 seconds
Started Jul 10 06:41:41 PM PDT 24
Finished Jul 10 06:41:45 PM PDT 24
Peak memory 206372 kb
Host smart-4c7865f2-de21-4edd-9adb-f959e54b9d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26460
38433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2646038433
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.299434818
Short name T2397
Test name
Test status
Simulation time 236839493 ps
CPU time 0.89 seconds
Started Jul 10 06:41:37 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206368 kb
Host smart-f85fa967-f5fd-40fb-8988-d1fbcf6b0bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29943
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.299434818
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.786875245
Short name T1227
Test name
Test status
Simulation time 216389037 ps
CPU time 0.87 seconds
Started Jul 10 06:41:43 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 206392 kb
Host smart-c4e6878d-21bb-40d8-b6d1-13b88a3dac8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78687
5245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.786875245
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2346165471
Short name T450
Test name
Test status
Simulation time 202493803 ps
CPU time 0.87 seconds
Started Jul 10 06:41:46 PM PDT 24
Finished Jul 10 06:41:50 PM PDT 24
Peak memory 206408 kb
Host smart-db268fb0-10c0-4984-b62d-c4d403730e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23461
65471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2346165471
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.11581266
Short name T1365
Test name
Test status
Simulation time 146744322 ps
CPU time 0.77 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 206368 kb
Host smart-8e0cb01b-c1fd-453c-a2b8-26c47665f73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11581
266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.11581266
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3496200193
Short name T889
Test name
Test status
Simulation time 154131069 ps
CPU time 0.77 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:41:48 PM PDT 24
Peak memory 206372 kb
Host smart-42900ca8-1c93-4277-8ef6-aa9acc822535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34962
00193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3496200193
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.116708840
Short name T1077
Test name
Test status
Simulation time 153708131 ps
CPU time 0.78 seconds
Started Jul 10 06:41:48 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206392 kb
Host smart-e4a5e786-2d4c-4b7a-9be0-9adcd15aedc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
8840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.116708840
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2058285384
Short name T912
Test name
Test status
Simulation time 225941779 ps
CPU time 0.95 seconds
Started Jul 10 06:41:43 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 206368 kb
Host smart-4b973451-bf40-42b0-8914-04f7cdac1374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582
85384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2058285384
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3856589556
Short name T831
Test name
Test status
Simulation time 4779791163 ps
CPU time 34.47 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:42:21 PM PDT 24
Peak memory 206632 kb
Host smart-86d1675b-5b35-4d74-9018-1e9273727b68
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3856589556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3856589556
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.4052053598
Short name T1012
Test name
Test status
Simulation time 195310325 ps
CPU time 0.79 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:41:48 PM PDT 24
Peak memory 206384 kb
Host smart-8c135d62-e5ab-4a75-b565-fb2de438e0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
53598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.4052053598
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.355577553
Short name T1064
Test name
Test status
Simulation time 209843228 ps
CPU time 0.86 seconds
Started Jul 10 06:41:43 PM PDT 24
Finished Jul 10 06:41:46 PM PDT 24
Peak memory 206388 kb
Host smart-47cc223c-f3b1-46a9-bdf3-6d9a7908aabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557
7553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.355577553
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1510569614
Short name T836
Test name
Test status
Simulation time 1259924037 ps
CPU time 2.57 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:41:50 PM PDT 24
Peak memory 206616 kb
Host smart-fccf40a5-b23a-4be7-92ea-9647ccc3fd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15105
69614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1510569614
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.1201578414
Short name T392
Test name
Test status
Simulation time 3809576737 ps
CPU time 36.88 seconds
Started Jul 10 06:41:45 PM PDT 24
Finished Jul 10 06:42:25 PM PDT 24
Peak memory 206668 kb
Host smart-b4192635-8300-4af7-bba2-b946e643e562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12015
78414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1201578414
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.3258990036
Short name T1728
Test name
Test status
Simulation time 39487552 ps
CPU time 0.66 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:41:53 PM PDT 24
Peak memory 206428 kb
Host smart-33070893-e92e-4986-82cd-c28ca6d13f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3258990036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.3258990036
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3539578552
Short name T1009
Test name
Test status
Simulation time 3954692831 ps
CPU time 4.9 seconds
Started Jul 10 06:41:46 PM PDT 24
Finished Jul 10 06:41:54 PM PDT 24
Peak memory 206616 kb
Host smart-5a986c0a-7edf-418c-b6da-8695376ad83e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3539578552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3539578552
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2452701439
Short name T10
Test name
Test status
Simulation time 13353356751 ps
CPU time 13.38 seconds
Started Jul 10 06:41:43 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206736 kb
Host smart-8345411e-192d-4e2b-a28b-1a960044d2ea
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2452701439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2452701439
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3815177437
Short name T1323
Test name
Test status
Simulation time 23384365935 ps
CPU time 23.35 seconds
Started Jul 10 06:41:47 PM PDT 24
Finished Jul 10 06:42:13 PM PDT 24
Peak memory 206460 kb
Host smart-30a15313-3ba3-4ea1-9c9e-818848a1752a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3815177437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.3815177437
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3236884173
Short name T2029
Test name
Test status
Simulation time 172078981 ps
CPU time 0.81 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:41:48 PM PDT 24
Peak memory 206376 kb
Host smart-a24345eb-6bfa-4db4-9236-8482b7f040ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32368
84173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3236884173
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.175794106
Short name T698
Test name
Test status
Simulation time 197417696 ps
CPU time 0.79 seconds
Started Jul 10 06:41:43 PM PDT 24
Finished Jul 10 06:41:46 PM PDT 24
Peak memory 206392 kb
Host smart-ff5632f3-21c4-49c1-bbb8-ed5574310a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17579
4106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.175794106
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.585793143
Short name T1322
Test name
Test status
Simulation time 456248765 ps
CPU time 1.39 seconds
Started Jul 10 06:41:45 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206396 kb
Host smart-330ad30c-1d78-4a56-9a15-487d6eeed8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58579
3143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.585793143
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3878134402
Short name T486
Test name
Test status
Simulation time 724244090 ps
CPU time 1.79 seconds
Started Jul 10 06:41:45 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206588 kb
Host smart-9f6fced9-27d7-48aa-ace0-9f18452b640c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38781
34402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3878134402
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1592096230
Short name T2680
Test name
Test status
Simulation time 20432176416 ps
CPU time 40.44 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:42:32 PM PDT 24
Peak memory 206656 kb
Host smart-5bf1efd3-b6bc-4cb7-8da4-96c685819d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15920
96230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1592096230
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1789974887
Short name T788
Test name
Test status
Simulation time 432160128 ps
CPU time 1.43 seconds
Started Jul 10 06:41:45 PM PDT 24
Finished Jul 10 06:41:50 PM PDT 24
Peak memory 206376 kb
Host smart-90f3c9d4-dd35-4f80-aa50-5b93181e5cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17899
74887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1789974887
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1598501317
Short name T540
Test name
Test status
Simulation time 144032485 ps
CPU time 0.77 seconds
Started Jul 10 06:41:47 PM PDT 24
Finished Jul 10 06:41:50 PM PDT 24
Peak memory 206360 kb
Host smart-3b4f1191-10b7-4e8d-8402-8f03afbc39fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15985
01317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1598501317
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1810784027
Short name T2442
Test name
Test status
Simulation time 71563025 ps
CPU time 0.75 seconds
Started Jul 10 06:41:47 PM PDT 24
Finished Jul 10 06:41:51 PM PDT 24
Peak memory 206376 kb
Host smart-99db9d58-1d8c-46c4-a740-338bd7f28bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
84027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1810784027
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.4099555823
Short name T348
Test name
Test status
Simulation time 973908808 ps
CPU time 2.23 seconds
Started Jul 10 06:41:47 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206604 kb
Host smart-10f240d8-27ce-41e1-a7c0-338b38a47243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40995
55823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.4099555823
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1817250711
Short name T1818
Test name
Test status
Simulation time 187133982 ps
CPU time 1.62 seconds
Started Jul 10 06:41:48 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206628 kb
Host smart-36b67e4c-ec79-4a00-a694-b5fb8bed151a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18172
50711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1817250711
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.51886538
Short name T1413
Test name
Test status
Simulation time 180688904 ps
CPU time 0.85 seconds
Started Jul 10 06:41:42 PM PDT 24
Finished Jul 10 06:41:46 PM PDT 24
Peak memory 206376 kb
Host smart-29ee2634-c631-46fc-8443-015db0c97843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51886
538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.51886538
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1398911814
Short name T1704
Test name
Test status
Simulation time 146839516 ps
CPU time 0.79 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 206392 kb
Host smart-c87af2f7-8367-4f52-817c-3b43812a9fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13989
11814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1398911814
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3545774685
Short name T1338
Test name
Test status
Simulation time 200226368 ps
CPU time 0.91 seconds
Started Jul 10 06:41:46 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206356 kb
Host smart-4bb9db71-7bda-485c-81f1-874f9090d4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35457
74685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3545774685
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3157212839
Short name T935
Test name
Test status
Simulation time 244884115 ps
CPU time 0.83 seconds
Started Jul 10 06:41:45 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206384 kb
Host smart-62f90ee6-df84-4fac-abc7-3c2abe1e792e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31572
12839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3157212839
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.691844652
Short name T1070
Test name
Test status
Simulation time 23357304615 ps
CPU time 22.65 seconds
Started Jul 10 06:41:45 PM PDT 24
Finished Jul 10 06:42:11 PM PDT 24
Peak memory 206456 kb
Host smart-683c242d-806e-4604-bcd5-5fb98fbaccc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69184
4652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.691844652
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3996737637
Short name T1684
Test name
Test status
Simulation time 3313845237 ps
CPU time 4.95 seconds
Started Jul 10 06:41:41 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206436 kb
Host smart-808a92b7-0e61-4a8b-b73a-046a733ea0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39967
37637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3996737637
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.897537241
Short name T1600
Test name
Test status
Simulation time 12769615300 ps
CPU time 343.47 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:47:30 PM PDT 24
Peak memory 206884 kb
Host smart-fb554909-0691-49de-9185-a097c5aef470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89753
7241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.897537241
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2699466041
Short name T659
Test name
Test status
Simulation time 5887618143 ps
CPU time 43.88 seconds
Started Jul 10 06:41:43 PM PDT 24
Finished Jul 10 06:42:30 PM PDT 24
Peak memory 206632 kb
Host smart-de6639f3-c8d3-46ab-bd21-8b079fae2380
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2699466041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2699466041
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1554981536
Short name T865
Test name
Test status
Simulation time 239192042 ps
CPU time 0.87 seconds
Started Jul 10 06:41:48 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206372 kb
Host smart-abaf8913-e75e-4bc0-934d-6b60d4c3f18a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1554981536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1554981536
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.482168382
Short name T1232
Test name
Test status
Simulation time 213120256 ps
CPU time 0.87 seconds
Started Jul 10 06:41:46 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206400 kb
Host smart-a7e2efd8-eb9b-4b5f-af7e-050af4e9cb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48216
8382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.482168382
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.274363706
Short name T1214
Test name
Test status
Simulation time 4424387658 ps
CPU time 38.64 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:42:25 PM PDT 24
Peak memory 206716 kb
Host smart-d4e132c6-6bbf-4f5c-8dae-ceaedd13f0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27436
3706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.274363706
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.4146730873
Short name T1037
Test name
Test status
Simulation time 5581744277 ps
CPU time 162.46 seconds
Started Jul 10 06:41:48 PM PDT 24
Finished Jul 10 06:44:33 PM PDT 24
Peak memory 206624 kb
Host smart-2e6c4953-c467-45cd-979e-a89c7668d92a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4146730873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.4146730873
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2181233579
Short name T582
Test name
Test status
Simulation time 160669966 ps
CPU time 0.79 seconds
Started Jul 10 06:41:44 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 206284 kb
Host smart-8ffc10e8-2199-45dc-a319-b1a15443a133
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2181233579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2181233579
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.608591173
Short name T511
Test name
Test status
Simulation time 140798624 ps
CPU time 0.81 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:41:55 PM PDT 24
Peak memory 206368 kb
Host smart-6c2bb2da-8c98-4897-8c9d-7f9a72c1ab7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60859
1173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.608591173
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1239875561
Short name T126
Test name
Test status
Simulation time 195987006 ps
CPU time 0.87 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:41:54 PM PDT 24
Peak memory 206392 kb
Host smart-3f875bfb-9f82-4ae3-884e-72a90825919c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12398
75561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1239875561
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2765705788
Short name T2744
Test name
Test status
Simulation time 148893858 ps
CPU time 0.87 seconds
Started Jul 10 06:41:51 PM PDT 24
Finished Jul 10 06:41:56 PM PDT 24
Peak memory 206360 kb
Host smart-44c78665-cc99-4c30-aaa6-062a400ed93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27657
05788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2765705788
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.521191616
Short name T742
Test name
Test status
Simulation time 178160846 ps
CPU time 0.81 seconds
Started Jul 10 06:41:52 PM PDT 24
Finished Jul 10 06:41:56 PM PDT 24
Peak memory 206372 kb
Host smart-af1716c7-6952-49aa-bf4d-d2600876794c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52119
1616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.521191616
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.975239634
Short name T1456
Test name
Test status
Simulation time 216036358 ps
CPU time 0.91 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206380 kb
Host smart-6f4b9c93-bacb-4704-b97d-dc45acd7c459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97523
9634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.975239634
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.47576896
Short name T974
Test name
Test status
Simulation time 181926925 ps
CPU time 0.85 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206384 kb
Host smart-ef7f2af6-767a-4b9f-ad6e-60daf1e18036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47576
896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.47576896
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1637335702
Short name T1889
Test name
Test status
Simulation time 216043919 ps
CPU time 0.9 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:41:54 PM PDT 24
Peak memory 206332 kb
Host smart-c34bdfbc-192a-4265-a1fa-5871e274be25
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1637335702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1637335702
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3154128291
Short name T784
Test name
Test status
Simulation time 154796575 ps
CPU time 0.79 seconds
Started Jul 10 06:41:51 PM PDT 24
Finished Jul 10 06:41:56 PM PDT 24
Peak memory 206380 kb
Host smart-45668399-5385-4a92-8ea1-d68bc8132eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31541
28291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3154128291
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.4094405451
Short name T2353
Test name
Test status
Simulation time 20178907666 ps
CPU time 40.9 seconds
Started Jul 10 06:41:53 PM PDT 24
Finished Jul 10 06:42:37 PM PDT 24
Peak memory 206688 kb
Host smart-b1d3d7b3-9f61-48d7-b5c9-f5b95c827fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
05451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.4094405451
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2199756420
Short name T1878
Test name
Test status
Simulation time 160329661 ps
CPU time 0.81 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:41:54 PM PDT 24
Peak memory 206376 kb
Host smart-c820ca4e-4c10-4fd6-af6d-587bdf0aaa0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21997
56420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2199756420
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3772527267
Short name T1399
Test name
Test status
Simulation time 213853139 ps
CPU time 0.84 seconds
Started Jul 10 06:41:48 PM PDT 24
Finished Jul 10 06:41:51 PM PDT 24
Peak memory 206368 kb
Host smart-40099f47-0077-4ec4-8c14-d9e25f473bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37725
27267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3772527267
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3763933835
Short name T1121
Test name
Test status
Simulation time 240962680 ps
CPU time 0.95 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:41:54 PM PDT 24
Peak memory 206368 kb
Host smart-fba4a5e7-4cc1-4c30-a3af-9c1d404775ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37639
33835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3763933835
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1920299006
Short name T847
Test name
Test status
Simulation time 183782992 ps
CPU time 0.84 seconds
Started Jul 10 06:41:51 PM PDT 24
Finished Jul 10 06:41:55 PM PDT 24
Peak memory 206384 kb
Host smart-7f85d838-1406-4d1e-8813-d21755e21fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19202
99006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1920299006
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1962728649
Short name T1930
Test name
Test status
Simulation time 150006461 ps
CPU time 0.78 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206356 kb
Host smart-bdcec52b-f579-46fb-8f73-821f37150677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19627
28649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1962728649
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.724594564
Short name T2285
Test name
Test status
Simulation time 177621768 ps
CPU time 0.81 seconds
Started Jul 10 06:41:48 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206376 kb
Host smart-826af92e-5c6d-4234-979b-fbc5a0eb75d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72459
4564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.724594564
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.871506713
Short name T522
Test name
Test status
Simulation time 151651902 ps
CPU time 0.78 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:41:55 PM PDT 24
Peak memory 206052 kb
Host smart-95884685-7105-47bb-bfa2-e3901d5b1089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87150
6713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.871506713
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3786585086
Short name T1807
Test name
Test status
Simulation time 188327163 ps
CPU time 0.89 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:41:53 PM PDT 24
Peak memory 206376 kb
Host smart-b2fb2b3a-0cb8-43f1-afb4-7444dff6dd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37865
85086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3786585086
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2974033255
Short name T2393
Test name
Test status
Simulation time 4089519294 ps
CPU time 107.17 seconds
Started Jul 10 06:41:51 PM PDT 24
Finished Jul 10 06:43:42 PM PDT 24
Peak memory 206612 kb
Host smart-6060a70f-bb62-443b-b72f-7f37083e0c97
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2974033255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2974033255
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2951692555
Short name T1998
Test name
Test status
Simulation time 195447350 ps
CPU time 0.84 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:41:54 PM PDT 24
Peak memory 206396 kb
Host smart-7e89120b-7a7b-4c43-a3d4-82a436cd7b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29516
92555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2951692555
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2635722229
Short name T2649
Test name
Test status
Simulation time 164866318 ps
CPU time 0.79 seconds
Started Jul 10 06:41:51 PM PDT 24
Finished Jul 10 06:41:55 PM PDT 24
Peak memory 206372 kb
Host smart-0962acc9-9679-4f47-9c9c-14e951ca1685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
22229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2635722229
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2262169043
Short name T936
Test name
Test status
Simulation time 279546981 ps
CPU time 0.89 seconds
Started Jul 10 06:41:48 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206380 kb
Host smart-0e42bc9a-d0ad-40fe-a6fc-e3889e43e9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22621
69043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2262169043
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2551635802
Short name T2182
Test name
Test status
Simulation time 3144994745 ps
CPU time 23 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:42:16 PM PDT 24
Peak memory 206620 kb
Host smart-8b77545e-d437-43ce-b963-2e201be27a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25516
35802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2551635802
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2920641613
Short name T185
Test name
Test status
Simulation time 38628687 ps
CPU time 0.69 seconds
Started Jul 10 06:42:04 PM PDT 24
Finished Jul 10 06:42:06 PM PDT 24
Peak memory 206404 kb
Host smart-ce31825e-5b4d-499d-a521-44cca91a0759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2920641613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2920641613
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1853270686
Short name T2188
Test name
Test status
Simulation time 3594194951 ps
CPU time 4.32 seconds
Started Jul 10 06:41:51 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206632 kb
Host smart-5f5bd8f2-9d0e-4d0a-9b24-23ebf37ea7a7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1853270686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1853270686
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.109327333
Short name T1810
Test name
Test status
Simulation time 13354484765 ps
CPU time 12.27 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:42:04 PM PDT 24
Peak memory 206436 kb
Host smart-94cc630b-bcdc-4040-b1c2-02bf8a587578
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=109327333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.109327333
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3513537486
Short name T12
Test name
Test status
Simulation time 23376134075 ps
CPU time 24.5 seconds
Started Jul 10 06:41:48 PM PDT 24
Finished Jul 10 06:42:15 PM PDT 24
Peak memory 206448 kb
Host smart-30645216-53fe-4f59-8a2f-ebb88f466362
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3513537486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3513537486
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2986828154
Short name T272
Test name
Test status
Simulation time 191502559 ps
CPU time 0.84 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:41:55 PM PDT 24
Peak memory 206392 kb
Host smart-4152889b-624c-4023-ab30-6215811c3530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29868
28154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2986828154
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2278324380
Short name T2671
Test name
Test status
Simulation time 167917940 ps
CPU time 0.78 seconds
Started Jul 10 06:41:50 PM PDT 24
Finished Jul 10 06:41:55 PM PDT 24
Peak memory 206080 kb
Host smart-ef0a5081-59a0-41d1-a48e-0586e03cacc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
24380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2278324380
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.173372390
Short name T1330
Test name
Test status
Simulation time 153618442 ps
CPU time 0.79 seconds
Started Jul 10 06:41:49 PM PDT 24
Finished Jul 10 06:41:53 PM PDT 24
Peak memory 206384 kb
Host smart-d14278e7-aa54-45fa-a3cc-1ea4921ebe8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17337
2390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.173372390
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3386641077
Short name T617
Test name
Test status
Simulation time 518542353 ps
CPU time 1.51 seconds
Started Jul 10 06:41:51 PM PDT 24
Finished Jul 10 06:41:57 PM PDT 24
Peak memory 206364 kb
Host smart-a0ddb33b-a2a6-4b04-b270-7da99be35ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33866
41077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3386641077
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.422621033
Short name T879
Test name
Test status
Simulation time 22512453048 ps
CPU time 43.23 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206716 kb
Host smart-519deb38-e5c9-47f8-977c-01fcd8504257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42262
1033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.422621033
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3203925389
Short name T1034
Test name
Test status
Simulation time 363330313 ps
CPU time 1.39 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:00 PM PDT 24
Peak memory 206384 kb
Host smart-965d0ace-4044-4367-b336-f36a1211fa7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32039
25389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3203925389
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.544370824
Short name T661
Test name
Test status
Simulation time 137663958 ps
CPU time 0.78 seconds
Started Jul 10 06:41:59 PM PDT 24
Finished Jul 10 06:42:03 PM PDT 24
Peak memory 206384 kb
Host smart-06de7137-ccf2-46e5-866f-cff92791d3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54437
0824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.544370824
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.162470404
Short name T1811
Test name
Test status
Simulation time 34611172 ps
CPU time 0.64 seconds
Started Jul 10 06:41:55 PM PDT 24
Finished Jul 10 06:41:57 PM PDT 24
Peak memory 206344 kb
Host smart-bcdc32e5-ffe7-4226-b62b-7f025b9075d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16247
0404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.162470404
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3496393819
Short name T2597
Test name
Test status
Simulation time 973488812 ps
CPU time 2.31 seconds
Started Jul 10 06:41:56 PM PDT 24
Finished Jul 10 06:42:00 PM PDT 24
Peak memory 206648 kb
Host smart-d239bbb5-d6e8-4390-b7c6-ddc2c514cd03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
93819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3496393819
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3103161490
Short name T795
Test name
Test status
Simulation time 186972376 ps
CPU time 1.75 seconds
Started Jul 10 06:41:59 PM PDT 24
Finished Jul 10 06:42:04 PM PDT 24
Peak memory 206632 kb
Host smart-5d46e352-0577-4aa1-b7c5-4d3a68b2590c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31031
61490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3103161490
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3002996704
Short name T2676
Test name
Test status
Simulation time 186199769 ps
CPU time 0.85 seconds
Started Jul 10 06:41:55 PM PDT 24
Finished Jul 10 06:41:57 PM PDT 24
Peak memory 206380 kb
Host smart-542a0824-798b-4f36-ae40-902ee8ad0250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30029
96704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3002996704
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3125924763
Short name T2469
Test name
Test status
Simulation time 143846837 ps
CPU time 0.78 seconds
Started Jul 10 06:41:58 PM PDT 24
Finished Jul 10 06:42:01 PM PDT 24
Peak memory 206392 kb
Host smart-edaf1dd3-3aba-4cfb-85d6-3ed688fcea49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31259
24763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3125924763
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3193811466
Short name T401
Test name
Test status
Simulation time 193659232 ps
CPU time 0.95 seconds
Started Jul 10 06:41:58 PM PDT 24
Finished Jul 10 06:42:02 PM PDT 24
Peak memory 206280 kb
Host smart-8f3af8a6-fd51-47af-a5c7-544523d16924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31938
11466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3193811466
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1562841747
Short name T81
Test name
Test status
Simulation time 5282755508 ps
CPU time 51.06 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:49 PM PDT 24
Peak memory 206656 kb
Host smart-b6f6dbca-1269-408f-8e08-41177688800a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1562841747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1562841747
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.560496715
Short name T1564
Test name
Test status
Simulation time 4431727475 ps
CPU time 35 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:42:46 PM PDT 24
Peak memory 206684 kb
Host smart-900438ca-8e4c-493a-ab34-72b0a7185ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56049
6715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.560496715
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1966516605
Short name T987
Test name
Test status
Simulation time 237802309 ps
CPU time 0.9 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:01 PM PDT 24
Peak memory 206328 kb
Host smart-df787bd2-15b5-491d-a9fa-e6d006f37a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
16605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1966516605
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.4092041793
Short name T2017
Test name
Test status
Simulation time 23333334464 ps
CPU time 22.92 seconds
Started Jul 10 06:41:58 PM PDT 24
Finished Jul 10 06:42:24 PM PDT 24
Peak memory 206420 kb
Host smart-8a07e6a5-fdfd-43bb-bf1a-30d4702b84b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920
41793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.4092041793
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.1243079810
Short name T1622
Test name
Test status
Simulation time 3327198922 ps
CPU time 3.81 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:04 PM PDT 24
Peak memory 206440 kb
Host smart-17edf5d5-a0cc-46c1-a3f2-27354882fce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12430
79810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1243079810
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1708083737
Short name T2345
Test name
Test status
Simulation time 10151768911 ps
CPU time 99.2 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:43:38 PM PDT 24
Peak memory 206704 kb
Host smart-1d971a6c-1fb9-4e53-b6cf-5445c672183b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17080
83737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1708083737
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3096760947
Short name T2678
Test name
Test status
Simulation time 6435970914 ps
CPU time 48.36 seconds
Started Jul 10 06:41:56 PM PDT 24
Finished Jul 10 06:42:46 PM PDT 24
Peak memory 206700 kb
Host smart-2cd38ceb-5a61-4997-8463-5d6aa448b118
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3096760947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3096760947
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.613821808
Short name T854
Test name
Test status
Simulation time 245379157 ps
CPU time 0.94 seconds
Started Jul 10 06:41:59 PM PDT 24
Finished Jul 10 06:42:03 PM PDT 24
Peak memory 206360 kb
Host smart-a1b7d8fc-a81a-4fd3-b0ea-5f47aaafe30f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=613821808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.613821808
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1919297083
Short name T2463
Test name
Test status
Simulation time 272995933 ps
CPU time 0.97 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:00 PM PDT 24
Peak memory 206392 kb
Host smart-bf854a6a-aff8-4ce9-9e87-06eac3a9e2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19192
97083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1919297083
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1201481835
Short name T2223
Test name
Test status
Simulation time 6327713683 ps
CPU time 176.06 seconds
Started Jul 10 06:42:00 PM PDT 24
Finished Jul 10 06:44:58 PM PDT 24
Peak memory 206548 kb
Host smart-927da72f-8d8c-488e-ac76-45dbe15bfbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12014
81835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1201481835
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1484652205
Short name T2588
Test name
Test status
Simulation time 7459422295 ps
CPU time 208.21 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:45:39 PM PDT 24
Peak memory 206648 kb
Host smart-cd05bdde-7d95-403f-951b-8cabb49c8a77
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1484652205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1484652205
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3950527024
Short name T1755
Test name
Test status
Simulation time 173407255 ps
CPU time 0.82 seconds
Started Jul 10 06:42:01 PM PDT 24
Finished Jul 10 06:42:03 PM PDT 24
Peak memory 206284 kb
Host smart-27974875-c53e-4e91-8f16-84ab5bd1eab7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3950527024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3950527024
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2808399306
Short name T1915
Test name
Test status
Simulation time 160345416 ps
CPU time 0.78 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:42:12 PM PDT 24
Peak memory 206400 kb
Host smart-de36eacb-9ad6-48b9-818b-daac2ad3e7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28083
99306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2808399306
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2974242952
Short name T739
Test name
Test status
Simulation time 179091656 ps
CPU time 0.83 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:42:12 PM PDT 24
Peak memory 206400 kb
Host smart-33c70855-f157-411c-ad75-c5339710c682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29742
42952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2974242952
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3384841683
Short name T1945
Test name
Test status
Simulation time 198362986 ps
CPU time 0.9 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:01 PM PDT 24
Peak memory 206304 kb
Host smart-e51d1a2f-ebab-4b69-84ee-70d5fd77cc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33848
41683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3384841683
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.4151207559
Short name T369
Test name
Test status
Simulation time 173915354 ps
CPU time 0.86 seconds
Started Jul 10 06:41:59 PM PDT 24
Finished Jul 10 06:42:03 PM PDT 24
Peak memory 206276 kb
Host smart-f42a4d52-69ad-46df-9920-e4f812a57705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41512
07559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.4151207559
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.505653090
Short name T757
Test name
Test status
Simulation time 144614535 ps
CPU time 0.76 seconds
Started Jul 10 06:41:55 PM PDT 24
Finished Jul 10 06:41:57 PM PDT 24
Peak memory 206396 kb
Host smart-9cac75da-638e-476b-96d4-522f8fa13a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50565
3090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.505653090
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.208561013
Short name T1986
Test name
Test status
Simulation time 213327175 ps
CPU time 0.95 seconds
Started Jul 10 06:41:58 PM PDT 24
Finished Jul 10 06:42:02 PM PDT 24
Peak memory 206384 kb
Host smart-25275585-ded4-44f2-a28e-0be3f8ee32ee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=208561013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.208561013
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.280725304
Short name T1065
Test name
Test status
Simulation time 142076289 ps
CPU time 0.78 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206400 kb
Host smart-1518d308-a343-46c7-a21c-5b1c9dcc1522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072
5304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.280725304
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1791313188
Short name T1000
Test name
Test status
Simulation time 39429867 ps
CPU time 0.69 seconds
Started Jul 10 06:41:56 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206372 kb
Host smart-0e599ff7-6911-4fd1-84d4-64eb8a169a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
13188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1791313188
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2144444195
Short name T1202
Test name
Test status
Simulation time 18811496386 ps
CPU time 42.39 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:42:54 PM PDT 24
Peak memory 206752 kb
Host smart-41491ddc-f2fe-49af-9e1c-1fdcec2937ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21444
44195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2144444195
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1635230570
Short name T609
Test name
Test status
Simulation time 169830459 ps
CPU time 0.93 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:00 PM PDT 24
Peak memory 206404 kb
Host smart-86a44c99-402b-4f7e-a4d5-b11ef160271b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352
30570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1635230570
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3822651892
Short name T1805
Test name
Test status
Simulation time 167339782 ps
CPU time 0.83 seconds
Started Jul 10 06:41:59 PM PDT 24
Finished Jul 10 06:42:03 PM PDT 24
Peak memory 206276 kb
Host smart-5e73219c-46a4-4591-ace7-7141478982d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38226
51892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3822651892
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1020994008
Short name T2696
Test name
Test status
Simulation time 191458317 ps
CPU time 0.9 seconds
Started Jul 10 06:42:01 PM PDT 24
Finished Jul 10 06:42:03 PM PDT 24
Peak memory 206316 kb
Host smart-6a5380bc-3fe0-4619-a443-96a6d7081f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10209
94008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1020994008
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.3131018281
Short name T1465
Test name
Test status
Simulation time 189548437 ps
CPU time 0.92 seconds
Started Jul 10 06:41:58 PM PDT 24
Finished Jul 10 06:42:01 PM PDT 24
Peak memory 206396 kb
Host smart-2a2995c2-5d77-43d9-aa76-1714517e38a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
18281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.3131018281
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3469238752
Short name T1714
Test name
Test status
Simulation time 183458659 ps
CPU time 0.87 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206376 kb
Host smart-236caa49-4357-40fb-9daa-a0c52b2d550f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34692
38752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3469238752
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.4216239411
Short name T1696
Test name
Test status
Simulation time 168180921 ps
CPU time 0.81 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206372 kb
Host smart-849f1c51-7c33-4ebc-9632-e6f337f5c932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42162
39411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.4216239411
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3184376186
Short name T898
Test name
Test status
Simulation time 142822010 ps
CPU time 0.77 seconds
Started Jul 10 06:41:58 PM PDT 24
Finished Jul 10 06:42:02 PM PDT 24
Peak memory 206380 kb
Host smart-4ee70d09-4a1a-4140-a73a-c8713f09c87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31843
76186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3184376186
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1317611770
Short name T886
Test name
Test status
Simulation time 216809960 ps
CPU time 0.94 seconds
Started Jul 10 06:42:06 PM PDT 24
Finished Jul 10 06:42:09 PM PDT 24
Peak memory 206376 kb
Host smart-ca09b6df-e233-4a9e-8d80-7f783c4bfb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13176
11770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1317611770
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2871790708
Short name T559
Test name
Test status
Simulation time 5223753154 ps
CPU time 143.4 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:44:35 PM PDT 24
Peak memory 206320 kb
Host smart-c6d7f691-285d-4375-99b8-b42a1f611fa3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2871790708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2871790708
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.4127852866
Short name T1603
Test name
Test status
Simulation time 188615528 ps
CPU time 0.89 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:09 PM PDT 24
Peak memory 206376 kb
Host smart-31e01ee9-e68f-4860-a2c3-8a1f557da460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41278
52866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.4127852866
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3704065271
Short name T2551
Test name
Test status
Simulation time 211389958 ps
CPU time 0.89 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:42:12 PM PDT 24
Peak memory 206396 kb
Host smart-0e8ce8fd-441f-4f27-b4f7-eda7aff4d90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37040
65271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3704065271
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3367053014
Short name T842
Test name
Test status
Simulation time 876252078 ps
CPU time 1.98 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:09 PM PDT 24
Peak memory 206616 kb
Host smart-a2155c79-e9c6-4a60-937f-10f944dd3192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33670
53014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3367053014
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.1191666128
Short name T580
Test name
Test status
Simulation time 160635061 ps
CPU time 0.82 seconds
Started Jul 10 06:41:57 PM PDT 24
Finished Jul 10 06:42:01 PM PDT 24
Peak memory 206372 kb
Host smart-3e6efee1-b4d1-4282-98c5-3e3c74b31513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916
66128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_host_handshake.1191666128
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2044728026
Short name T938
Test name
Test status
Simulation time 75090735 ps
CPU time 0.74 seconds
Started Jul 10 06:42:16 PM PDT 24
Finished Jul 10 06:42:18 PM PDT 24
Peak memory 206444 kb
Host smart-21443164-3028-4265-ad80-5ef3af268399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2044728026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2044728026
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1982358625
Short name T1087
Test name
Test status
Simulation time 4403340128 ps
CPU time 5.68 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:14 PM PDT 24
Peak memory 206708 kb
Host smart-c915c292-2677-494d-aad6-cfaea6a72248
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1982358625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1982358625
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3419988762
Short name T1133
Test name
Test status
Simulation time 13327834934 ps
CPU time 13.59 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:21 PM PDT 24
Peak memory 206444 kb
Host smart-1ddce0b3-288b-4e18-8e09-93018f1265de
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3419988762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3419988762
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.1949412103
Short name T1522
Test name
Test status
Simulation time 23358171880 ps
CPU time 23.57 seconds
Started Jul 10 06:42:04 PM PDT 24
Finished Jul 10 06:42:28 PM PDT 24
Peak memory 206432 kb
Host smart-8854a5e5-ad9b-48a1-9e79-da053d8de1e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1949412103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.1949412103
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2033112003
Short name T1873
Test name
Test status
Simulation time 161133232 ps
CPU time 0.83 seconds
Started Jul 10 06:42:06 PM PDT 24
Finished Jul 10 06:42:09 PM PDT 24
Peak memory 206392 kb
Host smart-191c5da0-2d85-41ee-badf-e838ea2b400b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331
12003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2033112003
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.2925086839
Short name T1628
Test name
Test status
Simulation time 201493697 ps
CPU time 0.8 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:08 PM PDT 24
Peak memory 206560 kb
Host smart-0cfc6040-56a6-4712-b92f-3d0e64e5514e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29250
86839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.2925086839
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2676761633
Short name T2564
Test name
Test status
Simulation time 261924549 ps
CPU time 1.01 seconds
Started Jul 10 06:42:06 PM PDT 24
Finished Jul 10 06:42:10 PM PDT 24
Peak memory 206396 kb
Host smart-880cb52f-7c2b-47cb-840a-35bca770092d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26767
61633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2676761633
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.2224103255
Short name T1302
Test name
Test status
Simulation time 800000029 ps
CPU time 2.07 seconds
Started Jul 10 06:42:09 PM PDT 24
Finished Jul 10 06:42:14 PM PDT 24
Peak memory 206560 kb
Host smart-9998286f-039f-457f-8b80-b8cb91c6e2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22241
03255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2224103255
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.1397920382
Short name T98
Test name
Test status
Simulation time 20262886089 ps
CPU time 36.24 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:44 PM PDT 24
Peak memory 206608 kb
Host smart-d9568bea-935e-4a07-ac30-2e48cc5721c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13979
20382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1397920382
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3964912362
Short name T1517
Test name
Test status
Simulation time 390481036 ps
CPU time 1.33 seconds
Started Jul 10 06:42:06 PM PDT 24
Finished Jul 10 06:42:10 PM PDT 24
Peak memory 206384 kb
Host smart-c09c64ac-59b6-4cb8-97dd-41bca3cd37bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39649
12362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3964912362
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2607453658
Short name T1205
Test name
Test status
Simulation time 176703933 ps
CPU time 0.79 seconds
Started Jul 10 06:42:07 PM PDT 24
Finished Jul 10 06:42:11 PM PDT 24
Peak memory 206396 kb
Host smart-bc32455e-2b6d-4f88-8ab1-8ffb34df17c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26074
53658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2607453658
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1384336984
Short name T2259
Test name
Test status
Simulation time 75077639 ps
CPU time 0.78 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:08 PM PDT 24
Peak memory 206380 kb
Host smart-d3905376-7cbe-4f92-ae85-f79aeca0d797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13843
36984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1384336984
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.645192581
Short name T750
Test name
Test status
Simulation time 1012595355 ps
CPU time 2.62 seconds
Started Jul 10 06:42:09 PM PDT 24
Finished Jul 10 06:42:15 PM PDT 24
Peak memory 206592 kb
Host smart-8db69914-7549-4afa-b33f-bed0d60ccdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64519
2581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.645192581
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3437703403
Short name T2304
Test name
Test status
Simulation time 214703195 ps
CPU time 1.47 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:09 PM PDT 24
Peak memory 206568 kb
Host smart-637c6236-0462-407e-b525-7d4b18dfff91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34377
03403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3437703403
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1258147192
Short name T1148
Test name
Test status
Simulation time 182307962 ps
CPU time 0.81 seconds
Started Jul 10 06:42:07 PM PDT 24
Finished Jul 10 06:42:11 PM PDT 24
Peak memory 206352 kb
Host smart-fb052733-afc9-42af-8425-02d2e25c3b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12581
47192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1258147192
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2636901105
Short name T838
Test name
Test status
Simulation time 150103949 ps
CPU time 0.75 seconds
Started Jul 10 06:42:04 PM PDT 24
Finished Jul 10 06:42:07 PM PDT 24
Peak memory 206372 kb
Host smart-87a7f937-45fe-493a-a179-7ac856389c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26369
01105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2636901105
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3856450091
Short name T1096
Test name
Test status
Simulation time 242428525 ps
CPU time 0.96 seconds
Started Jul 10 06:42:06 PM PDT 24
Finished Jul 10 06:42:10 PM PDT 24
Peak memory 206376 kb
Host smart-db9f0d5d-dec2-49b2-a62a-7bf7361322aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38564
50091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3856450091
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2602747582
Short name T1648
Test name
Test status
Simulation time 5031971826 ps
CPU time 35.7 seconds
Started Jul 10 06:42:07 PM PDT 24
Finished Jul 10 06:42:46 PM PDT 24
Peak memory 206660 kb
Host smart-0a6bab35-45ad-422b-805d-ab66318afbb8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2602747582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2602747582
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.3705848377
Short name T111
Test name
Test status
Simulation time 8875191119 ps
CPU time 32.45 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:39 PM PDT 24
Peak memory 206892 kb
Host smart-2a0f04b2-84bb-4038-8748-54e68c02b31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37058
48377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3705848377
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3762027501
Short name T2263
Test name
Test status
Simulation time 220039778 ps
CPU time 0.87 seconds
Started Jul 10 06:42:06 PM PDT 24
Finished Jul 10 06:42:10 PM PDT 24
Peak memory 206372 kb
Host smart-b450f3fd-379b-4545-919c-976c659f39c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37620
27501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3762027501
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.2986513912
Short name T1139
Test name
Test status
Simulation time 23350843300 ps
CPU time 21.76 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:30 PM PDT 24
Peak memory 206436 kb
Host smart-65848d34-a282-4ac8-a744-35288f701560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29865
13912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.2986513912
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.4240398422
Short name T18
Test name
Test status
Simulation time 3330157367 ps
CPU time 3.9 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:42:15 PM PDT 24
Peak memory 206468 kb
Host smart-84f3a90a-e849-48df-aa08-01a3ad78884a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
98422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.4240398422
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1430325
Short name T615
Test name
Test status
Simulation time 5705035403 ps
CPU time 53.84 seconds
Started Jul 10 06:42:06 PM PDT 24
Finished Jul 10 06:43:02 PM PDT 24
Peak memory 206676 kb
Host smart-84ef473e-6843-4097-bf77-a95292ea05b7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1430325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1430325
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2287066889
Short name T493
Test name
Test status
Simulation time 242036129 ps
CPU time 0.92 seconds
Started Jul 10 06:42:08 PM PDT 24
Finished Jul 10 06:42:13 PM PDT 24
Peak memory 206064 kb
Host smart-a07cd0f5-a4b9-4435-b50d-5cb10c2e46c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2287066889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2287066889
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2298650801
Short name T881
Test name
Test status
Simulation time 187939211 ps
CPU time 0.87 seconds
Started Jul 10 06:42:04 PM PDT 24
Finished Jul 10 06:42:08 PM PDT 24
Peak memory 206312 kb
Host smart-d6de6262-0a91-4e34-9933-37e0e7d628dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22986
50801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2298650801
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1114254061
Short name T1890
Test name
Test status
Simulation time 5279693683 ps
CPU time 38.21 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:45 PM PDT 24
Peak memory 206632 kb
Host smart-9bb68cea-97b4-4506-8011-e8c8cb1cb349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11142
54061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1114254061
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1451746796
Short name T324
Test name
Test status
Simulation time 7289878377 ps
CPU time 51.71 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:59 PM PDT 24
Peak memory 206680 kb
Host smart-84e0488c-d87b-4ce4-9197-712ceddf2c1f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1451746796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1451746796
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.205710232
Short name T1649
Test name
Test status
Simulation time 159200330 ps
CPU time 0.82 seconds
Started Jul 10 06:42:03 PM PDT 24
Finished Jul 10 06:42:05 PM PDT 24
Peak memory 206380 kb
Host smart-b2277dcd-2b59-4f7a-97f6-c75944e569a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=205710232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.205710232
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3719628562
Short name T2640
Test name
Test status
Simulation time 158097631 ps
CPU time 0.82 seconds
Started Jul 10 06:42:05 PM PDT 24
Finished Jul 10 06:42:09 PM PDT 24
Peak memory 206380 kb
Host smart-b60a3d11-f156-40df-b89e-83329bf18d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37196
28562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3719628562
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.4019541685
Short name T1062
Test name
Test status
Simulation time 182476322 ps
CPU time 0.88 seconds
Started Jul 10 06:42:17 PM PDT 24
Finished Jul 10 06:42:20 PM PDT 24
Peak memory 206376 kb
Host smart-e61b1952-1895-4934-ad63-fba76f152472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
41685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.4019541685
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1342256484
Short name T2280
Test name
Test status
Simulation time 178148603 ps
CPU time 0.8 seconds
Started Jul 10 06:42:15 PM PDT 24
Finished Jul 10 06:42:18 PM PDT 24
Peak memory 206392 kb
Host smart-560b3f5c-6a9d-46a9-8112-6b4a043acebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13422
56484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1342256484
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.4107413342
Short name T407
Test name
Test status
Simulation time 157745292 ps
CPU time 0.81 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:26 PM PDT 24
Peak memory 206400 kb
Host smart-a6c9ba50-35d4-4695-ad0c-ef78109513d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41074
13342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4107413342
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3701907037
Short name T385
Test name
Test status
Simulation time 170547837 ps
CPU time 0.81 seconds
Started Jul 10 06:42:15 PM PDT 24
Finished Jul 10 06:42:18 PM PDT 24
Peak memory 206560 kb
Host smart-852063ca-629e-4035-9647-8e14dbb4ca5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
07037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3701907037
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3858263408
Short name T1900
Test name
Test status
Simulation time 154075356 ps
CPU time 0.77 seconds
Started Jul 10 06:42:17 PM PDT 24
Finished Jul 10 06:42:19 PM PDT 24
Peak memory 206404 kb
Host smart-feb3ac0f-1b37-42ea-884b-9d24e6e9a987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582
63408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3858263408
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2133620338
Short name T371
Test name
Test status
Simulation time 205922729 ps
CPU time 0.91 seconds
Started Jul 10 06:42:20 PM PDT 24
Finished Jul 10 06:42:22 PM PDT 24
Peak memory 205340 kb
Host smart-da31c365-0e5a-43f2-a07c-86d3c17b509d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2133620338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2133620338
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3902862960
Short name T2313
Test name
Test status
Simulation time 179063183 ps
CPU time 0.79 seconds
Started Jul 10 06:42:20 PM PDT 24
Finished Jul 10 06:42:22 PM PDT 24
Peak memory 205308 kb
Host smart-6e2ec91e-4168-4bfd-ab41-ed89b68b2154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39028
62960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3902862960
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.378977100
Short name T780
Test name
Test status
Simulation time 39694144 ps
CPU time 0.67 seconds
Started Jul 10 06:42:15 PM PDT 24
Finished Jul 10 06:42:17 PM PDT 24
Peak memory 206272 kb
Host smart-7285845f-da6f-4ce6-be7b-a8e8ce8464b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37897
7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.378977100
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1380552220
Short name T675
Test name
Test status
Simulation time 13590716556 ps
CPU time 31.6 seconds
Started Jul 10 06:42:15 PM PDT 24
Finished Jul 10 06:42:48 PM PDT 24
Peak memory 206700 kb
Host smart-3744535f-918d-43e8-92a3-0d24b7fca080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13805
52220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1380552220
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3662476308
Short name T1360
Test name
Test status
Simulation time 183080085 ps
CPU time 0.81 seconds
Started Jul 10 06:42:15 PM PDT 24
Finished Jul 10 06:42:17 PM PDT 24
Peak memory 206376 kb
Host smart-ced736fa-8a14-48e5-924a-43a8554fb504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36624
76308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3662476308
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1779698687
Short name T2636
Test name
Test status
Simulation time 166499559 ps
CPU time 0.83 seconds
Started Jul 10 06:42:14 PM PDT 24
Finished Jul 10 06:42:17 PM PDT 24
Peak memory 206368 kb
Host smart-c17441eb-2996-4e57-82c1-324af926dc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
98687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1779698687
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.2343016757
Short name T1333
Test name
Test status
Simulation time 176389801 ps
CPU time 0.82 seconds
Started Jul 10 06:42:14 PM PDT 24
Finished Jul 10 06:42:17 PM PDT 24
Peak memory 206396 kb
Host smart-6532177d-bf98-46f4-825d-6f7d18efa73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
16757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.2343016757
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.400763539
Short name T315
Test name
Test status
Simulation time 158671157 ps
CPU time 0.84 seconds
Started Jul 10 06:42:16 PM PDT 24
Finished Jul 10 06:42:19 PM PDT 24
Peak memory 206388 kb
Host smart-5cb703dd-f137-4da8-9aa6-17c57066422c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40076
3539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.400763539
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1830954628
Short name T532
Test name
Test status
Simulation time 162240116 ps
CPU time 0.83 seconds
Started Jul 10 06:42:17 PM PDT 24
Finished Jul 10 06:42:19 PM PDT 24
Peak memory 206276 kb
Host smart-68f025ae-0097-4028-995a-79dd026b2fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18309
54628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1830954628
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.4191758692
Short name T2139
Test name
Test status
Simulation time 177578783 ps
CPU time 0.84 seconds
Started Jul 10 06:42:17 PM PDT 24
Finished Jul 10 06:42:19 PM PDT 24
Peak memory 206376 kb
Host smart-75a8c602-466c-4d52-a439-61386fcd8731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
58692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.4191758692
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2028958490
Short name T2202
Test name
Test status
Simulation time 163001215 ps
CPU time 0.8 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:42:23 PM PDT 24
Peak memory 206376 kb
Host smart-dcdd3555-bb11-41ac-a1ef-d7f142991d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20289
58490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2028958490
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3326217409
Short name T1272
Test name
Test status
Simulation time 237304524 ps
CPU time 0.93 seconds
Started Jul 10 06:42:15 PM PDT 24
Finished Jul 10 06:42:18 PM PDT 24
Peak memory 206376 kb
Host smart-b83c49ed-01d6-4a49-8dcf-1a80a4bff7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33262
17409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3326217409
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3689833736
Short name T2037
Test name
Test status
Simulation time 6623038669 ps
CPU time 66.44 seconds
Started Jul 10 06:42:16 PM PDT 24
Finished Jul 10 06:43:25 PM PDT 24
Peak memory 206700 kb
Host smart-1ab2f932-1878-48e1-967b-51845ad4c294
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3689833736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3689833736
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2209966300
Short name T1284
Test name
Test status
Simulation time 173693409 ps
CPU time 0.81 seconds
Started Jul 10 06:42:16 PM PDT 24
Finished Jul 10 06:42:19 PM PDT 24
Peak memory 206400 kb
Host smart-03fe7e51-d693-4d52-b1ce-96e13d368f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22099
66300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2209966300
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2483520316
Short name T746
Test name
Test status
Simulation time 181329294 ps
CPU time 0.81 seconds
Started Jul 10 06:42:14 PM PDT 24
Finished Jul 10 06:42:17 PM PDT 24
Peak memory 206376 kb
Host smart-d63d186d-0434-4b1f-9124-68841347acd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24835
20316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2483520316
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3417529675
Short name T17
Test name
Test status
Simulation time 588036402 ps
CPU time 1.46 seconds
Started Jul 10 06:42:17 PM PDT 24
Finished Jul 10 06:42:20 PM PDT 24
Peak memory 206392 kb
Host smart-e2330ead-b6b7-4546-9621-18922308505d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34175
29675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3417529675
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3469634367
Short name T2360
Test name
Test status
Simulation time 4248651370 ps
CPU time 28.9 seconds
Started Jul 10 06:42:15 PM PDT 24
Finished Jul 10 06:42:46 PM PDT 24
Peak memory 206632 kb
Host smart-8dc66483-17e8-48fd-bf01-a1ab23b38d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34696
34367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3469634367
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3841557789
Short name T30
Test name
Test status
Simulation time 49467710 ps
CPU time 0.66 seconds
Started Jul 10 06:42:25 PM PDT 24
Finished Jul 10 06:42:31 PM PDT 24
Peak memory 205960 kb
Host smart-dd20680d-cbe5-410b-bc7c-5fb7d5c3dd38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3841557789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3841557789
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.374141816
Short name T1461
Test name
Test status
Simulation time 4198000183 ps
CPU time 4.7 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:30 PM PDT 24
Peak memory 206420 kb
Host smart-7ab012b1-4073-4fd3-a93d-6ec5014e2a60
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=374141816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.374141816
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2551014639
Short name T2002
Test name
Test status
Simulation time 13316816601 ps
CPU time 15.69 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:42 PM PDT 24
Peak memory 206428 kb
Host smart-01db5933-0d70-40d4-b1ca-4e7247705c19
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2551014639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2551014639
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3555471362
Short name T1723
Test name
Test status
Simulation time 23330418963 ps
CPU time 21.64 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:49 PM PDT 24
Peak memory 206664 kb
Host smart-479683cf-9a3b-421f-aabd-bf128f36a9a6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3555471362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3555471362
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.4002977756
Short name T852
Test name
Test status
Simulation time 153443231 ps
CPU time 0.76 seconds
Started Jul 10 06:42:28 PM PDT 24
Finished Jul 10 06:42:34 PM PDT 24
Peak memory 206384 kb
Host smart-d1cfd813-dd05-49e2-8232-62697c1cbba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029
77756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.4002977756
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.3956566414
Short name T66
Test name
Test status
Simulation time 176843339 ps
CPU time 0.77 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:42:25 PM PDT 24
Peak memory 206308 kb
Host smart-71fd1557-0202-4055-982f-bff06b5c25ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39565
66414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.3956566414
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.174473323
Short name T1013
Test name
Test status
Simulation time 277452019 ps
CPU time 1.08 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:42:25 PM PDT 24
Peak memory 206568 kb
Host smart-0a58e67b-a079-4d6e-82eb-fb63b034b2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17447
3323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.174473323
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1699637386
Short name T481
Test name
Test status
Simulation time 335326598 ps
CPU time 1.01 seconds
Started Jul 10 06:42:25 PM PDT 24
Finished Jul 10 06:42:32 PM PDT 24
Peak memory 205844 kb
Host smart-ed73894b-75cf-4a9d-9142-32770213d39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16996
37386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1699637386
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2211808474
Short name T893
Test name
Test status
Simulation time 9492142974 ps
CPU time 17.54 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:45 PM PDT 24
Peak memory 206656 kb
Host smart-a6aea2b3-9cdd-4ca5-8798-0f7c87c5496d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22118
08474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2211808474
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2417339704
Short name T1436
Test name
Test status
Simulation time 238995685 ps
CPU time 0.95 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:27 PM PDT 24
Peak memory 206380 kb
Host smart-ad3c6e8a-2761-4f4b-9cb6-15b5ce7bcc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24173
39704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2417339704
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3909261602
Short name T1270
Test name
Test status
Simulation time 37776227 ps
CPU time 0.68 seconds
Started Jul 10 06:42:20 PM PDT 24
Finished Jul 10 06:42:21 PM PDT 24
Peak memory 206396 kb
Host smart-45823541-63f1-4f6f-a928-b8de94e75589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39092
61602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3909261602
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.117912218
Short name T1433
Test name
Test status
Simulation time 882737315 ps
CPU time 2.21 seconds
Started Jul 10 06:42:24 PM PDT 24
Finished Jul 10 06:42:32 PM PDT 24
Peak memory 206680 kb
Host smart-60584869-c59f-47f3-96a4-1e9690c06fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11791
2218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.117912218
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2770225162
Short name T1563
Test name
Test status
Simulation time 291492868 ps
CPU time 1.79 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:28 PM PDT 24
Peak memory 206568 kb
Host smart-ed210bcb-5ca3-413f-b5d6-161c285ba5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
25162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2770225162
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2472840362
Short name T1993
Test name
Test status
Simulation time 241495818 ps
CPU time 0.98 seconds
Started Jul 10 06:42:27 PM PDT 24
Finished Jul 10 06:42:33 PM PDT 24
Peak memory 206404 kb
Host smart-7a3b112b-753a-4d0f-b93f-383b4108fc42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24728
40362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2472840362
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1081385496
Short name T1888
Test name
Test status
Simulation time 213940561 ps
CPU time 0.83 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:26 PM PDT 24
Peak memory 206388 kb
Host smart-ad691735-6256-4313-97e7-2c7d6501bfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10813
85496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1081385496
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3479284760
Short name T2598
Test name
Test status
Simulation time 245446610 ps
CPU time 1.01 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206388 kb
Host smart-904fb8ff-ac77-47ea-9cc8-3f2925284804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34792
84760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3479284760
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.2599822200
Short name T820
Test name
Test status
Simulation time 10191229306 ps
CPU time 32.21 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:42:54 PM PDT 24
Peak memory 206696 kb
Host smart-d4c5d0e8-ca00-40ae-90da-64dde66a1657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25998
22200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2599822200
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.646804269
Short name T2713
Test name
Test status
Simulation time 213361003 ps
CPU time 0.85 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:42:35 PM PDT 24
Peak memory 206372 kb
Host smart-7b43d505-944e-429b-9a83-a23ee9ada3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64680
4269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.646804269
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.49518508
Short name T2474
Test name
Test status
Simulation time 23328356503 ps
CPU time 26.42 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:51 PM PDT 24
Peak memory 206436 kb
Host smart-18a794e5-93c8-4ab6-8687-85471d71c8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49518
508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.49518508
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1992972395
Short name T1463
Test name
Test status
Simulation time 3273101244 ps
CPU time 4.13 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:31 PM PDT 24
Peak memory 206440 kb
Host smart-2921ae40-deb5-4f1a-afb4-984dbc2da32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
72395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1992972395
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3568897009
Short name T2341
Test name
Test status
Simulation time 10994091521 ps
CPU time 303.31 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:47:27 PM PDT 24
Peak memory 206636 kb
Host smart-18c461a5-4678-42d0-88d1-179106f44c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35688
97009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3568897009
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.3250234201
Short name T2632
Test name
Test status
Simulation time 7863442523 ps
CPU time 58.73 seconds
Started Jul 10 06:42:24 PM PDT 24
Finished Jul 10 06:43:27 PM PDT 24
Peak memory 206360 kb
Host smart-afb3fab3-5b15-44c4-bff2-9fc4abec4757
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3250234201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.3250234201
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3553835945
Short name T1141
Test name
Test status
Simulation time 316939896 ps
CPU time 0.93 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206372 kb
Host smart-dd7acac4-e56f-494a-aadf-a9590b021a42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3553835945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3553835945
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.840811680
Short name T2086
Test name
Test status
Simulation time 200088074 ps
CPU time 0.86 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:26 PM PDT 24
Peak memory 206364 kb
Host smart-c3bb3a1a-da53-464d-9fac-d8ba74b9b693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84081
1680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.840811680
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.1531734688
Short name T445
Test name
Test status
Simulation time 4354477807 ps
CPU time 41.48 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206616 kb
Host smart-69ff44cb-b5bb-4b1f-96f9-24607f663a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15317
34688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.1531734688
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3533912394
Short name T1752
Test name
Test status
Simulation time 5305342764 ps
CPU time 144.74 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:44:52 PM PDT 24
Peak memory 206620 kb
Host smart-ed2838ab-d94c-467f-87f8-9fbe5a985cb2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3533912394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3533912394
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.780665550
Short name T2174
Test name
Test status
Simulation time 154752326 ps
CPU time 0.79 seconds
Started Jul 10 06:42:28 PM PDT 24
Finished Jul 10 06:42:33 PM PDT 24
Peak memory 206392 kb
Host smart-e7f20899-e7d1-4e31-b884-cb4686ee6c1e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=780665550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.780665550
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2292300605
Short name T858
Test name
Test status
Simulation time 156940954 ps
CPU time 0.81 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206396 kb
Host smart-a1eae0c9-cd98-44c6-9fd3-102924dba241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22923
00605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2292300605
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2231378082
Short name T118
Test name
Test status
Simulation time 184261419 ps
CPU time 0.83 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:28 PM PDT 24
Peak memory 206400 kb
Host smart-8cfd60aa-0be5-4bfa-8fd9-bc0fae69991a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22313
78082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2231378082
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2865468851
Short name T600
Test name
Test status
Simulation time 223462096 ps
CPU time 0.92 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206076 kb
Host smart-b66dca1c-f307-4e61-bb7b-70fc8844c3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28654
68851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2865468851
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1989534439
Short name T499
Test name
Test status
Simulation time 208537972 ps
CPU time 0.88 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:26 PM PDT 24
Peak memory 206280 kb
Host smart-aeaa11e6-3fa1-4476-b4dd-cfd4332b9382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
34439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1989534439
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1215319171
Short name T1489
Test name
Test status
Simulation time 183666967 ps
CPU time 0.81 seconds
Started Jul 10 06:42:25 PM PDT 24
Finished Jul 10 06:42:31 PM PDT 24
Peak memory 206384 kb
Host smart-b6dda367-9469-461a-9ef0-e21826439e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12153
19171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1215319171
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1209929208
Short name T1186
Test name
Test status
Simulation time 164456854 ps
CPU time 0.8 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:27 PM PDT 24
Peak memory 206380 kb
Host smart-678e2c02-ed5a-4cf9-8e64-a43ebad1da64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12099
29208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1209929208
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1834275686
Short name T421
Test name
Test status
Simulation time 239029728 ps
CPU time 1.01 seconds
Started Jul 10 06:42:24 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206400 kb
Host smart-3dff5ae9-f09d-4105-a9be-0b7b2fab12d3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1834275686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1834275686
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1938674339
Short name T2239
Test name
Test status
Simulation time 200198861 ps
CPU time 0.81 seconds
Started Jul 10 06:42:20 PM PDT 24
Finished Jul 10 06:42:23 PM PDT 24
Peak memory 206364 kb
Host smart-bc4d7501-594a-444e-a41c-f28fdfc8f858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19386
74339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1938674339
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2342558112
Short name T2481
Test name
Test status
Simulation time 58436867 ps
CPU time 0.71 seconds
Started Jul 10 06:42:24 PM PDT 24
Finished Jul 10 06:42:30 PM PDT 24
Peak memory 206368 kb
Host smart-988f3b93-0993-475f-a6cb-f6bdf7a26066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23425
58112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2342558112
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.161808490
Short name T1533
Test name
Test status
Simulation time 13678202097 ps
CPU time 29.5 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:56 PM PDT 24
Peak memory 206724 kb
Host smart-29203c09-565d-4287-b424-4b61707ae4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
8490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.161808490
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1281401925
Short name T529
Test name
Test status
Simulation time 164804060 ps
CPU time 0.83 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:28 PM PDT 24
Peak memory 206388 kb
Host smart-fe52573d-47ff-40f3-9afb-58b7bb0b5f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12814
01925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1281401925
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3590800014
Short name T1255
Test name
Test status
Simulation time 218400974 ps
CPU time 0.86 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:27 PM PDT 24
Peak memory 206372 kb
Host smart-44225c4c-4b68-4266-b4e2-dd6300b33d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35908
00014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3590800014
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.246039203
Short name T940
Test name
Test status
Simulation time 232160190 ps
CPU time 0.87 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206376 kb
Host smart-54fb8672-88f0-4dc5-9753-413ca79fbbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24603
9203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.246039203
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1062251227
Short name T713
Test name
Test status
Simulation time 166853515 ps
CPU time 0.82 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:42:23 PM PDT 24
Peak memory 206396 kb
Host smart-89a9b15a-17ca-4baa-afda-2edf3e14ff7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10622
51227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1062251227
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2911475388
Short name T794
Test name
Test status
Simulation time 141361779 ps
CPU time 0.77 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:26 PM PDT 24
Peak memory 206372 kb
Host smart-79193b90-ba22-4601-9706-d95c621882df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29114
75388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2911475388
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2790345509
Short name T695
Test name
Test status
Simulation time 186654243 ps
CPU time 0.8 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:28 PM PDT 24
Peak memory 206376 kb
Host smart-5f9c89b3-44c6-4254-a721-feb6fafe88da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27903
45509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2790345509
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3235746435
Short name T99
Test name
Test status
Simulation time 182084430 ps
CPU time 0.8 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:42:24 PM PDT 24
Peak memory 206380 kb
Host smart-e54d8d38-379e-4e01-92f3-1b96688e04fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32357
46435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3235746435
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1065445126
Short name T2379
Test name
Test status
Simulation time 208256204 ps
CPU time 1.03 seconds
Started Jul 10 06:42:24 PM PDT 24
Finished Jul 10 06:42:30 PM PDT 24
Peak memory 206376 kb
Host smart-81f31d4a-f3c2-49c7-9c80-f625d85fbf1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10654
45126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1065445126
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3424968716
Short name T2611
Test name
Test status
Simulation time 4034797286 ps
CPU time 27.88 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:42:51 PM PDT 24
Peak memory 206688 kb
Host smart-6bac54a2-bde9-47cf-8709-f65e8200e8c0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3424968716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3424968716
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.386424260
Short name T2
Test name
Test status
Simulation time 183484572 ps
CPU time 0.88 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206392 kb
Host smart-7365fbef-f3e2-4f6d-a010-5f9ca577ae57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38642
4260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.386424260
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3645443600
Short name T1035
Test name
Test status
Simulation time 181124393 ps
CPU time 0.83 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206372 kb
Host smart-7268671a-a69c-4dd4-9870-629938a9a8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36454
43600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3645443600
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2345110050
Short name T1265
Test name
Test status
Simulation time 345842993 ps
CPU time 1.03 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206380 kb
Host smart-1d5887bc-2480-4610-8b5a-842d438db195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
10050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2345110050
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3128444512
Short name T1472
Test name
Test status
Simulation time 7729314328 ps
CPU time 51.66 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:43:18 PM PDT 24
Peak memory 206704 kb
Host smart-bc782e92-5ca6-439a-88f0-3abcac1acf4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
44512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3128444512
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.4127808585
Short name T1920
Test name
Test status
Simulation time 45899825 ps
CPU time 0.7 seconds
Started Jul 10 06:42:30 PM PDT 24
Finished Jul 10 06:42:35 PM PDT 24
Peak memory 206440 kb
Host smart-9b6dc4f2-8b9a-44dd-b3a0-654e2c76dd9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4127808585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.4127808585
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1627177952
Short name T1857
Test name
Test status
Simulation time 13322247515 ps
CPU time 11.67 seconds
Started Jul 10 06:42:24 PM PDT 24
Finished Jul 10 06:42:40 PM PDT 24
Peak memory 206644 kb
Host smart-1d6aa573-e68c-43d0-ac8b-755427c3ff7d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1627177952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1627177952
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2470694931
Short name T1519
Test name
Test status
Simulation time 23400305765 ps
CPU time 24.96 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:51 PM PDT 24
Peak memory 206720 kb
Host smart-3bc6e4ce-0dc6-4477-9d42-8aea5149c2d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2470694931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.2470694931
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3134687156
Short name T2438
Test name
Test status
Simulation time 155584150 ps
CPU time 0.83 seconds
Started Jul 10 06:42:24 PM PDT 24
Finished Jul 10 06:42:30 PM PDT 24
Peak memory 206380 kb
Host smart-88ca5e3c-24e4-49fe-90aa-9af06de8538c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31346
87156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3134687156
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1750449005
Short name T2561
Test name
Test status
Simulation time 140358402 ps
CPU time 0.79 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206388 kb
Host smart-7a19582e-ad62-4c0b-82e2-c631d042ded7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17504
49005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1750449005
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.386019467
Short name T2348
Test name
Test status
Simulation time 224053010 ps
CPU time 0.95 seconds
Started Jul 10 06:42:25 PM PDT 24
Finished Jul 10 06:42:31 PM PDT 24
Peak memory 206384 kb
Host smart-cc4d256d-e40c-4d6c-a696-41ddc6d43a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38601
9467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.386019467
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2538047304
Short name T2293
Test name
Test status
Simulation time 1516352444 ps
CPU time 3.16 seconds
Started Jul 10 06:42:21 PM PDT 24
Finished Jul 10 06:42:27 PM PDT 24
Peak memory 206624 kb
Host smart-d9bb1192-b83f-4c62-866c-9dad42dda313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
47304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2538047304
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.948948131
Short name T1248
Test name
Test status
Simulation time 12202698405 ps
CPU time 21.79 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:42:56 PM PDT 24
Peak memory 206724 kb
Host smart-df6b0cbf-3f12-41b3-bfff-726588fbc85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94894
8131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.948948131
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1788303649
Short name T1518
Test name
Test status
Simulation time 461598638 ps
CPU time 1.48 seconds
Started Jul 10 06:42:32 PM PDT 24
Finished Jul 10 06:42:37 PM PDT 24
Peak memory 206312 kb
Host smart-f6f2838b-bc19-4cd7-b907-ad0ccf666b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17883
03649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1788303649
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.922931442
Short name T1198
Test name
Test status
Simulation time 140532225 ps
CPU time 0.78 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:27 PM PDT 24
Peak memory 206364 kb
Host smart-e68b0000-2485-49fd-9468-f6fe15d079d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92293
1442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.922931442
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3801552477
Short name T1544
Test name
Test status
Simulation time 35028997 ps
CPU time 0.63 seconds
Started Jul 10 06:42:22 PM PDT 24
Finished Jul 10 06:42:25 PM PDT 24
Peak memory 206296 kb
Host smart-508b1016-1ef3-4088-a56a-f985970e1cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38015
52477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3801552477
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.852314062
Short name T706
Test name
Test status
Simulation time 968096972 ps
CPU time 2.11 seconds
Started Jul 10 06:42:23 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206584 kb
Host smart-29195261-358f-4a5c-9c9d-35beaa6d41c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85231
4062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.852314062
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2252944899
Short name T183
Test name
Test status
Simulation time 220148879 ps
CPU time 1.41 seconds
Started Jul 10 06:42:30 PM PDT 24
Finished Jul 10 06:42:36 PM PDT 24
Peak memory 206656 kb
Host smart-e818f241-ae98-4c63-95c5-2dd9c8fcc9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22529
44899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2252944899
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2356374422
Short name T671
Test name
Test status
Simulation time 238152010 ps
CPU time 0.95 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:42:35 PM PDT 24
Peak memory 206392 kb
Host smart-1b97f3b3-698f-4a02-b92a-bde066a409a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23563
74422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2356374422
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1004404253
Short name T1756
Test name
Test status
Simulation time 150341326 ps
CPU time 0.79 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:42:35 PM PDT 24
Peak memory 206376 kb
Host smart-11b11487-c7fb-4edd-8228-3890a5a71730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10044
04253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1004404253
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1246482073
Short name T2336
Test name
Test status
Simulation time 172047873 ps
CPU time 0.83 seconds
Started Jul 10 06:42:30 PM PDT 24
Finished Jul 10 06:42:35 PM PDT 24
Peak memory 206280 kb
Host smart-c98e5933-8658-4437-a2ea-a91b07215e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12464
82073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1246482073
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.4218307347
Short name T536
Test name
Test status
Simulation time 4863548231 ps
CPU time 15.47 seconds
Started Jul 10 06:42:28 PM PDT 24
Finished Jul 10 06:42:48 PM PDT 24
Peak memory 206624 kb
Host smart-6c526982-3b59-4a8d-a25c-ffb4f3696938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42183
07347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.4218307347
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.1906063371
Short name T1503
Test name
Test status
Simulation time 208757856 ps
CPU time 0.86 seconds
Started Jul 10 06:42:33 PM PDT 24
Finished Jul 10 06:42:37 PM PDT 24
Peak memory 206376 kb
Host smart-a02f2c53-d867-43d0-8fff-2531dd75eb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19060
63371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1906063371
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.198734025
Short name T2590
Test name
Test status
Simulation time 23318682642 ps
CPU time 27.71 seconds
Started Jul 10 06:42:34 PM PDT 24
Finished Jul 10 06:43:04 PM PDT 24
Peak memory 206448 kb
Host smart-fb91a74c-6c6d-4a72-9b30-47c09efff62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19873
4025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.198734025
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.764183013
Short name T2048
Test name
Test status
Simulation time 3280353677 ps
CPU time 4.63 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:42:38 PM PDT 24
Peak memory 206624 kb
Host smart-a6c6463a-4dec-472a-8f38-1664d987043e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76418
3013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.764183013
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3897279976
Short name T226
Test name
Test status
Simulation time 6225051553 ps
CPU time 60.45 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:43:34 PM PDT 24
Peak memory 206716 kb
Host smart-662e2088-c228-4b36-ae0a-15dff805a002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38972
79976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3897279976
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.591894417
Short name T314
Test name
Test status
Simulation time 4911266648 ps
CPU time 131.52 seconds
Started Jul 10 06:42:31 PM PDT 24
Finished Jul 10 06:44:46 PM PDT 24
Peak memory 206640 kb
Host smart-7380f17e-84db-4a00-a6da-a869e8d30ef5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=591894417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.591894417
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.940737466
Short name T328
Test name
Test status
Simulation time 274241705 ps
CPU time 0.96 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:42:35 PM PDT 24
Peak memory 206368 kb
Host smart-e15ce9c6-adf3-4fe6-b205-66db28c1c37b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=940737466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.940737466
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.390369597
Short name T1085
Test name
Test status
Simulation time 200179475 ps
CPU time 0.86 seconds
Started Jul 10 06:42:28 PM PDT 24
Finished Jul 10 06:42:34 PM PDT 24
Peak memory 206376 kb
Host smart-9a0cd88a-52ef-4bdb-92bf-d45f821b98e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39036
9597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.390369597
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.2963019921
Short name T768
Test name
Test status
Simulation time 4696826774 ps
CPU time 44.74 seconds
Started Jul 10 06:42:31 PM PDT 24
Finished Jul 10 06:43:20 PM PDT 24
Peak memory 206676 kb
Host smart-fda599fc-2574-428a-8216-a0c23674cb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
19921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.2963019921
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1919572770
Short name T909
Test name
Test status
Simulation time 5150596430 ps
CPU time 48.42 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:43:22 PM PDT 24
Peak memory 206640 kb
Host smart-a97a3028-37d2-4ddc-a7fc-fa69f3337e26
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1919572770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1919572770
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.4126284474
Short name T2596
Test name
Test status
Simulation time 198027524 ps
CPU time 0.82 seconds
Started Jul 10 06:42:32 PM PDT 24
Finished Jul 10 06:42:37 PM PDT 24
Peak memory 206392 kb
Host smart-254860ca-7259-4468-8ce3-5f01c5b2d72d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4126284474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.4126284474
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2715305572
Short name T849
Test name
Test status
Simulation time 139026240 ps
CPU time 0.74 seconds
Started Jul 10 06:42:31 PM PDT 24
Finished Jul 10 06:42:36 PM PDT 24
Peak memory 206384 kb
Host smart-9147ce85-9ff6-43e9-936d-c15a9c3b0655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27153
05572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2715305572
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.1724175382
Short name T634
Test name
Test status
Simulation time 197206089 ps
CPU time 0.88 seconds
Started Jul 10 06:42:32 PM PDT 24
Finished Jul 10 06:42:36 PM PDT 24
Peak memory 206380 kb
Host smart-a600a6ef-7a96-4667-b483-2e1294a1f4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
75382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.1724175382
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1583960146
Short name T2740
Test name
Test status
Simulation time 169634276 ps
CPU time 0.88 seconds
Started Jul 10 06:42:32 PM PDT 24
Finished Jul 10 06:42:37 PM PDT 24
Peak memory 206388 kb
Host smart-5ca1baf3-6030-447b-8108-d22716cc132d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15839
60146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1583960146
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3769952653
Short name T1688
Test name
Test status
Simulation time 225499766 ps
CPU time 0.81 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:40 PM PDT 24
Peak memory 206392 kb
Host smart-1ebc20c7-a0f5-48de-9f07-aa4e5e872c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37699
52653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3769952653
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1628435269
Short name T1546
Test name
Test status
Simulation time 154945585 ps
CPU time 0.78 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:42:34 PM PDT 24
Peak memory 206372 kb
Host smart-bfb9290f-2775-4ea7-acdc-bc8d092fb422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16284
35269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1628435269
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.436118610
Short name T391
Test name
Test status
Simulation time 210597696 ps
CPU time 0.91 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206396 kb
Host smart-8c54648a-1485-4c8e-b44f-fe6ba5b2683a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=436118610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.436118610
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3712824319
Short name T190
Test name
Test status
Simulation time 145189351 ps
CPU time 0.78 seconds
Started Jul 10 06:42:31 PM PDT 24
Finished Jul 10 06:42:36 PM PDT 24
Peak memory 206404 kb
Host smart-1ef8840f-1afd-4a20-bd38-3f414f27cc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37128
24319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3712824319
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3264090365
Short name T670
Test name
Test status
Simulation time 54922493 ps
CPU time 0.7 seconds
Started Jul 10 06:42:31 PM PDT 24
Finished Jul 10 06:42:36 PM PDT 24
Peak memory 206396 kb
Host smart-3f48a43f-c056-44f2-b021-6bcda54970e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32640
90365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3264090365
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1176429721
Short name T2295
Test name
Test status
Simulation time 22101378432 ps
CPU time 53.1 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:43:27 PM PDT 24
Peak memory 206704 kb
Host smart-d6c96e5b-2d9c-4fd7-b220-1ee5852670f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11764
29721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1176429721
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1237404206
Short name T290
Test name
Test status
Simulation time 153537658 ps
CPU time 0.78 seconds
Started Jul 10 06:42:32 PM PDT 24
Finished Jul 10 06:42:37 PM PDT 24
Peak memory 206372 kb
Host smart-54ddf9cd-aad8-4525-ad6d-5cd4b343709a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12374
04206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1237404206
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2954718907
Short name T482
Test name
Test status
Simulation time 228608473 ps
CPU time 0.92 seconds
Started Jul 10 06:42:30 PM PDT 24
Finished Jul 10 06:42:35 PM PDT 24
Peak memory 206352 kb
Host smart-2d541145-5e7f-4153-b610-3529b42c10a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29547
18907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2954718907
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2037253681
Short name T1793
Test name
Test status
Simulation time 192232837 ps
CPU time 0.81 seconds
Started Jul 10 06:42:31 PM PDT 24
Finished Jul 10 06:42:36 PM PDT 24
Peak memory 206396 kb
Host smart-409c9ebe-7618-40e2-a0ca-6d10ae12656d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20372
53681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2037253681
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2132782945
Short name T2167
Test name
Test status
Simulation time 163485222 ps
CPU time 0.8 seconds
Started Jul 10 06:42:34 PM PDT 24
Finished Jul 10 06:42:38 PM PDT 24
Peak memory 206384 kb
Host smart-7b8be708-e002-4201-958b-d0a546b82582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21327
82945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2132782945
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3915661683
Short name T446
Test name
Test status
Simulation time 216945608 ps
CPU time 0.85 seconds
Started Jul 10 06:42:44 PM PDT 24
Finished Jul 10 06:42:48 PM PDT 24
Peak memory 206300 kb
Host smart-f0508428-a8e3-4291-90e3-918043b9c3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39156
61683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3915661683
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3548276701
Short name T770
Test name
Test status
Simulation time 184395324 ps
CPU time 0.82 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:40 PM PDT 24
Peak memory 206388 kb
Host smart-c0d09dd3-cafb-4ede-ac3e-4ad7a8a83f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35482
76701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3548276701
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1768495739
Short name T779
Test name
Test status
Simulation time 155915800 ps
CPU time 0.79 seconds
Started Jul 10 06:42:28 PM PDT 24
Finished Jul 10 06:42:34 PM PDT 24
Peak memory 206380 kb
Host smart-a0000e35-83ca-4277-bdf7-8af354a4622a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
95739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1768495739
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3637658702
Short name T997
Test name
Test status
Simulation time 218757053 ps
CPU time 0.99 seconds
Started Jul 10 06:42:34 PM PDT 24
Finished Jul 10 06:42:38 PM PDT 24
Peak memory 206388 kb
Host smart-b0c02546-210f-4d42-9545-f35b8b664725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36376
58702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3637658702
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3741420822
Short name T1554
Test name
Test status
Simulation time 5481840141 ps
CPU time 54.7 seconds
Started Jul 10 06:42:33 PM PDT 24
Finished Jul 10 06:43:31 PM PDT 24
Peak memory 206600 kb
Host smart-d9e6f0e2-7b0a-4827-956a-ea2a4c61b85b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3741420822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3741420822
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.913325479
Short name T2749
Test name
Test status
Simulation time 148174739 ps
CPU time 0.81 seconds
Started Jul 10 06:42:28 PM PDT 24
Finished Jul 10 06:42:33 PM PDT 24
Peak memory 206380 kb
Host smart-8990d2fc-764d-4a86-a684-7f1f4330cc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91332
5479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.913325479
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1164208279
Short name T2333
Test name
Test status
Simulation time 162489352 ps
CPU time 0.9 seconds
Started Jul 10 06:42:31 PM PDT 24
Finished Jul 10 06:42:36 PM PDT 24
Peak memory 206368 kb
Host smart-ba21620c-6b56-496a-aa54-fdf24b984b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642
08279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1164208279
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.1920368294
Short name T2558
Test name
Test status
Simulation time 749508975 ps
CPU time 1.83 seconds
Started Jul 10 06:42:29 PM PDT 24
Finished Jul 10 06:42:36 PM PDT 24
Peak memory 206616 kb
Host smart-96cfe6fa-4b9b-465d-8a88-4b72d6a9ee77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19203
68294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.1920368294
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1768794265
Short name T2392
Test name
Test status
Simulation time 5023567179 ps
CPU time 50.49 seconds
Started Jul 10 06:42:31 PM PDT 24
Finished Jul 10 06:43:25 PM PDT 24
Peak memory 206724 kb
Host smart-fe8fe5ba-7919-4823-977d-f48f9dbcc284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17687
94265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1768794265
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2004100944
Short name T896
Test name
Test status
Simulation time 29438967 ps
CPU time 0.7 seconds
Started Jul 10 06:42:48 PM PDT 24
Finished Jul 10 06:42:54 PM PDT 24
Peak memory 206400 kb
Host smart-40d837e1-a089-487f-bc96-e80e62c16343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2004100944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2004100944
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1118640059
Short name T2160
Test name
Test status
Simulation time 4182873565 ps
CPU time 4.63 seconds
Started Jul 10 06:42:33 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206412 kb
Host smart-751be88f-67e3-40f9-94eb-f23364994f2d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1118640059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1118640059
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1052491675
Short name T993
Test name
Test status
Simulation time 13408662812 ps
CPU time 12.66 seconds
Started Jul 10 06:42:28 PM PDT 24
Finished Jul 10 06:42:46 PM PDT 24
Peak memory 206380 kb
Host smart-b8f66ca5-c122-4fb4-b4bb-c28b2f3f5473
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1052491675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1052491675
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.603441025
Short name T2705
Test name
Test status
Simulation time 23332106384 ps
CPU time 24.43 seconds
Started Jul 10 06:42:45 PM PDT 24
Finished Jul 10 06:43:13 PM PDT 24
Peak memory 206372 kb
Host smart-83cebe30-d618-4627-b0ed-0e65d823bc86
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=603441025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.603441025
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.798572341
Short name T2004
Test name
Test status
Simulation time 207731093 ps
CPU time 0.82 seconds
Started Jul 10 06:42:44 PM PDT 24
Finished Jul 10 06:42:48 PM PDT 24
Peak memory 206292 kb
Host smart-a512950a-f808-4267-ba58-2ff9196fc310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79857
2341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.798572341
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3220883628
Short name T1154
Test name
Test status
Simulation time 146815797 ps
CPU time 0.76 seconds
Started Jul 10 06:42:44 PM PDT 24
Finished Jul 10 06:42:49 PM PDT 24
Peak memory 206272 kb
Host smart-de90a0dc-25d7-4080-b8ad-871cdd08af21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32208
83628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3220883628
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3834504156
Short name T2376
Test name
Test status
Simulation time 330476298 ps
CPU time 1.25 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206396 kb
Host smart-5e4b0e9e-5ed7-49f6-8938-0457c2379902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38345
04156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3834504156
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1761124125
Short name T1927
Test name
Test status
Simulation time 547830399 ps
CPU time 1.48 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206380 kb
Host smart-d8f60aae-b26b-4e7a-a93d-84f1c5828e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17611
24125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1761124125
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.847805105
Short name T907
Test name
Test status
Simulation time 12396661028 ps
CPU time 24.9 seconds
Started Jul 10 06:42:39 PM PDT 24
Finished Jul 10 06:43:08 PM PDT 24
Peak memory 206696 kb
Host smart-9a04d0fd-6ec0-45d0-a3e3-15c94e2db518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84780
5105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.847805105
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.755077196
Short name T404
Test name
Test status
Simulation time 435921448 ps
CPU time 1.32 seconds
Started Jul 10 06:42:35 PM PDT 24
Finished Jul 10 06:42:39 PM PDT 24
Peak memory 206384 kb
Host smart-98fc8f8f-f2dc-4630-b22d-72afa3ac4807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75507
7196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.755077196
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.361913773
Short name T2630
Test name
Test status
Simulation time 143156454 ps
CPU time 0.83 seconds
Started Jul 10 06:42:39 PM PDT 24
Finished Jul 10 06:42:44 PM PDT 24
Peak memory 206376 kb
Host smart-04c91f7c-a73b-402c-aadc-d844068efaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36191
3773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.361913773
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2008064977
Short name T1614
Test name
Test status
Simulation time 38706419 ps
CPU time 0.66 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:43 PM PDT 24
Peak memory 206376 kb
Host smart-012faca9-1b7f-48fb-91da-16edbe9ee4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20080
64977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2008064977
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2356834793
Short name T2256
Test name
Test status
Simulation time 390312408 ps
CPU time 2.3 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:45 PM PDT 24
Peak memory 206624 kb
Host smart-bb2a3020-9eb2-4d2e-82e8-94ec517bd4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23568
34793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2356834793
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.289893522
Short name T1593
Test name
Test status
Simulation time 194554018 ps
CPU time 0.83 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:39 PM PDT 24
Peak memory 206376 kb
Host smart-bafd0c74-7469-4360-b3a8-04478d7311fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28989
3522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.289893522
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2749319222
Short name T1390
Test name
Test status
Simulation time 149183094 ps
CPU time 0.78 seconds
Started Jul 10 06:42:37 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206376 kb
Host smart-d52d41c2-68b1-43a4-89bc-8fd3afdb98e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27493
19222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2749319222
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3453622631
Short name T1316
Test name
Test status
Simulation time 234725884 ps
CPU time 0.86 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:43 PM PDT 24
Peak memory 206376 kb
Host smart-8dcf66aa-9e66-4951-96fb-2b736c02898c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34536
22631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3453622631
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.691897251
Short name T1161
Test name
Test status
Simulation time 11213870208 ps
CPU time 98.35 seconds
Started Jul 10 06:42:37 PM PDT 24
Finished Jul 10 06:44:19 PM PDT 24
Peak memory 206692 kb
Host smart-59450402-42b9-45ef-a857-98dc322ffbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69189
7251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.691897251
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1342452610
Short name T552
Test name
Test status
Simulation time 203936974 ps
CPU time 0.85 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:40 PM PDT 24
Peak memory 206356 kb
Host smart-36826b20-3859-41f7-be96-7b58d41d493b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13424
52610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1342452610
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.2253103354
Short name T1440
Test name
Test status
Simulation time 23296632259 ps
CPU time 23 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:43:03 PM PDT 24
Peak memory 206452 kb
Host smart-d7085977-b5d7-4c07-9c45-cb60778801a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531
03354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.2253103354
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.625981928
Short name T517
Test name
Test status
Simulation time 3270180940 ps
CPU time 4.86 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:47 PM PDT 24
Peak memory 206444 kb
Host smart-00709f26-1a5e-456f-b928-fee3432da850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62598
1928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.625981928
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1556783447
Short name T808
Test name
Test status
Simulation time 8987540488 ps
CPU time 258.42 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 206720 kb
Host smart-98dc8982-4d5b-4adb-b962-401120b73a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15567
83447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1556783447
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1141150502
Short name T1297
Test name
Test status
Simulation time 6743930356 ps
CPU time 62.91 seconds
Started Jul 10 06:42:41 PM PDT 24
Finished Jul 10 06:43:48 PM PDT 24
Peak memory 206620 kb
Host smart-d41a9298-7588-40af-9108-b703784cdf8d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1141150502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1141150502
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.737148548
Short name T798
Test name
Test status
Simulation time 239341015 ps
CPU time 0.92 seconds
Started Jul 10 06:42:40 PM PDT 24
Finished Jul 10 06:42:45 PM PDT 24
Peak memory 206364 kb
Host smart-832e8358-6da2-4dc1-9923-5b3dd112bb97
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=737148548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.737148548
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4290063638
Short name T2085
Test name
Test status
Simulation time 187943486 ps
CPU time 0.84 seconds
Started Jul 10 06:42:37 PM PDT 24
Finished Jul 10 06:42:42 PM PDT 24
Peak memory 206380 kb
Host smart-621e52e2-8913-4186-8b1a-91d3a75a69ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42900
63638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4290063638
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.4043625509
Short name T2539
Test name
Test status
Simulation time 4408893432 ps
CPU time 39.47 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:43:18 PM PDT 24
Peak memory 206596 kb
Host smart-cb100cc6-d434-4e82-a339-c9f772954498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
25509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.4043625509
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3493936588
Short name T1221
Test name
Test status
Simulation time 4221970388 ps
CPU time 30.3 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206664 kb
Host smart-2be100fe-a48a-497d-86db-bb40286458a6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3493936588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3493936588
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.4005386473
Short name T1921
Test name
Test status
Simulation time 182375613 ps
CPU time 0.86 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:43 PM PDT 24
Peak memory 206364 kb
Host smart-815dc2a5-2408-4896-b7c8-505ac51c33e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4005386473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.4005386473
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1958687494
Short name T1392
Test name
Test status
Simulation time 160865721 ps
CPU time 0.86 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:44 PM PDT 24
Peak memory 206404 kb
Host smart-470d3ec7-0661-413c-9970-f3bdd173111e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19586
87494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1958687494
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2950744600
Short name T120
Test name
Test status
Simulation time 228069733 ps
CPU time 0.87 seconds
Started Jul 10 06:42:37 PM PDT 24
Finished Jul 10 06:42:42 PM PDT 24
Peak memory 206376 kb
Host smart-50bf2489-5083-4b5d-b9f0-3c6383ad085a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29507
44600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2950744600
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2258805290
Short name T1669
Test name
Test status
Simulation time 169606226 ps
CPU time 0.85 seconds
Started Jul 10 06:42:39 PM PDT 24
Finished Jul 10 06:42:44 PM PDT 24
Peak memory 206372 kb
Host smart-7ea6e111-1489-489b-8526-217704fd09b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22588
05290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2258805290
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.4235253820
Short name T1841
Test name
Test status
Simulation time 183892416 ps
CPU time 0.9 seconds
Started Jul 10 06:42:37 PM PDT 24
Finished Jul 10 06:42:42 PM PDT 24
Peak memory 206356 kb
Host smart-a3ea11fa-3d45-4ae1-8364-a13d8e091508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
53820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4235253820
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2826322156
Short name T2334
Test name
Test status
Simulation time 186261123 ps
CPU time 0.82 seconds
Started Jul 10 06:42:41 PM PDT 24
Finished Jul 10 06:42:46 PM PDT 24
Peak memory 206304 kb
Host smart-a34b7bc1-a02f-4533-a0e1-5df3b5d32fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28263
22156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2826322156
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.859459613
Short name T1097
Test name
Test status
Simulation time 165708549 ps
CPU time 0.76 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:40 PM PDT 24
Peak memory 206368 kb
Host smart-33bea15e-97e3-40a0-9515-bec589c99357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85945
9613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.859459613
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.195228880
Short name T2270
Test name
Test status
Simulation time 226356284 ps
CPU time 0.98 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:43 PM PDT 24
Peak memory 206396 kb
Host smart-f51b6b8e-5eea-41bc-8dea-f697755c4af7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=195228880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.195228880
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1217238065
Short name T2685
Test name
Test status
Simulation time 178750217 ps
CPU time 0.8 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:43 PM PDT 24
Peak memory 206396 kb
Host smart-6bcd02e0-ad86-4015-977b-ef4c0fee0844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12172
38065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1217238065
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1438767425
Short name T1353
Test name
Test status
Simulation time 7611252161 ps
CPU time 16.27 seconds
Started Jul 10 06:42:37 PM PDT 24
Finished Jul 10 06:42:57 PM PDT 24
Peak memory 206744 kb
Host smart-c070722b-2970-4cf4-a4bd-cc898e7e3589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
67425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1438767425
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1183521877
Short name T700
Test name
Test status
Simulation time 176357530 ps
CPU time 0.82 seconds
Started Jul 10 06:42:35 PM PDT 24
Finished Jul 10 06:42:39 PM PDT 24
Peak memory 206360 kb
Host smart-e8a76e48-14da-4ffa-b02a-4751a72041c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11835
21877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1183521877
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.912837606
Short name T1990
Test name
Test status
Simulation time 205567781 ps
CPU time 0.91 seconds
Started Jul 10 06:42:39 PM PDT 24
Finished Jul 10 06:42:44 PM PDT 24
Peak memory 206356 kb
Host smart-d5bc5f04-1829-4e00-8ec4-2091c19da2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91283
7606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.912837606
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.1750612662
Short name T1790
Test name
Test status
Simulation time 190415184 ps
CPU time 0.85 seconds
Started Jul 10 06:42:36 PM PDT 24
Finished Jul 10 06:42:41 PM PDT 24
Peak memory 206380 kb
Host smart-b4746ec6-42e9-4e3e-9e93-ffd792515d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
12662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.1750612662
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.744214703
Short name T89
Test name
Test status
Simulation time 194945635 ps
CPU time 0.88 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:43 PM PDT 24
Peak memory 206396 kb
Host smart-f598c1e2-d352-4093-bc98-93a53d5c0b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74421
4703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.744214703
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2268861826
Short name T2266
Test name
Test status
Simulation time 136780195 ps
CPU time 0.79 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:44 PM PDT 24
Peak memory 206372 kb
Host smart-047389a1-efdc-485e-a563-85a213ed7566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22688
61826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2268861826
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3003264640
Short name T1579
Test name
Test status
Simulation time 165258724 ps
CPU time 0.78 seconds
Started Jul 10 06:42:38 PM PDT 24
Finished Jul 10 06:42:42 PM PDT 24
Peak memory 206360 kb
Host smart-5e97bb5f-8535-4b13-8b26-60a1b0b03862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30032
64640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3003264640
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3436506029
Short name T2751
Test name
Test status
Simulation time 158775724 ps
CPU time 0.78 seconds
Started Jul 10 06:42:39 PM PDT 24
Finished Jul 10 06:42:45 PM PDT 24
Peak memory 206388 kb
Host smart-752b845d-5aab-4aca-bb81-b5b1133f671e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34365
06029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3436506029
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2689194722
Short name T1334
Test name
Test status
Simulation time 281877544 ps
CPU time 1.04 seconds
Started Jul 10 06:42:42 PM PDT 24
Finished Jul 10 06:42:47 PM PDT 24
Peak memory 206376 kb
Host smart-f9518f16-8db1-4b85-b3bb-9d9dd1b9b2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26891
94722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2689194722
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.868369240
Short name T2066
Test name
Test status
Simulation time 3446463431 ps
CPU time 33.36 seconds
Started Jul 10 06:42:48 PM PDT 24
Finished Jul 10 06:43:27 PM PDT 24
Peak memory 206644 kb
Host smart-f03e65d6-ea01-4c19-98a7-dd0a28aa422c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=868369240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.868369240
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.611543819
Short name T1716
Test name
Test status
Simulation time 151550982 ps
CPU time 0.76 seconds
Started Jul 10 06:42:40 PM PDT 24
Finished Jul 10 06:42:45 PM PDT 24
Peak memory 206380 kb
Host smart-5d98651c-0d7e-4670-9cf9-8c2cdd31ab67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61154
3819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.611543819
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1857217481
Short name T2686
Test name
Test status
Simulation time 173662658 ps
CPU time 0.83 seconds
Started Jul 10 06:42:39 PM PDT 24
Finished Jul 10 06:42:44 PM PDT 24
Peak memory 206340 kb
Host smart-8ffdafbf-87be-4d41-82cc-f48f111039a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18572
17481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1857217481
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.270514879
Short name T2206
Test name
Test status
Simulation time 1013935825 ps
CPU time 2.37 seconds
Started Jul 10 06:42:40 PM PDT 24
Finished Jul 10 06:42:46 PM PDT 24
Peak memory 206616 kb
Host smart-ddd7e845-0442-4517-9693-f49fe3df42d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27051
4879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.270514879
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2827774388
Short name T1280
Test name
Test status
Simulation time 5477426214 ps
CPU time 147.9 seconds
Started Jul 10 06:42:35 PM PDT 24
Finished Jul 10 06:45:06 PM PDT 24
Peak memory 206680 kb
Host smart-f5f9d73b-e4cf-4f43-9eaa-7b1ad7763cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
74388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2827774388
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.2687083708
Short name T1252
Test name
Test status
Simulation time 40950349 ps
CPU time 0.66 seconds
Started Jul 10 06:39:25 PM PDT 24
Finished Jul 10 06:39:31 PM PDT 24
Peak memory 206440 kb
Host smart-4b56f511-a3e7-4cff-bee2-3f19014224d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2687083708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2687083708
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.820023182
Short name T1057
Test name
Test status
Simulation time 4360470135 ps
CPU time 5.21 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:39:13 PM PDT 24
Peak memory 206404 kb
Host smart-395047d7-fd6a-4960-a9d6-e5584868c773
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=820023182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.820023182
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2628417267
Short name T9
Test name
Test status
Simulation time 13356527689 ps
CPU time 12.39 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:21 PM PDT 24
Peak memory 206464 kb
Host smart-437ad856-cfc9-496f-9a71-24a4d3040cd0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2628417267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2628417267
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2347219491
Short name T1303
Test name
Test status
Simulation time 23391478557 ps
CPU time 27.1 seconds
Started Jul 10 06:39:01 PM PDT 24
Finished Jul 10 06:39:33 PM PDT 24
Peak memory 206736 kb
Host smart-634dee5b-d54d-468b-8db5-b1df0e8d9e92
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2347219491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2347219491
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.4168151434
Short name T1868
Test name
Test status
Simulation time 157579401 ps
CPU time 0.85 seconds
Started Jul 10 06:39:02 PM PDT 24
Finished Jul 10 06:39:07 PM PDT 24
Peak memory 206372 kb
Host smart-298c49e5-9361-4e8d-977c-ba88a39e8e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41681
51434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.4168151434
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1091730322
Short name T59
Test name
Test status
Simulation time 193407782 ps
CPU time 0.83 seconds
Started Jul 10 06:39:09 PM PDT 24
Finished Jul 10 06:39:15 PM PDT 24
Peak memory 206400 kb
Host smart-c2a1a1be-c29c-4bf8-9bef-1ffdd7b19d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10917
30322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1091730322
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2057175651
Short name T68
Test name
Test status
Simulation time 149423752 ps
CPU time 0.85 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:09 PM PDT 24
Peak memory 206348 kb
Host smart-e6a2afa6-12e9-4c6a-8a37-25b4e6c3ef6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20571
75651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2057175651
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1088495584
Short name T652
Test name
Test status
Simulation time 152366429 ps
CPU time 0.78 seconds
Started Jul 10 06:39:09 PM PDT 24
Finished Jul 10 06:39:15 PM PDT 24
Peak memory 206396 kb
Host smart-3f6f7fbf-2ddc-4b80-99ec-14d64f9f164c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
95584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1088495584
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.2501335432
Short name T1157
Test name
Test status
Simulation time 402060367 ps
CPU time 1.25 seconds
Started Jul 10 06:39:02 PM PDT 24
Finished Jul 10 06:39:08 PM PDT 24
Peak memory 206392 kb
Host smart-ddb0450c-c53e-413d-b377-e96cb5024381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25013
35432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.2501335432
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2316573875
Short name T1967
Test name
Test status
Simulation time 764839099 ps
CPU time 1.96 seconds
Started Jul 10 06:39:02 PM PDT 24
Finished Jul 10 06:39:08 PM PDT 24
Peak memory 206624 kb
Host smart-3e0c9290-b287-4eb0-86e6-84fdfb258f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23165
73875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2316573875
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.398634439
Short name T1610
Test name
Test status
Simulation time 6337680073 ps
CPU time 12.31 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:39:20 PM PDT 24
Peak memory 206704 kb
Host smart-b8b6dff5-5900-49d2-a44e-5dc507941f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39863
4439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.398634439
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1047626399
Short name T2754
Test name
Test status
Simulation time 460507720 ps
CPU time 1.38 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:10 PM PDT 24
Peak memory 206368 kb
Host smart-0da4b468-0bcc-417a-93f5-4400c66a64d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10476
26399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1047626399
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1319668298
Short name T2648
Test name
Test status
Simulation time 148868985 ps
CPU time 0.77 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:39:08 PM PDT 24
Peak memory 206360 kb
Host smart-a9e8c051-3102-4318-8347-0520deedf1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13196
68298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1319668298
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2384762229
Short name T1886
Test name
Test status
Simulation time 35591809 ps
CPU time 0.67 seconds
Started Jul 10 06:39:02 PM PDT 24
Finished Jul 10 06:39:07 PM PDT 24
Peak memory 206372 kb
Host smart-e421439f-7db3-41b1-9232-4f16f1998f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23847
62229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2384762229
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1239107118
Short name T1206
Test name
Test status
Simulation time 823848611 ps
CPU time 1.94 seconds
Started Jul 10 06:39:01 PM PDT 24
Finished Jul 10 06:39:07 PM PDT 24
Peak memory 206568 kb
Host smart-029b333f-422e-4b8d-8451-c517b74b2a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12391
07118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1239107118
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.4122978124
Short name T1207
Test name
Test status
Simulation time 336377925 ps
CPU time 1.78 seconds
Started Jul 10 06:39:04 PM PDT 24
Finished Jul 10 06:39:10 PM PDT 24
Peak memory 206648 kb
Host smart-a8a19fe6-6c5a-4968-b5e7-e57c586ff56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41229
78124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.4122978124
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1372116812
Short name T2010
Test name
Test status
Simulation time 118190648585 ps
CPU time 158.87 seconds
Started Jul 10 06:39:02 PM PDT 24
Finished Jul 10 06:41:46 PM PDT 24
Peak memory 206628 kb
Host smart-abfb337d-5837-4ad3-8c9c-b65868296735
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1372116812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1372116812
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1105265913
Short name T1856
Test name
Test status
Simulation time 102081717288 ps
CPU time 138.63 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:41:27 PM PDT 24
Peak memory 206700 kb
Host smart-c55f6f23-3cfc-4bfd-80de-0c3a00c016ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105265913 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1105265913
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1166946765
Short name T866
Test name
Test status
Simulation time 102153962766 ps
CPU time 137.57 seconds
Started Jul 10 06:39:03 PM PDT 24
Finished Jul 10 06:41:25 PM PDT 24
Peak memory 206616 kb
Host smart-aad068ca-68af-4b82-a938-d34563b878df
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1166946765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1166946765
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1237418046
Short name T1167
Test name
Test status
Simulation time 90029285137 ps
CPU time 142.78 seconds
Started Jul 10 06:39:08 PM PDT 24
Finished Jul 10 06:41:36 PM PDT 24
Peak memory 206628 kb
Host smart-475fb506-ab07-4039-b922-f36245deb97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237418046 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1237418046
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.1401313554
Short name T1992
Test name
Test status
Simulation time 118180162583 ps
CPU time 163.46 seconds
Started Jul 10 06:39:13 PM PDT 24
Finished Jul 10 06:42:02 PM PDT 24
Peak memory 206656 kb
Host smart-2f38ad96-f94a-4898-b709-d42a5d349604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14013
13554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.1401313554
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1780260040
Short name T1943
Test name
Test status
Simulation time 210390636 ps
CPU time 0.89 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:16 PM PDT 24
Peak memory 206360 kb
Host smart-8644619d-dd94-4f21-9e9b-d9b401db1a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17802
60040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1780260040
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.82740762
Short name T1504
Test name
Test status
Simulation time 136376051 ps
CPU time 0.77 seconds
Started Jul 10 06:39:12 PM PDT 24
Finished Jul 10 06:39:18 PM PDT 24
Peak memory 206376 kb
Host smart-6adceba3-757d-450e-bf6a-6e0b2f3598d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82740
762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.82740762
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2275031691
Short name T607
Test name
Test status
Simulation time 227349476 ps
CPU time 0.88 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206388 kb
Host smart-7e82303b-232f-47d8-9b20-a8d75e6274bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22750
31691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2275031691
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.3926279306
Short name T227
Test name
Test status
Simulation time 9364230746 ps
CPU time 92.38 seconds
Started Jul 10 06:39:11 PM PDT 24
Finished Jul 10 06:40:49 PM PDT 24
Peak memory 206728 kb
Host smart-888eb34e-5fbd-421b-8dad-dc82990e5f5c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3926279306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.3926279306
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3113212814
Short name T2537
Test name
Test status
Simulation time 4682901327 ps
CPU time 17.06 seconds
Started Jul 10 06:39:09 PM PDT 24
Finished Jul 10 06:39:31 PM PDT 24
Peak memory 206540 kb
Host smart-e861c9e4-7062-49e3-b7ac-821444187828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132
12814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3113212814
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3311083651
Short name T1749
Test name
Test status
Simulation time 235207795 ps
CPU time 0.92 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206356 kb
Host smart-022be390-f213-4265-af52-08c9f111f85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33110
83651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3311083651
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3864094327
Short name T1210
Test name
Test status
Simulation time 23280906225 ps
CPU time 23.56 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:39 PM PDT 24
Peak memory 206416 kb
Host smart-00686816-bce4-433f-a338-6641e401da60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38640
94327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3864094327
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3693532768
Short name T1753
Test name
Test status
Simulation time 3329409166 ps
CPU time 3.74 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:18 PM PDT 24
Peak memory 206428 kb
Host smart-c8a213af-da62-4f83-8d67-db5d45aaed3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36935
32768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3693532768
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1707719314
Short name T1516
Test name
Test status
Simulation time 6906513422 ps
CPU time 47.96 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:40:04 PM PDT 24
Peak memory 206708 kb
Host smart-f517edee-d481-400d-99a7-66589523d627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17077
19314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1707719314
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1848980462
Short name T1626
Test name
Test status
Simulation time 3762304030 ps
CPU time 100.69 seconds
Started Jul 10 06:39:11 PM PDT 24
Finished Jul 10 06:40:57 PM PDT 24
Peak memory 206656 kb
Host smart-f3790f71-59db-4d25-8601-d9f1be1407d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1848980462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1848980462
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.949375425
Short name T871
Test name
Test status
Simulation time 247432657 ps
CPU time 0.88 seconds
Started Jul 10 06:39:13 PM PDT 24
Finished Jul 10 06:39:19 PM PDT 24
Peak memory 206388 kb
Host smart-21d1591d-e042-484c-9d1c-c4ab76b307b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=949375425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.949375425
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3842894185
Short name T1056
Test name
Test status
Simulation time 186828459 ps
CPU time 0.86 seconds
Started Jul 10 06:39:11 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206396 kb
Host smart-efae1769-3f9f-40b0-911d-6bae55c2e99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38428
94185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3842894185
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2657899096
Short name T599
Test name
Test status
Simulation time 3854863942 ps
CPU time 28.27 seconds
Started Jul 10 06:39:16 PM PDT 24
Finished Jul 10 06:39:50 PM PDT 24
Peak memory 206736 kb
Host smart-9b6b0aa5-c978-4d8c-9024-04715c15f457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26578
99096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2657899096
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.2112695563
Short name T1796
Test name
Test status
Simulation time 4846543212 ps
CPU time 34.58 seconds
Started Jul 10 06:39:12 PM PDT 24
Finished Jul 10 06:39:52 PM PDT 24
Peak memory 206716 kb
Host smart-539725bb-593e-4b55-99fe-162b29c04735
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2112695563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.2112695563
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3888290574
Short name T2033
Test name
Test status
Simulation time 154262669 ps
CPU time 0.78 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206332 kb
Host smart-85c6dae8-b678-4f6c-a3b2-d0775138d1bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3888290574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3888290574
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.406374166
Short name T478
Test name
Test status
Simulation time 144452418 ps
CPU time 0.76 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:16 PM PDT 24
Peak memory 206376 kb
Host smart-308610b3-052f-4d92-804a-e3a1444e598f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40637
4166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.406374166
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1556107525
Short name T965
Test name
Test status
Simulation time 174091079 ps
CPU time 0.8 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:16 PM PDT 24
Peak memory 206380 kb
Host smart-d8684d7f-52c1-42d2-8f6b-4583333b42a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15561
07525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1556107525
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3023398345
Short name T1103
Test name
Test status
Simulation time 195294256 ps
CPU time 0.8 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:16 PM PDT 24
Peak memory 206392 kb
Host smart-50a7d413-1426-4b80-b851-c551c166ef8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30233
98345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3023398345
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1868479805
Short name T972
Test name
Test status
Simulation time 201412223 ps
CPU time 0.84 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206372 kb
Host smart-9f7b3212-c4b9-4675-a98c-aec62664dbc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18684
79805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1868479805
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2529776848
Short name T2503
Test name
Test status
Simulation time 180651796 ps
CPU time 0.85 seconds
Started Jul 10 06:39:11 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206384 kb
Host smart-afa6129b-4847-484d-957e-2ae85722f013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25297
76848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2529776848
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1567438415
Short name T2600
Test name
Test status
Simulation time 204671159 ps
CPU time 0.93 seconds
Started Jul 10 06:39:09 PM PDT 24
Finished Jul 10 06:39:15 PM PDT 24
Peak memory 206396 kb
Host smart-7e003038-a17e-46db-8ed0-c2ff629483a1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1567438415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1567438415
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.469937676
Short name T1402
Test name
Test status
Simulation time 225832820 ps
CPU time 0.96 seconds
Started Jul 10 06:39:12 PM PDT 24
Finished Jul 10 06:39:18 PM PDT 24
Peak memory 206564 kb
Host smart-35f1a545-9f47-4952-aaad-557bead36cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46993
7676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.469937676
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.902683319
Short name T1357
Test name
Test status
Simulation time 148991144 ps
CPU time 0.75 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206396 kb
Host smart-3f4b380a-2066-4715-a66d-7547e6a5a472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90268
3319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.902683319
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2222455401
Short name T2100
Test name
Test status
Simulation time 30415871 ps
CPU time 0.66 seconds
Started Jul 10 06:39:12 PM PDT 24
Finished Jul 10 06:39:18 PM PDT 24
Peak memory 206388 kb
Host smart-b67cf400-f508-4429-9497-447686cd07eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22224
55401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2222455401
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3314588342
Short name T239
Test name
Test status
Simulation time 7997869718 ps
CPU time 17.79 seconds
Started Jul 10 06:39:13 PM PDT 24
Finished Jul 10 06:39:36 PM PDT 24
Peak memory 206708 kb
Host smart-2da2f307-58a5-4b0a-929c-04021fdd1d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145
88342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3314588342
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3604125366
Short name T2192
Test name
Test status
Simulation time 171467580 ps
CPU time 0.83 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:16 PM PDT 24
Peak memory 206396 kb
Host smart-5365f3c3-8c2b-4c40-8de4-638d12a1c8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36041
25366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3604125366
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1217586834
Short name T2055
Test name
Test status
Simulation time 221757042 ps
CPU time 0.87 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:39:16 PM PDT 24
Peak memory 206376 kb
Host smart-dc0d9e3c-3e3e-45b3-9e3a-cfd0bea19edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12175
86834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1217586834
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.529266964
Short name T164
Test name
Test status
Simulation time 11031611082 ps
CPU time 97.77 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:40:53 PM PDT 24
Peak memory 206716 kb
Host smart-6142f62d-d2d1-426f-a9c7-3012fe12d24b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=529266964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.529266964
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3385316993
Short name T173
Test name
Test status
Simulation time 9571807465 ps
CPU time 163.68 seconds
Started Jul 10 06:39:10 PM PDT 24
Finished Jul 10 06:42:00 PM PDT 24
Peak memory 206724 kb
Host smart-0c6b85cc-48c1-4861-805e-3bd73e11d2d2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3385316993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3385316993
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2723222142
Short name T712
Test name
Test status
Simulation time 16548805003 ps
CPU time 342.44 seconds
Started Jul 10 06:39:09 PM PDT 24
Finished Jul 10 06:44:56 PM PDT 24
Peak memory 206628 kb
Host smart-1849f852-88c9-4d27-b4e1-71f704da2c98
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2723222142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2723222142
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3182326299
Short name T1847
Test name
Test status
Simulation time 217535158 ps
CPU time 0.91 seconds
Started Jul 10 06:39:11 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206384 kb
Host smart-e9254efe-e4b1-4086-91cf-9b55afaea5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31823
26299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3182326299
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2830216807
Short name T2698
Test name
Test status
Simulation time 183183945 ps
CPU time 0.87 seconds
Started Jul 10 06:39:11 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206380 kb
Host smart-fbd77b9f-036b-4416-baf9-075b053e8c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28302
16807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2830216807
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1755827357
Short name T2009
Test name
Test status
Simulation time 171465764 ps
CPU time 0.79 seconds
Started Jul 10 06:39:11 PM PDT 24
Finished Jul 10 06:39:17 PM PDT 24
Peak memory 206376 kb
Host smart-d179c694-6e10-4c24-9b40-9799e0a97f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17558
27357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1755827357
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3457044359
Short name T207
Test name
Test status
Simulation time 948834200 ps
CPU time 1.91 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:25 PM PDT 24
Peak memory 225276 kb
Host smart-6617a351-e39e-42da-9607-4f152a265a6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3457044359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3457044359
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1930804930
Short name T58
Test name
Test status
Simulation time 426731575 ps
CPU time 1.28 seconds
Started Jul 10 06:39:09 PM PDT 24
Finished Jul 10 06:39:16 PM PDT 24
Peak memory 206392 kb
Host smart-54477d96-eedf-4f28-84cc-eb6c271f1b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19308
04930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1930804930
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.4113023363
Short name T853
Test name
Test status
Simulation time 242865700 ps
CPU time 0.9 seconds
Started Jul 10 06:39:12 PM PDT 24
Finished Jul 10 06:39:18 PM PDT 24
Peak memory 206380 kb
Host smart-e84f2f75-a604-4eda-873a-ec1d13b6aa2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41130
23363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.4113023363
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3128432396
Short name T1837
Test name
Test status
Simulation time 147039886 ps
CPU time 0.75 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:23 PM PDT 24
Peak memory 206308 kb
Host smart-105450ae-14c8-4ee4-9610-47d2ac328eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
32396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3128432396
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.4025421347
Short name T1475
Test name
Test status
Simulation time 154244465 ps
CPU time 0.77 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:39:26 PM PDT 24
Peak memory 206560 kb
Host smart-145d3b29-a15e-4a3b-91ae-e463ae987fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40254
21347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.4025421347
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2733969047
Short name T527
Test name
Test status
Simulation time 187679101 ps
CPU time 0.84 seconds
Started Jul 10 06:39:17 PM PDT 24
Finished Jul 10 06:39:23 PM PDT 24
Peak memory 206376 kb
Host smart-32303181-6cdc-46f8-9c68-1482abc5cc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27339
69047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2733969047
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.4040164625
Short name T157
Test name
Test status
Simulation time 5061341741 ps
CPU time 139.87 seconds
Started Jul 10 06:39:23 PM PDT 24
Finished Jul 10 06:41:48 PM PDT 24
Peak memory 206684 kb
Host smart-ef696142-5572-40bb-b3ef-0a994a11bbbe
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4040164625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.4040164625
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.71103035
Short name T1640
Test name
Test status
Simulation time 205413056 ps
CPU time 0.8 seconds
Started Jul 10 06:39:17 PM PDT 24
Finished Jul 10 06:39:23 PM PDT 24
Peak memory 206392 kb
Host smart-01efd980-6469-4e5e-9827-de5df227b5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71103
035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.71103035
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1738479634
Short name T1377
Test name
Test status
Simulation time 193331119 ps
CPU time 0.82 seconds
Started Jul 10 06:39:16 PM PDT 24
Finished Jul 10 06:39:22 PM PDT 24
Peak memory 206372 kb
Host smart-1a4e26e0-f5ba-4d21-aed4-a4add13cf772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17384
79634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1738479634
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2347015415
Short name T2269
Test name
Test status
Simulation time 610078646 ps
CPU time 1.49 seconds
Started Jul 10 06:39:17 PM PDT 24
Finished Jul 10 06:39:23 PM PDT 24
Peak memory 206376 kb
Host smart-cc16d5ea-354a-4475-b6b7-59a0b7aaf562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23470
15415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2347015415
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1952798335
Short name T668
Test name
Test status
Simulation time 4378068332 ps
CPU time 116.96 seconds
Started Jul 10 06:39:21 PM PDT 24
Finished Jul 10 06:41:24 PM PDT 24
Peak memory 206636 kb
Host smart-7bae8626-c9db-48a4-97b4-57fe89cde24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19527
98335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1952798335
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2152250401
Short name T558
Test name
Test status
Simulation time 34020753 ps
CPU time 0.71 seconds
Started Jul 10 06:42:53 PM PDT 24
Finished Jul 10 06:42:58 PM PDT 24
Peak memory 206416 kb
Host smart-45db52a5-0ca2-43a0-960f-7fee5d57d56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2152250401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2152250401
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2318742113
Short name T2105
Test name
Test status
Simulation time 4093574321 ps
CPU time 4.94 seconds
Started Jul 10 06:42:44 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206656 kb
Host smart-8d927e1a-4189-485a-ae47-7700caddb38f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2318742113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.2318742113
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3198800935
Short name T1160
Test name
Test status
Simulation time 13384161939 ps
CPU time 16.59 seconds
Started Jul 10 06:42:48 PM PDT 24
Finished Jul 10 06:43:10 PM PDT 24
Peak memory 206348 kb
Host smart-7c3e2d70-8bbc-414a-b471-c285accacc1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3198800935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3198800935
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3804412003
Short name T899
Test name
Test status
Simulation time 23373838120 ps
CPU time 23.82 seconds
Started Jul 10 06:42:47 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206700 kb
Host smart-d21abb56-bf5a-4bc7-b338-d6a94f515ca8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3804412003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3804412003
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3786200029
Short name T1895
Test name
Test status
Simulation time 159211697 ps
CPU time 0.83 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206276 kb
Host smart-c83ffbb3-36e0-4457-b905-6e8084f2f5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37862
00029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3786200029
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2538000406
Short name T859
Test name
Test status
Simulation time 146796400 ps
CPU time 0.77 seconds
Started Jul 10 06:42:47 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206388 kb
Host smart-5c3e4fad-f901-45e0-9fe9-80e59f232278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
00406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2538000406
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1984055911
Short name T2244
Test name
Test status
Simulation time 247563494 ps
CPU time 1 seconds
Started Jul 10 06:42:44 PM PDT 24
Finished Jul 10 06:42:49 PM PDT 24
Peak memory 206396 kb
Host smart-81a53c04-825a-46d8-931f-43a5beb0c37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19840
55911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1984055911
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3040445373
Short name T2674
Test name
Test status
Simulation time 907517802 ps
CPU time 2.37 seconds
Started Jul 10 06:42:48 PM PDT 24
Finished Jul 10 06:42:56 PM PDT 24
Peak memory 206568 kb
Host smart-944319fb-317c-4984-aadf-da10acb4dfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30404
45373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3040445373
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2820787907
Short name T1344
Test name
Test status
Simulation time 10305206857 ps
CPU time 18.53 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:43:11 PM PDT 24
Peak memory 206636 kb
Host smart-ae834dc8-0426-49cb-9a98-b9fd49a3deec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
87907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2820787907
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1463847523
Short name T360
Test name
Test status
Simulation time 542515769 ps
CPU time 1.41 seconds
Started Jul 10 06:42:45 PM PDT 24
Finished Jul 10 06:42:52 PM PDT 24
Peak memory 206368 kb
Host smart-71e8b4fb-da64-4c8f-995c-be08e58ddb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14638
47523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1463847523
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1124482804
Short name T213
Test name
Test status
Simulation time 147618436 ps
CPU time 0.78 seconds
Started Jul 10 06:42:49 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206380 kb
Host smart-a00b7c09-8694-4c82-b274-e577fd116f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11244
82804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1124482804
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3386360291
Short name T578
Test name
Test status
Simulation time 58982458 ps
CPU time 0.72 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206388 kb
Host smart-a8b65a89-a276-45d7-9dc5-fdeff4e82f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33863
60291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3386360291
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3693579562
Short name T1802
Test name
Test status
Simulation time 971378562 ps
CPU time 2.06 seconds
Started Jul 10 06:42:47 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206660 kb
Host smart-a9903a51-dd25-43a1-a020-c8a0e8c3a0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36935
79562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3693579562
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2219671401
Short name T2467
Test name
Test status
Simulation time 211662699 ps
CPU time 1.44 seconds
Started Jul 10 06:42:51 PM PDT 24
Finished Jul 10 06:42:57 PM PDT 24
Peak memory 206468 kb
Host smart-fee48eba-574a-461d-99d4-b64feb541117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22196
71401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2219671401
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2178593991
Short name T2356
Test name
Test status
Simulation time 231012677 ps
CPU time 1.01 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:42:52 PM PDT 24
Peak memory 206404 kb
Host smart-eeb2ca17-beb3-4a4f-a667-0d7965ca479d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21785
93991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2178593991
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1210743834
Short name T945
Test name
Test status
Simulation time 159619189 ps
CPU time 0.77 seconds
Started Jul 10 06:42:49 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206372 kb
Host smart-d6a8c9cc-2a91-4fa4-aaa4-ed9f634d94b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
43834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1210743834
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2300956778
Short name T424
Test name
Test status
Simulation time 205336402 ps
CPU time 0.91 seconds
Started Jul 10 06:42:51 PM PDT 24
Finished Jul 10 06:42:56 PM PDT 24
Peak memory 206232 kb
Host smart-0adc2932-3ab6-4c92-8fb2-858d26bcfdde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23009
56778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2300956778
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.298123671
Short name T92
Test name
Test status
Simulation time 7335398163 ps
CPU time 22.56 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:43:13 PM PDT 24
Peak memory 206668 kb
Host smart-c763e7b7-d0e6-4615-a95e-28292c529390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29812
3671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.298123671
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.4155610791
Short name T1165
Test name
Test status
Simulation time 217374792 ps
CPU time 0.8 seconds
Started Jul 10 06:42:43 PM PDT 24
Finished Jul 10 06:42:47 PM PDT 24
Peak memory 206368 kb
Host smart-84d3c425-56a4-49ab-90eb-77740e6f5dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41556
10791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.4155610791
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.471119020
Short name T380
Test name
Test status
Simulation time 23294337447 ps
CPU time 22.55 seconds
Started Jul 10 06:42:47 PM PDT 24
Finished Jul 10 06:43:16 PM PDT 24
Peak memory 206440 kb
Host smart-990886c9-855b-4e6d-8b75-03b31eb9e638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47111
9020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.471119020
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3907038000
Short name T2294
Test name
Test status
Simulation time 3309939754 ps
CPU time 3.81 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:42:56 PM PDT 24
Peak memory 206392 kb
Host smart-3a8220cf-92b0-4d08-8423-987bbbab7897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39070
38000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3907038000
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.797228124
Short name T920
Test name
Test status
Simulation time 12990162349 ps
CPU time 96.68 seconds
Started Jul 10 06:42:50 PM PDT 24
Finished Jul 10 06:44:32 PM PDT 24
Peak memory 206688 kb
Host smart-d3582709-98c9-409e-8497-f4f8002e73ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79722
8124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.797228124
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.606885722
Short name T389
Test name
Test status
Simulation time 5803616363 ps
CPU time 42.47 seconds
Started Jul 10 06:42:48 PM PDT 24
Finished Jul 10 06:43:36 PM PDT 24
Peak memory 206624 kb
Host smart-553351ba-1594-4e75-8fd6-28328e7f794f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=606885722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.606885722
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2669090523
Short name T1008
Test name
Test status
Simulation time 246997489 ps
CPU time 0.9 seconds
Started Jul 10 06:42:43 PM PDT 24
Finished Jul 10 06:42:48 PM PDT 24
Peak memory 206308 kb
Host smart-c5460357-e5f1-40d9-9e65-23ef8ba65b79
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2669090523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2669090523
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2436150776
Short name T763
Test name
Test status
Simulation time 212947134 ps
CPU time 0.96 seconds
Started Jul 10 06:42:45 PM PDT 24
Finished Jul 10 06:42:50 PM PDT 24
Peak memory 206380 kb
Host smart-e944ceb9-4520-4992-b5f1-db51a2f84101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24361
50776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2436150776
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3772677496
Short name T2398
Test name
Test status
Simulation time 3928783226 ps
CPU time 29.22 seconds
Started Jul 10 06:42:45 PM PDT 24
Finished Jul 10 06:43:19 PM PDT 24
Peak memory 206700 kb
Host smart-501c5b02-d74f-4cab-bf43-9f6e6bae5c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37726
77496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3772677496
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1316128926
Short name T1910
Test name
Test status
Simulation time 5648752440 ps
CPU time 157.25 seconds
Started Jul 10 06:42:48 PM PDT 24
Finished Jul 10 06:45:31 PM PDT 24
Peak memory 206616 kb
Host smart-53236450-b9da-41c6-b7d3-129606032ce0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1316128926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1316128926
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1347336237
Short name T566
Test name
Test status
Simulation time 186541960 ps
CPU time 0.82 seconds
Started Jul 10 06:42:50 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206360 kb
Host smart-9bcd2781-baf7-4409-ab27-bdfba9c63bc0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1347336237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1347336237
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.4102333200
Short name T2243
Test name
Test status
Simulation time 134162044 ps
CPU time 0.77 seconds
Started Jul 10 06:42:45 PM PDT 24
Finished Jul 10 06:42:50 PM PDT 24
Peak memory 206376 kb
Host smart-9239e6ab-c4a2-435b-b2f1-806c18848002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41023
33200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4102333200
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1072947357
Short name T2187
Test name
Test status
Simulation time 202999958 ps
CPU time 0.92 seconds
Started Jul 10 06:42:47 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206388 kb
Host smart-2bae29bd-f31b-498b-a764-2a6e59383c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10729
47357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1072947357
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.134310311
Short name T2604
Test name
Test status
Simulation time 187135325 ps
CPU time 0.87 seconds
Started Jul 10 06:42:45 PM PDT 24
Finished Jul 10 06:42:51 PM PDT 24
Peak memory 206376 kb
Host smart-bbcada27-7cfb-4941-9340-529a09e36a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13431
0311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.134310311
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.199967740
Short name T1278
Test name
Test status
Simulation time 161443138 ps
CPU time 0.81 seconds
Started Jul 10 06:42:49 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206376 kb
Host smart-d330317b-312f-492b-8ec8-538e832a669e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19996
7740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.199967740
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.4011415712
Short name T2574
Test name
Test status
Simulation time 158483276 ps
CPU time 0.81 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206392 kb
Host smart-541cf8f3-13a4-4083-adce-dff55b22fcb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40114
15712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.4011415712
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.247915658
Short name T2271
Test name
Test status
Simulation time 156817596 ps
CPU time 0.79 seconds
Started Jul 10 06:42:45 PM PDT 24
Finished Jul 10 06:42:50 PM PDT 24
Peak memory 206396 kb
Host smart-cc798795-e0f4-4f11-92e5-dd4150432366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24791
5658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.247915658
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1445878950
Short name T1398
Test name
Test status
Simulation time 246226036 ps
CPU time 0.97 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206392 kb
Host smart-51922158-fbff-4a74-8788-d31b356a1a6b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1445878950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1445878950
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.917412066
Short name T1395
Test name
Test status
Simulation time 150207411 ps
CPU time 0.78 seconds
Started Jul 10 06:42:48 PM PDT 24
Finished Jul 10 06:42:54 PM PDT 24
Peak memory 206368 kb
Host smart-025276ae-7d81-41cd-b927-6fd99c6ceac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91741
2066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.917412066
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2444727601
Short name T36
Test name
Test status
Simulation time 54459358 ps
CPU time 0.69 seconds
Started Jul 10 06:42:49 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206380 kb
Host smart-fb500db7-11f8-41fa-a44b-c957555eba1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24447
27601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2444727601
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3528943572
Short name T1575
Test name
Test status
Simulation time 19077351097 ps
CPU time 37.21 seconds
Started Jul 10 06:42:46 PM PDT 24
Finished Jul 10 06:43:29 PM PDT 24
Peak memory 206676 kb
Host smart-3af19c30-05c0-47df-8ffd-2a9a4bcb1512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35289
43572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3528943572
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2281148854
Short name T726
Test name
Test status
Simulation time 187564571 ps
CPU time 0.83 seconds
Started Jul 10 06:42:49 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206392 kb
Host smart-43e30b90-6e5a-4585-8c0f-537491435764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
48854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2281148854
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3857697018
Short name T1367
Test name
Test status
Simulation time 178561331 ps
CPU time 0.87 seconds
Started Jul 10 06:42:47 PM PDT 24
Finished Jul 10 06:42:53 PM PDT 24
Peak memory 206392 kb
Host smart-89d301fc-37b8-4899-a6d8-5ac39db04bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576
97018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3857697018
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.2050799051
Short name T1822
Test name
Test status
Simulation time 195639937 ps
CPU time 0.84 seconds
Started Jul 10 06:42:48 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206392 kb
Host smart-a95eb8fa-f91b-4392-afa2-1fa9c4f9fcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20507
99051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2050799051
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1789937705
Short name T591
Test name
Test status
Simulation time 147645175 ps
CPU time 0.84 seconds
Started Jul 10 06:42:53 PM PDT 24
Finished Jul 10 06:42:58 PM PDT 24
Peak memory 206376 kb
Host smart-609da136-b2e6-4e72-8eb3-2fb31b2cfb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17899
37705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1789937705
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1338423619
Short name T530
Test name
Test status
Simulation time 137195445 ps
CPU time 0.8 seconds
Started Jul 10 06:42:55 PM PDT 24
Finished Jul 10 06:43:00 PM PDT 24
Peak memory 206356 kb
Host smart-98776d55-5271-44e7-bd12-b61f80b5389c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13384
23619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1338423619
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2069675754
Short name T1271
Test name
Test status
Simulation time 185058407 ps
CPU time 0.79 seconds
Started Jul 10 06:42:56 PM PDT 24
Finished Jul 10 06:43:00 PM PDT 24
Peak memory 206388 kb
Host smart-891d15be-dbd8-4ad4-9ec5-029f3cd70c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20696
75754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2069675754
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2953735760
Short name T2719
Test name
Test status
Simulation time 148232136 ps
CPU time 0.84 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:42:59 PM PDT 24
Peak memory 206404 kb
Host smart-fd558a2c-5e90-439b-80dd-2b76d197d566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
35760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2953735760
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2555603826
Short name T1907
Test name
Test status
Simulation time 202325387 ps
CPU time 0.89 seconds
Started Jul 10 06:42:55 PM PDT 24
Finished Jul 10 06:43:00 PM PDT 24
Peak memory 206404 kb
Host smart-2afcc37f-f07e-4ce5-bd7f-8e1239fd7b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25556
03826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2555603826
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.3845151672
Short name T494
Test name
Test status
Simulation time 4767691948 ps
CPU time 43.12 seconds
Started Jul 10 06:42:55 PM PDT 24
Finished Jul 10 06:43:41 PM PDT 24
Peak memory 206612 kb
Host smart-197ed515-9b69-489e-b5a0-c9f041855028
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3845151672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3845151672
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3947501438
Short name T1961
Test name
Test status
Simulation time 177257854 ps
CPU time 0.8 seconds
Started Jul 10 06:42:57 PM PDT 24
Finished Jul 10 06:43:01 PM PDT 24
Peak memory 206400 kb
Host smart-45873c36-3232-4ab0-897b-e4869d6d3b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39475
01438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3947501438
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1153106973
Short name T1044
Test name
Test status
Simulation time 213204055 ps
CPU time 0.89 seconds
Started Jul 10 06:42:58 PM PDT 24
Finished Jul 10 06:43:02 PM PDT 24
Peak memory 206372 kb
Host smart-606c44b4-b17e-4bd6-b022-f20595b2a813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11531
06973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1153106973
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.4281766284
Short name T1046
Test name
Test status
Simulation time 1140932568 ps
CPU time 2.66 seconds
Started Jul 10 06:42:56 PM PDT 24
Finished Jul 10 06:43:02 PM PDT 24
Peak memory 206628 kb
Host smart-53d037b2-3140-46a4-a60f-03a827dacf68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42817
66284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.4281766284
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.410180985
Short name T506
Test name
Test status
Simulation time 4453987479 ps
CPU time 122.49 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:45:00 PM PDT 24
Peak memory 206632 kb
Host smart-86b10d8a-8a3c-4457-ae6f-c8d62afbddb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41018
0985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.410180985
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1275433860
Short name T2692
Test name
Test status
Simulation time 31150109 ps
CPU time 0.65 seconds
Started Jul 10 06:43:02 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206444 kb
Host smart-0b3fb57f-16c8-4929-85ee-814bf0572ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1275433860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1275433860
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.1827193314
Short name T1695
Test name
Test status
Simulation time 3508164293 ps
CPU time 4.34 seconds
Started Jul 10 06:42:56 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206476 kb
Host smart-0d55fe86-b5de-44f2-978c-e062821efc18
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1827193314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.1827193314
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2859597229
Short name T223
Test name
Test status
Simulation time 13440665712 ps
CPU time 14.11 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:43:11 PM PDT 24
Peak memory 206432 kb
Host smart-726fd8d4-13a7-419f-b0da-15abddf77c4c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2859597229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2859597229
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1970474609
Short name T572
Test name
Test status
Simulation time 23386107266 ps
CPU time 24.51 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:43:23 PM PDT 24
Peak memory 206444 kb
Host smart-2a00eaa9-814c-49a5-9040-c4fb1d26b742
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1970474609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.1970474609
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2435413690
Short name T626
Test name
Test status
Simulation time 186468871 ps
CPU time 0.87 seconds
Started Jul 10 06:42:58 PM PDT 24
Finished Jul 10 06:43:02 PM PDT 24
Peak memory 206376 kb
Host smart-ee1df2c0-200e-47dd-bbfb-1f076a39885f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24354
13690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2435413690
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2751614594
Short name T2281
Test name
Test status
Simulation time 191230664 ps
CPU time 0.88 seconds
Started Jul 10 06:42:55 PM PDT 24
Finished Jul 10 06:43:00 PM PDT 24
Peak memory 206400 kb
Host smart-0e178955-b648-4ac7-85e3-b59fa17f7149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27516
14594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2751614594
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1090016068
Short name T63
Test name
Test status
Simulation time 433922015 ps
CPU time 1.55 seconds
Started Jul 10 06:42:57 PM PDT 24
Finished Jul 10 06:43:02 PM PDT 24
Peak memory 206396 kb
Host smart-7181cdb8-2da7-418a-8af9-66ae21cb0167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10900
16068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1090016068
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3641525447
Short name T2444
Test name
Test status
Simulation time 21467159653 ps
CPU time 47.06 seconds
Started Jul 10 06:42:57 PM PDT 24
Finished Jul 10 06:43:47 PM PDT 24
Peak memory 206436 kb
Host smart-c206232d-47ba-40ae-ac11-339395a97602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36415
25447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3641525447
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3262181159
Short name T1786
Test name
Test status
Simulation time 519404392 ps
CPU time 1.49 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:43:00 PM PDT 24
Peak memory 206312 kb
Host smart-8517ec86-f89d-49f4-bbca-35db658cc68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32621
81159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3262181159
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.315170057
Short name T719
Test name
Test status
Simulation time 150676376 ps
CPU time 0.77 seconds
Started Jul 10 06:42:53 PM PDT 24
Finished Jul 10 06:42:57 PM PDT 24
Peak memory 206380 kb
Host smart-38cdef90-d33e-446a-a175-305f9468986a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31517
0057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.315170057
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1864918349
Short name T2509
Test name
Test status
Simulation time 91330419 ps
CPU time 0.71 seconds
Started Jul 10 06:42:53 PM PDT 24
Finished Jul 10 06:42:57 PM PDT 24
Peak memory 206368 kb
Host smart-143bba64-4252-40fd-b362-b3e6d26f53dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
18349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1864918349
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1129419303
Short name T468
Test name
Test status
Simulation time 941124208 ps
CPU time 2.12 seconds
Started Jul 10 06:42:55 PM PDT 24
Finished Jul 10 06:43:01 PM PDT 24
Peak memory 206596 kb
Host smart-d926dfc1-79b6-4942-9c10-52c36609eb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11294
19303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1129419303
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1170368039
Short name T2347
Test name
Test status
Simulation time 218654887 ps
CPU time 1.82 seconds
Started Jul 10 06:42:59 PM PDT 24
Finished Jul 10 06:43:03 PM PDT 24
Peak memory 206552 kb
Host smart-07e0c72b-180e-44de-8cca-aed2bc06dcbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11703
68039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1170368039
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1213159424
Short name T1863
Test name
Test status
Simulation time 268089295 ps
CPU time 0.91 seconds
Started Jul 10 06:42:57 PM PDT 24
Finished Jul 10 06:43:01 PM PDT 24
Peak memory 206348 kb
Host smart-28f2fb80-1e63-4f0f-97c8-51de5b78865f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131
59424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1213159424
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2523233382
Short name T448
Test name
Test status
Simulation time 144112269 ps
CPU time 0.75 seconds
Started Jul 10 06:42:55 PM PDT 24
Finished Jul 10 06:43:00 PM PDT 24
Peak memory 206376 kb
Host smart-e5719f4c-4a64-4594-98a4-d04778a6238d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25232
33382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2523233382
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2611826643
Short name T325
Test name
Test status
Simulation time 259803238 ps
CPU time 0.96 seconds
Started Jul 10 06:42:53 PM PDT 24
Finished Jul 10 06:42:58 PM PDT 24
Peak memory 206556 kb
Host smart-21f108e1-3d81-4495-a68d-81e4fec0cd7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
26643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2611826643
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.482200710
Short name T622
Test name
Test status
Simulation time 4906683283 ps
CPU time 33.26 seconds
Started Jul 10 06:42:59 PM PDT 24
Finished Jul 10 06:43:35 PM PDT 24
Peak memory 206620 kb
Host smart-80de3424-6816-4346-ac66-c317bd4b7ec3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=482200710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.482200710
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.1900165111
Short name T914
Test name
Test status
Simulation time 3698261680 ps
CPU time 35.77 seconds
Started Jul 10 06:42:57 PM PDT 24
Finished Jul 10 06:43:36 PM PDT 24
Peak memory 206652 kb
Host smart-fa6f028b-7418-4229-b44b-7d19e439a0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19001
65111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1900165111
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2848115702
Short name T2626
Test name
Test status
Simulation time 227877245 ps
CPU time 0.94 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:42:58 PM PDT 24
Peak memory 206372 kb
Host smart-d6b617bb-e190-41d6-963e-349f58682f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28481
15702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2848115702
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.265693209
Short name T2059
Test name
Test status
Simulation time 23368628143 ps
CPU time 21.96 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:43:19 PM PDT 24
Peak memory 206448 kb
Host smart-e3235304-f6a8-4e54-8e20-affc129d955a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26569
3209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.265693209
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.207194941
Short name T2292
Test name
Test status
Simulation time 3341280890 ps
CPU time 5.01 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:43:02 PM PDT 24
Peak memory 206628 kb
Host smart-9de07743-b6ee-4ecf-815e-14a38f21f266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20719
4941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.207194941
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1125629901
Short name T1778
Test name
Test status
Simulation time 10408489795 ps
CPU time 75.05 seconds
Started Jul 10 06:42:56 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206428 kb
Host smart-e48d2e62-6868-437b-96f0-b1ceeba5bb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11256
29901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1125629901
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2319716531
Short name T1794
Test name
Test status
Simulation time 3242439812 ps
CPU time 23.77 seconds
Started Jul 10 06:42:57 PM PDT 24
Finished Jul 10 06:43:24 PM PDT 24
Peak memory 206720 kb
Host smart-797221e5-d998-4666-b95c-c5acbbcb4126
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2319716531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2319716531
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3749953826
Short name T2618
Test name
Test status
Simulation time 252539978 ps
CPU time 0.98 seconds
Started Jul 10 06:42:55 PM PDT 24
Finished Jul 10 06:43:00 PM PDT 24
Peak memory 206352 kb
Host smart-29bfcb17-ebc0-4470-bbfa-de887429e6a6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3749953826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3749953826
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.339572991
Short name T2664
Test name
Test status
Simulation time 225439165 ps
CPU time 0.92 seconds
Started Jul 10 06:42:53 PM PDT 24
Finished Jul 10 06:42:58 PM PDT 24
Peak memory 206396 kb
Host smart-31688a9d-2a70-4b66-ac82-834300e05f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33957
2991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.339572991
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.3663620865
Short name T2064
Test name
Test status
Simulation time 5066035069 ps
CPU time 136.79 seconds
Started Jul 10 06:42:57 PM PDT 24
Finished Jul 10 06:45:17 PM PDT 24
Peak memory 206336 kb
Host smart-9439238c-2f78-4e01-87f2-c87fad991eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36636
20865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.3663620865
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.4005003664
Short name T714
Test name
Test status
Simulation time 5260799951 ps
CPU time 35.77 seconds
Started Jul 10 06:42:59 PM PDT 24
Finished Jul 10 06:43:38 PM PDT 24
Peak memory 206664 kb
Host smart-ab34307b-349c-4e30-b4c4-72ba968c0462
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4005003664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.4005003664
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1525670716
Short name T2565
Test name
Test status
Simulation time 166127760 ps
CPU time 0.86 seconds
Started Jul 10 06:42:57 PM PDT 24
Finished Jul 10 06:43:02 PM PDT 24
Peak memory 206380 kb
Host smart-10f033a1-8091-4bf0-a5e7-0c97225c4d49
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1525670716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1525670716
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.746599981
Short name T864
Test name
Test status
Simulation time 156732773 ps
CPU time 0.79 seconds
Started Jul 10 06:42:55 PM PDT 24
Finished Jul 10 06:43:00 PM PDT 24
Peak memory 206356 kb
Host smart-5f6dbe4d-22e7-4dd3-8391-fd99773088cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74659
9981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.746599981
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2673232152
Short name T1646
Test name
Test status
Simulation time 167683221 ps
CPU time 0.86 seconds
Started Jul 10 06:42:54 PM PDT 24
Finished Jul 10 06:42:58 PM PDT 24
Peak memory 206304 kb
Host smart-806a5d5c-2c37-4369-b5e5-a6a5037d2409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26732
32152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2673232152
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1825908554
Short name T976
Test name
Test status
Simulation time 165034334 ps
CPU time 0.84 seconds
Started Jul 10 06:43:02 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206400 kb
Host smart-858b50d5-fe33-4a85-bac2-a56cfca59488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18259
08554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1825908554
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.619077953
Short name T2644
Test name
Test status
Simulation time 201683762 ps
CPU time 0.87 seconds
Started Jul 10 06:43:00 PM PDT 24
Finished Jul 10 06:43:03 PM PDT 24
Peak memory 206280 kb
Host smart-52f82669-fca2-4569-b669-37276658a295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61907
7953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.619077953
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2836447385
Short name T1717
Test name
Test status
Simulation time 153071084 ps
CPU time 0.83 seconds
Started Jul 10 06:43:03 PM PDT 24
Finished Jul 10 06:43:06 PM PDT 24
Peak memory 206408 kb
Host smart-c42ad874-72f9-48ca-afda-aa7bf8005977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28364
47385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2836447385
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.4059770235
Short name T2525
Test name
Test status
Simulation time 232874230 ps
CPU time 0.98 seconds
Started Jul 10 06:43:01 PM PDT 24
Finished Jul 10 06:43:04 PM PDT 24
Peak memory 206380 kb
Host smart-f14184d1-5c40-4b45-b419-a786ba65ccf9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4059770235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.4059770235
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1027040146
Short name T2125
Test name
Test status
Simulation time 173387909 ps
CPU time 0.81 seconds
Started Jul 10 06:43:01 PM PDT 24
Finished Jul 10 06:43:04 PM PDT 24
Peak memory 206380 kb
Host smart-6eaafd99-73d8-4b3b-904f-fcaca126a0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
40146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1027040146
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2648082895
Short name T2733
Test name
Test status
Simulation time 30971824 ps
CPU time 0.67 seconds
Started Jul 10 06:43:00 PM PDT 24
Finished Jul 10 06:43:03 PM PDT 24
Peak memory 206372 kb
Host smart-d794328c-fb7b-4956-8e26-d2831e3d2c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26480
82895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2648082895
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.518711391
Short name T1391
Test name
Test status
Simulation time 21871124631 ps
CPU time 50.64 seconds
Started Jul 10 06:43:01 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206708 kb
Host smart-344d6a64-a828-4c3a-a169-a63b84b76d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51871
1391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.518711391
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2892981408
Short name T2436
Test name
Test status
Simulation time 170962250 ps
CPU time 0.8 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206360 kb
Host smart-d5a66f9c-f331-4faf-ab07-aba561e713b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28929
81408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2892981408
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2007156964
Short name T563
Test name
Test status
Simulation time 177704501 ps
CPU time 0.87 seconds
Started Jul 10 06:43:01 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206364 kb
Host smart-925f6b80-c442-4e2e-bf0c-97c430ae284e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20071
56964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2007156964
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.400124249
Short name T2622
Test name
Test status
Simulation time 210673331 ps
CPU time 0.85 seconds
Started Jul 10 06:43:02 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206392 kb
Host smart-69a3c6e7-ce12-4248-b8b6-2ca6ed326ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40012
4249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.400124249
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3689925612
Short name T1872
Test name
Test status
Simulation time 195067241 ps
CPU time 0.88 seconds
Started Jul 10 06:43:00 PM PDT 24
Finished Jul 10 06:43:03 PM PDT 24
Peak memory 206388 kb
Host smart-9d05f0b1-fa65-4526-a89e-aa62ffb525f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36899
25612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3689925612
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1608338474
Short name T2608
Test name
Test status
Simulation time 171899110 ps
CPU time 0.8 seconds
Started Jul 10 06:43:02 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206356 kb
Host smart-1d435726-50e6-45d2-966e-e86cfa0c761b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16083
38474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1608338474
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1440390627
Short name T1484
Test name
Test status
Simulation time 143658025 ps
CPU time 0.75 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206356 kb
Host smart-781adbe9-d517-4013-9e35-77de9ab46f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14403
90627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1440390627
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.10336129
Short name T533
Test name
Test status
Simulation time 218822822 ps
CPU time 0.87 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:15 PM PDT 24
Peak memory 206352 kb
Host smart-fe8499c5-7d7f-45af-9973-c96052ace786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10336
129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.10336129
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1803692284
Short name T1371
Test name
Test status
Simulation time 278886963 ps
CPU time 0.99 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:15 PM PDT 24
Peak memory 206340 kb
Host smart-dca2b330-1586-477e-b000-65df47b22c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18036
92284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1803692284
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3479255864
Short name T2651
Test name
Test status
Simulation time 5453038558 ps
CPU time 51.93 seconds
Started Jul 10 06:43:00 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206812 kb
Host smart-0c8d2251-b2e2-4b1e-8638-d005e17c8bbf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3479255864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3479255864
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2757264594
Short name T2011
Test name
Test status
Simulation time 159589215 ps
CPU time 0.78 seconds
Started Jul 10 06:43:01 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206384 kb
Host smart-bac836ee-b039-4d8c-b237-745a208aed8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27572
64594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2757264594
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3880289699
Short name T1201
Test name
Test status
Simulation time 183232419 ps
CPU time 0.8 seconds
Started Jul 10 06:43:00 PM PDT 24
Finished Jul 10 06:43:03 PM PDT 24
Peak memory 206388 kb
Host smart-e6c6fd62-e4c8-40da-9c66-f4abac3ff71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802
89699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3880289699
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3161581090
Short name T462
Test name
Test status
Simulation time 658333165 ps
CPU time 1.92 seconds
Started Jul 10 06:43:01 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206380 kb
Host smart-4cd10c3d-9a2c-435c-841a-c56fc2fef78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31615
81090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3161581090
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2995071373
Short name T2306
Test name
Test status
Simulation time 6791479428 ps
CPU time 201.73 seconds
Started Jul 10 06:43:01 PM PDT 24
Finished Jul 10 06:46:25 PM PDT 24
Peak memory 206652 kb
Host smart-eaca7cf2-e504-49ba-9375-e8e7d1864a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29950
71373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2995071373
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.621027735
Short name T1301
Test name
Test status
Simulation time 44283697 ps
CPU time 0.71 seconds
Started Jul 10 06:43:11 PM PDT 24
Finished Jul 10 06:43:16 PM PDT 24
Peak memory 206424 kb
Host smart-87ac8298-199f-45a9-afab-aff6b00fcf54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=621027735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.621027735
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3370503375
Short name T1145
Test name
Test status
Simulation time 3458995939 ps
CPU time 3.9 seconds
Started Jul 10 06:43:02 PM PDT 24
Finished Jul 10 06:43:08 PM PDT 24
Peak memory 206712 kb
Host smart-acff4349-fa08-4dc6-9b4e-48afae9e4b84
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3370503375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.3370503375
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1519168044
Short name T1217
Test name
Test status
Simulation time 13468176625 ps
CPU time 12.88 seconds
Started Jul 10 06:43:01 PM PDT 24
Finished Jul 10 06:43:16 PM PDT 24
Peak memory 206676 kb
Host smart-35995070-5f91-445c-944f-4ca8782da0fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1519168044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1519168044
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1479510710
Short name T1617
Test name
Test status
Simulation time 23507215005 ps
CPU time 23.9 seconds
Started Jul 10 06:43:03 PM PDT 24
Finished Jul 10 06:43:29 PM PDT 24
Peak memory 206664 kb
Host smart-17ffe924-26a3-49a1-aaf1-fcb8d08efa09
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1479510710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1479510710
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4050999477
Short name T2043
Test name
Test status
Simulation time 164304528 ps
CPU time 0.8 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206332 kb
Host smart-d49c7a2b-e603-4c10-859c-f198e85dba22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40509
99477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4050999477
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2475087030
Short name T1938
Test name
Test status
Simulation time 149800790 ps
CPU time 0.81 seconds
Started Jul 10 06:43:02 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206392 kb
Host smart-24c980ec-c98f-4cf9-9263-d359029bc40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24750
87030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2475087030
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.261646680
Short name T1192
Test name
Test status
Simulation time 281889268 ps
CPU time 1.11 seconds
Started Jul 10 06:43:02 PM PDT 24
Finished Jul 10 06:43:05 PM PDT 24
Peak memory 206404 kb
Host smart-46cf957a-c1f3-435a-a26e-6182ae9890c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26164
6680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.261646680
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2113536805
Short name T982
Test name
Test status
Simulation time 1210257586 ps
CPU time 3.08 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206552 kb
Host smart-03669b8e-4214-4ce2-b1f7-9a5611de0095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21135
36805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2113536805
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.44089598
Short name T891
Test name
Test status
Simulation time 10838773811 ps
CPU time 19.1 seconds
Started Jul 10 06:43:02 PM PDT 24
Finished Jul 10 06:43:23 PM PDT 24
Peak memory 206600 kb
Host smart-e5a9bec9-e477-49b1-9220-4d03a6a13f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44089
598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.44089598
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3309065023
Short name T1508
Test name
Test status
Simulation time 364789614 ps
CPU time 1.15 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:18 PM PDT 24
Peak memory 206380 kb
Host smart-43346268-9df0-44e8-9444-ec7425589603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33090
65023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3309065023
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.4229581527
Short name T1018
Test name
Test status
Simulation time 136711751 ps
CPU time 0.76 seconds
Started Jul 10 06:43:09 PM PDT 24
Finished Jul 10 06:43:12 PM PDT 24
Peak memory 206560 kb
Host smart-35d97a24-8b22-4aa6-8357-fc7f54a47cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42295
81527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.4229581527
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.132745735
Short name T236
Test name
Test status
Simulation time 35273915 ps
CPU time 0.67 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206356 kb
Host smart-02b57fdd-8573-4710-975e-d68a58715b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13274
5735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.132745735
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.209295961
Short name T317
Test name
Test status
Simulation time 926872168 ps
CPU time 2.2 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206596 kb
Host smart-8cb0efe9-4900-4ef0-946b-713aa9d394a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20929
5961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.209295961
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2537947080
Short name T651
Test name
Test status
Simulation time 234369710 ps
CPU time 1.64 seconds
Started Jul 10 06:43:11 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206640 kb
Host smart-be026a44-363f-44d7-8b5b-c6386eea6745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25379
47080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2537947080
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.388425093
Short name T1349
Test name
Test status
Simulation time 197329410 ps
CPU time 0.82 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:15 PM PDT 24
Peak memory 206388 kb
Host smart-6265ab2d-3e76-4356-8b1e-d1c4b9abd6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842
5093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.388425093
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.262584416
Short name T2457
Test name
Test status
Simulation time 180143899 ps
CPU time 0.84 seconds
Started Jul 10 06:43:13 PM PDT 24
Finished Jul 10 06:43:20 PM PDT 24
Peak memory 206392 kb
Host smart-4813b972-7bb5-4dfc-9838-c70ef4e01d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26258
4416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.262584416
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3606173633
Short name T709
Test name
Test status
Simulation time 172408856 ps
CPU time 0.81 seconds
Started Jul 10 06:43:14 PM PDT 24
Finished Jul 10 06:43:21 PM PDT 24
Peak memory 206376 kb
Host smart-4abd7b7a-3365-47ab-bdf1-73b1218a0bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36061
73633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3606173633
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.3803357356
Short name T217
Test name
Test status
Simulation time 11324637102 ps
CPU time 321.26 seconds
Started Jul 10 06:43:11 PM PDT 24
Finished Jul 10 06:48:37 PM PDT 24
Peak memory 206628 kb
Host smart-17475870-5fca-44f0-a3cf-527771c64625
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3803357356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.3803357356
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.632602350
Short name T594
Test name
Test status
Simulation time 259100066 ps
CPU time 0.91 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:15 PM PDT 24
Peak memory 206360 kb
Host smart-dbfdc96e-09d0-48c3-bce4-a938f2280648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63260
2350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.632602350
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1966984789
Short name T948
Test name
Test status
Simulation time 23329376431 ps
CPU time 28.68 seconds
Started Jul 10 06:43:14 PM PDT 24
Finished Jul 10 06:43:48 PM PDT 24
Peak memory 206440 kb
Host smart-c3fc8503-299c-421e-8ecf-ff45ebf0ee52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19669
84789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1966984789
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3106441986
Short name T320
Test name
Test status
Simulation time 3271181235 ps
CPU time 4.44 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206456 kb
Host smart-5873c7e7-3a28-411e-8926-bb50b84f1457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31064
41986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3106441986
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1777456376
Short name T2168
Test name
Test status
Simulation time 6694746699 ps
CPU time 47.25 seconds
Started Jul 10 06:43:08 PM PDT 24
Finished Jul 10 06:43:56 PM PDT 24
Peak memory 206684 kb
Host smart-89a5d2fb-c92f-40aa-bf86-dc6a8cdc3f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17774
56376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1777456376
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3966561649
Short name T1469
Test name
Test status
Simulation time 4055471863 ps
CPU time 39.44 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206652 kb
Host smart-b0ed56fd-b5e8-4f19-b83d-11e5d424c8bd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3966561649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3966561649
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1234853510
Short name T1213
Test name
Test status
Simulation time 236582488 ps
CPU time 0.93 seconds
Started Jul 10 06:43:09 PM PDT 24
Finished Jul 10 06:43:11 PM PDT 24
Peak memory 206328 kb
Host smart-3cb11ba7-7f73-4e83-95cb-1c515ca1c3bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1234853510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1234853510
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2724486250
Short name T362
Test name
Test status
Simulation time 190206934 ps
CPU time 0.84 seconds
Started Jul 10 06:43:11 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206340 kb
Host smart-8c5dbf09-2d80-4296-9db8-73e023098aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27244
86250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2724486250
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.1345603612
Short name T568
Test name
Test status
Simulation time 3789018894 ps
CPU time 38.02 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:55 PM PDT 24
Peak memory 206724 kb
Host smart-d30282ec-bd29-4889-9822-09d9fac113e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13456
03612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.1345603612
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.370343469
Short name T163
Test name
Test status
Simulation time 5080918499 ps
CPU time 140.37 seconds
Started Jul 10 06:43:11 PM PDT 24
Finished Jul 10 06:45:36 PM PDT 24
Peak memory 206644 kb
Host smart-de359e19-f378-4191-928a-70535a103c15
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=370343469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.370343469
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.4049647066
Short name T1089
Test name
Test status
Simulation time 170382823 ps
CPU time 0.91 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206392 kb
Host smart-7510b520-bd59-4575-81c9-205c8be5180d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4049647066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.4049647066
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3895110454
Short name T2390
Test name
Test status
Simulation time 147430659 ps
CPU time 0.79 seconds
Started Jul 10 06:43:14 PM PDT 24
Finished Jul 10 06:43:20 PM PDT 24
Peak memory 206368 kb
Host smart-1c45572c-133f-47ec-b524-e3f10000e5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38951
10454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3895110454
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.804463952
Short name T142
Test name
Test status
Simulation time 207155126 ps
CPU time 0.92 seconds
Started Jul 10 06:43:09 PM PDT 24
Finished Jul 10 06:43:12 PM PDT 24
Peak memory 206376 kb
Host smart-50c262aa-853e-47ed-88e3-06e9b04c786f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80446
3952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.804463952
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.738652204
Short name T101
Test name
Test status
Simulation time 199647404 ps
CPU time 0.86 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206372 kb
Host smart-a286ab15-13fe-464e-9304-136942f90802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73865
2204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.738652204
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.335469886
Short name T2554
Test name
Test status
Simulation time 150952685 ps
CPU time 0.77 seconds
Started Jul 10 06:43:13 PM PDT 24
Finished Jul 10 06:43:19 PM PDT 24
Peak memory 206372 kb
Host smart-45117a0f-8197-445f-b96d-031c27c82e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33546
9886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.335469886
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.4273219957
Short name T1694
Test name
Test status
Simulation time 148468662 ps
CPU time 0.78 seconds
Started Jul 10 06:43:14 PM PDT 24
Finished Jul 10 06:43:21 PM PDT 24
Peak memory 206380 kb
Host smart-25f751da-854f-4866-9b21-d9a771a56417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42732
19957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.4273219957
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1028706966
Short name T175
Test name
Test status
Simulation time 180774484 ps
CPU time 0.81 seconds
Started Jul 10 06:43:14 PM PDT 24
Finished Jul 10 06:43:20 PM PDT 24
Peak memory 206400 kb
Host smart-7f86dbe9-4d1e-4ecf-9511-8c09f3d47129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10287
06966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1028706966
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2453386116
Short name T1627
Test name
Test status
Simulation time 267069306 ps
CPU time 0.87 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206392 kb
Host smart-66b990c3-43cf-42a2-86f5-acf95a1e164d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2453386116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2453386116
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2738541874
Short name T597
Test name
Test status
Simulation time 163899015 ps
CPU time 0.8 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206380 kb
Host smart-702fc3b7-dc34-4ae8-9d9c-8770dde9a131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27385
41874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2738541874
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2015419913
Short name T2486
Test name
Test status
Simulation time 35916707 ps
CPU time 0.67 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:18 PM PDT 24
Peak memory 206388 kb
Host smart-0ab3fe37-d82f-45ea-b71a-4dbf4d7d9103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20154
19913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2015419913
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.156039501
Short name T1111
Test name
Test status
Simulation time 16826051755 ps
CPU time 35.67 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:52 PM PDT 24
Peak memory 206700 kb
Host smart-3b5ebf6e-ceef-4347-8cc2-21cccff03275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
9501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.156039501
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.863070817
Short name T627
Test name
Test status
Simulation time 231222361 ps
CPU time 0.87 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:18 PM PDT 24
Peak memory 206380 kb
Host smart-ccf99ca8-f8af-49da-bec0-789099109d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86307
0817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.863070817
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.975609349
Short name T472
Test name
Test status
Simulation time 204613224 ps
CPU time 0.87 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206336 kb
Host smart-64e534a1-a633-4efb-80f7-69311a06a8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97560
9349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.975609349
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1142880876
Short name T828
Test name
Test status
Simulation time 230077720 ps
CPU time 0.97 seconds
Started Jul 10 06:43:11 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206388 kb
Host smart-3a64a193-8dc6-42f9-8011-c2c3d25edeba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11428
80876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1142880876
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1790263643
Short name T1673
Test name
Test status
Simulation time 165124982 ps
CPU time 0.82 seconds
Started Jul 10 06:43:13 PM PDT 24
Finished Jul 10 06:43:20 PM PDT 24
Peak memory 206376 kb
Host smart-9f89a983-d76d-4df1-a39e-32a05942bb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17902
63643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1790263643
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2815433232
Short name T49
Test name
Test status
Simulation time 159685950 ps
CPU time 0.76 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206376 kb
Host smart-d403dea2-f131-4aaa-b700-145bac2b7d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28154
33232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2815433232
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3734153698
Short name T364
Test name
Test status
Simulation time 198259879 ps
CPU time 0.87 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206276 kb
Host smart-ef0f3e44-8110-4302-bc35-5c28f2ceea42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37341
53698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3734153698
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1539386649
Short name T1852
Test name
Test status
Simulation time 158434867 ps
CPU time 0.79 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:15 PM PDT 24
Peak memory 206376 kb
Host smart-5a6ef7cb-8f93-458c-8eb1-278fc3288970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15393
86649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1539386649
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1761177866
Short name T1607
Test name
Test status
Simulation time 263708821 ps
CPU time 0.99 seconds
Started Jul 10 06:43:10 PM PDT 24
Finished Jul 10 06:43:14 PM PDT 24
Peak memory 206360 kb
Host smart-8d8ae542-ed38-487f-84ad-c39573472ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17611
77866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1761177866
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1265096847
Short name T1126
Test name
Test status
Simulation time 5280803784 ps
CPU time 142.99 seconds
Started Jul 10 06:43:13 PM PDT 24
Finished Jul 10 06:45:42 PM PDT 24
Peak memory 206612 kb
Host smart-00f23e40-f680-4f9e-8683-30db4d535c3e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1265096847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1265096847
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3049491494
Short name T338
Test name
Test status
Simulation time 145420046 ps
CPU time 0.79 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:17 PM PDT 24
Peak memory 206396 kb
Host smart-27d90b5c-75a1-4306-9761-8b67542bddb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30494
91494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3049491494
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2390527598
Short name T1483
Test name
Test status
Simulation time 177675191 ps
CPU time 0.83 seconds
Started Jul 10 06:43:15 PM PDT 24
Finished Jul 10 06:43:21 PM PDT 24
Peak memory 206372 kb
Host smart-74bd1341-b486-4f58-ade0-192a6ffa1116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23905
27598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2390527598
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3174720182
Short name T2476
Test name
Test status
Simulation time 210895340 ps
CPU time 0.91 seconds
Started Jul 10 06:43:16 PM PDT 24
Finished Jul 10 06:43:22 PM PDT 24
Peak memory 206364 kb
Host smart-b0596db1-c6f5-448b-89d8-41e3de79e78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31747
20182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3174720182
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2679748879
Short name T1634
Test name
Test status
Simulation time 4509422203 ps
CPU time 121.4 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:45:19 PM PDT 24
Peak memory 206664 kb
Host smart-0804265a-5e8e-4654-b725-cbb0d2b32348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26797
48879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2679748879
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3502161326
Short name T1532
Test name
Test status
Simulation time 50349440 ps
CPU time 0.66 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:34 PM PDT 24
Peak memory 206416 kb
Host smart-a073e32e-b39d-4af8-bef8-5edbba51c118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3502161326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3502161326
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3181747964
Short name T2095
Test name
Test status
Simulation time 4314682762 ps
CPU time 5.85 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:23 PM PDT 24
Peak memory 206444 kb
Host smart-b6085180-332e-4cd1-86a5-626d222ae884
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3181747964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3181747964
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2883683772
Short name T1720
Test name
Test status
Simulation time 13390812277 ps
CPU time 14.94 seconds
Started Jul 10 06:43:09 PM PDT 24
Finished Jul 10 06:43:25 PM PDT 24
Peak memory 206448 kb
Host smart-941f47e9-18c2-4835-81e8-68f4b5d288aa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2883683772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2883683772
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.302528854
Short name T2311
Test name
Test status
Simulation time 23408583806 ps
CPU time 22.62 seconds
Started Jul 10 06:43:11 PM PDT 24
Finished Jul 10 06:43:38 PM PDT 24
Peak memory 206460 kb
Host smart-79159259-52ca-4064-8976-b0c2090f7143
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=302528854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.302528854
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1885535687
Short name T1442
Test name
Test status
Simulation time 194232643 ps
CPU time 0.87 seconds
Started Jul 10 06:43:15 PM PDT 24
Finished Jul 10 06:43:21 PM PDT 24
Peak memory 206376 kb
Host smart-0ead51b7-624b-4d66-a7c8-4e1fac5c12d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18855
35687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1885535687
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.832857916
Short name T1584
Test name
Test status
Simulation time 150174506 ps
CPU time 0.79 seconds
Started Jul 10 06:43:11 PM PDT 24
Finished Jul 10 06:43:16 PM PDT 24
Peak memory 206380 kb
Host smart-fb046fa1-19b6-408d-bc6e-fe4fa9124078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83285
7916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.832857916
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2116059812
Short name T105
Test name
Test status
Simulation time 288004959 ps
CPU time 1.12 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:18 PM PDT 24
Peak memory 206380 kb
Host smart-eae391b6-07dd-4305-9576-9142c1a80de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
59812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2116059812
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2653388824
Short name T2408
Test name
Test status
Simulation time 1360960845 ps
CPU time 3.13 seconds
Started Jul 10 06:43:16 PM PDT 24
Finished Jul 10 06:43:24 PM PDT 24
Peak memory 206576 kb
Host smart-de95a9aa-55d4-4425-b6e5-6ebf07719d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26533
88824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2653388824
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1067714080
Short name T884
Test name
Test status
Simulation time 12446170669 ps
CPU time 24.65 seconds
Started Jul 10 06:43:12 PM PDT 24
Finished Jul 10 06:43:42 PM PDT 24
Peak memory 206624 kb
Host smart-62ee6dc7-98f6-4767-a902-31aaa71af356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10677
14080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1067714080
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3465568005
Short name T1713
Test name
Test status
Simulation time 494533303 ps
CPU time 1.39 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:28 PM PDT 24
Peak memory 206396 kb
Host smart-ad6b6cde-9cd9-44fe-826f-0e7a8a8664f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655
68005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3465568005
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1652835185
Short name T427
Test name
Test status
Simulation time 162251107 ps
CPU time 0.8 seconds
Started Jul 10 06:43:21 PM PDT 24
Finished Jul 10 06:43:26 PM PDT 24
Peak memory 206380 kb
Host smart-57140a1b-f99f-4893-98ca-8b8965c870cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
35185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1652835185
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3155312968
Short name T368
Test name
Test status
Simulation time 63548409 ps
CPU time 0.69 seconds
Started Jul 10 06:43:23 PM PDT 24
Finished Jul 10 06:43:29 PM PDT 24
Peak memory 206380 kb
Host smart-d4b1eab5-6464-44ee-8e6d-e901b5b45635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31553
12968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3155312968
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1326816369
Short name T1110
Test name
Test status
Simulation time 854246787 ps
CPU time 2.18 seconds
Started Jul 10 06:43:20 PM PDT 24
Finished Jul 10 06:43:26 PM PDT 24
Peak memory 206568 kb
Host smart-66c1a171-a672-4030-97c0-a1684dd9be02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13268
16369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1326816369
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1160469533
Short name T1664
Test name
Test status
Simulation time 348485738 ps
CPU time 2.41 seconds
Started Jul 10 06:43:25 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206624 kb
Host smart-604c7fe4-b886-4fbd-b52f-7a9f09026635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
69533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1160469533
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1114885472
Short name T1496
Test name
Test status
Simulation time 194405221 ps
CPU time 0.87 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:27 PM PDT 24
Peak memory 206372 kb
Host smart-beb62c64-f9d9-4631-9aff-b69835e4a22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11148
85472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1114885472
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1689929328
Short name T1826
Test name
Test status
Simulation time 163906009 ps
CPU time 0.77 seconds
Started Jul 10 06:43:19 PM PDT 24
Finished Jul 10 06:43:24 PM PDT 24
Peak memory 206360 kb
Host smart-b1fc42f3-d842-49bc-8e30-3fe302bda0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16899
29328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1689929328
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.607193040
Short name T1685
Test name
Test status
Simulation time 196989482 ps
CPU time 0.86 seconds
Started Jul 10 06:43:20 PM PDT 24
Finished Jul 10 06:43:25 PM PDT 24
Peak memory 206308 kb
Host smart-4905ddbd-c0d7-44fb-a3c7-787cc0b2e530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60719
3040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.607193040
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.1143049739
Short name T102
Test name
Test status
Simulation time 9237849885 ps
CPU time 262.95 seconds
Started Jul 10 06:43:19 PM PDT 24
Finished Jul 10 06:47:46 PM PDT 24
Peak memory 206808 kb
Host smart-16fb955d-2066-4c34-b9ff-6ce0a339938a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1143049739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1143049739
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.2031002395
Short name T1298
Test name
Test status
Simulation time 12190720273 ps
CPU time 103.81 seconds
Started Jul 10 06:43:19 PM PDT 24
Finished Jul 10 06:45:07 PM PDT 24
Peak memory 206644 kb
Host smart-ea6b8ff9-ec8b-4994-abf5-d96152056e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20310
02395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.2031002395
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.877046276
Short name T432
Test name
Test status
Simulation time 231385610 ps
CPU time 0.96 seconds
Started Jul 10 06:43:21 PM PDT 24
Finished Jul 10 06:43:26 PM PDT 24
Peak memory 206360 kb
Host smart-1749fa98-edc9-4f20-a880-4daa3fdf8628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87704
6276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.877046276
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2118998757
Short name T1036
Test name
Test status
Simulation time 23283059853 ps
CPU time 25.22 seconds
Started Jul 10 06:43:18 PM PDT 24
Finished Jul 10 06:43:48 PM PDT 24
Peak memory 206444 kb
Host smart-6c3b19c2-059e-4daa-8e1c-8e894679587a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21189
98757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2118998757
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2559406189
Short name T1020
Test name
Test status
Simulation time 3298174182 ps
CPU time 4.64 seconds
Started Jul 10 06:43:25 PM PDT 24
Finished Jul 10 06:43:34 PM PDT 24
Peak memory 206440 kb
Host smart-41c3b062-6192-4675-9c29-ad07386b30b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25594
06189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2559406189
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3247641346
Short name T1189
Test name
Test status
Simulation time 8021530807 ps
CPU time 79.25 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:44:45 PM PDT 24
Peak memory 206712 kb
Host smart-a5e330b8-ea6b-4a86-b3cf-5fa93aac7ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32476
41346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3247641346
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1415267348
Short name T2736
Test name
Test status
Simulation time 4127449106 ps
CPU time 28.47 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:56 PM PDT 24
Peak memory 206712 kb
Host smart-9f127116-3ff4-4f5c-8c53-d07c8fd2a053
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1415267348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1415267348
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1285989738
Short name T1005
Test name
Test status
Simulation time 231391307 ps
CPU time 0.91 seconds
Started Jul 10 06:43:25 PM PDT 24
Finished Jul 10 06:43:30 PM PDT 24
Peak memory 206088 kb
Host smart-b8b4c008-a20c-468f-a451-c32fd3d4061a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1285989738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1285989738
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.373937317
Short name T575
Test name
Test status
Simulation time 239733529 ps
CPU time 0.97 seconds
Started Jul 10 06:43:21 PM PDT 24
Finished Jul 10 06:43:26 PM PDT 24
Peak memory 206384 kb
Host smart-25d3aca0-4abf-48bb-a7a3-bea89e74e45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37393
7317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.373937317
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2892625182
Short name T592
Test name
Test status
Simulation time 6517119900 ps
CPU time 61.48 seconds
Started Jul 10 06:43:19 PM PDT 24
Finished Jul 10 06:44:25 PM PDT 24
Peak memory 206644 kb
Host smart-12edc8a6-38b1-4a65-8ddc-98dca0a11586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28926
25182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2892625182
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3933952306
Short name T1256
Test name
Test status
Simulation time 5694625640 ps
CPU time 53.55 seconds
Started Jul 10 06:43:20 PM PDT 24
Finished Jul 10 06:44:17 PM PDT 24
Peak memory 206700 kb
Host smart-1afd629a-0d05-4f79-ac51-c65a36b72b79
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3933952306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3933952306
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.732126993
Short name T2321
Test name
Test status
Simulation time 164460163 ps
CPU time 0.81 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:28 PM PDT 24
Peak memory 206284 kb
Host smart-292ea16a-2cd2-4f94-b54c-b0c31d311d3a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=732126993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.732126993
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3404798919
Short name T1025
Test name
Test status
Simulation time 165179055 ps
CPU time 0.79 seconds
Started Jul 10 06:43:19 PM PDT 24
Finished Jul 10 06:43:24 PM PDT 24
Peak memory 206380 kb
Host smart-ba1936c0-b9b6-4313-8ea8-092dd4700bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047
98919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3404798919
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4048920370
Short name T1692
Test name
Test status
Simulation time 225451272 ps
CPU time 0.88 seconds
Started Jul 10 06:43:21 PM PDT 24
Finished Jul 10 06:43:26 PM PDT 24
Peak memory 206376 kb
Host smart-2f708c18-541e-425f-abb9-8910e1eeb183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40489
20370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4048920370
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3420675836
Short name T1482
Test name
Test status
Simulation time 188207534 ps
CPU time 0.89 seconds
Started Jul 10 06:43:19 PM PDT 24
Finished Jul 10 06:43:24 PM PDT 24
Peak memory 206564 kb
Host smart-630b5751-faca-4937-a9a7-6ecfab4171c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34206
75836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3420675836
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2939424338
Short name T2387
Test name
Test status
Simulation time 169196750 ps
CPU time 0.8 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:28 PM PDT 24
Peak memory 206284 kb
Host smart-4d7643ec-4dbf-4186-8628-1b157416b994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29394
24338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2939424338
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1161701533
Short name T2716
Test name
Test status
Simulation time 230444986 ps
CPU time 0.83 seconds
Started Jul 10 06:43:21 PM PDT 24
Finished Jul 10 06:43:26 PM PDT 24
Peak memory 206392 kb
Host smart-3e652deb-2b45-4dfc-b285-7f2a7f345725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11617
01533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1161701533
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3015419570
Short name T1042
Test name
Test status
Simulation time 180671637 ps
CPU time 0.8 seconds
Started Jul 10 06:43:20 PM PDT 24
Finished Jul 10 06:43:25 PM PDT 24
Peak memory 206376 kb
Host smart-5ab772cb-f109-47b6-bf40-648e4cd7bd75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30154
19570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3015419570
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1003294955
Short name T2752
Test name
Test status
Simulation time 262445350 ps
CPU time 1.01 seconds
Started Jul 10 06:43:23 PM PDT 24
Finished Jul 10 06:43:28 PM PDT 24
Peak memory 206380 kb
Host smart-5df61bfc-0550-4121-b0ba-c654dfde348d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1003294955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1003294955
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3203590678
Short name T1980
Test name
Test status
Simulation time 143655710 ps
CPU time 0.75 seconds
Started Jul 10 06:43:21 PM PDT 24
Finished Jul 10 06:43:25 PM PDT 24
Peak memory 206368 kb
Host smart-970a34ee-a348-4fd5-a5e1-efb14dc64cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32035
90678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3203590678
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.72107998
Short name T35
Test name
Test status
Simulation time 51110539 ps
CPU time 0.73 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:27 PM PDT 24
Peak memory 206304 kb
Host smart-70ecc240-d534-472c-8549-3117a3358c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72107
998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.72107998
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.742346542
Short name T1389
Test name
Test status
Simulation time 7192635977 ps
CPU time 16.9 seconds
Started Jul 10 06:43:25 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206568 kb
Host smart-70070936-2fde-4930-891e-501ccb232158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74234
6542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.742346542
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2594797536
Short name T676
Test name
Test status
Simulation time 195328515 ps
CPU time 0.79 seconds
Started Jul 10 06:43:25 PM PDT 24
Finished Jul 10 06:43:30 PM PDT 24
Peak memory 206124 kb
Host smart-bfcb7b4a-401f-4e8c-ac62-8c6ef3fc5da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25947
97536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2594797536
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1554168409
Short name T764
Test name
Test status
Simulation time 261202080 ps
CPU time 0.89 seconds
Started Jul 10 06:43:28 PM PDT 24
Finished Jul 10 06:43:33 PM PDT 24
Peak memory 206340 kb
Host smart-9867cf5f-2d5e-40bc-992b-92cda60bd867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
68409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1554168409
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.2760932390
Short name T2652
Test name
Test status
Simulation time 224137559 ps
CPU time 0.9 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:27 PM PDT 24
Peak memory 206364 kb
Host smart-f3f40e4f-1273-49ea-941b-4548c6bacec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27609
32390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.2760932390
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1237921775
Short name T2667
Test name
Test status
Simulation time 162348114 ps
CPU time 0.81 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206360 kb
Host smart-28a5516f-2113-4f74-9f3b-343fa9e5965f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12379
21775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1237921775
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2800034055
Short name T2318
Test name
Test status
Simulation time 190111295 ps
CPU time 0.85 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:27 PM PDT 24
Peak memory 206400 kb
Host smart-a9ae3968-2012-4a7b-9b3f-6da052bb7a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28000
34055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2800034055
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1882878868
Short name T2410
Test name
Test status
Simulation time 152197855 ps
CPU time 0.75 seconds
Started Jul 10 06:43:25 PM PDT 24
Finished Jul 10 06:43:30 PM PDT 24
Peak memory 206188 kb
Host smart-e518908a-4df6-4d28-9b12-73f9662f6bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18828
78868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1882878868
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2836495874
Short name T824
Test name
Test status
Simulation time 159498607 ps
CPU time 0.74 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:31 PM PDT 24
Peak memory 206352 kb
Host smart-2209f37d-9219-4714-a8ae-ee097dbc20dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28364
95874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2836495874
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.201429741
Short name T1381
Test name
Test status
Simulation time 218519585 ps
CPU time 0.93 seconds
Started Jul 10 06:43:21 PM PDT 24
Finished Jul 10 06:43:27 PM PDT 24
Peak memory 206376 kb
Host smart-bf853171-83f9-4bff-b62b-037591ef422d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20142
9741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.201429741
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3191132603
Short name T1094
Test name
Test status
Simulation time 2938284976 ps
CPU time 28.38 seconds
Started Jul 10 06:43:23 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206612 kb
Host smart-44480d46-8bb5-4746-8103-335312e3a08f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3191132603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3191132603
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.330710672
Short name T1415
Test name
Test status
Simulation time 178463625 ps
CPU time 0.84 seconds
Started Jul 10 06:43:28 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206356 kb
Host smart-0851427a-8665-48da-8071-32d9518c128e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071
0672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.330710672
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3161572071
Short name T497
Test name
Test status
Simulation time 169141829 ps
CPU time 0.8 seconds
Started Jul 10 06:43:28 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206352 kb
Host smart-5c207480-30f7-4e18-af35-6c5fa8e5c01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31615
72071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3161572071
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.3404638283
Short name T84
Test name
Test status
Simulation time 711056597 ps
CPU time 1.8 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:36 PM PDT 24
Peak memory 206632 kb
Host smart-3d1c9013-43b9-4cd6-81e4-e9a4ed351484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34046
38283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.3404638283
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3502709763
Short name T735
Test name
Test status
Simulation time 4371762734 ps
CPU time 29.42 seconds
Started Jul 10 06:43:23 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206712 kb
Host smart-7972ba43-0a6f-4bc3-beee-99ae3db3c8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35027
09763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3502709763
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.4201590353
Short name T2038
Test name
Test status
Simulation time 50659724 ps
CPU time 0.68 seconds
Started Jul 10 06:43:34 PM PDT 24
Finished Jul 10 06:43:41 PM PDT 24
Peak memory 206344 kb
Host smart-6e6ea380-6167-4dc6-9ae7-e4fed7e297aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4201590353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.4201590353
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3366260319
Short name T1262
Test name
Test status
Simulation time 3773899097 ps
CPU time 4.74 seconds
Started Jul 10 06:43:23 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206444 kb
Host smart-b1c0f186-30e9-4266-a4c1-d2997f66c99f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3366260319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3366260319
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2402812452
Short name T1838
Test name
Test status
Simulation time 13320971953 ps
CPU time 12.45 seconds
Started Jul 10 06:43:28 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206448 kb
Host smart-98113d52-33aa-43f2-a863-228ae0346855
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2402812452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2402812452
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.795148913
Short name T2409
Test name
Test status
Simulation time 23367330008 ps
CPU time 21.45 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:48 PM PDT 24
Peak memory 206640 kb
Host smart-1de87be7-b363-4175-ade5-ab3e395d90df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=795148913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.795148913
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3028697008
Short name T2257
Test name
Test status
Simulation time 164780061 ps
CPU time 0.85 seconds
Started Jul 10 06:43:23 PM PDT 24
Finished Jul 10 06:43:29 PM PDT 24
Peak memory 206372 kb
Host smart-c3f64c06-cf77-4121-8479-77d2abd8ce43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30286
97008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3028697008
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3934920196
Short name T1510
Test name
Test status
Simulation time 158173545 ps
CPU time 0.82 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:35 PM PDT 24
Peak memory 206380 kb
Host smart-78ace61b-0ef8-4050-b598-3c36978d1d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39349
20196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3934920196
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2178335458
Short name T2641
Test name
Test status
Simulation time 303813816 ps
CPU time 1.04 seconds
Started Jul 10 06:43:33 PM PDT 24
Finished Jul 10 06:43:40 PM PDT 24
Peak memory 206380 kb
Host smart-3e42f072-7d32-409e-a5cc-9818a478d322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21783
35458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2178335458
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3905177368
Short name T1866
Test name
Test status
Simulation time 1285564959 ps
CPU time 2.79 seconds
Started Jul 10 06:43:23 PM PDT 24
Finished Jul 10 06:43:30 PM PDT 24
Peak memory 206572 kb
Host smart-49369e53-091b-4fdf-891d-e387095d53eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39051
77368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3905177368
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3508897248
Short name T1355
Test name
Test status
Simulation time 10988765365 ps
CPU time 20.53 seconds
Started Jul 10 06:43:22 PM PDT 24
Finished Jul 10 06:43:47 PM PDT 24
Peak memory 206636 kb
Host smart-7586e3c0-4a67-401f-ad99-6374fc27ca99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35088
97248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3508897248
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.1471416258
Short name T2668
Test name
Test status
Simulation time 408808556 ps
CPU time 1.25 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:43:36 PM PDT 24
Peak memory 206380 kb
Host smart-c5a600f5-97a1-4071-802f-413fbeb1d698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
16258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.1471416258
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3330881706
Short name T1307
Test name
Test status
Simulation time 153695934 ps
CPU time 0.77 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:43:37 PM PDT 24
Peak memory 206392 kb
Host smart-0fb7359c-9805-4f4c-9df8-32201985b240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33308
81706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3330881706
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2929389800
Short name T547
Test name
Test status
Simulation time 56958282 ps
CPU time 0.69 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:31 PM PDT 24
Peak memory 206372 kb
Host smart-b356aed3-0ae4-42e1-9925-4590dfa0150c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29293
89800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2929389800
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.184435839
Short name T1972
Test name
Test status
Simulation time 1065221830 ps
CPU time 2.36 seconds
Started Jul 10 06:43:31 PM PDT 24
Finished Jul 10 06:43:39 PM PDT 24
Peak memory 206616 kb
Host smart-192ec638-67a9-4f5d-9869-e9efae1db81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18443
5839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.184435839
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3472091728
Short name T1245
Test name
Test status
Simulation time 175381058 ps
CPU time 1.63 seconds
Started Jul 10 06:43:35 PM PDT 24
Finished Jul 10 06:43:43 PM PDT 24
Peak memory 206496 kb
Host smart-348e4443-29cb-40bf-a25e-ea2ef259befb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34720
91728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3472091728
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2661001019
Short name T1450
Test name
Test status
Simulation time 307004161 ps
CPU time 0.94 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206400 kb
Host smart-ee01b1b3-1235-4e5e-8d81-cc58ca027967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26610
01019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2661001019
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3149133136
Short name T1218
Test name
Test status
Simulation time 141062593 ps
CPU time 0.76 seconds
Started Jul 10 06:43:26 PM PDT 24
Finished Jul 10 06:43:31 PM PDT 24
Peak memory 206360 kb
Host smart-bc103e70-8651-45b6-baf5-17f7ec6c84a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31491
33136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3149133136
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.328097265
Short name T1981
Test name
Test status
Simulation time 246423836 ps
CPU time 0.97 seconds
Started Jul 10 06:43:32 PM PDT 24
Finished Jul 10 06:43:39 PM PDT 24
Peak memory 206360 kb
Host smart-52a6c186-2104-4713-b052-6cdf692a755d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32809
7265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.328097265
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1214644646
Short name T1428
Test name
Test status
Simulation time 7732828980 ps
CPU time 52.17 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206672 kb
Host smart-0e69613d-42c5-4509-a150-60f60365c836
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1214644646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1214644646
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2851951105
Short name T633
Test name
Test status
Simulation time 217583181 ps
CPU time 0.95 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206360 kb
Host smart-f7065798-80b8-4b14-93fb-82ac6f2a56b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28519
51105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2851951105
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.2341372108
Short name T1379
Test name
Test status
Simulation time 23297798211 ps
CPU time 23.71 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:43:59 PM PDT 24
Peak memory 206364 kb
Host smart-f184a553-c4aa-4a22-9801-73ed5aab91ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
72108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.2341372108
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3007546968
Short name T1908
Test name
Test status
Simulation time 3312174805 ps
CPU time 3.57 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:43:40 PM PDT 24
Peak memory 206376 kb
Host smart-9c397754-320e-464c-8e78-3b46fb990b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30075
46968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3007546968
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.3400633385
Short name T2027
Test name
Test status
Simulation time 7807984154 ps
CPU time 72.41 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 206716 kb
Host smart-4a4b1e6f-b633-40db-b257-f6fdde651313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34006
33385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3400633385
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1149571382
Short name T2005
Test name
Test status
Simulation time 4255598339 ps
CPU time 121.92 seconds
Started Jul 10 06:43:32 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206636 kb
Host smart-7d1fe12a-5381-4306-931b-92a1b510d100
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1149571382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1149571382
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.577954032
Short name T577
Test name
Test status
Simulation time 268467565 ps
CPU time 0.99 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:36 PM PDT 24
Peak memory 206372 kb
Host smart-0a490933-071d-455d-ad0b-572b404bd062
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=577954032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.577954032
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2617009933
Short name T1244
Test name
Test status
Simulation time 195076243 ps
CPU time 0.89 seconds
Started Jul 10 06:43:26 PM PDT 24
Finished Jul 10 06:43:31 PM PDT 24
Peak memory 206384 kb
Host smart-69c4f5c6-70c4-4606-b82e-7b71655749dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26170
09933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2617009933
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3067178968
Short name T1561
Test name
Test status
Simulation time 3208362132 ps
CPU time 87.35 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:45:03 PM PDT 24
Peak memory 206640 kb
Host smart-6578d709-c32b-4fab-a036-b5fa8daf5f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30671
78968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3067178968
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.387531603
Short name T1419
Test name
Test status
Simulation time 2884606520 ps
CPU time 21.29 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206744 kb
Host smart-7569cda3-7bde-42de-9d7c-dfd4390372cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=387531603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.387531603
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.1198305260
Short name T999
Test name
Test status
Simulation time 185477434 ps
CPU time 0.83 seconds
Started Jul 10 06:43:31 PM PDT 24
Finished Jul 10 06:43:38 PM PDT 24
Peak memory 206392 kb
Host smart-60655476-179a-4843-ba82-bbb83c6efdb4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1198305260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.1198305260
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3207642297
Short name T2016
Test name
Test status
Simulation time 233032200 ps
CPU time 0.9 seconds
Started Jul 10 06:43:28 PM PDT 24
Finished Jul 10 06:43:33 PM PDT 24
Peak memory 206380 kb
Host smart-fd46ceff-6e9f-4864-96a1-3bff8c9f90ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32076
42297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3207642297
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3469508557
Short name T130
Test name
Test status
Simulation time 243016450 ps
CPU time 0.92 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:34 PM PDT 24
Peak memory 206376 kb
Host smart-5c23ac21-7453-4679-89c3-3bb4f6128202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34695
08557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3469508557
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.894658523
Short name T1830
Test name
Test status
Simulation time 181346177 ps
CPU time 0.81 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206372 kb
Host smart-13733fd0-350d-41ca-9dbd-05dac1010f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89465
8523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.894658523
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2805398047
Short name T1592
Test name
Test status
Simulation time 219340715 ps
CPU time 0.83 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:32 PM PDT 24
Peak memory 206376 kb
Host smart-3a783aca-6c2e-432a-866b-6c34b1cbfb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
98047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2805398047
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.759108836
Short name T2012
Test name
Test status
Simulation time 158414228 ps
CPU time 0.8 seconds
Started Jul 10 06:43:32 PM PDT 24
Finished Jul 10 06:43:39 PM PDT 24
Peak memory 206400 kb
Host smart-b6c1e6ae-c6d0-49d0-9d73-b99ce74167f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75910
8836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.759108836
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3092959810
Short name T1424
Test name
Test status
Simulation time 233582081 ps
CPU time 1.02 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:36 PM PDT 24
Peak memory 206380 kb
Host smart-b9c46509-cedd-445c-b8bf-7c5cd6701c46
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3092959810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3092959810
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3520851776
Short name T2265
Test name
Test status
Simulation time 150972321 ps
CPU time 0.76 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:34 PM PDT 24
Peak memory 206360 kb
Host smart-a7f37fa3-e57b-4f8b-b09a-f1a82e4f2076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35208
51776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3520851776
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2390943824
Short name T1556
Test name
Test status
Simulation time 38728964 ps
CPU time 0.68 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:31 PM PDT 24
Peak memory 206380 kb
Host smart-d44f386d-4507-4650-97de-267e585c0151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
43824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2390943824
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.206914995
Short name T1478
Test name
Test status
Simulation time 21473556748 ps
CPU time 48.24 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:44:22 PM PDT 24
Peak memory 214944 kb
Host smart-65ccd8cf-2d4f-4e89-b2c9-dbd78cb58c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20691
4995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.206914995
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3499053371
Short name T1662
Test name
Test status
Simulation time 226024658 ps
CPU time 0.87 seconds
Started Jul 10 06:43:28 PM PDT 24
Finished Jul 10 06:43:33 PM PDT 24
Peak memory 206404 kb
Host smart-55c4614b-4b59-4fbf-8615-9e78a5bb8689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
53371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3499053371
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3005145375
Short name T1237
Test name
Test status
Simulation time 223353093 ps
CPU time 0.91 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:34 PM PDT 24
Peak memory 206376 kb
Host smart-64e3efb5-f135-48ca-9cc5-e5f1dc92f58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051
45375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3005145375
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.1062257185
Short name T1003
Test name
Test status
Simulation time 188540132 ps
CPU time 0.79 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:35 PM PDT 24
Peak memory 206364 kb
Host smart-2c373670-c519-43d4-bbe3-9ce8da7eb485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10622
57185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.1062257185
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1470682444
Short name T2643
Test name
Test status
Simulation time 192781305 ps
CPU time 0.85 seconds
Started Jul 10 06:43:34 PM PDT 24
Finished Jul 10 06:43:41 PM PDT 24
Peak memory 206380 kb
Host smart-96c0fdcc-391a-430a-9aa5-5c76876293da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14706
82444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1470682444
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.113876365
Short name T1215
Test name
Test status
Simulation time 194483070 ps
CPU time 0.8 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:34 PM PDT 24
Peak memory 206380 kb
Host smart-ca066baa-3682-44d4-a301-ed7ff1270356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11387
6365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.113876365
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2105505926
Short name T2110
Test name
Test status
Simulation time 202651320 ps
CPU time 0.82 seconds
Started Jul 10 06:43:28 PM PDT 24
Finished Jul 10 06:43:33 PM PDT 24
Peak memory 206352 kb
Host smart-f9d660dd-2e3c-4524-bc78-6890ea6e8954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21055
05926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2105505926
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2065264628
Short name T1102
Test name
Test status
Simulation time 147717303 ps
CPU time 0.76 seconds
Started Jul 10 06:43:35 PM PDT 24
Finished Jul 10 06:43:42 PM PDT 24
Peak memory 206308 kb
Host smart-c11aedf2-e29f-4809-94fd-5c32caf3ec62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20652
64628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2065264628
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1278618531
Short name T1707
Test name
Test status
Simulation time 248776444 ps
CPU time 0.97 seconds
Started Jul 10 06:43:35 PM PDT 24
Finished Jul 10 06:43:42 PM PDT 24
Peak memory 206392 kb
Host smart-4ddbd85e-1edd-4cb1-be42-8053b7759d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12786
18531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1278618531
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.2383500256
Short name T1916
Test name
Test status
Simulation time 4084675005 ps
CPU time 39.99 seconds
Started Jul 10 06:43:34 PM PDT 24
Finished Jul 10 06:44:20 PM PDT 24
Peak memory 206688 kb
Host smart-a8a1f85e-4aa5-47dc-ac34-b95c2886c951
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2383500256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.2383500256
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1272709859
Short name T1328
Test name
Test status
Simulation time 190432917 ps
CPU time 0.86 seconds
Started Jul 10 06:43:34 PM PDT 24
Finished Jul 10 06:43:41 PM PDT 24
Peak memory 206384 kb
Host smart-ff7088fb-40db-465f-9c7f-16258b138791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12727
09859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1272709859
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2098055806
Short name T403
Test name
Test status
Simulation time 196144589 ps
CPU time 0.84 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:43:37 PM PDT 24
Peak memory 206400 kb
Host smart-2074e4cd-ea82-4909-99d4-6829aa790527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20980
55806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2098055806
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1118340605
Short name T1540
Test name
Test status
Simulation time 1264180558 ps
CPU time 2.87 seconds
Started Jul 10 06:43:32 PM PDT 24
Finished Jul 10 06:43:41 PM PDT 24
Peak memory 206628 kb
Host smart-17735e20-c112-46b8-b48d-4eb2b35f5aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11183
40605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1118340605
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1060975423
Short name T1231
Test name
Test status
Simulation time 3969874290 ps
CPU time 27.85 seconds
Started Jul 10 06:43:27 PM PDT 24
Finished Jul 10 06:43:59 PM PDT 24
Peak memory 206628 kb
Host smart-015c8087-99b1-447e-8643-b56a749514a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10609
75423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1060975423
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.479714463
Short name T1693
Test name
Test status
Simulation time 53552909 ps
CPU time 0.75 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206428 kb
Host smart-cd568d23-1c17-41af-8206-6f25867796e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=479714463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.479714463
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.4284038639
Short name T376
Test name
Test status
Simulation time 3965172026 ps
CPU time 4.46 seconds
Started Jul 10 06:43:34 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206444 kb
Host smart-c6bb5fc7-a399-42b7-83a6-cbaf8183e937
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4284038639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.4284038639
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1315963118
Short name T383
Test name
Test status
Simulation time 13382378114 ps
CPU time 12.68 seconds
Started Jul 10 06:43:30 PM PDT 24
Finished Jul 10 06:43:49 PM PDT 24
Peak memory 206716 kb
Host smart-f3254311-e78f-4978-91b9-4e99c6c301aa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1315963118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1315963118
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1416063275
Short name T2663
Test name
Test status
Simulation time 148024941 ps
CPU time 0.78 seconds
Started Jul 10 06:43:35 PM PDT 24
Finished Jul 10 06:43:42 PM PDT 24
Peak memory 206304 kb
Host smart-e0029f19-8ae0-4cb0-8b73-0228292afe8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14160
63275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1416063275
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.4214322694
Short name T451
Test name
Test status
Simulation time 156117295 ps
CPU time 0.78 seconds
Started Jul 10 06:43:33 PM PDT 24
Finished Jul 10 06:43:40 PM PDT 24
Peak memory 206396 kb
Host smart-0939549b-80d4-49f0-be0c-5cc9866c81a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42143
22694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.4214322694
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3585906860
Short name T1924
Test name
Test status
Simulation time 171787889 ps
CPU time 0.78 seconds
Started Jul 10 06:43:31 PM PDT 24
Finished Jul 10 06:43:38 PM PDT 24
Peak memory 206392 kb
Host smart-08893868-a101-4fd8-8ad3-4e24c79f8c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35859
06860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3585906860
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1639929432
Short name T632
Test name
Test status
Simulation time 703517031 ps
CPU time 1.67 seconds
Started Jul 10 06:43:29 PM PDT 24
Finished Jul 10 06:43:36 PM PDT 24
Peak memory 206588 kb
Host smart-b8349718-f4b1-43e5-9e9f-729ff5f76f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16399
29432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1639929432
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.337026857
Short name T2374
Test name
Test status
Simulation time 12990058355 ps
CPU time 23.22 seconds
Started Jul 10 06:43:31 PM PDT 24
Finished Jul 10 06:44:01 PM PDT 24
Peak memory 206648 kb
Host smart-0532f14c-5323-4fa4-a01a-5990278a6158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33702
6857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.337026857
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.651747262
Short name T1761
Test name
Test status
Simulation time 407125193 ps
CPU time 1.21 seconds
Started Jul 10 06:43:32 PM PDT 24
Finished Jul 10 06:43:40 PM PDT 24
Peak memory 206400 kb
Host smart-ad7a368c-f108-4c56-b3c2-c7d954544a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65174
7262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.651747262
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1743264128
Short name T374
Test name
Test status
Simulation time 166302925 ps
CPU time 0.79 seconds
Started Jul 10 06:43:28 PM PDT 24
Finished Jul 10 06:43:34 PM PDT 24
Peak memory 206304 kb
Host smart-048e0d83-651e-42d4-9ade-95d038f8b33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17432
64128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1743264128
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3343661806
Short name T523
Test name
Test status
Simulation time 95351548 ps
CPU time 0.7 seconds
Started Jul 10 06:43:32 PM PDT 24
Finished Jul 10 06:43:39 PM PDT 24
Peak memory 206384 kb
Host smart-14b24a1f-be7b-43f7-959e-d152feccf33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33436
61806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3343661806
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.3871539911
Short name T318
Test name
Test status
Simulation time 924660671 ps
CPU time 2.24 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206556 kb
Host smart-7c7566b7-a9ed-474e-b6e7-8536ddfcf212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38715
39911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3871539911
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.321670382
Short name T2711
Test name
Test status
Simulation time 196055365 ps
CPU time 2.18 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206744 kb
Host smart-0e3c6cb6-35fb-447b-8afc-df530a593dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167
0382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.321670382
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3005108755
Short name T949
Test name
Test status
Simulation time 255715085 ps
CPU time 0.91 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206396 kb
Host smart-698d2b64-b430-4f0e-b858-fe3c6d63f63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051
08755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3005108755
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1819398796
Short name T2693
Test name
Test status
Simulation time 147461196 ps
CPU time 0.78 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:43 PM PDT 24
Peak memory 206276 kb
Host smart-27b78cbe-6072-4099-852d-cb2709913b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18193
98796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1819398796
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.318429761
Short name T1831
Test name
Test status
Simulation time 211121275 ps
CPU time 0.84 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206376 kb
Host smart-0b208760-0614-46d8-9f18-a9a0ff0f78c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31842
9761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.318429761
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.769622106
Short name T106
Test name
Test status
Simulation time 9683449817 ps
CPU time 69.43 seconds
Started Jul 10 06:43:40 PM PDT 24
Finished Jul 10 06:44:55 PM PDT 24
Peak memory 206688 kb
Host smart-909a0f6f-2acf-4f6d-949a-8f4958ac2963
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=769622106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.769622106
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.432525681
Short name T2260
Test name
Test status
Simulation time 10763836962 ps
CPU time 90.96 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206656 kb
Host smart-82f8ebf5-f900-4861-98dc-aac6bdb564a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43252
5681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.432525681
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2802360425
Short name T2707
Test name
Test status
Simulation time 160509488 ps
CPU time 0.77 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:43 PM PDT 24
Peak memory 206388 kb
Host smart-7341924a-46e8-4685-b0da-225eb864354d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28023
60425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2802360425
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1402486134
Short name T624
Test name
Test status
Simulation time 23348316181 ps
CPU time 24.61 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:44:09 PM PDT 24
Peak memory 206440 kb
Host smart-905b60cd-cbbd-4931-a20d-c61a9b39f34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14024
86134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1402486134
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2854746926
Short name T606
Test name
Test status
Simulation time 3259172241 ps
CPU time 4.24 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206420 kb
Host smart-29a336d6-8956-4023-ae41-46cb397ee489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28547
46926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2854746926
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.760177786
Short name T1471
Test name
Test status
Simulation time 10087142934 ps
CPU time 273.96 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:48:16 PM PDT 24
Peak memory 206720 kb
Host smart-95ae6d87-c8a0-4661-8471-037d535e6704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76017
7786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.760177786
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.319630080
Short name T411
Test name
Test status
Simulation time 3053979737 ps
CPU time 22.45 seconds
Started Jul 10 06:43:41 PM PDT 24
Finished Jul 10 06:44:09 PM PDT 24
Peak memory 206512 kb
Host smart-f9745bf6-5deb-4dd5-b4e2-bdcea47b8d4a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=319630080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.319630080
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2432432763
Short name T1557
Test name
Test status
Simulation time 263353382 ps
CPU time 0.95 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206372 kb
Host smart-a2c64086-04ef-400a-a649-d07d1b84e175
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2432432763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2432432763
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2967533282
Short name T825
Test name
Test status
Simulation time 201015608 ps
CPU time 0.89 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:44 PM PDT 24
Peak memory 206376 kb
Host smart-d326bdad-6350-4841-807e-d19ceca848b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29675
33282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2967533282
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2097876897
Short name T2405
Test name
Test status
Simulation time 6115049703 ps
CPU time 173.7 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206664 kb
Host smart-e1031ab0-5114-4137-8ebb-d5af8463ebef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978
76897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2097876897
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2324289398
Short name T2215
Test name
Test status
Simulation time 7125913263 ps
CPU time 68.08 seconds
Started Jul 10 06:43:40 PM PDT 24
Finished Jul 10 06:44:55 PM PDT 24
Peak memory 206636 kb
Host smart-a64c5cab-7565-4f40-8d39-e04ae97c012f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2324289398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2324289398
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.867226275
Short name T929
Test name
Test status
Simulation time 171463751 ps
CPU time 0.81 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:43 PM PDT 24
Peak memory 206332 kb
Host smart-d003e34f-f7f6-43c4-8430-fc2ad09f96a5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=867226275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.867226275
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2134527021
Short name T669
Test name
Test status
Simulation time 154598279 ps
CPU time 0.77 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206308 kb
Host smart-cd0eaa49-09ba-4a74-bc9c-0812c3235a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
27021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2134527021
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.402250702
Short name T145
Test name
Test status
Simulation time 204537646 ps
CPU time 1 seconds
Started Jul 10 06:43:40 PM PDT 24
Finished Jul 10 06:43:47 PM PDT 24
Peak memory 205604 kb
Host smart-4cc8bf49-a195-44fe-b43b-658771edb604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40225
0702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.402250702
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.985248495
Short name T2454
Test name
Test status
Simulation time 183540282 ps
CPU time 0.99 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:43:44 PM PDT 24
Peak memory 206336 kb
Host smart-7632b49d-2b10-407f-b76f-87373905a7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98524
8495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.985248495
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1275549252
Short name T2366
Test name
Test status
Simulation time 172969793 ps
CPU time 0.88 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:43:44 PM PDT 24
Peak memory 206396 kb
Host smart-b9bc2443-add8-4f7e-b949-1cde86d66404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12755
49252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1275549252
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2017403277
Short name T646
Test name
Test status
Simulation time 217241671 ps
CPU time 0.86 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206392 kb
Host smart-9cace74d-25a1-4f70-bb93-9c169bba2c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20174
03277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2017403277
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3708165802
Short name T170
Test name
Test status
Simulation time 171968126 ps
CPU time 0.83 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206384 kb
Host smart-3b01f6d2-12cd-4d20-9411-f48eab073410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37081
65802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3708165802
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2279512554
Short name T2656
Test name
Test status
Simulation time 184411267 ps
CPU time 0.9 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:43 PM PDT 24
Peak memory 206376 kb
Host smart-5299c957-d180-490b-a108-01fc28d6cd0d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2279512554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2279512554
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2665904848
Short name T1815
Test name
Test status
Simulation time 142776618 ps
CPU time 0.83 seconds
Started Jul 10 06:43:41 PM PDT 24
Finished Jul 10 06:43:47 PM PDT 24
Peak memory 206156 kb
Host smart-937355a5-19fb-4fa3-9570-18887bd21fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
04848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2665904848
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4142491398
Short name T2518
Test name
Test status
Simulation time 41244076 ps
CPU time 0.66 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:43:44 PM PDT 24
Peak memory 206384 kb
Host smart-17ea7eb3-a79a-4b01-a2e4-f1fe3fe77b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41424
91398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4142491398
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1708592689
Short name T1710
Test name
Test status
Simulation time 16623368589 ps
CPU time 36.35 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:44:22 PM PDT 24
Peak memory 206740 kb
Host smart-745e0c16-4505-40a4-8990-0f256918884a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17085
92689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1708592689
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.134140044
Short name T2580
Test name
Test status
Simulation time 172239311 ps
CPU time 0.82 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206360 kb
Host smart-ac93a62d-e90c-41bf-ba1c-03e30bb61129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13414
0044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.134140044
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3968514344
Short name T337
Test name
Test status
Simulation time 225451611 ps
CPU time 0.94 seconds
Started Jul 10 06:43:35 PM PDT 24
Finished Jul 10 06:43:42 PM PDT 24
Peak memory 206372 kb
Host smart-bc475976-8bae-4355-9b6a-71deaffd9c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39685
14344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3968514344
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.1575237863
Short name T1887
Test name
Test status
Simulation time 241581923 ps
CPU time 0.87 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:43:44 PM PDT 24
Peak memory 206308 kb
Host smart-3ac39319-e671-43eb-b15a-5d6edc3e946f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752
37863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.1575237863
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.1754399697
Short name T1935
Test name
Test status
Simulation time 201733502 ps
CPU time 0.9 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206376 kb
Host smart-569a6f20-7f1b-46ec-81dc-8f68a50d7b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
99697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1754399697
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3497357118
Short name T2248
Test name
Test status
Simulation time 241573112 ps
CPU time 0.87 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:43 PM PDT 24
Peak memory 206388 kb
Host smart-21c8abf4-2092-4b37-a1a7-68e1196009c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34973
57118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3497357118
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3695683490
Short name T2717
Test name
Test status
Simulation time 208341135 ps
CPU time 0.88 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206396 kb
Host smart-c0de3cbb-b485-4b98-aab5-c7c72bb18933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36956
83490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3695683490
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2210248368
Short name T485
Test name
Test status
Simulation time 148183502 ps
CPU time 0.77 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206376 kb
Host smart-9e88fad5-9c18-4d4c-8dd3-c50eee9fc2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22102
48368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2210248368
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3925416132
Short name T1674
Test name
Test status
Simulation time 224166052 ps
CPU time 1 seconds
Started Jul 10 06:43:40 PM PDT 24
Finished Jul 10 06:43:47 PM PDT 24
Peak memory 206376 kb
Host smart-ddc3df1e-161a-41f0-be97-69daca14a6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39254
16132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3925416132
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.308321101
Short name T2694
Test name
Test status
Simulation time 4673308177 ps
CPU time 32.02 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206696 kb
Host smart-75d2a9fc-7afd-4e11-9de9-9f0378e55667
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=308321101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.308321101
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3618712214
Short name T1988
Test name
Test status
Simulation time 203157666 ps
CPU time 0.86 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:43:46 PM PDT 24
Peak memory 206384 kb
Host smart-048daf9c-4242-47cf-8329-2b1c87057eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36187
12214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3618712214
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.541192151
Short name T1639
Test name
Test status
Simulation time 171055157 ps
CPU time 0.8 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:43:44 PM PDT 24
Peak memory 206384 kb
Host smart-b33c59f8-3506-4516-9472-a63b418c8125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54119
2151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.541192151
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3173544898
Short name T1918
Test name
Test status
Simulation time 1333852762 ps
CPU time 2.63 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:43:47 PM PDT 24
Peak memory 206608 kb
Host smart-52e894a4-9b74-4039-b66f-0a7183d60752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31735
44898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3173544898
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2538911864
Short name T2262
Test name
Test status
Simulation time 5252331124 ps
CPU time 139.89 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:46:05 PM PDT 24
Peak memory 206628 kb
Host smart-755fb607-f64c-4b16-b0fd-d2ef9c0fed7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25389
11864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2538911864
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2450313325
Short name T2691
Test name
Test status
Simulation time 45932628 ps
CPU time 0.75 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:53 PM PDT 24
Peak memory 206420 kb
Host smart-f90659c7-c042-43a3-9a8c-7e64f0a5e596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2450313325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2450313325
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.4259438049
Short name T1098
Test name
Test status
Simulation time 4169066296 ps
CPU time 6.02 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:43:51 PM PDT 24
Peak memory 206444 kb
Host smart-4af49ead-38f4-45cf-91ca-e5bdb1803904
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4259438049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.4259438049
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3105971121
Short name T733
Test name
Test status
Simulation time 13411925283 ps
CPU time 14.03 seconds
Started Jul 10 06:43:39 PM PDT 24
Finished Jul 10 06:43:59 PM PDT 24
Peak memory 206644 kb
Host smart-e13b6454-6e01-4365-82e3-0c1a71a8ca71
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3105971121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3105971121
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2132126218
Short name T2673
Test name
Test status
Simulation time 23347202224 ps
CPU time 23.82 seconds
Started Jul 10 06:43:40 PM PDT 24
Finished Jul 10 06:44:10 PM PDT 24
Peak memory 206448 kb
Host smart-b1f39b38-71de-4f02-8f69-679777ea3210
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2132126218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2132126218
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1740655478
Short name T2120
Test name
Test status
Simulation time 180302406 ps
CPU time 0.9 seconds
Started Jul 10 06:43:37 PM PDT 24
Finished Jul 10 06:43:44 PM PDT 24
Peak memory 206244 kb
Host smart-b486cd73-7080-4630-8f95-f9edfa238237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17406
55478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1740655478
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.950471428
Short name T2555
Test name
Test status
Simulation time 171512056 ps
CPU time 0.82 seconds
Started Jul 10 06:43:40 PM PDT 24
Finished Jul 10 06:43:47 PM PDT 24
Peak memory 205732 kb
Host smart-402635b9-c54c-4f5f-8868-feb717a38ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95047
1428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.950471428
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3860912066
Short name T2575
Test name
Test status
Simulation time 416090626 ps
CPU time 1.34 seconds
Started Jul 10 06:43:36 PM PDT 24
Finished Jul 10 06:43:44 PM PDT 24
Peak memory 206392 kb
Host smart-e094a981-3fc7-4c7a-8167-698f46313391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38609
12066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3860912066
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2485602984
Short name T905
Test name
Test status
Simulation time 366461054 ps
CPU time 1.1 seconds
Started Jul 10 06:43:38 PM PDT 24
Finished Jul 10 06:43:45 PM PDT 24
Peak memory 206364 kb
Host smart-5fb09473-e6a3-417c-baa4-06393e7fb072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24856
02984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2485602984
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1205643870
Short name T2024
Test name
Test status
Simulation time 5843481689 ps
CPU time 10.76 seconds
Started Jul 10 06:43:45 PM PDT 24
Finished Jul 10 06:44:00 PM PDT 24
Peak memory 206660 kb
Host smart-87e569a1-a61c-47a9-a81b-75de2eb4f28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12056
43870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1205643870
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3728923418
Short name T480
Test name
Test status
Simulation time 338647951 ps
CPU time 1.13 seconds
Started Jul 10 06:43:48 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206400 kb
Host smart-b849e5dc-6349-4a43-bf57-56a4fae4d753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289
23418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3728923418
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3322539360
Short name T1763
Test name
Test status
Simulation time 158606737 ps
CPU time 0.82 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:53 PM PDT 24
Peak memory 206392 kb
Host smart-c0ea3a2a-d223-4934-a340-a50137a9180e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33225
39360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3322539360
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1549203592
Short name T2207
Test name
Test status
Simulation time 52596331 ps
CPU time 0.67 seconds
Started Jul 10 06:43:49 PM PDT 24
Finished Jul 10 06:43:55 PM PDT 24
Peak memory 206372 kb
Host smart-d6a43420-c961-446c-bc05-65bafa545a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
03592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1549203592
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2506096155
Short name T697
Test name
Test status
Simulation time 975152150 ps
CPU time 2.15 seconds
Started Jul 10 06:43:44 PM PDT 24
Finished Jul 10 06:43:50 PM PDT 24
Peak memory 206568 kb
Host smart-99589487-a556-4a2e-9513-8cdafa705719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25060
96155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2506096155
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3091311690
Short name T184
Test name
Test status
Simulation time 359297047 ps
CPU time 2.08 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206568 kb
Host smart-f21d737b-7959-44ae-8113-409b030071d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30913
11690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3091311690
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.776279442
Short name T1384
Test name
Test status
Simulation time 188735649 ps
CPU time 0.82 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:43:51 PM PDT 24
Peak memory 206384 kb
Host smart-7a42fbcd-6f68-4b05-a53f-c7e3f2e18ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77627
9442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.776279442
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.521183018
Short name T491
Test name
Test status
Simulation time 143530849 ps
CPU time 0.72 seconds
Started Jul 10 06:43:44 PM PDT 24
Finished Jul 10 06:43:49 PM PDT 24
Peak memory 206372 kb
Host smart-cb0baa41-0346-4df9-9934-5f92af7a1553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52118
3018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.521183018
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.4269189287
Short name T817
Test name
Test status
Simulation time 238273259 ps
CPU time 0.98 seconds
Started Jul 10 06:43:43 PM PDT 24
Finished Jul 10 06:43:49 PM PDT 24
Peak memory 206356 kb
Host smart-1adb3f95-8683-4da6-a531-a4f51ecbfa10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42691
89287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.4269189287
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.1615042182
Short name T2359
Test name
Test status
Simulation time 11087359075 ps
CPU time 92.8 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206624 kb
Host smart-ad8014f4-e111-43fc-8046-a040be1ae90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16150
42182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.1615042182
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3556629224
Short name T1969
Test name
Test status
Simulation time 185790778 ps
CPU time 0.84 seconds
Started Jul 10 06:43:44 PM PDT 24
Finished Jul 10 06:43:49 PM PDT 24
Peak memory 206556 kb
Host smart-d427954c-09dd-4ca9-a232-733a0ea5a913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35566
29224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3556629224
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.4242379381
Short name T2635
Test name
Test status
Simulation time 23286334965 ps
CPU time 27.99 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:44:20 PM PDT 24
Peak memory 206456 kb
Host smart-09126ba4-7668-4ba3-9627-12f42c265fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42423
79381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.4242379381
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.637366908
Short name T2735
Test name
Test status
Simulation time 3352052307 ps
CPU time 4.18 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206444 kb
Host smart-37a52316-6319-40cd-a281-8a6b9d81d629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63736
6908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.637366908
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3115346797
Short name T406
Test name
Test status
Simulation time 10525509667 ps
CPU time 293.19 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:48:44 PM PDT 24
Peak memory 206736 kb
Host smart-2455eed3-534a-44e8-bac3-4a65925bb2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31153
46797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3115346797
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2315368571
Short name T2149
Test name
Test status
Simulation time 4262030126 ps
CPU time 119.5 seconds
Started Jul 10 06:43:48 PM PDT 24
Finished Jul 10 06:45:52 PM PDT 24
Peak memory 206624 kb
Host smart-f4462faf-fa2e-4fcf-832f-b72907881025
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2315368571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2315368571
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.812914905
Short name T408
Test name
Test status
Simulation time 243308335 ps
CPU time 0.96 seconds
Started Jul 10 06:43:48 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206388 kb
Host smart-d9743a8f-fb58-456f-8df9-09f6275c6f16
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=812914905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.812914905
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1633063874
Short name T1164
Test name
Test status
Simulation time 235351253 ps
CPU time 0.95 seconds
Started Jul 10 06:43:45 PM PDT 24
Finished Jul 10 06:43:50 PM PDT 24
Peak memory 206364 kb
Host smart-c6b7b623-5876-4058-bf29-57d764bcaba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16330
63874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1633063874
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3079685205
Short name T1816
Test name
Test status
Simulation time 7453377890 ps
CPU time 69.02 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:45:01 PM PDT 24
Peak memory 206680 kb
Host smart-6cfb82ad-5292-44bf-bc15-75e0da230677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30796
85205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3079685205
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2469056508
Short name T1288
Test name
Test status
Simulation time 4435537649 ps
CPU time 126.42 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:45:57 PM PDT 24
Peak memory 206636 kb
Host smart-fc744748-83c9-4650-9914-fa0a62e51965
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2469056508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2469056508
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3990023316
Short name T1260
Test name
Test status
Simulation time 170244812 ps
CPU time 0.82 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:53 PM PDT 24
Peak memory 206360 kb
Host smart-458fc35b-7d75-48e7-9074-eadc852ce9f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3990023316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3990023316
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2484896342
Short name T442
Test name
Test status
Simulation time 146912673 ps
CPU time 0.78 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:53 PM PDT 24
Peak memory 206400 kb
Host smart-c810ca55-08a9-41a2-b865-ddf7630ca96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24848
96342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2484896342
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1344569107
Short name T2196
Test name
Test status
Simulation time 159527139 ps
CPU time 0.77 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:51 PM PDT 24
Peak memory 206388 kb
Host smart-aa911206-3e5c-4ddf-b672-c5662814b8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13445
69107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1344569107
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3163802258
Short name T2471
Test name
Test status
Simulation time 175181230 ps
CPU time 0.88 seconds
Started Jul 10 06:43:51 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206400 kb
Host smart-9cbc4464-9a50-48df-b005-af71dca6e7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31638
02258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3163802258
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.191299547
Short name T2499
Test name
Test status
Simulation time 143472395 ps
CPU time 0.76 seconds
Started Jul 10 06:43:43 PM PDT 24
Finished Jul 10 06:43:49 PM PDT 24
Peak memory 206376 kb
Host smart-b63c5087-327a-4c64-ab78-e8b0f9e61fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19129
9547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.191299547
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.166746192
Short name T1174
Test name
Test status
Simulation time 154309455 ps
CPU time 0.8 seconds
Started Jul 10 06:43:45 PM PDT 24
Finished Jul 10 06:43:50 PM PDT 24
Peak memory 206396 kb
Host smart-d829c875-fa2d-4a3b-a45d-b3ebc89246d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16674
6192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.166746192
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.4286066031
Short name T900
Test name
Test status
Simulation time 235308020 ps
CPU time 1.02 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:53 PM PDT 24
Peak memory 206396 kb
Host smart-9aec169b-1620-4e77-b31d-79b1f5e2bad3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4286066031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.4286066031
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2951180041
Short name T2050
Test name
Test status
Simulation time 132747661 ps
CPU time 0.73 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:43:50 PM PDT 24
Peak memory 206392 kb
Host smart-ccf7dc1e-a7b9-403d-a787-b8c2f7e2df67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511
80041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2951180041
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1819582220
Short name T2247
Test name
Test status
Simulation time 82070437 ps
CPU time 0.72 seconds
Started Jul 10 06:43:48 PM PDT 24
Finished Jul 10 06:43:53 PM PDT 24
Peak memory 206340 kb
Host smart-4d1863ef-2ebe-4643-87cb-9b435e9356bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
82220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1819582220
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3703724808
Short name T1410
Test name
Test status
Simulation time 20025010189 ps
CPU time 45.63 seconds
Started Jul 10 06:43:45 PM PDT 24
Finished Jul 10 06:44:35 PM PDT 24
Peak memory 206664 kb
Host smart-927188da-799f-4dcf-b19e-bdcee195d13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37037
24808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3703724808
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1051153134
Short name T2212
Test name
Test status
Simulation time 190969969 ps
CPU time 0.91 seconds
Started Jul 10 06:43:44 PM PDT 24
Finished Jul 10 06:43:49 PM PDT 24
Peak memory 206280 kb
Host smart-4b00b5e3-ccb6-416a-901a-1ea7ea8e9724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10511
53134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1051153134
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.271667004
Short name T2407
Test name
Test status
Simulation time 211618534 ps
CPU time 0.86 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:52 PM PDT 24
Peak memory 206396 kb
Host smart-c735bdc8-8798-4d52-b5f5-befe5ab39e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27166
7004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.271667004
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2565806689
Short name T1565
Test name
Test status
Simulation time 232168901 ps
CPU time 0.89 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206384 kb
Host smart-0b3c1ff4-d1f0-4b60-bad3-7ba06a3714ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
06689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2565806689
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.1682075617
Short name T916
Test name
Test status
Simulation time 161326617 ps
CPU time 0.81 seconds
Started Jul 10 06:43:44 PM PDT 24
Finished Jul 10 06:43:50 PM PDT 24
Peak memory 206388 kb
Host smart-53fab976-3398-48aa-8dd5-89616438e846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16820
75617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.1682075617
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1617991833
Short name T1800
Test name
Test status
Simulation time 145893242 ps
CPU time 0.76 seconds
Started Jul 10 06:43:45 PM PDT 24
Finished Jul 10 06:43:50 PM PDT 24
Peak memory 206372 kb
Host smart-c65258a1-6834-4738-99bc-e1196b1999db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16179
91833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1617991833
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2716554037
Short name T2157
Test name
Test status
Simulation time 156647647 ps
CPU time 0.84 seconds
Started Jul 10 06:43:44 PM PDT 24
Finished Jul 10 06:43:50 PM PDT 24
Peak memory 206376 kb
Host smart-7800b5fd-b76c-4480-9ca4-5b2d5c2b518c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27165
54037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2716554037
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.406414960
Short name T1314
Test name
Test status
Simulation time 149388109 ps
CPU time 0.79 seconds
Started Jul 10 06:43:51 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206404 kb
Host smart-a5a3d98b-1803-44f3-8ebd-e82914a3c1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40641
4960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.406414960
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2300471106
Short name T2505
Test name
Test status
Simulation time 199324367 ps
CPU time 0.9 seconds
Started Jul 10 06:43:48 PM PDT 24
Finished Jul 10 06:43:53 PM PDT 24
Peak memory 206384 kb
Host smart-c7bc805f-82fc-46ae-96a1-614872dd2263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23004
71106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2300471106
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1174655380
Short name T1173
Test name
Test status
Simulation time 3951859948 ps
CPU time 109.67 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206600 kb
Host smart-77e10ca9-ed01-40e6-9f32-9c8bbe1f49af
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1174655380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1174655380
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.661648630
Short name T2006
Test name
Test status
Simulation time 191751390 ps
CPU time 0.9 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:52 PM PDT 24
Peak memory 206380 kb
Host smart-c7265c1f-8b84-4bb6-9f14-657081454ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66164
8630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.661648630
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2930976024
Short name T1762
Test name
Test status
Simulation time 146796246 ps
CPU time 0.83 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206372 kb
Host smart-2129bed0-b0a0-40cb-ba50-d75ebf41cc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29309
76024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2930976024
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.2462818672
Short name T819
Test name
Test status
Simulation time 677965267 ps
CPU time 1.65 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:54 PM PDT 24
Peak memory 206604 kb
Host smart-5f85a7a0-12f3-497c-a008-c95ed305517f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24628
18672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.2462818672
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1291666740
Short name T1147
Test name
Test status
Simulation time 5840985153 ps
CPU time 154.77 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:46:24 PM PDT 24
Peak memory 206588 kb
Host smart-82852787-4abd-41a5-87ec-ddc469170de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12916
66740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1291666740
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3621810200
Short name T2296
Test name
Test status
Simulation time 34587810 ps
CPU time 0.67 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:07 PM PDT 24
Peak memory 206400 kb
Host smart-d72a9884-d5ac-4d3d-8bd5-e2e009b2cb02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3621810200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3621810200
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2296313303
Short name T1452
Test name
Test status
Simulation time 4015010320 ps
CPU time 4.53 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:43:55 PM PDT 24
Peak memory 206692 kb
Host smart-c9eb540c-52a5-44a4-b1ba-e0ac285ce25a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2296313303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.2296313303
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.757550094
Short name T1069
Test name
Test status
Simulation time 13330985174 ps
CPU time 12.64 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:44:02 PM PDT 24
Peak memory 206408 kb
Host smart-7c092bd0-52a4-4761-9d70-614b0bb9fed3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=757550094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.757550094
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1160157890
Short name T222
Test name
Test status
Simulation time 23515052696 ps
CPU time 26.21 seconds
Started Jul 10 06:43:51 PM PDT 24
Finished Jul 10 06:44:22 PM PDT 24
Peak memory 206712 kb
Host smart-bc9b8839-31e2-4660-8c93-d30b85be6632
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1160157890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1160157890
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3599030472
Short name T553
Test name
Test status
Simulation time 151969006 ps
CPU time 0.78 seconds
Started Jul 10 06:43:50 PM PDT 24
Finished Jul 10 06:43:56 PM PDT 24
Peak memory 206376 kb
Host smart-40f4164f-1dc2-49a9-a93d-f3d8bad6969f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35990
30472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3599030472
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2379317828
Short name T423
Test name
Test status
Simulation time 155042956 ps
CPU time 0.76 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:51 PM PDT 24
Peak memory 206396 kb
Host smart-e82b5683-baa0-4735-9776-122a6c384339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
17828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2379317828
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2722319992
Short name T2230
Test name
Test status
Simulation time 487112157 ps
CPU time 1.48 seconds
Started Jul 10 06:43:47 PM PDT 24
Finished Jul 10 06:43:52 PM PDT 24
Peak memory 206380 kb
Host smart-7e6dcf65-4ee8-4427-bfc4-a80f8449d3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27223
19992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2722319992
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3491394679
Short name T2661
Test name
Test status
Simulation time 571151510 ps
CPU time 1.43 seconds
Started Jul 10 06:43:48 PM PDT 24
Finished Jul 10 06:43:55 PM PDT 24
Peak memory 206388 kb
Host smart-adc3a0b9-dde6-4d7f-aae6-418c0a738c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34913
94679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3491394679
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2745051712
Short name T2603
Test name
Test status
Simulation time 14813525296 ps
CPU time 29.58 seconds
Started Jul 10 06:43:46 PM PDT 24
Finished Jul 10 06:44:19 PM PDT 24
Peak memory 206620 kb
Host smart-bb9cd464-aeb0-4c0d-92ab-feaba4a6c24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
51712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2745051712
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.4180990795
Short name T1768
Test name
Test status
Simulation time 376310228 ps
CPU time 1.18 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:43:58 PM PDT 24
Peak memory 206400 kb
Host smart-3fa356e2-664e-46cc-a34b-4b545472ce4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
90795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.4180990795
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.3491335202
Short name T1712
Test name
Test status
Simulation time 219917286 ps
CPU time 0.82 seconds
Started Jul 10 06:43:54 PM PDT 24
Finished Jul 10 06:43:59 PM PDT 24
Peak memory 206380 kb
Host smart-49d8e0b4-2764-486d-9953-7dfe82ac6a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34913
35202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.3491335202
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.785873013
Short name T518
Test name
Test status
Simulation time 46734856 ps
CPU time 0.65 seconds
Started Jul 10 06:43:54 PM PDT 24
Finished Jul 10 06:43:58 PM PDT 24
Peak memory 206372 kb
Host smart-162d6e51-faae-4db9-9b54-ffd85236891a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78587
3013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.785873013
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.4030392038
Short name T2249
Test name
Test status
Simulation time 800739577 ps
CPU time 1.87 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:43:58 PM PDT 24
Peak memory 206812 kb
Host smart-71468906-7608-4839-bf1d-dd19f2077f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40303
92038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.4030392038
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.431382248
Short name T1183
Test name
Test status
Simulation time 268383331 ps
CPU time 1.62 seconds
Started Jul 10 06:43:50 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206584 kb
Host smart-a1c04ac9-c9cb-4a08-a154-702c7946a2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43138
2248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.431382248
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.21022149
Short name T2045
Test name
Test status
Simulation time 190367611 ps
CPU time 0.9 seconds
Started Jul 10 06:43:51 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206324 kb
Host smart-3f6a2723-abe3-436f-a87f-08a411cb4cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21022
149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.21022149
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3221630610
Short name T1964
Test name
Test status
Simulation time 211628429 ps
CPU time 0.81 seconds
Started Jul 10 06:43:54 PM PDT 24
Finished Jul 10 06:43:59 PM PDT 24
Peak memory 206372 kb
Host smart-456c4d4f-f66a-43cb-8fea-94d505d856e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
30610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3221630610
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3572976239
Short name T550
Test name
Test status
Simulation time 253864332 ps
CPU time 0.96 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206396 kb
Host smart-c41536e6-8565-49af-90ee-097f28c704c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729
76239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3572976239
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3326066739
Short name T660
Test name
Test status
Simulation time 5082165908 ps
CPU time 37.42 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:44:34 PM PDT 24
Peak memory 206712 kb
Host smart-5136a3a4-1d12-4c81-9223-db0515ba07c8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3326066739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3326066739
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.1255446339
Short name T2373
Test name
Test status
Simulation time 13975538161 ps
CPU time 47.22 seconds
Started Jul 10 06:43:50 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 206716 kb
Host smart-c3821321-f238-498d-9bc9-36c6c852e1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12554
46339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.1255446339
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3984902446
Short name T330
Test name
Test status
Simulation time 162635002 ps
CPU time 0.77 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206280 kb
Host smart-a06f69f3-8851-4d11-853c-cd6d3fc6e832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39849
02446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3984902446
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3162567444
Short name T1132
Test name
Test status
Simulation time 23358487593 ps
CPU time 24.13 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:44:20 PM PDT 24
Peak memory 206616 kb
Host smart-1a603bc5-4b22-4e1c-9358-8c8505990117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31625
67444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3162567444
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1272529215
Short name T1701
Test name
Test status
Simulation time 3290959396 ps
CPU time 4.83 seconds
Started Jul 10 06:43:50 PM PDT 24
Finished Jul 10 06:44:00 PM PDT 24
Peak memory 206440 kb
Host smart-56565491-566a-4a88-b94d-b416e6bb9692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12725
29215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1272529215
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3640251448
Short name T1368
Test name
Test status
Simulation time 8411248158 ps
CPU time 79.04 seconds
Started Jul 10 06:43:55 PM PDT 24
Finished Jul 10 06:45:17 PM PDT 24
Peak memory 206776 kb
Host smart-c92cfae2-2975-4de3-8db0-e5a84f22ee8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36402
51448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3640251448
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.568055089
Short name T436
Test name
Test status
Simulation time 3508311798 ps
CPU time 33.13 seconds
Started Jul 10 06:43:54 PM PDT 24
Finished Jul 10 06:44:31 PM PDT 24
Peak memory 206660 kb
Host smart-7ec9987e-165d-4399-9a3d-bf520d0dd568
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=568055089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.568055089
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2728434234
Short name T1585
Test name
Test status
Simulation time 258521060 ps
CPU time 0.95 seconds
Started Jul 10 06:43:54 PM PDT 24
Finished Jul 10 06:43:59 PM PDT 24
Peak memory 206372 kb
Host smart-df2203d7-5572-48ed-9339-0ab30bfe7770
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2728434234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2728434234
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2303372145
Short name T2721
Test name
Test status
Simulation time 220423967 ps
CPU time 0.85 seconds
Started Jul 10 06:43:53 PM PDT 24
Finished Jul 10 06:43:57 PM PDT 24
Peak memory 206372 kb
Host smart-691ba70c-8cb0-4627-b8c6-9f55634a6f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23033
72145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2303372145
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3981748381
Short name T1629
Test name
Test status
Simulation time 6986893324 ps
CPU time 51.13 seconds
Started Jul 10 06:43:51 PM PDT 24
Finished Jul 10 06:44:47 PM PDT 24
Peak memory 206736 kb
Host smart-98de8e57-52d5-46d5-af16-63bf131f2919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
48381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3981748381
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1223490717
Short name T2655
Test name
Test status
Simulation time 3880037419 ps
CPU time 28.63 seconds
Started Jul 10 06:43:52 PM PDT 24
Finished Jul 10 06:44:25 PM PDT 24
Peak memory 206536 kb
Host smart-e2319be7-1305-4c34-be15-64b441b8022c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1223490717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1223490717
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3387202986
Short name T1296
Test name
Test status
Simulation time 159186081 ps
CPU time 0.82 seconds
Started Jul 10 06:43:53 PM PDT 24
Finished Jul 10 06:43:58 PM PDT 24
Peak memory 206360 kb
Host smart-05549037-66f6-4e13-ab21-b51c0d6c77dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3387202986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3387202986
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.458738502
Short name T1063
Test name
Test status
Simulation time 160289594 ps
CPU time 0.8 seconds
Started Jul 10 06:43:56 PM PDT 24
Finished Jul 10 06:44:00 PM PDT 24
Peak memory 206384 kb
Host smart-cdb7c117-0170-423d-8c03-a89a5881a69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45873
8502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.458738502
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3847968980
Short name T135
Test name
Test status
Simulation time 295614077 ps
CPU time 0.96 seconds
Started Jul 10 06:43:54 PM PDT 24
Finished Jul 10 06:43:58 PM PDT 24
Peak memory 206388 kb
Host smart-46122f37-c431-4799-9a2e-b7f6f505851e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38479
68980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3847968980
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.772094469
Short name T440
Test name
Test status
Simulation time 179218005 ps
CPU time 0.8 seconds
Started Jul 10 06:43:50 PM PDT 24
Finished Jul 10 06:43:56 PM PDT 24
Peak memory 206280 kb
Host smart-fcdc4df0-169f-429c-bb67-d38e766772e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77209
4469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.772094469
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2843933785
Short name T613
Test name
Test status
Simulation time 182000037 ps
CPU time 0.84 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206404 kb
Host smart-a285e026-ccb5-4a5c-9c52-18e6e3499740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28439
33785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2843933785
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1963622047
Short name T270
Test name
Test status
Simulation time 161079780 ps
CPU time 0.8 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:08 PM PDT 24
Peak memory 206364 kb
Host smart-3d4e40c2-71e8-4e25-99e9-460cb778cae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19636
22047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1963622047
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.82564183
Short name T388
Test name
Test status
Simulation time 162631744 ps
CPU time 0.76 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:09 PM PDT 24
Peak memory 206336 kb
Host smart-e160503d-d4b8-4e8a-b6c0-41962f3efb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82564
183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.82564183
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2916722656
Short name T1414
Test name
Test status
Simulation time 224492014 ps
CPU time 0.91 seconds
Started Jul 10 06:44:05 PM PDT 24
Finished Jul 10 06:44:09 PM PDT 24
Peak memory 206324 kb
Host smart-2bcb0aa7-4ecb-4195-8833-85e57b3cf9f9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2916722656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2916722656
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2108534806
Short name T1275
Test name
Test status
Simulation time 165393543 ps
CPU time 0.8 seconds
Started Jul 10 06:44:05 PM PDT 24
Finished Jul 10 06:44:09 PM PDT 24
Peak memory 206368 kb
Host smart-2281a749-5515-4ad4-b973-aa9d11d54b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21085
34806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2108534806
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1938249449
Short name T785
Test name
Test status
Simulation time 56123822 ps
CPU time 0.71 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 206388 kb
Host smart-2600d201-be8b-4b31-910c-f3c04f4290be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19382
49449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1938249449
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.531252009
Short name T1746
Test name
Test status
Simulation time 18640211284 ps
CPU time 39.1 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:47 PM PDT 24
Peak memory 206724 kb
Host smart-8badf45d-b0a7-4ff9-aff1-319ea440e5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53125
2009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.531252009
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1873892012
Short name T2404
Test name
Test status
Simulation time 189254666 ps
CPU time 0.92 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:07 PM PDT 24
Peak memory 206380 kb
Host smart-d43c46bc-d577-49d3-826a-d2cf153b8362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18738
92012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1873892012
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2225757329
Short name T377
Test name
Test status
Simulation time 228423879 ps
CPU time 0.89 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:07 PM PDT 24
Peak memory 206376 kb
Host smart-b2a7f7ab-a51f-447b-892d-5235fc7b8dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22257
57329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2225757329
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3470198933
Short name T2581
Test name
Test status
Simulation time 187282136 ps
CPU time 0.91 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:08 PM PDT 24
Peak memory 206396 kb
Host smart-b1bc0f11-805b-441d-9da4-7445b49674e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34701
98933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3470198933
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.4159527434
Short name T1666
Test name
Test status
Simulation time 148764028 ps
CPU time 0.88 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:07 PM PDT 24
Peak memory 206388 kb
Host smart-2d643410-a1c3-4e2a-8017-10ffe31a544a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41595
27434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.4159527434
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2137173589
Short name T1934
Test name
Test status
Simulation time 145810655 ps
CPU time 0.75 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206380 kb
Host smart-0a62e1f6-b194-4c5e-b1ec-22722fcead56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21371
73589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2137173589
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1162665375
Short name T1337
Test name
Test status
Simulation time 162973515 ps
CPU time 0.76 seconds
Started Jul 10 06:44:06 PM PDT 24
Finished Jul 10 06:44:12 PM PDT 24
Peak memory 206364 kb
Host smart-b0ae9245-d44d-403a-9d1d-f6d2cf5434fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11626
65375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1162665375
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2219258901
Short name T1086
Test name
Test status
Simulation time 161854424 ps
CPU time 0.79 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:09 PM PDT 24
Peak memory 206404 kb
Host smart-a5ab3829-22a4-400d-9c1b-b3a0548b0768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22192
58901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2219258901
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2335327079
Short name T2084
Test name
Test status
Simulation time 237577086 ps
CPU time 0.95 seconds
Started Jul 10 06:44:06 PM PDT 24
Finished Jul 10 06:44:11 PM PDT 24
Peak memory 206364 kb
Host smart-efcf5904-abab-4f7f-a072-f7eada259908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23353
27079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2335327079
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2055842516
Short name T561
Test name
Test status
Simulation time 7171728161 ps
CPU time 53.34 seconds
Started Jul 10 06:44:05 PM PDT 24
Finished Jul 10 06:45:02 PM PDT 24
Peak memory 206492 kb
Host smart-ea362921-8f8b-430c-832b-45a5e9a118b7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2055842516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2055842516
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3230908222
Short name T2403
Test name
Test status
Simulation time 180727526 ps
CPU time 0.81 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:08 PM PDT 24
Peak memory 206380 kb
Host smart-7275f0ef-7f02-4f9d-823b-e495174bf644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32309
08222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3230908222
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1310244695
Short name T773
Test name
Test status
Simulation time 179125326 ps
CPU time 0.82 seconds
Started Jul 10 06:44:10 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206376 kb
Host smart-2976a9e0-640b-4164-84eb-443475d901b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13102
44695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1310244695
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3114452723
Short name T1839
Test name
Test status
Simulation time 387248887 ps
CPU time 1.19 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 206396 kb
Host smart-baa1511b-c132-4bf1-9fe5-4f6c9864e472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31144
52723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3114452723
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1246398087
Short name T2447
Test name
Test status
Simulation time 4854417405 ps
CPU time 45.27 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:53 PM PDT 24
Peak memory 206680 kb
Host smart-51461841-da7e-4065-8ec1-c4ad8e67af54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463
98087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1246398087
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.2946167891
Short name T2666
Test name
Test status
Simulation time 38264994 ps
CPU time 0.63 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 206448 kb
Host smart-d2926290-10a2-4f27-94a3-14d187984073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2946167891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.2946167891
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.52162639
Short name T2189
Test name
Test status
Simulation time 4280338670 ps
CPU time 5.38 seconds
Started Jul 10 06:44:05 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 206420 kb
Host smart-24bb059b-dc0f-4baf-a7d2-8fccb16f8e57
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=52162639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.52162639
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.183347719
Short name T15
Test name
Test status
Simulation time 13382607538 ps
CPU time 12.75 seconds
Started Jul 10 06:44:06 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206604 kb
Host smart-55f5c8b0-14c4-47c6-9996-d456caac580b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=183347719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.183347719
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3427213643
Short name T1447
Test name
Test status
Simulation time 23383871070 ps
CPU time 22.34 seconds
Started Jul 10 06:44:05 PM PDT 24
Finished Jul 10 06:44:31 PM PDT 24
Peak memory 206576 kb
Host smart-1cc8d414-71ba-4edb-b56d-5a269f9e30da
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3427213643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3427213643
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.4278441060
Short name T647
Test name
Test status
Simulation time 158263800 ps
CPU time 0.79 seconds
Started Jul 10 06:44:06 PM PDT 24
Finished Jul 10 06:44:11 PM PDT 24
Peak memory 206392 kb
Host smart-77909c77-5cbe-4e7c-ac3a-dbdf4aa4920a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42784
41060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.4278441060
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1558539241
Short name T2485
Test name
Test status
Simulation time 147154949 ps
CPU time 0.78 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:12 PM PDT 24
Peak memory 206324 kb
Host smart-8fd1756a-114f-4a28-8343-2cedef3a296a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
39241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1558539241
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1732205941
Short name T1587
Test name
Test status
Simulation time 221324905 ps
CPU time 0.88 seconds
Started Jul 10 06:44:05 PM PDT 24
Finished Jul 10 06:44:10 PM PDT 24
Peak memory 206400 kb
Host smart-fe9b2898-f8e3-4583-be5c-63bb405d5470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17322
05941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1732205941
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1777148630
Short name T2540
Test name
Test status
Simulation time 1162478094 ps
CPU time 2.92 seconds
Started Jul 10 06:44:10 PM PDT 24
Finished Jul 10 06:44:17 PM PDT 24
Peak memory 206632 kb
Host smart-47433d4f-c395-49a4-859e-3d5e540de541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17771
48630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1777148630
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.582293107
Short name T2073
Test name
Test status
Simulation time 15824883722 ps
CPU time 30.16 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206652 kb
Host smart-f252cb7a-929f-4f68-8ca8-a8e1a0d323f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58229
3107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.582293107
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3744283030
Short name T331
Test name
Test status
Simulation time 380996634 ps
CPU time 1.17 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:06 PM PDT 24
Peak memory 206396 kb
Host smart-2472aadd-25d4-49b5-903e-df0b7d60ecb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37442
83030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3744283030
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3942767609
Short name T1170
Test name
Test status
Simulation time 153927384 ps
CPU time 0.82 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:08 PM PDT 24
Peak memory 206376 kb
Host smart-d300b0a6-437c-4dec-a38f-4ed477e9aa63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39427
67609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3942767609
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2744691642
Short name T619
Test name
Test status
Simulation time 37911502 ps
CPU time 0.68 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206376 kb
Host smart-ccc9bda5-7cfe-4be0-98a2-d67adbcc2fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27446
91642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2744691642
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.4227163365
Short name T1653
Test name
Test status
Simulation time 933371819 ps
CPU time 2.29 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206680 kb
Host smart-bc7e2f8b-5034-4110-974e-1b69b3224689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271
63365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.4227163365
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3288543085
Short name T1656
Test name
Test status
Simulation time 302234046 ps
CPU time 2.18 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 206496 kb
Host smart-951947ef-c7b3-416e-88ef-be6ca7af2f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32885
43085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3288543085
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.921982448
Short name T503
Test name
Test status
Simulation time 243575481 ps
CPU time 0.88 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:07 PM PDT 24
Peak memory 206392 kb
Host smart-0e718552-00fb-40f0-a9fa-afcfc4fc6602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92198
2448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.921982448
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3362151120
Short name T640
Test name
Test status
Simulation time 139492655 ps
CPU time 0.79 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:06 PM PDT 24
Peak memory 206388 kb
Host smart-763edde0-2bcb-45d4-94b7-67c16b49df5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33621
51120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3362151120
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2573952867
Short name T1834
Test name
Test status
Simulation time 265519953 ps
CPU time 1 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:08 PM PDT 24
Peak memory 206328 kb
Host smart-a0b94a32-54d0-4eae-a821-86fe106a3200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25739
52867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2573952867
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.522829449
Short name T2018
Test name
Test status
Simulation time 10404732221 ps
CPU time 291.92 seconds
Started Jul 10 06:44:01 PM PDT 24
Finished Jul 10 06:48:54 PM PDT 24
Peak memory 206612 kb
Host smart-cdfa1f59-1908-4b7d-a008-d27f080e48e9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=522829449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.522829449
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2896773220
Short name T1582
Test name
Test status
Simulation time 174216775 ps
CPU time 0.8 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206352 kb
Host smart-b78c1252-79aa-4489-951a-540c1860a03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28967
73220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2896773220
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.4126240604
Short name T1922
Test name
Test status
Simulation time 23299885662 ps
CPU time 20.98 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206384 kb
Host smart-14a812ac-b671-42dd-a79e-97bfec069684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41262
40604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.4126240604
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.118422229
Short name T2595
Test name
Test status
Simulation time 3325033049 ps
CPU time 3.72 seconds
Started Jul 10 06:44:06 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 206444 kb
Host smart-5beea2e8-ca6e-4669-86f1-b35e46d319ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11842
2229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.118422229
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1105774142
Short name T2430
Test name
Test status
Simulation time 9633093575 ps
CPU time 264.15 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:48:38 PM PDT 24
Peak memory 206704 kb
Host smart-0fbbada7-505d-4a3b-b7b7-1838687f60df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11057
74142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1105774142
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.1894804438
Short name T379
Test name
Test status
Simulation time 4689758186 ps
CPU time 32.63 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:44:40 PM PDT 24
Peak memory 206620 kb
Host smart-94889f25-e803-40e6-a62e-13d4f769501f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1894804438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.1894804438
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1562015639
Short name T711
Test name
Test status
Simulation time 241442984 ps
CPU time 0.9 seconds
Started Jul 10 06:44:05 PM PDT 24
Finished Jul 10 06:44:10 PM PDT 24
Peak memory 206376 kb
Host smart-5567a454-63e6-48dc-80da-9730dc41bb47
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1562015639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1562015639
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1631758727
Short name T1952
Test name
Test status
Simulation time 188168110 ps
CPU time 0.9 seconds
Started Jul 10 06:44:05 PM PDT 24
Finished Jul 10 06:44:10 PM PDT 24
Peak memory 206376 kb
Host smart-a86e37e7-fe6a-4a79-be09-a66bf8043edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
58727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1631758727
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.496589968
Short name T981
Test name
Test status
Simulation time 5946449937 ps
CPU time 163.41 seconds
Started Jul 10 06:44:04 PM PDT 24
Finished Jul 10 06:46:52 PM PDT 24
Peak memory 206692 kb
Host smart-e3b897d8-e9a5-49bb-b0e1-e18ad1afb243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49658
9968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.496589968
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1633687983
Short name T2411
Test name
Test status
Simulation time 4897477018 ps
CPU time 130.16 seconds
Started Jul 10 06:44:02 PM PDT 24
Finished Jul 10 06:46:13 PM PDT 24
Peak memory 206656 kb
Host smart-c32dee9e-164c-4096-b9b5-36d04d27ac11
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1633687983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1633687983
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.4063661297
Short name T930
Test name
Test status
Simulation time 145863400 ps
CPU time 0.8 seconds
Started Jul 10 06:44:03 PM PDT 24
Finished Jul 10 06:44:07 PM PDT 24
Peak memory 206380 kb
Host smart-439d9626-def7-4f20-b049-0f20c94ca05f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4063661297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.4063661297
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1919178732
Short name T2142
Test name
Test status
Simulation time 141155710 ps
CPU time 0.82 seconds
Started Jul 10 06:44:10 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206380 kb
Host smart-7e98391f-504c-43e8-b7c5-79fa8d341f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19191
78732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1919178732
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.890583993
Short name T140
Test name
Test status
Simulation time 217412617 ps
CPU time 0.87 seconds
Started Jul 10 06:44:21 PM PDT 24
Finished Jul 10 06:44:24 PM PDT 24
Peak memory 206168 kb
Host smart-4a9283a9-86cd-44ef-b786-2d6e02ff2bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89058
3993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.890583993
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2385922974
Short name T515
Test name
Test status
Simulation time 157380025 ps
CPU time 0.76 seconds
Started Jul 10 06:44:20 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206372 kb
Host smart-840608b7-762c-419f-a3c3-db4bff730a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23859
22974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2385922974
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3821745738
Short name T2548
Test name
Test status
Simulation time 191096066 ps
CPU time 0.89 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206396 kb
Host smart-b367902e-5252-40a3-9ee8-55a83015142d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38217
45738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3821745738
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3305092058
Short name T1045
Test name
Test status
Simulation time 155201037 ps
CPU time 0.78 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206392 kb
Host smart-b5fdbff9-6f07-46a2-ad65-03e06a0b1daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33050
92058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3305092058
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3949440479
Short name T998
Test name
Test status
Simulation time 147377526 ps
CPU time 0.83 seconds
Started Jul 10 06:44:11 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206384 kb
Host smart-49b3f561-755f-474c-ba81-0e8895581799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39494
40479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3949440479
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1166742534
Short name T734
Test name
Test status
Simulation time 193861814 ps
CPU time 0.88 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206396 kb
Host smart-07be6746-3828-4d50-9041-9681058226f0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1166742534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1166742534
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.4287376524
Short name T1535
Test name
Test status
Simulation time 139610002 ps
CPU time 0.78 seconds
Started Jul 10 06:44:21 PM PDT 24
Finished Jul 10 06:44:24 PM PDT 24
Peak memory 206280 kb
Host smart-1a662346-d938-4b66-b689-a61dbd7fff0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42873
76524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.4287376524
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2348172228
Short name T23
Test name
Test status
Simulation time 58594315 ps
CPU time 0.69 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206548 kb
Host smart-b8a9c733-d7f3-48a9-b092-832606083e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
72228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2348172228
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4167817753
Short name T93
Test name
Test status
Simulation time 14694090734 ps
CPU time 32.81 seconds
Started Jul 10 06:44:10 PM PDT 24
Finished Jul 10 06:44:47 PM PDT 24
Peak memory 214844 kb
Host smart-2d46a9b4-150c-4e1d-94cb-90d0c9b87c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41678
17753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4167817753
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2875855089
Short name T1689
Test name
Test status
Simulation time 202679342 ps
CPU time 0.88 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206380 kb
Host smart-1d3ea5f7-c5b9-440c-b38f-dd8941b10a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28758
55089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2875855089
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.465330056
Short name T361
Test name
Test status
Simulation time 221875499 ps
CPU time 0.86 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206332 kb
Host smart-b9421a02-3d8b-49f6-b752-cc898b46a198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46533
0056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.465330056
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2048075593
Short name T2364
Test name
Test status
Simulation time 163487530 ps
CPU time 0.8 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206376 kb
Host smart-d153c72e-12d8-4e6e-9fda-85fe82989f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20480
75593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2048075593
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3898984192
Short name T729
Test name
Test status
Simulation time 154881352 ps
CPU time 0.89 seconds
Started Jul 10 06:44:11 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206384 kb
Host smart-d6fcce31-5427-4fd8-ac76-056001da4cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38989
84192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3898984192
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3295011207
Short name T653
Test name
Test status
Simulation time 151969048 ps
CPU time 0.8 seconds
Started Jul 10 06:44:10 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206392 kb
Host smart-31eb49c1-74cc-4538-91dd-5902e2e86913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32950
11207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3295011207
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.632338572
Short name T1459
Test name
Test status
Simulation time 173772054 ps
CPU time 0.82 seconds
Started Jul 10 06:44:10 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206400 kb
Host smart-a313573c-38c6-44f7-9bb6-4ae90e9684cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63233
8572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.632338572
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2807985947
Short name T1397
Test name
Test status
Simulation time 153482462 ps
CPU time 0.77 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 206400 kb
Host smart-385fdce1-cc34-4555-86bc-dd24d5021267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28079
85947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2807985947
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1548809147
Short name T498
Test name
Test status
Simulation time 261161864 ps
CPU time 0.97 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206360 kb
Host smart-73be8673-f467-4906-9350-be86179f17da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15488
09147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1548809147
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1592732280
Short name T2625
Test name
Test status
Simulation time 5233410117 ps
CPU time 47.67 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:45:01 PM PDT 24
Peak memory 206604 kb
Host smart-85700931-a2ab-4c55-9fbe-3da410b3cfe2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1592732280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1592732280
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3792340966
Short name T2634
Test name
Test status
Simulation time 183300289 ps
CPU time 0.81 seconds
Started Jul 10 06:44:13 PM PDT 24
Finished Jul 10 06:44:17 PM PDT 24
Peak memory 206380 kb
Host smart-c9bb79e2-a364-4d19-9ab4-c1381efaebd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37923
40966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3792340966
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2581984449
Short name T402
Test name
Test status
Simulation time 187759480 ps
CPU time 0.81 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206372 kb
Host smart-817d5803-7956-48b8-9358-86fc298a64ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25819
84449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2581984449
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.2433101273
Short name T642
Test name
Test status
Simulation time 221594807 ps
CPU time 0.86 seconds
Started Jul 10 06:44:10 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206368 kb
Host smart-500e854f-1ae1-49be-8615-6444aabdcc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24331
01273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2433101273
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3658333444
Short name T2578
Test name
Test status
Simulation time 4765969986 ps
CPU time 130.17 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:46:24 PM PDT 24
Peak memory 206652 kb
Host smart-a237dcf1-0a1d-468d-a86e-65dd4d5d0244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36583
33444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3658333444
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3255929728
Short name T186
Test name
Test status
Simulation time 58612213 ps
CPU time 0.7 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:29 PM PDT 24
Peak memory 206420 kb
Host smart-f568f1be-52ff-4581-b2e8-6a0cdd551aa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3255929728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3255929728
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.90821923
Short name T1226
Test name
Test status
Simulation time 3362021094 ps
CPU time 3.95 seconds
Started Jul 10 06:44:07 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206604 kb
Host smart-db892f41-c05e-46f0-8103-75cefed49a10
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=90821923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.90821923
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3534356705
Short name T449
Test name
Test status
Simulation time 13358087552 ps
CPU time 12.52 seconds
Started Jul 10 06:44:11 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206720 kb
Host smart-c80eae06-9624-4e05-9076-1ecc292fdabd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3534356705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3534356705
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.719374083
Short name T500
Test name
Test status
Simulation time 23345731773 ps
CPU time 25.38 seconds
Started Jul 10 06:44:10 PM PDT 24
Finished Jul 10 06:44:40 PM PDT 24
Peak memory 206424 kb
Host smart-71f48f23-6ebe-4e2e-b9e1-fc6de0e0aef5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=719374083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.719374083
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3799132271
Short name T1498
Test name
Test status
Simulation time 152110558 ps
CPU time 0.8 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:44:13 PM PDT 24
Peak memory 206364 kb
Host smart-66076850-17a2-4814-ab72-79def2a94eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37991
32271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3799132271
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1115505641
Short name T214
Test name
Test status
Simulation time 181958691 ps
CPU time 0.81 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 206380 kb
Host smart-db7d724f-2b52-4292-bd7c-d5c3c06ce03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11155
05641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1115505641
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3579416488
Short name T1882
Test name
Test status
Simulation time 470562403 ps
CPU time 1.41 seconds
Started Jul 10 06:44:08 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206380 kb
Host smart-d7b1b95a-1578-4833-9855-4804c0d38cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35794
16488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3579416488
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3378177362
Short name T892
Test name
Test status
Simulation time 350007841 ps
CPU time 1.37 seconds
Started Jul 10 06:44:11 PM PDT 24
Finished Jul 10 06:44:17 PM PDT 24
Peak memory 206380 kb
Host smart-1b4b578f-f88e-4078-9bea-5899e8bb98e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33781
77362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3378177362
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3811882943
Short name T1350
Test name
Test status
Simulation time 23727063869 ps
CPU time 51.67 seconds
Started Jul 10 06:44:13 PM PDT 24
Finished Jul 10 06:45:09 PM PDT 24
Peak memory 206640 kb
Host smart-6d3bbb10-04dc-4312-9216-6bcb33f38cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38118
82943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3811882943
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1838463817
Short name T2237
Test name
Test status
Simulation time 411917535 ps
CPU time 1.4 seconds
Started Jul 10 06:44:20 PM PDT 24
Finished Jul 10 06:44:25 PM PDT 24
Peak memory 206392 kb
Host smart-c28f3166-ac45-4a9f-9fc8-2c09aca7071c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18384
63817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1838463817
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.617159592
Short name T1970
Test name
Test status
Simulation time 183232584 ps
CPU time 0.78 seconds
Started Jul 10 06:44:11 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206392 kb
Host smart-3824408c-10ba-4dd3-97f1-29b732b297da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61715
9592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.617159592
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1126103517
Short name T1735
Test name
Test status
Simulation time 39839022 ps
CPU time 0.68 seconds
Started Jul 10 06:44:11 PM PDT 24
Finished Jul 10 06:44:16 PM PDT 24
Peak memory 206368 kb
Host smart-a3917e25-ff57-4bc8-aa08-3de48297e498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11261
03517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1126103517
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3653346777
Short name T962
Test name
Test status
Simulation time 774461136 ps
CPU time 1.95 seconds
Started Jul 10 06:44:11 PM PDT 24
Finished Jul 10 06:44:18 PM PDT 24
Peak memory 206636 kb
Host smart-00c26f72-3441-463a-bcc6-d453c522b086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36533
46777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3653346777
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.597415040
Short name T546
Test name
Test status
Simulation time 170725220 ps
CPU time 1.59 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:24 PM PDT 24
Peak memory 206588 kb
Host smart-2ef933ff-76ec-4a38-ab1b-18ba43d0755a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59741
5040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.597415040
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.4091243102
Short name T1849
Test name
Test status
Simulation time 197295186 ps
CPU time 0.91 seconds
Started Jul 10 06:44:12 PM PDT 24
Finished Jul 10 06:44:17 PM PDT 24
Peak memory 206312 kb
Host smart-e3b27264-84a3-4e12-8322-aeb8805b1a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912
43102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.4091243102
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.311391722
Short name T2488
Test name
Test status
Simulation time 144509520 ps
CPU time 0.78 seconds
Started Jul 10 06:44:09 PM PDT 24
Finished Jul 10 06:44:15 PM PDT 24
Peak memory 206376 kb
Host smart-7cb19945-3556-496d-8149-dc1d47018e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31139
1722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.311391722
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.808962698
Short name T2645
Test name
Test status
Simulation time 190955371 ps
CPU time 0.86 seconds
Started Jul 10 06:44:16 PM PDT 24
Finished Jul 10 06:44:20 PM PDT 24
Peak memory 206388 kb
Host smart-7fc1e4a5-80dc-43cc-9fe6-bafb1bf42976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80896
2698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.808962698
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1105538721
Short name T702
Test name
Test status
Simulation time 6839858030 ps
CPU time 52.42 seconds
Started Jul 10 06:44:14 PM PDT 24
Finished Jul 10 06:45:10 PM PDT 24
Peak memory 206704 kb
Host smart-a709ed78-87dc-40f9-94e2-f20f041a105a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11055
38721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1105538721
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.106036696
Short name T2515
Test name
Test status
Simulation time 179012257 ps
CPU time 0.81 seconds
Started Jul 10 06:44:15 PM PDT 24
Finished Jul 10 06:44:19 PM PDT 24
Peak memory 206316 kb
Host smart-3ab5cab4-3255-4d33-843a-554463d85228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10603
6696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.106036696
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2778271417
Short name T1002
Test name
Test status
Simulation time 23336606534 ps
CPU time 22.29 seconds
Started Jul 10 06:44:21 PM PDT 24
Finished Jul 10 06:44:46 PM PDT 24
Peak memory 206188 kb
Host smart-d0507c9b-b59a-48f5-837c-bc7ac4c4a990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27782
71417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2778271417
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3372826345
Short name T353
Test name
Test status
Simulation time 3309938864 ps
CPU time 3.59 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:26 PM PDT 24
Peak memory 206444 kb
Host smart-cfac3fe2-9400-416a-a1f7-793d860f17ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33728
26345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3372826345
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.409587499
Short name T2286
Test name
Test status
Simulation time 9544574905 ps
CPU time 92.54 seconds
Started Jul 10 06:44:16 PM PDT 24
Finished Jul 10 06:45:52 PM PDT 24
Peak memory 206708 kb
Host smart-12258e0e-8894-42ea-93fd-4ecdde655670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40958
7499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.409587499
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2779067631
Short name T2252
Test name
Test status
Simulation time 5610999614 ps
CPU time 156.6 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:47:03 PM PDT 24
Peak memory 206600 kb
Host smart-4fe1d477-64c3-40c9-ac7c-f06219bef0c4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2779067631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2779067631
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.4142119982
Short name T2226
Test name
Test status
Simulation time 231078571 ps
CPU time 0.93 seconds
Started Jul 10 06:44:16 PM PDT 24
Finished Jul 10 06:44:20 PM PDT 24
Peak memory 206372 kb
Host smart-6e24dd87-fb92-4688-99e7-5ad6f7b95c5f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4142119982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.4142119982
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1341002750
Short name T2209
Test name
Test status
Simulation time 210619735 ps
CPU time 0.87 seconds
Started Jul 10 06:44:17 PM PDT 24
Finished Jul 10 06:44:21 PM PDT 24
Peak memory 206404 kb
Host smart-22656831-b1e0-4c0d-8d59-564e794eef1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13410
02750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1341002750
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.931015529
Short name T1690
Test name
Test status
Simulation time 6296277421 ps
CPU time 47 seconds
Started Jul 10 06:44:15 PM PDT 24
Finished Jul 10 06:45:05 PM PDT 24
Peak memory 206636 kb
Host smart-8b371ee8-5cb6-44ad-9b10-32fd54869b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93101
5529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.931015529
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3047571013
Short name T91
Test name
Test status
Simulation time 3904879488 ps
CPU time 38.1 seconds
Started Jul 10 06:44:17 PM PDT 24
Finished Jul 10 06:44:58 PM PDT 24
Peak memory 206700 kb
Host smart-53b7ad92-5dfd-4fec-977c-b89364eb28f5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3047571013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3047571013
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1482975137
Short name T2146
Test name
Test status
Simulation time 155858424 ps
CPU time 0.81 seconds
Started Jul 10 06:44:16 PM PDT 24
Finished Jul 10 06:44:19 PM PDT 24
Peak memory 206396 kb
Host smart-7a159d75-237d-45b9-b01b-daee5e7858e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1482975137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1482975137
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.692921470
Short name T2606
Test name
Test status
Simulation time 167634533 ps
CPU time 0.83 seconds
Started Jul 10 06:44:15 PM PDT 24
Finished Jul 10 06:44:19 PM PDT 24
Peak memory 206384 kb
Host smart-591c919b-5d19-41b3-ab49-ccdc29532235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69292
1470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.692921470
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.4250309727
Short name T2217
Test name
Test status
Simulation time 159418597 ps
CPU time 0.78 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:22 PM PDT 24
Peak memory 206372 kb
Host smart-a55fae4e-099f-4d7a-8803-faaadc885630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42503
09727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.4250309727
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3778772029
Short name T1088
Test name
Test status
Simulation time 177570894 ps
CPU time 0.83 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206392 kb
Host smart-cfca0aa0-49b3-4c33-aca8-0354e85a3b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37787
72029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3778772029
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3408472878
Short name T3
Test name
Test status
Simulation time 185764972 ps
CPU time 0.83 seconds
Started Jul 10 06:44:23 PM PDT 24
Finished Jul 10 06:44:26 PM PDT 24
Peak memory 206356 kb
Host smart-a5322f89-a86c-4f12-a7eb-79fffa2000e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
72878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3408472878
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.596653224
Short name T846
Test name
Test status
Simulation time 155658129 ps
CPU time 0.82 seconds
Started Jul 10 06:44:15 PM PDT 24
Finished Jul 10 06:44:19 PM PDT 24
Peak memory 206384 kb
Host smart-31be4982-0a27-4ebb-80ad-7898ea07adf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59665
3224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.596653224
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.612772205
Short name T1250
Test name
Test status
Simulation time 236789985 ps
CPU time 0.93 seconds
Started Jul 10 06:44:18 PM PDT 24
Finished Jul 10 06:44:22 PM PDT 24
Peak memory 206384 kb
Host smart-ba4fb4bc-cbf1-4d2d-ab66-3301a6ea438a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=612772205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.612772205
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1077375074
Short name T1311
Test name
Test status
Simulation time 179878221 ps
CPU time 0.82 seconds
Started Jul 10 06:44:17 PM PDT 24
Finished Jul 10 06:44:21 PM PDT 24
Peak memory 206380 kb
Host smart-3c234a5b-6fc7-4880-b5ca-e75bd542c202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10773
75074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1077375074
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.945772382
Short name T727
Test name
Test status
Simulation time 59620686 ps
CPU time 0.65 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:29 PM PDT 24
Peak memory 206384 kb
Host smart-19f8f4b3-8b7f-4095-8534-7c4ad2957031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94577
2382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.945772382
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2667756236
Short name T247
Test name
Test status
Simulation time 6895437970 ps
CPU time 16.74 seconds
Started Jul 10 06:44:16 PM PDT 24
Finished Jul 10 06:44:35 PM PDT 24
Peak memory 206648 kb
Host smart-737b8ceb-49ab-47d2-8348-59a0684c9055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26677
56236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2667756236
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3664875251
Short name T933
Test name
Test status
Simulation time 189870921 ps
CPU time 0.82 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:29 PM PDT 24
Peak memory 206364 kb
Host smart-fd1b1e02-9a5d-4e33-a488-8421683c3a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36648
75251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3664875251
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2876556394
Short name T603
Test name
Test status
Simulation time 228764357 ps
CPU time 0.85 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:29 PM PDT 24
Peak memory 206376 kb
Host smart-b266d54f-83ce-4811-b28d-83ae7dd59ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28765
56394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2876556394
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.477604093
Short name T495
Test name
Test status
Simulation time 226328742 ps
CPU time 0.91 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:31 PM PDT 24
Peak memory 206356 kb
Host smart-2d3a6c90-feab-4072-8815-21b0222cbd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47760
4093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.477604093
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1086172889
Short name T1975
Test name
Test status
Simulation time 194624086 ps
CPU time 0.82 seconds
Started Jul 10 06:44:16 PM PDT 24
Finished Jul 10 06:44:19 PM PDT 24
Peak memory 206364 kb
Host smart-2fa92a95-1a53-4a61-bc73-29eef5c8d806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
72889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1086172889
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.4232995167
Short name T1654
Test name
Test status
Simulation time 150863596 ps
CPU time 0.75 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:29 PM PDT 24
Peak memory 206368 kb
Host smart-35b38b9b-0b4c-4d8f-bf80-3e6019ef08fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42329
95167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.4232995167
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.397748882
Short name T1485
Test name
Test status
Simulation time 176190810 ps
CPU time 0.81 seconds
Started Jul 10 06:44:16 PM PDT 24
Finished Jul 10 06:44:20 PM PDT 24
Peak memory 206392 kb
Host smart-f4e5c89c-75e0-46d8-9773-4cb7343c485d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39774
8882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.397748882
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1423643505
Short name T2527
Test name
Test status
Simulation time 168657577 ps
CPU time 0.79 seconds
Started Jul 10 06:44:18 PM PDT 24
Finished Jul 10 06:44:22 PM PDT 24
Peak memory 206380 kb
Host smart-557d8f88-e354-4c91-bf2a-599fcfb3ce4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14236
43505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1423643505
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1382642297
Short name T1158
Test name
Test status
Simulation time 208663935 ps
CPU time 1 seconds
Started Jul 10 06:44:18 PM PDT 24
Finished Jul 10 06:44:22 PM PDT 24
Peak memory 206268 kb
Host smart-486e7ac0-5cff-4209-8678-3c59874e1222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13826
42297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1382642297
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.25531779
Short name T2477
Test name
Test status
Simulation time 6567476249 ps
CPU time 179.44 seconds
Started Jul 10 06:44:26 PM PDT 24
Finished Jul 10 06:47:30 PM PDT 24
Peak memory 206660 kb
Host smart-b9bc1f6a-aed7-43f4-8b03-5eb98ba57e3d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=25531779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.25531779
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2467219725
Short name T2015
Test name
Test status
Simulation time 183760845 ps
CPU time 0.79 seconds
Started Jul 10 06:44:17 PM PDT 24
Finished Jul 10 06:44:21 PM PDT 24
Peak memory 206384 kb
Host smart-206fe1c7-3357-4735-9a4c-fb8984d4a821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24672
19725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2467219725
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3700517135
Short name T1994
Test name
Test status
Simulation time 159445475 ps
CPU time 0.79 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206308 kb
Host smart-6ca14581-b83b-4403-a0ff-5445b5be1832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37005
17135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3700517135
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2051571743
Short name T1985
Test name
Test status
Simulation time 1133482117 ps
CPU time 2.59 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:30 PM PDT 24
Peak memory 206596 kb
Host smart-b57b1500-0c2a-4cba-a5a1-b4655d3ed6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20515
71743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2051571743
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.4274405049
Short name T2401
Test name
Test status
Simulation time 5997842984 ps
CPU time 57.95 seconds
Started Jul 10 06:44:17 PM PDT 24
Finished Jul 10 06:45:18 PM PDT 24
Peak memory 206688 kb
Host smart-71c93187-affb-4ca2-9332-70e6b701bbe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42744
05049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.4274405049
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3047446283
Short name T637
Test name
Test status
Simulation time 84221056 ps
CPU time 0.71 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:39:38 PM PDT 24
Peak memory 206416 kb
Host smart-40fb4dbe-157c-40ec-a912-9c35ec461a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3047446283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3047446283
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3405929443
Short name T827
Test name
Test status
Simulation time 4396658899 ps
CPU time 5.68 seconds
Started Jul 10 06:39:21 PM PDT 24
Finished Jul 10 06:39:32 PM PDT 24
Peak memory 206600 kb
Host smart-c6cb8eac-c603-40d0-b58f-2fccedecfeb3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3405929443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3405929443
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.106830756
Short name T1125
Test name
Test status
Simulation time 23475552811 ps
CPU time 30.18 seconds
Started Jul 10 06:39:16 PM PDT 24
Finished Jul 10 06:39:52 PM PDT 24
Peak memory 206700 kb
Host smart-c5014e27-5501-488d-83dc-8b08e8cdb0b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=106830756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.106830756
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3707251882
Short name T2592
Test name
Test status
Simulation time 183938871 ps
CPU time 0.85 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:39:30 PM PDT 24
Peak memory 206408 kb
Host smart-c99cfcb8-e134-43c7-b5f6-c98f10fd34ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37072
51882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3707251882
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2523044175
Short name T54
Test name
Test status
Simulation time 186151123 ps
CPU time 0.87 seconds
Started Jul 10 06:39:17 PM PDT 24
Finished Jul 10 06:39:23 PM PDT 24
Peak memory 206356 kb
Host smart-b867c2f0-d4c9-4d9d-a178-1a2ddf4c2b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25230
44175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2523044175
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3639726410
Short name T67
Test name
Test status
Simulation time 148202916 ps
CPU time 0.79 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:24 PM PDT 24
Peak memory 206372 kb
Host smart-a7917ad8-ec69-498b-9301-61e577b7f513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36397
26410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3639726410
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3196535245
Short name T1604
Test name
Test status
Simulation time 170853159 ps
CPU time 0.8 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:39:26 PM PDT 24
Peak memory 206396 kb
Host smart-8b808fdf-fada-4b86-bf4d-9d6fa50bb447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31965
35245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3196535245
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.4109318492
Short name T2051
Test name
Test status
Simulation time 325984832 ps
CPU time 1.1 seconds
Started Jul 10 06:39:22 PM PDT 24
Finished Jul 10 06:39:28 PM PDT 24
Peak memory 206376 kb
Host smart-fcc6202a-63e3-44b3-969b-f0fcb9530048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41093
18492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.4109318492
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.4212851284
Short name T514
Test name
Test status
Simulation time 549023315 ps
CPU time 1.57 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:25 PM PDT 24
Peak memory 206392 kb
Host smart-e7d84e4d-ea4e-45cf-868c-366cd3390df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42128
51284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.4212851284
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3217176636
Short name T2450
Test name
Test status
Simulation time 21366275360 ps
CPU time 38.46 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:40:04 PM PDT 24
Peak memory 206628 kb
Host smart-4f5391fe-28d1-4bcf-b1bd-a2acc703f4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32171
76636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3217176636
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.116638605
Short name T1149
Test name
Test status
Simulation time 410839757 ps
CPU time 1.24 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:25 PM PDT 24
Peak memory 206360 kb
Host smart-9a549771-5040-4933-8667-da505ca70859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11663
8605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.116638605
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1213100645
Short name T2535
Test name
Test status
Simulation time 185334934 ps
CPU time 0.76 seconds
Started Jul 10 06:39:23 PM PDT 24
Finished Jul 10 06:39:29 PM PDT 24
Peak memory 206400 kb
Host smart-6f057b25-5a1a-445e-982e-d719a274071f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131
00645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1213100645
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2793394823
Short name T370
Test name
Test status
Simulation time 38190616 ps
CPU time 0.65 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:23 PM PDT 24
Peak memory 206368 kb
Host smart-5d933b37-9945-49fa-a409-7075b81be37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27933
94823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2793394823
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1380386036
Short name T1295
Test name
Test status
Simulation time 789031029 ps
CPU time 1.92 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:39:28 PM PDT 24
Peak memory 206592 kb
Host smart-924a1675-41fa-4bb9-b470-25362d49de44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13803
86036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1380386036
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1498414489
Short name T216
Test name
Test status
Simulation time 312395255 ps
CPU time 2.27 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:39:28 PM PDT 24
Peak memory 206580 kb
Host smart-a74018f7-4387-495d-8613-520ef86ba5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14984
14489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1498414489
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3829455608
Short name T548
Test name
Test status
Simulation time 116199673366 ps
CPU time 156.72 seconds
Started Jul 10 06:39:17 PM PDT 24
Finished Jul 10 06:41:59 PM PDT 24
Peak memory 206596 kb
Host smart-e7bfe710-1173-40c8-a8cf-2a139b55277f
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3829455608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3829455608
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.524626500
Short name T2416
Test name
Test status
Simulation time 90087571121 ps
CPU time 118.09 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:41:24 PM PDT 24
Peak memory 206796 kb
Host smart-c479b7de-0155-4de9-a8a7-9892d0114cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524626500 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.524626500
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.1610249738
Short name T874
Test name
Test status
Simulation time 113101723238 ps
CPU time 182.74 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:42:29 PM PDT 24
Peak memory 206628 kb
Host smart-fc7393c2-fee9-47e8-b1ba-dedac842bd5d
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1610249738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.1610249738
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2203523769
Short name T2349
Test name
Test status
Simulation time 120985660932 ps
CPU time 177.91 seconds
Started Jul 10 06:39:22 PM PDT 24
Finished Jul 10 06:42:25 PM PDT 24
Peak memory 206632 kb
Host smart-bcef2d4b-91a6-4a1b-a708-6011394802aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203523769 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2203523769
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.4088845675
Short name T2119
Test name
Test status
Simulation time 102182799772 ps
CPU time 144.3 seconds
Started Jul 10 06:39:19 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206640 kb
Host smart-2e0b300a-a127-41cc-ae34-fb7864b001f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40888
45675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.4088845675
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2545415870
Short name T2346
Test name
Test status
Simulation time 225828284 ps
CPU time 0.9 seconds
Started Jul 10 06:39:16 PM PDT 24
Finished Jul 10 06:39:22 PM PDT 24
Peak memory 206364 kb
Host smart-a3b2e26f-961c-4bff-a8c9-d707189f7e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454
15870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2545415870
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2869178743
Short name T117
Test name
Test status
Simulation time 176412934 ps
CPU time 0.76 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:24 PM PDT 24
Peak memory 206364 kb
Host smart-340c875e-1ee7-429f-8c02-5e8e217313fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28691
78743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2869178743
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1449633811
Short name T1092
Test name
Test status
Simulation time 223120079 ps
CPU time 0.9 seconds
Started Jul 10 06:39:19 PM PDT 24
Finished Jul 10 06:39:25 PM PDT 24
Peak memory 206392 kb
Host smart-8a09a4a4-ac17-4ebe-983b-0b16a02add25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14496
33811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1449633811
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.2595759830
Short name T2108
Test name
Test status
Simulation time 7988822938 ps
CPU time 56.85 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:40:20 PM PDT 24
Peak memory 206684 kb
Host smart-0a2da544-101b-4389-aa01-044480c372b6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2595759830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2595759830
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2859533243
Short name T2472
Test name
Test status
Simulation time 4656097926 ps
CPU time 40.92 seconds
Started Jul 10 06:39:17 PM PDT 24
Finished Jul 10 06:40:03 PM PDT 24
Peak memory 206692 kb
Host smart-e25d8173-dd51-422f-8f86-63ec5612f692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28595
33243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2859533243
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3253732295
Short name T1721
Test name
Test status
Simulation time 202987997 ps
CPU time 0.8 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:24 PM PDT 24
Peak memory 206368 kb
Host smart-033dbd67-3cc7-4b5b-82a5-f2b1ffff956d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32537
32295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3253732295
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1220583527
Short name T1899
Test name
Test status
Simulation time 23332067665 ps
CPU time 27.29 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:39:53 PM PDT 24
Peak memory 206440 kb
Host smart-1d00f536-fe2f-46da-977c-83463c892388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12205
83527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1220583527
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2406577239
Short name T960
Test name
Test status
Simulation time 3355619724 ps
CPU time 4.15 seconds
Started Jul 10 06:39:19 PM PDT 24
Finished Jul 10 06:39:28 PM PDT 24
Peak memory 206476 kb
Host smart-1f5318ec-d5c8-4829-81e7-4a06e94a4088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24065
77239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2406577239
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1627657589
Short name T1448
Test name
Test status
Simulation time 10448746372 ps
CPU time 73.44 seconds
Started Jul 10 06:39:19 PM PDT 24
Finished Jul 10 06:40:38 PM PDT 24
Peak memory 206732 kb
Host smart-38c05a99-2ec3-4fc6-b14e-17b1ef55d279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16276
57589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1627657589
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.369321976
Short name T2068
Test name
Test status
Simulation time 5637759294 ps
CPU time 160.85 seconds
Started Jul 10 06:39:20 PM PDT 24
Finished Jul 10 06:42:06 PM PDT 24
Peak memory 206664 kb
Host smart-c8903503-5ef2-4c84-bfda-ac4613719d24
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=369321976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.369321976
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1334941162
Short name T2370
Test name
Test status
Simulation time 237336467 ps
CPU time 0.93 seconds
Started Jul 10 06:39:18 PM PDT 24
Finished Jul 10 06:39:24 PM PDT 24
Peak memory 206380 kb
Host smart-1d8d43ad-51cc-4e1b-88ef-694f61568c9f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1334941162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1334941162
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1476835805
Short name T2216
Test name
Test status
Simulation time 196811268 ps
CPU time 0.87 seconds
Started Jul 10 06:39:28 PM PDT 24
Finished Jul 10 06:39:34 PM PDT 24
Peak memory 206328 kb
Host smart-d4db1d87-24c4-4504-9566-d0348be6bcbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14768
35805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1476835805
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.292987172
Short name T1029
Test name
Test status
Simulation time 6417646159 ps
CPU time 43 seconds
Started Jul 10 06:39:27 PM PDT 24
Finished Jul 10 06:40:15 PM PDT 24
Peak memory 206644 kb
Host smart-4aac4b1b-9fb6-4599-834a-33f6c84e81c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29298
7172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.292987172
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2789109407
Short name T1759
Test name
Test status
Simulation time 7328615561 ps
CPU time 193.21 seconds
Started Jul 10 06:39:28 PM PDT 24
Finished Jul 10 06:42:46 PM PDT 24
Peak memory 206120 kb
Host smart-c7a1c44e-5941-41b0-92d9-ef4cdb9673fb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2789109407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2789109407
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3516573525
Short name T1962
Test name
Test status
Simulation time 169473385 ps
CPU time 0.85 seconds
Started Jul 10 06:39:27 PM PDT 24
Finished Jul 10 06:39:32 PM PDT 24
Peak memory 206380 kb
Host smart-d95855db-8429-47ad-a791-5ddeae8c449a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3516573525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3516573525
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1081275437
Short name T975
Test name
Test status
Simulation time 157703765 ps
CPU time 0.82 seconds
Started Jul 10 06:39:27 PM PDT 24
Finished Jul 10 06:39:32 PM PDT 24
Peak memory 206392 kb
Host smart-d6a0c23c-a6e3-430c-824e-03d6b9ba8166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10812
75437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1081275437
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1850683177
Short name T1865
Test name
Test status
Simulation time 220250189 ps
CPU time 0.87 seconds
Started Jul 10 06:39:23 PM PDT 24
Finished Jul 10 06:39:29 PM PDT 24
Peak memory 206400 kb
Host smart-b311853d-385b-4939-a04b-7083c09848d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18506
83177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1850683177
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3230092170
Short name T1502
Test name
Test status
Simulation time 196715486 ps
CPU time 0.8 seconds
Started Jul 10 06:39:23 PM PDT 24
Finished Jul 10 06:39:29 PM PDT 24
Peak memory 206388 kb
Host smart-e5ff454a-426a-4732-bc23-e5edc943dbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
92170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3230092170
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1431489742
Short name T1412
Test name
Test status
Simulation time 146140211 ps
CPU time 0.78 seconds
Started Jul 10 06:39:26 PM PDT 24
Finished Jul 10 06:39:32 PM PDT 24
Peak memory 206384 kb
Host smart-3ffc8c48-9f16-4a3c-9307-9a5cb5f2bbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14314
89742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1431489742
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.4112454184
Short name T778
Test name
Test status
Simulation time 184208704 ps
CPU time 0.8 seconds
Started Jul 10 06:39:28 PM PDT 24
Finished Jul 10 06:39:33 PM PDT 24
Peak memory 205820 kb
Host smart-ea52506c-c0a3-4b1f-aaee-a31b9b3c6d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41124
54184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.4112454184
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1368815740
Short name T2681
Test name
Test status
Simulation time 167171437 ps
CPU time 0.78 seconds
Started Jul 10 06:39:27 PM PDT 24
Finished Jul 10 06:39:32 PM PDT 24
Peak memory 206396 kb
Host smart-d49aa89a-70df-42b0-8704-c5096fb5a673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13688
15740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1368815740
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3884404952
Short name T1939
Test name
Test status
Simulation time 224779644 ps
CPU time 0.98 seconds
Started Jul 10 06:39:23 PM PDT 24
Finished Jul 10 06:39:29 PM PDT 24
Peak memory 206384 kb
Host smart-2620b1cf-1a49-45e0-a6bf-bc0322b659d0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3884404952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3884404952
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.4193484959
Short name T1875
Test name
Test status
Simulation time 242095734 ps
CPU time 0.97 seconds
Started Jul 10 06:39:25 PM PDT 24
Finished Jul 10 06:39:31 PM PDT 24
Peak memory 206420 kb
Host smart-dc225d5b-157f-4723-a42d-1f1e7f65e64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41934
84959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.4193484959
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.366726300
Short name T2023
Test name
Test status
Simulation time 142872676 ps
CPU time 0.81 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:39:30 PM PDT 24
Peak memory 206372 kb
Host smart-b6bd7ba5-b9e1-4664-a420-53922aa82791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36672
6300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.366726300
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2612870490
Short name T1725
Test name
Test status
Simulation time 105405217 ps
CPU time 0.72 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:39:30 PM PDT 24
Peak memory 206372 kb
Host smart-431b38b0-10c2-48ef-81f4-29dfda886a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26128
70490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2612870490
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3894787363
Short name T211
Test name
Test status
Simulation time 12990219208 ps
CPU time 32.51 seconds
Started Jul 10 06:39:25 PM PDT 24
Finished Jul 10 06:40:02 PM PDT 24
Peak memory 206688 kb
Host smart-2a6cbd7f-d241-41a8-8865-d09b731bf9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38947
87363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3894787363
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1823911573
Short name T1216
Test name
Test status
Simulation time 186367556 ps
CPU time 0.96 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:39:30 PM PDT 24
Peak memory 206376 kb
Host smart-a0e18eb9-7505-488f-aa71-ed8dcddd154a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18239
11573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1823911573
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3463088373
Short name T1691
Test name
Test status
Simulation time 211386737 ps
CPU time 0.87 seconds
Started Jul 10 06:39:27 PM PDT 24
Finished Jul 10 06:39:33 PM PDT 24
Peak memory 206392 kb
Host smart-65e2d0ca-ae8c-49d3-bdea-574322808890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34630
88373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3463088373
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.4198779518
Short name T2355
Test name
Test status
Simulation time 8038176837 ps
CPU time 55.56 seconds
Started Jul 10 06:39:25 PM PDT 24
Finished Jul 10 06:40:25 PM PDT 24
Peak memory 206692 kb
Host smart-fc283422-7359-447d-9120-ec2460d1617d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4198779518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.4198779518
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3662243267
Short name T1797
Test name
Test status
Simulation time 15323231526 ps
CPU time 102.82 seconds
Started Jul 10 06:39:23 PM PDT 24
Finished Jul 10 06:41:11 PM PDT 24
Peak memory 206700 kb
Host smart-8c5253f0-e5f4-4246-9870-07037bc8de77
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3662243267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3662243267
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3607702903
Short name T409
Test name
Test status
Simulation time 239378287 ps
CPU time 0.92 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:39:30 PM PDT 24
Peak memory 206284 kb
Host smart-46421824-25c6-42ad-b87a-19580257c7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36077
02903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3607702903
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1032493504
Short name T2670
Test name
Test status
Simulation time 216328947 ps
CPU time 0.88 seconds
Started Jul 10 06:39:26 PM PDT 24
Finished Jul 10 06:39:32 PM PDT 24
Peak memory 206380 kb
Host smart-f19d29f7-44ad-4737-af1e-fd1ec034cd29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10324
93504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1032493504
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3948644104
Short name T75
Test name
Test status
Simulation time 141379400 ps
CPU time 0.76 seconds
Started Jul 10 06:39:23 PM PDT 24
Finished Jul 10 06:39:29 PM PDT 24
Peak memory 206396 kb
Host smart-27723755-394a-4b1f-bb6b-84a64b486532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39486
44104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3948644104
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3883916324
Short name T80
Test name
Test status
Simulation time 204234395 ps
CPU time 0.83 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:39:29 PM PDT 24
Peak memory 206372 kb
Host smart-8f53fc3c-b54c-4210-b575-bc26b35a9ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
16324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3883916324
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1959173378
Short name T208
Test name
Test status
Simulation time 379189632 ps
CPU time 1.18 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:39:39 PM PDT 24
Peak memory 224268 kb
Host smart-9d362379-2f3b-421f-aa49-00f594cdab8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1959173378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1959173378
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.304441931
Short name T2609
Test name
Test status
Simulation time 357740860 ps
CPU time 1.34 seconds
Started Jul 10 06:39:25 PM PDT 24
Finished Jul 10 06:39:31 PM PDT 24
Peak memory 206400 kb
Host smart-9ba95acd-c9cf-44d2-b5fb-a469d8316f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30444
1931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.304441931
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2031469540
Short name T1300
Test name
Test status
Simulation time 299227779 ps
CPU time 1.03 seconds
Started Jul 10 06:39:24 PM PDT 24
Finished Jul 10 06:39:30 PM PDT 24
Peak memory 206332 kb
Host smart-03720bff-4c2b-4695-8c12-45332d26d3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20314
69540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2031469540
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.324551137
Short name T513
Test name
Test status
Simulation time 172074100 ps
CPU time 0.8 seconds
Started Jul 10 06:39:27 PM PDT 24
Finished Jul 10 06:39:32 PM PDT 24
Peak memory 206372 kb
Host smart-fbd0495a-a026-4fbb-baad-27ed738b5045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455
1137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.324551137
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2935344036
Short name T1571
Test name
Test status
Simulation time 162209244 ps
CPU time 0.76 seconds
Started Jul 10 06:39:23 PM PDT 24
Finished Jul 10 06:39:29 PM PDT 24
Peak memory 206376 kb
Host smart-85d6fbf3-1bea-452d-ab05-4c3a977bab08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29353
44036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2935344036
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3327123695
Short name T156
Test name
Test status
Simulation time 198728040 ps
CPU time 0.85 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:39:38 PM PDT 24
Peak memory 206276 kb
Host smart-ced8678c-f578-44b4-8492-ab568ba4ae31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33271
23695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3327123695
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3061714817
Short name T2069
Test name
Test status
Simulation time 3266043850 ps
CPU time 30.21 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206640 kb
Host smart-456cf2df-4846-4c5d-9f07-026cc6f0504f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3061714817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3061714817
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.494364937
Short name T834
Test name
Test status
Simulation time 151040500 ps
CPU time 0.8 seconds
Started Jul 10 06:39:34 PM PDT 24
Finished Jul 10 06:39:36 PM PDT 24
Peak memory 206392 kb
Host smart-8b3447e0-88d8-42d9-b834-92e83661d5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49436
4937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.494364937
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3338761167
Short name T1435
Test name
Test status
Simulation time 201500897 ps
CPU time 0.8 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:39:39 PM PDT 24
Peak memory 206376 kb
Host smart-0d1a984c-c5bc-4e03-8279-68e15d58ce80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33387
61167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3338761167
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3623235921
Short name T382
Test name
Test status
Simulation time 686567436 ps
CPU time 1.66 seconds
Started Jul 10 06:39:36 PM PDT 24
Finished Jul 10 06:39:40 PM PDT 24
Peak memory 206604 kb
Host smart-7cea24f3-01a6-41d2-8cc7-161bed26cae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36232
35921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3623235921
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.245175882
Short name T2394
Test name
Test status
Simulation time 4725741055 ps
CPU time 44 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:40:21 PM PDT 24
Peak memory 206664 kb
Host smart-f4f587f8-d5c6-4dc4-8764-1f299b25bf37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517
5882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.245175882
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.953297986
Short name T2577
Test name
Test status
Simulation time 48407078 ps
CPU time 0.68 seconds
Started Jul 10 06:44:27 PM PDT 24
Finished Jul 10 06:44:33 PM PDT 24
Peak memory 206432 kb
Host smart-b399c6ec-d2cd-48e9-a830-053c82c03782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=953297986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.953297986
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1831822152
Short name T1375
Test name
Test status
Simulation time 3995671841 ps
CPU time 5.21 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:34 PM PDT 24
Peak memory 206608 kb
Host smart-95235407-c280-4d39-b198-11d218b70f51
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1831822152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.1831822152
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3214883104
Short name T760
Test name
Test status
Simulation time 13321837695 ps
CPU time 13.5 seconds
Started Jul 10 06:44:15 PM PDT 24
Finished Jul 10 06:44:32 PM PDT 24
Peak memory 206692 kb
Host smart-472886d0-5448-4f1f-b843-b7d15694cdae
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3214883104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3214883104
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1621416650
Short name T1598
Test name
Test status
Simulation time 23409049126 ps
CPU time 24.74 seconds
Started Jul 10 06:44:15 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 206444 kb
Host smart-a44511e5-5ced-4636-837c-21bef94ad7be
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1621416650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1621416650
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.938763668
Short name T1480
Test name
Test status
Simulation time 180850162 ps
CPU time 0.84 seconds
Started Jul 10 06:44:17 PM PDT 24
Finished Jul 10 06:44:21 PM PDT 24
Peak memory 206352 kb
Host smart-bdac2bdf-0e8b-4bb8-a5c4-d45fabc20c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93876
3668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.938763668
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1635373048
Short name T2458
Test name
Test status
Simulation time 154360521 ps
CPU time 0.82 seconds
Started Jul 10 06:44:13 PM PDT 24
Finished Jul 10 06:44:18 PM PDT 24
Peak memory 206380 kb
Host smart-187712ee-89b7-4a51-ab06-854878a9438c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16353
73048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1635373048
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3502338765
Short name T2591
Test name
Test status
Simulation time 227755803 ps
CPU time 0.82 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206312 kb
Host smart-e5880937-f98a-495b-88f0-363289ea0bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35023
38765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3502338765
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.4086790787
Short name T2582
Test name
Test status
Simulation time 422992250 ps
CPU time 1.2 seconds
Started Jul 10 06:44:18 PM PDT 24
Finished Jul 10 06:44:22 PM PDT 24
Peak memory 206276 kb
Host smart-0527760f-87ce-414d-9a4a-ea6cd1acca19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40867
90787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.4086790787
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.837213171
Short name T1400
Test name
Test status
Simulation time 15776518214 ps
CPU time 31.3 seconds
Started Jul 10 06:44:17 PM PDT 24
Finished Jul 10 06:44:52 PM PDT 24
Peak memory 206676 kb
Host smart-b38488c8-aae6-472a-80cf-98ad99f997dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83721
3171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.837213171
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.950808409
Short name T444
Test name
Test status
Simulation time 407846951 ps
CPU time 1.22 seconds
Started Jul 10 06:44:16 PM PDT 24
Finished Jul 10 06:44:20 PM PDT 24
Peak memory 206396 kb
Host smart-bc651504-97ad-47d7-8d69-25f9b73899b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95080
8409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.950808409
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3319983237
Short name T883
Test name
Test status
Simulation time 174241235 ps
CPU time 0.86 seconds
Started Jul 10 06:44:23 PM PDT 24
Finished Jul 10 06:44:26 PM PDT 24
Peak memory 206356 kb
Host smart-2fc23f8a-7f01-4732-89ae-153706a31331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33199
83237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3319983237
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.4272574961
Short name T378
Test name
Test status
Simulation time 47758403 ps
CPU time 0.66 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206376 kb
Host smart-80f19309-a1de-4534-810e-acf42d2b1011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42725
74961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.4272574961
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3198671271
Short name T694
Test name
Test status
Simulation time 720988344 ps
CPU time 1.74 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:24 PM PDT 24
Peak memory 206620 kb
Host smart-72099e2f-9e91-472a-b3e3-491c4d657b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31986
71271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3198671271
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3610560916
Short name T1091
Test name
Test status
Simulation time 190972786 ps
CPU time 2.22 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:30 PM PDT 24
Peak memory 206560 kb
Host smart-1377fdfe-5e37-4c91-b228-9d95ee7b8635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36105
60916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3610560916
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.315024684
Short name T1580
Test name
Test status
Simulation time 175814710 ps
CPU time 0.84 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206304 kb
Host smart-f43bc39a-ca74-474a-a098-36dc666da47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502
4684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.315024684
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2601411726
Short name T903
Test name
Test status
Simulation time 162246040 ps
CPU time 0.76 seconds
Started Jul 10 06:44:19 PM PDT 24
Finished Jul 10 06:44:23 PM PDT 24
Peak memory 206372 kb
Host smart-db20b90a-f05e-4250-acb9-80ed8107161d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26014
11726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2601411726
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1261715765
Short name T1241
Test name
Test status
Simulation time 250919752 ps
CPU time 0.88 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206384 kb
Host smart-84e396a1-05f2-4f97-8a92-c35557d404ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12617
15765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1261715765
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2897772392
Short name T1779
Test name
Test status
Simulation time 7315034223 ps
CPU time 50.03 seconds
Started Jul 10 06:44:15 PM PDT 24
Finished Jul 10 06:45:08 PM PDT 24
Peak memory 206616 kb
Host smart-d4d7d8cb-db76-4b4e-aca1-dff8799b02ed
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2897772392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2897772392
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2939225025
Short name T636
Test name
Test status
Simulation time 4401274964 ps
CPU time 37.7 seconds
Started Jul 10 06:44:23 PM PDT 24
Finished Jul 10 06:45:03 PM PDT 24
Peak memory 206672 kb
Host smart-f17a34ae-ce3b-4e4b-9d7c-74c878f5e68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29392
25025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2939225025
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2437463656
Short name T681
Test name
Test status
Simulation time 227596417 ps
CPU time 0.84 seconds
Started Jul 10 06:44:23 PM PDT 24
Finished Jul 10 06:44:26 PM PDT 24
Peak memory 206376 kb
Host smart-4d0ac39d-6a55-4182-9da8-3b4571529579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24374
63656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2437463656
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3950465757
Short name T1566
Test name
Test status
Simulation time 23271600660 ps
CPU time 29.13 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:45:06 PM PDT 24
Peak memory 206444 kb
Host smart-b0b95907-894b-4235-af7d-e18d03cff4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39504
65757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3950465757
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.689667470
Short name T358
Test name
Test status
Simulation time 3342249297 ps
CPU time 4.07 seconds
Started Jul 10 06:44:26 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206440 kb
Host smart-233de6fc-de41-41fa-9b9d-81d9f1bc60b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68966
7470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.689667470
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.4068882817
Short name T655
Test name
Test status
Simulation time 11186765592 ps
CPU time 105.4 seconds
Started Jul 10 06:44:23 PM PDT 24
Finished Jul 10 06:46:10 PM PDT 24
Peak memory 206720 kb
Host smart-1008b015-75c6-47a4-9220-a8ab360448e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40688
82817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.4068882817
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3515069038
Short name T1495
Test name
Test status
Simulation time 6219385342 ps
CPU time 172.51 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:47:20 PM PDT 24
Peak memory 206624 kb
Host smart-7a8da94c-216d-4f01-bc11-c1c85c4b9862
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3515069038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3515069038
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2221020142
Short name T2267
Test name
Test status
Simulation time 242115190 ps
CPU time 0.93 seconds
Started Jul 10 06:44:20 PM PDT 24
Finished Jul 10 06:44:24 PM PDT 24
Peak memory 206376 kb
Host smart-ea32b197-2680-436f-94a9-f43eed2eabf3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2221020142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2221020142
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2374181972
Short name T1758
Test name
Test status
Simulation time 215577378 ps
CPU time 0.89 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:27 PM PDT 24
Peak memory 206312 kb
Host smart-557cda45-3fff-48da-8671-5fc8e7e64ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23741
81972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2374181972
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1424595104
Short name T1416
Test name
Test status
Simulation time 5482145780 ps
CPU time 152.81 seconds
Started Jul 10 06:44:21 PM PDT 24
Finished Jul 10 06:46:57 PM PDT 24
Peak memory 206644 kb
Host smart-30be7218-2559-4106-a5a7-66743a0fd198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14245
95104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1424595104
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1046393101
Short name T2420
Test name
Test status
Simulation time 5344896413 ps
CPU time 141.75 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:46:52 PM PDT 24
Peak memory 206552 kb
Host smart-2642e610-6657-4d50-a330-644f4a1cb7dc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1046393101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1046393101
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.993894184
Short name T2504
Test name
Test status
Simulation time 157133157 ps
CPU time 0.79 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:30 PM PDT 24
Peak memory 206356 kb
Host smart-ec73dccd-10d0-40b7-a826-c906ef6f291b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=993894184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.993894184
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.24869668
Short name T977
Test name
Test status
Simulation time 178926625 ps
CPU time 0.78 seconds
Started Jul 10 06:44:34 PM PDT 24
Finished Jul 10 06:44:39 PM PDT 24
Peak memory 206376 kb
Host smart-3450af03-b2df-458a-8c76-17f496900cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24869
668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.24869668
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.4280261821
Short name T1401
Test name
Test status
Simulation time 197358152 ps
CPU time 0.91 seconds
Started Jul 10 06:44:26 PM PDT 24
Finished Jul 10 06:44:31 PM PDT 24
Peak memory 206372 kb
Host smart-5432f2d8-12cd-41d0-88a3-06218c805fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42802
61821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.4280261821
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1787172822
Short name T1536
Test name
Test status
Simulation time 186676503 ps
CPU time 0.89 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206400 kb
Host smart-b638dfd8-5a6a-447d-a2eb-eb94d5c9acef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17871
72822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1787172822
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.624748233
Short name T428
Test name
Test status
Simulation time 184638407 ps
CPU time 0.79 seconds
Started Jul 10 06:44:26 PM PDT 24
Finished Jul 10 06:44:31 PM PDT 24
Peak memory 206376 kb
Host smart-8d10c693-2310-48f8-bab2-731f316f6b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62474
8233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.624748233
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.516132508
Short name T595
Test name
Test status
Simulation time 167865414 ps
CPU time 0.78 seconds
Started Jul 10 06:44:26 PM PDT 24
Finished Jul 10 06:44:32 PM PDT 24
Peak memory 206396 kb
Host smart-f6e88cd4-3de1-483b-876d-b73aeb693f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51613
2508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.516132508
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2124644001
Short name T2211
Test name
Test status
Simulation time 166239318 ps
CPU time 0.84 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206288 kb
Host smart-797ecbf1-48cd-4835-a0ea-84f159afdea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21246
44001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2124644001
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.2545519775
Short name T2179
Test name
Test status
Simulation time 240996912 ps
CPU time 0.94 seconds
Started Jul 10 06:44:23 PM PDT 24
Finished Jul 10 06:44:26 PM PDT 24
Peak memory 206376 kb
Host smart-ea9d6fe7-f287-4914-a394-0905e791a527
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2545519775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.2545519775
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3700409641
Short name T2731
Test name
Test status
Simulation time 150624599 ps
CPU time 0.8 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:27 PM PDT 24
Peak memory 206392 kb
Host smart-123e0c47-760b-47d2-be03-7e5eb4963fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37004
09641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3700409641
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1249425792
Short name T716
Test name
Test status
Simulation time 61573169 ps
CPU time 0.68 seconds
Started Jul 10 06:44:29 PM PDT 24
Finished Jul 10 06:44:34 PM PDT 24
Peak memory 206380 kb
Host smart-e2c1d6d1-742a-49a9-9614-3e790c4d5312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12494
25792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1249425792
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3783827866
Short name T1345
Test name
Test status
Simulation time 6137339645 ps
CPU time 15.95 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:44 PM PDT 24
Peak memory 206600 kb
Host smart-591c0df5-0524-4d74-b4d5-176526ade979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37838
27866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3783827866
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1791607945
Short name T851
Test name
Test status
Simulation time 191670048 ps
CPU time 0.78 seconds
Started Jul 10 06:44:23 PM PDT 24
Finished Jul 10 06:44:26 PM PDT 24
Peak memory 206280 kb
Host smart-fb0aa8c1-50f0-452a-93cf-45d58b691c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
07945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1791607945
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4169200796
Short name T1404
Test name
Test status
Simulation time 175884029 ps
CPU time 0.8 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:27 PM PDT 24
Peak memory 206364 kb
Host smart-3dbf6e12-ab4a-4d5c-93d8-b75cb54a2e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41692
00796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4169200796
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3754708099
Short name T519
Test name
Test status
Simulation time 239208337 ps
CPU time 0.98 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206400 kb
Host smart-7aacace1-cf3e-4e94-aaaf-2ede8ecfa14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37547
08099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3754708099
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2113014723
Short name T1487
Test name
Test status
Simulation time 219559033 ps
CPU time 0.82 seconds
Started Jul 10 06:44:22 PM PDT 24
Finished Jul 10 06:44:26 PM PDT 24
Peak memory 206396 kb
Host smart-35bde2ec-c42c-4f90-b664-9d672c5cd9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21130
14723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2113014723
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2753485899
Short name T1142
Test name
Test status
Simulation time 144295493 ps
CPU time 0.83 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:30 PM PDT 24
Peak memory 206392 kb
Host smart-fce5d8c9-5d83-46b5-9368-70592e13360f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27534
85899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2753485899
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1354053315
Short name T1437
Test name
Test status
Simulation time 146276967 ps
CPU time 0.72 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206388 kb
Host smart-6cb3412b-eadd-4b15-92ff-78e90436db07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13540
53315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1354053315
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.940183752
Short name T2114
Test name
Test status
Simulation time 148045609 ps
CPU time 0.75 seconds
Started Jul 10 06:44:23 PM PDT 24
Finished Jul 10 06:44:26 PM PDT 24
Peak memory 206280 kb
Host smart-ecb9fc42-6a72-45c8-90c1-5cb5b7763dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94018
3752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.940183752
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.636260930
Short name T2315
Test name
Test status
Simulation time 208573345 ps
CPU time 0.89 seconds
Started Jul 10 06:44:33 PM PDT 24
Finished Jul 10 06:44:39 PM PDT 24
Peak memory 206376 kb
Host smart-96312dcc-cf60-4f59-8e54-5c058cc15483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63626
0930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.636260930
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1053802531
Short name T1324
Test name
Test status
Simulation time 6964324753 ps
CPU time 67.49 seconds
Started Jul 10 06:44:35 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206612 kb
Host smart-cee8caae-6d12-4fea-b071-9b9ea95b32b7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1053802531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1053802531
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.484844974
Short name T366
Test name
Test status
Simulation time 176360167 ps
CPU time 0.78 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:30 PM PDT 24
Peak memory 206368 kb
Host smart-bda328b3-ed04-4b8b-a424-24da30a294b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48484
4974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.484844974
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.575661114
Short name T745
Test name
Test status
Simulation time 166375205 ps
CPU time 0.85 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206376 kb
Host smart-ab5aa156-3eb1-4842-8658-e274a3f9b3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57566
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.575661114
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1132011138
Short name T957
Test name
Test status
Simulation time 1072097581 ps
CPU time 2.36 seconds
Started Jul 10 06:44:33 PM PDT 24
Finished Jul 10 06:44:40 PM PDT 24
Peak memory 206576 kb
Host smart-5d067efc-601d-4066-b451-35b540bbee60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11320
11138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1132011138
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2287920322
Short name T2026
Test name
Test status
Simulation time 5438441774 ps
CPU time 153.88 seconds
Started Jul 10 06:44:33 PM PDT 24
Finished Jul 10 06:47:12 PM PDT 24
Peak memory 206600 kb
Host smart-6e578286-a72b-4f62-b559-604127186d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22879
20322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2287920322
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.3547707848
Short name T657
Test name
Test status
Simulation time 82345512 ps
CPU time 0.72 seconds
Started Jul 10 06:44:44 PM PDT 24
Finished Jul 10 06:44:48 PM PDT 24
Peak memory 206344 kb
Host smart-013c3761-60ad-45d7-896e-6cc877889a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3547707848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.3547707848
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3450804221
Short name T937
Test name
Test status
Simulation time 3820664058 ps
CPU time 4.83 seconds
Started Jul 10 06:44:27 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206656 kb
Host smart-3951a2cc-7a06-456d-8582-c15cfab33e45
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3450804221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3450804221
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1700251442
Short name T1687
Test name
Test status
Simulation time 13297349227 ps
CPU time 13.08 seconds
Started Jul 10 06:44:37 PM PDT 24
Finished Jul 10 06:44:53 PM PDT 24
Peak memory 206456 kb
Host smart-11776c45-11f3-4a15-916a-b88884635805
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1700251442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1700251442
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.4261277258
Short name T357
Test name
Test status
Simulation time 23337211379 ps
CPU time 30.18 seconds
Started Jul 10 06:44:25 PM PDT 24
Finished Jul 10 06:44:58 PM PDT 24
Peak memory 206464 kb
Host smart-057ca025-c611-4617-87b9-3efac305f358
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4261277258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.4261277258
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1207592336
Short name T1767
Test name
Test status
Simulation time 152007159 ps
CPU time 0.78 seconds
Started Jul 10 06:44:29 PM PDT 24
Finished Jul 10 06:44:34 PM PDT 24
Peak memory 206380 kb
Host smart-dba22967-a97e-489d-9305-56254075a3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12075
92336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1207592336
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1870879819
Short name T1619
Test name
Test status
Simulation time 151575389 ps
CPU time 0.78 seconds
Started Jul 10 06:44:26 PM PDT 24
Finished Jul 10 06:44:32 PM PDT 24
Peak memory 206380 kb
Host smart-a7c46dfc-5a94-4365-9966-2a3f2649e399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708
79819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1870879819
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2679131836
Short name T1667
Test name
Test status
Simulation time 259257720 ps
CPU time 1.01 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:28 PM PDT 24
Peak memory 206392 kb
Host smart-ec78311a-1df3-46eb-bd6f-89dc8fbe85f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26791
31836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2679131836
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3469011346
Short name T2093
Test name
Test status
Simulation time 1424126590 ps
CPU time 3.14 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:30 PM PDT 24
Peak memory 206588 kb
Host smart-cb72a6bc-d58b-4a66-8dec-6a42b4a2dae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34690
11346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3469011346
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3884111412
Short name T1090
Test name
Test status
Simulation time 7769090694 ps
CPU time 15.66 seconds
Started Jul 10 06:44:28 PM PDT 24
Finished Jul 10 06:44:49 PM PDT 24
Peak memory 206688 kb
Host smart-598addbf-5581-444b-96ad-c0ba5458165c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841
11412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3884111412
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.1584010836
Short name T1313
Test name
Test status
Simulation time 305276216 ps
CPU time 1.05 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:38 PM PDT 24
Peak memory 206396 kb
Host smart-c2248018-558c-4867-9123-caae53640bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15840
10836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.1584010836
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1812894323
Short name T334
Test name
Test status
Simulation time 160263120 ps
CPU time 0.75 seconds
Started Jul 10 06:44:24 PM PDT 24
Finished Jul 10 06:44:27 PM PDT 24
Peak memory 206376 kb
Host smart-3a2a6475-c810-40d5-b362-bd41e69951c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
94323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1812894323
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1476313594
Short name T946
Test name
Test status
Simulation time 40714319 ps
CPU time 0.65 seconds
Started Jul 10 06:44:29 PM PDT 24
Finished Jul 10 06:44:34 PM PDT 24
Peak memory 206388 kb
Host smart-df949a8e-fb0e-439b-93d7-93e062428651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14763
13594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1476313594
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1263561753
Short name T1011
Test name
Test status
Simulation time 888121249 ps
CPU time 2.21 seconds
Started Jul 10 06:44:34 PM PDT 24
Finished Jul 10 06:44:41 PM PDT 24
Peak memory 206532 kb
Host smart-31d0ff03-b5c8-483a-996d-1d48fa3baf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12635
61753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1263561753
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1311656074
Short name T2689
Test name
Test status
Simulation time 225525389 ps
CPU time 1.34 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206620 kb
Host smart-435a0ada-db6b-4c64-b5de-897f01fa675a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13116
56074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1311656074
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4111148266
Short name T1876
Test name
Test status
Simulation time 264645696 ps
CPU time 0.94 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206388 kb
Host smart-61584009-633d-4c91-a8a9-2ada0e10c057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41111
48266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4111148266
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2906973303
Short name T2750
Test name
Test status
Simulation time 139639371 ps
CPU time 0.77 seconds
Started Jul 10 06:44:30 PM PDT 24
Finished Jul 10 06:44:35 PM PDT 24
Peak memory 206276 kb
Host smart-1bc166c7-0d80-4717-89c5-dc8aacd25e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29069
73303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2906973303
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3221774616
Short name T1947
Test name
Test status
Simulation time 161388189 ps
CPU time 0.81 seconds
Started Jul 10 06:44:35 PM PDT 24
Finished Jul 10 06:44:40 PM PDT 24
Peak memory 206368 kb
Host smart-d94f5f14-0717-49bb-b454-0f3b6eda4680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32217
74616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3221774616
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.431757722
Short name T1352
Test name
Test status
Simulation time 10428868391 ps
CPU time 40.13 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:45:16 PM PDT 24
Peak memory 206636 kb
Host smart-29eebb26-5c4d-4a6c-b87f-ccab39dcaf5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43175
7722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.431757722
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.153544420
Short name T1893
Test name
Test status
Simulation time 234202439 ps
CPU time 0.95 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:44:49 PM PDT 24
Peak memory 206384 kb
Host smart-6a78d353-8feb-4a4f-9122-58d49464f0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15354
4420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.153544420
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3505637072
Short name T628
Test name
Test status
Simulation time 23349555444 ps
CPU time 24.06 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:44:59 PM PDT 24
Peak memory 206440 kb
Host smart-031e7809-f38a-4e95-a3e3-04364c9cb44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35056
37072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3505637072
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2403065963
Short name T2701
Test name
Test status
Simulation time 3279156404 ps
CPU time 4.03 seconds
Started Jul 10 06:44:30 PM PDT 24
Finished Jul 10 06:44:38 PM PDT 24
Peak memory 206432 kb
Host smart-43d167cd-7313-4dae-9cf0-e8b0dd38d36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24030
65963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2403065963
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1766093334
Short name T496
Test name
Test status
Simulation time 6499736084 ps
CPU time 50.65 seconds
Started Jul 10 06:44:34 PM PDT 24
Finished Jul 10 06:45:29 PM PDT 24
Peak memory 206704 kb
Host smart-0c9c3865-ac35-43d3-83bd-828b44aec518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17660
93334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1766093334
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.697857309
Short name T2104
Test name
Test status
Simulation time 3951755701 ps
CPU time 36.84 seconds
Started Jul 10 06:44:30 PM PDT 24
Finished Jul 10 06:45:11 PM PDT 24
Peak memory 206872 kb
Host smart-58c84309-5321-4148-9425-63a99dab6bca
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=697857309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.697857309
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1672918354
Short name T567
Test name
Test status
Simulation time 336668527 ps
CPU time 1.08 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206388 kb
Host smart-e49b480a-7f90-49d3-a99e-222dccea22a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1672918354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1672918354
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.622880609
Short name T2180
Test name
Test status
Simulation time 289097816 ps
CPU time 1 seconds
Started Jul 10 06:44:30 PM PDT 24
Finished Jul 10 06:44:35 PM PDT 24
Peak memory 206380 kb
Host smart-c3881371-34f1-46c6-8cf9-de6a8dd9f8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62288
0609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.622880609
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.827334151
Short name T154
Test name
Test status
Simulation time 4261540001 ps
CPU time 117.56 seconds
Started Jul 10 06:44:33 PM PDT 24
Finished Jul 10 06:46:35 PM PDT 24
Peak memory 206656 kb
Host smart-12aa19b5-3b12-42b1-b683-056159d9551b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82733
4151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.827334151
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2318798556
Short name T801
Test name
Test status
Simulation time 5599388141 ps
CPU time 40.19 seconds
Started Jul 10 06:44:40 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206704 kb
Host smart-928cc66c-d0c7-4bd3-9e4b-c9d1838e630a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2318798556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2318798556
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3202206972
Short name T1874
Test name
Test status
Simulation time 157579579 ps
CPU time 0.8 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:44:49 PM PDT 24
Peak memory 206396 kb
Host smart-57cb4295-86a7-452b-8b2a-c9d56043aa7c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3202206972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3202206972
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.287309605
Short name T2070
Test name
Test status
Simulation time 155134025 ps
CPU time 0.74 seconds
Started Jul 10 06:44:33 PM PDT 24
Finished Jul 10 06:44:38 PM PDT 24
Peak memory 206384 kb
Host smart-c1d6ca1a-425e-4179-827d-50dd69c823d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730
9605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.287309605
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2248608511
Short name T2708
Test name
Test status
Simulation time 219327149 ps
CPU time 0.88 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206384 kb
Host smart-81dfd025-a6f7-4888-9842-3c65ee86d918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22486
08511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2248608511
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3634734841
Short name T1143
Test name
Test status
Simulation time 178644937 ps
CPU time 0.83 seconds
Started Jul 10 06:44:29 PM PDT 24
Finished Jul 10 06:44:34 PM PDT 24
Peak memory 206564 kb
Host smart-e7605c59-a533-4699-86c6-765cbbf540aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36347
34841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3634734841
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2324080842
Short name T2520
Test name
Test status
Simulation time 189057698 ps
CPU time 0.8 seconds
Started Jul 10 06:44:33 PM PDT 24
Finished Jul 10 06:44:38 PM PDT 24
Peak memory 206312 kb
Host smart-99262422-6a9a-449e-bc12-3bcea836e720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23240
80842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2324080842
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1365734497
Short name T682
Test name
Test status
Simulation time 177117002 ps
CPU time 0.81 seconds
Started Jul 10 06:44:37 PM PDT 24
Finished Jul 10 06:44:41 PM PDT 24
Peak memory 206376 kb
Host smart-b35a854a-c4e8-49fe-b66a-e855a570f7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13657
34497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1365734497
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3859715759
Short name T2550
Test name
Test status
Simulation time 165989772 ps
CPU time 0.8 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206368 kb
Host smart-8e6bc2e8-7ab2-4cc2-a86e-9b3abf7983ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
15759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3859715759
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3056428901
Short name T2078
Test name
Test status
Simulation time 253262867 ps
CPU time 1 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206380 kb
Host smart-14547936-6e66-4748-be80-dce29b6f6f68
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3056428901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3056428901
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1344189097
Short name T38
Test name
Test status
Simulation time 148614213 ps
CPU time 0.77 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206360 kb
Host smart-90d9e35a-4a87-46d3-a495-5acfd4f682d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13441
89097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1344189097
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2620479601
Short name T601
Test name
Test status
Simulation time 70261224 ps
CPU time 0.7 seconds
Started Jul 10 06:44:29 PM PDT 24
Finished Jul 10 06:44:34 PM PDT 24
Peak memory 206368 kb
Host smart-82efac80-8d0f-4674-9e7d-26d4387daf48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26204
79601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2620479601
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3374133916
Short name T1812
Test name
Test status
Simulation time 11774133779 ps
CPU time 24.64 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:45:01 PM PDT 24
Peak memory 214860 kb
Host smart-c111e2e2-4c6f-4e02-9415-b5caef26627b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33741
33916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3374133916
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2806442790
Short name T621
Test name
Test status
Simulation time 188294215 ps
CPU time 0.89 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:44:49 PM PDT 24
Peak memory 206308 kb
Host smart-7fd7c15e-40ec-47dc-8ffb-d19cfb3e1a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
42790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2806442790
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2207836213
Short name T1181
Test name
Test status
Simulation time 193465437 ps
CPU time 0.89 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206360 kb
Host smart-5f1aa3e7-9dfe-4ec5-8abf-4483997376f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22078
36213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2207836213
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1372327926
Short name T1590
Test name
Test status
Simulation time 228319691 ps
CPU time 0.86 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:44:48 PM PDT 24
Peak memory 206312 kb
Host smart-6b0dfaf8-4e01-4a1a-9d51-b92ffdb35191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13723
27926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1372327926
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3152138658
Short name T1777
Test name
Test status
Simulation time 193102507 ps
CPU time 0.88 seconds
Started Jul 10 06:44:39 PM PDT 24
Finished Jul 10 06:44:41 PM PDT 24
Peak memory 206400 kb
Host smart-1ed78c70-9d0d-4150-a439-306958f7d748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31521
38658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3152138658
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2705491766
Short name T926
Test name
Test status
Simulation time 161579948 ps
CPU time 0.86 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206376 kb
Host smart-4366b730-be85-4dfb-a730-250ef2b7f1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
91766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2705491766
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1962649458
Short name T2116
Test name
Test status
Simulation time 158996311 ps
CPU time 0.8 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206356 kb
Host smart-32b7a01c-0c55-4273-880e-09f214cec9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19626
49458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1962649458
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2768748759
Short name T1846
Test name
Test status
Simulation time 168330925 ps
CPU time 0.78 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206372 kb
Host smart-c5623de0-4f50-457f-ad3e-0fbe903bfcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27687
48759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2768748759
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2226876868
Short name T2704
Test name
Test status
Simulation time 193835014 ps
CPU time 0.86 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206308 kb
Host smart-f39cd065-0c2c-46bd-b373-92da074342a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22268
76868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2226876868
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1031987263
Short name T897
Test name
Test status
Simulation time 5256402353 ps
CPU time 48.39 seconds
Started Jul 10 06:44:31 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206668 kb
Host smart-2feefd05-daf0-4680-af31-c6210ca0cb82
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1031987263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1031987263
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.981295764
Short name T744
Test name
Test status
Simulation time 161991973 ps
CPU time 0.79 seconds
Started Jul 10 06:44:36 PM PDT 24
Finished Jul 10 06:44:40 PM PDT 24
Peak memory 206396 kb
Host smart-66e41613-753d-47fb-85bc-3d973dacf179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98129
5764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.981295764
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2853377582
Short name T1187
Test name
Test status
Simulation time 186191332 ps
CPU time 0.81 seconds
Started Jul 10 06:44:34 PM PDT 24
Finished Jul 10 06:44:39 PM PDT 24
Peak memory 206400 kb
Host smart-45321775-b688-447f-a50c-279fa2284544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28533
77582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2853377582
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2051096489
Short name T888
Test name
Test status
Simulation time 1089920904 ps
CPU time 2.26 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:39 PM PDT 24
Peak memory 206644 kb
Host smart-43ed4506-4ebe-44c7-b08a-ffe172d7625d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20510
96489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2051096489
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2558466408
Short name T2516
Test name
Test status
Simulation time 7527034174 ps
CPU time 57.47 seconds
Started Jul 10 06:44:30 PM PDT 24
Finished Jul 10 06:45:32 PM PDT 24
Peak memory 206632 kb
Host smart-171558d7-f128-40a9-88ea-d1ff85366834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25584
66408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2558466408
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.142447645
Short name T2030
Test name
Test status
Simulation time 59006737 ps
CPU time 0.71 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:44:46 PM PDT 24
Peak memory 206412 kb
Host smart-c6d98f34-a73f-42cc-8f37-4d1c16116d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=142447645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.142447645
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3468835142
Short name T2235
Test name
Test status
Simulation time 3962493397 ps
CPU time 4.34 seconds
Started Jul 10 06:44:36 PM PDT 24
Finished Jul 10 06:44:44 PM PDT 24
Peak memory 206428 kb
Host smart-d56d33cf-4c7d-44cf-ae58-46463977bede
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3468835142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3468835142
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3364168477
Short name T2494
Test name
Test status
Simulation time 13376992347 ps
CPU time 12.49 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:44:57 PM PDT 24
Peak memory 206444 kb
Host smart-444f1589-0a30-4318-91c5-acfc7d19684f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3364168477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3364168477
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2923480781
Short name T1706
Test name
Test status
Simulation time 23480976673 ps
CPU time 25.41 seconds
Started Jul 10 06:44:35 PM PDT 24
Finished Jul 10 06:45:04 PM PDT 24
Peak memory 206720 kb
Host smart-6e4b3880-a9f2-49ea-ba9c-22f970b32622
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2923480781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.2923480781
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.4166579444
Short name T1559
Test name
Test status
Simulation time 167566445 ps
CPU time 0.81 seconds
Started Jul 10 06:44:33 PM PDT 24
Finished Jul 10 06:44:38 PM PDT 24
Peak memory 206380 kb
Host smart-f12df7f3-532b-4489-b104-bcecee887964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41665
79444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.4166579444
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2835996029
Short name T2205
Test name
Test status
Simulation time 185924236 ps
CPU time 0.84 seconds
Started Jul 10 06:44:32 PM PDT 24
Finished Jul 10 06:44:37 PM PDT 24
Peak memory 206400 kb
Host smart-b0ed2142-1647-4995-abcb-dcd04d48c3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28359
96029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2835996029
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.328736992
Short name T1860
Test name
Test status
Simulation time 314581116 ps
CPU time 1.18 seconds
Started Jul 10 06:44:30 PM PDT 24
Finished Jul 10 06:44:35 PM PDT 24
Peak memory 206372 kb
Host smart-08d2b6cb-52fe-4315-9da0-ee52c48b6de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32873
6992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.328736992
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1925469817
Short name T759
Test name
Test status
Simulation time 878364741 ps
CPU time 2.3 seconds
Started Jul 10 06:44:29 PM PDT 24
Finished Jul 10 06:44:36 PM PDT 24
Peak memory 206576 kb
Host smart-c7df26de-35ed-4fba-b48e-f51f991febd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19254
69817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1925469817
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3921121471
Short name T887
Test name
Test status
Simulation time 18129228448 ps
CPU time 32.54 seconds
Started Jul 10 06:44:36 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206728 kb
Host smart-9346af17-a824-406f-8c76-2cbe03a4b223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39211
21471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3921121471
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2538134908
Short name T2724
Test name
Test status
Simulation time 387500250 ps
CPU time 1.21 seconds
Started Jul 10 06:44:33 PM PDT 24
Finished Jul 10 06:44:39 PM PDT 24
Peak memory 206376 kb
Host smart-8d459c95-03bf-43ea-b71f-a326d629da2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25381
34908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2538134908
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1896773613
Short name T1374
Test name
Test status
Simulation time 152715071 ps
CPU time 0.81 seconds
Started Jul 10 06:44:35 PM PDT 24
Finished Jul 10 06:44:40 PM PDT 24
Peak memory 206372 kb
Host smart-def1410b-efdb-4438-93bd-d25b50dd6fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18967
73613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1896773613
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2181188434
Short name T2183
Test name
Test status
Simulation time 39293051 ps
CPU time 0.66 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:44:49 PM PDT 24
Peak memory 206228 kb
Host smart-3a0b8355-df04-4390-8f3e-f10969bb67e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21811
88434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2181188434
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1832693471
Short name T1632
Test name
Test status
Simulation time 1051829591 ps
CPU time 2.42 seconds
Started Jul 10 06:44:41 PM PDT 24
Finished Jul 10 06:44:45 PM PDT 24
Peak memory 206624 kb
Host smart-396d2896-3918-43c2-9e5d-fa0777b372b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18326
93471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1832693471
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.145729456
Short name T1909
Test name
Test status
Simulation time 203973804 ps
CPU time 1.42 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:44:45 PM PDT 24
Peak memory 206584 kb
Host smart-d36bb06c-b854-4709-853a-9d891ad4185b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14572
9456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.145729456
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.17108036
Short name T2614
Test name
Test status
Simulation time 262766220 ps
CPU time 0.89 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:44:45 PM PDT 24
Peak memory 206376 kb
Host smart-42748715-805c-445d-8277-4e3a95c9c133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17108
036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.17108036
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3480242402
Short name T2065
Test name
Test status
Simulation time 165294261 ps
CPU time 0.8 seconds
Started Jul 10 06:44:40 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 206364 kb
Host smart-3505aef1-af88-4593-bd4b-6a9b82ab6544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
42402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3480242402
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3549822421
Short name T510
Test name
Test status
Simulation time 222671528 ps
CPU time 0.95 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:44:46 PM PDT 24
Peak memory 206372 kb
Host smart-d5b5c3ff-5a53-485a-b7ab-fd17a4b030e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35498
22421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3549822421
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1986445542
Short name T2406
Test name
Test status
Simulation time 7707215019 ps
CPU time 74.3 seconds
Started Jul 10 06:44:41 PM PDT 24
Finished Jul 10 06:45:57 PM PDT 24
Peak memory 206688 kb
Host smart-e954cded-fb16-4c52-bb91-1da36322c66a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1986445542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1986445542
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.824916077
Short name T1742
Test name
Test status
Simulation time 5346708779 ps
CPU time 20.18 seconds
Started Jul 10 06:44:41 PM PDT 24
Finished Jul 10 06:45:03 PM PDT 24
Peak memory 206612 kb
Host smart-fd1661b1-67bf-4be9-95d7-cf62f9aba6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82491
6077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.824916077
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.4102402311
Short name T1963
Test name
Test status
Simulation time 219426760 ps
CPU time 0.9 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 206392 kb
Host smart-763e9a40-76f3-4376-8d96-6948ffa59831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41024
02311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.4102402311
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1351734605
Short name T1999
Test name
Test status
Simulation time 23264643721 ps
CPU time 25.29 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:45:10 PM PDT 24
Peak memory 206444 kb
Host smart-8659fa53-3fff-4439-b411-b9b239e24d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13517
34605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1351734605
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.828963139
Short name T333
Test name
Test status
Simulation time 3317131666 ps
CPU time 3.85 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:44:48 PM PDT 24
Peak memory 206460 kb
Host smart-29a88da3-2b9a-4fbe-9b79-4114d8e4efd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82896
3139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.828963139
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2973359893
Short name T1130
Test name
Test status
Simulation time 12901378595 ps
CPU time 124.14 seconds
Started Jul 10 06:44:40 PM PDT 24
Finished Jul 10 06:46:46 PM PDT 24
Peak memory 206704 kb
Host smart-f3e34e27-ce48-4897-99ba-08f990e88745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29733
59893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2973359893
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2412632606
Short name T5
Test name
Test status
Simulation time 3367776366 ps
CPU time 90.74 seconds
Started Jul 10 06:44:47 PM PDT 24
Finished Jul 10 06:46:26 PM PDT 24
Peak memory 206676 kb
Host smart-9c27aa9d-8ea5-4c23-b4fe-a599e93685bc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2412632606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2412632606
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3006411682
Short name T2682
Test name
Test status
Simulation time 287813853 ps
CPU time 1 seconds
Started Jul 10 06:44:44 PM PDT 24
Finished Jul 10 06:44:47 PM PDT 24
Peak memory 206376 kb
Host smart-1d88318b-a988-400d-b6c9-e42504869993
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3006411682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3006411682
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3601752226
Short name T1356
Test name
Test status
Simulation time 210956208 ps
CPU time 0.95 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:44:46 PM PDT 24
Peak memory 206364 kb
Host smart-59ccfe2c-6015-47ff-a425-01e1b00f04de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36017
52226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3601752226
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.168296838
Short name T1879
Test name
Test status
Simulation time 6770802986 ps
CPU time 65.87 seconds
Started Jul 10 06:44:44 PM PDT 24
Finished Jul 10 06:45:52 PM PDT 24
Peak memory 206720 kb
Host smart-429ad22e-38dd-47dc-9d04-7d16414fd20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16829
6838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.168296838
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.82146891
Short name T1251
Test name
Test status
Simulation time 4336491463 ps
CPU time 32.07 seconds
Started Jul 10 06:44:48 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206660 kb
Host smart-35ad4632-1d25-4d7a-8c13-b0bc3a6d0ac2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=82146891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.82146891
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3604217489
Short name T1204
Test name
Test status
Simulation time 162519957 ps
CPU time 0.84 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:44:44 PM PDT 24
Peak memory 206376 kb
Host smart-5b38bf88-e089-437a-a433-e7c4c6bff0d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3604217489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3604217489
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.951342881
Short name T928
Test name
Test status
Simulation time 152516940 ps
CPU time 0.76 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:44:45 PM PDT 24
Peak memory 206564 kb
Host smart-4fa14924-b986-4aff-8b54-4f321279e77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95134
2881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.951342881
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2874543755
Short name T124
Test name
Test status
Simulation time 211420895 ps
CPU time 0.87 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 206364 kb
Host smart-c53f50c2-55ce-417d-b83a-87769ea753b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745
43755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2874543755
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1100146744
Short name T952
Test name
Test status
Simulation time 167813325 ps
CPU time 0.79 seconds
Started Jul 10 06:44:44 PM PDT 24
Finished Jul 10 06:44:47 PM PDT 24
Peak memory 206372 kb
Host smart-b4f4197b-d73c-4a41-94d1-47faeda40baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11001
46744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1100146744
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.623904445
Short name T413
Test name
Test status
Simulation time 193186811 ps
CPU time 0.85 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 206388 kb
Host smart-9c11afeb-fbb6-4009-a4df-1aad75bc1364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62390
4445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.623904445
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.792398905
Short name T1652
Test name
Test status
Simulation time 209721386 ps
CPU time 0.86 seconds
Started Jul 10 06:44:47 PM PDT 24
Finished Jul 10 06:44:51 PM PDT 24
Peak memory 206328 kb
Host smart-dbeda957-071f-4dd6-863e-b6baae26108f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79239
8905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.792398905
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.799236647
Short name T1864
Test name
Test status
Simulation time 162149921 ps
CPU time 0.79 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:44:44 PM PDT 24
Peak memory 206316 kb
Host smart-bb198fa4-1dbb-4426-8c11-ea8862185333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79923
6647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.799236647
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.1889810756
Short name T1702
Test name
Test status
Simulation time 245893608 ps
CPU time 1.02 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:44:48 PM PDT 24
Peak memory 206380 kb
Host smart-9cd1e067-f303-4a83-bf7b-ab6f89b72089
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1889810756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1889810756
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.508564103
Short name T2726
Test name
Test status
Simulation time 136262803 ps
CPU time 0.77 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 206384 kb
Host smart-50946132-90a4-46e3-ac56-de80f1dfc35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50856
4103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.508564103
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3114810948
Short name T33
Test name
Test status
Simulation time 61944493 ps
CPU time 0.67 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:44:44 PM PDT 24
Peak memory 206368 kb
Host smart-2a836c23-aa41-45d0-b614-5127d6ce1729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31148
10948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3114810948
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.82591564
Short name T1765
Test name
Test status
Simulation time 17229326745 ps
CPU time 40.6 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:45:26 PM PDT 24
Peak memory 206720 kb
Host smart-e8e4c1f1-175d-4e5d-a43b-e642c1994688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82591
564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.82591564
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.375312471
Short name T1497
Test name
Test status
Simulation time 174187843 ps
CPU time 0.87 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 206380 kb
Host smart-2112fc9d-0114-4d0a-abfa-2e90617f5790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37531
2471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.375312471
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3866687298
Short name T1933
Test name
Test status
Simulation time 222114843 ps
CPU time 0.93 seconds
Started Jul 10 06:44:40 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 206348 kb
Host smart-d0daf278-b710-43f1-9cf8-c10e6226ceb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38666
87298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3866687298
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3865670831
Short name T673
Test name
Test status
Simulation time 255827785 ps
CPU time 0.89 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:44:45 PM PDT 24
Peak memory 206556 kb
Host smart-6c348935-c0e7-451a-beac-6160d2c61848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38656
70831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3865670831
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1173841774
Short name T917
Test name
Test status
Simulation time 151364835 ps
CPU time 0.78 seconds
Started Jul 10 06:44:51 PM PDT 24
Finished Jul 10 06:44:53 PM PDT 24
Peak memory 206404 kb
Host smart-db964d7a-8d3b-48ca-a6ab-e279a826fe8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11738
41774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1173841774
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3357565666
Short name T2684
Test name
Test status
Simulation time 180041811 ps
CPU time 0.88 seconds
Started Jul 10 06:44:41 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 206272 kb
Host smart-9e1d534c-af32-4ac2-94f5-db24c3dbcc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33575
65666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3357565666
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2582613237
Short name T1340
Test name
Test status
Simulation time 143525189 ps
CPU time 0.81 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 206392 kb
Host smart-63012104-778a-4adc-b08c-967ae9d33a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25826
13237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2582613237
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2694416972
Short name T455
Test name
Test status
Simulation time 156707958 ps
CPU time 0.81 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 206376 kb
Host smart-904d1896-7648-487b-a5e6-5906d3af8052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26944
16972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2694416972
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1803088691
Short name T2198
Test name
Test status
Simulation time 230992262 ps
CPU time 0.97 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:44:47 PM PDT 24
Peak memory 206376 kb
Host smart-2270d23d-2af1-4944-b759-5d5e993e445f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18030
88691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1803088691
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2408255024
Short name T351
Test name
Test status
Simulation time 4853978590 ps
CPU time 32.24 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:45:16 PM PDT 24
Peak memory 206612 kb
Host smart-271c496d-ee03-4da2-a7d1-3c6e61307567
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2408255024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2408255024
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2131434551
Short name T1539
Test name
Test status
Simulation time 167853122 ps
CPU time 0.76 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:44:45 PM PDT 24
Peak memory 206384 kb
Host smart-17e3e84d-0699-4aea-a09a-048e30611b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21314
34551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2131434551
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2496064323
Short name T1984
Test name
Test status
Simulation time 215267638 ps
CPU time 0.87 seconds
Started Jul 10 06:44:44 PM PDT 24
Finished Jul 10 06:44:48 PM PDT 24
Peak memory 206384 kb
Host smart-f2a6911a-a811-4267-ab96-f313c60ae91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
64323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2496064323
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.3441388175
Short name T1527
Test name
Test status
Simulation time 1238631850 ps
CPU time 2.53 seconds
Started Jul 10 06:44:41 PM PDT 24
Finished Jul 10 06:44:45 PM PDT 24
Peak memory 206636 kb
Host smart-02dd7fb2-5e99-40f0-b31d-4e4bb0342aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34413
88175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.3441388175
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3727957529
Short name T2129
Test name
Test status
Simulation time 3920339449 ps
CPU time 28.86 seconds
Started Jul 10 06:44:42 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206616 kb
Host smart-0188cfa6-e74c-4c2d-9024-5e4e0ff2df0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37279
57529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3727957529
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.2635681754
Short name T1197
Test name
Test status
Simulation time 130107100 ps
CPU time 0.79 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:45:05 PM PDT 24
Peak memory 206428 kb
Host smart-9205b478-4aaa-4481-a5df-7ecc94ed7b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2635681754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.2635681754
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3033117127
Short name T2197
Test name
Test status
Simulation time 3569524942 ps
CPU time 4.01 seconds
Started Jul 10 06:44:48 PM PDT 24
Finished Jul 10 06:44:55 PM PDT 24
Peak memory 206444 kb
Host smart-6d1b31c2-3234-4eb3-bb8c-82864dcb1052
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3033117127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.3033117127
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.4023181798
Short name T2677
Test name
Test status
Simulation time 13403556714 ps
CPU time 12.71 seconds
Started Jul 10 06:44:47 PM PDT 24
Finished Jul 10 06:45:03 PM PDT 24
Peak memory 206712 kb
Host smart-9f982864-f656-4ed0-8091-7cc61ac16c2c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4023181798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.4023181798
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3960576101
Short name T1315
Test name
Test status
Simulation time 23381743788 ps
CPU time 24.99 seconds
Started Jul 10 06:44:49 PM PDT 24
Finished Jul 10 06:45:16 PM PDT 24
Peak memory 206460 kb
Host smart-37151081-9994-4172-a16e-639806a0c49b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3960576101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.3960576101
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.186727558
Short name T1184
Test name
Test status
Simulation time 162035961 ps
CPU time 0.8 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:51 PM PDT 24
Peak memory 206284 kb
Host smart-2114facc-7a04-4d2f-802e-369a1331cc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672
7558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.186727558
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3254642721
Short name T1624
Test name
Test status
Simulation time 174255563 ps
CPU time 0.81 seconds
Started Jul 10 06:44:47 PM PDT 24
Finished Jul 10 06:44:51 PM PDT 24
Peak memory 206392 kb
Host smart-7c11c624-ad3f-41f9-b5b6-abd686bf09af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32546
42721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3254642721
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.4193545081
Short name T1049
Test name
Test status
Simulation time 258841133 ps
CPU time 1.02 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 206392 kb
Host smart-8e36e44a-eba3-4963-b26b-972dcb3318aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41935
45081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.4193545081
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2203308124
Short name T923
Test name
Test status
Simulation time 772344578 ps
CPU time 1.85 seconds
Started Jul 10 06:44:44 PM PDT 24
Finished Jul 10 06:44:48 PM PDT 24
Peak memory 206596 kb
Host smart-e9f15937-d911-4932-b445-d10758dd1652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22033
08124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2203308124
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1899865640
Short name T2441
Test name
Test status
Simulation time 15407218659 ps
CPU time 28.42 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:45:16 PM PDT 24
Peak memory 206696 kb
Host smart-692adf01-30d3-429a-9e9c-669fb73033b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18998
65640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1899865640
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1822017867
Short name T2035
Test name
Test status
Simulation time 442448044 ps
CPU time 1.41 seconds
Started Jul 10 06:44:41 PM PDT 24
Finished Jul 10 06:44:44 PM PDT 24
Peak memory 206384 kb
Host smart-1ed70091-cd34-4c4a-b9a3-7cd2e586bb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18220
17867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1822017867
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2774605950
Short name T970
Test name
Test status
Simulation time 181965654 ps
CPU time 0.8 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:51 PM PDT 24
Peak memory 206312 kb
Host smart-827c3974-53bc-4b73-bb55-96aac157efff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27746
05950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2774605950
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1126201877
Short name T1080
Test name
Test status
Simulation time 38722061 ps
CPU time 0.7 seconds
Started Jul 10 06:44:49 PM PDT 24
Finished Jul 10 06:44:52 PM PDT 24
Peak memory 206392 kb
Host smart-2dbd90c3-9f8d-4b28-b59c-da1cb317a5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11262
01877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1126201877
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2185910003
Short name T1420
Test name
Test status
Simulation time 888047481 ps
CPU time 2.21 seconds
Started Jul 10 06:44:49 PM PDT 24
Finished Jul 10 06:44:54 PM PDT 24
Peak memory 206624 kb
Host smart-e43cada3-9653-40fe-b171-b5ecabac757e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21859
10003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2185910003
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2333547422
Short name T815
Test name
Test status
Simulation time 275485057 ps
CPU time 1.91 seconds
Started Jul 10 06:44:46 PM PDT 24
Finished Jul 10 06:44:52 PM PDT 24
Peak memory 206648 kb
Host smart-484f67ec-2b20-46cd-a24f-f0674b05f034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23335
47422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2333547422
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3350973175
Short name T1736
Test name
Test status
Simulation time 152473649 ps
CPU time 0.81 seconds
Started Jul 10 06:44:47 PM PDT 24
Finished Jul 10 06:44:51 PM PDT 24
Peak memory 206360 kb
Host smart-1f007fa1-7c6b-494f-83cb-e3fdfa302839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33509
73175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3350973175
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1495913670
Short name T1919
Test name
Test status
Simulation time 162097557 ps
CPU time 0.78 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:44:49 PM PDT 24
Peak memory 206360 kb
Host smart-6df14051-0c57-4e6f-b696-7e1ebdd96536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14959
13670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1495913670
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2806417481
Short name T1828
Test name
Test status
Simulation time 237839095 ps
CPU time 0.91 seconds
Started Jul 10 06:44:45 PM PDT 24
Finished Jul 10 06:44:49 PM PDT 24
Peak memory 206360 kb
Host smart-15532593-2d51-4c0a-89a8-f7ab22c9c425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
17481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2806417481
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.3962196630
Short name T1595
Test name
Test status
Simulation time 10064923798 ps
CPU time 96.84 seconds
Started Jul 10 06:44:43 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206624 kb
Host smart-33a6bcd1-cb11-4bdd-a058-fd7a4d6bd832
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3962196630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3962196630
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.3208513734
Short name T2700
Test name
Test status
Simulation time 10261675066 ps
CPU time 33.51 seconds
Started Jul 10 06:44:47 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206692 kb
Host smart-13bdb68a-e738-44a4-a36d-8be3b64a5537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32085
13734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.3208513734
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2691134242
Short name T2617
Test name
Test status
Simulation time 232499092 ps
CPU time 0.95 seconds
Started Jul 10 06:44:55 PM PDT 24
Finished Jul 10 06:44:58 PM PDT 24
Peak memory 206256 kb
Host smart-f9afc2f0-36d8-4416-9690-51e9bceb3509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26911
34242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2691134242
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1867045714
Short name T40
Test name
Test status
Simulation time 23310495645 ps
CPU time 26.29 seconds
Started Jul 10 06:44:52 PM PDT 24
Finished Jul 10 06:45:20 PM PDT 24
Peak memory 206408 kb
Host smart-adf07b67-ea3b-403b-8ead-28ef483bfc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18670
45714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1867045714
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2507749403
Short name T1001
Test name
Test status
Simulation time 3303819158 ps
CPU time 3.88 seconds
Started Jul 10 06:44:52 PM PDT 24
Finished Jul 10 06:44:58 PM PDT 24
Peak memory 206436 kb
Host smart-90dc1f39-dcbf-4e14-922b-997dbf6bd204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077
49403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2507749403
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1962024147
Short name T602
Test name
Test status
Simulation time 9143729171 ps
CPU time 63.47 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:45:59 PM PDT 24
Peak memory 206716 kb
Host smart-bc1952d9-34bf-42b7-9145-e6dc7e7059f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19620
24147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1962024147
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.3311207740
Short name T2584
Test name
Test status
Simulation time 7084419910 ps
CPU time 204.74 seconds
Started Jul 10 06:44:59 PM PDT 24
Finished Jul 10 06:48:24 PM PDT 24
Peak memory 206828 kb
Host smart-9841ff2e-6a97-4db5-a0d3-4232672e9065
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3311207740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.3311207740
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.3788624056
Short name T856
Test name
Test status
Simulation time 241640239 ps
CPU time 0.92 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:44:56 PM PDT 24
Peak memory 206380 kb
Host smart-bd1759cc-2f9c-474e-b8fe-f193a8fc35b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3788624056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3788624056
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.4177034829
Short name T492
Test name
Test status
Simulation time 229363402 ps
CPU time 0.93 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:44:56 PM PDT 24
Peak memory 206360 kb
Host smart-63283f06-355d-49eb-aec8-7991d26ece74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41770
34829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.4177034829
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.2830116283
Short name T1135
Test name
Test status
Simulation time 4665123680 ps
CPU time 126.15 seconds
Started Jul 10 06:44:56 PM PDT 24
Finished Jul 10 06:47:03 PM PDT 24
Peak memory 206548 kb
Host smart-d2f32108-3e13-4b4f-bbdf-8c6cb5da4d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28301
16283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.2830116283
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.226278007
Short name T1555
Test name
Test status
Simulation time 3433042609 ps
CPU time 25.63 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206684 kb
Host smart-57664d25-98c9-42f0-8d7e-8d0de179b16f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=226278007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.226278007
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.1732131463
Short name T453
Test name
Test status
Simulation time 158794494 ps
CPU time 0.78 seconds
Started Jul 10 06:44:57 PM PDT 24
Finished Jul 10 06:44:59 PM PDT 24
Peak memory 206332 kb
Host smart-735d9b20-36eb-4ecd-87fd-0caa5098d1aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1732131463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1732131463
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3073979288
Short name T1842
Test name
Test status
Simulation time 189011842 ps
CPU time 0.87 seconds
Started Jul 10 06:44:57 PM PDT 24
Finished Jul 10 06:44:59 PM PDT 24
Peak memory 206396 kb
Host smart-61634048-eafc-4f83-a95e-05afeeb793f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30739
79288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3073979288
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3426235217
Short name T133
Test name
Test status
Simulation time 219503261 ps
CPU time 0.89 seconds
Started Jul 10 06:44:57 PM PDT 24
Finished Jul 10 06:44:59 PM PDT 24
Peak memory 206384 kb
Host smart-19542de1-ffe2-413f-a53e-3ee541bbb7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34262
35217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3426235217
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2787722590
Short name T557
Test name
Test status
Simulation time 181659371 ps
CPU time 0.86 seconds
Started Jul 10 06:44:52 PM PDT 24
Finished Jul 10 06:44:54 PM PDT 24
Peak memory 206376 kb
Host smart-f51e6802-7c09-40f3-ba9b-30aecc587a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
22590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2787722590
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3238287464
Short name T816
Test name
Test status
Simulation time 172695953 ps
CPU time 0.81 seconds
Started Jul 10 06:44:51 PM PDT 24
Finished Jul 10 06:44:54 PM PDT 24
Peak memory 206396 kb
Host smart-0bbecb53-d606-4df9-bfa3-c25dc580dad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32382
87464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3238287464
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1925069421
Short name T1219
Test name
Test status
Simulation time 165305788 ps
CPU time 0.86 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:44:55 PM PDT 24
Peak memory 206360 kb
Host smart-fb75006e-6013-43f8-86e8-5aeb35722083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19250
69421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1925069421
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3096445112
Short name T2421
Test name
Test status
Simulation time 153352520 ps
CPU time 0.83 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:44:56 PM PDT 24
Peak memory 206396 kb
Host smart-baaf5517-9192-41d3-889b-9fcada0d907d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30964
45112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3096445112
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1984452658
Short name T2298
Test name
Test status
Simulation time 206526333 ps
CPU time 0.9 seconds
Started Jul 10 06:44:54 PM PDT 24
Finished Jul 10 06:44:57 PM PDT 24
Peak memory 206372 kb
Host smart-f022dbb2-5512-49cf-b04b-77beefa3a736
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1984452658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1984452658
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2730618704
Short name T2106
Test name
Test status
Simulation time 140243453 ps
CPU time 0.81 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:44:56 PM PDT 24
Peak memory 206368 kb
Host smart-a4a7cc98-8139-4ee8-9093-896695fcc082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27306
18704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2730618704
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.440891694
Short name T1171
Test name
Test status
Simulation time 77582294 ps
CPU time 0.7 seconds
Started Jul 10 06:44:52 PM PDT 24
Finished Jul 10 06:44:54 PM PDT 24
Peak memory 206384 kb
Host smart-d10ac0dd-528f-4a88-bbc5-715ac9fce131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44089
1694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.440891694
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1715872211
Short name T1362
Test name
Test status
Simulation time 15003764320 ps
CPU time 35.96 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:45:31 PM PDT 24
Peak memory 206676 kb
Host smart-11254fe4-c177-4ade-a092-98558db098d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17158
72211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1715872211
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1448346631
Short name T1501
Test name
Test status
Simulation time 175672647 ps
CPU time 0.81 seconds
Started Jul 10 06:44:58 PM PDT 24
Finished Jul 10 06:45:00 PM PDT 24
Peak memory 206384 kb
Host smart-6dd82e63-ec7f-48f2-b0a4-f29cd149f234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14483
46631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1448346631
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2919009277
Short name T2274
Test name
Test status
Simulation time 188104790 ps
CPU time 0.85 seconds
Started Jul 10 06:44:55 PM PDT 24
Finished Jul 10 06:44:57 PM PDT 24
Peak memory 206388 kb
Host smart-52e6b8df-fc3a-4976-97cf-5c29bc7074ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29190
09277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2919009277
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2113417699
Short name T1068
Test name
Test status
Simulation time 167343800 ps
CPU time 0.84 seconds
Started Jul 10 06:44:58 PM PDT 24
Finished Jul 10 06:44:59 PM PDT 24
Peak memory 206392 kb
Host smart-7e106b95-c56a-4e73-9ecc-348644e2e698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21134
17699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2113417699
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.997787943
Short name T971
Test name
Test status
Simulation time 141404708 ps
CPU time 0.78 seconds
Started Jul 10 06:44:56 PM PDT 24
Finished Jul 10 06:44:58 PM PDT 24
Peak memory 206368 kb
Host smart-306c1fbf-6430-46a0-bacf-f62ec1d9eead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99778
7943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.997787943
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1415438066
Short name T901
Test name
Test status
Simulation time 159362236 ps
CPU time 0.78 seconds
Started Jul 10 06:44:52 PM PDT 24
Finished Jul 10 06:44:54 PM PDT 24
Peak memory 206364 kb
Host smart-f2327be3-bf24-4659-a3dc-4fefc02083f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154
38066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1415438066
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2111812639
Short name T951
Test name
Test status
Simulation time 166842922 ps
CPU time 0.78 seconds
Started Jul 10 06:44:53 PM PDT 24
Finished Jul 10 06:44:56 PM PDT 24
Peak memory 206388 kb
Host smart-1ff48efb-f95c-4e07-b8d3-a58276b3707c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21118
12639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2111812639
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1162131257
Short name T2490
Test name
Test status
Simulation time 157304624 ps
CPU time 0.79 seconds
Started Jul 10 06:44:54 PM PDT 24
Finished Jul 10 06:44:56 PM PDT 24
Peak memory 206376 kb
Host smart-578e0f65-b9b5-4574-b5a8-7f545d729f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11621
31257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1162131257
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.622249587
Short name T662
Test name
Test status
Simulation time 255612215 ps
CPU time 1.03 seconds
Started Jul 10 06:44:55 PM PDT 24
Finished Jul 10 06:44:58 PM PDT 24
Peak memory 206376 kb
Host smart-0d9a83f4-26cd-4129-99cd-49ee0814e49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62224
9587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.622249587
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3986937055
Short name T166
Test name
Test status
Simulation time 5885659867 ps
CPU time 55.92 seconds
Started Jul 10 06:44:54 PM PDT 24
Finished Jul 10 06:45:52 PM PDT 24
Peak memory 206664 kb
Host smart-03ad17c0-cd57-43b4-be07-fa0774e2ad70
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3986937055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3986937055
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3817848688
Short name T1798
Test name
Test status
Simulation time 171087710 ps
CPU time 0.77 seconds
Started Jul 10 06:44:52 PM PDT 24
Finished Jul 10 06:44:55 PM PDT 24
Peak memory 206384 kb
Host smart-9c7d708d-789d-4ea1-ac75-c338e499c8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38178
48688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3817848688
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2354778170
Short name T947
Test name
Test status
Simulation time 147690661 ps
CPU time 0.77 seconds
Started Jul 10 06:45:01 PM PDT 24
Finished Jul 10 06:45:04 PM PDT 24
Peak memory 206376 kb
Host smart-4867ba6b-d361-4eb5-a969-7edf00996ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
78170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2354778170
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1345842638
Short name T464
Test name
Test status
Simulation time 1320592984 ps
CPU time 3.1 seconds
Started Jul 10 06:45:05 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206616 kb
Host smart-5614b484-36bf-4b77-981b-e5b6a48cb703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13458
42638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1345842638
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1662806012
Short name T2039
Test name
Test status
Simulation time 4594809930 ps
CPU time 43.11 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:45:48 PM PDT 24
Peak memory 206716 kb
Host smart-56ccf2a9-d307-4bbd-a291-5a22cbc0519e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16628
06012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1662806012
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3569151080
Short name T756
Test name
Test status
Simulation time 39687202 ps
CPU time 0.66 seconds
Started Jul 10 06:45:11 PM PDT 24
Finished Jul 10 06:45:16 PM PDT 24
Peak memory 206420 kb
Host smart-5532742a-9c94-4f2d-b12b-fbbcb0c9feee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3569151080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3569151080
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1713297697
Short name T969
Test name
Test status
Simulation time 3719942654 ps
CPU time 4.14 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:19 PM PDT 24
Peak memory 206492 kb
Host smart-baff0ddf-7692-48fa-8594-931af7cab89e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1713297697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1713297697
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3775456019
Short name T1641
Test name
Test status
Simulation time 13395693482 ps
CPU time 13.57 seconds
Started Jul 10 06:45:04 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206688 kb
Host smart-9fb631e9-9d2d-48fa-9c0e-ee4171c310a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3775456019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3775456019
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.960277787
Short name T869
Test name
Test status
Simulation time 23441048616 ps
CPU time 26.21 seconds
Started Jul 10 06:45:01 PM PDT 24
Finished Jul 10 06:45:30 PM PDT 24
Peak memory 206664 kb
Host smart-65f980b7-cd73-40fa-88fc-faba0316d401
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=960277787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.960277787
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1728720056
Short name T725
Test name
Test status
Simulation time 181327295 ps
CPU time 0.83 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:45:06 PM PDT 24
Peak memory 206384 kb
Host smart-4ae674c3-6584-46c2-8a03-490912922cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
20056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1728720056
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1593561335
Short name T1581
Test name
Test status
Simulation time 146818057 ps
CPU time 0.77 seconds
Started Jul 10 06:45:04 PM PDT 24
Finished Jul 10 06:45:09 PM PDT 24
Peak memory 206380 kb
Host smart-4dd26d7c-7037-4067-bdc1-c0f15b7a170e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15935
61335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1593561335
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3608806791
Short name T1432
Test name
Test status
Simulation time 411621241 ps
CPU time 1.3 seconds
Started Jul 10 06:45:00 PM PDT 24
Finished Jul 10 06:45:03 PM PDT 24
Peak memory 206380 kb
Host smart-80b90489-8a50-474a-95eb-884337dc5544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36088
06791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3608806791
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1859465960
Short name T1858
Test name
Test status
Simulation time 1116423024 ps
CPU time 2.77 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:45:07 PM PDT 24
Peak memory 206524 kb
Host smart-f97c266b-68d8-4632-8cc0-e5873b60c85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18594
65960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1859465960
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2271037266
Short name T2155
Test name
Test status
Simulation time 20132582613 ps
CPU time 39.11 seconds
Started Jul 10 06:45:00 PM PDT 24
Finished Jul 10 06:45:41 PM PDT 24
Peak memory 206568 kb
Host smart-f24d48ce-2222-4796-83a3-04a34257a4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22710
37266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2271037266
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.886588234
Short name T2732
Test name
Test status
Simulation time 477386179 ps
CPU time 1.33 seconds
Started Jul 10 06:45:03 PM PDT 24
Finished Jul 10 06:45:08 PM PDT 24
Peak memory 206384 kb
Host smart-fb63ca6e-4b80-4f2c-af4a-8c066158a170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88658
8234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.886588234
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.707140282
Short name T2627
Test name
Test status
Simulation time 143406428 ps
CPU time 0.79 seconds
Started Jul 10 06:45:07 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206392 kb
Host smart-5b58ed11-9886-49ed-bb26-7fb144094585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70714
0282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.707140282
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2872263051
Short name T2222
Test name
Test status
Simulation time 39951815 ps
CPU time 0.68 seconds
Started Jul 10 06:45:00 PM PDT 24
Finished Jul 10 06:45:02 PM PDT 24
Peak memory 206364 kb
Host smart-a6072ab0-266e-4c20-baa5-9e5dfe65ffcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28722
63051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2872263051
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.157495425
Short name T1341
Test name
Test status
Simulation time 834182500 ps
CPU time 1.95 seconds
Started Jul 10 06:45:05 PM PDT 24
Finished Jul 10 06:45:11 PM PDT 24
Peak memory 206576 kb
Host smart-ce9fe1ca-80fd-4802-94a5-848e85db1060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15749
5425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.157495425
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1890393510
Short name T663
Test name
Test status
Simulation time 179239043 ps
CPU time 1.2 seconds
Started Jul 10 06:45:01 PM PDT 24
Finished Jul 10 06:45:05 PM PDT 24
Peak memory 206588 kb
Host smart-0ef14798-0cb9-43d4-ae4d-ab0a2c474055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18903
93510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1890393510
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3639413918
Short name T410
Test name
Test status
Simulation time 236536269 ps
CPU time 0.95 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206208 kb
Host smart-abfd5e08-aa08-4a85-9042-a1cb6fb48901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36394
13918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3639413918
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2715020146
Short name T2218
Test name
Test status
Simulation time 168638305 ps
CPU time 0.81 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206372 kb
Host smart-4fc06aa3-b739-47ff-83e8-1d55f8f60cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27150
20146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2715020146
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3813711175
Short name T1743
Test name
Test status
Simulation time 204130557 ps
CPU time 0.89 seconds
Started Jul 10 06:45:01 PM PDT 24
Finished Jul 10 06:45:05 PM PDT 24
Peak memory 206364 kb
Host smart-22451d57-8ba0-49b6-bce5-0250bb1ac846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137
11175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3813711175
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1153804846
Short name T643
Test name
Test status
Simulation time 193564764 ps
CPU time 0.83 seconds
Started Jul 10 06:44:59 PM PDT 24
Finished Jul 10 06:45:01 PM PDT 24
Peak memory 206368 kb
Host smart-1f383dd1-b47e-4010-8b7f-6b58ce7f83ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11538
04846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1153804846
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.2223044361
Short name T1979
Test name
Test status
Simulation time 23375196869 ps
CPU time 25.44 seconds
Started Jul 10 06:45:04 PM PDT 24
Finished Jul 10 06:45:33 PM PDT 24
Peak memory 206436 kb
Host smart-eec58e31-78d4-428d-99dd-c73cd404b99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22230
44361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.2223044361
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1182572412
Short name T1024
Test name
Test status
Simulation time 3273501551 ps
CPU time 5.09 seconds
Started Jul 10 06:44:59 PM PDT 24
Finished Jul 10 06:45:05 PM PDT 24
Peak memory 206452 kb
Host smart-3562b691-b626-4a4a-938b-66a939419fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11825
72412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1182572412
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2774636808
Short name T1319
Test name
Test status
Simulation time 6819419169 ps
CPU time 186.76 seconds
Started Jul 10 06:45:05 PM PDT 24
Finished Jul 10 06:48:16 PM PDT 24
Peak memory 206736 kb
Host smart-5051fb00-0fe0-4c5b-9b81-f26b4999c60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27746
36808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2774636808
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2153692377
Short name T2001
Test name
Test status
Simulation time 7202485831 ps
CPU time 206.09 seconds
Started Jul 10 06:45:03 PM PDT 24
Finished Jul 10 06:48:33 PM PDT 24
Peak memory 206636 kb
Host smart-19ee2a59-b0d9-45f8-b2da-978aa5150a16
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2153692377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2153692377
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.413293425
Short name T635
Test name
Test status
Simulation time 328523481 ps
CPU time 1.08 seconds
Started Jul 10 06:45:03 PM PDT 24
Finished Jul 10 06:45:07 PM PDT 24
Peak memory 206364 kb
Host smart-cfd9ee1a-920e-4617-8e47-3ecf91577c3b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=413293425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.413293425
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3079657330
Short name T538
Test name
Test status
Simulation time 197674671 ps
CPU time 0.9 seconds
Started Jul 10 06:45:03 PM PDT 24
Finished Jul 10 06:45:07 PM PDT 24
Peak memory 206396 kb
Host smart-1bf96c2f-c919-405d-a8df-d3ab3501ca87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30796
57330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3079657330
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.775934793
Short name T1513
Test name
Test status
Simulation time 6730013295 ps
CPU time 44.5 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:45:49 PM PDT 24
Peak memory 206596 kb
Host smart-7c5b951a-23db-4085-864c-7c08c135da5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77593
4793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.775934793
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2978919942
Short name T589
Test name
Test status
Simulation time 5365611837 ps
CPU time 137.28 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:47:21 PM PDT 24
Peak memory 206660 kb
Host smart-9f2369ed-7623-460d-963f-50ad41696209
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2978919942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2978919942
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2833028950
Short name T2395
Test name
Test status
Simulation time 156004236 ps
CPU time 0.83 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:45:05 PM PDT 24
Peak memory 206404 kb
Host smart-a97253b8-abd4-4a91-8701-0318347cb7df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2833028950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2833028950
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.997286330
Short name T687
Test name
Test status
Simulation time 144779522 ps
CPU time 0.81 seconds
Started Jul 10 06:45:00 PM PDT 24
Finished Jul 10 06:45:03 PM PDT 24
Peak memory 206404 kb
Host smart-95dfc3d4-b8ed-4075-b980-67040a50678b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99728
6330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.997286330
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3223983367
Short name T1521
Test name
Test status
Simulation time 229411914 ps
CPU time 0.93 seconds
Started Jul 10 06:45:01 PM PDT 24
Finished Jul 10 06:45:04 PM PDT 24
Peak memory 206320 kb
Host smart-8569bcb4-3d7b-4d86-8527-5513e31cfc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32239
83367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3223983367
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1818328397
Short name T1780
Test name
Test status
Simulation time 179543945 ps
CPU time 0.91 seconds
Started Jul 10 06:45:03 PM PDT 24
Finished Jul 10 06:45:07 PM PDT 24
Peak memory 206356 kb
Host smart-62d15ac1-4382-4b91-ae7d-01a21461d468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
28397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1818328397
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2355496078
Short name T1363
Test name
Test status
Simulation time 192514334 ps
CPU time 0.84 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:45:06 PM PDT 24
Peak memory 206356 kb
Host smart-866e59e8-669b-4ed5-afdb-598a79af575b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
96078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2355496078
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2662541426
Short name T2036
Test name
Test status
Simulation time 177301828 ps
CPU time 0.77 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:17 PM PDT 24
Peak memory 206308 kb
Host smart-235717f1-131a-4c2e-b8ce-36c56fa50e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26625
41426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2662541426
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1504350033
Short name T179
Test name
Test status
Simulation time 199415620 ps
CPU time 0.84 seconds
Started Jul 10 06:45:11 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206384 kb
Host smart-80d612fb-88ca-49a9-b6e8-1e40ffd0e970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15043
50033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1504350033
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2699856645
Short name T2452
Test name
Test status
Simulation time 220695624 ps
CPU time 0.94 seconds
Started Jul 10 06:45:00 PM PDT 24
Finished Jul 10 06:45:02 PM PDT 24
Peak memory 206380 kb
Host smart-eb47027f-02dd-482a-ae6d-fb222ff20f7a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2699856645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2699856645
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.376555312
Short name T2145
Test name
Test status
Simulation time 208770331 ps
CPU time 0.83 seconds
Started Jul 10 06:45:07 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206392 kb
Host smart-5fd4ddb0-5557-45c6-9cd2-208a9e0625e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37655
5312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.376555312
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3102287993
Short name T2427
Test name
Test status
Simulation time 70971259 ps
CPU time 0.71 seconds
Started Jul 10 06:45:02 PM PDT 24
Finished Jul 10 06:45:06 PM PDT 24
Peak memory 206368 kb
Host smart-f42141a4-5f23-45b3-87cd-93e181bfe963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31022
87993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3102287993
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1940133969
Short name T1588
Test name
Test status
Simulation time 21181936496 ps
CPU time 47.85 seconds
Started Jul 10 06:45:09 PM PDT 24
Finished Jul 10 06:46:01 PM PDT 24
Peak memory 206740 kb
Host smart-41116165-a4e0-47ac-af55-3fbd1004dd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19401
33969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1940133969
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3167283288
Short name T2288
Test name
Test status
Simulation time 168867403 ps
CPU time 0.83 seconds
Started Jul 10 06:45:08 PM PDT 24
Finished Jul 10 06:45:13 PM PDT 24
Peak memory 206380 kb
Host smart-58da73a9-71f1-465e-858b-8484b0abe2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31672
83288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3167283288
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3734453273
Short name T1569
Test name
Test status
Simulation time 204886148 ps
CPU time 0.86 seconds
Started Jul 10 06:45:04 PM PDT 24
Finished Jul 10 06:45:09 PM PDT 24
Peak memory 206376 kb
Host smart-83d304f7-bca3-4395-ac05-6a0dfe244f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37344
53273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3734453273
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.120964762
Short name T731
Test name
Test status
Simulation time 163587901 ps
CPU time 0.86 seconds
Started Jul 10 06:45:03 PM PDT 24
Finished Jul 10 06:45:08 PM PDT 24
Peak memory 206392 kb
Host smart-63bd50f0-72c0-4dff-86de-33155d72c2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12096
4762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.120964762
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2359649950
Short name T1418
Test name
Test status
Simulation time 208348013 ps
CPU time 0.92 seconds
Started Jul 10 06:45:01 PM PDT 24
Finished Jul 10 06:45:04 PM PDT 24
Peak memory 206372 kb
Host smart-3b1d58c3-ad35-4043-bba2-4562bca1c871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23596
49950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2359649950
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3998925006
Short name T1358
Test name
Test status
Simulation time 199079871 ps
CPU time 0.84 seconds
Started Jul 10 06:45:05 PM PDT 24
Finished Jul 10 06:45:10 PM PDT 24
Peak memory 206388 kb
Host smart-c1870dde-c21e-410b-9f16-6575b3d548bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39989
25006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3998925006
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.174594033
Short name T2305
Test name
Test status
Simulation time 157478140 ps
CPU time 0.79 seconds
Started Jul 10 06:45:05 PM PDT 24
Finished Jul 10 06:45:10 PM PDT 24
Peak memory 206388 kb
Host smart-b579a45e-49eb-4063-b72a-8ad42cbd4ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17459
4033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.174594033
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1857010878
Short name T2440
Test name
Test status
Simulation time 146446771 ps
CPU time 0.79 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:45:26 PM PDT 24
Peak memory 206376 kb
Host smart-e584d141-45db-4d88-a9aa-0c7ae0d5e962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18570
10878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1857010878
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.467845525
Short name T339
Test name
Test status
Simulation time 235470213 ps
CPU time 1 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:45:20 PM PDT 24
Peak memory 206372 kb
Host smart-3d6ac00c-d974-4c97-bf16-edae33483c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46784
5525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.467845525
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2573708634
Short name T1836
Test name
Test status
Simulation time 3003800747 ps
CPU time 77.37 seconds
Started Jul 10 06:45:11 PM PDT 24
Finished Jul 10 06:46:33 PM PDT 24
Peak memory 206612 kb
Host smart-3db18a3d-4053-4752-98de-fe15066c8bd2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2573708634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2573708634
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2231650955
Short name T1299
Test name
Test status
Simulation time 158483018 ps
CPU time 0.82 seconds
Started Jul 10 06:45:07 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206384 kb
Host smart-2c8870a8-85a0-4eeb-a715-1a14de24edd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22316
50955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2231650955
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1684894527
Short name T2082
Test name
Test status
Simulation time 167125097 ps
CPU time 0.8 seconds
Started Jul 10 06:45:05 PM PDT 24
Finished Jul 10 06:45:10 PM PDT 24
Peak memory 206376 kb
Host smart-c6e89d83-0487-4e7b-bcbc-884260a8018c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16848
94527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1684894527
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1468134476
Short name T313
Test name
Test status
Simulation time 456076064 ps
CPU time 1.3 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:19 PM PDT 24
Peak memory 206356 kb
Host smart-eaba69da-c5fb-449b-9fca-0ddcbc4e509d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14681
34476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1468134476
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3017746222
Short name T2170
Test name
Test status
Simulation time 5057221685 ps
CPU time 35.74 seconds
Started Jul 10 06:45:09 PM PDT 24
Finished Jul 10 06:45:48 PM PDT 24
Peak memory 206688 kb
Host smart-9c86857c-16f0-4f9c-b9cd-0a0c5013ef78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30177
46222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3017746222
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.195007184
Short name T2557
Test name
Test status
Simulation time 35030206 ps
CPU time 0.67 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206428 kb
Host smart-8ca8bca2-a88b-4120-b422-48cfe84f2670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=195007184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.195007184
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.447200210
Short name T1543
Test name
Test status
Simulation time 3487348362 ps
CPU time 4.8 seconds
Started Jul 10 06:45:06 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206688 kb
Host smart-4c32f541-0715-4f0c-adcf-bd6e3a86757c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=447200210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.447200210
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3739898897
Short name T720
Test name
Test status
Simulation time 13356411510 ps
CPU time 11.85 seconds
Started Jul 10 06:45:09 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206720 kb
Host smart-a435c556-6ebb-421f-820b-5f940463698b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3739898897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3739898897
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.622131835
Short name T2384
Test name
Test status
Simulation time 23461194930 ps
CPU time 24.27 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206716 kb
Host smart-6866d0a6-5ccd-4364-946e-74134813b7db
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=622131835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.622131835
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2013909178
Short name T1481
Test name
Test status
Simulation time 151677057 ps
CPU time 0.81 seconds
Started Jul 10 06:45:03 PM PDT 24
Finished Jul 10 06:45:07 PM PDT 24
Peak memory 206368 kb
Host smart-877c7a07-a5b7-4913-acab-1125106386a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
09178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2013909178
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1506525696
Short name T2434
Test name
Test status
Simulation time 153974422 ps
CPU time 0.81 seconds
Started Jul 10 06:45:04 PM PDT 24
Finished Jul 10 06:45:09 PM PDT 24
Peak memory 206396 kb
Host smart-b83d622e-6ad4-48bb-9e3a-b491374f70bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15065
25696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1506525696
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1037427855
Short name T2221
Test name
Test status
Simulation time 158614919 ps
CPU time 0.8 seconds
Started Jul 10 06:45:04 PM PDT 24
Finished Jul 10 06:45:10 PM PDT 24
Peak memory 206392 kb
Host smart-e34884ef-9cc9-4b18-9acc-4eb1f152076a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10374
27855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1037427855
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1275416523
Short name T1870
Test name
Test status
Simulation time 837107902 ps
CPU time 2 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206600 kb
Host smart-35adea3a-ed81-4131-a28e-04f4e1feea4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12754
16523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1275416523
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.166555668
Short name T1290
Test name
Test status
Simulation time 7337934335 ps
CPU time 14.26 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:37 PM PDT 24
Peak memory 206616 kb
Host smart-42582ab8-3b3f-4293-843d-c1f4a097afad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16655
5668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.166555668
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.704162935
Short name T1850
Test name
Test status
Simulation time 507638640 ps
CPU time 1.3 seconds
Started Jul 10 06:45:06 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206396 kb
Host smart-2d8dfb51-421f-45a0-84d8-400f6289c4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70416
2935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.704162935
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3028181116
Short name T441
Test name
Test status
Simulation time 180425812 ps
CPU time 0.83 seconds
Started Jul 10 06:45:05 PM PDT 24
Finished Jul 10 06:45:10 PM PDT 24
Peak memory 206396 kb
Host smart-0d5d0924-be9c-4898-b453-8d0fc4f3217f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30281
81116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3028181116
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.2675293427
Short name T955
Test name
Test status
Simulation time 53281637 ps
CPU time 0.69 seconds
Started Jul 10 06:45:04 PM PDT 24
Finished Jul 10 06:45:08 PM PDT 24
Peak memory 206380 kb
Host smart-6c06f194-a5ef-4cd9-9007-98a1f7436e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26752
93427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2675293427
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3193832921
Short name T2431
Test name
Test status
Simulation time 843516385 ps
CPU time 2.24 seconds
Started Jul 10 06:45:07 PM PDT 24
Finished Jul 10 06:45:13 PM PDT 24
Peak memory 206648 kb
Host smart-3aa1bd06-4cd1-4467-8a71-a4bec393ac89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31938
32921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3193832921
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2371172197
Short name T1293
Test name
Test status
Simulation time 338994804 ps
CPU time 2.07 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206568 kb
Host smart-4b539ac4-d80e-452a-be12-fcd6fd460216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23711
72197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2371172197
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.758225997
Short name T1754
Test name
Test status
Simulation time 182235652 ps
CPU time 0.81 seconds
Started Jul 10 06:45:07 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206388 kb
Host smart-c14bf671-9c26-495c-9cda-b86b9939a212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75822
5997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.758225997
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.579003203
Short name T2712
Test name
Test status
Simulation time 155505119 ps
CPU time 0.75 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206368 kb
Host smart-aa4d177f-f263-4eaa-adbf-f068479c1276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57900
3203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.579003203
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.4211108892
Short name T2567
Test name
Test status
Simulation time 236521951 ps
CPU time 0.97 seconds
Started Jul 10 06:45:07 PM PDT 24
Finished Jul 10 06:45:12 PM PDT 24
Peak memory 206352 kb
Host smart-ebf5c259-a5e0-41d1-82ff-31dced4067dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42111
08892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.4211108892
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3737728384
Short name T218
Test name
Test status
Simulation time 8329401376 ps
CPU time 239.15 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:49:17 PM PDT 24
Peak memory 206648 kb
Host smart-d054db7d-ef06-43bf-8be2-f8f0341251d9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3737728384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3737728384
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.2132917579
Short name T2071
Test name
Test status
Simulation time 10760884640 ps
CPU time 34.52 seconds
Started Jul 10 06:45:06 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206640 kb
Host smart-eef78469-012c-45da-9f3d-1440acc6851e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21329
17579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.2132917579
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1423408121
Short name T1446
Test name
Test status
Simulation time 198006611 ps
CPU time 0.81 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206300 kb
Host smart-6b8c51f9-d448-4dee-a591-a9a1aba09809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234
08121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1423408121
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1347038246
Short name T1486
Test name
Test status
Simulation time 23346574438 ps
CPU time 26.13 seconds
Started Jul 10 06:45:05 PM PDT 24
Finished Jul 10 06:45:35 PM PDT 24
Peak memory 206436 kb
Host smart-eda3fde3-848a-4f44-828d-5e19690c57cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13470
38246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1347038246
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.357837318
Short name T1467
Test name
Test status
Simulation time 3322219789 ps
CPU time 4.68 seconds
Started Jul 10 06:45:06 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206444 kb
Host smart-7a0cba2c-5c4c-4212-985f-c02a79299839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35783
7318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.357837318
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1490989486
Short name T489
Test name
Test status
Simulation time 11073625795 ps
CPU time 106.33 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:47:05 PM PDT 24
Peak memory 206704 kb
Host smart-9da71377-a09e-469e-a939-876d21111cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14909
89486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1490989486
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2959026348
Short name T2368
Test name
Test status
Simulation time 7664821126 ps
CPU time 220.37 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:49:05 PM PDT 24
Peak memory 206572 kb
Host smart-86a18761-1570-4dcd-9069-59b482d2dca0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2959026348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2959026348
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1356882702
Short name T1203
Test name
Test status
Simulation time 240963915 ps
CPU time 0.92 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206392 kb
Host smart-f6c6fcb0-34c3-4a6d-b843-2c8d9e972c02
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1356882702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1356882702
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3813861386
Short name T2072
Test name
Test status
Simulation time 189652225 ps
CPU time 0.85 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:19 PM PDT 24
Peak memory 206312 kb
Host smart-249961b9-69b5-464f-9638-0ff9023d7d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138
61386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3813861386
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2326633897
Short name T153
Test name
Test status
Simulation time 6480306171 ps
CPU time 60.41 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:46:20 PM PDT 24
Peak memory 206720 kb
Host smart-d27be1b0-7329-4615-b6ae-61e9361ee26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23266
33897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2326633897
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.4030293127
Short name T2111
Test name
Test status
Simulation time 3211960493 ps
CPU time 23.29 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206696 kb
Host smart-84a989ab-a4e8-429b-a9f8-9c3030de5e69
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4030293127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.4030293127
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2580793457
Short name T1373
Test name
Test status
Simulation time 164670291 ps
CPU time 0.76 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:22 PM PDT 24
Peak memory 206364 kb
Host smart-72dc065e-7281-4ba2-b8f9-6ecc1383a067
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2580793457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2580793457
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.550768788
Short name T551
Test name
Test status
Simulation time 139733182 ps
CPU time 0.78 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206396 kb
Host smart-f7af2687-6cf3-49c9-98e5-f11c9aee3c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55076
8788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.550768788
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3765832567
Short name T2361
Test name
Test status
Simulation time 234898425 ps
CPU time 0.93 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206376 kb
Host smart-15a829aa-a3ef-4294-a74b-ebb284d7ffee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37658
32567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3765832567
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.489392473
Short name T433
Test name
Test status
Simulation time 170221529 ps
CPU time 0.86 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:19 PM PDT 24
Peak memory 206388 kb
Host smart-a144cde0-fa08-454c-8bab-e64575a42359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48939
2473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.489392473
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.515310639
Short name T26
Test name
Test status
Simulation time 193202911 ps
CPU time 0.82 seconds
Started Jul 10 06:45:18 PM PDT 24
Finished Jul 10 06:45:26 PM PDT 24
Peak memory 206360 kb
Host smart-f7b84c9c-db5a-484d-8689-b9a78e01aefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51531
0639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.515310639
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3227401996
Short name T1914
Test name
Test status
Simulation time 173175777 ps
CPU time 0.81 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206312 kb
Host smart-c74f7f8b-811f-4b67-a2c9-4c9286e065c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32274
01996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3227401996
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1698258272
Short name T1246
Test name
Test status
Simulation time 154384069 ps
CPU time 0.77 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:22 PM PDT 24
Peak memory 206380 kb
Host smart-fa3d1f5e-0e5e-4847-a317-637c1137fdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16982
58272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1698258272
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.408238060
Short name T1228
Test name
Test status
Simulation time 235400561 ps
CPU time 1.01 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206408 kb
Host smart-14339bd6-c141-4ecb-b9d5-8e64dcb5ed3a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=408238060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.408238060
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.733533441
Short name T543
Test name
Test status
Simulation time 141623362 ps
CPU time 0.77 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206264 kb
Host smart-0b5f41a4-c480-460c-bbd9-ed4e6f31b4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73353
3441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.733533441
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.953647190
Short name T743
Test name
Test status
Simulation time 94088247 ps
CPU time 0.68 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:14 PM PDT 24
Peak memory 206388 kb
Host smart-4ce816b5-0780-499a-8220-006334e0152c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95364
7190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.953647190
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.641392643
Short name T2052
Test name
Test status
Simulation time 14533158746 ps
CPU time 34 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:45:53 PM PDT 24
Peak memory 206724 kb
Host smart-2aa884b1-4d2d-41fb-8e93-540bd3af33fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64139
2643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.641392643
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2748312875
Short name T2325
Test name
Test status
Simulation time 173222049 ps
CPU time 0.82 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206220 kb
Host smart-5b168030-ef17-4539-b0ff-7deaa9f8c54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27483
12875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2748312875
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3776326902
Short name T641
Test name
Test status
Simulation time 172932502 ps
CPU time 0.82 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:18 PM PDT 24
Peak memory 206364 kb
Host smart-bd28ac87-f5fc-4cc8-ad9f-47170e08f6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37763
26902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3776326902
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1113109377
Short name T443
Test name
Test status
Simulation time 185684008 ps
CPU time 0.89 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206380 kb
Host smart-b5ace9c4-e2f5-4679-a662-4d71947e8c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11131
09377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1113109377
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.1835378248
Short name T483
Test name
Test status
Simulation time 188506346 ps
CPU time 0.88 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:18 PM PDT 24
Peak memory 206372 kb
Host smart-e0baf7df-ee40-4c76-a29a-2437505d4125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18353
78248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.1835378248
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.337203041
Short name T1680
Test name
Test status
Simulation time 143642276 ps
CPU time 0.78 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:45:20 PM PDT 24
Peak memory 206352 kb
Host smart-9056b94c-8ad7-477a-b904-18ee75791ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33720
3041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.337203041
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.101833001
Short name T880
Test name
Test status
Simulation time 199567165 ps
CPU time 0.82 seconds
Started Jul 10 06:45:11 PM PDT 24
Finished Jul 10 06:45:16 PM PDT 24
Peak memory 206376 kb
Host smart-667b0e97-bbeb-411d-a863-bba2f1461d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10183
3001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.101833001
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2374077920
Short name T1053
Test name
Test status
Simulation time 191216605 ps
CPU time 0.8 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206356 kb
Host smart-b6854d51-4c12-45bf-a3c9-fec1b91af68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23740
77920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2374077920
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.27297936
Short name T986
Test name
Test status
Simulation time 207960441 ps
CPU time 0.94 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206348 kb
Host smart-35a23993-a4da-44ae-b575-0b4b079e5532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27297
936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.27297936
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2436108524
Short name T2132
Test name
Test status
Simulation time 4207897240 ps
CPU time 29.85 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:54 PM PDT 24
Peak memory 206532 kb
Host smart-e5a83f46-f93d-4aea-9229-abd6aac9d184
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2436108524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2436108524
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1278771115
Short name T243
Test name
Test status
Simulation time 155915810 ps
CPU time 0.78 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:17 PM PDT 24
Peak memory 206384 kb
Host smart-06a3e016-a3f1-4442-ba98-e6a28062c8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12787
71115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1278771115
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1566520263
Short name T736
Test name
Test status
Simulation time 154304002 ps
CPU time 0.76 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206292 kb
Host smart-3545f12e-5e2e-4468-a20d-d78052ea7f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15665
20263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1566520263
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.3803157359
Short name T2381
Test name
Test status
Simulation time 202872271 ps
CPU time 1.09 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206380 kb
Host smart-076f9ad0-1a4e-4400-a96d-20e74770a92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38031
57359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.3803157359
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3233861680
Short name T1997
Test name
Test status
Simulation time 6326170614 ps
CPU time 161.45 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:48:02 PM PDT 24
Peak memory 206604 kb
Host smart-aa67f3fd-82ee-4e00-83bf-503a0cff3e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32338
61680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3233861680
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.3264597523
Short name T1140
Test name
Test status
Simulation time 45455610 ps
CPU time 0.66 seconds
Started Jul 10 06:45:21 PM PDT 24
Finished Jul 10 06:45:29 PM PDT 24
Peak memory 206432 kb
Host smart-432b6b14-0034-4b89-aa87-c1ea98998414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3264597523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3264597523
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.539068205
Short name T608
Test name
Test status
Simulation time 4347508697 ps
CPU time 5.21 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:19 PM PDT 24
Peak memory 206616 kb
Host smart-bd091dee-b769-4493-b73d-05b4299b444c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=539068205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.539068205
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.477893040
Short name T1116
Test name
Test status
Simulation time 13391670727 ps
CPU time 16.12 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:37 PM PDT 24
Peak memory 206352 kb
Host smart-775ca169-ab47-43ed-a6b9-d1ff59629c3e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=477893040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.477893040
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.6363413
Short name T2152
Test name
Test status
Simulation time 23455983404 ps
CPU time 22.81 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206600 kb
Host smart-e5652b90-2e4d-4d62-9903-0444ade3a788
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=6363413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.6363413
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2984347780
Short name T1668
Test name
Test status
Simulation time 192873213 ps
CPU time 0.85 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206392 kb
Host smart-fd772940-582e-4013-98ca-12f5677cd51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29843
47780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2984347780
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.779560056
Short name T65
Test name
Test status
Simulation time 181588300 ps
CPU time 0.79 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:15 PM PDT 24
Peak memory 206388 kb
Host smart-db4b8137-e4b0-496e-8440-8e67571a2d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77956
0056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.779560056
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.363775137
Short name T2228
Test name
Test status
Simulation time 250823879 ps
CPU time 1.01 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206360 kb
Host smart-45cf3737-dcd9-4922-a3e3-65bf095f0c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36377
5137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.363775137
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2240929477
Short name T2124
Test name
Test status
Simulation time 658512409 ps
CPU time 1.58 seconds
Started Jul 10 06:45:13 PM PDT 24
Finished Jul 10 06:45:21 PM PDT 24
Peak memory 206632 kb
Host smart-f557d264-c7f0-4db3-abba-6a0f4f443b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
29477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2240929477
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.3932504568
Short name T1703
Test name
Test status
Simulation time 15563500323 ps
CPU time 30.74 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:55 PM PDT 24
Peak memory 206544 kb
Host smart-303f68cb-1974-4ba5-b8fc-083baa062d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39325
04568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3932504568
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.582612585
Short name T1047
Test name
Test status
Simulation time 415856512 ps
CPU time 1.36 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:18 PM PDT 24
Peak memory 206376 kb
Host smart-30b0008c-c5b9-411c-ac81-ec8abe192da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58261
2585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.582612585
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2091875960
Short name T2576
Test name
Test status
Simulation time 147776010 ps
CPU time 0.74 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206364 kb
Host smart-62f66931-44c5-40e1-8471-72ccc8b4bdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20918
75960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2091875960
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.9916775
Short name T347
Test name
Test status
Simulation time 50442151 ps
CPU time 0.65 seconds
Started Jul 10 06:45:12 PM PDT 24
Finished Jul 10 06:45:18 PM PDT 24
Peak memory 206380 kb
Host smart-d3c48290-447e-4ce6-b264-a2c82a6e71c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99167
75 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.9916775
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.1689070691
Short name T1106
Test name
Test status
Simulation time 919393195 ps
CPU time 2.17 seconds
Started Jul 10 06:45:10 PM PDT 24
Finished Jul 10 06:45:17 PM PDT 24
Peak memory 206636 kb
Host smart-0d7babb2-6560-45d7-8fca-7cb95d1b27f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16890
70691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.1689070691
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2078561548
Short name T792
Test name
Test status
Simulation time 183628291 ps
CPU time 1.82 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206636 kb
Host smart-9a7eed96-d562-48f2-bf82-8a6bb32e3ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20785
61548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2078561548
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.4035730540
Short name T2147
Test name
Test status
Simulation time 233278578 ps
CPU time 0.92 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:22 PM PDT 24
Peak memory 206360 kb
Host smart-c14861b7-af54-4d7a-94c4-993b93ede970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40357
30540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.4035730540
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.692161140
Short name T116
Test name
Test status
Simulation time 200397203 ps
CPU time 0.78 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206372 kb
Host smart-bfeba9fc-d869-416d-b1c4-5ef2ff975092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69216
1140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.692161140
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.585484249
Short name T2702
Test name
Test status
Simulation time 167034204 ps
CPU time 0.84 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206376 kb
Host smart-459fff2d-b615-4c2b-a122-0c8541eb9ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58548
4249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.585484249
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2364034321
Short name T336
Test name
Test status
Simulation time 280117064 ps
CPU time 0.9 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206360 kb
Host smart-b8b0fc38-2c6d-45bf-b42f-3775064f4db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23640
34321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2364034321
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.2141425702
Short name T420
Test name
Test status
Simulation time 23280875681 ps
CPU time 21.11 seconds
Started Jul 10 06:45:19 PM PDT 24
Finished Jul 10 06:45:47 PM PDT 24
Peak memory 206440 kb
Host smart-ae0b4f0d-b601-4596-8464-7d5ec7c4b0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21414
25702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2141425702
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.48098413
Short name T329
Test name
Test status
Simulation time 3351690591 ps
CPU time 4.41 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:35 PM PDT 24
Peak memory 206380 kb
Host smart-da05b16e-555c-4f33-817c-f221d9dbb0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48098
413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.48098413
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2404193880
Short name T1651
Test name
Test status
Simulation time 7872769372 ps
CPU time 58.29 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:46:28 PM PDT 24
Peak memory 206620 kb
Host smart-7b75021a-0a76-4630-b4d3-bbf5f7e80f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
93880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2404193880
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.796744361
Short name T504
Test name
Test status
Simulation time 6132582574 ps
CPU time 179.71 seconds
Started Jul 10 06:45:21 PM PDT 24
Finished Jul 10 06:48:28 PM PDT 24
Peak memory 206624 kb
Host smart-da0b18f1-f773-4741-b6ea-eb0417317267
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=796744361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.796744361
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2931295226
Short name T1637
Test name
Test status
Simulation time 249958242 ps
CPU time 0.96 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:32 PM PDT 24
Peak memory 206356 kb
Host smart-008b2529-1841-49fb-8632-66dfe666e4c7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2931295226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2931295226
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2771782941
Short name T1824
Test name
Test status
Simulation time 229226655 ps
CPU time 0.86 seconds
Started Jul 10 06:45:18 PM PDT 24
Finished Jul 10 06:45:26 PM PDT 24
Peak memory 206392 kb
Host smart-23f4b1a3-2f35-48f4-943e-dc078ae19b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27717
82941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2771782941
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2981576590
Short name T740
Test name
Test status
Simulation time 5588875856 ps
CPU time 152.52 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:48:06 PM PDT 24
Peak memory 206644 kb
Host smart-51540a2c-cefb-47c9-a545-2214a3d86550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29815
76590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2981576590
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.4223341784
Short name T1675
Test name
Test status
Simulation time 7491799554 ps
CPU time 206.36 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:48:56 PM PDT 24
Peak memory 206624 kb
Host smart-1f6a6159-84ec-4729-8cad-65bf3660dd18
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4223341784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.4223341784
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2544167138
Short name T996
Test name
Test status
Simulation time 155688832 ps
CPU time 0.78 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:35 PM PDT 24
Peak memory 206380 kb
Host smart-db38a26a-3465-40ac-82c1-9cdb21f4c2e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2544167138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2544167138
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3327018541
Short name T1493
Test name
Test status
Simulation time 184336483 ps
CPU time 0.87 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206364 kb
Host smart-4f161e3a-63d5-48cc-a410-d637b68f9166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33270
18541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3327018541
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3203322702
Short name T123
Test name
Test status
Simulation time 189480568 ps
CPU time 0.81 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:31 PM PDT 24
Peak memory 206356 kb
Host smart-8aa5a7d6-5562-4f22-acc4-7f944a25278f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32033
22702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3203322702
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.351601992
Short name T1238
Test name
Test status
Simulation time 181189416 ps
CPU time 0.85 seconds
Started Jul 10 06:45:21 PM PDT 24
Finished Jul 10 06:45:29 PM PDT 24
Peak memory 206376 kb
Host smart-937dd2d2-9d0c-407e-b558-383a2617b9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35160
1992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.351601992
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3360954744
Short name T1977
Test name
Test status
Simulation time 163976220 ps
CPU time 0.82 seconds
Started Jul 10 06:45:19 PM PDT 24
Finished Jul 10 06:45:28 PM PDT 24
Peak memory 206564 kb
Host smart-3bc4886c-0e0b-4e2b-a6ee-08549b7f049c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33609
54744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3360954744
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1035934414
Short name T1060
Test name
Test status
Simulation time 162721731 ps
CPU time 0.82 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206376 kb
Host smart-5687cc89-2f31-441b-9bc4-12eb8b315385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10359
34414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1035934414
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1082341169
Short name T1443
Test name
Test status
Simulation time 164382394 ps
CPU time 0.81 seconds
Started Jul 10 06:45:17 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206384 kb
Host smart-997211d7-9ea8-4c79-9b87-e1870fb3a592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10823
41169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1082341169
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3248519521
Short name T2624
Test name
Test status
Simulation time 263753473 ps
CPU time 0.9 seconds
Started Jul 10 06:45:19 PM PDT 24
Finished Jul 10 06:45:27 PM PDT 24
Peak memory 206396 kb
Host smart-0a864d17-6c2f-4268-b76a-f7cbc0163d6c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3248519521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3248519521
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2803549985
Short name T2722
Test name
Test status
Simulation time 163039188 ps
CPU time 0.75 seconds
Started Jul 10 06:45:36 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206380 kb
Host smart-965be4c9-9227-4ac2-9058-f5ca5e126cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28035
49985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2803549985
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3191861791
Short name T966
Test name
Test status
Simulation time 43007778 ps
CPU time 0.68 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206356 kb
Host smart-c8e7b02f-3a9d-4191-b520-d108b463db92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31918
61791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3191861791
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2699498184
Short name T2061
Test name
Test status
Simulation time 19673119501 ps
CPU time 39.81 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:46:10 PM PDT 24
Peak memory 214908 kb
Host smart-a3f2f43f-d723-4874-8d14-539d05c4a75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26994
98184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2699498184
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3719066322
Short name T1175
Test name
Test status
Simulation time 164611468 ps
CPU time 0.81 seconds
Started Jul 10 06:45:33 PM PDT 24
Finished Jul 10 06:45:41 PM PDT 24
Peak memory 206364 kb
Host smart-59b0d816-38a0-48be-9694-7ce1640b23b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
66322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3719066322
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2639912285
Short name T2583
Test name
Test status
Simulation time 223858819 ps
CPU time 0.98 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206364 kb
Host smart-b42b5960-c40d-46bb-9723-fe4f3bf386c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26399
12285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2639912285
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1370133428
Short name T1771
Test name
Test status
Simulation time 203769520 ps
CPU time 0.84 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206380 kb
Host smart-f0665e5f-190e-4043-ae4a-76b421c86b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13701
33428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1370133428
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3845175014
Short name T2687
Test name
Test status
Simulation time 155428149 ps
CPU time 0.8 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:35 PM PDT 24
Peak memory 206384 kb
Host smart-fd1ede5f-28dc-41ab-a1ea-cfd822d687ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451
75014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3845175014
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2050844128
Short name T1409
Test name
Test status
Simulation time 230917160 ps
CPU time 0.86 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:22 PM PDT 24
Peak memory 206364 kb
Host smart-40b00870-9f99-4305-ab7b-e8ddeb26adc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20508
44128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2050844128
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.4122042112
Short name T1829
Test name
Test status
Simulation time 173028690 ps
CPU time 0.84 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206372 kb
Host smart-faa117c7-08fe-44eb-9671-9c9db20bfced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41220
42112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.4122042112
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1598034001
Short name T1190
Test name
Test status
Simulation time 164701474 ps
CPU time 0.78 seconds
Started Jul 10 06:45:29 PM PDT 24
Finished Jul 10 06:45:36 PM PDT 24
Peak memory 206004 kb
Host smart-b5f2748f-c162-49db-bd5b-d890666724d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15980
34001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1598034001
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.77760445
Short name T2283
Test name
Test status
Simulation time 288481472 ps
CPU time 0.97 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206272 kb
Host smart-1c14d872-8bad-4c32-a040-d9ab7d0e792b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77760
445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.77760445
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2758655349
Short name T1289
Test name
Test status
Simulation time 5521620285 ps
CPU time 38.58 seconds
Started Jul 10 06:45:19 PM PDT 24
Finished Jul 10 06:46:04 PM PDT 24
Peak memory 206612 kb
Host smart-5b9644eb-c021-4e80-8972-33021bd6adc6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2758655349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2758655349
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2607636305
Short name T1286
Test name
Test status
Simulation time 169210333 ps
CPU time 0.79 seconds
Started Jul 10 06:45:29 PM PDT 24
Finished Jul 10 06:45:36 PM PDT 24
Peak memory 206332 kb
Host smart-061ae393-6419-45e4-b125-363b66270991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
36305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2607636305
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2392727514
Short name T2739
Test name
Test status
Simulation time 187252757 ps
CPU time 0.87 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:24 PM PDT 24
Peak memory 206372 kb
Host smart-581ec563-ee99-434d-ac98-fb4c2ba288d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23927
27514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2392727514
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.441631974
Short name T1462
Test name
Test status
Simulation time 570220224 ps
CPU time 1.51 seconds
Started Jul 10 06:45:27 PM PDT 24
Finished Jul 10 06:45:34 PM PDT 24
Peak memory 206388 kb
Host smart-d8df023c-fc8e-438e-9bd9-5f17640a2892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44163
1974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.441631974
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3215652154
Short name T2208
Test name
Test status
Simulation time 7223879977 ps
CPU time 199.76 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:48:50 PM PDT 24
Peak memory 206616 kb
Host smart-ffb6a9ce-3da8-4859-9dec-4c323329fc4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32156
52154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3215652154
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2486596231
Short name T787
Test name
Test status
Simulation time 52293734 ps
CPU time 0.75 seconds
Started Jul 10 06:45:27 PM PDT 24
Finished Jul 10 06:45:33 PM PDT 24
Peak memory 206440 kb
Host smart-76608439-e19c-4558-a7fc-4d853adee324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2486596231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2486596231
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1364628584
Short name T2190
Test name
Test status
Simulation time 4022006402 ps
CPU time 4.96 seconds
Started Jul 10 06:45:20 PM PDT 24
Finished Jul 10 06:45:32 PM PDT 24
Peak memory 206716 kb
Host smart-6931ce07-0b6d-4616-bcbd-56c65ecb5e3d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1364628584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1364628584
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3452940964
Short name T509
Test name
Test status
Simulation time 13318810006 ps
CPU time 13.23 seconds
Started Jul 10 06:45:19 PM PDT 24
Finished Jul 10 06:45:39 PM PDT 24
Peak memory 206444 kb
Host smart-5fae24bd-8e9b-43fb-b107-6753dcc6b834
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3452940964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3452940964
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2700163299
Short name T1744
Test name
Test status
Simulation time 23401780300 ps
CPU time 22.53 seconds
Started Jul 10 06:45:20 PM PDT 24
Finished Jul 10 06:45:50 PM PDT 24
Peak memory 206708 kb
Host smart-de6b75ff-b87b-47c1-8af5-e92c6a365050
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2700163299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.2700163299
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2026212733
Short name T1387
Test name
Test status
Simulation time 148470233 ps
CPU time 0.76 seconds
Started Jul 10 06:45:27 PM PDT 24
Finished Jul 10 06:45:33 PM PDT 24
Peak memory 206360 kb
Host smart-eba5ad2f-bb36-4751-9ca1-b13c00639065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20262
12733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2026212733
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3020226412
Short name T1511
Test name
Test status
Simulation time 181485751 ps
CPU time 0.87 seconds
Started Jul 10 06:45:32 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206388 kb
Host smart-dc07f2c7-f6c9-4401-94d8-d890f40940e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30202
26412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3020226412
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.948235138
Short name T1697
Test name
Test status
Simulation time 495449769 ps
CPU time 1.48 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206540 kb
Host smart-c0e3ab5e-a362-4a47-b1d5-c9ecb6b3eeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94823
5138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.948235138
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1501979410
Short name T1560
Test name
Test status
Simulation time 657098574 ps
CPU time 1.8 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:36 PM PDT 24
Peak memory 206576 kb
Host smart-b60f30c7-40bf-4545-9eb7-038cdd8c84d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15019
79410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1501979410
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.869693084
Short name T2748
Test name
Test status
Simulation time 11622740673 ps
CPU time 21.14 seconds
Started Jul 10 06:45:26 PM PDT 24
Finished Jul 10 06:45:53 PM PDT 24
Peak memory 206688 kb
Host smart-7645674e-7510-4052-a771-d0a183b35901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86969
3084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.869693084
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.397564252
Short name T2034
Test name
Test status
Simulation time 335485363 ps
CPU time 1.18 seconds
Started Jul 10 06:45:16 PM PDT 24
Finished Jul 10 06:45:25 PM PDT 24
Peak memory 206400 kb
Host smart-9a54fa0c-a73e-4252-a9ba-a19d0f1b4cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39756
4252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.397564252
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2916250326
Short name T2098
Test name
Test status
Simulation time 198151331 ps
CPU time 0.78 seconds
Started Jul 10 06:45:19 PM PDT 24
Finished Jul 10 06:45:27 PM PDT 24
Peak memory 206396 kb
Host smart-ac2ae663-388c-4b5d-80a3-5e313942f363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29162
50326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2916250326
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.4064443060
Short name T1054
Test name
Test status
Simulation time 40022887 ps
CPU time 0.68 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206376 kb
Host smart-f632aedf-cb31-45c3-8ac3-45dce9397b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40644
43060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.4064443060
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3881555867
Short name T2628
Test name
Test status
Simulation time 974974361 ps
CPU time 2.23 seconds
Started Jul 10 06:45:26 PM PDT 24
Finished Jul 10 06:45:34 PM PDT 24
Peak memory 206620 kb
Host smart-35d90605-d22e-4a31-ab33-c3c092e90d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38815
55867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3881555867
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2795277578
Short name T1429
Test name
Test status
Simulation time 293830567 ps
CPU time 1.69 seconds
Started Jul 10 06:45:32 PM PDT 24
Finished Jul 10 06:45:41 PM PDT 24
Peak memory 206548 kb
Host smart-b8a25a74-fbf3-4c50-a46a-0c0dee0d7ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27952
77578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2795277578
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3865386097
Short name T1901
Test name
Test status
Simulation time 179601145 ps
CPU time 0.88 seconds
Started Jul 10 06:45:32 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206388 kb
Host smart-b3cb937b-7ee7-4719-b238-a5d13572f809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38653
86097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3865386097
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.587947189
Short name T1466
Test name
Test status
Simulation time 142806056 ps
CPU time 0.75 seconds
Started Jul 10 06:45:29 PM PDT 24
Finished Jul 10 06:45:36 PM PDT 24
Peak memory 206072 kb
Host smart-c5c747b4-5f97-4e93-82a7-8b4e012ee080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58794
7189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.587947189
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3372152505
Short name T475
Test name
Test status
Simulation time 197589548 ps
CPU time 0.91 seconds
Started Jul 10 06:45:32 PM PDT 24
Finished Jul 10 06:45:41 PM PDT 24
Peak memory 206360 kb
Host smart-06c6e5a0-2296-475c-8fce-29d9c940230d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33721
52505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3372152505
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.352271668
Short name T625
Test name
Test status
Simulation time 5031830941 ps
CPU time 136.82 seconds
Started Jul 10 06:45:14 PM PDT 24
Finished Jul 10 06:47:38 PM PDT 24
Peak memory 206524 kb
Host smart-8b5d006e-37a3-4e5b-bd5e-78cf25fedae0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=352271668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.352271668
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.3945798941
Short name T921
Test name
Test status
Simulation time 5470524554 ps
CPU time 18.84 seconds
Started Jul 10 06:45:20 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206616 kb
Host smart-63525729-e7d6-4ef5-af7c-9f07630ab1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39457
98941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.3945798941
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3060445196
Short name T2156
Test name
Test status
Simulation time 195448167 ps
CPU time 0.86 seconds
Started Jul 10 06:45:15 PM PDT 24
Finished Jul 10 06:45:23 PM PDT 24
Peak memory 206392 kb
Host smart-9ed43e19-7a5e-48b2-90c1-60a12e839ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30604
45196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3060445196
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.393610279
Short name T732
Test name
Test status
Simulation time 23299235518 ps
CPU time 22.56 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:59 PM PDT 24
Peak memory 206372 kb
Host smart-e29883cc-b2da-4a2a-9427-f35d64e2d3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39361
0279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.393610279
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.4006900391
Short name T2277
Test name
Test status
Simulation time 3320201274 ps
CPU time 4.34 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206084 kb
Host smart-d295414d-1734-4b63-a5e3-8d050d32c51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40069
00391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.4006900391
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.414804100
Short name T564
Test name
Test status
Simulation time 7547923341 ps
CPU time 202.81 seconds
Started Jul 10 06:45:38 PM PDT 24
Finished Jul 10 06:49:07 PM PDT 24
Peak memory 206708 kb
Host smart-f735e46a-81bf-4ccd-a3b0-97affb8bbb95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41480
4100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.414804100
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.1886725698
Short name T2523
Test name
Test status
Simulation time 3420561209 ps
CPU time 31.32 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:46:01 PM PDT 24
Peak memory 206636 kb
Host smart-7c9029d7-0e52-46d7-a96f-39fb2ec11951
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1886725698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.1886725698
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.4191261164
Short name T978
Test name
Test status
Simulation time 235356017 ps
CPU time 0.91 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:31 PM PDT 24
Peak memory 206388 kb
Host smart-18152f7e-d849-4925-978d-0b4c6357dd84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4191261164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.4191261164
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.4172693604
Short name T747
Test name
Test status
Simulation time 227074530 ps
CPU time 0.88 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:35 PM PDT 24
Peak memory 206368 kb
Host smart-09a31a83-8b09-4baf-a364-539f83f2d481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41726
93604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.4172693604
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1543771995
Short name T2446
Test name
Test status
Simulation time 4463639896 ps
CPU time 42.61 seconds
Started Jul 10 06:45:26 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206588 kb
Host smart-68a5dba4-2ce4-4bf5-9616-bdcd70578f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15437
71995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1543771995
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2881844068
Short name T1597
Test name
Test status
Simulation time 3392239275 ps
CPU time 33.08 seconds
Started Jul 10 06:45:23 PM PDT 24
Finished Jul 10 06:46:02 PM PDT 24
Peak memory 206676 kb
Host smart-a1ac495a-8a3c-4162-a029-e37d0ae1797d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2881844068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2881844068
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.2435254599
Short name T343
Test name
Test status
Simulation time 161093139 ps
CPU time 0.79 seconds
Started Jul 10 06:45:32 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206364 kb
Host smart-5cc48258-7430-4b8c-a8c5-4c5e394adcb0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2435254599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.2435254599
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1978842257
Short name T2546
Test name
Test status
Simulation time 176499900 ps
CPU time 0.76 seconds
Started Jul 10 06:45:29 PM PDT 24
Finished Jul 10 06:45:37 PM PDT 24
Peak memory 206364 kb
Host smart-7d321fd4-74fe-49b1-a49b-aba17297987a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19788
42257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1978842257
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3763614697
Short name T2153
Test name
Test status
Simulation time 225557123 ps
CPU time 0.85 seconds
Started Jul 10 06:45:27 PM PDT 24
Finished Jul 10 06:45:33 PM PDT 24
Peak memory 206376 kb
Host smart-db487412-b56f-4478-8c42-a0925d6df14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37636
14697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3763614697
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2182785221
Short name T1671
Test name
Test status
Simulation time 177972621 ps
CPU time 0.9 seconds
Started Jul 10 06:45:22 PM PDT 24
Finished Jul 10 06:45:29 PM PDT 24
Peak memory 206368 kb
Host smart-ad585a2f-095a-40e3-91fb-9f70a2f3bca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21827
85221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2182785221
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1681293225
Short name T2619
Test name
Test status
Simulation time 184091951 ps
CPU time 0.83 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:32 PM PDT 24
Peak memory 206324 kb
Host smart-7476294a-31a0-42bb-81f7-6cb56b42d9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16812
93225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1681293225
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1726522332
Short name T2443
Test name
Test status
Simulation time 187812613 ps
CPU time 0.86 seconds
Started Jul 10 06:45:22 PM PDT 24
Finished Jul 10 06:45:29 PM PDT 24
Peak memory 206388 kb
Host smart-cbbf32ab-9d22-427d-af46-e0927dbb0f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17265
22332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1726522332
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2879901289
Short name T2613
Test name
Test status
Simulation time 153725385 ps
CPU time 0.82 seconds
Started Jul 10 06:45:33 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206388 kb
Host smart-648a2bac-6e43-4109-bbac-dbe25cfdac34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28799
01289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2879901289
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.3747746316
Short name T2383
Test name
Test status
Simulation time 252870821 ps
CPU time 0.96 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:34 PM PDT 24
Peak memory 206380 kb
Host smart-ff410541-2034-4d05-9751-1d8750928ba6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3747746316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.3747746316
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1953026823
Short name T2343
Test name
Test status
Simulation time 180983863 ps
CPU time 0.77 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:32 PM PDT 24
Peak memory 206388 kb
Host smart-928d5f3c-a6c2-4996-b6a2-7a0cfb6b6aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19530
26823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1953026823
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2470170656
Short name T861
Test name
Test status
Simulation time 38972761 ps
CPU time 0.68 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:45:30 PM PDT 24
Peak memory 206356 kb
Host smart-5a5ab81a-cf14-47f8-ae94-5a418b94672d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24701
70656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2470170656
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.167740816
Short name T245
Test name
Test status
Simulation time 10699935128 ps
CPU time 25.5 seconds
Started Jul 10 06:45:29 PM PDT 24
Finished Jul 10 06:46:00 PM PDT 24
Peak memory 206652 kb
Host smart-d957f9fe-7c15-439f-9964-ea2b3f3494e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16774
0816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.167740816
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.759386547
Short name T2328
Test name
Test status
Simulation time 255681927 ps
CPU time 0.95 seconds
Started Jul 10 06:45:42 PM PDT 24
Finished Jul 10 06:45:49 PM PDT 24
Peak memory 206396 kb
Host smart-eae5598b-2195-48f8-b945-45611a534f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75938
6547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.759386547
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.4127446832
Short name T1118
Test name
Test status
Simulation time 232294015 ps
CPU time 0.87 seconds
Started Jul 10 06:45:36 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206376 kb
Host smart-048fafc6-e5b2-4bb4-b6ec-738699a98c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41274
46832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.4127446832
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.100398488
Short name T1059
Test name
Test status
Simulation time 180052526 ps
CPU time 0.84 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:45:30 PM PDT 24
Peak memory 206360 kb
Host smart-a51a1425-c51d-4774-9869-4891f852f573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10039
8488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.100398488
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3182267901
Short name T1553
Test name
Test status
Simulation time 187029869 ps
CPU time 0.84 seconds
Started Jul 10 06:45:27 PM PDT 24
Finished Jul 10 06:45:34 PM PDT 24
Peak memory 206400 kb
Host smart-6286c705-0edd-49b4-ae6f-260b97592fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31822
67901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3182267901
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2696060044
Short name T1869
Test name
Test status
Simulation time 166249687 ps
CPU time 0.82 seconds
Started Jul 10 06:45:36 PM PDT 24
Finished Jul 10 06:45:43 PM PDT 24
Peak memory 206376 kb
Host smart-9932b613-616b-43e9-8a53-cee2b8833834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26960
60044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2696060044
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2729593326
Short name T1212
Test name
Test status
Simulation time 189882417 ps
CPU time 0.77 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206372 kb
Host smart-2f906f52-6a4d-47c5-b612-8a0037214e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
93326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2729593326
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3552540439
Short name T2021
Test name
Test status
Simulation time 151321292 ps
CPU time 0.76 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:35 PM PDT 24
Peak memory 206308 kb
Host smart-10a47e2e-cf66-4377-ad18-b5e32b57bd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35525
40439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3552540439
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1837804907
Short name T2493
Test name
Test status
Simulation time 210605762 ps
CPU time 0.91 seconds
Started Jul 10 06:45:37 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206376 kb
Host smart-d8f443fb-901c-412a-802c-f40cd14b3eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378
04907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1837804907
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2222153743
Short name T1808
Test name
Test status
Simulation time 4283901245 ps
CPU time 31.2 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:46:01 PM PDT 24
Peak memory 206636 kb
Host smart-d869796c-368c-4fe5-8722-ee9b49f9c531
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2222153743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2222153743
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.256922645
Short name T520
Test name
Test status
Simulation time 166940330 ps
CPU time 0.79 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:34 PM PDT 24
Peak memory 206312 kb
Host smart-8c213aed-514c-49f9-8212-30db93c76437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25692
2645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.256922645
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3688709446
Short name T882
Test name
Test status
Simulation time 190162862 ps
CPU time 0.81 seconds
Started Jul 10 06:45:33 PM PDT 24
Finished Jul 10 06:45:41 PM PDT 24
Peak memory 206304 kb
Host smart-144b2168-34e9-488b-a27e-44b18e58f478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36887
09446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3688709446
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2384993031
Short name T345
Test name
Test status
Simulation time 1054801372 ps
CPU time 2.35 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:35 PM PDT 24
Peak memory 206616 kb
Host smart-9e5fde51-18db-47a0-90ee-674bc6b52640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23849
93031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2384993031
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1789699392
Short name T829
Test name
Test status
Simulation time 5452239263 ps
CPU time 54.6 seconds
Started Jul 10 06:45:34 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206668 kb
Host smart-205fabb5-5e52-4e0e-bdbb-89de8fd4c544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17896
99392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1789699392
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.4199956830
Short name T2057
Test name
Test status
Simulation time 38802150 ps
CPU time 0.7 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:45:50 PM PDT 24
Peak memory 206416 kb
Host smart-8b2c14e4-891f-411d-885e-c0f3097277ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4199956830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.4199956830
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1068587151
Short name T1343
Test name
Test status
Simulation time 3701877338 ps
CPU time 5.06 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:45:34 PM PDT 24
Peak memory 206680 kb
Host smart-5a45c44e-5076-4d96-9d70-e63649b86ba2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1068587151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1068587151
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2528818737
Short name T2264
Test name
Test status
Simulation time 13314701261 ps
CPU time 12.28 seconds
Started Jul 10 06:45:26 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206620 kb
Host smart-260fabfe-edb4-421f-b564-e715531cf672
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2528818737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2528818737
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.130482023
Short name T1014
Test name
Test status
Simulation time 23423558275 ps
CPU time 25.18 seconds
Started Jul 10 06:45:29 PM PDT 24
Finished Jul 10 06:46:00 PM PDT 24
Peak memory 206448 kb
Host smart-38b010a3-7423-4f0a-bb19-64148fb9b35b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=130482023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.130482023
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3241757757
Short name T2320
Test name
Test status
Simulation time 201872169 ps
CPU time 0.83 seconds
Started Jul 10 06:45:26 PM PDT 24
Finished Jul 10 06:45:32 PM PDT 24
Peak memory 206260 kb
Host smart-e357a6f9-b5ce-4a06-90bb-964d6c17cced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32417
57757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3241757757
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2471265784
Short name T1366
Test name
Test status
Simulation time 165220094 ps
CPU time 0.79 seconds
Started Jul 10 06:45:29 PM PDT 24
Finished Jul 10 06:45:36 PM PDT 24
Peak memory 206380 kb
Host smart-b6a12f8f-02b8-4e36-8391-f250de4b38dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24712
65784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2471265784
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2439118029
Short name T2491
Test name
Test status
Simulation time 581046382 ps
CPU time 1.61 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:33 PM PDT 24
Peak memory 206628 kb
Host smart-c7b42208-ef40-4066-b442-756252a47f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24391
18029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2439118029
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.614927593
Short name T2344
Test name
Test status
Simulation time 1337573880 ps
CPU time 3.09 seconds
Started Jul 10 06:45:34 PM PDT 24
Finished Jul 10 06:45:45 PM PDT 24
Peak memory 206584 kb
Host smart-66e33843-2b1a-4aae-b295-95b9f49820e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61492
7593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.614927593
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.2515684007
Short name T2054
Test name
Test status
Simulation time 14195915933 ps
CPU time 25.17 seconds
Started Jul 10 06:45:33 PM PDT 24
Finished Jul 10 06:46:06 PM PDT 24
Peak memory 206648 kb
Host smart-fb046bb9-c7e3-4805-917f-c3d4f7da1f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25156
84007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.2515684007
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.483454914
Short name T1978
Test name
Test status
Simulation time 495245128 ps
CPU time 1.32 seconds
Started Jul 10 06:45:33 PM PDT 24
Finished Jul 10 06:45:41 PM PDT 24
Peak memory 206316 kb
Host smart-d0a850d7-978f-4598-bb21-3120609f591a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48345
4914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.483454914
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3820811327
Short name T571
Test name
Test status
Simulation time 155954469 ps
CPU time 0.77 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206400 kb
Host smart-aac44bf4-35c6-4679-b9eb-4df374c65ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38208
11327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3820811327
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3275768087
Short name T516
Test name
Test status
Simulation time 85485620 ps
CPU time 0.77 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:45:30 PM PDT 24
Peak memory 206364 kb
Host smart-a0e3df0b-7497-495e-883c-a70db0b07ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32757
68087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3275768087
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1574056212
Short name T2747
Test name
Test status
Simulation time 817640460 ps
CPU time 2.17 seconds
Started Jul 10 06:45:23 PM PDT 24
Finished Jul 10 06:45:31 PM PDT 24
Peak memory 206536 kb
Host smart-c015b854-3ea9-46fc-95a7-961bdda959b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15740
56212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1574056212
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2086036626
Short name T1905
Test name
Test status
Simulation time 317225752 ps
CPU time 2.06 seconds
Started Jul 10 06:45:23 PM PDT 24
Finished Jul 10 06:45:31 PM PDT 24
Peak memory 206556 kb
Host smart-7220b447-9c6d-4fde-b78e-a2e633020b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20860
36626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2086036626
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3869156448
Short name T1032
Test name
Test status
Simulation time 209113928 ps
CPU time 0.97 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:31 PM PDT 24
Peak memory 206392 kb
Host smart-62984805-3791-412b-97cd-0039a6ea6baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38691
56448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3869156448
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2080147744
Short name T115
Test name
Test status
Simulation time 149382664 ps
CPU time 0.78 seconds
Started Jul 10 06:45:28 PM PDT 24
Finished Jul 10 06:45:34 PM PDT 24
Peak memory 206020 kb
Host smart-d31bce04-1079-484c-98c3-c0b538cdbb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20801
47744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2080147744
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.373848465
Short name T2659
Test name
Test status
Simulation time 180707267 ps
CPU time 0.85 seconds
Started Jul 10 06:45:25 PM PDT 24
Finished Jul 10 06:45:32 PM PDT 24
Peak memory 206376 kb
Host smart-bcc29d7b-2402-4a96-a3ed-2e07548f7832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37384
8465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.373848465
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.573389066
Short name T2240
Test name
Test status
Simulation time 5557851273 ps
CPU time 40.56 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:46:10 PM PDT 24
Peak memory 206832 kb
Host smart-7c7d19b5-7598-4280-88bd-1c7d1e50e178
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=573389066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.573389066
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.3246094037
Short name T2350
Test name
Test status
Simulation time 11932868835 ps
CPU time 100.13 seconds
Started Jul 10 06:45:27 PM PDT 24
Finished Jul 10 06:47:12 PM PDT 24
Peak memory 206588 kb
Host smart-77621fab-ec80-4c6c-a7cc-a44ddb7643ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32460
94037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.3246094037
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.4096976762
Short name T583
Test name
Test status
Simulation time 214106667 ps
CPU time 0.83 seconds
Started Jul 10 06:45:24 PM PDT 24
Finished Jul 10 06:45:31 PM PDT 24
Peak memory 206388 kb
Host smart-07aec763-5c51-4ac5-925f-531b70df4298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40969
76762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.4096976762
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.474438995
Short name T983
Test name
Test status
Simulation time 23304463136 ps
CPU time 24 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:46:11 PM PDT 24
Peak memory 206420 kb
Host smart-7779bae2-ba9c-4d86-8d0a-26c611b1e827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47443
8995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.474438995
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1940888538
Short name T704
Test name
Test status
Simulation time 3377087553 ps
CPU time 4.02 seconds
Started Jul 10 06:45:29 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206464 kb
Host smart-c5438704-dc9a-4d42-bef7-27556dc646bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19408
88538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1940888538
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1245307974
Short name T2660
Test name
Test status
Simulation time 10929022779 ps
CPU time 105.1 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:47:23 PM PDT 24
Peak memory 206880 kb
Host smart-5de711b1-b4c6-4cf0-bc25-8a43b22f51f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453
07974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1245307974
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3195091511
Short name T2137
Test name
Test status
Simulation time 4809479791 ps
CPU time 125.33 seconds
Started Jul 10 06:45:40 PM PDT 24
Finished Jul 10 06:47:51 PM PDT 24
Peak memory 206656 kb
Host smart-4c0af1b7-3a12-418b-a0dd-5c6b79534019
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3195091511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3195091511
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3414666113
Short name T958
Test name
Test status
Simulation time 245288753 ps
CPU time 1 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206376 kb
Host smart-c1e5f490-a30c-412e-9cdd-2450167acce5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3414666113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3414666113
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3910291115
Short name T1434
Test name
Test status
Simulation time 229772559 ps
CPU time 0.92 seconds
Started Jul 10 06:45:32 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206376 kb
Host smart-2deb29ab-c8c8-4732-a221-476547a1604e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39102
91115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3910291115
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1552346105
Short name T1348
Test name
Test status
Simulation time 5768376938 ps
CPU time 55.91 seconds
Started Jul 10 06:45:45 PM PDT 24
Finished Jul 10 06:46:45 PM PDT 24
Peak memory 206712 kb
Host smart-d22aecdb-2795-460d-b210-af519954180b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15523
46105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1552346105
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1711142901
Short name T1578
Test name
Test status
Simulation time 4445246692 ps
CPU time 120.7 seconds
Started Jul 10 06:45:34 PM PDT 24
Finished Jul 10 06:47:42 PM PDT 24
Peak memory 206624 kb
Host smart-19b43353-dce1-49bc-bab5-f90e54feb4bf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1711142901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1711142901
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2245176922
Short name T1549
Test name
Test status
Simulation time 150141737 ps
CPU time 0.78 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:37 PM PDT 24
Peak memory 206392 kb
Host smart-f87f43d5-0b43-493d-acd6-3a24a9262952
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2245176922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2245176922
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2052381343
Short name T2742
Test name
Test status
Simulation time 144288581 ps
CPU time 0.77 seconds
Started Jul 10 06:45:34 PM PDT 24
Finished Jul 10 06:45:42 PM PDT 24
Peak memory 206364 kb
Host smart-5eb9dd8c-40b4-49a4-a4d9-a648be87bb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20523
81343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2052381343
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2548391020
Short name T139
Test name
Test status
Simulation time 228006166 ps
CPU time 0.88 seconds
Started Jul 10 06:45:31 PM PDT 24
Finished Jul 10 06:45:39 PM PDT 24
Peak memory 206376 kb
Host smart-c52c8436-1cde-4472-a9a0-2a33cfa4e608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25483
91020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2548391020
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1812676113
Short name T85
Test name
Test status
Simulation time 175155529 ps
CPU time 0.85 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206372 kb
Host smart-06ab228a-72f6-4b3b-bce5-3780942429ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18126
76113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1812676113
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3616517778
Short name T2710
Test name
Test status
Simulation time 173088121 ps
CPU time 0.77 seconds
Started Jul 10 06:45:31 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206324 kb
Host smart-34f7ba7d-fd63-4b71-8aac-a8e5fa6a5a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36165
17778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3616517778
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1142689203
Short name T395
Test name
Test status
Simulation time 185412614 ps
CPU time 0.87 seconds
Started Jul 10 06:45:35 PM PDT 24
Finished Jul 10 06:45:43 PM PDT 24
Peak memory 206404 kb
Host smart-acc4b21c-58d4-4c61-8c51-746d19d73bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11426
89203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1142689203
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1499111027
Short name T180
Test name
Test status
Simulation time 153204442 ps
CPU time 0.8 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206384 kb
Host smart-be465bb3-7a7b-4a36-a8de-12112740261d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14991
11027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1499111027
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.1244220730
Short name T1108
Test name
Test status
Simulation time 221196874 ps
CPU time 0.88 seconds
Started Jul 10 06:45:35 PM PDT 24
Finished Jul 10 06:45:43 PM PDT 24
Peak memory 206308 kb
Host smart-bcc744e9-b52a-4faa-ad6e-fbdd71dd9a1c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1244220730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.1244220730
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.911192926
Short name T312
Test name
Test status
Simulation time 149188045 ps
CPU time 0.79 seconds
Started Jul 10 06:45:40 PM PDT 24
Finished Jul 10 06:45:50 PM PDT 24
Peak memory 206380 kb
Host smart-abc982f8-dadc-4211-981b-d121b3517d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91119
2926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.911192926
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1712635576
Short name T1490
Test name
Test status
Simulation time 55533089 ps
CPU time 0.65 seconds
Started Jul 10 06:45:38 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206372 kb
Host smart-21c1b918-34cd-4fcb-9a02-831280a84ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17126
35576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1712635576
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2085595852
Short name T2424
Test name
Test status
Simulation time 12149665179 ps
CPU time 28.25 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:46:06 PM PDT 24
Peak memory 206684 kb
Host smart-508e8783-c96b-4734-8061-a6d7db3120d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20855
95852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2085595852
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1742153598
Short name T291
Test name
Test status
Simulation time 259541407 ps
CPU time 0.93 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206396 kb
Host smart-460e53bb-76f9-4148-ba0a-495841bc9c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17421
53598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1742153598
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3823894186
Short name T2602
Test name
Test status
Simulation time 210636596 ps
CPU time 0.83 seconds
Started Jul 10 06:45:39 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206340 kb
Host smart-91c42e81-e284-4a2c-b16c-daea33401142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38238
94186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3823894186
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1717788062
Short name T1599
Test name
Test status
Simulation time 243072309 ps
CPU time 0.85 seconds
Started Jul 10 06:45:40 PM PDT 24
Finished Jul 10 06:45:47 PM PDT 24
Peak memory 206392 kb
Host smart-535bbf74-a013-44a9-a74a-fd8089fae917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17177
88062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1717788062
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.2363260997
Short name T545
Test name
Test status
Simulation time 152762349 ps
CPU time 0.79 seconds
Started Jul 10 06:45:32 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206396 kb
Host smart-e31a31be-571e-4285-a21e-81a62de8ea69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23632
60997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.2363260997
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1086290311
Short name T717
Test name
Test status
Simulation time 159962293 ps
CPU time 0.88 seconds
Started Jul 10 06:45:33 PM PDT 24
Finished Jul 10 06:45:40 PM PDT 24
Peak memory 206384 kb
Host smart-0dfa8d5f-bb90-463a-b484-8b95d6777496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10862
90311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1086290311
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2306134222
Short name T394
Test name
Test status
Simulation time 153355313 ps
CPU time 0.76 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206376 kb
Host smart-51241f7f-b969-4ded-aeed-8260d071d607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23061
34222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2306134222
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2963230469
Short name T804
Test name
Test status
Simulation time 176295517 ps
CPU time 0.79 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:38 PM PDT 24
Peak memory 206380 kb
Host smart-00418ab5-9649-458d-abef-ac122279f34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
30469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2963230469
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2028692694
Short name T502
Test name
Test status
Simulation time 233121732 ps
CPU time 0.95 seconds
Started Jul 10 06:45:31 PM PDT 24
Finished Jul 10 06:45:39 PM PDT 24
Peak memory 206304 kb
Host smart-dc8d9136-3ac4-4cac-883b-e939545255ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20286
92694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2028692694
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1520506009
Short name T1200
Test name
Test status
Simulation time 5634891748 ps
CPU time 38.99 seconds
Started Jul 10 06:45:36 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206648 kb
Host smart-ecbe4b72-4dbc-4628-a139-333fa66dae95
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1520506009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1520506009
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2043829355
Short name T1193
Test name
Test status
Simulation time 160099047 ps
CPU time 0.78 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:45:48 PM PDT 24
Peak memory 206372 kb
Host smart-2ae651eb-655e-47f5-979f-0b69092000b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438
29355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2043829355
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3566362790
Short name T1325
Test name
Test status
Simulation time 191085797 ps
CPU time 0.84 seconds
Started Jul 10 06:45:31 PM PDT 24
Finished Jul 10 06:45:39 PM PDT 24
Peak memory 206376 kb
Host smart-cab17f05-3b87-4d73-9400-d16b80ae0fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35663
62790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3566362790
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2520125179
Short name T862
Test name
Test status
Simulation time 1343930379 ps
CPU time 2.69 seconds
Started Jul 10 06:45:33 PM PDT 24
Finished Jul 10 06:45:43 PM PDT 24
Peak memory 206624 kb
Host smart-7d63234b-c6cd-4cb7-b649-52a662e9d6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
25179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2520125179
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3359115515
Short name T562
Test name
Test status
Simulation time 5507417913 ps
CPU time 48.75 seconds
Started Jul 10 06:45:35 PM PDT 24
Finished Jul 10 06:46:31 PM PDT 24
Peak memory 206648 kb
Host smart-cab9ea28-01c7-4a65-8d11-7ea5c56ce1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33591
15515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3359115515
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1804337655
Short name T2433
Test name
Test status
Simulation time 30079153 ps
CPU time 0.7 seconds
Started Jul 10 06:46:00 PM PDT 24
Finished Jul 10 06:46:04 PM PDT 24
Peak memory 206436 kb
Host smart-b013eea2-ef9e-49bb-aaf5-4a2eeb95912c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1804337655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1804337655
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.83030790
Short name T13
Test name
Test status
Simulation time 4251458833 ps
CPU time 4.65 seconds
Started Jul 10 06:45:30 PM PDT 24
Finished Jul 10 06:45:42 PM PDT 24
Peak memory 206776 kb
Host smart-74d1042e-a2a9-4e32-8065-0dccd780e9de
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=83030790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.83030790
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.763975163
Short name T1572
Test name
Test status
Simulation time 13401181380 ps
CPU time 12.62 seconds
Started Jul 10 06:45:45 PM PDT 24
Finished Jul 10 06:46:02 PM PDT 24
Peak memory 206456 kb
Host smart-1ea8a980-9a2b-4e9a-aa8e-dfdc9d10ef52
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=763975163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.763975163
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.398498185
Short name T1312
Test name
Test status
Simulation time 23344655485 ps
CPU time 22.22 seconds
Started Jul 10 06:45:31 PM PDT 24
Finished Jul 10 06:46:00 PM PDT 24
Peak memory 206644 kb
Host smart-0252844a-4fe1-4230-af45-8e18c0717d0c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=398498185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.398498185
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1055201223
Short name T1438
Test name
Test status
Simulation time 179033938 ps
CPU time 0.87 seconds
Started Jul 10 06:45:35 PM PDT 24
Finished Jul 10 06:45:43 PM PDT 24
Peak memory 206380 kb
Host smart-b329b866-d6dd-42f8-995f-872543a8867a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10552
01223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1055201223
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1007935392
Short name T1751
Test name
Test status
Simulation time 164904388 ps
CPU time 0.75 seconds
Started Jul 10 06:45:55 PM PDT 24
Finished Jul 10 06:45:56 PM PDT 24
Peak memory 206388 kb
Host smart-b9bed211-7f12-4f7c-b2da-c01436b5f345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10079
35392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1007935392
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.2058299415
Short name T696
Test name
Test status
Simulation time 267131339 ps
CPU time 1.09 seconds
Started Jul 10 06:45:31 PM PDT 24
Finished Jul 10 06:45:39 PM PDT 24
Peak memory 206376 kb
Host smart-35fdecd7-b366-43f6-b54f-77b03bda557f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582
99415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2058299415
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.454790954
Short name T1388
Test name
Test status
Simulation time 666022256 ps
CPU time 1.71 seconds
Started Jul 10 06:45:31 PM PDT 24
Finished Jul 10 06:45:39 PM PDT 24
Peak memory 206552 kb
Host smart-d1af49bc-fbfa-42e6-b7c9-09eb0509cbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45479
0954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.454790954
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.4187564387
Short name T1732
Test name
Test status
Simulation time 13612615646 ps
CPU time 28.4 seconds
Started Jul 10 06:45:44 PM PDT 24
Finished Jul 10 06:46:17 PM PDT 24
Peak memory 206688 kb
Host smart-58d7be28-d4e3-4b30-9478-ef3ceaa0e923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
64387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.4187564387
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2971928211
Short name T686
Test name
Test status
Simulation time 387787972 ps
CPU time 1.33 seconds
Started Jul 10 06:45:47 PM PDT 24
Finished Jul 10 06:45:52 PM PDT 24
Peak memory 206380 kb
Host smart-7db5f664-f032-4020-84f0-8afe717ffea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
28211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2971928211
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.4285465181
Short name T800
Test name
Test status
Simulation time 181815841 ps
CPU time 0.79 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:45:48 PM PDT 24
Peak memory 206376 kb
Host smart-60f4a082-8f51-42a8-aaca-14ecce6a6726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
65181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.4285465181
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3086102031
Short name T1411
Test name
Test status
Simulation time 54195454 ps
CPU time 0.72 seconds
Started Jul 10 06:45:57 PM PDT 24
Finished Jul 10 06:46:00 PM PDT 24
Peak memory 206352 kb
Host smart-6f87f992-7dbb-4b1e-8d28-46f25ae272dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30861
02031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3086102031
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3074481600
Short name T1926
Test name
Test status
Simulation time 929280955 ps
CPU time 2.13 seconds
Started Jul 10 06:45:37 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206628 kb
Host smart-caecc041-d311-4be0-a68d-fb03f7ff31d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30744
81600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3074481600
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.750837718
Short name T1940
Test name
Test status
Simulation time 225940404 ps
CPU time 1.35 seconds
Started Jul 10 06:45:38 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206624 kb
Host smart-ab512be1-4fa6-4e44-b9cf-74c3fcefcb91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75083
7718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.750837718
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2199991735
Short name T2690
Test name
Test status
Simulation time 193147841 ps
CPU time 0.8 seconds
Started Jul 10 06:45:43 PM PDT 24
Finished Jul 10 06:45:49 PM PDT 24
Peak memory 206364 kb
Host smart-cbfe0fe0-9426-4c76-9c1a-07f487730995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21999
91735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2199991735
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.456488427
Short name T1454
Test name
Test status
Simulation time 152321699 ps
CPU time 0.79 seconds
Started Jul 10 06:45:37 PM PDT 24
Finished Jul 10 06:45:44 PM PDT 24
Peak memory 206388 kb
Host smart-27dadf58-1d74-4723-b5ea-5ba40195252b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45648
8427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.456488427
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2699824832
Short name T473
Test name
Test status
Simulation time 254560947 ps
CPU time 0.89 seconds
Started Jul 10 06:45:57 PM PDT 24
Finished Jul 10 06:46:00 PM PDT 24
Peak memory 206376 kb
Host smart-738995fc-4fb7-4449-9c51-5d0e369b9021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26998
24832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2699824832
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2440266735
Short name T2417
Test name
Test status
Simulation time 11126814983 ps
CPU time 96.2 seconds
Started Jul 10 06:45:43 PM PDT 24
Finished Jul 10 06:47:24 PM PDT 24
Peak memory 206700 kb
Host smart-2db7c1d4-52df-4aac-bda4-62f99c98c983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
66735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2440266735
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.789729552
Short name T1681
Test name
Test status
Simulation time 222676774 ps
CPU time 0.91 seconds
Started Jul 10 06:45:58 PM PDT 24
Finished Jul 10 06:46:02 PM PDT 24
Peak memory 206388 kb
Host smart-63d50fa2-b76e-4deb-8bf5-ba38fd455a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78972
9552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.789729552
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.995736854
Short name T367
Test name
Test status
Simulation time 23331166764 ps
CPU time 23.27 seconds
Started Jul 10 06:45:55 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206464 kb
Host smart-de23ea28-644a-4528-98b6-a1296c4a92f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99573
6854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.995736854
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.4213074268
Short name T375
Test name
Test status
Simulation time 3340243002 ps
CPU time 3.81 seconds
Started Jul 10 06:45:39 PM PDT 24
Finished Jul 10 06:45:49 PM PDT 24
Peak memory 206452 kb
Host smart-f4f615af-f326-4752-907c-eaebb13e9077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42130
74268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.4213074268
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2763530748
Short name T2204
Test name
Test status
Simulation time 7724280683 ps
CPU time 59.04 seconds
Started Jul 10 06:45:37 PM PDT 24
Finished Jul 10 06:46:43 PM PDT 24
Peak memory 206692 kb
Host smart-cb140cc0-6c49-4d2b-9f7d-45234b7fa2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27635
30748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2763530748
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.825754254
Short name T528
Test name
Test status
Simulation time 7802847753 ps
CPU time 73.16 seconds
Started Jul 10 06:45:39 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206696 kb
Host smart-8e3a84a3-43ed-4f35-8178-e61202063d04
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=825754254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.825754254
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2451094442
Short name T919
Test name
Test status
Simulation time 246442924 ps
CPU time 0.99 seconds
Started Jul 10 06:45:35 PM PDT 24
Finished Jul 10 06:45:43 PM PDT 24
Peak memory 206372 kb
Host smart-dc5ce674-78f7-47c6-bbad-8f33a5e42be7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2451094442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2451094442
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2048670968
Short name T1320
Test name
Test status
Simulation time 251594683 ps
CPU time 0.94 seconds
Started Jul 10 06:45:38 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206380 kb
Host smart-91e7ba97-09c0-4e78-ad09-749f2a7736c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486
70968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2048670968
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1848868838
Short name T2097
Test name
Test status
Simulation time 3584462475 ps
CPU time 102.87 seconds
Started Jul 10 06:45:37 PM PDT 24
Finished Jul 10 06:47:27 PM PDT 24
Peak memory 206620 kb
Host smart-98da6825-87d5-4a94-aea6-230650155495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18488
68838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1848868838
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3452746206
Short name T1987
Test name
Test status
Simulation time 4254085632 ps
CPU time 39.11 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:46:26 PM PDT 24
Peak memory 206608 kb
Host smart-1df7dbb1-71d1-4149-b2b7-aad29b7d75a8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3452746206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3452746206
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3268899962
Short name T1892
Test name
Test status
Simulation time 157207817 ps
CPU time 0.79 seconds
Started Jul 10 06:45:40 PM PDT 24
Finished Jul 10 06:45:47 PM PDT 24
Peak memory 206364 kb
Host smart-411820bb-6312-4cd5-b930-272f5526b17f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3268899962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3268899962
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1055709982
Short name T1281
Test name
Test status
Simulation time 169605114 ps
CPU time 0.79 seconds
Started Jul 10 06:45:55 PM PDT 24
Finished Jul 10 06:45:57 PM PDT 24
Peak memory 206404 kb
Host smart-77ad9fc5-4e7d-47f8-ae40-5f7a4d490d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10557
09982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1055709982
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2201578508
Short name T143
Test name
Test status
Simulation time 236034919 ps
CPU time 1.03 seconds
Started Jul 10 06:45:39 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206356 kb
Host smart-e3d1bb55-5531-463d-9c2f-27cf836516c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22015
78508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2201578508
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2629255297
Short name T1547
Test name
Test status
Simulation time 188393300 ps
CPU time 0.98 seconds
Started Jul 10 06:45:37 PM PDT 24
Finished Jul 10 06:45:45 PM PDT 24
Peak memory 206372 kb
Host smart-33b28abc-4a78-4af2-abf1-5411cef9c918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26292
55297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2629255297
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.395934393
Short name T954
Test name
Test status
Simulation time 144849521 ps
CPU time 0.75 seconds
Started Jul 10 06:45:53 PM PDT 24
Finished Jul 10 06:45:55 PM PDT 24
Peak memory 206392 kb
Host smart-14dc5f01-0760-4958-a5ec-65cfb694b527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39593
4393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.395934393
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3078532750
Short name T1081
Test name
Test status
Simulation time 179102393 ps
CPU time 0.87 seconds
Started Jul 10 06:45:39 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206380 kb
Host smart-040fc76d-798f-4876-b569-27c77990f947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30785
32750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3078532750
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.381317758
Short name T2683
Test name
Test status
Simulation time 147634468 ps
CPU time 0.78 seconds
Started Jul 10 06:45:52 PM PDT 24
Finished Jul 10 06:45:54 PM PDT 24
Peak memory 206408 kb
Host smart-e98118bd-db8f-4447-93ce-9f98b3b0e610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38131
7758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.381317758
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.579155554
Short name T1678
Test name
Test status
Simulation time 253363203 ps
CPU time 0.99 seconds
Started Jul 10 06:45:39 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206372 kb
Host smart-d2649194-678b-4a7a-8532-ebbbe952d9e5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=579155554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.579155554
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2770244161
Short name T1883
Test name
Test status
Simulation time 152827566 ps
CPU time 0.79 seconds
Started Jul 10 06:45:54 PM PDT 24
Finished Jul 10 06:45:56 PM PDT 24
Peak memory 206380 kb
Host smart-86c3c859-b29d-4326-abd5-2d21061e4fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
44161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2770244161
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.4109360588
Short name T2729
Test name
Test status
Simulation time 30430451 ps
CPU time 0.64 seconds
Started Jul 10 06:45:50 PM PDT 24
Finished Jul 10 06:45:53 PM PDT 24
Peak memory 206372 kb
Host smart-b6cb7808-0f36-4b79-8d2c-395f273e6711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41093
60588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.4109360588
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2806168637
Short name T1948
Test name
Test status
Simulation time 13761276884 ps
CPU time 29.16 seconds
Started Jul 10 06:45:56 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206744 kb
Host smart-523cbd3e-815a-4981-a408-ad239a7bbf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28061
68637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2806168637
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.153320044
Short name T639
Test name
Test status
Simulation time 168576864 ps
CPU time 0.85 seconds
Started Jul 10 06:45:37 PM PDT 24
Finished Jul 10 06:45:45 PM PDT 24
Peak memory 206392 kb
Host smart-77b05c1a-abaa-409c-a5cf-6b58baa7a2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15332
0044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.153320044
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.277542315
Short name T1658
Test name
Test status
Simulation time 273320292 ps
CPU time 0.93 seconds
Started Jul 10 06:45:54 PM PDT 24
Finished Jul 10 06:45:56 PM PDT 24
Peak memory 206372 kb
Host smart-ee38f3f9-8088-4351-b10e-9392c7a790a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27754
2315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.277542315
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.2053966978
Short name T995
Test name
Test status
Simulation time 156362202 ps
CPU time 0.85 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:45:48 PM PDT 24
Peak memory 206400 kb
Host smart-6eb9d5c3-5da0-4901-b246-e613b55a5d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20539
66978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.2053966978
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1231127768
Short name T1095
Test name
Test status
Simulation time 180842883 ps
CPU time 0.88 seconds
Started Jul 10 06:45:38 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206400 kb
Host smart-945ee9fe-b582-4d28-ad88-157fce24cc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12311
27768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1231127768
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.658223854
Short name T2080
Test name
Test status
Simulation time 198502633 ps
CPU time 0.83 seconds
Started Jul 10 06:45:59 PM PDT 24
Finished Jul 10 06:46:03 PM PDT 24
Peak memory 206380 kb
Host smart-954767c5-45a1-4c7e-8974-9c474642d416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65822
3854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.658223854
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.536978861
Short name T2605
Test name
Test status
Simulation time 152929278 ps
CPU time 0.86 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:45:48 PM PDT 24
Peak memory 206376 kb
Host smart-8f2f605a-2316-4fa3-bc66-f8fa0ed8d69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53697
8861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.536978861
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.791849080
Short name T1476
Test name
Test status
Simulation time 200208664 ps
CPU time 0.86 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:45:47 PM PDT 24
Peak memory 206356 kb
Host smart-6c73a7d4-c2e6-4408-9f3d-a9b61e7e5a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79184
9080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.791849080
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.296990222
Short name T487
Test name
Test status
Simulation time 245063436 ps
CPU time 1.05 seconds
Started Jul 10 06:45:47 PM PDT 24
Finished Jul 10 06:45:51 PM PDT 24
Peak memory 206328 kb
Host smart-d38ec100-9580-4df1-99d6-f489c6814e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29699
0222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.296990222
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.4068859319
Short name T1382
Test name
Test status
Simulation time 3932006380 ps
CPU time 108.34 seconds
Started Jul 10 06:45:39 PM PDT 24
Finished Jul 10 06:47:34 PM PDT 24
Peak memory 206656 kb
Host smart-7a7d4523-1e70-4388-be61-7702f6487b4a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4068859319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.4068859319
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1385776166
Short name T1799
Test name
Test status
Simulation time 178313024 ps
CPU time 0.83 seconds
Started Jul 10 06:45:40 PM PDT 24
Finished Jul 10 06:45:46 PM PDT 24
Peak memory 206396 kb
Host smart-e3082bee-23e9-4e85-bedb-7eb65e966fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13857
76166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1385776166
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1255219887
Short name T1336
Test name
Test status
Simulation time 202042532 ps
CPU time 0.87 seconds
Started Jul 10 06:45:52 PM PDT 24
Finished Jul 10 06:45:54 PM PDT 24
Peak memory 206328 kb
Host smart-c06740f9-d99f-4c8c-8429-bf4eecb48537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12552
19887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1255219887
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3063960183
Short name T1039
Test name
Test status
Simulation time 1003623170 ps
CPU time 2.11 seconds
Started Jul 10 06:45:40 PM PDT 24
Finished Jul 10 06:45:48 PM PDT 24
Peak memory 206576 kb
Host smart-b5e8b0e3-ab78-4350-99a4-81ebdc552fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30639
60183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3063960183
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.793105746
Short name T2246
Test name
Test status
Simulation time 4150269984 ps
CPU time 29.26 seconds
Started Jul 10 06:45:41 PM PDT 24
Finished Jul 10 06:46:16 PM PDT 24
Peak memory 206692 kb
Host smart-a9969b8d-3304-45a9-8bdb-eefdfb3796e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79310
5746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.793105746
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2334666680
Short name T1306
Test name
Test status
Simulation time 34072568 ps
CPU time 0.66 seconds
Started Jul 10 06:39:52 PM PDT 24
Finished Jul 10 06:39:57 PM PDT 24
Peak memory 206408 kb
Host smart-6761edb3-cbae-475f-b561-6d9b62d2a4a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2334666680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2334666680
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2634510126
Short name T525
Test name
Test status
Simulation time 4430681781 ps
CPU time 5.75 seconds
Started Jul 10 06:39:34 PM PDT 24
Finished Jul 10 06:39:41 PM PDT 24
Peak memory 206436 kb
Host smart-1fbb2989-3443-4a21-9d5f-edcce8da8f80
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2634510126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2634510126
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1640429150
Short name T1925
Test name
Test status
Simulation time 13360559425 ps
CPU time 13.82 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206600 kb
Host smart-d92f5ea2-bf2b-4e44-b28e-4659edb651b4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1640429150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1640429150
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1139527927
Short name T2637
Test name
Test status
Simulation time 23340114400 ps
CPU time 23 seconds
Started Jul 10 06:39:34 PM PDT 24
Finished Jul 10 06:39:59 PM PDT 24
Peak memory 206464 kb
Host smart-6556e6e0-add9-4acc-b1fa-00262e836deb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1139527927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.1139527927
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.4226364665
Short name T767
Test name
Test status
Simulation time 154894092 ps
CPU time 0.83 seconds
Started Jul 10 06:39:33 PM PDT 24
Finished Jul 10 06:39:35 PM PDT 24
Peak memory 206272 kb
Host smart-19bc8d4d-cf24-4340-a0dc-5aefa3658650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42263
64665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.4226364665
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.113693541
Short name T53
Test name
Test status
Simulation time 192292621 ps
CPU time 0.86 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:39:38 PM PDT 24
Peak memory 206388 kb
Host smart-f2852429-871b-4cbe-b276-ca5b369c1dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
3541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.113693541
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.790814687
Short name T1048
Test name
Test status
Simulation time 183021773 ps
CPU time 0.82 seconds
Started Jul 10 06:39:35 PM PDT 24
Finished Jul 10 06:39:38 PM PDT 24
Peak memory 206356 kb
Host smart-ad616742-265b-43d0-add9-b68a1a38bc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79081
4687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.790814687
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1867712650
Short name T1376
Test name
Test status
Simulation time 343337321 ps
CPU time 1.2 seconds
Started Jul 10 06:39:48 PM PDT 24
Finished Jul 10 06:39:54 PM PDT 24
Peak memory 206376 kb
Host smart-d9f05e62-8c3d-452e-a4bc-c8041dadd3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18677
12650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1867712650
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3088778468
Short name T2697
Test name
Test status
Simulation time 1401154544 ps
CPU time 3.46 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:39:52 PM PDT 24
Peak memory 206644 kb
Host smart-84ca4b0b-0ee4-4b02-9aee-48b393b50e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30887
78468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3088778468
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2493900405
Short name T910
Test name
Test status
Simulation time 20098284149 ps
CPU time 40.25 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:40:30 PM PDT 24
Peak memory 206640 kb
Host smart-92c4c3b7-8bd8-4c70-bdf2-9ada55a58bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24939
00405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2493900405
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1163402245
Short name T2199
Test name
Test status
Simulation time 377696509 ps
CPU time 1.32 seconds
Started Jul 10 06:39:47 PM PDT 24
Finished Jul 10 06:39:53 PM PDT 24
Peak memory 206404 kb
Host smart-a1b6edbe-6590-4218-8a63-e9deabeeba44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11634
02245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1163402245
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.4254464207
Short name T1259
Test name
Test status
Simulation time 161678213 ps
CPU time 0.8 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206384 kb
Host smart-408a4c5a-509b-4a54-9ddf-46cde6f7567e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42544
64207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.4254464207
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1613039698
Short name T2352
Test name
Test status
Simulation time 55223292 ps
CPU time 0.69 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:39:49 PM PDT 24
Peak memory 206384 kb
Host smart-107c435b-e8ae-44c2-9ae1-ed7de17d3e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16130
39698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1613039698
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2246520104
Short name T2087
Test name
Test status
Simulation time 844203805 ps
CPU time 1.86 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:52 PM PDT 24
Peak memory 206640 kb
Host smart-5dccd081-6511-4549-8b22-7010d5e38a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22465
20104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2246520104
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.4245669713
Short name T2138
Test name
Test status
Simulation time 241193098 ps
CPU time 1.42 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:39:49 PM PDT 24
Peak memory 206568 kb
Host smart-ee52a038-134e-4550-babb-ecde4a3ea59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
69713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.4245669713
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.229175772
Short name T1474
Test name
Test status
Simulation time 106176258556 ps
CPU time 150.43 seconds
Started Jul 10 06:39:44 PM PDT 24
Finished Jul 10 06:42:17 PM PDT 24
Peak memory 206680 kb
Host smart-59350608-a864-43d0-82d1-7dc9bce5e75d
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=229175772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.229175772
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.147567772
Short name T2022
Test name
Test status
Simulation time 109032316025 ps
CPU time 143.15 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:42:10 PM PDT 24
Peak memory 206612 kb
Host smart-d43793fe-f6c7-4d69-9f99-12b9b8f0b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147567772 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.147567772
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.3380570741
Short name T1660
Test name
Test status
Simulation time 110104021708 ps
CPU time 148.2 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:42:16 PM PDT 24
Peak memory 206616 kb
Host smart-8f7f1f19-c84d-4f1f-abab-457095b72db8
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3380570741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3380570741
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1817753383
Short name T2514
Test name
Test status
Simulation time 115186761537 ps
CPU time 190.77 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:43:01 PM PDT 24
Peak memory 206620 kb
Host smart-2237b178-7969-4021-9cf6-e3102dbc8cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817753383 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1817753383
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.814687794
Short name T2414
Test name
Test status
Simulation time 96188135330 ps
CPU time 129.16 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:41:57 PM PDT 24
Peak memory 206596 kb
Host smart-e70c8f3a-90cc-4974-8b62-7d0e60916e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81468
7794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.814687794
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1747529724
Short name T1378
Test name
Test status
Simulation time 190490277 ps
CPU time 0.89 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:39:49 PM PDT 24
Peak memory 206364 kb
Host smart-2c058633-9bf6-4031-9531-c97f2b64d4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17475
29724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1747529724
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1875846295
Short name T570
Test name
Test status
Simulation time 154280009 ps
CPU time 0.78 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:39:48 PM PDT 24
Peak memory 206396 kb
Host smart-21c9d881-5e0d-4d4c-90ff-065c475a8bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18758
46295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1875846295
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1986322484
Short name T2473
Test name
Test status
Simulation time 251561633 ps
CPU time 0.92 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206388 kb
Host smart-094c91cd-b302-4a57-8fe2-7b2c57e5b517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19863
22484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1986322484
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.929311490
Short name T2219
Test name
Test status
Simulation time 5695010034 ps
CPU time 17.85 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:40:05 PM PDT 24
Peak memory 206668 kb
Host smart-9265e43a-838c-41bc-8a58-6366dc18030d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92931
1490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.929311490
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.513904026
Short name T2730
Test name
Test status
Simulation time 205352446 ps
CPU time 0.88 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206376 kb
Host smart-0275b975-8d0f-4403-a7dd-d39566afd9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51390
4026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.513904026
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1819711947
Short name T2003
Test name
Test status
Simulation time 23363241036 ps
CPU time 23.1 seconds
Started Jul 10 06:39:44 PM PDT 24
Finished Jul 10 06:40:08 PM PDT 24
Peak memory 206420 kb
Host smart-45aa0a7f-fc5d-408d-bef3-f3d5bd09cefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18197
11947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1819711947
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.51145355
Short name T1027
Test name
Test status
Simulation time 3295657330 ps
CPU time 4.18 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:55 PM PDT 24
Peak memory 206424 kb
Host smart-de810e98-0bc4-4ddf-833e-5a6cf83422fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51145
355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.51145355
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3181838297
Short name T1113
Test name
Test status
Simulation time 6410007682 ps
CPU time 46.37 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:40:33 PM PDT 24
Peak memory 206700 kb
Host smart-e5681ac5-fabe-4437-98fa-6c43d9c18bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31818
38297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3181838297
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.4062759049
Short name T397
Test name
Test status
Simulation time 5604404370 ps
CPU time 42.79 seconds
Started Jul 10 06:39:47 PM PDT 24
Finished Jul 10 06:40:34 PM PDT 24
Peak memory 206800 kb
Host smart-eba661ad-3c8c-4736-be78-d1b7f466efba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4062759049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.4062759049
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3727463583
Short name T437
Test name
Test status
Simulation time 236090112 ps
CPU time 0.92 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:39:49 PM PDT 24
Peak memory 206372 kb
Host smart-28d6b3f0-a02d-4881-b9e2-b751e4875466
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3727463583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3727463583
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.871669004
Short name T537
Test name
Test status
Simulation time 204470855 ps
CPU time 0.88 seconds
Started Jul 10 06:39:47 PM PDT 24
Finished Jul 10 06:39:52 PM PDT 24
Peak memory 206360 kb
Host smart-73128309-a887-4ef4-8567-4eca792058de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87166
9004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.871669004
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.723022807
Short name T1770
Test name
Test status
Simulation time 4383445138 ps
CPU time 121.7 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:41:52 PM PDT 24
Peak memory 206644 kb
Host smart-1b5259b1-d875-4758-a80b-8fd250e2a903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72302
2807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.723022807
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2797898703
Short name T1083
Test name
Test status
Simulation time 6925738288 ps
CPU time 47.52 seconds
Started Jul 10 06:39:48 PM PDT 24
Finished Jul 10 06:40:40 PM PDT 24
Peak memory 206644 kb
Host smart-5ec14127-7075-45ea-9030-32b635aa3053
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2797898703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2797898703
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.3355128848
Short name T1809
Test name
Test status
Simulation time 157195136 ps
CPU time 0.84 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206360 kb
Host smart-c65fb35c-e740-4846-99e7-f49ea59d6a5f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3355128848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.3355128848
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1489673189
Short name T412
Test name
Test status
Simulation time 164164666 ps
CPU time 0.82 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206384 kb
Host smart-fd589519-8412-4e62-9007-0b8f23c85f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14896
73189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1489673189
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3871895583
Short name T2563
Test name
Test status
Simulation time 209347792 ps
CPU time 0.83 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:39:49 PM PDT 24
Peak memory 206384 kb
Host smart-89d97187-cc58-4e45-884a-e2ba5ab81eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38718
95583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3871895583
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2426865441
Short name T1112
Test name
Test status
Simulation time 180181619 ps
CPU time 0.86 seconds
Started Jul 10 06:39:44 PM PDT 24
Finished Jul 10 06:39:47 PM PDT 24
Peak memory 206380 kb
Host smart-cf6b45dd-1ebc-4c3e-9a33-993bb2f97c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24268
65441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2426865441
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1095019408
Short name T2287
Test name
Test status
Simulation time 156965603 ps
CPU time 0.78 seconds
Started Jul 10 06:39:51 PM PDT 24
Finished Jul 10 06:39:56 PM PDT 24
Peak memory 206380 kb
Host smart-0cbee29b-423e-4e5b-a07b-6b5ddad9948f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10950
19408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1095019408
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2924024833
Short name T844
Test name
Test status
Simulation time 162488936 ps
CPU time 0.81 seconds
Started Jul 10 06:39:52 PM PDT 24
Finished Jul 10 06:39:57 PM PDT 24
Peak memory 206376 kb
Host smart-47dd33a5-393e-4de8-9daf-a4ba015b8964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29240
24833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2924024833
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1454109816
Short name T2529
Test name
Test status
Simulation time 152622151 ps
CPU time 0.78 seconds
Started Jul 10 06:39:45 PM PDT 24
Finished Jul 10 06:39:49 PM PDT 24
Peak memory 206288 kb
Host smart-fdf183fa-03b5-4f29-becb-2e35d6f44543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14541
09816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1454109816
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1723331548
Short name T1862
Test name
Test status
Simulation time 212523214 ps
CPU time 0.89 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206384 kb
Host smart-0cd1e945-43fe-4959-89c9-4659cb840811
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1723331548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1723331548
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.87728081
Short name T200
Test name
Test status
Simulation time 205641503 ps
CPU time 0.91 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206376 kb
Host smart-622561bb-8a75-487b-add7-4c4d639dea76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87728
081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.87728081
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.221808165
Short name T94
Test name
Test status
Simulation time 147937639 ps
CPU time 0.78 seconds
Started Jul 10 06:39:46 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 206384 kb
Host smart-c4a82644-780e-4f44-8f5f-e9144526af50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22180
8165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.221808165
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2820786376
Short name T2741
Test name
Test status
Simulation time 48503816 ps
CPU time 0.68 seconds
Started Jul 10 06:39:47 PM PDT 24
Finished Jul 10 06:39:53 PM PDT 24
Peak memory 206344 kb
Host smart-ce8c2a4f-4909-43bc-8d8a-0b13bdc9afef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
86376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2820786376
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.298366609
Short name T2040
Test name
Test status
Simulation time 6787314816 ps
CPU time 15.77 seconds
Started Jul 10 06:39:47 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206900 kb
Host smart-e4c6bc27-9b48-4e5f-9840-05bebeb1219f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29836
6609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.298366609
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2116845244
Short name T2723
Test name
Test status
Simulation time 159573501 ps
CPU time 0.76 seconds
Started Jul 10 06:39:54 PM PDT 24
Finished Jul 10 06:39:59 PM PDT 24
Peak memory 206376 kb
Host smart-446ba23f-5545-4995-be59-3a8ce99d0a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21168
45244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2116845244
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.31877987
Short name T458
Test name
Test status
Simulation time 236024900 ps
CPU time 0.91 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:58 PM PDT 24
Peak memory 206376 kb
Host smart-04a8c919-5343-470e-8cb7-d261c29b9d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877
987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.31877987
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1054849581
Short name T1573
Test name
Test status
Simulation time 16685308499 ps
CPU time 117.23 seconds
Started Jul 10 06:39:51 PM PDT 24
Finished Jul 10 06:41:53 PM PDT 24
Peak memory 206712 kb
Host smart-19eff727-bc29-4021-a936-526cb4241b7b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1054849581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1054849581
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2213388746
Short name T932
Test name
Test status
Simulation time 12182035758 ps
CPU time 61.28 seconds
Started Jul 10 06:39:59 PM PDT 24
Finished Jul 10 06:41:05 PM PDT 24
Peak memory 206644 kb
Host smart-bc49731e-188e-42af-8a3b-d7f48b151ed0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2213388746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2213388746
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3912870007
Short name T2000
Test name
Test status
Simulation time 10790132912 ps
CPU time 64.42 seconds
Started Jul 10 06:39:54 PM PDT 24
Finished Jul 10 06:41:03 PM PDT 24
Peak memory 206684 kb
Host smart-e0668a1b-d58a-4cea-b2f9-2a8252f6ff80
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3912870007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3912870007
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.145363863
Short name T877
Test name
Test status
Simulation time 196769406 ps
CPU time 0.89 seconds
Started Jul 10 06:39:54 PM PDT 24
Finished Jul 10 06:40:00 PM PDT 24
Peak memory 206400 kb
Host smart-1996e032-a650-4090-8ab5-f10153988453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.145363863
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1198573551
Short name T2091
Test name
Test status
Simulation time 195609922 ps
CPU time 0.83 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:58 PM PDT 24
Peak memory 206380 kb
Host smart-0cb3c302-d6e0-4e96-933c-7be06c3177f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11985
73551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1198573551
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1749648661
Short name T1570
Test name
Test status
Simulation time 200023419 ps
CPU time 0.82 seconds
Started Jul 10 06:39:54 PM PDT 24
Finished Jul 10 06:40:00 PM PDT 24
Peak memory 206376 kb
Host smart-a8dc5d00-b599-413c-880a-24dab47358e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
48661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1749648661
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1341162352
Short name T79
Test name
Test status
Simulation time 175368259 ps
CPU time 0.79 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:58 PM PDT 24
Peak memory 206376 kb
Host smart-8089f6d6-90df-422a-be94-bec9146f6e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13411
62352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1341162352
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2627730712
Short name T57
Test name
Test status
Simulation time 365526917 ps
CPU time 1.13 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:58 PM PDT 24
Peak memory 206312 kb
Host smart-c9ab83a0-c61b-4107-b0f2-776a7037ec48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
30712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2627730712
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2430386417
Short name T806
Test name
Test status
Simulation time 188771244 ps
CPU time 0.87 seconds
Started Jul 10 06:39:54 PM PDT 24
Finished Jul 10 06:40:00 PM PDT 24
Peak memory 206384 kb
Host smart-12bb1b69-7697-4523-a195-db40496ddb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303
86417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2430386417
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3455451531
Short name T1335
Test name
Test status
Simulation time 154791008 ps
CPU time 0.74 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:58 PM PDT 24
Peak memory 206360 kb
Host smart-22a66d90-44e6-4b7f-86ba-3697c8b39b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34554
51531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3455451531
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3036875797
Short name T2396
Test name
Test status
Simulation time 160640214 ps
CPU time 0.87 seconds
Started Jul 10 06:39:57 PM PDT 24
Finished Jul 10 06:40:03 PM PDT 24
Peak memory 206376 kb
Host smart-7a5d83d9-dc22-439f-94ea-ce0133801858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30368
75797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3036875797
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3238621337
Short name T1806
Test name
Test status
Simulation time 217147083 ps
CPU time 0.94 seconds
Started Jul 10 06:39:55 PM PDT 24
Finished Jul 10 06:40:01 PM PDT 24
Peak memory 206352 kb
Host smart-7d200dea-c6dd-4dfc-a5f3-3c29d5ac12da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32386
21337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3238621337
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.4106070218
Short name T1240
Test name
Test status
Simulation time 4343540007 ps
CPU time 40.63 seconds
Started Jul 10 06:39:56 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206708 kb
Host smart-b40cbdd6-1fbc-4311-a516-fffbb9c659d7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4106070218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.4106070218
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4280358117
Short name T1748
Test name
Test status
Simulation time 144881355 ps
CPU time 0.75 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:59 PM PDT 24
Peak memory 206380 kb
Host smart-16d17ca5-4a3d-4d3c-9f41-68d859273260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42803
58117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4280358117
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1755117146
Short name T835
Test name
Test status
Simulation time 170762029 ps
CPU time 0.8 seconds
Started Jul 10 06:39:54 PM PDT 24
Finished Jul 10 06:40:00 PM PDT 24
Peak memory 206388 kb
Host smart-febb7531-3c19-49b2-9491-a8c73590d4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
17146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1755117146
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2570068375
Short name T2159
Test name
Test status
Simulation time 1042653925 ps
CPU time 2.17 seconds
Started Jul 10 06:39:54 PM PDT 24
Finished Jul 10 06:40:01 PM PDT 24
Peak memory 206644 kb
Host smart-e06ba6ef-6a32-44ab-af21-a1a7b84033f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25700
68375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2570068375
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.4045791400
Short name T1531
Test name
Test status
Simulation time 4149354391 ps
CPU time 29.55 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:40:28 PM PDT 24
Peak memory 206652 kb
Host smart-c20d1853-b9ce-45ad-b315-40c3df0a7c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40457
91400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.4045791400
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3238231024
Short name T20
Test name
Test status
Simulation time 29384564 ps
CPU time 0.73 seconds
Started Jul 10 06:45:53 PM PDT 24
Finished Jul 10 06:45:54 PM PDT 24
Peak memory 206436 kb
Host smart-fd831df5-d0a2-4c88-8c4c-f8c9737fe0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3238231024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3238231024
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.507726738
Short name T11
Test name
Test status
Simulation time 3655972811 ps
CPU time 5.07 seconds
Started Jul 10 06:45:50 PM PDT 24
Finished Jul 10 06:45:57 PM PDT 24
Peak memory 206396 kb
Host smart-46601bc1-0f9b-47a0-87b8-01453213de88
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=507726738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.507726738
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3561800559
Short name T560
Test name
Test status
Simulation time 13302518457 ps
CPU time 12.82 seconds
Started Jul 10 06:45:51 PM PDT 24
Finished Jul 10 06:46:06 PM PDT 24
Peak memory 206444 kb
Host smart-e7fa8e87-ac58-4f4d-b912-5dfc7f4f302f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3561800559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3561800559
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3086069823
Short name T1453
Test name
Test status
Simulation time 23304789880 ps
CPU time 24.86 seconds
Started Jul 10 06:45:47 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206444 kb
Host smart-eb80ff69-ad52-4316-96fb-22e90701429a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3086069823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3086069823
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3883522249
Short name T1659
Test name
Test status
Simulation time 171052102 ps
CPU time 0.79 seconds
Started Jul 10 06:45:45 PM PDT 24
Finished Jul 10 06:45:50 PM PDT 24
Peak memory 206392 kb
Host smart-badbabe3-9b38-40a2-93a6-7ebc967e72ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38835
22249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3883522249
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.1892711567
Short name T894
Test name
Test status
Simulation time 150402927 ps
CPU time 0.8 seconds
Started Jul 10 06:45:52 PM PDT 24
Finished Jul 10 06:45:54 PM PDT 24
Peak memory 206392 kb
Host smart-80359319-0137-4ba6-b90e-406f1649b86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18927
11567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.1892711567
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1726779437
Short name T2589
Test name
Test status
Simulation time 473970805 ps
CPU time 1.49 seconds
Started Jul 10 06:45:54 PM PDT 24
Finished Jul 10 06:45:57 PM PDT 24
Peak memory 206380 kb
Host smart-6c65528c-9c6a-41a3-a885-f21aa7b0af5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17267
79437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1726779437
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.60271362
Short name T2429
Test name
Test status
Simulation time 971006407 ps
CPU time 2.27 seconds
Started Jul 10 06:45:51 PM PDT 24
Finished Jul 10 06:45:54 PM PDT 24
Peak memory 206628 kb
Host smart-70f67186-4875-4981-bf23-9bea4cbc3d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60271
362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.60271362
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2480317858
Short name T96
Test name
Test status
Simulation time 9512384363 ps
CPU time 20.1 seconds
Started Jul 10 06:45:47 PM PDT 24
Finished Jul 10 06:46:10 PM PDT 24
Peak memory 206632 kb
Host smart-20613c1e-0abc-4c4b-ae4a-f9e3a019c34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24803
17858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2480317858
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3887834428
Short name T875
Test name
Test status
Simulation time 406528803 ps
CPU time 1.18 seconds
Started Jul 10 06:45:45 PM PDT 24
Finished Jul 10 06:45:50 PM PDT 24
Peak memory 206376 kb
Host smart-ef300836-1c1d-49ac-b1ff-62cdefbdb4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38878
34428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3887834428
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.725685973
Short name T46
Test name
Test status
Simulation time 147752971 ps
CPU time 0.75 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206388 kb
Host smart-1a7558ad-be44-4023-bc24-30d7dc78ad22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72568
5973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.725685973
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.828929875
Short name T1022
Test name
Test status
Simulation time 33337134 ps
CPU time 0.63 seconds
Started Jul 10 06:45:56 PM PDT 24
Finished Jul 10 06:45:59 PM PDT 24
Peak memory 206360 kb
Host smart-0e9846ea-88c4-4d69-9800-bc259360451b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82892
9875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.828929875
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3426431389
Short name T2020
Test name
Test status
Simulation time 999060602 ps
CPU time 2.62 seconds
Started Jul 10 06:45:47 PM PDT 24
Finished Jul 10 06:45:52 PM PDT 24
Peak memory 206632 kb
Host smart-5a4e9ec0-da98-44b9-8694-61652f3c41c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34264
31389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3426431389
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.4063711784
Short name T2234
Test name
Test status
Simulation time 268788341 ps
CPU time 1.76 seconds
Started Jul 10 06:46:01 PM PDT 24
Finished Jul 10 06:46:05 PM PDT 24
Peak memory 206592 kb
Host smart-11972fcb-6725-4f37-a18a-7d64f663a723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40637
11784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.4063711784
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3810550214
Short name T2462
Test name
Test status
Simulation time 238552649 ps
CPU time 0.92 seconds
Started Jul 10 06:45:58 PM PDT 24
Finished Jul 10 06:46:01 PM PDT 24
Peak memory 206356 kb
Host smart-2e802728-c8b1-4ca9-97b7-b1dab868bc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38105
50214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3810550214
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2004795184
Short name T1347
Test name
Test status
Simulation time 157773474 ps
CPU time 0.79 seconds
Started Jul 10 06:46:04 PM PDT 24
Finished Jul 10 06:46:07 PM PDT 24
Peak memory 206356 kb
Host smart-0fc7b6d3-efec-4944-856a-7b66eb976345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20047
95184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2004795184
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.373307545
Short name T2077
Test name
Test status
Simulation time 209755385 ps
CPU time 0.9 seconds
Started Jul 10 06:45:54 PM PDT 24
Finished Jul 10 06:45:56 PM PDT 24
Peak memory 206376 kb
Host smart-c555a731-009e-4411-97db-1203acfe5d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330
7545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.373307545
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.3628289385
Short name T1583
Test name
Test status
Simulation time 8809849128 ps
CPU time 31.1 seconds
Started Jul 10 06:46:02 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206688 kb
Host smart-1706cfc1-5b27-4358-a61e-200234a639b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36282
89385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.3628289385
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.3066485667
Short name T638
Test name
Test status
Simulation time 227707920 ps
CPU time 1.02 seconds
Started Jul 10 06:46:01 PM PDT 24
Finished Jul 10 06:46:05 PM PDT 24
Peak memory 206392 kb
Host smart-54bc763d-075c-4e13-9718-7769fe3bfe17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30664
85667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.3066485667
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3175284354
Short name T850
Test name
Test status
Simulation time 23293249377 ps
CPU time 28.06 seconds
Started Jul 10 06:45:57 PM PDT 24
Finished Jul 10 06:46:28 PM PDT 24
Peak memory 206416 kb
Host smart-ae5e6218-a6b2-41c6-ad2e-97222ee74ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31752
84354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3175284354
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.1996804465
Short name T471
Test name
Test status
Simulation time 3311296348 ps
CPU time 3.73 seconds
Started Jul 10 06:45:45 PM PDT 24
Finished Jul 10 06:45:53 PM PDT 24
Peak memory 206456 kb
Host smart-e6314ab8-5691-4c3b-8e37-f1f7f57fc416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19968
04465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1996804465
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1319782475
Short name T2123
Test name
Test status
Simulation time 10067265069 ps
CPU time 283.8 seconds
Started Jul 10 06:45:56 PM PDT 24
Finished Jul 10 06:50:42 PM PDT 24
Peak memory 206712 kb
Host smart-6fec04e6-0548-44f4-a6f3-6482096c2851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197
82475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1319782475
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1854995403
Short name T2126
Test name
Test status
Simulation time 3309412933 ps
CPU time 23.57 seconds
Started Jul 10 06:45:58 PM PDT 24
Finished Jul 10 06:46:24 PM PDT 24
Peak memory 206688 kb
Host smart-44d2bbb3-5de9-4dc5-8cc0-33716ecb2913
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1854995403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1854995403
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.1491270427
Short name T2658
Test name
Test status
Simulation time 239887762 ps
CPU time 0.92 seconds
Started Jul 10 06:45:49 PM PDT 24
Finished Jul 10 06:45:52 PM PDT 24
Peak memory 206396 kb
Host smart-a63ef0bf-fd05-4148-8fe4-a5c28b845e04
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1491270427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.1491270427
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2628251531
Short name T833
Test name
Test status
Simulation time 210965065 ps
CPU time 0.86 seconds
Started Jul 10 06:45:51 PM PDT 24
Finished Jul 10 06:45:54 PM PDT 24
Peak memory 206376 kb
Host smart-6751cd30-7f15-4c20-8a99-a9244662110b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26282
51531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2628251531
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.354908805
Short name T1120
Test name
Test status
Simulation time 5765362039 ps
CPU time 39.45 seconds
Started Jul 10 06:46:01 PM PDT 24
Finished Jul 10 06:46:44 PM PDT 24
Peak memory 206668 kb
Host smart-05f08f79-1cf3-4803-9585-4fca69b06f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35490
8805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.354908805
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.415612701
Short name T160
Test name
Test status
Simulation time 5744623863 ps
CPU time 158.23 seconds
Started Jul 10 06:45:47 PM PDT 24
Finished Jul 10 06:48:28 PM PDT 24
Peak memory 206620 kb
Host smart-50cd7ebc-1b6c-463e-8c29-ec2c337304f5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=415612701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.415612701
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3810881714
Short name T1843
Test name
Test status
Simulation time 169038865 ps
CPU time 0.8 seconds
Started Jul 10 06:45:56 PM PDT 24
Finished Jul 10 06:45:59 PM PDT 24
Peak memory 206372 kb
Host smart-58d3c8b8-d4a6-4c3d-aecb-f9da61a1f836
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3810881714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3810881714
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1790009191
Short name T2169
Test name
Test status
Simulation time 143602255 ps
CPU time 0.77 seconds
Started Jul 10 06:45:45 PM PDT 24
Finished Jul 10 06:45:50 PM PDT 24
Peak memory 206368 kb
Host smart-3e4bb9c7-f07e-42dd-8a9f-04d45406d679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17900
09191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1790009191
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2787389995
Short name T146
Test name
Test status
Simulation time 209321028 ps
CPU time 0.88 seconds
Started Jul 10 06:45:52 PM PDT 24
Finished Jul 10 06:45:54 PM PDT 24
Peak memory 206396 kb
Host smart-aa6b1070-da42-4589-b003-491d3a9b48fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27873
89995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2787389995
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1279390512
Short name T1636
Test name
Test status
Simulation time 258612811 ps
CPU time 0.9 seconds
Started Jul 10 06:45:55 PM PDT 24
Finished Jul 10 06:45:57 PM PDT 24
Peak memory 206328 kb
Host smart-b6b3dd39-7135-4207-8882-7e8f98f66fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
90512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1279390512
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1174100231
Short name T1427
Test name
Test status
Simulation time 180542653 ps
CPU time 0.84 seconds
Started Jul 10 06:45:56 PM PDT 24
Finished Jul 10 06:45:59 PM PDT 24
Peak memory 206384 kb
Host smart-9333fc65-485e-471b-8374-fc9391fafb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11741
00231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1174100231
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2911205070
Short name T2528
Test name
Test status
Simulation time 183077319 ps
CPU time 0.83 seconds
Started Jul 10 06:45:47 PM PDT 24
Finished Jul 10 06:45:51 PM PDT 24
Peak memory 206380 kb
Host smart-4e45b702-3b68-4209-8c87-728cc5c2a540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29112
05070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2911205070
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3047774288
Short name T2587
Test name
Test status
Simulation time 160494969 ps
CPU time 0.79 seconds
Started Jul 10 06:45:44 PM PDT 24
Finished Jul 10 06:45:49 PM PDT 24
Peak memory 206384 kb
Host smart-095daad7-c28c-4c40-9da5-86449525f8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30477
74288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3047774288
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2371516262
Short name T2300
Test name
Test status
Simulation time 237342468 ps
CPU time 0.97 seconds
Started Jul 10 06:45:56 PM PDT 24
Finished Jul 10 06:45:59 PM PDT 24
Peak memory 206396 kb
Host smart-0634a1db-362f-4610-a160-db053b5e3dff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2371516262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2371516262
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.215039194
Short name T1902
Test name
Test status
Simulation time 179435345 ps
CPU time 0.89 seconds
Started Jul 10 06:45:46 PM PDT 24
Finished Jul 10 06:45:50 PM PDT 24
Peak memory 206384 kb
Host smart-c77f82cd-0c98-4794-a132-47dd2e1c6f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21503
9194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.215039194
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1899234281
Short name T2468
Test name
Test status
Simulation time 42103149 ps
CPU time 0.67 seconds
Started Jul 10 06:45:57 PM PDT 24
Finished Jul 10 06:46:00 PM PDT 24
Peak memory 206368 kb
Host smart-56796d88-9fe1-41f8-aafd-97affd2f109d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18992
34281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1899234281
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3897188826
Short name T276
Test name
Test status
Simulation time 22153073068 ps
CPU time 52.01 seconds
Started Jul 10 06:45:59 PM PDT 24
Finished Jul 10 06:46:53 PM PDT 24
Peak memory 206688 kb
Host smart-964f2b35-dc42-4a51-836f-15fe88917536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38971
88826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3897188826
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1339473257
Short name T1530
Test name
Test status
Simulation time 159590648 ps
CPU time 0.84 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:46:11 PM PDT 24
Peak memory 206372 kb
Host smart-b0bc7f3d-02ea-4c95-966c-1be7833eb5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
73257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1339473257
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2824230150
Short name T1974
Test name
Test status
Simulation time 261924866 ps
CPU time 0.96 seconds
Started Jul 10 06:45:57 PM PDT 24
Finished Jul 10 06:46:01 PM PDT 24
Peak memory 206372 kb
Host smart-0ec98cbd-e215-45d0-b794-460f017f9cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28242
30150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2824230150
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2615180238
Short name T1369
Test name
Test status
Simulation time 299315968 ps
CPU time 0.92 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:46:12 PM PDT 24
Peak memory 206364 kb
Host smart-3a1c4a57-6b40-42d4-a0bd-5ec16a8a205e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26151
80238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2615180238
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2383903727
Short name T2470
Test name
Test status
Simulation time 150284589 ps
CPU time 0.85 seconds
Started Jul 10 06:46:10 PM PDT 24
Finished Jul 10 06:46:15 PM PDT 24
Peak memory 206392 kb
Host smart-d0e55bde-0222-436b-bcc5-ec4b3b3e1e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23839
03727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2383903727
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2459468202
Short name T614
Test name
Test status
Simulation time 147052343 ps
CPU time 0.79 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:10 PM PDT 24
Peak memory 206368 kb
Host smart-77cb6f8a-8892-49d1-b6f4-4a7b385ea824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24594
68202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2459468202
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.226499077
Short name T2200
Test name
Test status
Simulation time 163850424 ps
CPU time 0.79 seconds
Started Jul 10 06:45:57 PM PDT 24
Finished Jul 10 06:46:00 PM PDT 24
Peak memory 206384 kb
Host smart-3ac4d87d-5c69-4633-94e3-eb4dd79ce02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22649
9077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.226499077
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1892987966
Short name T1473
Test name
Test status
Simulation time 147767301 ps
CPU time 0.82 seconds
Started Jul 10 06:46:02 PM PDT 24
Finished Jul 10 06:46:06 PM PDT 24
Peak memory 206396 kb
Host smart-4fd1a540-6b3b-4444-b4b0-6ec560da9b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18929
87966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1892987966
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1984745754
Short name T469
Test name
Test status
Simulation time 246147230 ps
CPU time 0.93 seconds
Started Jul 10 06:45:56 PM PDT 24
Finished Jul 10 06:45:59 PM PDT 24
Peak memory 206384 kb
Host smart-63be89ea-370b-4e35-8f5f-f902e2df961d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19847
45754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1984745754
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2367973985
Short name T2314
Test name
Test status
Simulation time 3856401206 ps
CPU time 103.17 seconds
Started Jul 10 06:46:02 PM PDT 24
Finished Jul 10 06:47:48 PM PDT 24
Peak memory 206604 kb
Host smart-dd910e06-b863-4e14-beac-2f74abe66fdd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2367973985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2367973985
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3491176999
Short name T1230
Test name
Test status
Simulation time 165798140 ps
CPU time 0.84 seconds
Started Jul 10 06:46:09 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206396 kb
Host smart-8cf5bd4e-283d-4f27-8109-504c19fb4c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34911
76999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3491176999
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1618068983
Short name T1028
Test name
Test status
Simulation time 148252148 ps
CPU time 0.81 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:46:11 PM PDT 24
Peak memory 206340 kb
Host smart-bde39f10-4f08-4754-bcbc-66345a015bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
68983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1618068983
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.769780825
Short name T2117
Test name
Test status
Simulation time 683469068 ps
CPU time 1.68 seconds
Started Jul 10 06:45:58 PM PDT 24
Finished Jul 10 06:46:02 PM PDT 24
Peak memory 206560 kb
Host smart-ce6836d6-bc65-48a8-a931-e6c40368b4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76978
0825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.769780825
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3580693166
Short name T2399
Test name
Test status
Simulation time 4000606460 ps
CPU time 34.86 seconds
Started Jul 10 06:46:00 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206648 kb
Host smart-5d548032-e81a-41f3-bc2f-5d3abb390c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
93166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3580693166
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3605496712
Short name T2380
Test name
Test status
Simulation time 91971116 ps
CPU time 0.76 seconds
Started Jul 10 06:46:04 PM PDT 24
Finished Jul 10 06:46:07 PM PDT 24
Peak memory 206432 kb
Host smart-6504699f-c04e-4beb-b57e-962f0485b5b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3605496712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3605496712
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2921753668
Short name T2642
Test name
Test status
Simulation time 3994829571 ps
CPU time 5.4 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206444 kb
Host smart-88404958-990d-4cd0-b905-f39d0ac9e5fe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2921753668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2921753668
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2457434833
Short name T693
Test name
Test status
Simulation time 13391026204 ps
CPU time 14.22 seconds
Started Jul 10 06:45:58 PM PDT 24
Finished Jul 10 06:46:15 PM PDT 24
Peak memory 206700 kb
Host smart-8bfe3794-3798-49b5-9f00-3fb3f30fa0f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2457434833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2457434833
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3767729585
Short name T1249
Test name
Test status
Simulation time 23421357262 ps
CPU time 27.94 seconds
Started Jul 10 06:45:59 PM PDT 24
Finished Jul 10 06:46:29 PM PDT 24
Peak memory 206448 kb
Host smart-4193203b-9984-4422-bcb3-8564275dd925
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3767729585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3767729585
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1394788728
Short name T1953
Test name
Test status
Simulation time 157095412 ps
CPU time 0.81 seconds
Started Jul 10 06:46:11 PM PDT 24
Finished Jul 10 06:46:16 PM PDT 24
Peak memory 206388 kb
Host smart-dd5245b8-15a6-441f-885a-e58ba5529b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13947
88728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1394788728
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1073339270
Short name T769
Test name
Test status
Simulation time 153754127 ps
CPU time 0.77 seconds
Started Jul 10 06:46:14 PM PDT 24
Finished Jul 10 06:46:20 PM PDT 24
Peak memory 206372 kb
Host smart-159850f0-5556-4488-96ba-0ef0f82e2b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10733
39270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1073339270
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.4193653876
Short name T425
Test name
Test status
Simulation time 221675228 ps
CPU time 0.92 seconds
Started Jul 10 06:45:58 PM PDT 24
Finished Jul 10 06:46:02 PM PDT 24
Peak memory 206392 kb
Host smart-8cf434f0-62f4-437f-b08b-d6f7436075d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41936
53876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.4193653876
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3406756629
Short name T1342
Test name
Test status
Simulation time 375464072 ps
CPU time 1.1 seconds
Started Jul 10 06:46:11 PM PDT 24
Finished Jul 10 06:46:16 PM PDT 24
Peak memory 206380 kb
Host smart-890ad79c-1e0e-4a37-bd81-ac886f1f7317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
56629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3406756629
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.3078137457
Short name T1172
Test name
Test status
Simulation time 14447085068 ps
CPU time 28.24 seconds
Started Jul 10 06:46:09 PM PDT 24
Finished Jul 10 06:46:41 PM PDT 24
Peak memory 206704 kb
Host smart-35617126-c64e-4b02-bfc1-8b5d621f26a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781
37457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3078137457
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.9372316
Short name T1254
Test name
Test status
Simulation time 393633283 ps
CPU time 1.22 seconds
Started Jul 10 06:46:03 PM PDT 24
Finished Jul 10 06:46:07 PM PDT 24
Peak memory 206404 kb
Host smart-7abc1cfc-383a-4ade-b602-0579056c3276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93723
16 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.9372316
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1945383384
Short name T1168
Test name
Test status
Simulation time 187499873 ps
CPU time 0.9 seconds
Started Jul 10 06:46:01 PM PDT 24
Finished Jul 10 06:46:05 PM PDT 24
Peak memory 206380 kb
Host smart-0153ce10-f631-4bdc-ab95-dc9d5b7507c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
83384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1945383384
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3753930785
Short name T1247
Test name
Test status
Simulation time 50204632 ps
CPU time 0.68 seconds
Started Jul 10 06:45:58 PM PDT 24
Finished Jul 10 06:46:02 PM PDT 24
Peak memory 206372 kb
Host smart-65d23f69-5c2b-485b-b09c-9b7afff6723d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37539
30785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3753930785
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3517342131
Short name T1983
Test name
Test status
Simulation time 842908166 ps
CPU time 2.04 seconds
Started Jul 10 06:45:59 PM PDT 24
Finished Jul 10 06:46:03 PM PDT 24
Peak memory 206632 kb
Host smart-0b9cab94-da90-406c-8af2-dfeea97dc33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35173
42131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3517342131
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3273000623
Short name T2728
Test name
Test status
Simulation time 194574521 ps
CPU time 1.97 seconds
Started Jul 10 06:46:02 PM PDT 24
Finished Jul 10 06:46:06 PM PDT 24
Peak memory 206624 kb
Host smart-403756f1-54f6-46a1-a8ef-e0d1b51a5ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32730
00623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3273000623
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.64293813
Short name T2497
Test name
Test status
Simulation time 217917998 ps
CPU time 0.91 seconds
Started Jul 10 06:45:59 PM PDT 24
Finished Jul 10 06:46:03 PM PDT 24
Peak memory 206360 kb
Host smart-ece7a312-ee82-4118-b135-598fef9a1454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64293
813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.64293813
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.4133940955
Short name T2191
Test name
Test status
Simulation time 161348901 ps
CPU time 0.88 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206372 kb
Host smart-16a37ce4-21f5-4cdb-85be-74fddf16cc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41339
40955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.4133940955
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2503295227
Short name T1115
Test name
Test status
Simulation time 235172344 ps
CPU time 0.93 seconds
Started Jul 10 06:46:00 PM PDT 24
Finished Jul 10 06:46:03 PM PDT 24
Peak memory 206564 kb
Host smart-cded1e34-b72c-45a2-9a71-1a2fb5343133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25032
95227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2503295227
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2036835168
Short name T77
Test name
Test status
Simulation time 8907000100 ps
CPU time 86 seconds
Started Jul 10 06:46:00 PM PDT 24
Finished Jul 10 06:47:29 PM PDT 24
Peak memory 206600 kb
Host smart-53de524c-3673-4912-af07-c70b5e112ad2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2036835168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2036835168
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.1871503715
Short name T1038
Test name
Test status
Simulation time 6743448167 ps
CPU time 25.77 seconds
Started Jul 10 06:46:01 PM PDT 24
Finished Jul 10 06:46:29 PM PDT 24
Peak memory 206652 kb
Host smart-a2742ffe-c148-4eb9-b7f9-33b1b154affe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18715
03715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.1871503715
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1542185298
Short name T1804
Test name
Test status
Simulation time 285766094 ps
CPU time 0.95 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:10 PM PDT 24
Peak memory 206368 kb
Host smart-896a7b3c-fa79-4ab5-97c3-53c52ee8ff85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15421
85298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1542185298
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1501162994
Short name T1179
Test name
Test status
Simulation time 23274868406 ps
CPU time 26.59 seconds
Started Jul 10 06:45:59 PM PDT 24
Finished Jul 10 06:46:28 PM PDT 24
Peak memory 206432 kb
Host smart-70a1d1fa-ed84-48f9-aacd-16e6380e030e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15011
62994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1501162994
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2031593822
Short name T1550
Test name
Test status
Simulation time 3312881561 ps
CPU time 4.1 seconds
Started Jul 10 06:46:11 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206440 kb
Host smart-edb59ed5-a9a6-4fcf-89d1-cbebb7fb09cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20315
93822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2031593822
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.658132759
Short name T1266
Test name
Test status
Simulation time 9206075225 ps
CPU time 85.04 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:47:34 PM PDT 24
Peak memory 206736 kb
Host smart-1e28a2e1-a3bf-4c5f-991c-7a125aa6fe6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65813
2759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.658132759
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3292991650
Short name T890
Test name
Test status
Simulation time 4432941178 ps
CPU time 43.37 seconds
Started Jul 10 06:46:09 PM PDT 24
Finished Jul 10 06:46:57 PM PDT 24
Peak memory 206656 kb
Host smart-eda857ab-e1ff-4356-9376-887ac6893d03
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3292991650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3292991650
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1391136251
Short name T689
Test name
Test status
Simulation time 254908144 ps
CPU time 0.94 seconds
Started Jul 10 06:46:01 PM PDT 24
Finished Jul 10 06:46:04 PM PDT 24
Peak memory 206388 kb
Host smart-ff594ca0-f292-4a8e-9afe-ba58cd3f0b67
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1391136251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1391136251
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1159458469
Short name T1821
Test name
Test status
Simulation time 197012258 ps
CPU time 0.86 seconds
Started Jul 10 06:46:09 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206368 kb
Host smart-553e1ac3-e8ef-4874-b72f-3a63fbedfca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11594
58469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1159458469
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.554830735
Short name T149
Test name
Test status
Simulation time 6588402934 ps
CPU time 59.32 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:47:09 PM PDT 24
Peak memory 206724 kb
Host smart-f7d8060e-a74f-43ae-8f55-96820a027819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55483
0735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.554830735
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3538553323
Short name T1074
Test name
Test status
Simulation time 3920100958 ps
CPU time 36.92 seconds
Started Jul 10 06:46:04 PM PDT 24
Finished Jul 10 06:46:43 PM PDT 24
Peak memory 206624 kb
Host smart-ce3470ed-35d4-4f76-a794-828876f3a1b0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3538553323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3538553323
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2953885187
Short name T521
Test name
Test status
Simulation time 161279455 ps
CPU time 0.82 seconds
Started Jul 10 06:46:05 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206356 kb
Host smart-0bab4bb8-9a65-407d-97d8-c46d05ce7232
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2953885187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2953885187
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1257996592
Short name T1016
Test name
Test status
Simulation time 154023448 ps
CPU time 0.79 seconds
Started Jul 10 06:46:03 PM PDT 24
Finished Jul 10 06:46:06 PM PDT 24
Peak memory 206376 kb
Host smart-70b68b4e-2e23-4899-adc2-5d49880faddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12579
96592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1257996592
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2934159542
Short name T122
Test name
Test status
Simulation time 157274516 ps
CPU time 0.79 seconds
Started Jul 10 06:46:10 PM PDT 24
Finished Jul 10 06:46:16 PM PDT 24
Peak memory 206352 kb
Host smart-1c754f7b-5cbd-40a4-a425-5ad232828c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29341
59542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2934159542
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2846743932
Short name T1109
Test name
Test status
Simulation time 208033193 ps
CPU time 0.89 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:10 PM PDT 24
Peak memory 206376 kb
Host smart-a6411233-a8c2-412a-a6fb-c4424e2f82f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28467
43932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2846743932
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1543547808
Short name T751
Test name
Test status
Simulation time 176858537 ps
CPU time 0.8 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:18 PM PDT 24
Peak memory 206388 kb
Host smart-81d2a7a8-6898-4072-ae0c-6640d5f64f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15435
47808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1543547808
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1556625472
Short name T1359
Test name
Test status
Simulation time 187801243 ps
CPU time 0.84 seconds
Started Jul 10 06:46:01 PM PDT 24
Finished Jul 10 06:46:05 PM PDT 24
Peak memory 206368 kb
Host smart-402a216d-cf75-4988-915a-92a8605133e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
25472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1556625472
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2713861935
Short name T1004
Test name
Test status
Simulation time 173500847 ps
CPU time 0.81 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206384 kb
Host smart-295c18a1-ae2b-4049-a94c-972a0d42caf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27138
61935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2713861935
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3207957289
Short name T814
Test name
Test status
Simulation time 220394496 ps
CPU time 0.91 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:46:10 PM PDT 24
Peak memory 206392 kb
Host smart-c07be814-b808-49ae-af6e-2888dd6ab5f8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3207957289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3207957289
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3993931721
Short name T941
Test name
Test status
Simulation time 155922815 ps
CPU time 0.8 seconds
Started Jul 10 06:46:08 PM PDT 24
Finished Jul 10 06:46:13 PM PDT 24
Peak memory 206388 kb
Host smart-d02ec5da-4ac9-4152-b013-0d754b3912f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39939
31721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3993931721
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1187148282
Short name T699
Test name
Test status
Simulation time 86046530 ps
CPU time 0.71 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206340 kb
Host smart-9fdbffe2-54e4-4995-972b-6b8e802a9269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11871
48282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1187148282
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.758885865
Short name T246
Test name
Test status
Simulation time 21798150322 ps
CPU time 50.55 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 214872 kb
Host smart-6f401d09-2ebf-4b93-9db4-7fc2f2825cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75888
5865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.758885865
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2261876557
Short name T1705
Test name
Test status
Simulation time 180796055 ps
CPU time 0.85 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206364 kb
Host smart-9f9b236f-8681-4870-a3f1-3e05a690b66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22618
76557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2261876557
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3542700221
Short name T776
Test name
Test status
Simulation time 207508099 ps
CPU time 0.88 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206372 kb
Host smart-0653f220-4a55-41e6-9578-a5e87eb9cb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35427
00221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3542700221
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1020134919
Short name T2675
Test name
Test status
Simulation time 187835981 ps
CPU time 0.86 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206376 kb
Host smart-13a1e24b-bf70-4280-bd20-474bb3357626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10201
34919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1020134919
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.301295331
Short name T1757
Test name
Test status
Simulation time 167828095 ps
CPU time 0.87 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206372 kb
Host smart-6595f373-b030-463e-a1ce-4a14ee29396a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30129
5331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.301295331
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2180611502
Short name T1332
Test name
Test status
Simulation time 178883011 ps
CPU time 0.83 seconds
Started Jul 10 06:46:05 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206376 kb
Host smart-a77b1058-12e0-4148-81dd-9aad2b29d61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21806
11502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2180611502
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2647372874
Short name T2058
Test name
Test status
Simulation time 155825212 ps
CPU time 0.8 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:46:11 PM PDT 24
Peak memory 206372 kb
Host smart-a0a9cc63-d018-4632-abaa-7caf5fd0442e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26473
72874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2647372874
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.4165072511
Short name T467
Test name
Test status
Simulation time 166496811 ps
CPU time 0.87 seconds
Started Jul 10 06:46:09 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206356 kb
Host smart-f277da95-6937-4e34-89d9-ec9a2d8f2e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41650
72511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.4165072511
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1016695589
Short name T1006
Test name
Test status
Simulation time 221084356 ps
CPU time 1.07 seconds
Started Jul 10 06:46:09 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206388 kb
Host smart-2f4496bb-9c51-4fcf-982b-e657099b68f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166
95589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1016695589
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2864756534
Short name T1224
Test name
Test status
Simulation time 5863641681 ps
CPU time 53.76 seconds
Started Jul 10 06:46:02 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206580 kb
Host smart-5ed5a66c-c0d7-4695-b2ae-d613caa9b491
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2864756534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2864756534
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.4074137418
Short name T461
Test name
Test status
Simulation time 165925952 ps
CPU time 0.78 seconds
Started Jul 10 06:46:00 PM PDT 24
Finished Jul 10 06:46:03 PM PDT 24
Peak memory 206396 kb
Host smart-6c9ccf85-8138-4ad6-84b1-1aefe319d756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40741
37418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.4074137418
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2629017669
Short name T992
Test name
Test status
Simulation time 194827562 ps
CPU time 0.79 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:17 PM PDT 24
Peak memory 206372 kb
Host smart-5e62aa25-ac41-4e1c-a5b5-173f62d4924c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26290
17669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2629017669
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.70269553
Short name T322
Test name
Test status
Simulation time 264082039 ps
CPU time 0.97 seconds
Started Jul 10 06:46:11 PM PDT 24
Finished Jul 10 06:46:16 PM PDT 24
Peak memory 206360 kb
Host smart-188259be-c767-4d20-a4ec-2844261ef889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70269
553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.70269553
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2597630624
Short name T701
Test name
Test status
Simulation time 7164508773 ps
CPU time 199.65 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:49:29 PM PDT 24
Peak memory 206108 kb
Host smart-3a8d6e91-bbbd-4104-8ead-b7fe020d84ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25976
30624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2597630624
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1310756267
Short name T2282
Test name
Test status
Simulation time 38158639 ps
CPU time 0.67 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:17 PM PDT 24
Peak memory 206424 kb
Host smart-6c2d01c7-168b-4408-bbb5-55a03bd3ad09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1310756267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1310756267
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1462156885
Short name T431
Test name
Test status
Simulation time 3605681108 ps
CPU time 4.21 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:13 PM PDT 24
Peak memory 206444 kb
Host smart-b794df20-786d-4e6a-b033-a679bae87ff6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1462156885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1462156885
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1051684850
Short name T1523
Test name
Test status
Simulation time 13343183004 ps
CPU time 13.12 seconds
Started Jul 10 06:46:10 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206456 kb
Host smart-b1705c73-8623-4219-9556-84ecb2fe60c7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1051684850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1051684850
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3153371452
Short name T2164
Test name
Test status
Simulation time 23290977325 ps
CPU time 28.91 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:47 PM PDT 24
Peak memory 206644 kb
Host smart-ec2ae5be-09e8-45aa-b524-8052c8304276
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3153371452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3153371452
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1590857843
Short name T2165
Test name
Test status
Simulation time 176972231 ps
CPU time 0.84 seconds
Started Jul 10 06:46:10 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206376 kb
Host smart-18504706-e96a-43ca-b46b-bfc3cda2150e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
57843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1590857843
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3248048260
Short name T775
Test name
Test status
Simulation time 156493246 ps
CPU time 0.78 seconds
Started Jul 10 06:46:04 PM PDT 24
Finished Jul 10 06:46:07 PM PDT 24
Peak memory 206380 kb
Host smart-9a766573-31e6-44af-93d7-62e30b21e121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32480
48260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3248048260
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1716199031
Short name T2579
Test name
Test status
Simulation time 437408774 ps
CPU time 1.42 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:46:11 PM PDT 24
Peak memory 205880 kb
Host smart-d7d496c6-f643-4239-8926-14581e18896f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17161
99031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1716199031
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1449883628
Short name T841
Test name
Test status
Simulation time 1054444551 ps
CPU time 2.42 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:46:12 PM PDT 24
Peak memory 206576 kb
Host smart-7d5d7650-ab63-4e86-85bb-aa95eb09b4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14498
83628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1449883628
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1828408108
Short name T2238
Test name
Test status
Simulation time 17790096911 ps
CPU time 37.18 seconds
Started Jul 10 06:45:58 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206632 kb
Host smart-5b76db3a-49a8-46f8-b084-c7e139ce4261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
08108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1828408108
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.1824209828
Short name T2309
Test name
Test status
Simulation time 368349528 ps
CPU time 1.08 seconds
Started Jul 10 06:46:07 PM PDT 24
Finished Jul 10 06:46:11 PM PDT 24
Peak memory 206392 kb
Host smart-2be6f1d0-553d-41bb-b0bf-ad2ab9605d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242
09828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.1824209828
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3419328942
Short name T728
Test name
Test status
Simulation time 184882138 ps
CPU time 0.82 seconds
Started Jul 10 06:46:09 PM PDT 24
Finished Jul 10 06:46:13 PM PDT 24
Peak memory 206380 kb
Host smart-2da6c735-9a4b-4415-b704-2e1a375ac197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34193
28942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3419328942
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2409061479
Short name T964
Test name
Test status
Simulation time 36574189 ps
CPU time 0.66 seconds
Started Jul 10 06:46:06 PM PDT 24
Finished Jul 10 06:46:09 PM PDT 24
Peak memory 206352 kb
Host smart-59caf97c-375a-4988-acac-4ba70a2ad7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24090
61479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2409061479
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3541788058
Short name T1623
Test name
Test status
Simulation time 776402426 ps
CPU time 1.96 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:20 PM PDT 24
Peak memory 206636 kb
Host smart-f9d97cc0-2f92-435d-9f1a-cba77e314abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
88058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3541788058
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.4169748555
Short name T1845
Test name
Test status
Simulation time 189218210 ps
CPU time 1.55 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:18 PM PDT 24
Peak memory 206588 kb
Host smart-00ad0365-ce9f-46a0-8f3a-ef736dc6acea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41697
48555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.4169748555
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2133716522
Short name T490
Test name
Test status
Simulation time 171562490 ps
CPU time 0.84 seconds
Started Jul 10 06:46:17 PM PDT 24
Finished Jul 10 06:46:23 PM PDT 24
Peak memory 206404 kb
Host smart-6e62e2dd-3b32-40b3-8891-75c8315df248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21337
16522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2133716522
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2447720661
Short name T845
Test name
Test status
Simulation time 166545090 ps
CPU time 0.81 seconds
Started Jul 10 06:46:15 PM PDT 24
Finished Jul 10 06:46:21 PM PDT 24
Peak memory 206388 kb
Host smart-2cad8886-450e-4c36-9ac2-da1299dd69d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24477
20661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2447720661
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.195878500
Short name T885
Test name
Test status
Simulation time 188303205 ps
CPU time 0.88 seconds
Started Jul 10 06:46:09 PM PDT 24
Finished Jul 10 06:46:14 PM PDT 24
Peak memory 206372 kb
Host smart-a77bb229-6607-4316-8fa9-d8ab3d086507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19587
8500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.195878500
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.4090831543
Short name T1264
Test name
Test status
Simulation time 5453178832 ps
CPU time 40.07 seconds
Started Jul 10 06:46:14 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 206660 kb
Host smart-b0d7e772-747e-4eab-88aa-909479ee3df8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4090831543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.4090831543
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.1561821696
Short name T1408
Test name
Test status
Simulation time 3846759588 ps
CPU time 33.79 seconds
Started Jul 10 06:46:08 PM PDT 24
Finished Jul 10 06:46:46 PM PDT 24
Peak memory 206592 kb
Host smart-805262a9-c005-4163-a086-8563dbfd7753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618
21696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.1561821696
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.238026668
Short name T1182
Test name
Test status
Simulation time 237046066 ps
CPU time 0.95 seconds
Started Jul 10 06:46:11 PM PDT 24
Finished Jul 10 06:46:16 PM PDT 24
Peak memory 206364 kb
Host smart-31c539de-a78c-43e7-98e9-4c5f8c136682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23802
6668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.238026668
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1880716320
Short name T1430
Test name
Test status
Simulation time 23294896607 ps
CPU time 26.4 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:45 PM PDT 24
Peak memory 206452 kb
Host smart-af2e662e-d6c0-41b0-a8de-88b47f419b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18807
16320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1880716320
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.88590561
Short name T574
Test name
Test status
Simulation time 3347365009 ps
CPU time 4.32 seconds
Started Jul 10 06:46:14 PM PDT 24
Finished Jul 10 06:46:24 PM PDT 24
Peak memory 206464 kb
Host smart-cb51365e-3c50-44c7-8d10-32dc9a0bfd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88590
561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.88590561
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.985930199
Short name T2679
Test name
Test status
Simulation time 8514554194 ps
CPU time 245.26 seconds
Started Jul 10 06:46:19 PM PDT 24
Finished Jul 10 06:50:30 PM PDT 24
Peak memory 206752 kb
Host smart-4c32022d-20dc-4ec7-ae4f-375741f15a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98593
0199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.985930199
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1675141686
Short name T2284
Test name
Test status
Simulation time 4202557750 ps
CPU time 113.36 seconds
Started Jul 10 06:46:17 PM PDT 24
Finished Jul 10 06:48:16 PM PDT 24
Peak memory 206648 kb
Host smart-f22e83be-ac8c-4f91-8967-a038a378293f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1675141686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1675141686
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.306064934
Short name T1825
Test name
Test status
Simulation time 264985658 ps
CPU time 0.94 seconds
Started Jul 10 06:46:17 PM PDT 24
Finished Jul 10 06:46:23 PM PDT 24
Peak memory 206404 kb
Host smart-268958eb-3c68-481c-ab30-efd5ae9af7b7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=306064934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.306064934
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1975431172
Short name T1526
Test name
Test status
Simulation time 190884413 ps
CPU time 0.84 seconds
Started Jul 10 06:46:17 PM PDT 24
Finished Jul 10 06:46:23 PM PDT 24
Peak memory 206408 kb
Host smart-35abb7a1-90b7-42b7-a17a-377b7014b9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
31172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1975431172
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2438618647
Short name T2553
Test name
Test status
Simulation time 3612645800 ps
CPU time 33.96 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:53 PM PDT 24
Peak memory 206660 kb
Host smart-f03e24f8-84d3-4bf1-a24e-1ab663262b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24386
18647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2438618647
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.2609150555
Short name T771
Test name
Test status
Simulation time 4390855756 ps
CPU time 32.99 seconds
Started Jul 10 06:46:11 PM PDT 24
Finished Jul 10 06:46:48 PM PDT 24
Peak memory 206724 kb
Host smart-1db8fadd-b2a0-4abf-b3d1-882c87b64616
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2609150555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2609150555
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.390638109
Short name T2653
Test name
Test status
Simulation time 156897228 ps
CPU time 0.76 seconds
Started Jul 10 06:46:16 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206404 kb
Host smart-2d29cb8e-ba85-42ef-af71-2198d808a282
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=390638109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.390638109
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1010752590
Short name T463
Test name
Test status
Simulation time 140199443 ps
CPU time 0.76 seconds
Started Jul 10 06:46:15 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206376 kb
Host smart-5e684427-5de5-4bc0-a4ce-639e1574f645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10107
52590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1010752590
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1336298481
Short name T2646
Test name
Test status
Simulation time 165907846 ps
CPU time 0.79 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206376 kb
Host smart-511626ae-6ccd-47cd-855c-4f58064964e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13362
98481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1336298481
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.4276351123
Short name T452
Test name
Test status
Simulation time 181001840 ps
CPU time 0.83 seconds
Started Jul 10 06:46:15 PM PDT 24
Finished Jul 10 06:46:21 PM PDT 24
Peak memory 206372 kb
Host smart-372e8507-72a0-472e-8ed9-707605a3b78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42763
51123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.4276351123
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.639987246
Short name T28
Test name
Test status
Simulation time 207717672 ps
CPU time 0.93 seconds
Started Jul 10 06:46:16 PM PDT 24
Finished Jul 10 06:46:23 PM PDT 24
Peak memory 206372 kb
Host smart-5fea4039-1b2a-49d2-a35f-c7f668c843ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63998
7246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.639987246
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2618015200
Short name T867
Test name
Test status
Simulation time 263790115 ps
CPU time 0.88 seconds
Started Jul 10 06:46:15 PM PDT 24
Finished Jul 10 06:46:21 PM PDT 24
Peak memory 206376 kb
Host smart-8a5e4da1-2647-4177-954e-48940b4260e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26180
15200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2618015200
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.162372642
Short name T1608
Test name
Test status
Simulation time 158694494 ps
CPU time 0.77 seconds
Started Jul 10 06:46:16 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206396 kb
Host smart-2c844207-0a33-48a0-b838-7c5fad604687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16237
2642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.162372642
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3899146150
Short name T1386
Test name
Test status
Simulation time 212623476 ps
CPU time 0.91 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206404 kb
Host smart-40963015-4f64-4bab-94c1-1b56d6e38967
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3899146150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3899146150
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.985018371
Short name T2517
Test name
Test status
Simulation time 140433184 ps
CPU time 0.73 seconds
Started Jul 10 06:46:15 PM PDT 24
Finished Jul 10 06:46:21 PM PDT 24
Peak memory 206384 kb
Host smart-738f019a-f918-4977-9ce4-558aee41d277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98501
8371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.985018371
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3144539357
Short name T1976
Test name
Test status
Simulation time 39611918 ps
CPU time 0.66 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206356 kb
Host smart-0a97d6e0-7840-4f6d-a5d1-9324a29b5c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31445
39357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3144539357
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1102400243
Short name T1698
Test name
Test status
Simulation time 6983901371 ps
CPU time 17.18 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:34 PM PDT 24
Peak memory 206672 kb
Host smart-b540266f-1042-47a0-a8cb-ac75e79f8b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11024
00243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1102400243
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2798902940
Short name T658
Test name
Test status
Simulation time 188419136 ps
CPU time 0.85 seconds
Started Jul 10 06:46:15 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206380 kb
Host smart-bd78f6cb-7db9-41e4-a838-f0457d2851a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27989
02940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2798902940
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1130770944
Short name T352
Test name
Test status
Simulation time 254304297 ps
CPU time 0.84 seconds
Started Jul 10 06:46:16 PM PDT 24
Finished Jul 10 06:46:23 PM PDT 24
Peak memory 206400 kb
Host smart-14bb3d1e-6ed9-49f2-ac1c-d7a9a0f596e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
70944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1130770944
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.1420729957
Short name T2502
Test name
Test status
Simulation time 194563248 ps
CPU time 0.87 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206388 kb
Host smart-d5eda33d-a082-4a63-b416-973ee5fbbaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14207
29957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.1420729957
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3741813185
Short name T1644
Test name
Test status
Simulation time 179911937 ps
CPU time 0.89 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206396 kb
Host smart-8c3f78b7-f16f-4c3a-9bf8-1f847a82b09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37418
13185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3741813185
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1803029686
Short name T1326
Test name
Test status
Simulation time 175113064 ps
CPU time 0.81 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:18 PM PDT 24
Peak memory 206380 kb
Host smart-9e06ecd3-ff22-44f6-aacb-893f946fe6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18030
29686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1803029686
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1845673465
Short name T1950
Test name
Test status
Simulation time 161341107 ps
CPU time 0.78 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206372 kb
Host smart-dfa45a18-2ba8-4f9c-b3b2-1b9327413b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18456
73465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1845673465
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.838652505
Short name T2112
Test name
Test status
Simulation time 171239575 ps
CPU time 0.81 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206376 kb
Host smart-1dfd6bb0-8a6d-433e-a7fc-62d02d1f6a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83865
2505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.838652505
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2409279569
Short name T872
Test name
Test status
Simulation time 231871375 ps
CPU time 0.97 seconds
Started Jul 10 06:46:16 PM PDT 24
Finished Jul 10 06:46:23 PM PDT 24
Peak memory 206396 kb
Host smart-fc1c1480-9e74-451f-8a4c-7497e28a2b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24092
79569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2409279569
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.3238994744
Short name T2706
Test name
Test status
Simulation time 5180586571 ps
CPU time 38.64 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206612 kb
Host smart-40ebb004-d296-4f2f-bcf1-aafab7bb6e85
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3238994744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.3238994744
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.536692411
Short name T1896
Test name
Test status
Simulation time 172582969 ps
CPU time 0.85 seconds
Started Jul 10 06:46:16 PM PDT 24
Finished Jul 10 06:46:23 PM PDT 24
Peak memory 206392 kb
Host smart-1ee17fa0-4727-41c1-8bf9-c14240d8256c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53669
2411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.536692411
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3356747394
Short name T1708
Test name
Test status
Simulation time 199232835 ps
CPU time 0.84 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:17 PM PDT 24
Peak memory 206356 kb
Host smart-06a4bba2-0b3b-48c3-b5a1-0908d02d393c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33567
47394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3356747394
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.122432966
Short name T1917
Test name
Test status
Simulation time 1104686339 ps
CPU time 2.47 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:19 PM PDT 24
Peak memory 206576 kb
Host smart-55c11ecd-f723-41c7-b17e-64df0af62388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12243
2966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.122432966
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2535843448
Short name T2151
Test name
Test status
Simulation time 3034690515 ps
CPU time 82.22 seconds
Started Jul 10 06:46:11 PM PDT 24
Finished Jul 10 06:47:37 PM PDT 24
Peak memory 206648 kb
Host smart-c271a4cb-67e5-4ba7-aebc-a7bc67995353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25358
43448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2535843448
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.57120478
Short name T715
Test name
Test status
Simulation time 40905516 ps
CPU time 0.64 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206404 kb
Host smart-e6d522c3-37bc-41b7-908d-e24ab5d5bc22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=57120478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.57120478
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.872031726
Short name T1989
Test name
Test status
Simulation time 3948755511 ps
CPU time 4.87 seconds
Started Jul 10 06:46:08 PM PDT 24
Finished Jul 10 06:46:17 PM PDT 24
Peak memory 206416 kb
Host smart-4768a950-7645-4090-a653-bbb4ec9d46bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=872031726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.872031726
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2126587351
Short name T1114
Test name
Test status
Simulation time 13364276855 ps
CPU time 14.67 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:30 PM PDT 24
Peak memory 206608 kb
Host smart-93b7777a-967e-4699-b7c7-062e53339ea6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2126587351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2126587351
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.469417910
Short name T2720
Test name
Test status
Simulation time 23503680013 ps
CPU time 22.59 seconds
Started Jul 10 06:46:14 PM PDT 24
Finished Jul 10 06:46:43 PM PDT 24
Peak memory 206660 kb
Host smart-58b0a986-5bc8-4f95-aca9-0d355bac3dac
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=469417910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.469417910
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3580972617
Short name T644
Test name
Test status
Simulation time 152617365 ps
CPU time 0.79 seconds
Started Jul 10 06:46:11 PM PDT 24
Finished Jul 10 06:46:16 PM PDT 24
Peak memory 206368 kb
Host smart-93b6ee79-1fc6-441e-b7c6-7e59f4b606c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
72617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3580972617
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3371178443
Short name T1129
Test name
Test status
Simulation time 162016093 ps
CPU time 0.81 seconds
Started Jul 10 06:46:15 PM PDT 24
Finished Jul 10 06:46:21 PM PDT 24
Peak memory 206388 kb
Host smart-03f8199f-6115-4962-9313-4431d16ed0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33711
78443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3371178443
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.330867887
Short name T1010
Test name
Test status
Simulation time 299888373 ps
CPU time 1.08 seconds
Started Jul 10 06:46:13 PM PDT 24
Finished Jul 10 06:46:20 PM PDT 24
Peak memory 206396 kb
Host smart-641feda2-5f71-4445-b0b6-41d3647b7c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
7887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.330867887
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.885907335
Short name T680
Test name
Test status
Simulation time 598268569 ps
CPU time 1.56 seconds
Started Jul 10 06:46:14 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206376 kb
Host smart-a38e4b68-16cf-4852-8a13-245c4ba8de3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88590
7335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.885907335
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.1526327044
Short name T1208
Test name
Test status
Simulation time 13746933088 ps
CPU time 25.98 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:43 PM PDT 24
Peak memory 206596 kb
Host smart-567afd15-19d2-4d3d-9c30-62339dbcd6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15263
27044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.1526327044
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1643879798
Short name T753
Test name
Test status
Simulation time 465290657 ps
CPU time 1.33 seconds
Started Jul 10 06:46:20 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206288 kb
Host smart-c7043e91-c6b1-4ba7-b95d-617d6950bce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16438
79798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1643879798
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3238061979
Short name T1079
Test name
Test status
Simulation time 144143906 ps
CPU time 0.77 seconds
Started Jul 10 06:46:12 PM PDT 24
Finished Jul 10 06:46:18 PM PDT 24
Peak memory 206280 kb
Host smart-746598fe-541b-451f-a21a-6ea30c707602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
61979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3238061979
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.4269177752
Short name T2231
Test name
Test status
Simulation time 41772011 ps
CPU time 0.68 seconds
Started Jul 10 06:46:14 PM PDT 24
Finished Jul 10 06:46:21 PM PDT 24
Peak memory 206376 kb
Host smart-abe512d2-1ace-49da-822b-2bb35ddf25c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42691
77752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.4269177752
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1018094648
Short name T2162
Test name
Test status
Simulation time 777628429 ps
CPU time 1.96 seconds
Started Jul 10 06:46:14 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206640 kb
Host smart-a5d64c26-8a0d-40ab-806e-64a0e1c1fa7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
94648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1018094648
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1037686213
Short name T762
Test name
Test status
Simulation time 346103877 ps
CPU time 1.97 seconds
Started Jul 10 06:46:15 PM PDT 24
Finished Jul 10 06:46:22 PM PDT 24
Peak memory 206468 kb
Host smart-37f38612-27da-4ee8-a64e-3744a1c77d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10376
86213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1037686213
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.627563778
Short name T2371
Test name
Test status
Simulation time 160471287 ps
CPU time 0.83 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206368 kb
Host smart-3e04cefa-4c0b-487a-9ad2-70997b01f9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62756
3778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.627563778
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2371204087
Short name T2291
Test name
Test status
Simulation time 139653969 ps
CPU time 0.74 seconds
Started Jul 10 06:46:27 PM PDT 24
Finished Jul 10 06:46:31 PM PDT 24
Peak memory 206308 kb
Host smart-2bb58c3d-e1af-4c3d-a89c-d73e74e924cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23712
04087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2371204087
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.178635459
Short name T1458
Test name
Test status
Simulation time 267895034 ps
CPU time 0.93 seconds
Started Jul 10 06:46:19 PM PDT 24
Finished Jul 10 06:46:25 PM PDT 24
Peak memory 206388 kb
Host smart-31c77e7c-d859-435c-844e-b86094d49028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17863
5459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.178635459
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.142446458
Short name T1740
Test name
Test status
Simulation time 8024209199 ps
CPU time 32.83 seconds
Started Jul 10 06:46:26 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206708 kb
Host smart-e70ebcc1-9529-4268-b641-ecf466b9663c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14244
6458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.142446458
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3128378378
Short name T107
Test name
Test status
Simulation time 217778153 ps
CPU time 0.86 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206364 kb
Host smart-48701855-4496-4e4b-9dfb-4afc933e540c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31283
78378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3128378378
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.853611580
Short name T2163
Test name
Test status
Simulation time 23336958675 ps
CPU time 23.23 seconds
Started Jul 10 06:46:24 PM PDT 24
Finished Jul 10 06:46:52 PM PDT 24
Peak memory 206452 kb
Host smart-9737ec01-b91a-47a1-88e4-1c1ac029be4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85361
1580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.853611580
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.440391553
Short name T1568
Test name
Test status
Simulation time 3311900470 ps
CPU time 3.67 seconds
Started Jul 10 06:46:24 PM PDT 24
Finished Jul 10 06:46:32 PM PDT 24
Peak memory 206440 kb
Host smart-d643eebf-1b6e-49b6-b8b3-2e8444b5871e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44039
1553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.440391553
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3481654161
Short name T1525
Test name
Test status
Simulation time 5964283065 ps
CPU time 164.3 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:49:19 PM PDT 24
Peak memory 206756 kb
Host smart-e250f0a0-56c4-46bd-92cf-63cc1c69b011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34816
54161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3481654161
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3132675712
Short name T2185
Test name
Test status
Simulation time 4814879738 ps
CPU time 48.46 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:47:15 PM PDT 24
Peak memory 206680 kb
Host smart-0f442751-416d-4441-97cb-811d5c2c3eab
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3132675712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3132675712
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2257370819
Short name T1601
Test name
Test status
Simulation time 236558426 ps
CPU time 0.91 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206380 kb
Host smart-2165ff86-fd51-47b1-896c-8d117590dbbb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2257370819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2257370819
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2471814081
Short name T1457
Test name
Test status
Simulation time 192784102 ps
CPU time 0.84 seconds
Started Jul 10 06:46:19 PM PDT 24
Finished Jul 10 06:46:25 PM PDT 24
Peak memory 206372 kb
Host smart-e22c9570-afac-4616-8b71-93ce67726be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24718
14081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2471814081
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.545987941
Short name T953
Test name
Test status
Simulation time 3705527382 ps
CPU time 33 seconds
Started Jul 10 06:46:24 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206648 kb
Host smart-fc002669-8849-47f7-aae2-e5431376218f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54598
7941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.545987941
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.4007334686
Short name T2099
Test name
Test status
Simulation time 3359102314 ps
CPU time 24.34 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:51 PM PDT 24
Peak memory 206692 kb
Host smart-fe314baa-cc12-4073-886d-4febe37936b7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4007334686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.4007334686
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2561840327
Short name T1541
Test name
Test status
Simulation time 174420540 ps
CPU time 0.79 seconds
Started Jul 10 06:46:19 PM PDT 24
Finished Jul 10 06:46:25 PM PDT 24
Peak memory 206404 kb
Host smart-923b5e26-9856-488d-8ac7-dc83d9dc2ff1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2561840327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2561840327
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.712068614
Short name T1033
Test name
Test status
Simulation time 154396089 ps
CPU time 0.76 seconds
Started Jul 10 06:46:24 PM PDT 24
Finished Jul 10 06:46:30 PM PDT 24
Peak memory 206400 kb
Host smart-fa3f2888-e179-4b52-b820-c6dfb36dce10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71206
8614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.712068614
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.225982921
Short name T342
Test name
Test status
Simulation time 215514755 ps
CPU time 0.82 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:32 PM PDT 24
Peak memory 206368 kb
Host smart-7c4322ec-858d-438f-8700-311d5cd0552a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22598
2921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.225982921
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3104823978
Short name T2047
Test name
Test status
Simulation time 155295886 ps
CPU time 0.79 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206376 kb
Host smart-b56d4645-ddee-4366-99f3-3c9bf1e1b7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048
23978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3104823978
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3913477430
Short name T985
Test name
Test status
Simulation time 185201571 ps
CPU time 0.83 seconds
Started Jul 10 06:46:25 PM PDT 24
Finished Jul 10 06:46:30 PM PDT 24
Peak memory 206564 kb
Host smart-e57b61b0-dbc2-4baf-a776-5bf8670db865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39134
77430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3913477430
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.411376027
Short name T176
Test name
Test status
Simulation time 143488574 ps
CPU time 0.77 seconds
Started Jul 10 06:46:20 PM PDT 24
Finished Jul 10 06:46:26 PM PDT 24
Peak memory 206380 kb
Host smart-09336e0c-158d-4dc5-8f80-589ae81cb126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
6027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.411376027
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.1444704003
Short name T83
Test name
Test status
Simulation time 222405236 ps
CPU time 0.92 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206364 kb
Host smart-d61d7f69-9516-4a91-9746-459e1c12cc36
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1444704003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.1444704003
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2411627289
Short name T939
Test name
Test status
Simulation time 200991225 ps
CPU time 0.8 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206376 kb
Host smart-32e1b133-fb22-4b97-9e95-fc9cafa31b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24116
27289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2411627289
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1938099100
Short name T2607
Test name
Test status
Simulation time 36823427 ps
CPU time 0.63 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206356 kb
Host smart-6b802172-7e5b-47b2-82ed-9858059dccf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19380
99100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1938099100
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1451412638
Short name T248
Test name
Test status
Simulation time 21391132454 ps
CPU time 42.85 seconds
Started Jul 10 06:46:26 PM PDT 24
Finished Jul 10 06:47:12 PM PDT 24
Peak memory 206672 kb
Host smart-a982ebdb-e660-40bd-8dcc-5598535d8aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14514
12638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1451412638
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.221744515
Short name T1551
Test name
Test status
Simulation time 182414015 ps
CPU time 0.88 seconds
Started Jul 10 06:46:20 PM PDT 24
Finished Jul 10 06:46:26 PM PDT 24
Peak memory 206380 kb
Host smart-6fc8c1a0-ad48-454b-b6c2-9c77aef6cbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22174
4515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.221744515
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3173695152
Short name T341
Test name
Test status
Simulation time 180221040 ps
CPU time 0.83 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:35 PM PDT 24
Peak memory 206352 kb
Host smart-0a5b7466-ccb4-41c4-a9b1-94594463a9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31736
95152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3173695152
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2236138966
Short name T741
Test name
Test status
Simulation time 188748491 ps
CPU time 0.83 seconds
Started Jul 10 06:46:19 PM PDT 24
Finished Jul 10 06:46:25 PM PDT 24
Peak memory 206380 kb
Host smart-34ee2aed-8806-4c5d-95cd-3eef26dfc70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22361
38966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2236138966
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.4190736881
Short name T2133
Test name
Test status
Simulation time 187306266 ps
CPU time 0.88 seconds
Started Jul 10 06:46:19 PM PDT 24
Finished Jul 10 06:46:25 PM PDT 24
Peak memory 206400 kb
Host smart-fa41fc42-c527-4aa2-aee2-b3089c17ebfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41907
36881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.4190736881
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3260589773
Short name T588
Test name
Test status
Simulation time 183486435 ps
CPU time 0.85 seconds
Started Jul 10 06:46:20 PM PDT 24
Finished Jul 10 06:46:26 PM PDT 24
Peak memory 206360 kb
Host smart-dee60231-4271-4ea4-acf6-d901803b495b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32605
89773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3260589773
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3669046557
Short name T2178
Test name
Test status
Simulation time 148789058 ps
CPU time 0.77 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206276 kb
Host smart-8c307a07-0ca4-46ed-a4f0-ad18fe0e82ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36690
46557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3669046557
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1990509792
Short name T766
Test name
Test status
Simulation time 152166439 ps
CPU time 0.78 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:27 PM PDT 24
Peak memory 206364 kb
Host smart-d5b3def0-15f7-4346-853c-7eff34ea9fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19905
09792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1990509792
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2327305890
Short name T434
Test name
Test status
Simulation time 223764776 ps
CPU time 0.94 seconds
Started Jul 10 06:46:22 PM PDT 24
Finished Jul 10 06:46:28 PM PDT 24
Peak memory 206388 kb
Host smart-c88b670a-d7ca-4351-8dc7-558e2c23c50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23273
05890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2327305890
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.449290560
Short name T2572
Test name
Test status
Simulation time 4442882750 ps
CPU time 127.01 seconds
Started Jul 10 06:46:22 PM PDT 24
Finished Jul 10 06:48:34 PM PDT 24
Peak memory 206672 kb
Host smart-f235171d-1d87-40b4-9af4-44b1ab04e939
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=449290560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.449290560
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1899077816
Short name T1470
Test name
Test status
Simulation time 170062785 ps
CPU time 0.79 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:26 PM PDT 24
Peak memory 206284 kb
Host smart-0a0b32bd-2efa-4329-acd5-52f39bc40d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18990
77816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1899077816
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1512949453
Short name T748
Test name
Test status
Simulation time 168087270 ps
CPU time 0.78 seconds
Started Jul 10 06:46:26 PM PDT 24
Finished Jul 10 06:46:30 PM PDT 24
Peak memory 206376 kb
Host smart-f537264c-f970-43c5-9ac7-7b9ea8d16a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129
49453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1512949453
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.2716144417
Short name T2067
Test name
Test status
Simulation time 1058190636 ps
CPU time 2.2 seconds
Started Jul 10 06:46:26 PM PDT 24
Finished Jul 10 06:46:32 PM PDT 24
Peak memory 206616 kb
Host smart-068b7053-4a68-46a2-a1af-e8a7cccc5809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27161
44417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.2716144417
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1569889761
Short name T2445
Test name
Test status
Simulation time 3252624931 ps
CPU time 28.46 seconds
Started Jul 10 06:46:22 PM PDT 24
Finished Jul 10 06:46:56 PM PDT 24
Peak memory 206636 kb
Host smart-2488c28c-545b-498a-a9cd-a83d55b81f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15698
89761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1569889761
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3483119364
Short name T1760
Test name
Test status
Simulation time 41694311 ps
CPU time 0.66 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206416 kb
Host smart-147df6df-35e2-4c89-ae11-d110b9143379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3483119364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3483119364
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3016730254
Short name T2422
Test name
Test status
Simulation time 3593989490 ps
CPU time 5 seconds
Started Jul 10 06:46:20 PM PDT 24
Finished Jul 10 06:46:30 PM PDT 24
Peak memory 206444 kb
Host smart-de86d798-cc67-47a1-bfff-f1f792b5f967
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3016730254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3016730254
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3789040346
Short name T2250
Test name
Test status
Simulation time 13427853299 ps
CPU time 13.22 seconds
Started Jul 10 06:46:19 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206636 kb
Host smart-d2316bb3-360b-43a9-a366-eb78a6f337ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3789040346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3789040346
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2380592010
Short name T2092
Test name
Test status
Simulation time 23368809883 ps
CPU time 23.19 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:55 PM PDT 24
Peak memory 206624 kb
Host smart-fb237557-b31e-4cbd-8cd2-3fcc64b5f514
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2380592010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2380592010
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1175349073
Short name T1724
Test name
Test status
Simulation time 245500785 ps
CPU time 0.87 seconds
Started Jul 10 06:46:24 PM PDT 24
Finished Jul 10 06:46:30 PM PDT 24
Peak memory 206380 kb
Host smart-738e0070-b6f9-4131-8796-26f9a653a71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11753
49073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1175349073
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.455874413
Short name T1040
Test name
Test status
Simulation time 139599543 ps
CPU time 0.79 seconds
Started Jul 10 06:46:22 PM PDT 24
Finished Jul 10 06:46:28 PM PDT 24
Peak memory 206384 kb
Host smart-bdeb22c3-c43c-4151-9897-cb853c32bdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45587
4413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.455874413
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.842399072
Short name T707
Test name
Test status
Simulation time 220832112 ps
CPU time 0.95 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:34 PM PDT 24
Peak memory 206376 kb
Host smart-b2e421fd-c45e-47d5-8fa0-c37e8379a917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84239
9072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.842399072
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1500676462
Short name T2122
Test name
Test status
Simulation time 883299792 ps
CPU time 1.97 seconds
Started Jul 10 06:46:24 PM PDT 24
Finished Jul 10 06:46:30 PM PDT 24
Peak memory 206568 kb
Host smart-588404d7-3684-4eaa-acac-d4ee42e3d98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15006
76462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1500676462
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1387072478
Short name T1823
Test name
Test status
Simulation time 7639202125 ps
CPU time 15.19 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:42 PM PDT 24
Peak memory 206620 kb
Host smart-6b7b898d-c58f-44e0-a7e4-0b89480a4add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13870
72478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1387072478
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.218728355
Short name T754
Test name
Test status
Simulation time 316073253 ps
CPU time 1.07 seconds
Started Jul 10 06:46:22 PM PDT 24
Finished Jul 10 06:46:28 PM PDT 24
Peak memory 206384 kb
Host smart-c893857b-b204-44fd-a72e-bfbbc45270ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21872
8355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.218728355
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.391771495
Short name T863
Test name
Test status
Simulation time 149374111 ps
CPU time 0.74 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:32 PM PDT 24
Peak memory 206380 kb
Host smart-e30cdf50-8023-4f7e-8393-7b40fc9eca7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39177
1495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.391771495
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1655308980
Short name T1775
Test name
Test status
Simulation time 56140932 ps
CPU time 0.7 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:33 PM PDT 24
Peak memory 206376 kb
Host smart-1612fd22-90aa-4402-a5ee-415b3723d8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16553
08980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1655308980
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1833928263
Short name T1405
Test name
Test status
Simulation time 739399984 ps
CPU time 1.92 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:35 PM PDT 24
Peak memory 206592 kb
Host smart-66868ff9-77d2-4dab-a86a-35607723c8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18339
28263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1833928263
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4222479916
Short name T215
Test name
Test status
Simulation time 171808789 ps
CPU time 1.38 seconds
Started Jul 10 06:46:21 PM PDT 24
Finished Jul 10 06:46:28 PM PDT 24
Peak memory 206564 kb
Host smart-a629514e-0378-4395-b41f-c6afaaa0f32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42224
79916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4222479916
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1629023816
Short name T2545
Test name
Test status
Simulation time 188769367 ps
CPU time 0.87 seconds
Started Jul 10 06:46:22 PM PDT 24
Finished Jul 10 06:46:28 PM PDT 24
Peak memory 206376 kb
Host smart-3c7b55ba-f594-4928-9abe-beae4d773920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
23816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1629023816
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3326472442
Short name T2484
Test name
Test status
Simulation time 230680527 ps
CPU time 0.84 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:32 PM PDT 24
Peak memory 206372 kb
Host smart-e98f46ab-bead-45cb-9d1c-e5cd84b7fb88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33264
72442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3326472442
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3783070404
Short name T793
Test name
Test status
Simulation time 188259569 ps
CPU time 0.87 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:35 PM PDT 24
Peak memory 206376 kb
Host smart-e56b6a6a-c1f5-4bc6-8873-230db22e869d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37830
70404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3783070404
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1730984864
Short name T1178
Test name
Test status
Simulation time 5526844590 ps
CPU time 37.49 seconds
Started Jul 10 06:46:19 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206688 kb
Host smart-c6cf84bf-8779-493f-bb63-d54e19ab7b69
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1730984864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1730984864
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3965697429
Short name T2301
Test name
Test status
Simulation time 5862298461 ps
CPU time 18.32 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:54 PM PDT 24
Peak memory 206660 kb
Host smart-9a5defcb-dfd9-4416-bda0-842331ec6735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39656
97429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3965697429
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.3035670188
Short name T911
Test name
Test status
Simulation time 243022366 ps
CPU time 0.91 seconds
Started Jul 10 06:46:27 PM PDT 24
Finished Jul 10 06:46:31 PM PDT 24
Peak memory 206392 kb
Host smart-4d696f22-67bd-454a-8f6a-fbdabf950cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30356
70188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.3035670188
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2743915806
Short name T508
Test name
Test status
Simulation time 23328227103 ps
CPU time 24.1 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:57 PM PDT 24
Peak memory 206364 kb
Host smart-e8c51302-cd97-4211-af29-ab20101a10f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27439
15806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2743915806
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2033783493
Short name T1911
Test name
Test status
Simulation time 3364561396 ps
CPU time 3.92 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:40 PM PDT 24
Peak memory 206452 kb
Host smart-f0b0ac46-00ff-4287-89f2-cd86f08089a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20337
83493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2033783493
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2187960832
Short name T830
Test name
Test status
Simulation time 9532867657 ps
CPU time 252.85 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:50:48 PM PDT 24
Peak memory 206700 kb
Host smart-aaed612a-f289-4524-ac28-c058c4dce829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21879
60832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2187960832
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.2048545478
Short name T2746
Test name
Test status
Simulation time 3897190682 ps
CPU time 35.84 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:47:07 PM PDT 24
Peak memory 206640 kb
Host smart-483223a8-9c07-422c-940c-e4cbb248ba7b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2048545478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2048545478
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3278258759
Short name T1642
Test name
Test status
Simulation time 253170633 ps
CPU time 0.96 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:33 PM PDT 24
Peak memory 206368 kb
Host smart-b05ff733-d300-4cd6-9fff-0beb4fe5f259
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3278258759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3278258759
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.608878889
Short name T718
Test name
Test status
Simulation time 191276875 ps
CPU time 0.83 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:39 PM PDT 24
Peak memory 206380 kb
Host smart-26ec101e-897f-43d6-84fa-4ce178c3baec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60887
8889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.608878889
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3853568638
Short name T1817
Test name
Test status
Simulation time 3888433229 ps
CPU time 35.08 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:47:15 PM PDT 24
Peak memory 206644 kb
Host smart-a14fe392-226a-44a9-af2d-71a21d5f5851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38535
68638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3853568638
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.795144601
Short name T2375
Test name
Test status
Simulation time 6059143040 ps
CPU time 42.28 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:47:20 PM PDT 24
Peak memory 206712 kb
Host smart-0fbfa426-60f7-4e20-9ed5-5c449e930ec8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=795144601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.795144601
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2998981239
Short name T447
Test name
Test status
Simulation time 164947952 ps
CPU time 0.83 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:39 PM PDT 24
Peak memory 206380 kb
Host smart-e435cd93-8f85-4c89-963e-8181ac91ab50
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2998981239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2998981239
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.108732429
Short name T1346
Test name
Test status
Simulation time 145649650 ps
CPU time 0.76 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:33 PM PDT 24
Peak memory 206384 kb
Host smart-27c6d7d0-a5c5-4ecd-911d-7f8d831dba08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10873
2429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.108732429
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3022959579
Short name T128
Test name
Test status
Simulation time 180356449 ps
CPU time 0.87 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:39 PM PDT 24
Peak memory 206376 kb
Host smart-f6671099-c0f0-4b28-bad9-9daf9cdafb8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30229
59579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3022959579
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3679764759
Short name T2737
Test name
Test status
Simulation time 155618228 ps
CPU time 0.79 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206392 kb
Host smart-b8500442-11fc-45c6-aa18-a5f7e6c03261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36797
64759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3679764759
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1461989800
Short name T630
Test name
Test status
Simulation time 204296500 ps
CPU time 0.84 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206372 kb
Host smart-5f983426-35b7-489d-ace7-3b533dc451c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14619
89800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1461989800
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2689628188
Short name T21
Test name
Test status
Simulation time 175284222 ps
CPU time 0.76 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206376 kb
Host smart-c77c5e24-371c-4e64-9345-4db77d52d78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26896
28188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2689628188
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.4012650006
Short name T271
Test name
Test status
Simulation time 152939336 ps
CPU time 0.78 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:32 PM PDT 24
Peak memory 206376 kb
Host smart-d7458efe-58c3-4cb3-b4d9-b847de83eebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40126
50006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.4012650006
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.291996193
Short name T155
Test name
Test status
Simulation time 213581846 ps
CPU time 0.95 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:35 PM PDT 24
Peak memory 206380 kb
Host smart-314becda-0848-48c2-9abc-d519380abf5a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=291996193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.291996193
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3735320638
Short name T645
Test name
Test status
Simulation time 141543697 ps
CPU time 0.81 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:39 PM PDT 24
Peak memory 206364 kb
Host smart-4b79ccdc-540d-422d-ab59-fb49af529d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37353
20638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3735320638
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2451297685
Short name T1499
Test name
Test status
Simulation time 33779821 ps
CPU time 0.64 seconds
Started Jul 10 06:46:27 PM PDT 24
Finished Jul 10 06:46:31 PM PDT 24
Peak memory 206388 kb
Host smart-c371c031-8b49-4bc1-b592-7ea98748869d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24512
97685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2451297685
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.41534696
Short name T2135
Test name
Test status
Simulation time 7574766009 ps
CPU time 17.49 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:55 PM PDT 24
Peak memory 206732 kb
Host smart-49da6bab-c5bc-4bcf-baa8-0a3d5c5b3d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41534
696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.41534696
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2545116529
Short name T723
Test name
Test status
Simulation time 151139948 ps
CPU time 0.82 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206560 kb
Host smart-4988f62a-844b-45b5-95ae-4a305679a7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25451
16529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2545116529
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2331110863
Short name T1766
Test name
Test status
Simulation time 174840581 ps
CPU time 0.84 seconds
Started Jul 10 06:46:27 PM PDT 24
Finished Jul 10 06:46:31 PM PDT 24
Peak memory 206360 kb
Host smart-4cc216a4-8ac2-4d8b-ab32-a640e88bff9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23311
10863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2331110863
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2560294306
Short name T310
Test name
Test status
Simulation time 153499285 ps
CPU time 0.77 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206372 kb
Host smart-e320f882-e849-4b48-aae7-6b01a6b9f040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25602
94306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2560294306
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3788472424
Short name T1682
Test name
Test status
Simulation time 181788682 ps
CPU time 0.82 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206400 kb
Host smart-02a83a0b-5fa3-4e86-a9d5-836ce6c1d103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37884
72424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3788472424
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.143515252
Short name T1782
Test name
Test status
Simulation time 157459410 ps
CPU time 0.79 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206376 kb
Host smart-79e1412e-e91a-4a34-8216-0bf3df58a92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14351
5252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.143515252
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2788140764
Short name T2465
Test name
Test status
Simulation time 149220960 ps
CPU time 0.75 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206356 kb
Host smart-df4243af-c420-40a6-81d6-5f8f101ebd52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
40764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2788140764
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1831033262
Short name T1538
Test name
Test status
Simulation time 148904466 ps
CPU time 0.78 seconds
Started Jul 10 06:46:28 PM PDT 24
Finished Jul 10 06:46:33 PM PDT 24
Peak memory 206388 kb
Host smart-bfb18400-1a2b-4aeb-8605-15fb49f2809c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18310
33262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1831033262
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3008899650
Short name T1576
Test name
Test status
Simulation time 217371181 ps
CPU time 0.88 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:34 PM PDT 24
Peak memory 206372 kb
Host smart-d082a9e4-a98f-4cb8-aa78-c2b02e851081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30088
99650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3008899650
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2829912850
Short name T2571
Test name
Test status
Simulation time 3848678935 ps
CPU time 106.71 seconds
Started Jul 10 06:46:27 PM PDT 24
Finished Jul 10 06:48:17 PM PDT 24
Peak memory 206592 kb
Host smart-85649415-efda-4fa5-8f87-33b99680e1a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2829912850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2829912850
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3619799754
Short name T2144
Test name
Test status
Simulation time 200631092 ps
CPU time 0.8 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 205488 kb
Host smart-f319893c-f8cf-4660-b7f1-eb201c432840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197
99754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3619799754
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2561679300
Short name T1738
Test name
Test status
Simulation time 148660509 ps
CPU time 0.77 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206356 kb
Host smart-18f3d9b8-c987-4b4d-aecd-1b1acfcde996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25616
79300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2561679300
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.1802477417
Short name T2448
Test name
Test status
Simulation time 190698863 ps
CPU time 0.81 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206360 kb
Host smart-4884c5ab-278d-457e-99d9-3fa88dab49c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18024
77417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1802477417
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.3969568437
Short name T1991
Test name
Test status
Simulation time 3372072493 ps
CPU time 23.7 seconds
Started Jul 10 06:46:35 PM PDT 24
Finished Jul 10 06:47:04 PM PDT 24
Peak memory 206664 kb
Host smart-9c50105c-1f7b-4023-adf4-583708a7f796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39695
68437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.3969568437
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3414254168
Short name T1941
Test name
Test status
Simulation time 44564380 ps
CPU time 0.68 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:46:57 PM PDT 24
Peak memory 206444 kb
Host smart-96c6f876-b76c-41c9-bbd4-f516320cbba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3414254168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3414254168
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2419944543
Short name T1774
Test name
Test status
Simulation time 4187268033 ps
CPU time 4.92 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:43 PM PDT 24
Peak memory 205652 kb
Host smart-9f8317de-e81b-408c-8e0f-1df9af692897
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2419944543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.2419944543
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2591601029
Short name T501
Test name
Test status
Simulation time 13401656744 ps
CPU time 12.92 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:51 PM PDT 24
Peak memory 206472 kb
Host smart-4b6c2010-71dd-4c20-a434-bf75470992f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2591601029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2591601029
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.674419898
Short name T2351
Test name
Test status
Simulation time 23366910855 ps
CPU time 24.23 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:47:01 PM PDT 24
Peak memory 206432 kb
Host smart-cd304abd-55d6-4710-9cb0-ab5de94dbac4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=674419898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.674419898
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3111549198
Short name T418
Test name
Test status
Simulation time 149500655 ps
CPU time 0.79 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206388 kb
Host smart-c51f7cff-1b07-4f63-a37a-24792b69c603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31115
49198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3111549198
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.4496695
Short name T2725
Test name
Test status
Simulation time 211771913 ps
CPU time 0.83 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:46:36 PM PDT 24
Peak memory 206400 kb
Host smart-105ebe9d-bc0d-411c-82f8-a8086300811f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44966
95 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.4496695
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.703843062
Short name T2480
Test name
Test status
Simulation time 212510773 ps
CPU time 0.86 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:35 PM PDT 24
Peak memory 206568 kb
Host smart-5b1dbe60-e6bb-4900-bf69-b6750982935a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70384
3062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.703843062
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1232942250
Short name T110
Test name
Test status
Simulation time 335152813 ps
CPU time 1.04 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:40 PM PDT 24
Peak memory 206392 kb
Host smart-d34666ab-1305-45f6-b275-0a370e78fbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12329
42250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1232942250
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.374025832
Short name T97
Test name
Test status
Simulation time 11616551496 ps
CPU time 21.07 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:55 PM PDT 24
Peak memory 206676 kb
Host smart-5a052566-2181-4a67-84ae-5088cbae5f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37402
5832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.374025832
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3518613530
Short name T708
Test name
Test status
Simulation time 441527824 ps
CPU time 1.32 seconds
Started Jul 10 06:46:39 PM PDT 24
Finished Jul 10 06:46:44 PM PDT 24
Peak memory 206408 kb
Host smart-61179198-b196-466d-a72c-bb58d5ec91dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35186
13530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3518613530
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1037400752
Short name T1722
Test name
Test status
Simulation time 140318166 ps
CPU time 0.78 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:39 PM PDT 24
Peak memory 206376 kb
Host smart-041236ca-b343-438a-887d-e40fc99b1773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10374
00752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1037400752
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.227521918
Short name T1596
Test name
Test status
Simulation time 51725675 ps
CPU time 0.7 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206360 kb
Host smart-fbcbc1d5-7676-49bf-a38d-f2dedf9c4895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22752
1918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.227521918
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1580451232
Short name T1383
Test name
Test status
Simulation time 742119665 ps
CPU time 2.01 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:46:37 PM PDT 24
Peak memory 206636 kb
Host smart-73f84766-3063-44b3-a81f-a421ba4a5756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15804
51232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1580451232
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1498865348
Short name T539
Test name
Test status
Simulation time 230152433 ps
CPU time 1.84 seconds
Started Jul 10 06:46:38 PM PDT 24
Finished Jul 10 06:46:44 PM PDT 24
Peak memory 206640 kb
Host smart-04e7b87c-ac9b-4674-bbec-eaf2b95de698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14988
65348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1498865348
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.891634903
Short name T585
Test name
Test status
Simulation time 212038745 ps
CPU time 0.9 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:46:40 PM PDT 24
Peak memory 205600 kb
Host smart-0d94e1e7-6272-4ef1-9646-bf2e21f61303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89163
4903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.891634903
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1877338388
Short name T2289
Test name
Test status
Simulation time 178236867 ps
CPU time 0.79 seconds
Started Jul 10 06:46:33 PM PDT 24
Finished Jul 10 06:46:40 PM PDT 24
Peak memory 206400 kb
Host smart-7d28511b-81e9-403b-b594-081d123e96aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18773
38388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1877338388
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3561343638
Short name T346
Test name
Test status
Simulation time 209435823 ps
CPU time 0.9 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:39 PM PDT 24
Peak memory 206368 kb
Host smart-98430023-0e88-482f-96de-79e7a03f43b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35613
43638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3561343638
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.1697664537
Short name T878
Test name
Test status
Simulation time 7494959470 ps
CPU time 54.25 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:47:29 PM PDT 24
Peak memory 206688 kb
Host smart-6a9553e0-a826-4062-b315-81b34df729d2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1697664537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.1697664537
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.412897798
Short name T2569
Test name
Test status
Simulation time 187969641 ps
CPU time 0.85 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:46:41 PM PDT 24
Peak memory 206376 kb
Host smart-acc4e82e-a75d-421c-92e9-468300b95974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41289
7798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.412897798
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.4109672188
Short name T2127
Test name
Test status
Simulation time 23347476951 ps
CPU time 21.61 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:55 PM PDT 24
Peak memory 206448 kb
Host smart-5fc506b2-7151-493b-8c2e-df061c788f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
72188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.4109672188
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.1542868396
Short name T327
Test name
Test status
Simulation time 3366842763 ps
CPU time 3.74 seconds
Started Jul 10 06:46:50 PM PDT 24
Finished Jul 10 06:46:55 PM PDT 24
Peak memory 206444 kb
Host smart-c0a6d3a1-c1ef-4501-98f5-216573289b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428
68396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.1542868396
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2399646067
Short name T1803
Test name
Test status
Simulation time 11359580609 ps
CPU time 79.73 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:47:56 PM PDT 24
Peak memory 206700 kb
Host smart-c4e3debd-3dd8-414a-858a-9058d41e97ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23996
46067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2399646067
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1079866147
Short name T915
Test name
Test status
Simulation time 4256355678 ps
CPU time 40.84 seconds
Started Jul 10 06:46:35 PM PDT 24
Finished Jul 10 06:47:21 PM PDT 24
Peak memory 206696 kb
Host smart-fcd98599-6a91-4f8c-b590-ccd6c4d0ac28
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1079866147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1079866147
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.518522967
Short name T1243
Test name
Test status
Simulation time 258516096 ps
CPU time 0.88 seconds
Started Jul 10 06:46:37 PM PDT 24
Finished Jul 10 06:46:42 PM PDT 24
Peak memory 206376 kb
Host smart-1811e04d-35dd-4ee9-9cbb-eab46e3a4fc4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=518522967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.518522967
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3038702117
Short name T581
Test name
Test status
Simulation time 191053428 ps
CPU time 0.85 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206368 kb
Host smart-74356fb0-f21e-4919-8a30-ca265305903d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30387
02117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3038702117
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.1455670042
Short name T1185
Test name
Test status
Simulation time 5338766465 ps
CPU time 52.41 seconds
Started Jul 10 06:46:30 PM PDT 24
Finished Jul 10 06:47:28 PM PDT 24
Peak memory 206712 kb
Host smart-fff876b3-2201-463e-95b4-3f1f14f90e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14556
70042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.1455670042
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.93799235
Short name T1913
Test name
Test status
Simulation time 4683138484 ps
CPU time 125.87 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:48:46 PM PDT 24
Peak memory 206664 kb
Host smart-6a049c9c-720d-405b-b2e3-a283ae16b7e4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=93799235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.93799235
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3964955936
Short name T1855
Test name
Test status
Simulation time 150819889 ps
CPU time 0.84 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206328 kb
Host smart-478143fd-bac9-405e-92aa-a04dccbae62e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3964955936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3964955936
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3344926224
Short name T1729
Test name
Test status
Simulation time 178075526 ps
CPU time 0.79 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:39 PM PDT 24
Peak memory 206404 kb
Host smart-e3ca3532-f9b6-4289-ad95-d247ad653746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33449
26224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3344926224
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3198237874
Short name T127
Test name
Test status
Simulation time 216740763 ps
CPU time 0.9 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206348 kb
Host smart-a51a54e5-6a6e-410c-99cb-39f336bb61c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31982
37874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3198237874
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3574314117
Short name T2560
Test name
Test status
Simulation time 189353639 ps
CPU time 0.89 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206376 kb
Host smart-09b64498-bbdf-41e9-b62a-9c3fe39e4b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35743
14117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3574314117
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.276107894
Short name T269
Test name
Test status
Simulation time 171217867 ps
CPU time 0.81 seconds
Started Jul 10 06:46:51 PM PDT 24
Finished Jul 10 06:46:53 PM PDT 24
Peak memory 206376 kb
Host smart-8f0f7564-4477-48a3-8905-798148392fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27610
7894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.276107894
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3915277254
Short name T1015
Test name
Test status
Simulation time 217286991 ps
CPU time 0.87 seconds
Started Jul 10 06:46:42 PM PDT 24
Finished Jul 10 06:46:45 PM PDT 24
Peak memory 206380 kb
Host smart-37713d82-111e-44b8-b63b-71b89fa334fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39152
77254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3915277254
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1542262428
Short name T177
Test name
Test status
Simulation time 179450631 ps
CPU time 0.91 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:46:41 PM PDT 24
Peak memory 206384 kb
Host smart-fdb44767-9484-4c99-b63c-eaf97d1c85a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15422
62428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1542262428
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.1108345591
Short name T335
Test name
Test status
Simulation time 255442769 ps
CPU time 0.97 seconds
Started Jul 10 06:46:33 PM PDT 24
Finished Jul 10 06:46:40 PM PDT 24
Peak memory 206392 kb
Host smart-2378363b-4618-4193-92c3-896bac377e6a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1108345591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.1108345591
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2623250088
Short name T2753
Test name
Test status
Simulation time 152506346 ps
CPU time 0.75 seconds
Started Jul 10 06:46:37 PM PDT 24
Finished Jul 10 06:46:42 PM PDT 24
Peak memory 206380 kb
Host smart-086fdcba-072f-4e72-b511-5f7d4036288c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26232
50088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2623250088
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1983373702
Short name T22
Test name
Test status
Simulation time 56174945 ps
CPU time 0.71 seconds
Started Jul 10 06:46:37 PM PDT 24
Finished Jul 10 06:46:42 PM PDT 24
Peak memory 206372 kb
Host smart-ebef1f73-70ee-47a5-a9c7-f108d518220c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
73702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1983373702
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3800951688
Short name T2500
Test name
Test status
Simulation time 19617810459 ps
CPU time 45.11 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:47:24 PM PDT 24
Peak memory 206732 kb
Host smart-2b8b2549-179d-47d2-9792-9fcba092a340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
51688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3800951688
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1690460125
Short name T2647
Test name
Test status
Simulation time 155530444 ps
CPU time 0.81 seconds
Started Jul 10 06:46:33 PM PDT 24
Finished Jul 10 06:46:40 PM PDT 24
Peak memory 206384 kb
Host smart-76a7cf2c-5920-4db9-8ebf-329b412a8865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16904
60125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1690460125
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.98636698
Short name T1929
Test name
Test status
Simulation time 214179174 ps
CPU time 0.89 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:46:41 PM PDT 24
Peak memory 206392 kb
Host smart-8fbff2fc-11f3-441d-9cf3-5611fefd9f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98636
698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.98636698
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3670947693
Short name T781
Test name
Test status
Simulation time 264798329 ps
CPU time 0.88 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:46:40 PM PDT 24
Peak memory 206332 kb
Host smart-8fe86d39-b544-4dea-9090-3163ed37b0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36709
47693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3670947693
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2082880604
Short name T1138
Test name
Test status
Simulation time 170601311 ps
CPU time 0.84 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:46:41 PM PDT 24
Peak memory 206384 kb
Host smart-13d5abda-19ca-4a1c-b9f8-f8983d122d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20828
80604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2082880604
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1256275402
Short name T2007
Test name
Test status
Simulation time 183525021 ps
CPU time 0.81 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:35 PM PDT 24
Peak memory 206352 kb
Host smart-20f4fcfc-3cf3-4985-b081-c1762a7acd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
75402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1256275402
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1200554178
Short name T477
Test name
Test status
Simulation time 189654443 ps
CPU time 0.83 seconds
Started Jul 10 06:46:35 PM PDT 24
Finished Jul 10 06:46:41 PM PDT 24
Peak memory 206392 kb
Host smart-faa9ba57-7050-4646-b076-1528728d07fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005
54178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1200554178
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2036450794
Short name T611
Test name
Test status
Simulation time 164729396 ps
CPU time 0.83 seconds
Started Jul 10 06:46:32 PM PDT 24
Finished Jul 10 06:46:42 PM PDT 24
Peak memory 206388 kb
Host smart-604c82b3-a19b-4d33-a444-5eb72f452127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20364
50794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2036450794
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2563455031
Short name T400
Test name
Test status
Simulation time 288371680 ps
CPU time 1 seconds
Started Jul 10 06:46:29 PM PDT 24
Finished Jul 10 06:46:35 PM PDT 24
Peak memory 206376 kb
Host smart-9177e083-aef9-460b-9f55-74c36c2ba8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25634
55031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2563455031
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3687160218
Short name T2456
Test name
Test status
Simulation time 6237209726 ps
CPU time 176.88 seconds
Started Jul 10 06:46:34 PM PDT 24
Finished Jul 10 06:49:36 PM PDT 24
Peak memory 205884 kb
Host smart-c247cc58-1847-4cc5-a454-d32e14f42b66
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3687160218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3687160218
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3529673443
Short name T1220
Test name
Test status
Simulation time 251186974 ps
CPU time 0.9 seconds
Started Jul 10 06:46:31 PM PDT 24
Finished Jul 10 06:46:38 PM PDT 24
Peak memory 206392 kb
Host smart-2c5cb28c-7586-4634-b5db-18f2de1fdf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35296
73443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3529673443
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.990187748
Short name T1159
Test name
Test status
Simulation time 164635998 ps
CPU time 0.82 seconds
Started Jul 10 06:46:57 PM PDT 24
Finished Jul 10 06:47:01 PM PDT 24
Peak memory 206376 kb
Host smart-ea638a4c-709f-446d-bfd3-fc31356ad43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99018
7748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.990187748
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.3050201310
Short name T2358
Test name
Test status
Simulation time 941993709 ps
CPU time 2.11 seconds
Started Jul 10 06:46:44 PM PDT 24
Finished Jul 10 06:46:48 PM PDT 24
Peak memory 206520 kb
Host smart-26cd0ee3-48d7-48a2-96f8-c6c700acee9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30502
01310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.3050201310
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3843441821
Short name T1677
Test name
Test status
Simulation time 6184236550 ps
CPU time 44.26 seconds
Started Jul 10 06:46:37 PM PDT 24
Finished Jul 10 06:47:26 PM PDT 24
Peak memory 206644 kb
Host smart-abc10627-794c-400e-913d-73fdd1a3202f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38434
41821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3843441821
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.3917543079
Short name T730
Test name
Test status
Simulation time 43826115 ps
CPU time 0.65 seconds
Started Jul 10 06:46:56 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 206424 kb
Host smart-d5c478e3-30b9-4bf4-b8ea-163ba2775ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3917543079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.3917543079
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3933300806
Short name T631
Test name
Test status
Simulation time 3804581178 ps
CPU time 4.42 seconds
Started Jul 10 06:46:36 PM PDT 24
Finished Jul 10 06:46:45 PM PDT 24
Peak memory 206616 kb
Host smart-42d741ae-fe10-4b26-96e6-74ec23368c02
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3933300806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3933300806
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1885197059
Short name T1820
Test name
Test status
Simulation time 13398896379 ps
CPU time 16.43 seconds
Started Jul 10 06:46:36 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206636 kb
Host smart-4928493a-e9fa-404d-8343-a1a07fc389fb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1885197059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1885197059
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2603895985
Short name T554
Test name
Test status
Simulation time 23362660474 ps
CPU time 26.42 seconds
Started Jul 10 06:46:48 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206448 kb
Host smart-b0b736f0-3994-4d0c-a1ba-25edf788ee0d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2603895985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2603895985
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.159372227
Short name T2391
Test name
Test status
Simulation time 173157778 ps
CPU time 0.84 seconds
Started Jul 10 06:46:48 PM PDT 24
Finished Jul 10 06:46:50 PM PDT 24
Peak memory 206376 kb
Host smart-31c3f0e4-b81b-4c53-9c46-39291b9601f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
2227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.159372227
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3127673322
Short name T422
Test name
Test status
Simulation time 196162813 ps
CPU time 0.86 seconds
Started Jul 10 06:46:40 PM PDT 24
Finished Jul 10 06:46:44 PM PDT 24
Peak memory 206380 kb
Host smart-d77f74e0-f520-462f-bae7-8c6e9ec9e05d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31276
73322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3127673322
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3927857608
Short name T705
Test name
Test status
Simulation time 496038068 ps
CPU time 1.63 seconds
Started Jul 10 06:46:47 PM PDT 24
Finished Jul 10 06:46:50 PM PDT 24
Peak memory 206596 kb
Host smart-9ee8eb18-455b-4489-84a3-2516ff6fe2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39278
57608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3927857608
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3183101548
Short name T1951
Test name
Test status
Simulation time 840705239 ps
CPU time 1.96 seconds
Started Jul 10 06:46:51 PM PDT 24
Finished Jul 10 06:46:54 PM PDT 24
Peak memory 206572 kb
Host smart-6f622766-76a0-40b5-ad12-1fdbbbe69ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
01548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3183101548
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.4174534732
Short name T1101
Test name
Test status
Simulation time 19475343081 ps
CPU time 34.53 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:47:37 PM PDT 24
Peak memory 206652 kb
Host smart-b1df6a9f-ea8e-4af7-aa51-ee5315b6c5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41745
34732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.4174534732
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2336037506
Short name T1331
Test name
Test status
Simulation time 421439449 ps
CPU time 1.36 seconds
Started Jul 10 06:46:46 PM PDT 24
Finished Jul 10 06:46:49 PM PDT 24
Peak memory 206400 kb
Host smart-a893a76a-c100-4485-b2c8-aac484a9aec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23360
37506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2336037506
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2490061210
Short name T1308
Test name
Test status
Simulation time 141708630 ps
CPU time 0.74 seconds
Started Jul 10 06:46:45 PM PDT 24
Finished Jul 10 06:46:47 PM PDT 24
Peak memory 206284 kb
Host smart-ea498553-3f4a-42b1-91ba-9369a51e4ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24900
61210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2490061210
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2370894713
Short name T2367
Test name
Test status
Simulation time 31369906 ps
CPU time 0.64 seconds
Started Jul 10 06:46:48 PM PDT 24
Finished Jul 10 06:46:50 PM PDT 24
Peak memory 206380 kb
Host smart-6e7ab736-d7e4-4544-9eb7-043314650a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
94713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2370894713
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3123063537
Short name T590
Test name
Test status
Simulation time 941740075 ps
CPU time 2.18 seconds
Started Jul 10 06:46:48 PM PDT 24
Finished Jul 10 06:46:52 PM PDT 24
Peak memory 206568 kb
Host smart-8b9ff7c2-6412-4e5b-b6fd-90ce177c4e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31230
63537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3123063537
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3373201288
Short name T512
Test name
Test status
Simulation time 166696701 ps
CPU time 1.67 seconds
Started Jul 10 06:47:00 PM PDT 24
Finished Jul 10 06:47:06 PM PDT 24
Peak memory 206584 kb
Host smart-d544cae8-d843-40a1-9572-f7c3361d8569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33732
01288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3373201288
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3755557323
Short name T1076
Test name
Test status
Simulation time 208974392 ps
CPU time 0.91 seconds
Started Jul 10 06:46:51 PM PDT 24
Finished Jul 10 06:46:54 PM PDT 24
Peak memory 206312 kb
Host smart-424a10a6-672a-4dce-b1eb-ae1c94ce871b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
57323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3755557323
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2966696187
Short name T2526
Test name
Test status
Simulation time 141853188 ps
CPU time 0.78 seconds
Started Jul 10 06:46:37 PM PDT 24
Finished Jul 10 06:46:42 PM PDT 24
Peak memory 206328 kb
Host smart-f09d12e1-e401-4247-8d7d-98ec552bf3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29666
96187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2966696187
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1395063081
Short name T1861
Test name
Test status
Simulation time 171839648 ps
CPU time 0.83 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206376 kb
Host smart-9a4f3411-ffcf-42d7-aa14-c89976c75d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13950
63081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1395063081
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.333674924
Short name T103
Test name
Test status
Simulation time 6584783052 ps
CPU time 188.7 seconds
Started Jul 10 06:46:44 PM PDT 24
Finished Jul 10 06:49:54 PM PDT 24
Peak memory 206652 kb
Host smart-d4fe8d7a-b29b-4f85-9520-a587ffe1803c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=333674924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.333674924
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.3201551634
Short name T1776
Test name
Test status
Simulation time 11573728454 ps
CPU time 39.84 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:47 PM PDT 24
Peak memory 206692 kb
Host smart-5985471a-9740-4b21-9165-e1c22e67db96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32015
51634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.3201551634
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2460839510
Short name T2533
Test name
Test status
Simulation time 228269777 ps
CPU time 0.96 seconds
Started Jul 10 06:46:38 PM PDT 24
Finished Jul 10 06:46:43 PM PDT 24
Peak memory 206372 kb
Host smart-8c138e23-c183-472f-9520-dde8ec339f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24608
39510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2460839510
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.212858485
Short name T786
Test name
Test status
Simulation time 23302947638 ps
CPU time 25.99 seconds
Started Jul 10 06:46:44 PM PDT 24
Finished Jul 10 06:47:11 PM PDT 24
Peak memory 206368 kb
Host smart-139fb63f-98f6-4a60-b4ed-8a4ba34a52ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21285
8485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.212858485
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2411086921
Short name T1370
Test name
Test status
Simulation time 3293392683 ps
CPU time 4.5 seconds
Started Jul 10 06:46:43 PM PDT 24
Finished Jul 10 06:46:50 PM PDT 24
Peak memory 206376 kb
Host smart-9d63cde7-b6ad-4808-8e83-a840187944d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24110
86921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2411086921
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.4134276168
Short name T1512
Test name
Test status
Simulation time 7106898972 ps
CPU time 66.15 seconds
Started Jul 10 06:46:42 PM PDT 24
Finished Jul 10 06:47:50 PM PDT 24
Peak memory 206636 kb
Host smart-b78200ea-708f-437c-8804-c713eb6bd3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
76168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.4134276168
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2014137750
Short name T765
Test name
Test status
Simulation time 5022845811 ps
CPU time 35.77 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:37 PM PDT 24
Peak memory 206692 kb
Host smart-6160ae33-69de-40fa-8f01-6b6f92da8ccc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2014137750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2014137750
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3234894497
Short name T484
Test name
Test status
Simulation time 254209265 ps
CPU time 0.94 seconds
Started Jul 10 06:47:01 PM PDT 24
Finished Jul 10 06:47:06 PM PDT 24
Peak memory 206392 kb
Host smart-beea0fce-03f0-456e-ab77-19efa5486d2f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3234894497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3234894497
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3400222463
Short name T488
Test name
Test status
Simulation time 226413740 ps
CPU time 0.9 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:03 PM PDT 24
Peak memory 206396 kb
Host smart-d25f1efb-427f-4a8a-9d7b-d24b04df9344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34002
22463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3400222463
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2118940054
Short name T1783
Test name
Test status
Simulation time 5467581104 ps
CPU time 38.5 seconds
Started Jul 10 06:46:37 PM PDT 24
Finished Jul 10 06:47:20 PM PDT 24
Peak memory 206612 kb
Host smart-29053588-6b4b-4638-8549-765799fcf6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21189
40054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2118940054
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.741726559
Short name T2354
Test name
Test status
Simulation time 3582329036 ps
CPU time 32.99 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:47:31 PM PDT 24
Peak memory 206652 kb
Host smart-ab4fac5b-66f9-473e-b0ac-50ae252a53bd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=741726559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.741726559
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1317573999
Short name T2489
Test name
Test status
Simulation time 153170652 ps
CPU time 0.77 seconds
Started Jul 10 06:46:51 PM PDT 24
Finished Jul 10 06:46:54 PM PDT 24
Peak memory 206332 kb
Host smart-267a4df0-c475-42a7-b404-3b86c544b4fa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1317573999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1317573999
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3063834699
Short name T1630
Test name
Test status
Simulation time 148407305 ps
CPU time 0.84 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:46:57 PM PDT 24
Peak memory 206380 kb
Host smart-c6696e14-e6b8-488d-870a-b2651a068852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
34699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3063834699
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3712820713
Short name T121
Test name
Test status
Simulation time 223265330 ps
CPU time 0.87 seconds
Started Jul 10 06:46:41 PM PDT 24
Finished Jul 10 06:46:45 PM PDT 24
Peak memory 206248 kb
Host smart-08d3f890-f8c7-415b-b63a-2921c0daa7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37128
20713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3712820713
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1154112547
Short name T1188
Test name
Test status
Simulation time 166312285 ps
CPU time 0.87 seconds
Started Jul 10 06:46:51 PM PDT 24
Finished Jul 10 06:46:53 PM PDT 24
Peak memory 206280 kb
Host smart-ea492598-4bc1-4fc7-879e-fb77b9e1a502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11541
12547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1154112547
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.206225106
Short name T2227
Test name
Test status
Simulation time 155690697 ps
CPU time 0.78 seconds
Started Jul 10 06:46:45 PM PDT 24
Finished Jul 10 06:46:47 PM PDT 24
Peak memory 206280 kb
Host smart-24abb1d8-52d8-4d5a-8e60-e166c557e85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
5106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.206225106
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3594164047
Short name T2053
Test name
Test status
Simulation time 174904124 ps
CPU time 0.89 seconds
Started Jul 10 06:46:37 PM PDT 24
Finished Jul 10 06:46:43 PM PDT 24
Peak memory 206364 kb
Host smart-d359a2ab-ce1c-4bff-9f46-cd1ce2425733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35941
64047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3594164047
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1142497112
Short name T181
Test name
Test status
Simulation time 180418475 ps
CPU time 0.85 seconds
Started Jul 10 06:46:51 PM PDT 24
Finished Jul 10 06:46:53 PM PDT 24
Peak memory 206400 kb
Host smart-707b733f-c63d-42c4-b096-3739cfa628fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11424
97112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1142497112
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.928195416
Short name T1956
Test name
Test status
Simulation time 251221184 ps
CPU time 0.99 seconds
Started Jul 10 06:46:51 PM PDT 24
Finished Jul 10 06:46:54 PM PDT 24
Peak memory 206404 kb
Host smart-486672c4-b0bf-47d7-96bd-6865402ddcfe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=928195416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.928195416
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3124980714
Short name T2498
Test name
Test status
Simulation time 150701732 ps
CPU time 0.79 seconds
Started Jul 10 06:46:41 PM PDT 24
Finished Jul 10 06:46:45 PM PDT 24
Peak memory 206288 kb
Host smart-b73f62ca-0615-4534-a88e-17d794a103a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31249
80714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3124980714
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1564565532
Short name T1787
Test name
Test status
Simulation time 38956272 ps
CPU time 0.66 seconds
Started Jul 10 06:46:37 PM PDT 24
Finished Jul 10 06:46:42 PM PDT 24
Peak memory 206372 kb
Host smart-3343c414-3e9c-4e47-b257-e06a1e391600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15645
65532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1564565532
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2339695585
Short name T2435
Test name
Test status
Simulation time 8217785573 ps
CPU time 19 seconds
Started Jul 10 06:46:35 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 206652 kb
Host smart-b7dd7ac8-95be-448f-82d8-606aebee16ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23396
95585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2339695585
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2869902393
Short name T2014
Test name
Test status
Simulation time 174617658 ps
CPU time 0.85 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:08 PM PDT 24
Peak memory 206356 kb
Host smart-0534a2e7-f662-4e61-896e-958f73dc131a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
02393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2869902393
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3368459254
Short name T925
Test name
Test status
Simulation time 221088154 ps
CPU time 0.84 seconds
Started Jul 10 06:46:48 PM PDT 24
Finished Jul 10 06:46:50 PM PDT 24
Peak memory 206308 kb
Host smart-b50f69b0-5535-41a8-bed5-80b32a4a471f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33684
59254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3368459254
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3326798593
Short name T810
Test name
Test status
Simulation time 251912308 ps
CPU time 0.91 seconds
Started Jul 10 06:46:49 PM PDT 24
Finished Jul 10 06:46:51 PM PDT 24
Peak memory 206400 kb
Host smart-dc2f5257-32d7-482b-8b5b-9455aea47f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33267
98593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3326798593
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1422401465
Short name T1055
Test name
Test status
Simulation time 235733275 ps
CPU time 0.91 seconds
Started Jul 10 06:46:53 PM PDT 24
Finished Jul 10 06:46:55 PM PDT 24
Peak memory 206404 kb
Host smart-bc7ea656-5031-45be-a712-83629daa525a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
01465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1422401465
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.859513794
Short name T1867
Test name
Test status
Simulation time 223872896 ps
CPU time 0.87 seconds
Started Jul 10 06:47:01 PM PDT 24
Finished Jul 10 06:47:06 PM PDT 24
Peak memory 206392 kb
Host smart-d0cfad36-0bdb-494d-8f9d-236b653a6585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85951
3794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.859513794
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1018018222
Short name T405
Test name
Test status
Simulation time 155119481 ps
CPU time 0.83 seconds
Started Jul 10 06:46:57 PM PDT 24
Finished Jul 10 06:47:01 PM PDT 24
Peak memory 206360 kb
Host smart-9f2227a4-3cef-4195-8182-904c4299d567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
18222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1018018222
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2258455962
Short name T1169
Test name
Test status
Simulation time 159143278 ps
CPU time 0.82 seconds
Started Jul 10 06:46:44 PM PDT 24
Finished Jul 10 06:46:46 PM PDT 24
Peak memory 206560 kb
Host smart-06b5d69d-15ae-4d91-82c1-0d76bf046da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22584
55962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2258455962
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3745661057
Short name T1451
Test name
Test status
Simulation time 227980552 ps
CPU time 0.92 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206376 kb
Host smart-4b39b310-0a70-4381-8e9e-43cf82802082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37456
61057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3745661057
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.2617559326
Short name T1960
Test name
Test status
Simulation time 4378940618 ps
CPU time 113.45 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:48:56 PM PDT 24
Peak memory 206592 kb
Host smart-a5c04067-4d62-4e83-b760-570797afbee1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2617559326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.2617559326
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3141577568
Short name T429
Test name
Test status
Simulation time 190794788 ps
CPU time 0.86 seconds
Started Jul 10 06:46:44 PM PDT 24
Finished Jul 10 06:46:47 PM PDT 24
Peak memory 206384 kb
Host smart-81004e12-27d9-4079-b6c0-a88934b8a81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31415
77568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3141577568
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1207335402
Short name T2166
Test name
Test status
Simulation time 144086760 ps
CPU time 0.8 seconds
Started Jul 10 06:46:45 PM PDT 24
Finished Jul 10 06:46:47 PM PDT 24
Peak memory 206348 kb
Host smart-ba4652f2-8c84-494b-ae9f-d94f65ebd03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
35402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1207335402
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2051297819
Short name T648
Test name
Test status
Simulation time 328032810 ps
CPU time 1.12 seconds
Started Jul 10 06:46:50 PM PDT 24
Finished Jul 10 06:46:52 PM PDT 24
Peak memory 206344 kb
Host smart-16e3dc0c-1b39-40fd-93f6-4694d454eb69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20512
97819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2051297819
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.2173680964
Short name T1007
Test name
Test status
Simulation time 3709186500 ps
CPU time 105.98 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:48:44 PM PDT 24
Peak memory 206680 kb
Host smart-654bbc5d-2214-4684-8ee2-20f0a2ac211f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21736
80964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2173680964
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3430029530
Short name T1534
Test name
Test status
Simulation time 43225979 ps
CPU time 0.72 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206432 kb
Host smart-16d4eedd-d8de-49e9-afae-eee069afd1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3430029530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3430029530
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3481425039
Short name T2385
Test name
Test status
Simulation time 4467937482 ps
CPU time 5.43 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206632 kb
Host smart-ae890d03-5e5b-4ac8-9d48-bb83a3a7d078
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3481425039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.3481425039
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3580351413
Short name T2418
Test name
Test status
Simulation time 13378127717 ps
CPU time 13.64 seconds
Started Jul 10 06:46:51 PM PDT 24
Finished Jul 10 06:47:05 PM PDT 24
Peak memory 206468 kb
Host smart-7b9f92bb-53bf-4dcb-9676-557435b25ecd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3580351413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3580351413
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2043081667
Short name T1099
Test name
Test status
Simulation time 23452565269 ps
CPU time 25.71 seconds
Started Jul 10 06:46:44 PM PDT 24
Finished Jul 10 06:47:11 PM PDT 24
Peak memory 206660 kb
Host smart-61c8169c-7f3a-4eb1-82e4-2f42a8856d1e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2043081667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.2043081667
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1552583709
Short name T2330
Test name
Test status
Simulation time 197557208 ps
CPU time 0.91 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206364 kb
Host smart-93cbe688-ae74-49b1-8c6e-ee1646f2a90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15525
83709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1552583709
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2011148928
Short name T534
Test name
Test status
Simulation time 150859298 ps
CPU time 0.82 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:46:56 PM PDT 24
Peak memory 206380 kb
Host smart-95b0fecc-285d-4124-b890-9b4e8c142673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20111
48928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2011148928
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.10734083
Short name T2365
Test name
Test status
Simulation time 459588336 ps
CPU time 1.39 seconds
Started Jul 10 06:46:45 PM PDT 24
Finished Jul 10 06:46:48 PM PDT 24
Peak memory 206316 kb
Host smart-7394f3d2-d280-4472-8649-43b8a3dc6d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10734
083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.10734083
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3981888546
Short name T2088
Test name
Test status
Simulation time 1450101960 ps
CPU time 3.25 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 206644 kb
Host smart-8bebd5e5-5a8a-46cb-bc7d-9cb0c352c210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
88546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3981888546
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2051198825
Short name T1781
Test name
Test status
Simulation time 453132459 ps
CPU time 1.4 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 206392 kb
Host smart-fbb6d2a2-81d8-492c-bf05-38f0a5d05be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20511
98825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2051198825
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.755698103
Short name T1954
Test name
Test status
Simulation time 154335999 ps
CPU time 0.78 seconds
Started Jul 10 06:46:53 PM PDT 24
Finished Jul 10 06:46:56 PM PDT 24
Peak memory 206364 kb
Host smart-507ddf30-66e0-4630-8519-f30720cb84cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75569
8103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.755698103
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3313211463
Short name T2377
Test name
Test status
Simulation time 48549862 ps
CPU time 0.67 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:47:04 PM PDT 24
Peak memory 206348 kb
Host smart-a1807b0d-1dfb-4995-8197-356a36ee749a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33132
11463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3313211463
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.771846243
Short name T1431
Test name
Test status
Simulation time 673243910 ps
CPU time 1.91 seconds
Started Jul 10 06:46:43 PM PDT 24
Finished Jul 10 06:46:47 PM PDT 24
Peak memory 206624 kb
Host smart-9f9fd269-bdc8-46fd-bb87-cd5c46b2beeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77184
6243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.771846243
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1134540534
Short name T2714
Test name
Test status
Simulation time 197290685 ps
CPU time 1.28 seconds
Started Jul 10 06:46:52 PM PDT 24
Finished Jul 10 06:46:55 PM PDT 24
Peak memory 206548 kb
Host smart-da07c4db-fed8-4417-acb3-bd5970158b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11345
40534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1134540534
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.4150673661
Short name T1844
Test name
Test status
Simulation time 173578073 ps
CPU time 0.88 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:47:05 PM PDT 24
Peak memory 206380 kb
Host smart-f55e173f-eeaa-4d56-8e5c-9822fa3dddbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
73661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.4150673661
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2598331477
Short name T1131
Test name
Test status
Simulation time 151854583 ps
CPU time 0.83 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:46:57 PM PDT 24
Peak memory 206376 kb
Host smart-f58f14f6-3ccf-49ce-a125-9fcfa3841301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
31477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2598331477
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3944804204
Short name T812
Test name
Test status
Simulation time 186071115 ps
CPU time 0.87 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206344 kb
Host smart-abdc234a-3a6f-4537-b207-dd68c6862832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
04204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3944804204
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.3816350
Short name T855
Test name
Test status
Simulation time 6455156898 ps
CPU time 59.49 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:47:56 PM PDT 24
Peak memory 206604 kb
Host smart-7ae535c4-d399-4139-a69d-459039218f7f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3816350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3816350
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1671679706
Short name T454
Test name
Test status
Simulation time 12158112055 ps
CPU time 43.93 seconds
Started Jul 10 06:46:56 PM PDT 24
Finished Jul 10 06:47:43 PM PDT 24
Peak memory 206816 kb
Host smart-1c3c7167-3a0a-46a2-bd4f-b2f8fb3dc96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16716
79706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1671679706
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.4068371115
Short name T799
Test name
Test status
Simulation time 182257287 ps
CPU time 0.87 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:47:03 PM PDT 24
Peak memory 206364 kb
Host smart-53900423-fe85-4b1d-9803-1f4995d6bc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40683
71115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.4068371115
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.4197598540
Short name T1719
Test name
Test status
Simulation time 23302543534 ps
CPU time 26.42 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:47:23 PM PDT 24
Peak memory 206420 kb
Host smart-87bb5a9a-b723-4ed5-a20e-88203e10926d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41975
98540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.4197598540
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.62415407
Short name T692
Test name
Test status
Simulation time 3318501626 ps
CPU time 4.06 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:06 PM PDT 24
Peak memory 206380 kb
Host smart-bb8040bc-c3d6-4212-bc12-e8b9a761794b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62415
407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.62415407
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1060368418
Short name T1242
Test name
Test status
Simulation time 8423549777 ps
CPU time 240.1 seconds
Started Jul 10 06:46:43 PM PDT 24
Finished Jul 10 06:50:45 PM PDT 24
Peak memory 206736 kb
Host smart-2c9908d7-0a96-469c-ba38-c09dfedadb94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10603
68418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1060368418
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.138191975
Short name T1351
Test name
Test status
Simulation time 2970930485 ps
CPU time 22.99 seconds
Started Jul 10 06:46:52 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206632 kb
Host smart-65908678-5f23-435b-8d14-7e0e2baabdda
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=138191975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.138191975
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.4085319276
Short name T2451
Test name
Test status
Simulation time 268680193 ps
CPU time 1.01 seconds
Started Jul 10 06:46:52 PM PDT 24
Finished Jul 10 06:46:55 PM PDT 24
Peak memory 206372 kb
Host smart-78f128d7-aa4e-4911-99aa-90a1bf1e45c3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4085319276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.4085319276
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1919097330
Short name T1124
Test name
Test status
Simulation time 203439558 ps
CPU time 0.87 seconds
Started Jul 10 06:46:46 PM PDT 24
Finished Jul 10 06:46:48 PM PDT 24
Peak memory 206380 kb
Host smart-16785b2a-5055-40fe-8d27-cbe368b4cbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190
97330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1919097330
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.592599673
Short name T399
Test name
Test status
Simulation time 3714047842 ps
CPU time 27.16 seconds
Started Jul 10 06:46:57 PM PDT 24
Finished Jul 10 06:47:27 PM PDT 24
Peak memory 206624 kb
Host smart-b477963c-f319-44c4-aab8-75c40910898e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59259
9673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.592599673
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3291500100
Short name T387
Test name
Test status
Simulation time 6102488568 ps
CPU time 160.55 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:49:38 PM PDT 24
Peak memory 206636 kb
Host smart-d39f23c9-2896-4a68-bc1d-2c8703069d10
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3291500100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3291500100
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2027164496
Short name T363
Test name
Test status
Simulation time 169412611 ps
CPU time 0.87 seconds
Started Jul 10 06:46:57 PM PDT 24
Finished Jul 10 06:47:01 PM PDT 24
Peak memory 206400 kb
Host smart-e2ab0ac2-af48-4c07-8778-789d154048c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2027164496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2027164496
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1077523378
Short name T2461
Test name
Test status
Simulation time 144485151 ps
CPU time 0.79 seconds
Started Jul 10 06:46:57 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206392 kb
Host smart-3ca412de-1ed7-4bfb-a172-23cb6ee8b53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775
23378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1077523378
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.325455693
Short name T2025
Test name
Test status
Simulation time 215025470 ps
CPU time 0.85 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206348 kb
Host smart-99a41dff-4256-454f-801c-5f0fcb9adea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32545
5693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.325455693
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.487013629
Short name T1663
Test name
Test status
Simulation time 186008467 ps
CPU time 0.89 seconds
Started Jul 10 06:46:57 PM PDT 24
Finished Jul 10 06:47:01 PM PDT 24
Peak memory 206384 kb
Host smart-e931073e-3c03-429d-b9e8-bc8e6a668601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48701
3629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.487013629
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.30376256
Short name T629
Test name
Test status
Simulation time 192205090 ps
CPU time 0.84 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206384 kb
Host smart-848acad1-cd88-4627-b0c2-3fd6fff0244d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.30376256
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3293449037
Short name T1229
Test name
Test status
Simulation time 159959356 ps
CPU time 0.83 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206376 kb
Host smart-051baedb-7043-4a5f-adf9-969ad9412e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32934
49037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3293449037
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.4219036351
Short name T1912
Test name
Test status
Simulation time 168898453 ps
CPU time 0.86 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206400 kb
Host smart-14b2c1a1-7fd4-4be5-ad92-9297d8ed771e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42190
36351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.4219036351
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3921049946
Short name T1136
Test name
Test status
Simulation time 220828676 ps
CPU time 0.91 seconds
Started Jul 10 06:47:02 PM PDT 24
Finished Jul 10 06:47:07 PM PDT 24
Peak memory 206376 kb
Host smart-59d707cb-34ae-4356-adf1-c571f8ef934e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3921049946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3921049946
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2765948804
Short name T752
Test name
Test status
Simulation time 149237941 ps
CPU time 0.81 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:46:59 PM PDT 24
Peak memory 206376 kb
Host smart-990b3b7c-8943-4836-b30c-115a4af64423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659
48804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2765948804
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3320484169
Short name T772
Test name
Test status
Simulation time 42137961 ps
CPU time 0.66 seconds
Started Jul 10 06:47:01 PM PDT 24
Finished Jul 10 06:47:06 PM PDT 24
Peak memory 206384 kb
Host smart-d40e192f-9453-4cb8-b004-0c5f50c5a4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33204
84169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3320484169
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.4218436799
Short name T1276
Test name
Test status
Simulation time 21595897170 ps
CPU time 47.23 seconds
Started Jul 10 06:47:05 PM PDT 24
Finished Jul 10 06:47:56 PM PDT 24
Peak memory 206692 kb
Host smart-045bb9f9-7e29-4d0d-9f04-95307f20adba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42184
36799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.4218436799
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2259511894
Short name T419
Test name
Test status
Simulation time 186410114 ps
CPU time 0.83 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:07 PM PDT 24
Peak memory 206380 kb
Host smart-2998c7ec-7833-422c-80c4-8d9c2862fe82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22595
11894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2259511894
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3822069001
Short name T1439
Test name
Test status
Simulation time 184815065 ps
CPU time 0.84 seconds
Started Jul 10 06:46:54 PM PDT 24
Finished Jul 10 06:46:57 PM PDT 24
Peak memory 206372 kb
Host smart-e9e10142-8d88-41ca-b20c-aa7d42e2ab4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38220
69001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3822069001
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.41893357
Short name T2063
Test name
Test status
Simulation time 237147349 ps
CPU time 0.97 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:46:58 PM PDT 24
Peak memory 206396 kb
Host smart-a9e193fb-0b77-4ba0-b820-75acdac338fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41893
357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.41893357
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1932850049
Short name T1733
Test name
Test status
Simulation time 158647854 ps
CPU time 0.87 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:07 PM PDT 24
Peak memory 206396 kb
Host smart-36829666-fcfa-4450-8746-a72c09c7d2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19328
50049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1932850049
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.995084719
Short name T1329
Test name
Test status
Simulation time 153245796 ps
CPU time 0.75 seconds
Started Jul 10 06:47:07 PM PDT 24
Finished Jul 10 06:47:11 PM PDT 24
Peak memory 206392 kb
Host smart-88cd9a16-be5e-4489-a9c3-a74e338aca01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99508
4719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.995084719
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.268443071
Short name T994
Test name
Test status
Simulation time 173635435 ps
CPU time 0.8 seconds
Started Jul 10 06:47:00 PM PDT 24
Finished Jul 10 06:47:05 PM PDT 24
Peak memory 206556 kb
Host smart-3b0f9cd8-6869-495e-9bc5-214daaa823e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26844
3071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.268443071
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.104820163
Short name T100
Test name
Test status
Simulation time 155934578 ps
CPU time 0.77 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:46:59 PM PDT 24
Peak memory 206372 kb
Host smart-5b79ee6b-187f-47fe-af6e-b2a54e986b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10482
0163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.104820163
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3771107829
Short name T664
Test name
Test status
Simulation time 282332994 ps
CPU time 1 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:47:03 PM PDT 24
Peak memory 206376 kb
Host smart-cfdd4b77-b663-488a-b023-59070401ab34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37711
07829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3771107829
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2507913464
Short name T649
Test name
Test status
Simulation time 3732143031 ps
CPU time 34.24 seconds
Started Jul 10 06:47:01 PM PDT 24
Finished Jul 10 06:47:39 PM PDT 24
Peak memory 206700 kb
Host smart-a94aa430-1f89-4261-99cb-f892922d5c49
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2507913464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2507913464
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2110819686
Short name T2495
Test name
Test status
Simulation time 170186021 ps
CPU time 0.79 seconds
Started Jul 10 06:47:17 PM PDT 24
Finished Jul 10 06:47:19 PM PDT 24
Peak memory 206384 kb
Host smart-744ecba7-877d-41e2-a91b-c8a600cd1332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108
19686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2110819686
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3607652368
Short name T1615
Test name
Test status
Simulation time 180106807 ps
CPU time 0.85 seconds
Started Jul 10 06:47:06 PM PDT 24
Finished Jul 10 06:47:11 PM PDT 24
Peak memory 206376 kb
Host smart-68a9ae35-a2e9-438c-9bfc-69e751c48769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36076
52368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3607652368
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1356529448
Short name T1814
Test name
Test status
Simulation time 470382624 ps
CPU time 1.33 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 206376 kb
Host smart-667a7fa7-1bac-4532-8395-f48ce1661707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13565
29448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1356529448
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1027427822
Short name T384
Test name
Test status
Simulation time 3471163953 ps
CPU time 93.99 seconds
Started Jul 10 06:46:53 PM PDT 24
Finished Jul 10 06:48:29 PM PDT 24
Peak memory 206680 kb
Host smart-24c52329-2339-415d-bb57-cb8d6b9c39d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
27822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1027427822
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2025288353
Short name T2275
Test name
Test status
Simulation time 42129819 ps
CPU time 0.68 seconds
Started Jul 10 06:47:02 PM PDT 24
Finished Jul 10 06:47:07 PM PDT 24
Peak memory 206416 kb
Host smart-1cc50bd6-4d54-4b5a-aa31-f3f879be629e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2025288353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2025288353
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3124168924
Short name T8
Test name
Test status
Simulation time 4147112113 ps
CPU time 5.17 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:47:04 PM PDT 24
Peak memory 206440 kb
Host smart-273186b0-d1fa-4d8a-bafb-cfec4291c177
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3124168924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3124168924
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2559656939
Short name T1071
Test name
Test status
Simulation time 13308379357 ps
CPU time 12.56 seconds
Started Jul 10 06:46:57 PM PDT 24
Finished Jul 10 06:47:13 PM PDT 24
Peak memory 206464 kb
Host smart-f28db17e-fd49-4489-8e2c-dc5e022e8362
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2559656939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2559656939
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.462272840
Short name T1764
Test name
Test status
Simulation time 23330991313 ps
CPU time 25.3 seconds
Started Jul 10 06:46:55 PM PDT 24
Finished Jul 10 06:47:23 PM PDT 24
Peak memory 206692 kb
Host smart-d5bb6a3d-3dcc-40ff-bb8c-5f9516029f71
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=462272840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.462272840
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.287362997
Short name T1625
Test name
Test status
Simulation time 167098304 ps
CPU time 0.8 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:08 PM PDT 24
Peak memory 206352 kb
Host smart-2ad776e6-2b35-434f-99a9-dc06ef85f77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28736
2997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.287362997
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2274410694
Short name T1468
Test name
Test status
Simulation time 140903775 ps
CPU time 0.78 seconds
Started Jul 10 06:46:56 PM PDT 24
Finished Jul 10 06:47:00 PM PDT 24
Peak memory 206380 kb
Host smart-1600bd1a-1c7a-4c44-a7dd-03036351adfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22744
10694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2274410694
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2899476438
Short name T2203
Test name
Test status
Simulation time 220826389 ps
CPU time 0.99 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206392 kb
Host smart-663369a6-25d7-4783-aaa0-fc2e8260dd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28994
76438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2899476438
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2299824164
Short name T839
Test name
Test status
Simulation time 1127346937 ps
CPU time 2.6 seconds
Started Jul 10 06:47:02 PM PDT 24
Finished Jul 10 06:47:09 PM PDT 24
Peak memory 206612 kb
Host smart-a6b8cede-36ee-49ac-9c65-8e7d3146b4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22998
24164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2299824164
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1755016105
Short name T1104
Test name
Test status
Simulation time 10069237160 ps
CPU time 19.48 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:47:23 PM PDT 24
Peak memory 206728 kb
Host smart-20b9f95d-6ed3-4caf-93c1-f8b4249550db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17550
16105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1755016105
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1165340699
Short name T2308
Test name
Test status
Simulation time 402230639 ps
CPU time 1.3 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:03 PM PDT 24
Peak memory 206400 kb
Host smart-580f36a3-0644-4d3a-8279-ab0fd16960c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11653
40699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1165340699
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.27908084
Short name T1026
Test name
Test status
Simulation time 142872220 ps
CPU time 0.75 seconds
Started Jul 10 06:46:58 PM PDT 24
Finished Jul 10 06:47:02 PM PDT 24
Peak memory 206396 kb
Host smart-b298d156-b885-4ad4-a83f-b9002aff1826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27908
084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.27908084
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1940046893
Short name T2631
Test name
Test status
Simulation time 35653894 ps
CPU time 0.64 seconds
Started Jul 10 06:47:02 PM PDT 24
Finished Jul 10 06:47:06 PM PDT 24
Peak memory 206364 kb
Host smart-0ab4f5db-7074-4970-a8b2-9679997fea1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19400
46893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1940046893
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1187261461
Short name T612
Test name
Test status
Simulation time 1030914222 ps
CPU time 2.57 seconds
Started Jul 10 06:47:09 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206560 kb
Host smart-b6103146-a4e8-40ec-a42f-53fa4e242e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11872
61461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1187261461
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3590369611
Short name T1966
Test name
Test status
Simulation time 193450997 ps
CPU time 1.62 seconds
Started Jul 10 06:47:01 PM PDT 24
Finished Jul 10 06:47:07 PM PDT 24
Peak memory 206624 kb
Host smart-c1e2676f-a32f-44fc-9b64-7fcd3a923b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35903
69611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3590369611
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.4050100954
Short name T2599
Test name
Test status
Simulation time 193395781 ps
CPU time 0.91 seconds
Started Jul 10 06:47:06 PM PDT 24
Finished Jul 10 06:47:11 PM PDT 24
Peak memory 206392 kb
Host smart-09e22c78-82ba-44d9-9bac-1e620c3a6ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40501
00954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.4050100954
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1174645643
Short name T1537
Test name
Test status
Simulation time 153884048 ps
CPU time 0.76 seconds
Started Jul 10 06:47:15 PM PDT 24
Finished Jul 10 06:47:18 PM PDT 24
Peak memory 206400 kb
Host smart-57a5a1b3-6bfa-4293-a151-06c09315c89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11746
45643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1174645643
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.201951086
Short name T2195
Test name
Test status
Simulation time 239257039 ps
CPU time 0.96 seconds
Started Jul 10 06:47:01 PM PDT 24
Finished Jul 10 06:47:06 PM PDT 24
Peak memory 206344 kb
Host smart-58ff3bca-d830-430b-9a72-cff5d0545379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20195
1086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.201951086
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.4089343393
Short name T826
Test name
Test status
Simulation time 260111637 ps
CPU time 0.95 seconds
Started Jul 10 06:47:09 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206360 kb
Host smart-d23672a1-d81a-411b-b4a5-1115b879768e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40893
43393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.4089343393
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.656636972
Short name T724
Test name
Test status
Simulation time 23352152922 ps
CPU time 24.8 seconds
Started Jul 10 06:47:11 PM PDT 24
Finished Jul 10 06:47:39 PM PDT 24
Peak memory 206440 kb
Host smart-d0ad6121-e9d8-4672-a2ae-684fccbc39c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65663
6972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.656636972
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.16544985
Short name T1285
Test name
Test status
Simulation time 3293071766 ps
CPU time 3.84 seconds
Started Jul 10 06:47:05 PM PDT 24
Finished Jul 10 06:47:13 PM PDT 24
Peak memory 206448 kb
Host smart-476a9cec-6c9e-4214-8c39-fbbbe7f62a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16544
985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.16544985
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.195615435
Short name T152
Test name
Test status
Simulation time 6819281672 ps
CPU time 49.85 seconds
Started Jul 10 06:47:02 PM PDT 24
Finished Jul 10 06:47:56 PM PDT 24
Peak memory 206704 kb
Host smart-8326aae4-fbee-4974-9e74-6bd71b66c447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19561
5435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.195615435
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2986284466
Short name T2316
Test name
Test status
Simulation time 4448548712 ps
CPU time 32.25 seconds
Started Jul 10 06:47:15 PM PDT 24
Finished Jul 10 06:47:50 PM PDT 24
Peak memory 206648 kb
Host smart-6bf8943c-a465-413f-94a5-ac373edac9ce
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2986284466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2986284466
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2251501844
Short name T1586
Test name
Test status
Simulation time 258903449 ps
CPU time 1.05 seconds
Started Jul 10 06:47:16 PM PDT 24
Finished Jul 10 06:47:19 PM PDT 24
Peak memory 206372 kb
Host smart-26fb249b-bff7-4083-b804-6b0fbc1d71a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2251501844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2251501844
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1692438839
Short name T2324
Test name
Test status
Simulation time 188047621 ps
CPU time 0.88 seconds
Started Jul 10 06:47:02 PM PDT 24
Finished Jul 10 06:47:07 PM PDT 24
Peak memory 206396 kb
Host smart-0be5eff7-8e80-40d8-b182-161e3f794b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16924
38839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1692438839
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.1767813973
Short name T1785
Test name
Test status
Simulation time 2966032611 ps
CPU time 79.91 seconds
Started Jul 10 06:47:08 PM PDT 24
Finished Jul 10 06:48:31 PM PDT 24
Peak memory 206668 kb
Host smart-1a220570-73dc-4c92-aeaf-5ac4e0c75c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17678
13973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.1767813973
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2738813169
Short name T6
Test name
Test status
Simulation time 4522820177 ps
CPU time 125.28 seconds
Started Jul 10 06:47:08 PM PDT 24
Finished Jul 10 06:49:17 PM PDT 24
Peak memory 206656 kb
Host smart-4e1961ee-6e35-4742-8c89-5321af6a01f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2738813169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2738813169
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1878899446
Short name T1107
Test name
Test status
Simulation time 165095732 ps
CPU time 0.84 seconds
Started Jul 10 06:47:09 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206356 kb
Host smart-84f58972-a2af-471b-b7df-e8f2cb9527d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1878899446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1878899446
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1568265905
Short name T1488
Test name
Test status
Simulation time 180047846 ps
CPU time 0.79 seconds
Started Jul 10 06:47:07 PM PDT 24
Finished Jul 10 06:47:12 PM PDT 24
Peak memory 206392 kb
Host smart-20077703-1fef-4bde-bc08-7b81a0b31490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15682
65905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1568265905
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1588001655
Short name T1672
Test name
Test status
Simulation time 224004721 ps
CPU time 0.91 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:47:04 PM PDT 24
Peak memory 206388 kb
Host smart-928fa4ad-076c-4f0a-b78c-0bd484a671b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15880
01655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1588001655
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2465481394
Short name T1304
Test name
Test status
Simulation time 163104648 ps
CPU time 0.91 seconds
Started Jul 10 06:47:15 PM PDT 24
Finished Jul 10 06:47:18 PM PDT 24
Peak memory 206376 kb
Host smart-d9abe834-9107-4f8c-9b39-492198eabe11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24654
81394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2465481394
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.806923841
Short name T1635
Test name
Test status
Simulation time 188748508 ps
CPU time 0.83 seconds
Started Jul 10 06:47:06 PM PDT 24
Finished Jul 10 06:47:11 PM PDT 24
Peak memory 206384 kb
Host smart-b5d4aa95-0a2f-4966-a23e-cfd8aaab946e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80692
3841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.806923841
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.4086351875
Short name T1267
Test name
Test status
Simulation time 162856687 ps
CPU time 0.81 seconds
Started Jul 10 06:47:12 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206376 kb
Host smart-0ded4671-6690-4e65-8791-cc390df4c700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40863
51875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.4086351875
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.4086251199
Short name T2140
Test name
Test status
Simulation time 150981599 ps
CPU time 0.85 seconds
Started Jul 10 06:46:59 PM PDT 24
Finished Jul 10 06:47:05 PM PDT 24
Peak memory 206384 kb
Host smart-b3afa89e-1009-46d8-a8d2-1ce0d9219d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
51199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.4086251199
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3656746833
Short name T1282
Test name
Test status
Simulation time 327414823 ps
CPU time 1.08 seconds
Started Jul 10 06:47:09 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206364 kb
Host smart-23be5fc6-c2f6-44e2-9b86-9c68e5a939f0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3656746833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3656746833
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3820991118
Short name T2492
Test name
Test status
Simulation time 205614030 ps
CPU time 0.84 seconds
Started Jul 10 06:47:04 PM PDT 24
Finished Jul 10 06:47:09 PM PDT 24
Peak memory 206392 kb
Host smart-8bc180f8-ac16-466f-858d-ba55c06dfd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38209
91118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3820991118
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1247488074
Short name T1700
Test name
Test status
Simulation time 40531265 ps
CPU time 0.65 seconds
Started Jul 10 06:47:15 PM PDT 24
Finished Jul 10 06:47:18 PM PDT 24
Peak memory 206396 kb
Host smart-dc9508c8-a1eb-45f5-9f9e-aa58446e505f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12474
88074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1247488074
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2729680417
Short name T2709
Test name
Test status
Simulation time 18279576693 ps
CPU time 46.77 seconds
Started Jul 10 06:47:18 PM PDT 24
Finished Jul 10 06:48:06 PM PDT 24
Peak memory 206756 kb
Host smart-d3ffdec0-480e-467d-97d2-8e17568493a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27296
80417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2729680417
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.9320003
Short name T2662
Test name
Test status
Simulation time 171960972 ps
CPU time 0.84 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:07 PM PDT 24
Peak memory 206372 kb
Host smart-27854d00-fdc6-4e1f-8147-c03950ac9079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93200
03 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.9320003
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1091653728
Short name T1676
Test name
Test status
Simulation time 209534981 ps
CPU time 0.85 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:08 PM PDT 24
Peak memory 206376 kb
Host smart-36947551-3d11-4919-bcdd-6602b7f705a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10916
53728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1091653728
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2102648818
Short name T1491
Test name
Test status
Simulation time 166377419 ps
CPU time 0.8 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:08 PM PDT 24
Peak memory 206396 kb
Host smart-bc3a922d-f05d-4b40-ab30-ae021a48a36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21026
48818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2102648818
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1581088103
Short name T988
Test name
Test status
Simulation time 176628401 ps
CPU time 0.83 seconds
Started Jul 10 06:47:10 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206364 kb
Host smart-050a8418-153f-4746-accb-556f16e87bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15810
88103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1581088103
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.241733804
Short name T2519
Test name
Test status
Simulation time 184544373 ps
CPU time 0.83 seconds
Started Jul 10 06:47:04 PM PDT 24
Finished Jul 10 06:47:09 PM PDT 24
Peak memory 206380 kb
Host smart-d5532842-fd93-4005-b5b1-e5b6cc202eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24173
3804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.241733804
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2391912673
Short name T783
Test name
Test status
Simulation time 159210880 ps
CPU time 0.79 seconds
Started Jul 10 06:47:08 PM PDT 24
Finished Jul 10 06:47:12 PM PDT 24
Peak memory 206372 kb
Host smart-3e9562cb-2676-44f8-a23a-9fe2c22798cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23919
12673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2391912673
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.986116036
Short name T386
Test name
Test status
Simulation time 214608456 ps
CPU time 0.87 seconds
Started Jul 10 06:47:11 PM PDT 24
Finished Jul 10 06:47:15 PM PDT 24
Peak memory 206376 kb
Host smart-c8a24650-dcac-4c23-9b80-56996b935491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98611
6036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.986116036
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2323992258
Short name T2337
Test name
Test status
Simulation time 5950351003 ps
CPU time 170.22 seconds
Started Jul 10 06:47:04 PM PDT 24
Finished Jul 10 06:49:58 PM PDT 24
Peak memory 206612 kb
Host smart-7ec65b75-ca09-400c-8659-7aac02a7bffa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2323992258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2323992258
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2570585807
Short name T2176
Test name
Test status
Simulation time 200939473 ps
CPU time 0.85 seconds
Started Jul 10 06:47:05 PM PDT 24
Finished Jul 10 06:47:10 PM PDT 24
Peak memory 206392 kb
Host smart-7cd36a2d-c5b9-4c4a-aa17-9d8b3c5c036d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705
85807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2570585807
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3150830961
Short name T931
Test name
Test status
Simulation time 195521087 ps
CPU time 0.82 seconds
Started Jul 10 06:47:10 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206276 kb
Host smart-a19e010d-3dbb-43c3-ab32-204fca8e9cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31508
30961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3150830961
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2062196118
Short name T1853
Test name
Test status
Simulation time 438032848 ps
CPU time 1.25 seconds
Started Jul 10 06:47:04 PM PDT 24
Finished Jul 10 06:47:09 PM PDT 24
Peak memory 206364 kb
Host smart-50836561-d36e-42f7-9adf-493049e205b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20621
96118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2062196118
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3030219910
Short name T2134
Test name
Test status
Simulation time 4144784505 ps
CPU time 38.56 seconds
Started Jul 10 06:47:09 PM PDT 24
Finished Jul 10 06:47:52 PM PDT 24
Peak memory 206536 kb
Host smart-7cf2cf06-985d-4c26-85d6-46517b93df49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
19910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3030219910
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.2284695499
Short name T803
Test name
Test status
Simulation time 39863549 ps
CPU time 0.69 seconds
Started Jul 10 06:47:13 PM PDT 24
Finished Jul 10 06:47:17 PM PDT 24
Peak memory 206608 kb
Host smart-7294ca5b-0d57-421b-a5bb-7755e657ee8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2284695499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2284695499
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.217511194
Short name T2432
Test name
Test status
Simulation time 4368152184 ps
CPU time 5.14 seconds
Started Jul 10 06:47:07 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206676 kb
Host smart-84830ec0-6b44-46b0-8a4b-561068997f22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=217511194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.217511194
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.4027893375
Short name T1750
Test name
Test status
Simulation time 13359578008 ps
CPU time 12.37 seconds
Started Jul 10 06:47:04 PM PDT 24
Finished Jul 10 06:47:20 PM PDT 24
Peak memory 206616 kb
Host smart-bf58b94e-541b-4619-878b-5abf76ef7f4f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4027893375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.4027893375
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.4116726788
Short name T1558
Test name
Test status
Simulation time 23507843092 ps
CPU time 26.54 seconds
Started Jul 10 06:47:06 PM PDT 24
Finished Jul 10 06:47:36 PM PDT 24
Peak memory 206700 kb
Host smart-2ef1b0d0-18e5-4980-86cf-dcbbdc299f80
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4116726788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.4116726788
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1060310600
Short name T479
Test name
Test status
Simulation time 200478367 ps
CPU time 0.91 seconds
Started Jul 10 06:47:21 PM PDT 24
Finished Jul 10 06:47:24 PM PDT 24
Peak memory 206372 kb
Host smart-5b25f6a2-54c9-476b-b589-db5827abffa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10603
10600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1060310600
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.229570568
Short name T64
Test name
Test status
Simulation time 212443787 ps
CPU time 0.83 seconds
Started Jul 10 06:47:07 PM PDT 24
Finished Jul 10 06:47:12 PM PDT 24
Peak memory 206376 kb
Host smart-3e4b8713-3dc6-49cb-a06c-f429a962ab46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22957
0568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.229570568
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.285697671
Short name T114
Test name
Test status
Simulation time 444016466 ps
CPU time 1.46 seconds
Started Jul 10 06:47:15 PM PDT 24
Finished Jul 10 06:47:19 PM PDT 24
Peak memory 206408 kb
Host smart-681e8da8-381f-4704-a803-3012a62527a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28569
7671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.285697671
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.4203424471
Short name T789
Test name
Test status
Simulation time 1201902001 ps
CPU time 2.6 seconds
Started Jul 10 06:47:08 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206628 kb
Host smart-7cf3e3a5-817f-453b-8447-f2e9c80e08e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
24471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.4203424471
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1968684747
Short name T1567
Test name
Test status
Simulation time 11331273368 ps
CPU time 22.53 seconds
Started Jul 10 06:47:15 PM PDT 24
Finished Jul 10 06:47:40 PM PDT 24
Peak memory 206664 kb
Host smart-3759dede-ffc5-4233-97b6-36efb49eaaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19686
84747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1968684747
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.2285545460
Short name T87
Test name
Test status
Simulation time 460865100 ps
CPU time 1.38 seconds
Started Jul 10 06:47:08 PM PDT 24
Finished Jul 10 06:47:13 PM PDT 24
Peak memory 206372 kb
Host smart-9163c504-b911-40f8-ae76-558f00386b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22855
45460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.2285545460
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3789534430
Short name T2079
Test name
Test status
Simulation time 191205096 ps
CPU time 0.86 seconds
Started Jul 10 06:47:09 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206376 kb
Host smart-3198ad1c-1fa9-4d9a-a995-623580fc9c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37895
34430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3789534430
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.631916997
Short name T1574
Test name
Test status
Simulation time 46685340 ps
CPU time 0.69 seconds
Started Jul 10 06:47:06 PM PDT 24
Finished Jul 10 06:47:10 PM PDT 24
Peak memory 206376 kb
Host smart-0acc337d-e73c-448c-8700-3016a9708052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63191
6997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.631916997
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2724951739
Short name T2075
Test name
Test status
Simulation time 828112694 ps
CPU time 2.14 seconds
Started Jul 10 06:47:04 PM PDT 24
Finished Jul 10 06:47:10 PM PDT 24
Peak memory 206568 kb
Host smart-86ab4e98-a74e-461f-9b6f-d602add421a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27249
51739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2724951739
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1258424681
Short name T2669
Test name
Test status
Simulation time 230106995 ps
CPU time 1.69 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:08 PM PDT 24
Peak memory 206624 kb
Host smart-7e24d452-df4e-4d34-850c-5d3e6593311e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12584
24681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1258424681
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.4268559061
Short name T2610
Test name
Test status
Simulation time 191173086 ps
CPU time 0.82 seconds
Started Jul 10 06:47:09 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206360 kb
Host smart-51f7268f-5203-4f46-9540-8455c8155379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42685
59061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.4268559061
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1278551523
Short name T1239
Test name
Test status
Simulation time 146633192 ps
CPU time 0.78 seconds
Started Jul 10 06:47:09 PM PDT 24
Finished Jul 10 06:47:14 PM PDT 24
Peak memory 206260 kb
Host smart-e6794461-2730-4500-96cf-e42686731346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12785
51523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1278551523
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1636643236
Short name T1548
Test name
Test status
Simulation time 222194287 ps
CPU time 0.87 seconds
Started Jul 10 06:47:03 PM PDT 24
Finished Jul 10 06:47:08 PM PDT 24
Peak memory 206348 kb
Host smart-6641491f-a53d-4fd9-8003-056a6f491978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16366
43236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1636643236
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.3147274032
Short name T2103
Test name
Test status
Simulation time 8458267072 ps
CPU time 67.99 seconds
Started Jul 10 06:47:10 PM PDT 24
Finished Jul 10 06:48:22 PM PDT 24
Peak memory 206712 kb
Host smart-a332f5f3-931c-40b6-9ee0-653f78762872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
74032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.3147274032
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2920542074
Short name T1577
Test name
Test status
Simulation time 243561264 ps
CPU time 0.91 seconds
Started Jul 10 06:47:11 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206368 kb
Host smart-daf2bae3-3a1b-46e4-ad0f-9f20f5a2e38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29205
42074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2920542074
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1320391377
Short name T1194
Test name
Test status
Simulation time 23336414741 ps
CPU time 23.43 seconds
Started Jul 10 06:47:16 PM PDT 24
Finished Jul 10 06:47:47 PM PDT 24
Peak memory 206460 kb
Host smart-a0f087a0-2b29-49a8-90cd-fc1c14595cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13203
91377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1320391377
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2287477035
Short name T1422
Test name
Test status
Simulation time 3335241246 ps
CPU time 4.67 seconds
Started Jul 10 06:47:23 PM PDT 24
Finished Jul 10 06:47:32 PM PDT 24
Peak memory 206444 kb
Host smart-fa56fe40-ed5f-42b5-92c7-db135e1f368e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22874
77035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2287477035
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.292678175
Short name T837
Test name
Test status
Simulation time 7790817426 ps
CPU time 211.6 seconds
Started Jul 10 06:47:12 PM PDT 24
Finished Jul 10 06:50:47 PM PDT 24
Peak memory 206704 kb
Host smart-a61f4842-329f-4b64-871a-e8e14142c4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29267
8175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.292678175
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3876472842
Short name T150
Test name
Test status
Simulation time 5950713698 ps
CPU time 163.8 seconds
Started Jul 10 06:47:12 PM PDT 24
Finished Jul 10 06:49:59 PM PDT 24
Peak memory 206648 kb
Host smart-84983e31-3a21-4c15-9128-5b8103a5243a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3876472842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3876472842
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2838523115
Short name T805
Test name
Test status
Simulation time 243007281 ps
CPU time 0.93 seconds
Started Jul 10 06:47:11 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206376 kb
Host smart-59d10242-b2af-41e7-bdfb-f0e36d7c1bf6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2838523115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2838523115
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3095329869
Short name T1739
Test name
Test status
Simulation time 206679806 ps
CPU time 0.88 seconds
Started Jul 10 06:47:12 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206380 kb
Host smart-7b25bde7-3f8c-491f-908a-40f0ff92528b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30953
29869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3095329869
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2989980717
Short name T2251
Test name
Test status
Simulation time 5146095055 ps
CPU time 148.48 seconds
Started Jul 10 06:47:18 PM PDT 24
Finished Jul 10 06:49:48 PM PDT 24
Peak memory 206668 kb
Host smart-d92e4891-75d4-4ac2-b086-2ef56d915e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899
80717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2989980717
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.4124651593
Short name T2299
Test name
Test status
Simulation time 3793607251 ps
CPU time 25.68 seconds
Started Jul 10 06:47:24 PM PDT 24
Finished Jul 10 06:47:55 PM PDT 24
Peak memory 206628 kb
Host smart-712dfbfd-48af-4f7d-96c5-0fec25fc078c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4124651593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.4124651593
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.500283301
Short name T2483
Test name
Test status
Simulation time 174382764 ps
CPU time 0.8 seconds
Started Jul 10 06:47:21 PM PDT 24
Finished Jul 10 06:47:26 PM PDT 24
Peak memory 206412 kb
Host smart-f05cbd6a-28fc-475d-b63c-efa235877130
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=500283301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.500283301
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2417580668
Short name T2510
Test name
Test status
Simulation time 167881013 ps
CPU time 0.85 seconds
Started Jul 10 06:47:15 PM PDT 24
Finished Jul 10 06:47:18 PM PDT 24
Peak memory 206404 kb
Host smart-c4e73b93-adcb-47cb-83d0-665342ab15d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24175
80668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2417580668
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2678581599
Short name T902
Test name
Test status
Simulation time 165230537 ps
CPU time 0.83 seconds
Started Jul 10 06:47:12 PM PDT 24
Finished Jul 10 06:47:17 PM PDT 24
Peak memory 206372 kb
Host smart-65a81e58-64de-4753-927c-949bbdac7fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26785
81599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2678581599
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1457718909
Short name T1788
Test name
Test status
Simulation time 184841249 ps
CPU time 0.78 seconds
Started Jul 10 06:47:19 PM PDT 24
Finished Jul 10 06:47:21 PM PDT 24
Peak memory 206388 kb
Host smart-08515983-636e-4dcd-ba4b-5d2ec41b0ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14577
18909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1457718909
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2067012420
Short name T2715
Test name
Test status
Simulation time 162087398 ps
CPU time 0.76 seconds
Started Jul 10 06:47:23 PM PDT 24
Finished Jul 10 06:47:28 PM PDT 24
Peak memory 206380 kb
Host smart-b049e662-fb93-479f-9d81-8ba68b12d2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20670
12420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2067012420
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3754971458
Short name T2415
Test name
Test status
Simulation time 152151578 ps
CPU time 0.78 seconds
Started Jul 10 06:47:20 PM PDT 24
Finished Jul 10 06:47:23 PM PDT 24
Peak memory 206336 kb
Host smart-22ae75e8-c658-41b2-a046-4593b2c7d237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
71458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3754971458
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3465287999
Short name T416
Test name
Test status
Simulation time 277337699 ps
CPU time 1.08 seconds
Started Jul 10 06:47:22 PM PDT 24
Finished Jul 10 06:47:27 PM PDT 24
Peak memory 206376 kb
Host smart-dbbed30c-4a06-4804-ae69-b08a0671648c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3465287999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3465287999
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3735496434
Short name T2688
Test name
Test status
Simulation time 146714987 ps
CPU time 0.81 seconds
Started Jul 10 06:47:11 PM PDT 24
Finished Jul 10 06:47:15 PM PDT 24
Peak memory 206380 kb
Host smart-c65ec471-b435-48ea-afeb-940e26ec2378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37354
96434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3735496434
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2858804105
Short name T2101
Test name
Test status
Simulation time 27759034 ps
CPU time 0.66 seconds
Started Jul 10 06:47:11 PM PDT 24
Finished Jul 10 06:47:15 PM PDT 24
Peak memory 206388 kb
Host smart-579ec56b-0297-4933-a527-6c71e1776ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28588
04105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2858804105
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1063256549
Short name T1715
Test name
Test status
Simulation time 21018713912 ps
CPU time 50.25 seconds
Started Jul 10 06:47:23 PM PDT 24
Finished Jul 10 06:48:18 PM PDT 24
Peak memory 206700 kb
Host smart-d1db1a16-5300-4911-94cb-f8f6ddfd664f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10632
56549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1063256549
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2771364391
Short name T212
Test name
Test status
Simulation time 187350567 ps
CPU time 0.89 seconds
Started Jul 10 06:47:10 PM PDT 24
Finished Jul 10 06:47:15 PM PDT 24
Peak memory 206376 kb
Host smart-cb198adf-8bf5-4b18-aa6e-fad0737fcaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27713
64391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2771364391
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3216030380
Short name T2225
Test name
Test status
Simulation time 171488433 ps
CPU time 0.8 seconds
Started Jul 10 06:47:15 PM PDT 24
Finished Jul 10 06:47:18 PM PDT 24
Peak memory 206384 kb
Host smart-c4a3d65f-e79d-4d13-97eb-1416e438c459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32160
30380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3216030380
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3561403213
Short name T507
Test name
Test status
Simulation time 174675849 ps
CPU time 0.81 seconds
Started Jul 10 06:47:23 PM PDT 24
Finished Jul 10 06:47:28 PM PDT 24
Peak memory 206368 kb
Host smart-425967fa-77ac-47c1-b23f-4f0bd070b6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35614
03213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3561403213
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1642105348
Short name T1605
Test name
Test status
Simulation time 166005491 ps
CPU time 0.81 seconds
Started Jul 10 06:47:13 PM PDT 24
Finished Jul 10 06:47:17 PM PDT 24
Peak memory 206380 kb
Host smart-be9a7a09-79c8-4c96-b15c-4e6abe25cefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16421
05348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1642105348
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.1478689982
Short name T544
Test name
Test status
Simulation time 195858139 ps
CPU time 0.84 seconds
Started Jul 10 06:47:11 PM PDT 24
Finished Jul 10 06:47:15 PM PDT 24
Peak memory 206372 kb
Host smart-8eb98e11-0d83-4a6f-a5ee-449f8c88efb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14786
89982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1478689982
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.4195663467
Short name T1128
Test name
Test status
Simulation time 163083132 ps
CPU time 0.82 seconds
Started Jul 10 06:47:11 PM PDT 24
Finished Jul 10 06:47:15 PM PDT 24
Peak memory 206368 kb
Host smart-9da13b55-e2bc-4583-92f5-551864a627ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41956
63467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.4195663467
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2200448390
Short name T2060
Test name
Test status
Simulation time 187469466 ps
CPU time 0.81 seconds
Started Jul 10 06:47:21 PM PDT 24
Finished Jul 10 06:47:26 PM PDT 24
Peak memory 206364 kb
Host smart-e41bea6a-ff02-45d7-89c0-c0e5577f6d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22004
48390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2200448390
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.582265987
Short name T2128
Test name
Test status
Simulation time 243383779 ps
CPU time 1.03 seconds
Started Jul 10 06:47:12 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206360 kb
Host smart-22c55272-d8b3-450d-933d-b84a8647931c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58226
5987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.582265987
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1699303724
Short name T1052
Test name
Test status
Simulation time 4167575550 ps
CPU time 38.13 seconds
Started Jul 10 06:47:18 PM PDT 24
Finished Jul 10 06:47:57 PM PDT 24
Peak memory 206700 kb
Host smart-b4d05de6-ada8-4e09-8434-684483347f04
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1699303724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1699303724
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.4239834232
Short name T584
Test name
Test status
Simulation time 186676375 ps
CPU time 0.8 seconds
Started Jul 10 06:47:21 PM PDT 24
Finished Jul 10 06:47:24 PM PDT 24
Peak memory 206312 kb
Host smart-df51710a-0d13-4c36-82c5-b3130ea51165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42398
34232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.4239834232
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2610295908
Short name T1784
Test name
Test status
Simulation time 233730659 ps
CPU time 0.88 seconds
Started Jul 10 06:47:12 PM PDT 24
Finished Jul 10 06:47:16 PM PDT 24
Peak memory 206388 kb
Host smart-db96b12e-dcd3-4af9-87f0-2998a58c54b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
95908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2610295908
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1780205259
Short name T340
Test name
Test status
Simulation time 987853090 ps
CPU time 2.11 seconds
Started Jul 10 06:47:17 PM PDT 24
Finished Jul 10 06:47:21 PM PDT 24
Peak memory 206632 kb
Host smart-8a4b3d75-a77b-43f8-b075-0bfa5eebc726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17802
05259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1780205259
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.183966063
Short name T2657
Test name
Test status
Simulation time 3984501188 ps
CPU time 30.5 seconds
Started Jul 10 06:47:17 PM PDT 24
Finished Jul 10 06:47:49 PM PDT 24
Peak memory 206632 kb
Host smart-0641c736-1bde-4e0b-a8e3-fbd1040fb663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18396
6063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.183966063
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2666224635
Short name T956
Test name
Test status
Simulation time 55546632 ps
CPU time 0.73 seconds
Started Jul 10 06:40:03 PM PDT 24
Finished Jul 10 06:40:09 PM PDT 24
Peak memory 206480 kb
Host smart-e6ca51ee-08c1-4bab-a525-c767975b1834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2666224635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2666224635
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1889186636
Short name T2076
Test name
Test status
Simulation time 3998524267 ps
CPU time 5.69 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:40:03 PM PDT 24
Peak memory 206616 kb
Host smart-507032fb-ce3e-48c5-9ee6-18572dc2cc4b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1889186636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1889186636
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.4028083655
Short name T2382
Test name
Test status
Simulation time 13334249239 ps
CPU time 12.89 seconds
Started Jul 10 06:39:52 PM PDT 24
Finished Jul 10 06:40:09 PM PDT 24
Peak memory 206368 kb
Host smart-77e7e53a-40aa-4277-89a6-3ae512ea905a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4028083655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.4028083655
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1232883948
Short name T1552
Test name
Test status
Simulation time 23472178654 ps
CPU time 26.92 seconds
Started Jul 10 06:39:55 PM PDT 24
Finished Jul 10 06:40:27 PM PDT 24
Peak memory 206456 kb
Host smart-7105f777-1eab-405e-984f-ca62bddb665d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1232883948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.1232883948
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3063037951
Short name T1234
Test name
Test status
Simulation time 154018683 ps
CPU time 0.8 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:58 PM PDT 24
Peak memory 206384 kb
Host smart-ddf46caa-b568-4dd3-92d0-62b54f62aefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30630
37951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3063037951
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3067638868
Short name T2083
Test name
Test status
Simulation time 146546099 ps
CPU time 0.76 seconds
Started Jul 10 06:39:57 PM PDT 24
Finished Jul 10 06:40:03 PM PDT 24
Peak memory 206384 kb
Host smart-a295497d-fc1c-4f29-b78e-4b555e6f0aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30676
38868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3067638868
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.684474289
Short name T1620
Test name
Test status
Simulation time 394122826 ps
CPU time 1.28 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:59 PM PDT 24
Peak memory 206368 kb
Host smart-6f429760-1dc7-451a-a073-d1e4e8b03a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68447
4289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.684474289
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1661900210
Short name T811
Test name
Test status
Simulation time 1089500478 ps
CPU time 2.4 seconds
Started Jul 10 06:39:56 PM PDT 24
Finished Jul 10 06:40:03 PM PDT 24
Peak memory 206648 kb
Host smart-016d3a73-2d38-4e18-838c-1771dc86fd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16619
00210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1661900210
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.281604685
Short name T586
Test name
Test status
Simulation time 16942450645 ps
CPU time 32.73 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:40:30 PM PDT 24
Peak memory 206692 kb
Host smart-15dbef7e-9a1d-43b8-8d59-7a25e64118c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28160
4685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.281604685
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3020737979
Short name T1965
Test name
Test status
Simulation time 426012753 ps
CPU time 1.33 seconds
Started Jul 10 06:39:54 PM PDT 24
Finished Jul 10 06:40:00 PM PDT 24
Peak memory 206372 kb
Host smart-1203cca2-3b55-4ac1-a053-59c9208abcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30207
37979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3020737979
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3575368047
Short name T372
Test name
Test status
Simulation time 144699287 ps
CPU time 0.84 seconds
Started Jul 10 06:39:55 PM PDT 24
Finished Jul 10 06:40:01 PM PDT 24
Peak memory 206368 kb
Host smart-bd40ba0a-9f9d-442a-b9f8-cdc9ec86e872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
68047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3575368047
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1089038649
Short name T1061
Test name
Test status
Simulation time 50574031 ps
CPU time 0.66 seconds
Started Jul 10 06:39:53 PM PDT 24
Finished Jul 10 06:39:58 PM PDT 24
Peak memory 206364 kb
Host smart-4cd6b299-380c-4f8f-9102-87b08cda8ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10890
38649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1089038649
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.218119682
Short name T2210
Test name
Test status
Simulation time 615268274 ps
CPU time 1.7 seconds
Started Jul 10 06:39:52 PM PDT 24
Finished Jul 10 06:39:58 PM PDT 24
Peak memory 206636 kb
Host smart-dcc247e9-8c15-41e7-bbf1-109c7da4f4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21811
9682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.218119682
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3281469856
Short name T1144
Test name
Test status
Simulation time 210507570 ps
CPU time 1.41 seconds
Started Jul 10 06:39:57 PM PDT 24
Finished Jul 10 06:40:03 PM PDT 24
Peak memory 206628 kb
Host smart-3db0a2c4-6de5-4438-9b76-05ae564abb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32814
69856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3281469856
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2826051070
Short name T1426
Test name
Test status
Simulation time 230320768 ps
CPU time 0.95 seconds
Started Jul 10 06:39:55 PM PDT 24
Finished Jul 10 06:40:02 PM PDT 24
Peak memory 206396 kb
Host smart-056e15a7-feaf-442b-ba99-862816467843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28260
51070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2826051070
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.934409463
Short name T848
Test name
Test status
Simulation time 136906343 ps
CPU time 0.75 seconds
Started Jul 10 06:39:56 PM PDT 24
Finished Jul 10 06:40:02 PM PDT 24
Peak memory 206348 kb
Host smart-ab3b161c-64ab-4a63-b749-2c1bc75477cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93440
9463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.934409463
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.810102383
Short name T1394
Test name
Test status
Simulation time 209818773 ps
CPU time 0.88 seconds
Started Jul 10 06:39:57 PM PDT 24
Finished Jul 10 06:40:03 PM PDT 24
Peak memory 206376 kb
Host smart-eeccb60f-cc50-46e2-a6f9-0b3c155c16db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81010
2383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.810102383
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.334406371
Short name T61
Test name
Test status
Simulation time 166172854 ps
CPU time 0.79 seconds
Started Jul 10 06:39:59 PM PDT 24
Finished Jul 10 06:40:04 PM PDT 24
Peak memory 206360 kb
Host smart-5c0cc0bc-7104-40df-96b4-2ac32f460566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33440
6371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.334406371
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.150760569
Short name T1236
Test name
Test status
Simulation time 23371160911 ps
CPU time 24.19 seconds
Started Jul 10 06:39:57 PM PDT 24
Finished Jul 10 06:40:26 PM PDT 24
Peak memory 206460 kb
Host smart-454bff98-03e4-4ab4-beba-e3769d187b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15076
0569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.150760569
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2539454285
Short name T1894
Test name
Test status
Simulation time 3324325637 ps
CPU time 3.81 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:10 PM PDT 24
Peak memory 206464 kb
Host smart-e15fdd9e-09f9-4770-bdff-e2ff2a29bafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25394
54285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2539454285
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.27617604
Short name T688
Test name
Test status
Simulation time 10121011419 ps
CPU time 91.83 seconds
Started Jul 10 06:39:59 PM PDT 24
Finished Jul 10 06:41:35 PM PDT 24
Peak memory 206624 kb
Host smart-d14d2bd0-ab0d-42c3-bb1a-881136afad12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27617
604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.27617604
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.4201890253
Short name T2743
Test name
Test status
Simulation time 7040774441 ps
CPU time 193.57 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:43:19 PM PDT 24
Peak memory 206616 kb
Host smart-e6cfe8fb-acb9-4109-9cfe-dc851b641b7b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4201890253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.4201890253
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1886079889
Short name T1137
Test name
Test status
Simulation time 263457355 ps
CPU time 0.91 seconds
Started Jul 10 06:39:59 PM PDT 24
Finished Jul 10 06:40:05 PM PDT 24
Peak memory 206368 kb
Host smart-13f9453f-758d-4e78-b652-987e501b36b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1886079889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1886079889
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3404957084
Short name T857
Test name
Test status
Simulation time 217850588 ps
CPU time 0.94 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:40:06 PM PDT 24
Peak memory 206408 kb
Host smart-cfb99ba1-1060-4777-b6c5-1ff03d4636ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34049
57084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3404957084
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1754482422
Short name T162
Test name
Test status
Simulation time 5232617647 ps
CPU time 145.82 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:42:31 PM PDT 24
Peak memory 205936 kb
Host smart-776c093b-6378-42c2-9fcc-2c6989fab134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17544
82422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1754482422
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2957414357
Short name T2161
Test name
Test status
Simulation time 3776709397 ps
CPU time 26.17 seconds
Started Jul 10 06:39:59 PM PDT 24
Finished Jul 10 06:40:30 PM PDT 24
Peak memory 206644 kb
Host smart-7e218e01-b89a-4f08-bfac-58830afd73ab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2957414357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2957414357
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3556253841
Short name T1075
Test name
Test status
Simulation time 157406025 ps
CPU time 0.79 seconds
Started Jul 10 06:40:03 PM PDT 24
Finished Jul 10 06:40:08 PM PDT 24
Peak memory 206376 kb
Host smart-4f4fd267-3a9c-4ced-9708-141d43372613
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3556253841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3556253841
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3654403125
Short name T2419
Test name
Test status
Simulation time 144245502 ps
CPU time 0.77 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:06 PM PDT 24
Peak memory 206380 kb
Host smart-dd0e1edd-c69c-4cca-8c97-d222477e5913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
03125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3654403125
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2261348494
Short name T136
Test name
Test status
Simulation time 216056954 ps
CPU time 0.95 seconds
Started Jul 10 06:39:59 PM PDT 24
Finished Jul 10 06:40:04 PM PDT 24
Peak memory 206396 kb
Host smart-5c2935a7-7961-4844-9921-6ea8b7d746ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22613
48494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2261348494
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4040773980
Short name T414
Test name
Test status
Simulation time 169835322 ps
CPU time 0.8 seconds
Started Jul 10 06:39:58 PM PDT 24
Finished Jul 10 06:40:04 PM PDT 24
Peak memory 206380 kb
Host smart-12647320-b01b-4dfb-a7d1-f2553617337e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40407
73980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4040773980
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2287833672
Short name T242
Test name
Test status
Simulation time 206600271 ps
CPU time 0.85 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206380 kb
Host smart-8b02d7d2-1b4f-4c9a-b449-1cb0b15f9b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22878
33672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2287833672
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2102891342
Short name T1562
Test name
Test status
Simulation time 197006932 ps
CPU time 0.86 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206392 kb
Host smart-ac4ef320-d953-40a2-bcf5-2c13a1cba7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21028
91342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2102891342
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1632232073
Short name T1946
Test name
Test status
Simulation time 160196968 ps
CPU time 0.8 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:06 PM PDT 24
Peak memory 206564 kb
Host smart-cf4332b3-d1cc-4cfe-aafa-a4b001860fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16322
32073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1632232073
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.272506058
Short name T1589
Test name
Test status
Simulation time 257117977 ps
CPU time 0.95 seconds
Started Jul 10 06:39:59 PM PDT 24
Finished Jul 10 06:40:05 PM PDT 24
Peak memory 206368 kb
Host smart-0398be19-ab87-41a4-adb6-b5c90e95e102
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=272506058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.272506058
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1625113045
Short name T2460
Test name
Test status
Simulation time 154039070 ps
CPU time 0.74 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:40:05 PM PDT 24
Peak memory 206396 kb
Host smart-dba63175-99ff-48c5-a496-943d6c073cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16251
13045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1625113045
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1514336055
Short name T37
Test name
Test status
Simulation time 33110872 ps
CPU time 0.67 seconds
Started Jul 10 06:40:02 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206388 kb
Host smart-9c66269d-d67d-4ecf-8600-f6f4904b06f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15143
36055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1514336055
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1853261722
Short name T275
Test name
Test status
Simulation time 15891785662 ps
CPU time 34.18 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:40:39 PM PDT 24
Peak memory 206744 kb
Host smart-1ad090d3-bf1f-47d5-8d36-f834f386ed15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18532
61722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1853261722
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3470450595
Short name T1196
Test name
Test status
Simulation time 186998900 ps
CPU time 0.85 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:40:06 PM PDT 24
Peak memory 205704 kb
Host smart-4a932dd5-1491-4597-bac3-1f9909f3561e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
50595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3470450595
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1461679235
Short name T1444
Test name
Test status
Simulation time 205977269 ps
CPU time 0.9 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206328 kb
Host smart-49d3df23-cf72-4a08-a3a3-939787f07555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14616
79235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1461679235
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2312792848
Short name T749
Test name
Test status
Simulation time 8913155969 ps
CPU time 55.97 seconds
Started Jul 10 06:40:02 PM PDT 24
Finished Jul 10 06:41:03 PM PDT 24
Peak memory 206728 kb
Host smart-156594e7-1ad9-4dde-9ceb-fe1382bb59fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2312792848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2312792848
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.4234622231
Short name T2273
Test name
Test status
Simulation time 8535522229 ps
CPU time 40.53 seconds
Started Jul 10 06:40:04 PM PDT 24
Finished Jul 10 06:40:50 PM PDT 24
Peak memory 206648 kb
Host smart-e19d54e8-c507-46dd-b58b-fe2f415ca393
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4234622231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.4234622231
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3796170317
Short name T1931
Test name
Test status
Simulation time 238319469 ps
CPU time 0.94 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:40:05 PM PDT 24
Peak memory 206360 kb
Host smart-0e8e6e9f-3b97-485e-8c62-9396af83d50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37961
70317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3796170317
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3417058007
Short name T596
Test name
Test status
Simulation time 219247811 ps
CPU time 0.85 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:40:06 PM PDT 24
Peak memory 206388 kb
Host smart-a89b085a-32c1-43cc-b4fa-369b6fe79a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34170
58007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3417058007
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2086520342
Short name T1066
Test name
Test status
Simulation time 149853844 ps
CPU time 0.79 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206388 kb
Host smart-7c8c4d89-ca3c-4eb0-bc9c-0fdf4f9440ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20865
20342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2086520342
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1250812772
Short name T2327
Test name
Test status
Simulation time 155920125 ps
CPU time 0.77 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206304 kb
Host smart-b5346d89-fa56-467b-a433-26e2658bf81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12508
12772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1250812772
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1543626511
Short name T2172
Test name
Test status
Simulation time 154656659 ps
CPU time 0.77 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:06 PM PDT 24
Peak memory 206352 kb
Host smart-b53a4e7a-066a-41d6-8e22-8baf4ccfc2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
26511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1543626511
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1661387869
Short name T2184
Test name
Test status
Simulation time 266468125 ps
CPU time 0.98 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:07 PM PDT 24
Peak memory 206376 kb
Host smart-a9d1ca43-9006-4a4e-bdc4-65b727733e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16613
87869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1661387869
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3877451206
Short name T2402
Test name
Test status
Simulation time 3266108084 ps
CPU time 30.6 seconds
Started Jul 10 06:40:01 PM PDT 24
Finished Jul 10 06:40:37 PM PDT 24
Peak memory 206524 kb
Host smart-8717aa68-a09b-4f40-a3ba-eaa3fd9977ad
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3877451206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3877451206
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2805656279
Short name T1310
Test name
Test status
Simulation time 187575586 ps
CPU time 0.82 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:40:06 PM PDT 24
Peak memory 206384 kb
Host smart-ec8abfa5-a2d4-4eb8-ada6-479530163dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28056
56279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2805656279
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.4291383134
Short name T1515
Test name
Test status
Simulation time 177660911 ps
CPU time 0.81 seconds
Started Jul 10 06:40:03 PM PDT 24
Finished Jul 10 06:40:08 PM PDT 24
Peak memory 206376 kb
Host smart-0a23e853-99c7-4adb-a4a7-997bbbf71bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42913
83134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.4291383134
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.847460132
Short name T721
Test name
Test status
Simulation time 563939508 ps
CPU time 1.44 seconds
Started Jul 10 06:40:04 PM PDT 24
Finished Jul 10 06:40:10 PM PDT 24
Peak memory 206372 kb
Host smart-77f707ed-532c-40b4-9d4b-854c123595c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84746
0132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.847460132
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2117692113
Short name T2028
Test name
Test status
Simulation time 5833433560 ps
CPU time 55.9 seconds
Started Jul 10 06:40:00 PM PDT 24
Finished Jul 10 06:41:01 PM PDT 24
Peak memory 206616 kb
Host smart-596d23e7-6a69-4732-9a75-2d5204892eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21176
92113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2117692113
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.711424549
Short name T1460
Test name
Test status
Simulation time 38617678 ps
CPU time 0.66 seconds
Started Jul 10 06:40:18 PM PDT 24
Finished Jul 10 06:40:23 PM PDT 24
Peak memory 206424 kb
Host smart-87a8a9a7-050f-4c5e-b5ed-c514fee60fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=711424549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.711424549
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1446994270
Short name T876
Test name
Test status
Simulation time 4220935695 ps
CPU time 5.32 seconds
Started Jul 10 06:40:05 PM PDT 24
Finished Jul 10 06:40:14 PM PDT 24
Peak memory 206404 kb
Host smart-96b1f2af-8efc-4eb5-addb-0a1cc824958a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1446994270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1446994270
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.430441058
Short name T1955
Test name
Test status
Simulation time 13455281274 ps
CPU time 13.45 seconds
Started Jul 10 06:40:04 PM PDT 24
Finished Jul 10 06:40:22 PM PDT 24
Peak memory 206600 kb
Host smart-4e788dee-6203-41ce-8430-7f40b8764fef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=430441058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.430441058
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.160154085
Short name T1665
Test name
Test status
Simulation time 23361833792 ps
CPU time 23.99 seconds
Started Jul 10 06:40:05 PM PDT 24
Finished Jul 10 06:40:33 PM PDT 24
Peak memory 206600 kb
Host smart-f6100d58-6683-41a4-a469-8241ca2504af
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=160154085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.160154085
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2107142111
Short name T2046
Test name
Test status
Simulation time 179633462 ps
CPU time 0.87 seconds
Started Jul 10 06:40:05 PM PDT 24
Finished Jul 10 06:40:10 PM PDT 24
Peak memory 206368 kb
Host smart-865363c5-6a89-4c3d-8351-04668c0add66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21071
42111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2107142111
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.256095520
Short name T2276
Test name
Test status
Simulation time 238974085 ps
CPU time 0.87 seconds
Started Jul 10 06:40:06 PM PDT 24
Finished Jul 10 06:40:11 PM PDT 24
Peak memory 206376 kb
Host smart-10c5284b-efc2-4c14-a10e-51fdc779d237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25609
5520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.256095520
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.231095272
Short name T2109
Test name
Test status
Simulation time 422866341 ps
CPU time 1.28 seconds
Started Jul 10 06:40:06 PM PDT 24
Finished Jul 10 06:40:11 PM PDT 24
Peak memory 206400 kb
Host smart-77c49351-255f-4821-8dd4-3e1407849c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23109
5272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.231095272
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1558147971
Short name T973
Test name
Test status
Simulation time 454458002 ps
CPU time 1.3 seconds
Started Jul 10 06:40:09 PM PDT 24
Finished Jul 10 06:40:13 PM PDT 24
Peak memory 206372 kb
Host smart-0186de69-cf22-4299-901c-b2e07654b562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15581
47971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1558147971
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3581503583
Short name T1621
Test name
Test status
Simulation time 22484147056 ps
CPU time 45.65 seconds
Started Jul 10 06:40:09 PM PDT 24
Finished Jul 10 06:40:58 PM PDT 24
Peak memory 206672 kb
Host smart-c72a92e9-8ed1-460c-9d87-1ea303b65756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35815
03583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3581503583
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.2423762291
Short name T782
Test name
Test status
Simulation time 146669536 ps
CPU time 0.79 seconds
Started Jul 10 06:40:07 PM PDT 24
Finished Jul 10 06:40:12 PM PDT 24
Peak memory 206392 kb
Host smart-83f0fadc-0df0-4316-a54c-a72d804e1034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24237
62291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.2423762291
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.4219920644
Short name T2307
Test name
Test status
Simulation time 422851975 ps
CPU time 1.31 seconds
Started Jul 10 06:40:08 PM PDT 24
Finished Jul 10 06:40:13 PM PDT 24
Peak memory 206384 kb
Host smart-86008e46-2de1-40db-a948-b50be33fc478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42199
20644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.4219920644
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2675300379
Short name T1638
Test name
Test status
Simulation time 170283903 ps
CPU time 0.75 seconds
Started Jul 10 06:40:07 PM PDT 24
Finished Jul 10 06:40:12 PM PDT 24
Peak memory 206560 kb
Host smart-fd681b5c-dd47-4108-8ec2-b1cfc43e2714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26753
00379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2675300379
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1613708101
Short name T873
Test name
Test status
Simulation time 33349923 ps
CPU time 0.64 seconds
Started Jul 10 06:40:08 PM PDT 24
Finished Jul 10 06:40:12 PM PDT 24
Peak memory 206352 kb
Host smart-96085fbf-8051-493a-9e0e-8e95b3c76d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16137
08101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1613708101
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2412641106
Short name T2426
Test name
Test status
Simulation time 929024589 ps
CPU time 2.37 seconds
Started Jul 10 06:40:07 PM PDT 24
Finished Jul 10 06:40:13 PM PDT 24
Peak memory 206664 kb
Host smart-66237a0d-39ec-4bfd-b1ab-5eef497b0ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24126
41106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2412641106
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1648306457
Short name T1209
Test name
Test status
Simulation time 201034490 ps
CPU time 2.16 seconds
Started Jul 10 06:40:17 PM PDT 24
Finished Jul 10 06:40:23 PM PDT 24
Peak memory 206640 kb
Host smart-2944d0f6-48bd-42a6-a6fd-094b54ad2a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16483
06457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1648306457
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.562478985
Short name T618
Test name
Test status
Simulation time 180696485 ps
CPU time 0.83 seconds
Started Jul 10 06:40:07 PM PDT 24
Finished Jul 10 06:40:11 PM PDT 24
Peak memory 206304 kb
Host smart-617ebf78-7a73-4768-8ea5-d0eaf1c94275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56247
8985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.562478985
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.593062249
Short name T1257
Test name
Test status
Simulation time 181627136 ps
CPU time 0.89 seconds
Started Jul 10 06:40:08 PM PDT 24
Finished Jul 10 06:40:12 PM PDT 24
Peak memory 206356 kb
Host smart-45c842e1-c06a-4cde-9aec-9036c283d70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59306
2249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.593062249
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2742251624
Short name T1819
Test name
Test status
Simulation time 187535963 ps
CPU time 0.87 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:40:22 PM PDT 24
Peak memory 206392 kb
Host smart-d9a3dcfd-ad57-464c-be82-dc19e8048e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
51624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2742251624
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.556626893
Short name T2107
Test name
Test status
Simulation time 10856893984 ps
CPU time 88.07 seconds
Started Jul 10 06:40:08 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206692 kb
Host smart-9946cbe4-77dd-4e5e-9aaa-05be7ca2e5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55662
6893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.556626893
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.881442677
Short name T1971
Test name
Test status
Simulation time 227327928 ps
CPU time 0.92 seconds
Started Jul 10 06:40:06 PM PDT 24
Finished Jul 10 06:40:11 PM PDT 24
Peak memory 206368 kb
Host smart-a4c279e6-5dbc-496a-a6dd-cf8bb229f834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88144
2677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.881442677
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.3270708374
Short name T1023
Test name
Test status
Simulation time 23307439790 ps
CPU time 23.04 seconds
Started Jul 10 06:40:07 PM PDT 24
Finished Jul 10 06:40:34 PM PDT 24
Peak memory 206436 kb
Host smart-35e249c2-f4a1-4084-bc51-9dc63672af44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32707
08374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.3270708374
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1645459979
Short name T2255
Test name
Test status
Simulation time 3335088077 ps
CPU time 3.84 seconds
Started Jul 10 06:40:07 PM PDT 24
Finished Jul 10 06:40:15 PM PDT 24
Peak memory 206456 kb
Host smart-e118d492-e25a-4e3a-a2ba-5d5b667da366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16454
59979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1645459979
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2717704940
Short name T2531
Test name
Test status
Simulation time 8120829104 ps
CPU time 231.91 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:44:12 PM PDT 24
Peak memory 206712 kb
Host smart-44419a26-caeb-4973-9410-de201fca6d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27177
04940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2717704940
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.694642177
Short name T2496
Test name
Test status
Simulation time 3512243123 ps
CPU time 96.82 seconds
Started Jul 10 06:40:08 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206700 kb
Host smart-d504b557-6d35-4c2a-ae24-63fe544e9bf3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=694642177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.694642177
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2521305054
Short name T790
Test name
Test status
Simulation time 246596088 ps
CPU time 0.96 seconds
Started Jul 10 06:40:17 PM PDT 24
Finished Jul 10 06:40:22 PM PDT 24
Peak memory 206388 kb
Host smart-db2e325f-48b3-4bbd-8981-cdc371ba98bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2521305054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2521305054
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1751714472
Short name T961
Test name
Test status
Simulation time 201125551 ps
CPU time 0.93 seconds
Started Jul 10 06:40:09 PM PDT 24
Finished Jul 10 06:40:13 PM PDT 24
Peak memory 206384 kb
Host smart-233a261d-aa9e-47ff-9a46-883830d05076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17517
14472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1751714472
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2922202365
Short name T1031
Test name
Test status
Simulation time 4475318813 ps
CPU time 42.87 seconds
Started Jul 10 06:40:08 PM PDT 24
Finished Jul 10 06:40:55 PM PDT 24
Peak memory 206644 kb
Host smart-26a32665-74d4-4df4-ba5b-a72269e3ce5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29222
02365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2922202365
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3893362092
Short name T356
Test name
Test status
Simulation time 5576636882 ps
CPU time 39.06 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206732 kb
Host smart-a297dc38-431e-4a49-85c3-ac37c06ff429
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3893362092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3893362092
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.274198927
Short name T722
Test name
Test status
Simulation time 173427898 ps
CPU time 0.87 seconds
Started Jul 10 06:40:10 PM PDT 24
Finished Jul 10 06:40:13 PM PDT 24
Peak memory 206364 kb
Host smart-216d63c4-8a95-479d-aebf-f2ffde688c26
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=274198927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.274198927
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1811882937
Short name T2638
Test name
Test status
Simulation time 141183710 ps
CPU time 0.78 seconds
Started Jul 10 06:40:08 PM PDT 24
Finished Jul 10 06:40:12 PM PDT 24
Peak memory 206376 kb
Host smart-7bf00371-5b96-436b-b80a-ac391bbf6a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18118
82937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1811882937
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3890590659
Short name T148
Test name
Test status
Simulation time 242089056 ps
CPU time 0.92 seconds
Started Jul 10 06:40:18 PM PDT 24
Finished Jul 10 06:40:23 PM PDT 24
Peak memory 206400 kb
Host smart-b7c9e9b9-d6e8-4055-9cde-0b9ea423d769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38905
90659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3890590659
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.4232005897
Short name T1180
Test name
Test status
Simulation time 170474134 ps
CPU time 0.87 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:18 PM PDT 24
Peak memory 206380 kb
Host smart-1bc2c5d3-c9bb-4d04-b421-8662e91c7523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
05897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.4232005897
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2651942921
Short name T959
Test name
Test status
Simulation time 150734448 ps
CPU time 0.77 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:18 PM PDT 24
Peak memory 206400 kb
Host smart-1cb6d4b9-61ac-4ee9-88da-257b2ecad452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26519
42921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2651942921
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4222720466
Short name T1117
Test name
Test status
Simulation time 176106623 ps
CPU time 0.83 seconds
Started Jul 10 06:40:17 PM PDT 24
Finished Jul 10 06:40:22 PM PDT 24
Peak memory 206380 kb
Host smart-96a73fba-b58b-48ad-aff2-bf824dda8392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42227
20466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4222720466
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2243169232
Short name T579
Test name
Test status
Simulation time 156746816 ps
CPU time 0.86 seconds
Started Jul 10 06:40:19 PM PDT 24
Finished Jul 10 06:40:24 PM PDT 24
Peak memory 206364 kb
Host smart-94cf8d37-e48e-40d6-bcd1-02874b092135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22431
69232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2243169232
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.2502679242
Short name T1253
Test name
Test status
Simulation time 236559400 ps
CPU time 0.91 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:40:21 PM PDT 24
Peak memory 206392 kb
Host smart-7e110c1b-65ee-42fc-98aa-350b65702182
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2502679242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.2502679242
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1072380283
Short name T2118
Test name
Test status
Simulation time 148541461 ps
CPU time 0.81 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:19 PM PDT 24
Peak memory 206376 kb
Host smart-8694395d-2021-4b21-8508-621040fa3341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10723
80283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1072380283
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.498383276
Short name T2738
Test name
Test status
Simulation time 37924567 ps
CPU time 0.67 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:18 PM PDT 24
Peak memory 206368 kb
Host smart-aaf6b004-c320-4ba2-b2c0-4b69a0836d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49838
3276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.498383276
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.74863602
Short name T1726
Test name
Test status
Simulation time 16424329872 ps
CPU time 38.46 seconds
Started Jul 10 06:40:14 PM PDT 24
Finished Jul 10 06:40:54 PM PDT 24
Peak memory 206736 kb
Host smart-9e0a941b-a627-43ca-9ead-bb3be7bb7d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74863
602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.74863602
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1319636042
Short name T870
Test name
Test status
Simulation time 151428967 ps
CPU time 0.79 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:19 PM PDT 24
Peak memory 206304 kb
Host smart-04c79b33-3643-4963-ad48-5187389982a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13196
36042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1319636042
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.878577050
Short name T457
Test name
Test status
Simulation time 210782859 ps
CPU time 0.9 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:40:21 PM PDT 24
Peak memory 206364 kb
Host smart-3a1ac53d-6841-4a72-8b2a-dd071ed7c42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87857
7050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.878577050
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2197684839
Short name T165
Test name
Test status
Simulation time 12229112311 ps
CPU time 81.85 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:41:40 PM PDT 24
Peak memory 206668 kb
Host smart-3d0fcf67-e3b5-4092-90dc-bb9552c7bbb9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2197684839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2197684839
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3881048784
Short name T2089
Test name
Test status
Simulation time 6205239768 ps
CPU time 153.66 seconds
Started Jul 10 06:40:17 PM PDT 24
Finished Jul 10 06:42:55 PM PDT 24
Peak memory 206740 kb
Host smart-52f95f6f-760a-4981-9566-9b6747264eb6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3881048784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3881048784
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.4105588251
Short name T2013
Test name
Test status
Simulation time 10245315143 ps
CPU time 188.89 seconds
Started Jul 10 06:40:14 PM PDT 24
Finished Jul 10 06:43:25 PM PDT 24
Peak memory 206672 kb
Host smart-53baafb1-aee5-4086-80db-81894aa67ae4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4105588251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.4105588251
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2915849231
Short name T598
Test name
Test status
Simulation time 186251568 ps
CPU time 0.86 seconds
Started Jul 10 06:40:14 PM PDT 24
Finished Jul 10 06:40:17 PM PDT 24
Peak memory 206384 kb
Host smart-466834a5-86f2-4ae4-9c51-87ceb3c84cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29158
49231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2915849231
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.777346697
Short name T674
Test name
Test status
Simulation time 198332633 ps
CPU time 0.85 seconds
Started Jul 10 06:40:20 PM PDT 24
Finished Jul 10 06:40:24 PM PDT 24
Peak memory 206368 kb
Host smart-19a88900-8c71-412a-a011-499bc5e1efcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77734
6697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.777346697
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.900727350
Short name T1885
Test name
Test status
Simulation time 209021967 ps
CPU time 0.91 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:40:21 PM PDT 24
Peak memory 206384 kb
Host smart-8bc7e248-f3ad-477a-a266-797cca4c71cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90072
7350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.900727350
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.963656978
Short name T1747
Test name
Test status
Simulation time 183869769 ps
CPU time 0.86 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:18 PM PDT 24
Peak memory 206392 kb
Host smart-03b7d98b-dbe3-487d-8174-b403cd5f0b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96365
6978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.963656978
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.601704462
Short name T2745
Test name
Test status
Simulation time 194071865 ps
CPU time 0.82 seconds
Started Jul 10 06:40:14 PM PDT 24
Finished Jul 10 06:40:16 PM PDT 24
Peak memory 206376 kb
Host smart-e7192fbf-1fe2-4ccf-8527-dcc798c26cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60170
4462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.601704462
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1353749880
Short name T158
Test name
Test status
Simulation time 215948015 ps
CPU time 0.95 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:40:21 PM PDT 24
Peak memory 206376 kb
Host smart-8dc417d6-a825-4723-88cf-5a907941d49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537
49880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1353749880
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.717573301
Short name T963
Test name
Test status
Simulation time 4818676977 ps
CPU time 45.75 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:41:06 PM PDT 24
Peak memory 206640 kb
Host smart-16b06ea7-40f8-403d-ab36-e455ff83ea3f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=717573301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.717573301
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2504513845
Short name T2372
Test name
Test status
Simulation time 227691625 ps
CPU time 0.82 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:19 PM PDT 24
Peak memory 206384 kb
Host smart-f9b0573e-3df7-49bf-b572-1041fc0d9e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25045
13845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2504513845
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1243800026
Short name T1166
Test name
Test status
Simulation time 179663319 ps
CPU time 0.84 seconds
Started Jul 10 06:40:14 PM PDT 24
Finished Jul 10 06:40:17 PM PDT 24
Peak memory 206396 kb
Host smart-9675469e-256b-4b2a-918f-cfc16471d762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
00026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1243800026
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.761309391
Short name T2056
Test name
Test status
Simulation time 1405516847 ps
CPU time 2.89 seconds
Started Jul 10 06:40:18 PM PDT 24
Finished Jul 10 06:40:25 PM PDT 24
Peak memory 206620 kb
Host smart-db52f0ef-7427-4a1e-aa09-b8631a3201c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76130
9391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.761309391
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3564279940
Short name T1407
Test name
Test status
Simulation time 3919774608 ps
CPU time 104.89 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:42:06 PM PDT 24
Peak memory 206612 kb
Host smart-a2b8fdbe-fc2a-46b0-acb6-6cb7d39c3a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35642
79940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3564279940
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.989879782
Short name T2482
Test name
Test status
Simulation time 37335023 ps
CPU time 0.69 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:40:43 PM PDT 24
Peak memory 206428 kb
Host smart-0f5d55c6-1677-442b-8246-7ebc18067310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=989879782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.989879782
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1587971953
Short name T738
Test name
Test status
Simulation time 4059764806 ps
CPU time 4.6 seconds
Started Jul 10 06:40:14 PM PDT 24
Finished Jul 10 06:40:19 PM PDT 24
Peak memory 206688 kb
Host smart-f8e8fc8d-72e2-4a48-a71e-7723d1e935ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1587971953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1587971953
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1211980839
Short name T895
Test name
Test status
Simulation time 13303454160 ps
CPU time 11.97 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:40:32 PM PDT 24
Peak memory 206596 kb
Host smart-aa7a18b8-74c6-483f-8721-b50205f8a6aa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1211980839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1211980839
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2749173286
Short name T16
Test name
Test status
Simulation time 23348717313 ps
CPU time 24.75 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206484 kb
Host smart-41035372-4a28-4cd5-a715-e919881e6e8b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2749173286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2749173286
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.590840812
Short name T1670
Test name
Test status
Simulation time 200030313 ps
CPU time 0.89 seconds
Started Jul 10 06:40:17 PM PDT 24
Finished Jul 10 06:40:22 PM PDT 24
Peak memory 206372 kb
Host smart-2b75d1af-53b3-4eb5-bf0d-c97306e414d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59084
0812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.590840812
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2024738436
Short name T1730
Test name
Test status
Simulation time 178959352 ps
CPU time 0.83 seconds
Started Jul 10 06:40:19 PM PDT 24
Finished Jul 10 06:40:24 PM PDT 24
Peak memory 206372 kb
Host smart-4ef4593a-2d94-4460-bafe-7009a244f0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
38436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2024738436
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.439382729
Short name T904
Test name
Test status
Simulation time 310718069 ps
CPU time 1.08 seconds
Started Jul 10 06:40:14 PM PDT 24
Finished Jul 10 06:40:17 PM PDT 24
Peak memory 206384 kb
Host smart-cad14f3a-2213-41ac-aee8-4950eb0fafaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43938
2729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.439382729
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1658791079
Short name T396
Test name
Test status
Simulation time 931471668 ps
CPU time 2.01 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:20 PM PDT 24
Peak memory 206572 kb
Host smart-0d1d3257-56b8-4c7c-8b78-a26c801196f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16587
91079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1658791079
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.867941523
Short name T758
Test name
Test status
Simulation time 7388602895 ps
CPU time 15.42 seconds
Started Jul 10 06:40:15 PM PDT 24
Finished Jul 10 06:40:34 PM PDT 24
Peak memory 206696 kb
Host smart-97f2bd81-9bcb-41a9-878f-d6fe6d1ef26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86794
1523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.867941523
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2756397361
Short name T2621
Test name
Test status
Simulation time 462842957 ps
CPU time 1.44 seconds
Started Jul 10 06:40:18 PM PDT 24
Finished Jul 10 06:40:24 PM PDT 24
Peak memory 206400 kb
Host smart-7e7bf975-ec35-4f72-a8cf-84a819191b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
97361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2756397361
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1915091150
Short name T45
Test name
Test status
Simulation time 139160067 ps
CPU time 0.75 seconds
Started Jul 10 06:40:16 PM PDT 24
Finished Jul 10 06:40:20 PM PDT 24
Peak memory 206360 kb
Host smart-52b6ebe9-5c00-4af0-8222-7090e80f45e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19150
91150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1915091150
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1771221754
Short name T2339
Test name
Test status
Simulation time 124682398 ps
CPU time 0.73 seconds
Started Jul 10 06:40:22 PM PDT 24
Finished Jul 10 06:40:26 PM PDT 24
Peak memory 206376 kb
Host smart-97fd53b0-01ab-4078-b5ff-a05a152ef92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17712
21754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1771221754
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2681112051
Short name T1937
Test name
Test status
Simulation time 986620410 ps
CPU time 2.07 seconds
Started Jul 10 06:40:23 PM PDT 24
Finished Jul 10 06:40:28 PM PDT 24
Peak memory 206660 kb
Host smart-d8ce807a-ba87-4c86-b106-9dc7a9c2185e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26811
12051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2681112051
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1361329042
Short name T1268
Test name
Test status
Simulation time 296908003 ps
CPU time 2.31 seconds
Started Jul 10 06:40:21 PM PDT 24
Finished Jul 10 06:40:27 PM PDT 24
Peak memory 206644 kb
Host smart-760ff793-3538-4131-8538-41556d8d125c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13613
29042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1361329042
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.526237524
Short name T822
Test name
Test status
Simulation time 182605330 ps
CPU time 0.85 seconds
Started Jul 10 06:40:24 PM PDT 24
Finished Jul 10 06:40:27 PM PDT 24
Peak memory 206352 kb
Host smart-84210e9c-f6a2-4ea4-91eb-1bec111e22b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52623
7524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.526237524
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3977860615
Short name T1859
Test name
Test status
Simulation time 144541042 ps
CPU time 0.77 seconds
Started Jul 10 06:40:26 PM PDT 24
Finished Jul 10 06:40:28 PM PDT 24
Peak memory 206388 kb
Host smart-6e3470c1-d88f-4161-b2dc-658b29905c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39778
60615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3977860615
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2062281238
Short name T426
Test name
Test status
Simulation time 233957730 ps
CPU time 0.91 seconds
Started Jul 10 06:40:23 PM PDT 24
Finished Jul 10 06:40:27 PM PDT 24
Peak memory 206388 kb
Host smart-c625155e-1235-44cd-973c-827ffe464926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
81238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2062281238
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.370081197
Short name T2171
Test name
Test status
Simulation time 5006640690 ps
CPU time 45.12 seconds
Started Jul 10 06:40:21 PM PDT 24
Finished Jul 10 06:41:09 PM PDT 24
Peak memory 206584 kb
Host smart-d43936c8-e462-4a6c-ba3c-fc2d27059e75
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=370081197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.370081197
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.2427977477
Short name T2538
Test name
Test status
Simulation time 5174561107 ps
CPU time 15.86 seconds
Started Jul 10 06:40:25 PM PDT 24
Finished Jul 10 06:40:43 PM PDT 24
Peak memory 206636 kb
Host smart-026ac567-d17a-4875-8d2e-eaea3792dcd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279
77477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2427977477
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1219663115
Short name T1734
Test name
Test status
Simulation time 232357684 ps
CPU time 0.93 seconds
Started Jul 10 06:40:24 PM PDT 24
Finished Jul 10 06:40:27 PM PDT 24
Peak memory 206348 kb
Host smart-9b21fe58-dd94-4b87-8672-0f3126aa07ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12196
63115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1219663115
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2403781335
Short name T1631
Test name
Test status
Simulation time 23262736716 ps
CPU time 23.46 seconds
Started Jul 10 06:40:23 PM PDT 24
Finished Jul 10 06:40:50 PM PDT 24
Peak memory 206436 kb
Host smart-9c586fcb-471a-49bc-b770-bd591198b898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24037
81335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2403781335
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1433329466
Short name T2412
Test name
Test status
Simulation time 3301056671 ps
CPU time 4.52 seconds
Started Jul 10 06:40:22 PM PDT 24
Finished Jul 10 06:40:30 PM PDT 24
Peak memory 206444 kb
Host smart-7952e409-ab89-4dea-99ff-c84a9d5d9671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14333
29466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1433329466
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3250427167
Short name T2623
Test name
Test status
Simulation time 11571596759 ps
CPU time 107.89 seconds
Started Jul 10 06:40:21 PM PDT 24
Finished Jul 10 06:42:12 PM PDT 24
Peak memory 206696 kb
Host smart-bd63c526-7cfb-4b91-9244-5d640c3f0507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32504
27167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3250427167
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.553631395
Short name T1494
Test name
Test status
Simulation time 4570954914 ps
CPU time 41.37 seconds
Started Jul 10 06:40:22 PM PDT 24
Finished Jul 10 06:41:06 PM PDT 24
Peak memory 206692 kb
Host smart-a628706f-1632-47e1-96c5-64deb9bf2d85
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=553631395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.553631395
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.845628599
Short name T1327
Test name
Test status
Simulation time 238183597 ps
CPU time 0.92 seconds
Started Jul 10 06:40:22 PM PDT 24
Finished Jul 10 06:40:26 PM PDT 24
Peak memory 206392 kb
Host smart-81eb6f96-26b3-4204-9f00-c727a2c74f07
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=845628599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.845628599
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1123437397
Short name T1235
Test name
Test status
Simulation time 184247627 ps
CPU time 0.86 seconds
Started Jul 10 06:40:22 PM PDT 24
Finished Jul 10 06:40:25 PM PDT 24
Peak memory 206384 kb
Host smart-b6cb1c79-4ef3-41cc-b215-9e0b2a03773e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11234
37397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1123437397
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.882705488
Short name T2428
Test name
Test status
Simulation time 3532971807 ps
CPU time 26.12 seconds
Started Jul 10 06:40:22 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206600 kb
Host smart-8e64b7d7-7713-4866-8058-944689eac291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88270
5488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.882705488
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2541847527
Short name T2331
Test name
Test status
Simulation time 5648076915 ps
CPU time 162.83 seconds
Started Jul 10 06:40:21 PM PDT 24
Finished Jul 10 06:43:07 PM PDT 24
Peak memory 206692 kb
Host smart-76b23c67-f7de-4aee-acee-f920b87fa2c7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2541847527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2541847527
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.4248958176
Short name T2181
Test name
Test status
Simulation time 155565837 ps
CPU time 0.78 seconds
Started Jul 10 06:40:30 PM PDT 24
Finished Jul 10 06:40:37 PM PDT 24
Peak memory 206404 kb
Host smart-a2d50966-c9d6-4de2-8657-7f3fa22b21a9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4248958176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.4248958176
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3702549800
Short name T2258
Test name
Test status
Simulation time 137948847 ps
CPU time 0.77 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:40:43 PM PDT 24
Peak memory 206396 kb
Host smart-09e357ad-bf2c-4633-90f1-f99aead045ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37025
49800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3702549800
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2203600554
Short name T1880
Test name
Test status
Simulation time 251683168 ps
CPU time 0.87 seconds
Started Jul 10 06:40:30 PM PDT 24
Finished Jul 10 06:40:36 PM PDT 24
Peak memory 206388 kb
Host smart-a0fc540b-dd9d-4b3d-9e9c-1dd209898477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22036
00554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2203600554
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.4294323737
Short name T1177
Test name
Test status
Simulation time 188275559 ps
CPU time 0.81 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206392 kb
Host smart-d4de1176-0d99-4a02-a668-ff11e3256bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42943
23737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.4294323737
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1273017907
Short name T1813
Test name
Test status
Simulation time 199446848 ps
CPU time 0.86 seconds
Started Jul 10 06:40:28 PM PDT 24
Finished Jul 10 06:40:30 PM PDT 24
Peak memory 206400 kb
Host smart-e9bc8ba0-234b-4da7-8077-8fb367fbad0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12730
17907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1273017907
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.853970935
Short name T1051
Test name
Test status
Simulation time 173528933 ps
CPU time 0.8 seconds
Started Jul 10 06:40:30 PM PDT 24
Finished Jul 10 06:40:36 PM PDT 24
Peak memory 206376 kb
Host smart-cd123dd3-481b-488b-a7a1-8ab170be89e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85397
0935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.853970935
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.177245570
Short name T2413
Test name
Test status
Simulation time 145050799 ps
CPU time 0.79 seconds
Started Jul 10 06:40:30 PM PDT 24
Finished Jul 10 06:40:36 PM PDT 24
Peak memory 206368 kb
Host smart-89ed594e-b7bc-4c56-a51a-42dd7a857cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17724
5570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.177245570
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1740313689
Short name T1944
Test name
Test status
Simulation time 196437838 ps
CPU time 0.96 seconds
Started Jul 10 06:40:30 PM PDT 24
Finished Jul 10 06:40:37 PM PDT 24
Peak memory 206408 kb
Host smart-1bc789b3-d7ea-45fb-aa2c-e2ce191df982
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1740313689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1740313689
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1964948057
Short name T737
Test name
Test status
Simulation time 140027541 ps
CPU time 0.79 seconds
Started Jul 10 06:40:29 PM PDT 24
Finished Jul 10 06:40:34 PM PDT 24
Peak memory 206384 kb
Host smart-d9731a62-9f37-455e-8c89-cc6e6a3ab06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19649
48057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1964948057
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.874084694
Short name T2672
Test name
Test status
Simulation time 61461034 ps
CPU time 0.65 seconds
Started Jul 10 06:40:36 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206384 kb
Host smart-bff178df-16a5-405f-98e4-f1dbfd64c879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87408
4694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.874084694
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1013256465
Short name T2044
Test name
Test status
Simulation time 5879874429 ps
CPU time 13.63 seconds
Started Jul 10 06:40:34 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206728 kb
Host smart-f4dfd545-f8b0-4da7-a08b-d1c6e163de8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10132
56465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1013256465
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1283203211
Short name T2718
Test name
Test status
Simulation time 169774936 ps
CPU time 0.82 seconds
Started Jul 10 06:40:30 PM PDT 24
Finished Jul 10 06:40:36 PM PDT 24
Peak memory 206384 kb
Host smart-9cdc4237-9c92-4559-b6a5-ef878ead0060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
03211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1283203211
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2734555850
Short name T623
Test name
Test status
Simulation time 241998821 ps
CPU time 0.9 seconds
Started Jul 10 06:40:36 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206392 kb
Host smart-37890847-92a6-4e51-8a72-ae3e251039e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27345
55850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2734555850
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.30212771
Short name T1769
Test name
Test status
Simulation time 9532996567 ps
CPU time 79.68 seconds
Started Jul 10 06:40:28 PM PDT 24
Finished Jul 10 06:41:48 PM PDT 24
Peak memory 206660 kb
Host smart-92e6a02f-e767-4f39-8a23-4f1c3c1ccf0d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=30212771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.30212771
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2554722169
Short name T2342
Test name
Test status
Simulation time 19503652602 ps
CPU time 146.42 seconds
Started Jul 10 06:40:36 PM PDT 24
Finished Jul 10 06:43:08 PM PDT 24
Peak memory 206668 kb
Host smart-cd1cacb9-840b-4304-9612-5b3f7183cbfd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2554722169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2554722169
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2098115840
Short name T524
Test name
Test status
Simulation time 12867072020 ps
CPU time 65.64 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 206700 kb
Host smart-1e006afa-03f6-4d4f-9bda-4c2b324ff1d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2098115840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2098115840
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.4176975738
Short name T1891
Test name
Test status
Simulation time 232561514 ps
CPU time 0.89 seconds
Started Jul 10 06:40:33 PM PDT 24
Finished Jul 10 06:40:39 PM PDT 24
Peak memory 206392 kb
Host smart-aeee572e-541d-4f98-9eb5-12232330e86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41769
75738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.4176975738
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.434863147
Short name T1152
Test name
Test status
Simulation time 175287718 ps
CPU time 0.83 seconds
Started Jul 10 06:40:29 PM PDT 24
Finished Jul 10 06:40:32 PM PDT 24
Peak memory 206560 kb
Host smart-b0a93c81-9115-464a-b323-55dabf872475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43486
3147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.434863147
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2467454755
Short name T2062
Test name
Test status
Simulation time 241762201 ps
CPU time 0.88 seconds
Started Jul 10 06:40:30 PM PDT 24
Finished Jul 10 06:40:37 PM PDT 24
Peak memory 206396 kb
Host smart-d98795f8-19cc-49be-9607-e97f1ffd67c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24674
54755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2467454755
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1531012514
Short name T1291
Test name
Test status
Simulation time 153725944 ps
CPU time 0.82 seconds
Started Jul 10 06:40:30 PM PDT 24
Finished Jul 10 06:40:36 PM PDT 24
Peak memory 206352 kb
Host smart-ad4672d6-1c63-4f13-9371-cca778565596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15310
12514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1531012514
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.643582594
Short name T1791
Test name
Test status
Simulation time 209423282 ps
CPU time 0.91 seconds
Started Jul 10 06:40:29 PM PDT 24
Finished Jul 10 06:40:32 PM PDT 24
Peak memory 206376 kb
Host smart-9b66b084-b133-473e-87d0-8848e1359ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64358
2594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.643582594
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.4072356514
Short name T2570
Test name
Test status
Simulation time 274751640 ps
CPU time 1.02 seconds
Started Jul 10 06:40:31 PM PDT 24
Finished Jul 10 06:40:38 PM PDT 24
Peak memory 206376 kb
Host smart-1e163319-f218-4fa9-8527-fa049a97229b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40723
56514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.4072356514
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1508465507
Short name T2323
Test name
Test status
Simulation time 4446622957 ps
CPU time 120.4 seconds
Started Jul 10 06:40:33 PM PDT 24
Finished Jul 10 06:42:39 PM PDT 24
Peak memory 206688 kb
Host smart-df527654-8c63-428e-a845-c68510e35e4b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1508465507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1508465507
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.119362574
Short name T990
Test name
Test status
Simulation time 170110490 ps
CPU time 0.85 seconds
Started Jul 10 06:40:29 PM PDT 24
Finished Jul 10 06:40:35 PM PDT 24
Peak memory 206376 kb
Host smart-3dd95681-5c8f-4c77-b806-fa64882b969a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
2574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.119362574
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1615458824
Short name T991
Test name
Test status
Simulation time 159666205 ps
CPU time 0.82 seconds
Started Jul 10 06:40:34 PM PDT 24
Finished Jul 10 06:40:40 PM PDT 24
Peak memory 206376 kb
Host smart-5f5bb9cd-60d7-4ab2-8979-51868ba24d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16154
58824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1615458824
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2907448183
Short name T1602
Test name
Test status
Simulation time 499598403 ps
CPU time 1.34 seconds
Started Jul 10 06:40:31 PM PDT 24
Finished Jul 10 06:40:38 PM PDT 24
Peak memory 206396 kb
Host smart-905db6c3-37a9-417d-b096-242712478d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29074
48183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2907448183
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3001599864
Short name T2233
Test name
Test status
Simulation time 4520156498 ps
CPU time 33.97 seconds
Started Jul 10 06:40:31 PM PDT 24
Finished Jul 10 06:41:10 PM PDT 24
Peak memory 206636 kb
Host smart-d84dce5b-f318-4392-a3ad-844f985c99fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30015
99864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3001599864
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.468347969
Short name T1848
Test name
Test status
Simulation time 43734551 ps
CPU time 0.71 seconds
Started Jul 10 06:40:44 PM PDT 24
Finished Jul 10 06:40:49 PM PDT 24
Peak memory 206424 kb
Host smart-c1811c29-5b69-4db2-aec6-5a5975fc9b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=468347969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.468347969
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.505473631
Short name T2102
Test name
Test status
Simulation time 3719340113 ps
CPU time 5.38 seconds
Started Jul 10 06:40:33 PM PDT 24
Finished Jul 10 06:40:44 PM PDT 24
Peak memory 206420 kb
Host smart-2343decf-26eb-4241-8e5a-c8150a5df441
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=505473631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.505473631
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1760986721
Short name T1959
Test name
Test status
Simulation time 13382880606 ps
CPU time 12.54 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:40:55 PM PDT 24
Peak memory 206420 kb
Host smart-9615c412-98fe-417a-a5e8-d9887bd028fe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1760986721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1760986721
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2724106015
Short name T2475
Test name
Test status
Simulation time 23473261283 ps
CPU time 30.41 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:41:14 PM PDT 24
Peak memory 206448 kb
Host smart-08bfeb47-383b-4f37-b904-760cc198d4b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2724106015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2724106015
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.424874923
Short name T684
Test name
Test status
Simulation time 154367585 ps
CPU time 0.8 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:40:43 PM PDT 24
Peak memory 206380 kb
Host smart-fc9b8da8-9304-4e37-9241-8a901bf6d43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
4923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.424874923
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3147204744
Short name T2136
Test name
Test status
Simulation time 145110774 ps
CPU time 0.78 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:40:44 PM PDT 24
Peak memory 206384 kb
Host smart-53edbf2a-6649-4a32-878a-6922375c6432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
04744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3147204744
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.1462336600
Short name T1150
Test name
Test status
Simulation time 460101084 ps
CPU time 1.41 seconds
Started Jul 10 06:40:36 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206360 kb
Host smart-b1a2e185-963a-4eca-85ee-4ffc99862c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
36600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.1462336600
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.260543426
Short name T1657
Test name
Test status
Simulation time 796324559 ps
CPU time 1.88 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:40:44 PM PDT 24
Peak memory 206612 kb
Host smart-5bc72d6a-457a-4f6f-a1f3-a01278cf63f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26054
3426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.260543426
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2774138830
Short name T1898
Test name
Test status
Simulation time 12228154599 ps
CPU time 22.38 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:41:05 PM PDT 24
Peak memory 206672 kb
Host smart-e2ab9a0f-b183-4d5d-bf48-61a83dab34e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741
38830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2774138830
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3100985193
Short name T2654
Test name
Test status
Simulation time 443578058 ps
CPU time 1.34 seconds
Started Jul 10 06:40:36 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206384 kb
Host smart-ce59fd4c-8122-4de2-81db-97210bc96eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31009
85193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3100985193
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.177686018
Short name T860
Test name
Test status
Simulation time 159599407 ps
CPU time 0.77 seconds
Started Jul 10 06:40:41 PM PDT 24
Finished Jul 10 06:40:46 PM PDT 24
Peak memory 206352 kb
Host smart-71da057e-7de0-42a6-aeb6-c86e29505765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17768
6018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.177686018
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2236450256
Short name T2338
Test name
Test status
Simulation time 45307158 ps
CPU time 0.67 seconds
Started Jul 10 06:40:39 PM PDT 24
Finished Jul 10 06:40:45 PM PDT 24
Peak memory 206356 kb
Host smart-a9851bf9-c218-4c7e-a03d-81932d170b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22364
50256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2236450256
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.2487286828
Short name T1222
Test name
Test status
Simulation time 1047070675 ps
CPU time 2.62 seconds
Started Jul 10 06:40:41 PM PDT 24
Finished Jul 10 06:40:48 PM PDT 24
Peak memory 206608 kb
Host smart-b75f87fc-e9c0-4104-83c6-6f4ff3658daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24872
86828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2487286828
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.564617758
Short name T2177
Test name
Test status
Simulation time 332603565 ps
CPU time 2.12 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:40:45 PM PDT 24
Peak memory 206624 kb
Host smart-8aa549f7-097c-4e77-9107-5cea7fd1d7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56461
7758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.564617758
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.807546277
Short name T2150
Test name
Test status
Simulation time 194347065 ps
CPU time 0.9 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206352 kb
Host smart-477c27a4-296d-422e-a582-0e365de8fb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80754
6277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.807546277
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1595350932
Short name T1613
Test name
Test status
Simulation time 141973927 ps
CPU time 0.8 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:40:44 PM PDT 24
Peak memory 206380 kb
Host smart-9c1fa1fd-dd6f-4d42-9776-d1ca8dd2638f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15953
50932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1595350932
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3603355730
Short name T1854
Test name
Test status
Simulation time 231014249 ps
CPU time 0.86 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:40:43 PM PDT 24
Peak memory 206380 kb
Host smart-0ef2daef-3d15-42e7-a6b6-d1c3e07c4061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36033
55730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3603355730
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.4214448917
Short name T1647
Test name
Test status
Simulation time 11252986206 ps
CPU time 88.26 seconds
Started Jul 10 06:40:39 PM PDT 24
Finished Jul 10 06:42:12 PM PDT 24
Peak memory 206684 kb
Host smart-8afdcfef-f509-4ca1-99a1-a3ddb141c7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42144
48917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.4214448917
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3604251000
Short name T2121
Test name
Test status
Simulation time 186469376 ps
CPU time 0.93 seconds
Started Jul 10 06:40:40 PM PDT 24
Finished Jul 10 06:40:46 PM PDT 24
Peak memory 206392 kb
Host smart-9ce7136a-c5ab-4bb1-9e87-c6599a6d6eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36042
51000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3604251000
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3713680871
Short name T319
Test name
Test status
Simulation time 23306698632 ps
CPU time 24.71 seconds
Started Jul 10 06:40:42 PM PDT 24
Finished Jul 10 06:41:11 PM PDT 24
Peak memory 206412 kb
Host smart-9e3df945-8c3e-4ef6-92ba-839a74e52518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37136
80871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3713680871
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2496889851
Short name T666
Test name
Test status
Simulation time 3278144165 ps
CPU time 3.66 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:40:47 PM PDT 24
Peak memory 206464 kb
Host smart-5c2ef613-b2c1-4a70-8f3a-164c4516fcc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24968
89851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2496889851
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3456652742
Short name T2229
Test name
Test status
Simulation time 10508744547 ps
CPU time 285.88 seconds
Started Jul 10 06:40:39 PM PDT 24
Finished Jul 10 06:45:30 PM PDT 24
Peak memory 206716 kb
Host smart-5addec52-d3ef-4de0-84eb-7e2afbaf9382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34566
52742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3456652742
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2573560168
Short name T2303
Test name
Test status
Simulation time 4950517876 ps
CPU time 50.34 seconds
Started Jul 10 06:40:35 PM PDT 24
Finished Jul 10 06:41:30 PM PDT 24
Peak memory 206640 kb
Host smart-322b11b4-ff84-4c1f-9739-a2ad2cdee3df
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2573560168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2573560168
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3889249172
Short name T326
Test name
Test status
Simulation time 238929949 ps
CPU time 0.98 seconds
Started Jul 10 06:40:39 PM PDT 24
Finished Jul 10 06:40:45 PM PDT 24
Peak memory 206372 kb
Host smart-cc6745f7-db5f-4977-8650-23ab7e339b80
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3889249172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3889249172
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2260024984
Short name T1942
Test name
Test status
Simulation time 229812136 ps
CPU time 0.88 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:40:44 PM PDT 24
Peak memory 206396 kb
Host smart-41d34adc-d05d-4cdc-a12e-b2589715be24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22600
24984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2260024984
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3870986620
Short name T42
Test name
Test status
Simulation time 5746009776 ps
CPU time 56.22 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:41:39 PM PDT 24
Peak memory 206660 kb
Host smart-f067bd3b-6d8a-4fcc-973c-5ef75e4bff54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
86620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3870986620
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.4294728402
Short name T1449
Test name
Test status
Simulation time 4704547524 ps
CPU time 124.7 seconds
Started Jul 10 06:40:38 PM PDT 24
Finished Jul 10 06:42:48 PM PDT 24
Peak memory 206576 kb
Host smart-6553f7bb-aa9c-4c54-b133-90e8de10e512
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4294728402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.4294728402
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3403505154
Short name T1019
Test name
Test status
Simulation time 177299919 ps
CPU time 0.82 seconds
Started Jul 10 06:40:36 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206388 kb
Host smart-39017d12-d553-45f9-b75e-24fb9b28b64f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3403505154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3403505154
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.603101367
Short name T273
Test name
Test status
Simulation time 174915137 ps
CPU time 0.86 seconds
Started Jul 10 06:40:37 PM PDT 24
Finished Jul 10 06:40:43 PM PDT 24
Peak memory 206384 kb
Host smart-8a868d77-c6b1-42b3-9b6d-841cf9720771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60310
1367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.603101367
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.223462401
Short name T132
Test name
Test status
Simulation time 241930000 ps
CPU time 0.98 seconds
Started Jul 10 06:40:36 PM PDT 24
Finished Jul 10 06:40:42 PM PDT 24
Peak memory 206392 kb
Host smart-262efa37-ac22-4799-a6ad-e3c212c9df2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22346
2401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.223462401
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1842787554
Short name T2695
Test name
Test status
Simulation time 154800755 ps
CPU time 0.79 seconds
Started Jul 10 06:40:39 PM PDT 24
Finished Jul 10 06:40:45 PM PDT 24
Peak memory 206364 kb
Host smart-90d55ace-21c9-45f7-92a8-09ea99eaf20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
87554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1842787554
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1230550294
Short name T373
Test name
Test status
Simulation time 181935493 ps
CPU time 0.81 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206372 kb
Host smart-3dafddae-5a87-46f0-91f4-d2793acce198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12305
50294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1230550294
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.291954284
Short name T1403
Test name
Test status
Simulation time 213161546 ps
CPU time 0.85 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:50 PM PDT 24
Peak memory 206384 kb
Host smart-52b135bd-d0c3-433c-8c01-062ff69c7f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29195
4284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.291954284
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2852928884
Short name T460
Test name
Test status
Simulation time 174509693 ps
CPU time 0.81 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206384 kb
Host smart-f59b5f01-5ed0-4e19-946a-289ffb4c930c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28529
28884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2852928884
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2194526236
Short name T2423
Test name
Test status
Simulation time 210768486 ps
CPU time 0.89 seconds
Started Jul 10 06:40:44 PM PDT 24
Finished Jul 10 06:40:49 PM PDT 24
Peak memory 206380 kb
Host smart-62e4b5c8-c55c-4230-8c7f-1f398fed1853
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2194526236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2194526236
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2789042726
Short name T32
Test name
Test status
Simulation time 147711412 ps
CPU time 0.77 seconds
Started Jul 10 06:40:43 PM PDT 24
Finished Jul 10 06:40:48 PM PDT 24
Peak memory 206380 kb
Host smart-e4699d34-fc6a-436d-8cc2-ce295ea55d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27890
42726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2789042726
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1156157677
Short name T34
Test name
Test status
Simulation time 51460876 ps
CPU time 0.7 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:49 PM PDT 24
Peak memory 206392 kb
Host smart-f38b2212-1247-4e9b-bebb-9f5531799ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11561
57677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1156157677
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.4258915669
Short name T274
Test name
Test status
Simulation time 17885336571 ps
CPU time 37.86 seconds
Started Jul 10 06:40:44 PM PDT 24
Finished Jul 10 06:41:26 PM PDT 24
Peak memory 206688 kb
Host smart-d273ca33-ad71-420c-a101-3290b20e267f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42589
15669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.4258915669
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3994385223
Short name T2549
Test name
Test status
Simulation time 155359829 ps
CPU time 0.83 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:51 PM PDT 24
Peak memory 206308 kb
Host smart-c494a114-760c-46d2-bf4d-be2e046646ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39943
85223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3994385223
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2318602003
Short name T1425
Test name
Test status
Simulation time 207591933 ps
CPU time 0.84 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206400 kb
Host smart-ff3bd5ec-f227-4b3a-b34b-69de7fccfff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
02003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2318602003
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1765965916
Short name T1283
Test name
Test status
Simulation time 17016835216 ps
CPU time 135.21 seconds
Started Jul 10 06:40:48 PM PDT 24
Finished Jul 10 06:43:08 PM PDT 24
Peak memory 206636 kb
Host smart-5f628562-fda2-4322-9f46-69f45c09c519
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1765965916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1765965916
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3274451460
Short name T797
Test name
Test status
Simulation time 12659570746 ps
CPU time 242.82 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:44:53 PM PDT 24
Peak memory 206668 kb
Host smart-50c25aa4-2267-42cb-b54e-30608e70e5ad
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3274451460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3274451460
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1128935906
Short name T1122
Test name
Test status
Simulation time 235778776 ps
CPU time 0.92 seconds
Started Jul 10 06:40:44 PM PDT 24
Finished Jul 10 06:40:49 PM PDT 24
Peak memory 206384 kb
Host smart-18f6e8ba-2534-4518-bee4-d07be6c234bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11289
35906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1128935906
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1048052004
Short name T1903
Test name
Test status
Simulation time 230370757 ps
CPU time 0.95 seconds
Started Jul 10 06:40:43 PM PDT 24
Finished Jul 10 06:40:48 PM PDT 24
Peak memory 206380 kb
Host smart-526f1cf1-7037-4e65-827d-e2efb7a7d1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10480
52004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1048052004
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3930276053
Short name T1041
Test name
Test status
Simulation time 137566643 ps
CPU time 0.76 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206396 kb
Host smart-30723369-a5fa-4c93-9d7d-722c18a774d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39302
76053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3930276053
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2406465951
Short name T2193
Test name
Test status
Simulation time 153235348 ps
CPU time 0.75 seconds
Started Jul 10 06:40:47 PM PDT 24
Finished Jul 10 06:40:53 PM PDT 24
Peak memory 206372 kb
Host smart-33757ba6-f4a9-4599-bc6a-724031d3d394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064
65951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2406465951
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2135935622
Short name T1396
Test name
Test status
Simulation time 156210530 ps
CPU time 0.86 seconds
Started Jul 10 06:40:47 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206356 kb
Host smart-3a22ab12-04a0-49bb-8b16-8775bb70b09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21359
35622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2135935622
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.952616977
Short name T344
Test name
Test status
Simulation time 251544523 ps
CPU time 0.99 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206372 kb
Host smart-c775345d-0bb6-41f6-82b5-21c53bfd7bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95261
6977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.952616977
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3684061804
Short name T2041
Test name
Test status
Simulation time 5800242970 ps
CPU time 55.04 seconds
Started Jul 10 06:40:43 PM PDT 24
Finished Jul 10 06:41:42 PM PDT 24
Peak memory 206708 kb
Host smart-f6524d19-8262-4a7d-a19b-feb30e5e3cf1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3684061804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3684061804
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.494332229
Short name T2629
Test name
Test status
Simulation time 185845306 ps
CPU time 0.8 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206388 kb
Host smart-bf7a4173-3477-4acf-b84f-34e53e3b076f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49433
2229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.494332229
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2716582391
Short name T1105
Test name
Test status
Simulation time 172118626 ps
CPU time 0.76 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:50 PM PDT 24
Peak memory 206304 kb
Host smart-35a3efcd-9391-4ebd-aca2-9f3a0cf80ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27165
82391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2716582391
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3768398766
Short name T2232
Test name
Test status
Simulation time 194633719 ps
CPU time 0.88 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:51 PM PDT 24
Peak memory 206392 kb
Host smart-30ed033f-fa09-4a47-9de9-5fb70376a4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37683
98766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3768398766
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.545577234
Short name T2400
Test name
Test status
Simulation time 5383306746 ps
CPU time 151.94 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:43:22 PM PDT 24
Peak memory 206636 kb
Host smart-966b366f-fae1-4b6b-99cd-75c15cfdcc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54557
7234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.545577234
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.573829415
Short name T2501
Test name
Test status
Simulation time 36555820 ps
CPU time 0.69 seconds
Started Jul 10 06:40:54 PM PDT 24
Finished Jul 10 06:41:00 PM PDT 24
Peak memory 206428 kb
Host smart-5aab242f-3b4b-4c30-91a3-ab851248ed49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=573829415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.573829415
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3485229768
Short name T2530
Test name
Test status
Simulation time 3814642289 ps
CPU time 4.73 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:54 PM PDT 24
Peak memory 206672 kb
Host smart-eb0ab800-e085-4aa6-852f-f61a1e817fd8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3485229768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.3485229768
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.717129457
Short name T843
Test name
Test status
Simulation time 13323208670 ps
CPU time 13.79 seconds
Started Jul 10 06:40:49 PM PDT 24
Finished Jul 10 06:41:08 PM PDT 24
Peak memory 206612 kb
Host smart-3527c098-fed8-44b6-b454-56f7cf74fa7a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=717129457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.717129457
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.4203791590
Short name T1318
Test name
Test status
Simulation time 23374792210 ps
CPU time 24.97 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:41:16 PM PDT 24
Peak memory 206460 kb
Host smart-15aa9718-3c44-44d0-a77a-d858bd1f9ae5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4203791590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.4203791590
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.346724658
Short name T415
Test name
Test status
Simulation time 225319604 ps
CPU time 0.9 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206400 kb
Host smart-9f9ca361-271f-416e-972a-558411ada160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34672
4658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.346724658
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1856545377
Short name T1973
Test name
Test status
Simulation time 153660256 ps
CPU time 0.76 seconds
Started Jul 10 06:40:44 PM PDT 24
Finished Jul 10 06:40:48 PM PDT 24
Peak memory 206380 kb
Host smart-16fd9739-1d94-4f95-8196-4e1f871b97b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
45377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1856545377
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.1961569483
Short name T2154
Test name
Test status
Simulation time 208014407 ps
CPU time 0.94 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206360 kb
Host smart-304f9903-7883-4d90-9c67-aec5107aa3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
69483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.1961569483
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.307288072
Short name T1773
Test name
Test status
Simulation time 400179855 ps
CPU time 1.14 seconds
Started Jul 10 06:40:50 PM PDT 24
Finished Jul 10 06:40:57 PM PDT 24
Peak memory 206352 kb
Host smart-cfeb6bcb-af07-4c2d-bf14-fb76d7c7d463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30728
8072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.307288072
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3391461486
Short name T1021
Test name
Test status
Simulation time 17696656403 ps
CPU time 31.18 seconds
Started Jul 10 06:40:48 PM PDT 24
Finished Jul 10 06:41:24 PM PDT 24
Peak memory 206692 kb
Host smart-f713c87c-16dc-4db4-ab1d-efef5dffee00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33914
61486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3391461486
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1190791120
Short name T1904
Test name
Test status
Simulation time 371401716 ps
CPU time 1.18 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206368 kb
Host smart-614b1781-c191-413c-9245-103cf6ea34a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11907
91120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1190791120
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.664403891
Short name T2378
Test name
Test status
Simulation time 135119731 ps
CPU time 0.72 seconds
Started Jul 10 06:40:51 PM PDT 24
Finished Jul 10 06:40:56 PM PDT 24
Peak memory 206348 kb
Host smart-1aee5106-d00b-4fd7-8f97-cf1f27f087b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66440
3891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.664403891
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1016021952
Short name T476
Test name
Test status
Simulation time 78844859 ps
CPU time 0.69 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:50 PM PDT 24
Peak memory 206352 kb
Host smart-9f0c4ba6-da13-4b35-8e1d-a5c9b97c5cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10160
21952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1016021952
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3901802597
Short name T710
Test name
Test status
Simulation time 675580177 ps
CPU time 1.84 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206624 kb
Host smart-ebef1d31-6934-4902-981d-8cee8d5febbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39018
02597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3901802597
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.624321699
Short name T1119
Test name
Test status
Simulation time 203444042 ps
CPU time 0.84 seconds
Started Jul 10 06:40:47 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206348 kb
Host smart-bb033e59-32fa-4ec9-a983-9ed7cdd3dc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62432
1699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.624321699
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2029951086
Short name T1072
Test name
Test status
Simulation time 145962255 ps
CPU time 0.76 seconds
Started Jul 10 06:40:47 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206364 kb
Host smart-ac48b4fe-f8aa-447e-be23-acce48cf9778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20299
51086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2029951086
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2141067902
Short name T359
Test name
Test status
Simulation time 154898432 ps
CPU time 0.8 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:51 PM PDT 24
Peak memory 206376 kb
Host smart-84982323-5c59-4ade-8abc-f3fb3707b491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21410
67902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2141067902
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.284503896
Short name T219
Test name
Test status
Simulation time 7261517053 ps
CPU time 68.61 seconds
Started Jul 10 06:40:47 PM PDT 24
Finished Jul 10 06:42:00 PM PDT 24
Peak memory 206592 kb
Host smart-ebc5a728-0f5a-4d1b-8a1b-4342d9a742c9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=284503896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.284503896
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.581504800
Short name T2031
Test name
Test status
Simulation time 5453182669 ps
CPU time 16.83 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:41:06 PM PDT 24
Peak memory 206652 kb
Host smart-6b010825-72fb-48ac-b257-e176b6415309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58150
4800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.581504800
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2765555687
Short name T691
Test name
Test status
Simulation time 231390827 ps
CPU time 0.87 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 206308 kb
Host smart-810397a8-9101-41c3-926a-b1723649525d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27655
55687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2765555687
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3969474288
Short name T1655
Test name
Test status
Simulation time 23335245792 ps
CPU time 26.26 seconds
Started Jul 10 06:40:46 PM PDT 24
Finished Jul 10 06:41:17 PM PDT 24
Peak memory 206368 kb
Host smart-7ed5aed9-92cf-4060-b2a8-9b2b73a3bd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39694
74288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3969474288
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3883491744
Short name T1928
Test name
Test status
Simulation time 3305982598 ps
CPU time 3.92 seconds
Started Jul 10 06:40:54 PM PDT 24
Finished Jul 10 06:41:03 PM PDT 24
Peak memory 206468 kb
Host smart-0c5675fb-c627-4089-918a-285dcbcddc06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38834
91744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3883491744
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2651424097
Short name T2536
Test name
Test status
Simulation time 8677727978 ps
CPU time 237.6 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:44:47 PM PDT 24
Peak memory 206656 kb
Host smart-68e4c034-ae54-45d0-b767-2f969109af80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26514
24097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2651424097
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.2367701885
Short name T1996
Test name
Test status
Simulation time 5112105415 ps
CPU time 149.1 seconds
Started Jul 10 06:40:54 PM PDT 24
Finished Jul 10 06:43:28 PM PDT 24
Peak memory 206680 kb
Host smart-ee8bd3f5-98c9-4d58-98e8-a236b78a90a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2367701885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.2367701885
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.201848836
Short name T1261
Test name
Test status
Simulation time 279461210 ps
CPU time 0.97 seconds
Started Jul 10 06:40:45 PM PDT 24
Finished Jul 10 06:40:50 PM PDT 24
Peak memory 206372 kb
Host smart-34c56a91-f0e2-44e7-99d8-544729c15af3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=201848836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.201848836
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.434555769
Short name T2194
Test name
Test status
Simulation time 201403416 ps
CPU time 0.91 seconds
Started Jul 10 06:40:55 PM PDT 24
Finished Jul 10 06:41:01 PM PDT 24
Peak memory 206564 kb
Host smart-ac00f994-bf8e-489f-95e8-695b6ff43893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43455
5769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.434555769
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.45810674
Short name T2326
Test name
Test status
Simulation time 5968575644 ps
CPU time 40.93 seconds
Started Jul 10 06:40:55 PM PDT 24
Finished Jul 10 06:41:41 PM PDT 24
Peak memory 206700 kb
Host smart-8fcb143f-7d44-416d-8822-fc55b188b336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45810
674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.45810674
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.4059957519
Short name T555
Test name
Test status
Simulation time 3851581500 ps
CPU time 29.46 seconds
Started Jul 10 06:40:56 PM PDT 24
Finished Jul 10 06:41:31 PM PDT 24
Peak memory 206604 kb
Host smart-ce1b0ea9-6c8c-4d90-baf8-6e2dd5334cc9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4059957519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.4059957519
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.579365741
Short name T604
Test name
Test status
Simulation time 181570735 ps
CPU time 0.86 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:58 PM PDT 24
Peak memory 206396 kb
Host smart-286123b0-c390-43a7-aecb-11da5ef24faf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=579365741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.579365741
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3462774044
Short name T1273
Test name
Test status
Simulation time 151635850 ps
CPU time 0.76 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206400 kb
Host smart-4b069210-037b-4574-844b-32dc56cc9a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34627
74044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3462774044
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1685471944
Short name T134
Test name
Test status
Simulation time 221038472 ps
CPU time 0.92 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206376 kb
Host smart-6a234885-6ece-4250-8c76-30a2af8c02d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16854
71944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1685471944
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2555959395
Short name T549
Test name
Test status
Simulation time 161244651 ps
CPU time 0.8 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:58 PM PDT 24
Peak memory 206380 kb
Host smart-d98328cd-0b37-4c72-9096-7625ff65d761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25559
59395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2555959395
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1291729923
Short name T1618
Test name
Test status
Simulation time 175372581 ps
CPU time 0.79 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206348 kb
Host smart-4c85f449-3c20-4e60-9941-078e8ffca6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12917
29923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1291729923
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2672680644
Short name T1263
Test name
Test status
Simulation time 206737266 ps
CPU time 0.94 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206392 kb
Host smart-3b86e276-abd7-4b61-908e-842b33fb4db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26726
80644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2672680644
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1634221219
Short name T1686
Test name
Test status
Simulation time 155492443 ps
CPU time 0.84 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206384 kb
Host smart-d1ee695b-0fec-416d-988b-a6c23db66894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16342
21219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1634221219
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.285838600
Short name T51
Test name
Test status
Simulation time 186228668 ps
CPU time 0.85 seconds
Started Jul 10 06:40:55 PM PDT 24
Finished Jul 10 06:41:00 PM PDT 24
Peak memory 206360 kb
Host smart-f431cb86-6633-4e04-b82a-8d34879270e0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=285838600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.285838600
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2760299369
Short name T2542
Test name
Test status
Simulation time 162046953 ps
CPU time 0.78 seconds
Started Jul 10 06:40:52 PM PDT 24
Finished Jul 10 06:40:58 PM PDT 24
Peak memory 206392 kb
Host smart-87519049-5065-420e-a0e1-24576655f45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602
99369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2760299369
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3793040702
Short name T934
Test name
Test status
Simulation time 39152507 ps
CPU time 0.69 seconds
Started Jul 10 06:40:54 PM PDT 24
Finished Jul 10 06:41:00 PM PDT 24
Peak memory 206352 kb
Host smart-3c6b3803-c2fc-47bd-ab9f-4d4781379813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37930
40702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3793040702
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3827595408
Short name T2357
Test name
Test status
Simulation time 15748868370 ps
CPU time 37.04 seconds
Started Jul 10 06:40:55 PM PDT 24
Finished Jul 10 06:41:37 PM PDT 24
Peak memory 206644 kb
Host smart-2d2d5755-0c1e-4fc1-944a-0cd97e7191f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38275
95408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3827595408
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2042910263
Short name T906
Test name
Test status
Simulation time 181935559 ps
CPU time 0.84 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:58 PM PDT 24
Peak memory 206396 kb
Host smart-8be38010-d047-4c9b-b7ae-3ce4951395dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20429
10263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2042910263
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3984106607
Short name T2302
Test name
Test status
Simulation time 241316458 ps
CPU time 0.95 seconds
Started Jul 10 06:40:52 PM PDT 24
Finished Jul 10 06:40:58 PM PDT 24
Peak memory 206380 kb
Host smart-43196111-792a-44af-a044-3d9087916c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39841
06607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3984106607
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1771532874
Short name T188
Test name
Test status
Simulation time 11019785192 ps
CPU time 93.01 seconds
Started Jul 10 06:40:54 PM PDT 24
Finished Jul 10 06:42:32 PM PDT 24
Peak memory 206684 kb
Host smart-0d0daf93-788c-4b90-9fe9-bc8b7e23aadf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1771532874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1771532874
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3347427649
Short name T168
Test name
Test status
Simulation time 9267091959 ps
CPU time 56.37 seconds
Started Jul 10 06:40:55 PM PDT 24
Finished Jul 10 06:41:56 PM PDT 24
Peak memory 206688 kb
Host smart-90d726c3-8eed-43d0-8e0b-9a66f4a9d921
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3347427649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3347427649
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.4204071008
Short name T2213
Test name
Test status
Simulation time 7741727229 ps
CPU time 128.13 seconds
Started Jul 10 06:40:55 PM PDT 24
Finished Jul 10 06:43:08 PM PDT 24
Peak memory 206848 kb
Host smart-86c87dcf-bddc-48da-a2f1-fd8abee6d2c6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4204071008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.4204071008
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3570563204
Short name T417
Test name
Test status
Simulation time 176018308 ps
CPU time 0.83 seconds
Started Jul 10 06:40:58 PM PDT 24
Finished Jul 10 06:41:04 PM PDT 24
Peak memory 206280 kb
Host smart-80489fc0-0eb0-4cdc-ae0b-a63177f0a18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35705
63204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3570563204
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2282744715
Short name T832
Test name
Test status
Simulation time 156804611 ps
CPU time 0.79 seconds
Started Jul 10 06:40:53 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206332 kb
Host smart-84dbdf1b-6eb3-43df-86f3-4b95edd8e0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22827
44715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2282744715
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2221432084
Short name T1134
Test name
Test status
Simulation time 154638989 ps
CPU time 0.86 seconds
Started Jul 10 06:40:56 PM PDT 24
Finished Jul 10 06:41:02 PM PDT 24
Peak memory 206392 kb
Host smart-747e03c4-d65c-4df4-b254-3e2de8ca86ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22214
32084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2221432084
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.4103163431
Short name T980
Test name
Test status
Simulation time 159861277 ps
CPU time 0.8 seconds
Started Jul 10 06:40:54 PM PDT 24
Finished Jul 10 06:41:00 PM PDT 24
Peak memory 206388 kb
Host smart-76342095-c96d-4e3e-903e-a2b89db8d0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41031
63431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.4103163431
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2041667811
Short name T465
Test name
Test status
Simulation time 144765856 ps
CPU time 0.77 seconds
Started Jul 10 06:40:51 PM PDT 24
Finished Jul 10 06:40:57 PM PDT 24
Peak memory 206352 kb
Host smart-eaa284bb-6cda-4b7c-af83-186ad03c7c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20416
67811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2041667811
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.4022160477
Short name T679
Test name
Test status
Simulation time 224289472 ps
CPU time 0.89 seconds
Started Jul 10 06:40:52 PM PDT 24
Finished Jul 10 06:40:58 PM PDT 24
Peak memory 206368 kb
Host smart-24a4da09-7bc7-4ff2-b52b-4214b34ac48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40221
60477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.4022160477
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1428159870
Short name T1155
Test name
Test status
Simulation time 5622989745 ps
CPU time 52.14 seconds
Started Jul 10 06:40:52 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 206844 kb
Host smart-1973e085-eae0-4e2c-8138-f8b449fcb942
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1428159870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1428159870
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3714331406
Short name T2594
Test name
Test status
Simulation time 187002528 ps
CPU time 0.84 seconds
Started Jul 10 06:40:55 PM PDT 24
Finished Jul 10 06:41:00 PM PDT 24
Peak memory 206368 kb
Host smart-f5c9cc2f-175e-4fe7-b7be-f7840f18f8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37143
31406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3714331406
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1025368498
Short name T1906
Test name
Test status
Simulation time 178061279 ps
CPU time 0.84 seconds
Started Jul 10 06:40:54 PM PDT 24
Finished Jul 10 06:40:59 PM PDT 24
Peak memory 206388 kb
Host smart-e162fa19-f23d-41b9-bd49-9f71da5b41e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10253
68498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1025368498
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3116579463
Short name T989
Test name
Test status
Simulation time 1077189231 ps
CPU time 2.48 seconds
Started Jul 10 06:40:54 PM PDT 24
Finished Jul 10 06:41:02 PM PDT 24
Peak memory 206608 kb
Host smart-12325bd9-a7f1-4179-bccb-82a484b066c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
79463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3116579463
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.4028035302
Short name T505
Test name
Test status
Simulation time 6488495023 ps
CPU time 49.65 seconds
Started Jul 10 06:40:52 PM PDT 24
Finished Jul 10 06:41:46 PM PDT 24
Peak memory 206624 kb
Host smart-87b18fd6-f194-41c7-a521-aefee04f513c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
35302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.4028035302
Directory /workspace/9.usbdev_streaming_out/latest
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