Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	86659	1		T1	2		T2	4		T3	2
all_values[1]	86659	1		T1	2		T2	4		T3	2
all_values[2]	86659	1		T1	2		T2	4		T3	2
all_values[3]	86659	1		T1	2		T2	4		T3	2
all_values[4]	86659	1		T1	2		T2	4		T3	2
all_values[5]	86659	1		T1	2		T2	4		T3	2
all_values[6]	86659	1		T1	2		T2	4		T3	2
all_values[7]	86659	1		T1	2		T2	4		T3	2
all_values[8]	86659	1		T1	2		T2	4		T3	2
all_values[9]	86659	1		T1	2		T2	4		T3	2
all_values[10]	86659	1		T1	2		T2	4		T3	2
all_values[11]	86659	1		T1	2		T2	4		T3	2
all_values[12]	86659	1		T1	2		T2	4		T3	2
all_values[13]	86659	1		T1	2		T2	4		T3	2
all_values[14]	86659	1		T1	2		T2	4		T3	2
all_values[15]	86659	1		T1	2		T2	4		T3	2
all_values[16]	86659	1		T1	2		T2	4		T3	2
all_values[17]	86659	1		T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1553044	1		T1	36		T2	72		T3	36
auto[1]	6818	1		T35	3		T33	2		T53	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1554901	1		T1	36		T2	72		T3	36
auto[1]	4961	1		T216	132		T217	116		T218	132

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85683	1		T1	2		T2	4		T3	2
all_values[0]	auto[0]	auto[1]	151	1		T216	5		T217	4		T218	2
all_values[0]	auto[1]	auto[0]	696	1		T35	3		T51	3		T17	3
all_values[0]	auto[1]	auto[1]	129	1		T216	2		T217	4		T218	6
all_values[1]	auto[0]	auto[0]	84862	1		T1	2		T2	4		T3	2
all_values[1]	auto[0]	auto[1]	150	1		T216	3		T217	3		T218	3
all_values[1]	auto[1]	auto[0]	1527	1		T33	2		T52	3		T40	2
all_values[1]	auto[1]	auto[1]	120	1		T216	5		T218	3		T294	1
all_values[2]	auto[0]	auto[0]	86258	1		T1	2		T2	4		T3	2
all_values[2]	auto[0]	auto[1]	141	1		T216	4		T217	4		T218	7
all_values[2]	auto[1]	auto[0]	121	1		T46	2		T47	2		T48	2
all_values[2]	auto[1]	auto[1]	139	1		T216	3		T217	3		T218	1
all_values[3]	auto[0]	auto[0]	84874	1		T1	2		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	124	1		T216	1		T217	2		T218	5
all_values[3]	auto[1]	auto[0]	1513	1		T70	1485		T216	1		T217	1
all_values[3]	auto[1]	auto[1]	148	1		T216	5		T217	5		T218	3
all_values[4]	auto[0]	auto[0]	86360	1		T1	2		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	124	1		T216	5		T217	1		T218	4
all_values[4]	auto[1]	auto[0]	41	1		T71	2		T295	1		T293	1
all_values[4]	auto[1]	auto[1]	134	1		T216	2		T217	5		T218	4
all_values[5]	auto[0]	auto[0]	86362	1		T1	2		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	146	1		T216	4		T217	3		T218	4
all_values[5]	auto[1]	auto[0]	31	1		T218	2		T291	2		T294	2
all_values[5]	auto[1]	auto[1]	120	1		T216	4		T217	5		T218	2
all_values[6]	auto[0]	auto[0]	86355	1		T1	2		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	135	1		T216	4		T218	4		T291	3
all_values[6]	auto[1]	auto[0]	32	1		T216	1		T217	3		T292	5
all_values[6]	auto[1]	auto[1]	137	1		T216	2		T218	4		T291	2
all_values[7]	auto[0]	auto[0]	86353	1		T1	2		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	160	1		T216	3		T217	4		T218	5
all_values[7]	auto[1]	auto[0]	23	1		T55	2		T56	2		T216	1
all_values[7]	auto[1]	auto[1]	123	1		T216	4		T217	3		T218	1
all_values[8]	auto[0]	auto[0]	86346	1		T1	2		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	145	1		T216	5		T217	2		T218	4
all_values[8]	auto[1]	auto[0]	32	1		T60	11		T296	2		T297	3
all_values[8]	auto[1]	auto[1]	136	1		T216	3		T217	6		T218	4
all_values[9]	auto[0]	auto[0]	86343	1		T1	2		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	152	1		T216	5		T217	6		T218	4
all_values[9]	auto[1]	auto[0]	48	1		T67	5		T68	5		T69	5
all_values[9]	auto[1]	auto[1]	116	1		T216	2		T217	1		T218	4
all_values[10]	auto[0]	auto[0]	86358	1		T1	2		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	128	1		T216	3		T217	6		T218	5
all_values[10]	auto[1]	auto[0]	28	1		T216	1		T217	1		T295	1
all_values[10]	auto[1]	auto[1]	145	1		T216	4		T217	1		T218	3
all_values[11]	auto[0]	auto[0]	86259	1		T1	2		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	142	1		T216	4		T217	5		T218	5
all_values[11]	auto[1]	auto[0]	127	1		T53	2		T77	2		T78	2
all_values[11]	auto[1]	auto[1]	131	1		T216	4		T217	2		T218	3
all_values[12]	auto[0]	auto[0]	86343	1		T1	2		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	161	1		T216	4		T217	6		T218	4
all_values[12]	auto[1]	auto[0]	37	1		T80	3		T81	3		T82	3
all_values[12]	auto[1]	auto[1]	118	1		T216	4		T217	2		T291	3
all_values[13]	auto[0]	auto[0]	86351	1		T1	2		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	124	1		T216	2		T217	2		T218	3
all_values[13]	auto[1]	auto[0]	22	1		T295	1		T298	2		T299	1
all_values[13]	auto[1]	auto[1]	162	1		T216	6		T217	6		T218	5
all_values[14]	auto[0]	auto[0]	86346	1		T1	2		T2	4		T3	2
all_values[14]	auto[0]	auto[1]	150	1		T216	5		T217	4		T218	1
all_values[14]	auto[1]	auto[0]	21	1		T216	1		T218	2		T291	2
all_values[14]	auto[1]	auto[1]	142	1		T216	2		T217	2		T218	5
all_values[15]	auto[0]	auto[0]	86359	1		T1	2		T2	4		T3	2
all_values[15]	auto[0]	auto[1]	141	1		T216	4		T217	6		T218	5
all_values[15]	auto[1]	auto[0]	31	1		T216	1		T291	2		T300	1
all_values[15]	auto[1]	auto[1]	128	1		T216	3		T217	2		T218	3
all_values[16]	auto[0]	auto[0]	86338	1		T1	2		T2	4		T3	2
all_values[16]	auto[0]	auto[1]	121	1		T216	3		T217	6		T218	4
all_values[16]	auto[1]	auto[0]	45	1		T72	8		T73	8		T74	8
all_values[16]	auto[1]	auto[1]	155	1		T216	5		T217	2		T218	4
all_values[17]	auto[0]	auto[0]	86346	1		T1	2		T2	4		T3	2
all_values[17]	auto[0]	auto[1]	153	1		T216	6		T218	7		T291	1
all_values[17]	auto[1]	auto[0]	30	1		T61	2		T62	2		T63	2
all_values[17]	auto[1]	auto[1]	130	1		T216	2		T217	3		T218	1