Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	86659	1		T1	2		T2	4		T3	2
all_pins[1]	86659	1		T1	2		T2	4		T3	2
all_pins[2]	86659	1		T1	2		T2	4		T3	2
all_pins[3]	86659	1		T1	2		T2	4		T3	2
all_pins[4]	86659	1		T1	2		T2	4		T3	2
all_pins[5]	86659	1		T1	2		T2	4		T3	2
all_pins[6]	86659	1		T1	2		T2	4		T3	2
all_pins[7]	86659	1		T1	2		T2	4		T3	2
all_pins[8]	86659	1		T1	2		T2	4		T3	2
all_pins[9]	86659	1		T1	2		T2	4		T3	2
all_pins[10]	86659	1		T1	2		T2	4		T3	2
all_pins[11]	86659	1		T1	2		T2	4		T3	2
all_pins[12]	86659	1		T1	2		T2	4		T3	2
all_pins[13]	86659	1		T1	2		T2	4		T3	2
all_pins[14]	86659	1		T1	2		T2	4		T3	2
all_pins[15]	86659	1		T1	2		T2	4		T3	2
all_pins[16]	86659	1		T1	2		T2	4		T3	2
all_pins[17]	86659	1		T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1557605	1		T1	36		T2	72		T3	36
values[0x1]	2257	1		T33	1		T53	1		T52	1
transitions[0x0=>0x1]	1991	1		T33	1		T53	1		T52	1
transitions[0x1=>0x0]	2003	1		T33	1		T53	1		T52	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	86549	1		T1	2		T2	4		T3	2
all_pins[0]	values[0x1]	110	1		T54	1		T301	1		T302	1
all_pins[0]	transitions[0x0=>0x1]	99	1		T54	1		T301	1		T302	1
all_pins[0]	transitions[0x1=>0x0]	989	1		T33	1		T52	1		T40	1
all_pins[1]	values[0x0]	85659	1		T1	2		T2	4		T3	2
all_pins[1]	values[0x1]	1000	1		T33	1		T52	1		T40	1
all_pins[1]	transitions[0x0=>0x1]	987	1		T33	1		T52	1		T40	1
all_pins[1]	transitions[0x1=>0x0]	117	1		T46	1		T47	1		T48	1
all_pins[2]	values[0x0]	86529	1		T1	2		T2	4		T3	2
all_pins[2]	values[0x1]	130	1		T46	1		T47	1		T48	1
all_pins[2]	transitions[0x0=>0x1]	108	1		T46	1		T47	1		T48	1
all_pins[2]	transitions[0x1=>0x0]	44	1		T70	1		T216	1		T291	1
all_pins[3]	values[0x0]	86593	1		T1	2		T2	4		T3	2
all_pins[3]	values[0x1]	66	1		T70	1		T216	3		T218	1
all_pins[3]	transitions[0x0=>0x1]	46	1		T70	1		T216	2		T218	1
all_pins[3]	transitions[0x1=>0x0]	50	1		T71	1		T216	1		T217	3
all_pins[4]	values[0x0]	86589	1		T1	2		T2	4		T3	2
all_pins[4]	values[0x1]	70	1		T71	1		T216	2		T217	3
all_pins[4]	transitions[0x0=>0x1]	56	1		T71	1		T216	1		T217	3
all_pins[4]	transitions[0x1=>0x0]	44	1		T216	2		T217	2		T218	2
all_pins[5]	values[0x0]	86601	1		T1	2		T2	4		T3	2
all_pins[5]	values[0x1]	58	1		T216	3		T217	2		T218	2
all_pins[5]	transitions[0x0=>0x1]	41	1		T216	2		T217	2		T218	2
all_pins[5]	transitions[0x1=>0x0]	54	1		T216	1		T218	1		T291	2
all_pins[6]	values[0x0]	86588	1		T1	2		T2	4		T3	2
all_pins[6]	values[0x1]	71	1		T216	2		T218	1		T291	2
all_pins[6]	transitions[0x0=>0x1]	60	1		T216	1		T218	1		T291	1
all_pins[6]	transitions[0x1=>0x0]	43	1		T55	1		T56	1		T216	2
all_pins[7]	values[0x0]	86605	1		T1	2		T2	4		T3	2
all_pins[7]	values[0x1]	54	1		T55	1		T56	1		T216	3
all_pins[7]	transitions[0x0=>0x1]	41	1		T55	1		T56	1		T216	1
all_pins[7]	transitions[0x1=>0x0]	45	1		T60	1		T216	1		T217	3
all_pins[8]	values[0x0]	86601	1		T1	2		T2	4		T3	2
all_pins[8]	values[0x1]	58	1		T60	1		T216	3		T217	4
all_pins[8]	transitions[0x0=>0x1]	44	1		T60	1		T216	2		T217	3
all_pins[8]	transitions[0x1=>0x0]	59	1		T67	2		T68	2		T69	2
all_pins[9]	values[0x0]	86586	1		T1	2		T2	4		T3	2
all_pins[9]	values[0x1]	73	1		T67	2		T68	2		T69	2
all_pins[9]	transitions[0x0=>0x1]	64	1		T67	2		T68	2		T69	2
all_pins[9]	transitions[0x1=>0x0]	54	1		T216	3		T217	1		T218	2
all_pins[10]	values[0x0]	86596	1		T1	2		T2	4		T3	2
all_pins[10]	values[0x1]	63	1		T216	3		T217	1		T218	2
all_pins[10]	transitions[0x0=>0x1]	49	1		T216	1		T217	1		T218	2
all_pins[10]	transitions[0x1=>0x0]	90	1		T53	1		T77	1		T78	1
all_pins[11]	values[0x0]	86555	1		T1	2		T2	4		T3	2
all_pins[11]	values[0x1]	104	1		T53	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	95	1		T53	1		T77	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	55	1		T80	1		T81	1		T82	1
all_pins[12]	values[0x0]	86595	1		T1	2		T2	4		T3	2
all_pins[12]	values[0x1]	64	1		T80	1		T81	1		T82	1
all_pins[12]	transitions[0x0=>0x1]	53	1		T80	1		T81	1		T82	1
all_pins[12]	transitions[0x1=>0x0]	51	1		T216	1		T217	2		T218	2
all_pins[13]	values[0x0]	86597	1		T1	2		T2	4		T3	2
all_pins[13]	values[0x1]	62	1		T216	1		T217	2		T218	2
all_pins[13]	transitions[0x0=>0x1]	45	1		T216	1		T217	2		T292	1
all_pins[13]	transitions[0x1=>0x0]	51	1		T216	1		T217	1		T300	3
all_pins[14]	values[0x0]	86591	1		T1	2		T2	4		T3	2
all_pins[14]	values[0x1]	68	1		T216	1		T217	1		T218	2
all_pins[14]	transitions[0x0=>0x1]	52	1		T217	1		T218	2		T300	3
all_pins[14]	transitions[0x1=>0x0]	43	1		T216	1		T217	1		T291	2
all_pins[15]	values[0x0]	86600	1		T1	2		T2	4		T3	2
all_pins[15]	values[0x1]	59	1		T216	2		T217	1		T291	2
all_pins[15]	transitions[0x0=>0x1]	42	1		T216	1		T217	1		T294	1
all_pins[15]	transitions[0x1=>0x0]	70	1		T72	4		T73	4		T74	4
all_pins[16]	values[0x0]	86572	1		T1	2		T2	4		T3	2
all_pins[16]	values[0x1]	87	1		T72	4		T73	4		T74	4
all_pins[16]	transitions[0x0=>0x1]	72	1		T72	4		T73	4		T74	4
all_pins[16]	transitions[0x1=>0x0]	45	1		T61	1		T62	1		T63	1
all_pins[17]	values[0x0]	86599	1		T1	2		T2	4		T3	2
all_pins[17]	values[0x1]	60	1		T61	1		T62	1		T63	1
all_pins[17]	transitions[0x0=>0x1]	37	1		T61	1		T62	1		T63	1
all_pins[17]	transitions[0x1=>0x0]	99	1		T54	1		T301	1		T302	1