Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T216	7		T217	7		T218	7
all_values[1]	278	1		T216	7		T217	7		T218	7
all_values[2]	278	1		T216	7		T217	7		T218	7
all_values[3]	278	1		T216	7		T217	7		T218	7
all_values[4]	278	1		T216	7		T217	7		T218	7
all_values[5]	278	1		T216	7		T217	7		T218	7
all_values[6]	278	1		T216	7		T217	7		T218	7
all_values[7]	278	1		T216	7		T217	7		T218	7
all_values[8]	278	1		T216	7		T217	7		T218	7
all_values[9]	278	1		T216	7		T217	7		T218	7
all_values[10]	278	1		T216	7		T217	7		T218	7
all_values[11]	278	1		T216	7		T217	7		T218	7
all_values[12]	278	1		T216	7		T217	7		T218	7
all_values[13]	278	1		T216	7		T217	7		T218	7
all_values[14]	278	1		T216	7		T217	7		T218	7
all_values[15]	278	1		T216	7		T217	7		T218	7
all_values[16]	278	1		T216	7		T217	7		T218	7
all_values[17]	278	1		T216	7		T217	7		T218	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2823	1		T216	75		T217	74		T218	79
auto[1]	2181	1		T216	51		T217	52		T218	47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	889	1		T216	12		T217	27		T218	12
auto[1]	4115	1		T216	114		T217	99		T218	114

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2917	1		T216	64		T217	67		T218	70
auto[1]	2087	1		T216	62		T217	59		T218	56

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1		T216	1		T294	1		T300	1
all_values[0]	auto[0]	auto[0]	auto[1]	67	1		T216	4		T217	2		T295	1
all_values[0]	auto[0]	auto[1]	auto[0]	16	1		T300	1		T297	1		T303	4
all_values[0]	auto[0]	auto[1]	auto[1]	55	1		T217	2		T218	2		T291	2
all_values[0]	auto[1]	auto[0]	auto[1]	52	1		T216	1		T217	1		T218	2
all_values[0]	auto[1]	auto[1]	auto[1]	59	1		T216	1		T217	2		T218	3
all_values[1]	auto[0]	auto[0]	auto[0]	36	1		T217	3		T218	2		T291	1
all_values[1]	auto[0]	auto[0]	auto[1]	69	1		T216	1		T217	1		T218	2
all_values[1]	auto[0]	auto[1]	auto[0]	20	1		T217	2		T293	2		T297	1
all_values[1]	auto[0]	auto[1]	auto[1]	49	1		T216	1		T218	1		T292	1
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T216	2		T291	2		T294	2
all_values[1]	auto[1]	auto[1]	auto[1]	41	1		T216	3		T217	1		T218	2
all_values[2]	auto[0]	auto[0]	auto[0]	28	1		T216	1		T217	1		T295	1
all_values[2]	auto[0]	auto[0]	auto[1]	59	1		T216	1		T217	1		T218	2
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T295	1		T292	2		T304	1
all_values[2]	auto[0]	auto[1]	auto[1]	65	1		T216	1		T217	2		T218	1
all_values[2]	auto[1]	auto[0]	auto[1]	73	1		T216	3		T217	1		T218	4
all_values[2]	auto[1]	auto[1]	auto[1]	37	1		T216	1		T217	2		T300	2
all_values[3]	auto[0]	auto[0]	auto[0]	37	1		T216	2		T217	1		T294	1
all_values[3]	auto[0]	auto[0]	auto[1]	54	1		T218	4		T291	2		T300	1
all_values[3]	auto[0]	auto[1]	auto[0]	14	1		T295	2		T292	1		T293	1
all_values[3]	auto[0]	auto[1]	auto[1]	58	1		T216	2		T217	3		T218	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T216	1		T217	2		T218	1
all_values[3]	auto[1]	auto[1]	auto[1]	52	1		T216	2		T217	1		T218	1
all_values[4]	auto[0]	auto[0]	auto[0]	41	1		T216	1		T217	2		T294	1
all_values[4]	auto[0]	auto[0]	auto[1]	47	1		T216	3		T218	3		T294	2
all_values[4]	auto[0]	auto[1]	auto[0]	23	1		T295	1		T293	1		T296	1
all_values[4]	auto[0]	auto[1]	auto[1]	57	1		T217	2		T218	1		T291	2
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T216	2		T217	1		T218	1
all_values[4]	auto[1]	auto[1]	auto[1]	55	1		T216	1		T217	2		T218	2
all_values[5]	auto[0]	auto[0]	auto[0]	37	1		T218	1		T294	1		T300	4
all_values[5]	auto[0]	auto[0]	auto[1]	64	1		T216	3		T217	2		T218	2
all_values[5]	auto[0]	auto[1]	auto[0]	20	1		T218	1		T291	2		T294	1
all_values[5]	auto[0]	auto[1]	auto[1]	54	1		T217	1		T218	1		T291	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T216	2		T217	3		T295	1
all_values[5]	auto[1]	auto[1]	auto[1]	39	1		T216	2		T217	1		T218	2
all_values[6]	auto[0]	auto[0]	auto[0]	33	1		T216	1		T217	6		T292	1
all_values[6]	auto[0]	auto[0]	auto[1]	49	1		T216	2		T218	2		T291	2
all_values[6]	auto[0]	auto[1]	auto[0]	20	1		T216	1		T217	1		T292	3
all_values[6]	auto[0]	auto[1]	auto[1]	59	1		T216	1		T218	3		T291	1
all_values[6]	auto[1]	auto[0]	auto[1]	66	1		T218	2		T294	1		T300	3
all_values[6]	auto[1]	auto[1]	auto[1]	51	1		T216	2		T291	1		T294	2
all_values[7]	auto[0]	auto[0]	auto[0]	34	1		T216	1		T217	1		T218	2
all_values[7]	auto[0]	auto[0]	auto[1]	61	1		T216	2		T217	1		T218	3
all_values[7]	auto[0]	auto[1]	auto[0]	10	1		T300	1		T298	1		T305	1
all_values[7]	auto[0]	auto[1]	auto[1]	49	1		T216	1		T218	1		T294	1
all_values[7]	auto[1]	auto[0]	auto[1]	79	1		T217	1		T218	1		T291	1
all_values[7]	auto[1]	auto[1]	auto[1]	45	1		T216	3		T217	4		T297	1
all_values[8]	auto[0]	auto[0]	auto[0]	28	1		T291	1		T294	1		T295	1
all_values[8]	auto[0]	auto[0]	auto[1]	62	1		T216	3		T217	1		T300	3
all_values[8]	auto[0]	auto[1]	auto[0]	16	1		T296	2		T297	2		T306	2
all_values[8]	auto[0]	auto[1]	auto[1]	53	1		T217	1		T218	1		T291	2
all_values[8]	auto[1]	auto[0]	auto[1]	72	1		T216	3		T217	3		T218	4
all_values[8]	auto[1]	auto[1]	auto[1]	47	1		T216	1		T217	2		T218	2
all_values[9]	auto[0]	auto[0]	auto[0]	45	1		T216	1		T217	1		T294	4
all_values[9]	auto[0]	auto[0]	auto[1]	69	1		T216	2		T217	3		T218	3
all_values[9]	auto[0]	auto[1]	auto[0]	12	1		T307	1		T308	1		T306	1
all_values[9]	auto[0]	auto[1]	auto[1]	43	1		T218	1		T295	2		T293	1
all_values[9]	auto[1]	auto[0]	auto[1]	53	1		T216	1		T217	2		T218	1
all_values[9]	auto[1]	auto[1]	auto[1]	56	1		T216	3		T217	1		T218	2
all_values[10]	auto[0]	auto[0]	auto[0]	32	1		T216	1		T217	1		T291	2
all_values[10]	auto[0]	auto[0]	auto[1]	47	1		T217	2		T218	2		T291	1
all_values[10]	auto[0]	auto[1]	auto[0]	21	1		T295	1		T308	2		T304	1
all_values[10]	auto[0]	auto[1]	auto[1]	62	1		T216	1		T218	1		T295	2
all_values[10]	auto[1]	auto[0]	auto[1]	65	1		T216	3		T217	3		T218	3
all_values[10]	auto[1]	auto[1]	auto[1]	51	1		T216	2		T217	1		T218	1
all_values[11]	auto[0]	auto[0]	auto[0]	35	1		T217	1		T294	1		T300	1
all_values[11]	auto[0]	auto[0]	auto[1]	52	1		T216	2		T217	2		T218	3
all_values[11]	auto[0]	auto[1]	auto[0]	16	1		T295	2		T298	2		T307	1
all_values[11]	auto[0]	auto[1]	auto[1]	58	1		T216	2		T218	1		T300	2
all_values[11]	auto[1]	auto[0]	auto[1]	64	1		T216	1		T217	2		T218	2
all_values[11]	auto[1]	auto[1]	auto[1]	53	1		T216	2		T217	2		T218	1
all_values[12]	auto[0]	auto[0]	auto[0]	34	1		T218	4		T296	2		T299	2
all_values[12]	auto[0]	auto[0]	auto[1]	59	1		T216	3		T217	3		T218	1
all_values[12]	auto[0]	auto[1]	auto[0]	12	1		T291	1		T296	1		T307	4
all_values[12]	auto[0]	auto[1]	auto[1]	51	1		T216	1		T217	1		T291	1
all_values[12]	auto[1]	auto[0]	auto[1]	75	1		T216	1		T217	3		T218	1
all_values[12]	auto[1]	auto[1]	auto[1]	47	1		T216	2		T218	1		T291	2
all_values[13]	auto[0]	auto[0]	auto[0]	24	1		T300	1		T295	1		T296	1
all_values[13]	auto[0]	auto[0]	auto[1]	48	1		T291	2		T294	2		T300	1
all_values[13]	auto[0]	auto[1]	auto[0]	16	1		T295	1		T298	2		T299	1
all_values[13]	auto[0]	auto[1]	auto[1]	59	1		T216	3		T217	2		T218	1
all_values[13]	auto[1]	auto[0]	auto[1]	67	1		T216	2		T217	2		T218	3
all_values[13]	auto[1]	auto[1]	auto[1]	64	1		T216	2		T217	3		T218	3
all_values[14]	auto[0]	auto[0]	auto[0]	21	1		T216	1		T217	2		T218	1
all_values[14]	auto[0]	auto[0]	auto[1]	57	1		T216	2		T217	1		T218	1
all_values[14]	auto[0]	auto[1]	auto[0]	14	1		T218	1		T291	2		T294	1
all_values[14]	auto[0]	auto[1]	auto[1]	53	1		T216	1		T218	1		T300	1
all_values[14]	auto[1]	auto[0]	auto[1]	77	1		T216	2		T217	1		T291	1
all_values[14]	auto[1]	auto[1]	auto[1]	56	1		T216	1		T217	3		T218	3
all_values[15]	auto[0]	auto[0]	auto[0]	33	1		T216	1		T293	1		T298	1
all_values[15]	auto[0]	auto[0]	auto[1]	53	1		T216	1		T217	1		T218	4
all_values[15]	auto[0]	auto[1]	auto[0]	21	1		T291	2		T300	1		T305	3
all_values[15]	auto[0]	auto[1]	auto[1]	53	1		T216	2		T217	2		T218	1
all_values[15]	auto[1]	auto[0]	auto[1]	72	1		T216	2		T217	3		T218	1
all_values[15]	auto[1]	auto[1]	auto[1]	46	1		T216	1		T217	1		T218	1
all_values[16]	auto[0]	auto[0]	auto[0]	37	1		T296	1		T297	1		T299	2
all_values[16]	auto[0]	auto[0]	auto[1]	52	1		T216	2		T217	1		T218	1
all_values[16]	auto[0]	auto[1]	auto[0]	14	1		T296	1		T307	2		T309	2
all_values[16]	auto[0]	auto[1]	auto[1]	67	1		T216	2		T217	2		T218	3
all_values[16]	auto[1]	auto[0]	auto[1]	65	1		T216	1		T217	3		T218	3
all_values[16]	auto[1]	auto[1]	auto[1]	43	1		T216	2		T217	1		T291	2
all_values[17]	auto[0]	auto[0]	auto[0]	31	1		T217	3		T293	1		T307	2
all_values[17]	auto[0]	auto[0]	auto[1]	64	1		T216	3		T218	4		T300	2
all_values[17]	auto[0]	auto[1]	auto[0]	13	1		T217	2		T293	1		T307	2
all_values[17]	auto[0]	auto[1]	auto[1]	50	1		T217	1		T291	2		T294	1
all_values[17]	auto[1]	auto[0]	auto[1]	70	1		T216	3		T218	3		T294	1
all_values[17]	auto[1]	auto[1]	auto[1]	50	1		T216	1		T217	1		T291	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal