Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.81 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2852
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T275 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1713833524 Jul 11 05:36:53 PM PDT 24 Jul 11 05:37:01 PM PDT 24 156409206 ps
T2763 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.829345044 Jul 11 05:38:04 PM PDT 24 Jul 11 05:38:11 PM PDT 24 1466086547 ps
T306 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3934613573 Jul 11 05:38:56 PM PDT 24 Jul 11 05:38:58 PM PDT 24 36903464 ps
T303 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.931075504 Jul 11 05:38:13 PM PDT 24 Jul 11 05:38:15 PM PDT 24 45499776 ps
T2764 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.791531969 Jul 11 05:36:53 PM PDT 24 Jul 11 05:37:00 PM PDT 24 190801539 ps
T2765 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.132713524 Jul 11 05:37:06 PM PDT 24 Jul 11 05:37:09 PM PDT 24 120129807 ps
T2766 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1853715174 Jul 11 05:38:26 PM PDT 24 Jul 11 05:38:28 PM PDT 24 114785764 ps
T2767 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2227939665 Jul 11 05:37:06 PM PDT 24 Jul 11 05:37:09 PM PDT 24 110335247 ps
T2768 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1424841443 Jul 11 05:37:36 PM PDT 24 Jul 11 05:37:41 PM PDT 24 488398140 ps
T2769 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2530307161 Jul 11 05:38:04 PM PDT 24 Jul 11 05:38:07 PM PDT 24 206949326 ps
T276 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2573283805 Jul 11 05:36:52 PM PDT 24 Jul 11 05:36:58 PM PDT 24 67216666 ps
T2770 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3107329975 Jul 11 05:36:57 PM PDT 24 Jul 11 05:37:03 PM PDT 24 94723391 ps
T277 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2718968869 Jul 11 05:38:30 PM PDT 24 Jul 11 05:38:32 PM PDT 24 77808608 ps
T2771 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3823613856 Jul 11 05:38:04 PM PDT 24 Jul 11 05:38:07 PM PDT 24 173469767 ps
T2772 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.813209481 Jul 11 05:39:00 PM PDT 24 Jul 11 05:39:02 PM PDT 24 49703770 ps
T2773 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1742455440 Jul 11 05:38:17 PM PDT 24 Jul 11 05:38:21 PM PDT 24 266288962 ps
T309 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3409369180 Jul 11 05:38:50 PM PDT 24 Jul 11 05:38:51 PM PDT 24 55560098 ps
T278 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1949150968 Jul 11 05:36:51 PM PDT 24 Jul 11 05:36:57 PM PDT 24 86985011 ps
T2774 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1239622845 Jul 11 05:37:00 PM PDT 24 Jul 11 05:37:04 PM PDT 24 124392596 ps
T2775 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1929767752 Jul 11 05:37:00 PM PDT 24 Jul 11 05:37:03 PM PDT 24 36489256 ps
T2776 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2253683178 Jul 11 05:38:13 PM PDT 24 Jul 11 05:38:16 PM PDT 24 156906950 ps
T2777 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1296837112 Jul 11 05:38:30 PM PDT 24 Jul 11 05:38:36 PM PDT 24 486939493 ps
T2778 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2154081203 Jul 11 05:37:07 PM PDT 24 Jul 11 05:37:10 PM PDT 24 55762930 ps
T2779 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2942091187 Jul 11 05:38:14 PM PDT 24 Jul 11 05:38:16 PM PDT 24 33796279 ps
T2780 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3410537464 Jul 11 05:38:15 PM PDT 24 Jul 11 05:38:18 PM PDT 24 181363371 ps
T279 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.658694890 Jul 11 05:37:20 PM PDT 24 Jul 11 05:37:25 PM PDT 24 95095266 ps
T2781 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1937896598 Jul 11 05:38:47 PM PDT 24 Jul 11 05:38:48 PM PDT 24 44883558 ps
T2782 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3448808434 Jul 11 05:37:05 PM PDT 24 Jul 11 05:37:09 PM PDT 24 229713417 ps
T2783 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4176592140 Jul 11 05:38:04 PM PDT 24 Jul 11 05:38:07 PM PDT 24 152309466 ps
T314 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.943126972 Jul 11 05:38:15 PM PDT 24 Jul 11 05:38:21 PM PDT 24 490612562 ps
T2784 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2590495357 Jul 11 05:38:06 PM PDT 24 Jul 11 05:38:09 PM PDT 24 46337579 ps
T2785 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4277884947 Jul 11 05:38:07 PM PDT 24 Jul 11 05:38:10 PM PDT 24 88187124 ps
T316 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3856299925 Jul 11 05:37:07 PM PDT 24 Jul 11 05:37:11 PM PDT 24 436000346 ps
T2786 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.465263996 Jul 11 05:48:16 PM PDT 24 Jul 11 05:48:23 PM PDT 24 248741418 ps
T2787 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2689946490 Jul 11 05:36:44 PM PDT 24 Jul 11 05:36:48 PM PDT 24 74480476 ps
T2788 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.98280317 Jul 11 05:38:26 PM PDT 24 Jul 11 05:38:29 PM PDT 24 104276346 ps
T2789 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.668259209 Jul 11 05:36:57 PM PDT 24 Jul 11 05:37:02 PM PDT 24 51337615 ps
T2790 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2097583133 Jul 11 05:38:14 PM PDT 24 Jul 11 05:38:17 PM PDT 24 197949717 ps
T2791 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4072790506 Jul 11 05:38:06 PM PDT 24 Jul 11 05:38:13 PM PDT 24 855773550 ps
T2792 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3544724718 Jul 11 05:36:54 PM PDT 24 Jul 11 05:36:59 PM PDT 24 55076692 ps
T2793 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.807607000 Jul 11 05:38:31 PM PDT 24 Jul 11 05:38:33 PM PDT 24 45627747 ps
T317 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1375402922 Jul 11 05:36:50 PM PDT 24 Jul 11 05:36:58 PM PDT 24 575717565 ps
T2794 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3473739689 Jul 11 05:36:45 PM PDT 24 Jul 11 05:36:49 PM PDT 24 110706532 ps
T2795 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4195318420 Jul 11 05:38:31 PM PDT 24 Jul 11 05:38:33 PM PDT 24 44220130 ps
T2796 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4018374310 Jul 11 05:37:01 PM PDT 24 Jul 11 05:37:04 PM PDT 24 93302106 ps
T2797 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.669699307 Jul 11 05:39:17 PM PDT 24 Jul 11 05:39:18 PM PDT 24 45723951 ps
T2798 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2930643761 Jul 11 05:38:26 PM PDT 24 Jul 11 05:38:28 PM PDT 24 47115242 ps
T2799 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3811302524 Jul 11 05:36:51 PM PDT 24 Jul 11 05:36:56 PM PDT 24 75099195 ps
T2800 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2832294614 Jul 11 05:36:57 PM PDT 24 Jul 11 05:37:03 PM PDT 24 69440783 ps
T2801 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1871925545 Jul 11 05:38:29 PM PDT 24 Jul 11 05:38:30 PM PDT 24 41555968 ps
T2802 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2122830292 Jul 11 05:39:00 PM PDT 24 Jul 11 05:39:02 PM PDT 24 38380130 ps
T2803 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3196869562 Jul 11 05:36:54 PM PDT 24 Jul 11 05:37:00 PM PDT 24 100486477 ps
T2804 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2292010425 Jul 11 05:36:52 PM PDT 24 Jul 11 05:36:59 PM PDT 24 498145842 ps
T2805 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1996037843 Jul 11 05:38:06 PM PDT 24 Jul 11 05:38:11 PM PDT 24 382821104 ps
T2806 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3378619431 Jul 11 05:38:02 PM PDT 24 Jul 11 05:38:04 PM PDT 24 61683661 ps
T2807 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3693257680 Jul 11 05:37:06 PM PDT 24 Jul 11 05:37:08 PM PDT 24 268073141 ps
T2808 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1492643705 Jul 11 05:36:50 PM PDT 24 Jul 11 05:36:55 PM PDT 24 87684649 ps
T2809 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2894206328 Jul 11 05:37:06 PM PDT 24 Jul 11 05:37:09 PM PDT 24 175686408 ps
T2810 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2794358190 Jul 11 05:38:56 PM PDT 24 Jul 11 05:38:59 PM PDT 24 48072387 ps
T2811 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3314562977 Jul 11 05:38:31 PM PDT 24 Jul 11 05:38:34 PM PDT 24 192764487 ps
T2812 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.773260580 Jul 11 05:38:51 PM PDT 24 Jul 11 05:38:53 PM PDT 24 41940567 ps
T2813 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4163510641 Jul 11 05:36:55 PM PDT 24 Jul 11 05:37:00 PM PDT 24 42701705 ps
T2814 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.738844106 Jul 11 05:38:18 PM PDT 24 Jul 11 05:38:20 PM PDT 24 46337065 ps
T2815 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3518094262 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:56 PM PDT 24 329238429 ps
T2816 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.70118706 Jul 11 05:38:32 PM PDT 24 Jul 11 05:38:34 PM PDT 24 36578555 ps
T2817 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1025754448 Jul 11 05:36:52 PM PDT 24 Jul 11 05:36:59 PM PDT 24 171555262 ps
T2818 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4012582300 Jul 11 05:38:29 PM PDT 24 Jul 11 05:38:31 PM PDT 24 29879536 ps
T2819 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2453284016 Jul 11 05:37:07 PM PDT 24 Jul 11 05:37:10 PM PDT 24 53853775 ps
T2820 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3045446209 Jul 11 05:37:10 PM PDT 24 Jul 11 05:37:13 PM PDT 24 152556134 ps
T2821 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3906485142 Jul 11 05:38:21 PM PDT 24 Jul 11 05:38:23 PM PDT 24 43677690 ps
T2822 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1599880582 Jul 11 05:38:04 PM PDT 24 Jul 11 05:38:09 PM PDT 24 561092184 ps
T2823 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2001689300 Jul 11 05:38:16 PM PDT 24 Jul 11 05:38:18 PM PDT 24 56741828 ps
T2824 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1142200115 Jul 11 05:38:04 PM PDT 24 Jul 11 05:38:08 PM PDT 24 179091669 ps
T2825 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.654189933 Jul 11 05:36:54 PM PDT 24 Jul 11 05:37:00 PM PDT 24 42155520 ps
T2826 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2325090852 Jul 11 05:37:07 PM PDT 24 Jul 11 05:37:09 PM PDT 24 43874212 ps
T2827 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1851441104 Jul 11 05:36:48 PM PDT 24 Jul 11 05:36:53 PM PDT 24 88760742 ps
T2828 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2968453399 Jul 11 05:38:15 PM PDT 24 Jul 11 05:38:17 PM PDT 24 42120040 ps
T2829 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2316268712 Jul 11 05:38:15 PM PDT 24 Jul 11 05:38:17 PM PDT 24 52068676 ps
T2830 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1415256449 Jul 11 05:38:04 PM PDT 24 Jul 11 05:38:08 PM PDT 24 103466641 ps
T2831 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4170544768 Jul 11 05:37:00 PM PDT 24 Jul 11 05:37:06 PM PDT 24 424911769 ps
T2832 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4162304701 Jul 11 05:36:53 PM PDT 24 Jul 11 05:36:59 PM PDT 24 36962162 ps
T2833 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3945264870 Jul 11 05:36:59 PM PDT 24 Jul 11 05:37:03 PM PDT 24 58691499 ps
T2834 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4181366348 Jul 11 05:37:20 PM PDT 24 Jul 11 05:37:33 PM PDT 24 1818327225 ps
T2835 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1019467678 Jul 11 05:38:28 PM PDT 24 Jul 11 05:38:30 PM PDT 24 43251291 ps
T2836 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.657538169 Jul 11 05:36:52 PM PDT 24 Jul 11 05:36:58 PM PDT 24 116679677 ps
T2837 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.667754805 Jul 11 05:38:32 PM PDT 24 Jul 11 05:38:34 PM PDT 24 62148667 ps
T2838 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.118797392 Jul 11 05:37:07 PM PDT 24 Jul 11 05:37:10 PM PDT 24 69538321 ps
T2839 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1031697841 Jul 11 05:36:51 PM PDT 24 Jul 11 05:36:56 PM PDT 24 101759818 ps
T2840 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2368121095 Jul 11 05:36:57 PM PDT 24 Jul 11 05:37:02 PM PDT 24 36110822 ps
T2841 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1571700424 Jul 11 05:36:52 PM PDT 24 Jul 11 05:37:06 PM PDT 24 1852376400 ps
T2842 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1413864499 Jul 11 05:36:59 PM PDT 24 Jul 11 05:37:03 PM PDT 24 74610650 ps
T2843 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.641189290 Jul 11 05:38:15 PM PDT 24 Jul 11 05:38:17 PM PDT 24 79475054 ps
T2844 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.324790630 Jul 11 05:37:19 PM PDT 24 Jul 11 05:37:22 PM PDT 24 94586319 ps
T2845 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4233188252 Jul 11 05:36:52 PM PDT 24 Jul 11 05:37:00 PM PDT 24 362645345 ps
T315 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.60110099 Jul 11 05:36:50 PM PDT 24 Jul 11 05:36:59 PM PDT 24 505538477 ps
T2846 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1223778519 Jul 11 05:38:32 PM PDT 24 Jul 11 05:38:34 PM PDT 24 57482891 ps
T2847 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.4178985231 Jul 11 05:37:08 PM PDT 24 Jul 11 05:37:11 PM PDT 24 54811383 ps
T2848 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.86760802 Jul 11 05:36:58 PM PDT 24 Jul 11 05:37:03 PM PDT 24 159651059 ps
T2849 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3285426417 Jul 11 05:36:54 PM PDT 24 Jul 11 05:37:00 PM PDT 24 200496083 ps
T2850 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.696047557 Jul 11 05:36:52 PM PDT 24 Jul 11 05:36:58 PM PDT 24 288113395 ps
T2851 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3398816151 Jul 11 05:38:29 PM PDT 24 Jul 11 05:38:30 PM PDT 24 62564220 ps
T2852 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1714990114 Jul 11 05:38:05 PM PDT 24 Jul 11 05:38:08 PM PDT 24 108716812 ps

Test location /workspace/coverage/default/1.usbdev_device_address.2726624686
Short name T1
Test name
Test status
Simulation time 10227502467 ps
CPU time 18.22 seconds
Started Jul 11 05:53:22 PM PDT 24
Finished Jul 11 05:53:41 PM PDT 24
Peak memory 206644 kb
Host smart-b36e6e47-a865-43b7-9753-3b5f8c67a168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27266
24686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2726624686
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1651284499
Short name T216
Test name
Test status
Simulation time 45189652 ps
CPU time 0.67 seconds
Started Jul 11 05:38:50 PM PDT 24
Finished Jul 11 05:38:52 PM PDT 24
Peak memory 206012 kb
Host smart-d6a332c6-e2aa-4dd2-877d-9d9b8c8115e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1651284499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1651284499
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3077270645
Short name T40
Test name
Test status
Simulation time 3358321987 ps
CPU time 3.98 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:28 PM PDT 24
Peak memory 206452 kb
Host smart-d3c8aa3d-a4c2-4d58-bdb7-92b8601ff88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30772
70645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3077270645
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2539330932
Short name T209
Test name
Test status
Simulation time 971805126 ps
CPU time 4.74 seconds
Started Jul 11 05:37:17 PM PDT 24
Finished Jul 11 05:37:24 PM PDT 24
Peak memory 206324 kb
Host smart-4bacc22b-9631-4529-a640-22974d02d0f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2539330932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2539330932
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2265034986
Short name T12
Test name
Test status
Simulation time 13355104211 ps
CPU time 13.25 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:57:00 PM PDT 24
Peak memory 206336 kb
Host smart-3c43cd16-9f04-4adf-af44-ff059734afc7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2265034986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2265034986
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.1745009902
Short name T4
Test name
Test status
Simulation time 5087043870 ps
CPU time 16.04 seconds
Started Jul 11 05:57:29 PM PDT 24
Finished Jul 11 05:57:51 PM PDT 24
Peak memory 206648 kb
Host smart-04e73ace-86f1-4af6-a8eb-eab31c4e13e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17450
09902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.1745009902
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3982422144
Short name T103
Test name
Test status
Simulation time 176779259 ps
CPU time 0.81 seconds
Started Jul 11 05:59:59 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206388 kb
Host smart-c6240227-c4fa-4b97-9357-51f492cb2b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39824
22144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3982422144
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1693618412
Short name T47
Test name
Test status
Simulation time 147164339 ps
CPU time 0.8 seconds
Started Jul 11 05:57:04 PM PDT 24
Finished Jul 11 05:57:12 PM PDT 24
Peak memory 205796 kb
Host smart-03f253f5-27bf-4ca1-b142-251693ee8417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16936
18412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1693618412
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2323510690
Short name T75
Test name
Test status
Simulation time 11107662001 ps
CPU time 99.05 seconds
Started Jul 11 06:01:42 PM PDT 24
Finished Jul 11 06:03:34 PM PDT 24
Peak memory 206616 kb
Host smart-7f6d2729-39a9-4d83-85cc-2dbff07e5258
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2323510690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2323510690
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1418523583
Short name T295
Test name
Test status
Simulation time 48449259 ps
CPU time 0.69 seconds
Started Jul 11 05:39:00 PM PDT 24
Finished Jul 11 05:39:02 PM PDT 24
Peak memory 206040 kb
Host smart-e2adfc51-a174-48c9-a077-ceea9c46f8c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1418523583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1418523583
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1630552849
Short name T126
Test name
Test status
Simulation time 250214813 ps
CPU time 0.9 seconds
Started Jul 11 05:57:55 PM PDT 24
Finished Jul 11 05:58:03 PM PDT 24
Peak memory 206384 kb
Host smart-f9d90025-ad06-4fdf-b048-8ed2eddf7ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16305
52849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1630552849
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.64548081
Short name T526
Test name
Test status
Simulation time 3968919028 ps
CPU time 4.47 seconds
Started Jul 11 05:56:41 PM PDT 24
Finished Jul 11 05:56:48 PM PDT 24
Peak memory 206372 kb
Host smart-1325640a-44cc-473b-9f5e-712a48b484ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=64548081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.64548081
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1597086232
Short name T232
Test name
Test status
Simulation time 133263200 ps
CPU time 1.32 seconds
Started Jul 11 05:36:55 PM PDT 24
Finished Jul 11 05:37:01 PM PDT 24
Peak memory 222748 kb
Host smart-90b9a049-c20c-4287-a084-daafb71d4674
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597086232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1597086232
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2412084517
Short name T38
Test name
Test status
Simulation time 35585061 ps
CPU time 0.66 seconds
Started Jul 11 05:56:39 PM PDT 24
Finished Jul 11 05:56:43 PM PDT 24
Peak memory 206396 kb
Host smart-7c9c680c-e434-465e-b5f7-b5a40fe62e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24120
84517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2412084517
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2678498622
Short name T111
Test name
Test status
Simulation time 1424779934 ps
CPU time 3.03 seconds
Started Jul 11 05:58:57 PM PDT 24
Finished Jul 11 05:59:11 PM PDT 24
Peak memory 206584 kb
Host smart-3fa5d23b-f8f6-444b-b19d-a1d3c40af5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26784
98622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2678498622
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.827703130
Short name T221
Test name
Test status
Simulation time 824361980 ps
CPU time 1.64 seconds
Started Jul 11 05:53:21 PM PDT 24
Finished Jul 11 05:53:24 PM PDT 24
Peak memory 224284 kb
Host smart-3f45306b-7340-405d-a669-233807ecc736
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=827703130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.827703130
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2616768816
Short name T307
Test name
Test status
Simulation time 62449938 ps
CPU time 0.7 seconds
Started Jul 11 05:38:56 PM PDT 24
Finished Jul 11 05:38:59 PM PDT 24
Peak memory 205972 kb
Host smart-2dd0aa93-2b83-46d5-8274-d5db8a2cb09f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2616768816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2616768816
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.279776979
Short name T535
Test name
Test status
Simulation time 39208930 ps
CPU time 0.67 seconds
Started Jul 11 05:58:00 PM PDT 24
Finished Jul 11 05:58:07 PM PDT 24
Peak memory 206328 kb
Host smart-b95934f9-b916-4a69-b53d-8e10d6263d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=279776979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.279776979
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.790334599
Short name T83
Test name
Test status
Simulation time 310780403 ps
CPU time 1.03 seconds
Started Jul 11 05:53:14 PM PDT 24
Finished Jul 11 05:53:15 PM PDT 24
Peak memory 206392 kb
Host smart-3086c7b3-f829-447c-bd35-e0b8bf92f3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79033
4599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.790334599
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1470815535
Short name T464
Test name
Test status
Simulation time 219673030 ps
CPU time 0.92 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:00:57 PM PDT 24
Peak memory 206540 kb
Host smart-03371e8d-e105-4e5a-8bd0-071efbd26031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708
15535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1470815535
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.351264562
Short name T50
Test name
Test status
Simulation time 20165134327 ps
CPU time 22.08 seconds
Started Jul 11 05:53:32 PM PDT 24
Finished Jul 11 05:53:55 PM PDT 24
Peak memory 206376 kb
Host smart-27aa1d5b-85da-44db-9d3b-58ae42233ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35126
4562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.351264562
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.708502856
Short name T271
Test name
Test status
Simulation time 73478025 ps
CPU time 0.91 seconds
Started Jul 11 05:38:14 PM PDT 24
Finished Jul 11 05:38:16 PM PDT 24
Peak memory 205988 kb
Host smart-0c6cfb45-a252-48d1-a7ba-7a12c052ced2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=708502856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.708502856
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1236430123
Short name T218
Test name
Test status
Simulation time 37289893 ps
CPU time 0.71 seconds
Started Jul 11 05:38:57 PM PDT 24
Finished Jul 11 05:38:59 PM PDT 24
Peak memory 205944 kb
Host smart-e6cc3e49-2ccc-4029-9d23-ba05de1111f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1236430123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1236430123
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2115870720
Short name T244
Test name
Test status
Simulation time 209019377 ps
CPU time 2.74 seconds
Started Jul 11 05:38:30 PM PDT 24
Finished Jul 11 05:38:34 PM PDT 24
Peak memory 214528 kb
Host smart-0f0453bd-b1d8-4c30-b1b6-1f14ce22c73a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2115870720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2115870720
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2332262664
Short name T480
Test name
Test status
Simulation time 172943793 ps
CPU time 0.8 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206384 kb
Host smart-d8e27673-80b1-4f09-a79c-a9ee85cadf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23322
62664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2332262664
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2710647102
Short name T302
Test name
Test status
Simulation time 159039436 ps
CPU time 0.73 seconds
Started Jul 11 05:56:33 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206404 kb
Host smart-565efa19-7953-4654-83f7-b72cb319348e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27106
47102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2710647102
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2942091187
Short name T2779
Test name
Test status
Simulation time 33796279 ps
CPU time 0.7 seconds
Started Jul 11 05:38:14 PM PDT 24
Finished Jul 11 05:38:16 PM PDT 24
Peak memory 205948 kb
Host smart-845aedb9-72fe-4afb-880d-4bad53742607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2942091187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2942091187
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.330033306
Short name T310
Test name
Test status
Simulation time 2459188350 ps
CPU time 6.4 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:07 PM PDT 24
Peak memory 206412 kb
Host smart-90c7a642-29f9-4f0b-a7c7-39256a4ec3ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=330033306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.330033306
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1051022214
Short name T3
Test name
Test status
Simulation time 14345827786 ps
CPU time 30.59 seconds
Started Jul 11 06:00:25 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206620 kb
Host smart-f6b99f09-5a48-4d7d-b576-082501b05fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10510
22214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1051022214
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3657677415
Short name T65
Test name
Test status
Simulation time 173582385 ps
CPU time 0.77 seconds
Started Jul 11 05:56:11 PM PDT 24
Finished Jul 11 05:56:15 PM PDT 24
Peak memory 206388 kb
Host smart-e3f9df80-1fab-47d3-b144-3dc49fc924e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36576
77415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3657677415
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1156156737
Short name T73
Test name
Test status
Simulation time 417613236 ps
CPU time 1.38 seconds
Started Jul 11 05:53:15 PM PDT 24
Finished Jul 11 05:53:18 PM PDT 24
Peak memory 206308 kb
Host smart-9961900b-f10a-43f7-b545-d45531b5c70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11561
56737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.1156156737
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1492643705
Short name T2808
Test name
Test status
Simulation time 87684649 ps
CPU time 0.73 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:55 PM PDT 24
Peak memory 205972 kb
Host smart-0538c0e4-a09b-48b3-aa5f-ed9fa3c82520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1492643705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1492643705
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2461266768
Short name T180
Test name
Test status
Simulation time 8746945665 ps
CPU time 230.07 seconds
Started Jul 11 05:53:48 PM PDT 24
Finished Jul 11 05:57:38 PM PDT 24
Peak memory 206736 kb
Host smart-274a9991-c0b5-41bc-a142-94bb678f2624
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2461266768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2461266768
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.319323294
Short name T60
Test name
Test status
Simulation time 251633533 ps
CPU time 0.93 seconds
Started Jul 11 05:53:16 PM PDT 24
Finished Jul 11 05:53:18 PM PDT 24
Peak memory 206400 kb
Host smart-322ac935-1587-40d8-8448-9f22efcc03d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31932
3294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.319323294
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2082886840
Short name T266
Test name
Test status
Simulation time 14764837849 ps
CPU time 31.1 seconds
Started Jul 11 05:56:18 PM PDT 24
Finished Jul 11 05:56:52 PM PDT 24
Peak memory 214872 kb
Host smart-2d0a5db3-8aa5-42c0-97b4-652b326de443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20828
86840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2082886840
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3977217911
Short name T68
Test name
Test status
Simulation time 144588223 ps
CPU time 0.74 seconds
Started Jul 11 05:52:38 PM PDT 24
Finished Jul 11 05:52:40 PM PDT 24
Peak memory 206380 kb
Host smart-a3cf2608-e23c-4f8c-8264-f714351b4b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39772
17911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3977217911
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1375402922
Short name T317
Test name
Test status
Simulation time 575717565 ps
CPU time 2.86 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 206248 kb
Host smart-d3682e24-6ddf-4d50-9b03-2e8e194725d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1375402922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1375402922
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1298938459
Short name T243
Test name
Test status
Simulation time 144145582 ps
CPU time 1.9 seconds
Started Jul 11 05:38:05 PM PDT 24
Finished Jul 11 05:38:09 PM PDT 24
Peak memory 221872 kb
Host smart-003dce5a-f25c-43c7-8dcd-d3851b2883f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1298938459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1298938459
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.388110298
Short name T76
Test name
Test status
Simulation time 7393480263 ps
CPU time 202.33 seconds
Started Jul 11 05:57:27 PM PDT 24
Finished Jul 11 06:00:55 PM PDT 24
Peak memory 206628 kb
Host smart-e8f7e694-0df3-490c-9f3e-cceb4615467d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=388110298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.388110298
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1246309429
Short name T164
Test name
Test status
Simulation time 8222571782 ps
CPU time 224.94 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:04:43 PM PDT 24
Peak memory 206712 kb
Host smart-64fac852-768d-4041-b62b-7b44c85bbf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463
09429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1246309429
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.911250801
Short name T173
Test name
Test status
Simulation time 7470209236 ps
CPU time 64.49 seconds
Started Jul 11 05:53:14 PM PDT 24
Finished Jul 11 05:54:19 PM PDT 24
Peak memory 206572 kb
Host smart-b35e22f0-2a10-49b2-8616-edd563402ebd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=911250801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.911250801
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1030554713
Short name T1204
Test name
Test status
Simulation time 44923143 ps
CPU time 0.64 seconds
Started Jul 11 05:56:52 PM PDT 24
Finished Jul 11 05:56:57 PM PDT 24
Peak memory 206304 kb
Host smart-131da096-0b95-40a5-89c6-b2e22945eb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10305
54713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1030554713
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2536760071
Short name T512
Test name
Test status
Simulation time 156649620 ps
CPU time 0.77 seconds
Started Jul 11 05:53:13 PM PDT 24
Finished Jul 11 05:53:14 PM PDT 24
Peak memory 206268 kb
Host smart-cbec76a1-9782-4751-8b19-4f93012bb903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25367
60071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2536760071
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1790457690
Short name T11
Test name
Test status
Simulation time 3436478559 ps
CPU time 4.23 seconds
Started Jul 11 05:56:11 PM PDT 24
Finished Jul 11 05:56:19 PM PDT 24
Peak memory 206396 kb
Host smart-6235b652-221c-482a-9a98-cb2aa41039d1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1790457690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1790457690
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2981954666
Short name T188
Test name
Test status
Simulation time 9272447549 ps
CPU time 57.4 seconds
Started Jul 11 05:53:26 PM PDT 24
Finished Jul 11 05:54:25 PM PDT 24
Peak memory 206664 kb
Host smart-854e4731-0dd1-4190-b883-4c104f0e3f84
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2981954666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2981954666
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2741148672
Short name T490
Test name
Test status
Simulation time 212825679 ps
CPU time 1.48 seconds
Started Jul 11 05:53:31 PM PDT 24
Finished Jul 11 05:53:33 PM PDT 24
Peak memory 206544 kb
Host smart-2453c653-727a-4187-aa16-218c952d43db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27411
48672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2741148672
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3209907400
Short name T112
Test name
Test status
Simulation time 9383886148 ps
CPU time 258.32 seconds
Started Jul 11 05:56:49 PM PDT 24
Finished Jul 11 06:01:11 PM PDT 24
Peak memory 206652 kb
Host smart-f5a75fd7-b3ce-4b7a-a312-fa41b813c3a2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3209907400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3209907400
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.566214854
Short name T69
Test name
Test status
Simulation time 176480917 ps
CPU time 0.83 seconds
Started Jul 11 05:54:27 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 206308 kb
Host smart-aa396d0d-f2ae-4996-8fe2-c3fee152ada7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56621
4854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.566214854
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3721648448
Short name T61
Test name
Test status
Simulation time 173790581 ps
CPU time 0.8 seconds
Started Jul 11 05:52:36 PM PDT 24
Finished Jul 11 05:52:37 PM PDT 24
Peak memory 206404 kb
Host smart-aa9191ea-6af8-4c0f-a4b0-bd40f0d12a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37216
48448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3721648448
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3011471909
Short name T70
Test name
Test status
Simulation time 4182824923 ps
CPU time 8.16 seconds
Started Jul 11 05:52:47 PM PDT 24
Finished Jul 11 05:52:55 PM PDT 24
Peak memory 206648 kb
Host smart-fc563a09-1ea0-44e2-86bb-13f59c2b8f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30114
71909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3011471909
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.4221060923
Short name T71
Test name
Test status
Simulation time 159968968 ps
CPU time 0.75 seconds
Started Jul 11 05:52:57 PM PDT 24
Finished Jul 11 05:52:58 PM PDT 24
Peak memory 206272 kb
Host smart-4be3fb17-e0fa-452d-9d57-b5d53d64f135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42210
60923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.4221060923
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3594186978
Short name T1671
Test name
Test status
Simulation time 178031198 ps
CPU time 0.81 seconds
Started Jul 11 05:53:20 PM PDT 24
Finished Jul 11 05:53:21 PM PDT 24
Peak memory 206384 kb
Host smart-1ac0e92d-aba5-4c98-af3f-58dc02feaf04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35941
86978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3594186978
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1849980263
Short name T55
Test name
Test status
Simulation time 172341699 ps
CPU time 0.85 seconds
Started Jul 11 05:53:28 PM PDT 24
Finished Jul 11 05:53:30 PM PDT 24
Peak memory 206388 kb
Host smart-65201b0e-3936-4351-8287-c490a93ecd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18499
80263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1849980263
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2194975135
Short name T312
Test name
Test status
Simulation time 989900833 ps
CPU time 4.82 seconds
Started Jul 11 05:38:32 PM PDT 24
Finished Jul 11 05:38:38 PM PDT 24
Peak memory 206288 kb
Host smart-99085238-8897-4e96-befe-fb765482f3f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2194975135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2194975135
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2288822093
Short name T129
Test name
Test status
Simulation time 189689257 ps
CPU time 0.85 seconds
Started Jul 11 05:53:08 PM PDT 24
Finished Jul 11 05:53:09 PM PDT 24
Peak memory 206396 kb
Host smart-a717b428-76a9-4811-af8d-fb5e1c644e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22888
22093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2288822093
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.2772135431
Short name T57
Test name
Test status
Simulation time 325087700 ps
CPU time 1.11 seconds
Started Jul 11 05:53:16 PM PDT 24
Finished Jul 11 05:53:19 PM PDT 24
Peak memory 206400 kb
Host smart-ae72c4a7-c2d7-41ef-af9d-5630204096d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27721
35431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.2772135431
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2485046345
Short name T143
Test name
Test status
Simulation time 187174372 ps
CPU time 0.8 seconds
Started Jul 11 05:56:16 PM PDT 24
Finished Jul 11 05:56:20 PM PDT 24
Peak memory 206332 kb
Host smart-5447272f-e31e-4f09-b261-9cfe5b7ef21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24850
46345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2485046345
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.996376010
Short name T139
Test name
Test status
Simulation time 188722481 ps
CPU time 0.85 seconds
Started Jul 11 05:56:48 PM PDT 24
Finished Jul 11 05:56:52 PM PDT 24
Peak memory 206364 kb
Host smart-3365f78d-8a77-41e1-b393-3c756eac5380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99637
6010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.996376010
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.3995603510
Short name T122
Test name
Test status
Simulation time 8037954707 ps
CPU time 55.79 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:58:09 PM PDT 24
Peak memory 206320 kb
Host smart-69591f65-1a3a-42e4-884d-8c4e68cb813a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3995603510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.3995603510
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.292480686
Short name T2590
Test name
Test status
Simulation time 188542869 ps
CPU time 0.87 seconds
Started Jul 11 05:57:09 PM PDT 24
Finished Jul 11 05:57:16 PM PDT 24
Peak memory 206372 kb
Host smart-95d95fdd-9c40-44cf-9eac-5f007ed5fd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29248
0686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.292480686
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3569389392
Short name T157
Test name
Test status
Simulation time 259053613 ps
CPU time 0.94 seconds
Started Jul 11 05:57:17 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206392 kb
Host smart-5645d0f6-84f6-4957-8ebf-c2126b92ccae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35693
89392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3569389392
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1143665644
Short name T135
Test name
Test status
Simulation time 192197173 ps
CPU time 0.88 seconds
Started Jul 11 05:57:30 PM PDT 24
Finished Jul 11 05:57:36 PM PDT 24
Peak memory 206380 kb
Host smart-c20625b6-ce31-4d98-b947-dd11281b1237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11436
65644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1143665644
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3372414547
Short name T152
Test name
Test status
Simulation time 267093870 ps
CPU time 0.93 seconds
Started Jul 11 05:57:49 PM PDT 24
Finished Jul 11 05:57:54 PM PDT 24
Peak memory 206300 kb
Host smart-11c67299-c10b-4a88-a153-144335f25d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33724
14547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3372414547
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2229182601
Short name T142
Test name
Test status
Simulation time 209469063 ps
CPU time 0.91 seconds
Started Jul 11 05:58:07 PM PDT 24
Finished Jul 11 05:58:17 PM PDT 24
Peak memory 206340 kb
Host smart-6bdd238c-c5f7-4a11-b652-75f65f98ab76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22291
82601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2229182601
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.265901948
Short name T155
Test name
Test status
Simulation time 195776162 ps
CPU time 0.84 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:01 PM PDT 24
Peak memory 206376 kb
Host smart-13adc6bf-7b7a-43b5-b3d2-d6a6a083245b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26590
1948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.265901948
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1255363628
Short name T150
Test name
Test status
Simulation time 172811419 ps
CPU time 0.8 seconds
Started Jul 11 06:00:56 PM PDT 24
Finished Jul 11 06:01:04 PM PDT 24
Peak memory 206388 kb
Host smart-792ad45b-057b-48d6-b7d7-bfda67e4c239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
63628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1255363628
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3707458203
Short name T2363
Test name
Test status
Simulation time 217976887 ps
CPU time 0.9 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206400 kb
Host smart-0fae10f8-4fa7-4251-8a89-0b2c00042e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37074
58203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3707458203
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3518094262
Short name T2815
Test name
Test status
Simulation time 329238429 ps
CPU time 3.49 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 206256 kb
Host smart-bcdce6ef-1c28-4949-9c69-2efe7ddbb1e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3518094262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3518094262
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1571700424
Short name T2841
Test name
Test status
Simulation time 1852376400 ps
CPU time 8.71 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:37:06 PM PDT 24
Peak memory 206260 kb
Host smart-6c5b31c9-7b50-4464-9030-52f8fb20c685
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1571700424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1571700424
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1851441104
Short name T2827
Test name
Test status
Simulation time 88760742 ps
CPU time 0.81 seconds
Started Jul 11 05:36:48 PM PDT 24
Finished Jul 11 05:36:53 PM PDT 24
Peak memory 206064 kb
Host smart-6555d595-4551-4862-b1b6-c8dca8112523
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1851441104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1851441104
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3285426417
Short name T2849
Test name
Test status
Simulation time 200496083 ps
CPU time 1.53 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 214584 kb
Host smart-869ac13c-895f-4b47-aad5-33d26cd0d17d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285426417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3285426417
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2152863753
Short name T273
Test name
Test status
Simulation time 49450475 ps
CPU time 1.01 seconds
Started Jul 11 05:36:53 PM PDT 24
Finished Jul 11 05:36:59 PM PDT 24
Peak memory 206272 kb
Host smart-1283feeb-95fa-4b57-a3dd-20e9add043a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2152863753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2152863753
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3544724718
Short name T2792
Test name
Test status
Simulation time 55076692 ps
CPU time 0.7 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:36:59 PM PDT 24
Peak memory 206020 kb
Host smart-2316065e-a53c-4c7e-b099-dd7fb2f5c1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3544724718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3544724718
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3473739689
Short name T2794
Test name
Test status
Simulation time 110706532 ps
CPU time 1.45 seconds
Started Jul 11 05:36:45 PM PDT 24
Finished Jul 11 05:36:49 PM PDT 24
Peak memory 215648 kb
Host smart-79111111-2578-4884-a127-2097b7c41556
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3473739689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3473739689
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.144267095
Short name T2745
Test name
Test status
Simulation time 104168406 ps
CPU time 2.48 seconds
Started Jul 11 05:37:19 PM PDT 24
Finished Jul 11 05:37:24 PM PDT 24
Peak memory 206160 kb
Host smart-c4284530-5766-432e-b64c-61ad232e0700
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=144267095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.144267095
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.324790630
Short name T2844
Test name
Test status
Simulation time 94586319 ps
CPU time 1.18 seconds
Started Jul 11 05:37:19 PM PDT 24
Finished Jul 11 05:37:22 PM PDT 24
Peak memory 206312 kb
Host smart-20f6613f-abf0-42ac-ba8d-1526a600b825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=324790630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.324790630
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3697396329
Short name T247
Test name
Test status
Simulation time 99208515 ps
CPU time 2.3 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 214612 kb
Host smart-e71da89d-e235-4cd9-af9f-e21857e45c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3697396329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3697396329
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1713833524
Short name T275
Test name
Test status
Simulation time 156409206 ps
CPU time 3.14 seconds
Started Jul 11 05:36:53 PM PDT 24
Finished Jul 11 05:37:01 PM PDT 24
Peak memory 206276 kb
Host smart-e4cefc30-35e2-47e1-a7bb-2ea35cfd3daf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1713833524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1713833524
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.763310039
Short name T269
Test name
Test status
Simulation time 662502807 ps
CPU time 4.27 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 206268 kb
Host smart-70a679cf-ae6a-4176-8a9b-4ae5ef9d268c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=763310039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.763310039
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.715936036
Short name T219
Test name
Test status
Simulation time 105970892 ps
CPU time 0.95 seconds
Started Jul 11 05:37:20 PM PDT 24
Finished Jul 11 05:37:24 PM PDT 24
Peak memory 206004 kb
Host smart-b3281018-9f9d-4d34-bc0c-99dfb6844ece
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=715936036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.715936036
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3196869562
Short name T2803
Test name
Test status
Simulation time 100486477 ps
CPU time 1.29 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 214540 kb
Host smart-2d3d22b2-921f-4322-882e-bf7a9d128901
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196869562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3196869562
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2455140284
Short name T288
Test name
Test status
Simulation time 43347671 ps
CPU time 0.79 seconds
Started Jul 11 05:37:05 PM PDT 24
Finished Jul 11 05:37:07 PM PDT 24
Peak memory 206064 kb
Host smart-844b7c4e-2597-4244-9ee4-35fe9396c2f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2455140284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2455140284
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2573283805
Short name T276
Test name
Test status
Simulation time 67216666 ps
CPU time 1.4 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 222652 kb
Host smart-04a4bbbb-73aa-489c-9617-d5bd34e87e5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2573283805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2573283805
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1657951033
Short name T2752
Test name
Test status
Simulation time 262257383 ps
CPU time 2.38 seconds
Started Jul 11 05:36:51 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 206244 kb
Host smart-cc879fef-c4c2-46b9-b6e6-2408946f438a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1657951033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1657951033
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.696047557
Short name T2850
Test name
Test status
Simulation time 288113395 ps
CPU time 1.74 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 206292 kb
Host smart-c50326cb-70b8-47a6-bd0e-1bf4f3173a94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=696047557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.696047557
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2689946490
Short name T2787
Test name
Test status
Simulation time 74480476 ps
CPU time 1.45 seconds
Started Jul 11 05:36:44 PM PDT 24
Finished Jul 11 05:36:48 PM PDT 24
Peak memory 206412 kb
Host smart-54ed4c7f-8e12-4d32-8a3b-8b14c1bc0ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2689946490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2689946490
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3157924688
Short name T252
Test name
Test status
Simulation time 88401258 ps
CPU time 1.15 seconds
Started Jul 11 05:37:06 PM PDT 24
Finished Jul 11 05:37:09 PM PDT 24
Peak memory 216116 kb
Host smart-603493ef-987b-455e-aaa9-7db4889e5568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157924688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3157924688
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.118797392
Short name T2838
Test name
Test status
Simulation time 69538321 ps
CPU time 0.96 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:10 PM PDT 24
Peak memory 206132 kb
Host smart-4614815e-d2cf-487d-9ea4-a35aed234d92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=118797392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.118797392
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2325090852
Short name T2826
Test name
Test status
Simulation time 43874212 ps
CPU time 0.67 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:09 PM PDT 24
Peak memory 205956 kb
Host smart-cb62b239-5928-4889-b6ef-b138c7b76a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2325090852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2325090852
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.132382581
Short name T2759
Test name
Test status
Simulation time 90212146 ps
CPU time 1.08 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:10 PM PDT 24
Peak memory 206152 kb
Host smart-ff04653d-eb22-434a-afb8-3fec4be3f381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=132382581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.132382581
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3448808434
Short name T2782
Test name
Test status
Simulation time 229713417 ps
CPU time 2.73 seconds
Started Jul 11 05:37:05 PM PDT 24
Finished Jul 11 05:37:09 PM PDT 24
Peak memory 214440 kb
Host smart-86db8e71-fa75-4e41-840e-8bbab3ec8b01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3448808434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3448808434
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1599880582
Short name T2822
Test name
Test status
Simulation time 561092184 ps
CPU time 3 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:09 PM PDT 24
Peak memory 205420 kb
Host smart-7841d386-d63f-441b-b752-3631a0181d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1599880582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1599880582
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.465263996
Short name T2786
Test name
Test status
Simulation time 248741418 ps
CPU time 2.16 seconds
Started Jul 11 05:48:16 PM PDT 24
Finished Jul 11 05:48:23 PM PDT 24
Peak memory 214556 kb
Host smart-cc42a371-cee1-44c0-b112-028330865b77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465263996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.465263996
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3945264870
Short name T2833
Test name
Test status
Simulation time 58691499 ps
CPU time 1.02 seconds
Started Jul 11 05:36:59 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 206408 kb
Host smart-29a4ab5d-1d9f-4869-b702-3a7670208240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3945264870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3945264870
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2154081203
Short name T2778
Test name
Test status
Simulation time 55762930 ps
CPU time 0.69 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:10 PM PDT 24
Peak memory 206040 kb
Host smart-721fc316-b1be-43b1-9b8b-16395b218a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2154081203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2154081203
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4018374310
Short name T2796
Test name
Test status
Simulation time 93302106 ps
CPU time 1.13 seconds
Started Jul 11 05:37:01 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 206372 kb
Host smart-1290a407-268b-4f3e-9a49-dad2a59a910b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4018374310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.4018374310
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3045446209
Short name T2820
Test name
Test status
Simulation time 152556134 ps
CPU time 1.68 seconds
Started Jul 11 05:37:10 PM PDT 24
Finished Jul 11 05:37:13 PM PDT 24
Peak memory 222012 kb
Host smart-d2b9a6f3-bd56-40dd-965f-965d5511fd99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3045446209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3045446209
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.994857176
Short name T311
Test name
Test status
Simulation time 1640774925 ps
CPU time 5.52 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:14 PM PDT 24
Peak memory 206232 kb
Host smart-78f8595d-b7b8-49a1-b02f-7af97dbc8a56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=994857176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.994857176
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3968040167
Short name T2748
Test name
Test status
Simulation time 101673671 ps
CPU time 2.19 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:09 PM PDT 24
Peak memory 214532 kb
Host smart-45cfa60e-0d27-4248-b7ec-0f0d36c71da0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968040167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3968040167
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1313036305
Short name T291
Test name
Test status
Simulation time 70055946 ps
CPU time 0.67 seconds
Started Jul 11 05:38:14 PM PDT 24
Finished Jul 11 05:38:16 PM PDT 24
Peak memory 205784 kb
Host smart-11797f3c-4488-459b-8874-5b07bbea8b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1313036305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1313036305
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.17973256
Short name T236
Test name
Test status
Simulation time 156115360 ps
CPU time 1.13 seconds
Started Jul 11 05:38:17 PM PDT 24
Finished Jul 11 05:38:20 PM PDT 24
Peak memory 206304 kb
Host smart-8e76ad5d-dcdc-46e2-93e6-d3044cb2d1fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=17973256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.17973256
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.52672103
Short name T240
Test name
Test status
Simulation time 85338390 ps
CPU time 1.62 seconds
Started Jul 11 05:37:06 PM PDT 24
Finished Jul 11 05:37:08 PM PDT 24
Peak memory 206400 kb
Host smart-81540182-428c-4e4f-8125-205076f726ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=52672103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.52672103
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4072790506
Short name T2791
Test name
Test status
Simulation time 855773550 ps
CPU time 5.11 seconds
Started Jul 11 05:38:06 PM PDT 24
Finished Jul 11 05:38:13 PM PDT 24
Peak memory 206312 kb
Host smart-1e326c22-88ec-46db-b80b-96f8b8a1164e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4072790506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.4072790506
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1108958500
Short name T207
Test name
Test status
Simulation time 103869062 ps
CPU time 2.45 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:08 PM PDT 24
Peak memory 214584 kb
Host smart-dc8d0639-c398-423e-a78b-3939fabb1c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108958500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1108958500
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.11649782
Short name T274
Test name
Test status
Simulation time 89018166 ps
CPU time 0.81 seconds
Started Jul 11 05:38:13 PM PDT 24
Finished Jul 11 05:38:14 PM PDT 24
Peak memory 206064 kb
Host smart-d70888a2-28ca-486a-af67-a1cba6fd5880
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=11649782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.11649782
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2590495357
Short name T2784
Test name
Test status
Simulation time 46337579 ps
CPU time 0.69 seconds
Started Jul 11 05:38:06 PM PDT 24
Finished Jul 11 05:38:09 PM PDT 24
Peak memory 206012 kb
Host smart-03ebca53-b732-4cd8-83e0-66c459c339a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2590495357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2590495357
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2097583133
Short name T2790
Test name
Test status
Simulation time 197949717 ps
CPU time 1.75 seconds
Started Jul 11 05:38:14 PM PDT 24
Finished Jul 11 05:38:17 PM PDT 24
Peak memory 206300 kb
Host smart-e122dac1-ff54-4a41-a4b8-7e7fcc952b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2097583133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2097583133
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3360589350
Short name T241
Test name
Test status
Simulation time 118248518 ps
CPU time 2.87 seconds
Started Jul 11 05:38:17 PM PDT 24
Finished Jul 11 05:38:21 PM PDT 24
Peak memory 214600 kb
Host smart-173dbcc4-6a1f-402f-a06a-11c2dad7bf95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3360589350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3360589350
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2253683178
Short name T2776
Test name
Test status
Simulation time 156906950 ps
CPU time 1.66 seconds
Started Jul 11 05:38:13 PM PDT 24
Finished Jul 11 05:38:16 PM PDT 24
Peak memory 214556 kb
Host smart-439e934e-0bdf-434e-9ff5-13b62e12c55f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253683178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2253683178
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3378619431
Short name T2806
Test name
Test status
Simulation time 61683661 ps
CPU time 0.88 seconds
Started Jul 11 05:38:02 PM PDT 24
Finished Jul 11 05:38:04 PM PDT 24
Peak memory 206020 kb
Host smart-dba2c6b3-b872-47a1-b0f9-e6c764a47ac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3378619431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3378619431
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.931075504
Short name T303
Test name
Test status
Simulation time 45499776 ps
CPU time 0.67 seconds
Started Jul 11 05:38:13 PM PDT 24
Finished Jul 11 05:38:15 PM PDT 24
Peak memory 206008 kb
Host smart-4d08ac77-e3f9-49d4-8539-249c171bf875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=931075504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.931075504
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2874369037
Short name T2751
Test name
Test status
Simulation time 343812331 ps
CPU time 1.84 seconds
Started Jul 11 05:38:15 PM PDT 24
Finished Jul 11 05:38:18 PM PDT 24
Peak memory 206328 kb
Host smart-b6965d0b-015c-46f2-8fa5-e9251e62baf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2874369037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2874369037
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.870225705
Short name T2750
Test name
Test status
Simulation time 238875408 ps
CPU time 2.72 seconds
Started Jul 11 05:38:14 PM PDT 24
Finished Jul 11 05:38:18 PM PDT 24
Peak memory 206428 kb
Host smart-1d967eac-d022-4d20-9c3f-6fd79b506598
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=870225705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.870225705
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1996037843
Short name T2805
Test name
Test status
Simulation time 382821104 ps
CPU time 3.01 seconds
Started Jul 11 05:38:06 PM PDT 24
Finished Jul 11 05:38:11 PM PDT 24
Peak memory 206360 kb
Host smart-4188f80a-d947-487d-aa16-95bbd53c31f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1996037843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1996037843
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1714990114
Short name T2852
Test name
Test status
Simulation time 108716812 ps
CPU time 1.24 seconds
Started Jul 11 05:38:05 PM PDT 24
Finished Jul 11 05:38:08 PM PDT 24
Peak memory 214444 kb
Host smart-11c45ac7-173a-4a49-8690-e1147c5beb1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714990114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1714990114
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2218206930
Short name T2755
Test name
Test status
Simulation time 111070108 ps
CPU time 0.92 seconds
Started Jul 11 05:38:02 PM PDT 24
Finished Jul 11 05:38:04 PM PDT 24
Peak memory 206020 kb
Host smart-e326c0b2-2b68-49fb-90ef-0b1db310d4fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2218206930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2218206930
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1124989976
Short name T282
Test name
Test status
Simulation time 294077739 ps
CPU time 1.65 seconds
Started Jul 11 05:38:06 PM PDT 24
Finished Jul 11 05:38:10 PM PDT 24
Peak memory 206320 kb
Host smart-04076840-3605-45fb-88e5-840f8cfa2979
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1124989976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1124989976
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2316268712
Short name T2829
Test name
Test status
Simulation time 52068676 ps
CPU time 1.3 seconds
Started Jul 11 05:38:15 PM PDT 24
Finished Jul 11 05:38:17 PM PDT 24
Peak memory 221936 kb
Host smart-5d242a9b-ed6b-410a-bcd0-6486d252162e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2316268712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2316268712
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2466861851
Short name T290
Test name
Test status
Simulation time 555852221 ps
CPU time 3.18 seconds
Started Jul 11 05:38:06 PM PDT 24
Finished Jul 11 05:38:12 PM PDT 24
Peak memory 206372 kb
Host smart-5325bc4e-41ba-4f78-8f6c-b31758b669ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2466861851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2466861851
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1995825707
Short name T210
Test name
Test status
Simulation time 109461050 ps
CPU time 1.41 seconds
Started Jul 11 05:38:05 PM PDT 24
Finished Jul 11 05:38:09 PM PDT 24
Peak memory 214544 kb
Host smart-6a5be98b-3991-40d7-aabc-35bab6e1773b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995825707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1995825707
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.641189290
Short name T2843
Test name
Test status
Simulation time 79475054 ps
CPU time 1.04 seconds
Started Jul 11 05:38:15 PM PDT 24
Finished Jul 11 05:38:17 PM PDT 24
Peak memory 206216 kb
Host smart-9afc618d-0d46-43d3-8b77-11c5e3084af7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=641189290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.641189290
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.703630096
Short name T299
Test name
Test status
Simulation time 44313303 ps
CPU time 0.69 seconds
Started Jul 11 05:38:18 PM PDT 24
Finished Jul 11 05:38:19 PM PDT 24
Peak memory 205976 kb
Host smart-8b6f1b30-91bc-4bdb-9631-908ea4c16bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=703630096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.703630096
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2393908233
Short name T281
Test name
Test status
Simulation time 210001205 ps
CPU time 1.78 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:08 PM PDT 24
Peak memory 206300 kb
Host smart-7c97b960-cc34-42f8-b2a4-72fe7475194d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2393908233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2393908233
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.753890446
Short name T289
Test name
Test status
Simulation time 492759578 ps
CPU time 3.17 seconds
Started Jul 11 05:38:15 PM PDT 24
Finished Jul 11 05:38:20 PM PDT 24
Peak memory 206316 kb
Host smart-1a1e990c-6daa-43bd-ad36-c15f79e97750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=753890446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.753890446
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3314562977
Short name T2811
Test name
Test status
Simulation time 192764487 ps
CPU time 1.78 seconds
Started Jul 11 05:38:31 PM PDT 24
Finished Jul 11 05:38:34 PM PDT 24
Peak memory 218092 kb
Host smart-e67ba38b-71bb-4971-b7e5-11803db15e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314562977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3314562977
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4277884947
Short name T2785
Test name
Test status
Simulation time 88187124 ps
CPU time 1.03 seconds
Started Jul 11 05:38:07 PM PDT 24
Finished Jul 11 05:38:10 PM PDT 24
Peak memory 206296 kb
Host smart-cf73b027-8372-4334-8bd1-92bf46935d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4277884947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4277884947
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2534906453
Short name T305
Test name
Test status
Simulation time 94774155 ps
CPU time 0.7 seconds
Started Jul 11 05:38:15 PM PDT 24
Finished Jul 11 05:38:17 PM PDT 24
Peak memory 206040 kb
Host smart-f49ec8c3-8f7c-4739-9adf-81db482113e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2534906453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2534906453
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2901402299
Short name T2754
Test name
Test status
Simulation time 182597981 ps
CPU time 1.25 seconds
Started Jul 11 05:38:30 PM PDT 24
Finished Jul 11 05:38:33 PM PDT 24
Peak memory 206400 kb
Host smart-ea62021a-5e4d-43b4-8754-08ce423904a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2901402299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2901402299
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1742455440
Short name T2773
Test name
Test status
Simulation time 266288962 ps
CPU time 2.61 seconds
Started Jul 11 05:38:17 PM PDT 24
Finished Jul 11 05:38:21 PM PDT 24
Peak memory 222584 kb
Host smart-84d277ab-2fdd-49f2-8f72-f617d3a5a1b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1742455440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1742455440
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4073748924
Short name T234
Test name
Test status
Simulation time 1079876438 ps
CPU time 4 seconds
Started Jul 11 05:38:31 PM PDT 24
Finished Jul 11 05:38:36 PM PDT 24
Peak memory 206372 kb
Host smart-19bbf9fe-2b6c-4a0e-8223-e8473dea2224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4073748924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.4073748924
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3410537464
Short name T2780
Test name
Test status
Simulation time 181363371 ps
CPU time 1.34 seconds
Started Jul 11 05:38:15 PM PDT 24
Finished Jul 11 05:38:18 PM PDT 24
Peak memory 214628 kb
Host smart-99191526-b133-4d56-a8b4-0793d7914545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410537464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3410537464
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1492413007
Short name T2761
Test name
Test status
Simulation time 105191303 ps
CPU time 0.79 seconds
Started Jul 11 05:38:26 PM PDT 24
Finished Jul 11 05:38:28 PM PDT 24
Peak memory 205948 kb
Host smart-5e90017a-0753-4a0b-aa3d-ec6c1120c14b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1492413007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1492413007
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4195318420
Short name T2795
Test name
Test status
Simulation time 44220130 ps
CPU time 0.7 seconds
Started Jul 11 05:38:31 PM PDT 24
Finished Jul 11 05:38:33 PM PDT 24
Peak memory 205952 kb
Host smart-86597beb-ed5b-40d8-9080-911c9f674700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4195318420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4195318420
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.142851542
Short name T283
Test name
Test status
Simulation time 96938601 ps
CPU time 1.05 seconds
Started Jul 11 05:38:27 PM PDT 24
Finished Jul 11 05:38:29 PM PDT 24
Peak memory 206204 kb
Host smart-f3b86cd2-c0f0-4ad4-bdfd-bf617abbd149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=142851542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.142851542
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.943126972
Short name T314
Test name
Test status
Simulation time 490612562 ps
CPU time 3.94 seconds
Started Jul 11 05:38:15 PM PDT 24
Finished Jul 11 05:38:21 PM PDT 24
Peak memory 206368 kb
Host smart-606ad344-9bd7-497a-95c5-7c92e29071b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=943126972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.943126972
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1853715174
Short name T2766
Test name
Test status
Simulation time 114785764 ps
CPU time 1.67 seconds
Started Jul 11 05:38:26 PM PDT 24
Finished Jul 11 05:38:28 PM PDT 24
Peak memory 214468 kb
Host smart-035bbbed-1afe-4d13-a481-8863ef9205e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853715174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1853715174
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2718968869
Short name T277
Test name
Test status
Simulation time 77808608 ps
CPU time 0.86 seconds
Started Jul 11 05:38:30 PM PDT 24
Finished Jul 11 05:38:32 PM PDT 24
Peak memory 206004 kb
Host smart-cbbd2e52-677f-4a61-9629-11f6be80732d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2718968869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2718968869
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.807607000
Short name T2793
Test name
Test status
Simulation time 45627747 ps
CPU time 0.68 seconds
Started Jul 11 05:38:31 PM PDT 24
Finished Jul 11 05:38:33 PM PDT 24
Peak memory 206008 kb
Host smart-fdf3fd99-c6a7-450d-a269-c6e21bf34a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=807607000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.807607000
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3731483304
Short name T284
Test name
Test status
Simulation time 109113334 ps
CPU time 1.63 seconds
Started Jul 11 05:38:30 PM PDT 24
Finished Jul 11 05:38:33 PM PDT 24
Peak memory 205628 kb
Host smart-4833858a-307f-4a9d-a1fa-f229d15c42a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3731483304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3731483304
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.98280317
Short name T2788
Test name
Test status
Simulation time 104276346 ps
CPU time 2.72 seconds
Started Jul 11 05:38:26 PM PDT 24
Finished Jul 11 05:38:29 PM PDT 24
Peak memory 222616 kb
Host smart-56b1006e-ab45-40f5-ab38-4abc0773e4d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=98280317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.98280317
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1296837112
Short name T2777
Test name
Test status
Simulation time 486939493 ps
CPU time 4.67 seconds
Started Jul 11 05:38:30 PM PDT 24
Finished Jul 11 05:38:36 PM PDT 24
Peak memory 206336 kb
Host smart-d742bed9-a06a-443e-9d62-5cf09fc434ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1296837112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1296837112
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4233188252
Short name T2845
Test name
Test status
Simulation time 362645345 ps
CPU time 3.65 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 206292 kb
Host smart-9e839288-492c-49a7-a902-f48229a95ee1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4233188252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.4233188252
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.335927048
Short name T2746
Test name
Test status
Simulation time 639308998 ps
CPU time 4.19 seconds
Started Jul 11 05:37:20 PM PDT 24
Finished Jul 11 05:37:28 PM PDT 24
Peak memory 206012 kb
Host smart-613060e6-b1a0-4982-9675-02f48843555f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=335927048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.335927048
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4163510641
Short name T2813
Test name
Test status
Simulation time 42701705 ps
CPU time 0.73 seconds
Started Jul 11 05:36:55 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 206032 kb
Host smart-f8d2fe7f-aaaa-401b-baf7-340556a2a785
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4163510641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.4163510641
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.791531969
Short name T2764
Test name
Test status
Simulation time 190801539 ps
CPU time 1.82 seconds
Started Jul 11 05:36:53 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 214616 kb
Host smart-cb1bc013-732e-4846-b60d-b267ccddf48f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791531969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.791531969
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2453284016
Short name T2819
Test name
Test status
Simulation time 53853775 ps
CPU time 0.84 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:10 PM PDT 24
Peak memory 206064 kb
Host smart-1b162992-4473-4320-b13a-1d6b76ed10d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2453284016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2453284016
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.654189933
Short name T2825
Test name
Test status
Simulation time 42155520 ps
CPU time 0.64 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 206008 kb
Host smart-1b9de969-4eee-4440-8ecd-2eca1a49dc9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=654189933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.654189933
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1949150968
Short name T278
Test name
Test status
Simulation time 86985011 ps
CPU time 1.35 seconds
Started Jul 11 05:36:51 PM PDT 24
Finished Jul 11 05:36:57 PM PDT 24
Peak memory 215780 kb
Host smart-deb9eb78-788c-41bb-8802-eb9a34b486a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1949150968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1949150968
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1424841443
Short name T2768
Test name
Test status
Simulation time 488398140 ps
CPU time 4.19 seconds
Started Jul 11 05:37:36 PM PDT 24
Finished Jul 11 05:37:41 PM PDT 24
Peak memory 206232 kb
Host smart-cf21cb8b-04cc-4ef8-b9a5-05f97cd8113b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1424841443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1424841443
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.657538169
Short name T2836
Test name
Test status
Simulation time 116679677 ps
CPU time 1.2 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 206292 kb
Host smart-1e209fb2-199f-4ff3-8532-b6d1429f80c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=657538169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.657538169
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1025754448
Short name T2817
Test name
Test status
Simulation time 171555262 ps
CPU time 2.17 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:36:59 PM PDT 24
Peak memory 206400 kb
Host smart-34f555c8-6df9-46d3-afd5-995b7426d739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1025754448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1025754448
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2292010425
Short name T2804
Test name
Test status
Simulation time 498145842 ps
CPU time 2.83 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:36:59 PM PDT 24
Peak memory 206360 kb
Host smart-7e729db6-5cbd-48ea-a420-72e16e187c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2292010425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2292010425
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1223778519
Short name T2846
Test name
Test status
Simulation time 57482891 ps
CPU time 0.71 seconds
Started Jul 11 05:38:32 PM PDT 24
Finished Jul 11 05:38:34 PM PDT 24
Peak memory 206008 kb
Host smart-4bf7f1dd-6885-4dea-b9f6-5e5b83e415fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1223778519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1223778519
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2968453399
Short name T2828
Test name
Test status
Simulation time 42120040 ps
CPU time 0.67 seconds
Started Jul 11 05:38:15 PM PDT 24
Finished Jul 11 05:38:17 PM PDT 24
Peak memory 206008 kb
Host smart-e2b5d166-cc46-41b6-b354-d2a639e1549f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2968453399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2968453399
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2930643761
Short name T2798
Test name
Test status
Simulation time 47115242 ps
CPU time 0.68 seconds
Started Jul 11 05:38:26 PM PDT 24
Finished Jul 11 05:38:28 PM PDT 24
Peak memory 205928 kb
Host smart-f6dcf237-7f2b-479b-86b2-1bf5eee7eccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2930643761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2930643761
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.70118706
Short name T2816
Test name
Test status
Simulation time 36578555 ps
CPU time 0.68 seconds
Started Jul 11 05:38:32 PM PDT 24
Finished Jul 11 05:38:34 PM PDT 24
Peak memory 206008 kb
Host smart-22438981-efa2-4ecf-b6aa-ddbe99b06cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=70118706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.70118706
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1937896598
Short name T2781
Test name
Test status
Simulation time 44883558 ps
CPU time 0.69 seconds
Started Jul 11 05:38:47 PM PDT 24
Finished Jul 11 05:38:48 PM PDT 24
Peak memory 206008 kb
Host smart-f79a552d-304a-44b4-9136-954f2f71f2b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1937896598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1937896598
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2709481669
Short name T293
Test name
Test status
Simulation time 58347125 ps
CPU time 0.71 seconds
Started Jul 11 05:38:30 PM PDT 24
Finished Jul 11 05:38:32 PM PDT 24
Peak memory 205228 kb
Host smart-c922ba8c-0520-4b72-8f18-e272bf66d758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2709481669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2709481669
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1078560297
Short name T297
Test name
Test status
Simulation time 117144008 ps
CPU time 0.73 seconds
Started Jul 11 05:38:32 PM PDT 24
Finished Jul 11 05:38:34 PM PDT 24
Peak memory 206008 kb
Host smart-a215f8cd-5d9e-4163-b7f4-2e12260304b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1078560297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1078560297
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.667754805
Short name T2837
Test name
Test status
Simulation time 62148667 ps
CPU time 0.72 seconds
Started Jul 11 05:38:32 PM PDT 24
Finished Jul 11 05:38:34 PM PDT 24
Peak memory 206008 kb
Host smart-4c915edd-bb07-41b0-8f70-6efb3ff8cd64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=667754805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.667754805
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2001689300
Short name T2823
Test name
Test status
Simulation time 56741828 ps
CPU time 0.67 seconds
Started Jul 11 05:38:16 PM PDT 24
Finished Jul 11 05:38:18 PM PDT 24
Peak memory 206004 kb
Host smart-c0912852-ccc5-428f-b35f-d48a951aeb44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2001689300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2001689300
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3906485142
Short name T2821
Test name
Test status
Simulation time 43677690 ps
CPU time 0.65 seconds
Started Jul 11 05:38:21 PM PDT 24
Finished Jul 11 05:38:23 PM PDT 24
Peak memory 206008 kb
Host smart-f97990a7-45f4-4ebb-b41d-3180739232cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3906485142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3906485142
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.867504374
Short name T235
Test name
Test status
Simulation time 84347196 ps
CPU time 1.96 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:57 PM PDT 24
Peak memory 206280 kb
Host smart-ad01f347-8f6e-43a9-9208-8ba0e1cde072
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=867504374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.867504374
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4181366348
Short name T2834
Test name
Test status
Simulation time 1818327225 ps
CPU time 9.32 seconds
Started Jul 11 05:37:20 PM PDT 24
Finished Jul 11 05:37:33 PM PDT 24
Peak memory 206064 kb
Host smart-00de76c1-8ec4-48a6-8e4d-461882822f53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4181366348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.4181366348
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2513123692
Short name T2762
Test name
Test status
Simulation time 76519912 ps
CPU time 0.84 seconds
Started Jul 11 05:37:20 PM PDT 24
Finished Jul 11 05:37:24 PM PDT 24
Peak memory 205972 kb
Host smart-d029fb15-4f32-41a3-9cf0-b17d54c91d2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2513123692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2513123692
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2779463282
Short name T268
Test name
Test status
Simulation time 59969056 ps
CPU time 0.89 seconds
Started Jul 11 05:37:01 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 206024 kb
Host smart-e3718759-7549-4712-ad54-93c0f5a3ae09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2779463282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2779463282
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1935679780
Short name T217
Test name
Test status
Simulation time 34926396 ps
CPU time 0.65 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 206004 kb
Host smart-0ef153ef-ae6d-4ef6-a3e7-ffaf4f34ef7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1935679780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1935679780
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2026937346
Short name T272
Test name
Test status
Simulation time 164542089 ps
CPU time 2.29 seconds
Started Jul 11 05:36:53 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 214432 kb
Host smart-093349a4-60f5-4b6b-9d30-fe9dc38bf475
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2026937346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2026937346
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.4014650548
Short name T2749
Test name
Test status
Simulation time 173218806 ps
CPU time 4.01 seconds
Started Jul 11 05:36:55 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 206292 kb
Host smart-c8f8c326-2151-49c0-816f-fcb56a5208df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4014650548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.4014650548
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1031697841
Short name T2839
Test name
Test status
Simulation time 101759818 ps
CPU time 1.05 seconds
Started Jul 11 05:36:51 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 206280 kb
Host smart-0d89782b-5321-43a4-93bd-062414425fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1031697841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1031697841
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3226486799
Short name T246
Test name
Test status
Simulation time 230140751 ps
CPU time 2.75 seconds
Started Jul 11 05:37:20 PM PDT 24
Finished Jul 11 05:37:26 PM PDT 24
Peak memory 221984 kb
Host smart-be162beb-18e4-4502-ad8e-046c311305cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3226486799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3226486799
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.73021682
Short name T2758
Test name
Test status
Simulation time 772121827 ps
CPU time 3.54 seconds
Started Jul 11 05:36:52 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 206516 kb
Host smart-ed71a537-8b20-4409-b604-510b004b7d59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=73021682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.73021682
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3934613573
Short name T306
Test name
Test status
Simulation time 36903464 ps
CPU time 0.68 seconds
Started Jul 11 05:38:56 PM PDT 24
Finished Jul 11 05:38:58 PM PDT 24
Peak memory 205908 kb
Host smart-8110d89d-d5a1-42cb-9ea3-8f625a193269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3934613573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3934613573
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.738844106
Short name T2814
Test name
Test status
Simulation time 46337065 ps
CPU time 0.7 seconds
Started Jul 11 05:38:18 PM PDT 24
Finished Jul 11 05:38:20 PM PDT 24
Peak memory 206004 kb
Host smart-6e2eedac-4734-41c8-b7bf-8121d73c339f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=738844106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.738844106
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2794358190
Short name T2810
Test name
Test status
Simulation time 48072387 ps
CPU time 0.71 seconds
Started Jul 11 05:38:56 PM PDT 24
Finished Jul 11 05:38:59 PM PDT 24
Peak memory 205940 kb
Host smart-189e57bb-57d4-49c6-acfb-77d6ada5995b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2794358190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2794358190
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1627183257
Short name T292
Test name
Test status
Simulation time 56445881 ps
CPU time 0.72 seconds
Started Jul 11 05:38:58 PM PDT 24
Finished Jul 11 05:39:00 PM PDT 24
Peak memory 205972 kb
Host smart-04da0167-47f2-4b4b-be42-f8f707d3c373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1627183257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1627183257
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3401118387
Short name T300
Test name
Test status
Simulation time 59086662 ps
CPU time 0.73 seconds
Started Jul 11 05:38:38 PM PDT 24
Finished Jul 11 05:38:40 PM PDT 24
Peak memory 206012 kb
Host smart-6b9fa044-ae55-4594-9935-2ea3a78865a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3401118387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3401118387
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1019467678
Short name T2835
Test name
Test status
Simulation time 43251291 ps
CPU time 0.65 seconds
Started Jul 11 05:38:28 PM PDT 24
Finished Jul 11 05:38:30 PM PDT 24
Peak memory 206012 kb
Host smart-7dcdee11-988c-48ec-80c1-bbf4af2d260a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1019467678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1019467678
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3384444725
Short name T304
Test name
Test status
Simulation time 74210545 ps
CPU time 0.74 seconds
Started Jul 11 05:38:29 PM PDT 24
Finished Jul 11 05:38:31 PM PDT 24
Peak memory 205972 kb
Host smart-5af08161-d38f-496e-abea-9ae99ce57854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3384444725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3384444725
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1871925545
Short name T2801
Test name
Test status
Simulation time 41555968 ps
CPU time 0.68 seconds
Started Jul 11 05:38:29 PM PDT 24
Finished Jul 11 05:38:30 PM PDT 24
Peak memory 206012 kb
Host smart-77938486-d458-4f57-8881-12286e3ea76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1871925545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1871925545
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3629032778
Short name T2747
Test name
Test status
Simulation time 136541165 ps
CPU time 3.42 seconds
Started Jul 11 05:37:00 PM PDT 24
Finished Jul 11 05:37:06 PM PDT 24
Peak memory 206296 kb
Host smart-54731873-da5c-4db7-9fba-71538fe7c398
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3629032778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3629032778
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2245052701
Short name T2753
Test name
Test status
Simulation time 1012341201 ps
CPU time 7.37 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:08 PM PDT 24
Peak memory 206240 kb
Host smart-619581da-b957-48e8-b7bb-27bb0a349d55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2245052701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2245052701
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3811302524
Short name T2799
Test name
Test status
Simulation time 75099195 ps
CPU time 0.85 seconds
Started Jul 11 05:36:51 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 206184 kb
Host smart-d4f7f9ad-88ea-4b98-aeff-e9fd0f4d170f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3811302524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3811302524
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2530307161
Short name T2769
Test name
Test status
Simulation time 206949326 ps
CPU time 1.98 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:07 PM PDT 24
Peak memory 214532 kb
Host smart-54ab64a2-1436-4f55-a8a1-27fe1a2e53b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530307161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2530307161
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2116131069
Short name T2760
Test name
Test status
Simulation time 48639844 ps
CPU time 0.81 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:00 PM PDT 24
Peak memory 206032 kb
Host smart-ff468e59-1fcf-46a1-86b3-1c6fb95f87db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2116131069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2116131069
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3928869268
Short name T308
Test name
Test status
Simulation time 98735344 ps
CPU time 0.79 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:10 PM PDT 24
Peak memory 206008 kb
Host smart-57e5ced5-9892-40e5-9cbc-82be790ca88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3928869268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3928869268
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.658694890
Short name T279
Test name
Test status
Simulation time 95095266 ps
CPU time 1.48 seconds
Started Jul 11 05:37:20 PM PDT 24
Finished Jul 11 05:37:25 PM PDT 24
Peak memory 222500 kb
Host smart-1362bc65-e655-4f5b-8965-4aaa4a050d25
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=658694890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.658694890
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4170544768
Short name T2831
Test name
Test status
Simulation time 424911769 ps
CPU time 2.86 seconds
Started Jul 11 05:37:00 PM PDT 24
Finished Jul 11 05:37:06 PM PDT 24
Peak memory 206184 kb
Host smart-c0d0f10f-ca5c-406a-b217-b1ac6b9247b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4170544768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.4170544768
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1645118612
Short name T280
Test name
Test status
Simulation time 129539741 ps
CPU time 1.5 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:08 PM PDT 24
Peak memory 206308 kb
Host smart-d3a77107-f28c-433c-ad87-e1d816ecd866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1645118612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1645118612
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4164268039
Short name T245
Test name
Test status
Simulation time 211494428 ps
CPU time 1.99 seconds
Started Jul 11 05:37:20 PM PDT 24
Finished Jul 11 05:37:25 PM PDT 24
Peak memory 206368 kb
Host smart-0e6757d8-b531-4e0e-9574-24bcbfdd4c32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4164268039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.4164268039
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.60110099
Short name T315
Test name
Test status
Simulation time 505538477 ps
CPU time 4.22 seconds
Started Jul 11 05:36:50 PM PDT 24
Finished Jul 11 05:36:59 PM PDT 24
Peak memory 206372 kb
Host smart-a8c3b7b8-fa99-49da-9d7f-6cd179f360bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=60110099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.60110099
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4012582300
Short name T2818
Test name
Test status
Simulation time 29879536 ps
CPU time 0.68 seconds
Started Jul 11 05:38:29 PM PDT 24
Finished Jul 11 05:38:31 PM PDT 24
Peak memory 205976 kb
Host smart-44cafb56-e92a-4509-8af4-1f183f8e961a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4012582300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.4012582300
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3398816151
Short name T2851
Test name
Test status
Simulation time 62564220 ps
CPU time 0.7 seconds
Started Jul 11 05:38:29 PM PDT 24
Finished Jul 11 05:38:30 PM PDT 24
Peak memory 206008 kb
Host smart-1de3a996-2bc5-4e7c-939c-aaa276ed212b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3398816151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3398816151
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.669699307
Short name T2797
Test name
Test status
Simulation time 45723951 ps
CPU time 0.64 seconds
Started Jul 11 05:39:17 PM PDT 24
Finished Jul 11 05:39:18 PM PDT 24
Peak memory 205968 kb
Host smart-e005b96b-36d4-432e-9df4-37f81e723dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=669699307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.669699307
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3409369180
Short name T309
Test name
Test status
Simulation time 55560098 ps
CPU time 0.68 seconds
Started Jul 11 05:38:50 PM PDT 24
Finished Jul 11 05:38:51 PM PDT 24
Peak memory 206012 kb
Host smart-a3ae0a82-0a41-48b9-941b-662c74ce5e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3409369180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3409369180
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2122830292
Short name T2802
Test name
Test status
Simulation time 38380130 ps
CPU time 0.68 seconds
Started Jul 11 05:39:00 PM PDT 24
Finished Jul 11 05:39:02 PM PDT 24
Peak memory 206012 kb
Host smart-605ae1c2-3ca1-4372-876c-2611635d8d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2122830292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2122830292
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3063976258
Short name T298
Test name
Test status
Simulation time 64954695 ps
CPU time 0.69 seconds
Started Jul 11 05:38:58 PM PDT 24
Finished Jul 11 05:39:00 PM PDT 24
Peak memory 205944 kb
Host smart-a39b846f-c643-4fa8-831a-6b8d02177550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3063976258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3063976258
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.773260580
Short name T2812
Test name
Test status
Simulation time 41940567 ps
CPU time 0.7 seconds
Started Jul 11 05:38:51 PM PDT 24
Finished Jul 11 05:38:53 PM PDT 24
Peak memory 206004 kb
Host smart-de3d2957-6d94-44f4-aa4e-6d1abd0b61ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=773260580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.773260580
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.813209481
Short name T2772
Test name
Test status
Simulation time 49703770 ps
CPU time 0.7 seconds
Started Jul 11 05:39:00 PM PDT 24
Finished Jul 11 05:39:02 PM PDT 24
Peak memory 206008 kb
Host smart-a0c44c33-ef5f-47d1-bd13-77493287d4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=813209481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.813209481
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2894206328
Short name T2809
Test name
Test status
Simulation time 175686408 ps
CPU time 1.62 seconds
Started Jul 11 05:37:06 PM PDT 24
Finished Jul 11 05:37:09 PM PDT 24
Peak memory 214380 kb
Host smart-258ce895-ef93-4f0e-862a-286c8a6b5f71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894206328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2894206328
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3856664723
Short name T270
Test name
Test status
Simulation time 168932827 ps
CPU time 1.07 seconds
Started Jul 11 05:36:57 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 206308 kb
Host smart-0e028bde-0b53-47d6-9174-1f1cd5c7baf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3856664723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3856664723
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2368121095
Short name T2840
Test name
Test status
Simulation time 36110822 ps
CPU time 0.65 seconds
Started Jul 11 05:36:57 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 206024 kb
Host smart-b052cd7c-2941-4418-90bd-6b4c343b0ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2368121095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2368121095
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3706545351
Short name T285
Test name
Test status
Simulation time 159463286 ps
CPU time 1.67 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 206316 kb
Host smart-a20fb1dd-288b-435b-b07c-ad89e81c0757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3706545351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3706545351
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4112524503
Short name T2757
Test name
Test status
Simulation time 107725579 ps
CPU time 2.66 seconds
Started Jul 11 05:36:54 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 206400 kb
Host smart-2e86dc4a-9937-45e0-8322-7790c2d98985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4112524503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4112524503
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.132713524
Short name T2765
Test name
Test status
Simulation time 120129807 ps
CPU time 1.3 seconds
Started Jul 11 05:37:06 PM PDT 24
Finished Jul 11 05:37:09 PM PDT 24
Peak memory 214432 kb
Host smart-b91d3082-3815-4a10-ba4c-de257c85ce80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132713524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.132713524
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3767543809
Short name T2756
Test name
Test status
Simulation time 78005567 ps
CPU time 0.94 seconds
Started Jul 11 05:36:55 PM PDT 24
Finished Jul 11 05:37:01 PM PDT 24
Peak memory 206288 kb
Host smart-b4022833-6ea1-4218-8a51-ee51102627c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3767543809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3767543809
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4162304701
Short name T2832
Test name
Test status
Simulation time 36962162 ps
CPU time 0.65 seconds
Started Jul 11 05:36:53 PM PDT 24
Finished Jul 11 05:36:59 PM PDT 24
Peak memory 205992 kb
Host smart-93468027-2622-4c46-b659-b72638c52394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4162304701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.4162304701
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3823613856
Short name T2771
Test name
Test status
Simulation time 173469767 ps
CPU time 1.54 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:07 PM PDT 24
Peak memory 206348 kb
Host smart-18c94e5b-f9a4-425e-b5c0-50e77b1ce5b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3823613856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3823613856
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.4178985231
Short name T2847
Test name
Test status
Simulation time 54811383 ps
CPU time 1.31 seconds
Started Jul 11 05:37:08 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 206172 kb
Host smart-f06ed465-7ce4-4a51-a156-cd341ebaa6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4178985231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.4178985231
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.829345044
Short name T2763
Test name
Test status
Simulation time 1466086547 ps
CPU time 5.56 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:11 PM PDT 24
Peak memory 206364 kb
Host smart-409b8306-68ca-4c10-ab85-22ebdd41c384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=829345044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.829345044
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3107329975
Short name T2770
Test name
Test status
Simulation time 94723391 ps
CPU time 1.33 seconds
Started Jul 11 05:36:57 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 214496 kb
Host smart-701380a9-ca3e-4984-a802-182cbbd21a1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107329975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3107329975
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2832294614
Short name T2800
Test name
Test status
Simulation time 69440783 ps
CPU time 0.97 seconds
Started Jul 11 05:36:57 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 206308 kb
Host smart-45a6214e-d834-4057-ae45-800f10205762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2832294614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2832294614
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4212576022
Short name T294
Test name
Test status
Simulation time 59740097 ps
CPU time 0.68 seconds
Started Jul 11 05:36:57 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 206180 kb
Host smart-4abc12a4-ab83-4327-b594-77703ec290b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4212576022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4212576022
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2227939665
Short name T2767
Test name
Test status
Simulation time 110335247 ps
CPU time 1.19 seconds
Started Jul 11 05:37:06 PM PDT 24
Finished Jul 11 05:37:09 PM PDT 24
Peak memory 206392 kb
Host smart-b607c829-1de1-4e26-bab2-31aecc1c6e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2227939665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2227939665
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1142200115
Short name T2824
Test name
Test status
Simulation time 179091669 ps
CPU time 2.27 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:08 PM PDT 24
Peak memory 206404 kb
Host smart-360cd11b-a36e-4b51-b1bf-2c94ff4564f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1142200115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1142200115
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2403897203
Short name T313
Test name
Test status
Simulation time 811691918 ps
CPU time 3.31 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 206308 kb
Host smart-374bfeb0-7853-46c9-891b-dd0699470fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2403897203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2403897203
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1239622845
Short name T2774
Test name
Test status
Simulation time 124392596 ps
CPU time 1.2 seconds
Started Jul 11 05:37:00 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 216324 kb
Host smart-a189616b-db0c-42ce-b115-82fac37bc1f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239622845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1239622845
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4176592140
Short name T2783
Test name
Test status
Simulation time 152309466 ps
CPU time 1.15 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:07 PM PDT 24
Peak memory 205264 kb
Host smart-341ac0b3-504b-475c-9f09-a6d8931511cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4176592140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.4176592140
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2798448254
Short name T296
Test name
Test status
Simulation time 53706231 ps
CPU time 0.68 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:01 PM PDT 24
Peak memory 206024 kb
Host smart-38d01f56-21c0-4308-9c01-1e6e179b57ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2798448254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2798448254
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3693257680
Short name T2807
Test name
Test status
Simulation time 268073141 ps
CPU time 1.41 seconds
Started Jul 11 05:37:06 PM PDT 24
Finished Jul 11 05:37:08 PM PDT 24
Peak memory 206212 kb
Host smart-6f9a4f23-2d14-4cf2-b303-b3a667fa81ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3693257680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3693257680
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1415256449
Short name T2830
Test name
Test status
Simulation time 103466641 ps
CPU time 1.85 seconds
Started Jul 11 05:38:04 PM PDT 24
Finished Jul 11 05:38:08 PM PDT 24
Peak memory 206404 kb
Host smart-ad9f0908-4dbd-467a-ad7d-d2adcddf962e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1415256449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1415256449
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3856299925
Short name T316
Test name
Test status
Simulation time 436000346 ps
CPU time 3.08 seconds
Started Jul 11 05:37:07 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 206236 kb
Host smart-b4f1d9b7-77bf-4169-83c4-ec43616e5211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3856299925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3856299925
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3978293023
Short name T208
Test name
Test status
Simulation time 144479734 ps
CPU time 1.36 seconds
Started Jul 11 05:36:56 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 214572 kb
Host smart-8df78811-217a-4d2b-9689-91faef6c708e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978293023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3978293023
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.668259209
Short name T2789
Test name
Test status
Simulation time 51337615 ps
CPU time 0.96 seconds
Started Jul 11 05:36:57 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 206276 kb
Host smart-d776cb20-324f-4e07-a942-e7f037ebdcf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=668259209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.668259209
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1929767752
Short name T2775
Test name
Test status
Simulation time 36489256 ps
CPU time 0.65 seconds
Started Jul 11 05:37:00 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 206008 kb
Host smart-abdc2b48-830d-4816-94be-f0ea55510bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1929767752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1929767752
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.86760802
Short name T2848
Test name
Test status
Simulation time 159651059 ps
CPU time 1.64 seconds
Started Jul 11 05:36:58 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 206304 kb
Host smart-f0ce34f3-aee0-4530-9477-4a570e5c2089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=86760802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.86760802
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1413864499
Short name T2842
Test name
Test status
Simulation time 74610650 ps
CPU time 1.11 seconds
Started Jul 11 05:36:59 PM PDT 24
Finished Jul 11 05:37:03 PM PDT 24
Peak memory 206312 kb
Host smart-2bd45fb1-0fbb-43bc-8398-7d78a209dca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1413864499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1413864499
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2264872999
Short name T233
Test name
Test status
Simulation time 488223677 ps
CPU time 4.25 seconds
Started Jul 11 05:37:06 PM PDT 24
Finished Jul 11 05:37:12 PM PDT 24
Peak memory 206376 kb
Host smart-dc4ad5ca-988b-4705-aa95-57f0c99207d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2264872999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2264872999
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1160753800
Short name T2026
Test name
Test status
Simulation time 62245847 ps
CPU time 0.73 seconds
Started Jul 11 05:53:18 PM PDT 24
Finished Jul 11 05:53:20 PM PDT 24
Peak memory 206412 kb
Host smart-da6cad3a-40ba-48a6-af36-22ffe4c6e97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1160753800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1160753800
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3006472330
Short name T2257
Test name
Test status
Simulation time 3953442905 ps
CPU time 5.17 seconds
Started Jul 11 05:52:38 PM PDT 24
Finished Jul 11 05:52:44 PM PDT 24
Peak memory 206620 kb
Host smart-280c82b3-5758-4d04-b70d-62ab50d1ef1e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3006472330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3006472330
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2737139611
Short name T919
Test name
Test status
Simulation time 13315536674 ps
CPU time 14.77 seconds
Started Jul 11 05:52:36 PM PDT 24
Finished Jul 11 05:52:52 PM PDT 24
Peak memory 206700 kb
Host smart-507a73ff-aac1-4585-a6cf-3c52b022cc7a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2737139611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2737139611
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2939295912
Short name T2737
Test name
Test status
Simulation time 23395057134 ps
CPU time 23.22 seconds
Started Jul 11 05:52:36 PM PDT 24
Finished Jul 11 05:53:00 PM PDT 24
Peak memory 206456 kb
Host smart-69670668-82b6-422f-b81d-d6d367753d92
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2939295912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2939295912
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.361002367
Short name T1048
Test name
Test status
Simulation time 148592376 ps
CPU time 0.75 seconds
Started Jul 11 05:52:36 PM PDT 24
Finished Jul 11 05:52:37 PM PDT 24
Peak memory 206400 kb
Host smart-ef360584-f897-4d53-a993-ba46039bcdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36100
2367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.361002367
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1398610920
Short name T2592
Test name
Test status
Simulation time 151922440 ps
CPU time 0.74 seconds
Started Jul 11 05:52:42 PM PDT 24
Finished Jul 11 05:52:43 PM PDT 24
Peak memory 206388 kb
Host smart-2f9cb310-a968-4b80-b737-85d78a3a531e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13986
10920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1398610920
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.590754545
Short name T525
Test name
Test status
Simulation time 357438972 ps
CPU time 1.27 seconds
Started Jul 11 05:52:39 PM PDT 24
Finished Jul 11 05:52:41 PM PDT 24
Peak memory 206300 kb
Host smart-b004fa5d-232a-4f93-8bb0-d83e92dd8427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59075
4545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.590754545
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2115447099
Short name T2087
Test name
Test status
Simulation time 635521022 ps
CPU time 1.51 seconds
Started Jul 11 05:52:39 PM PDT 24
Finished Jul 11 05:52:42 PM PDT 24
Peak memory 206584 kb
Host smart-08a4e43f-d317-47dd-b059-a7b86ded6000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
47099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2115447099
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2346678942
Short name T1608
Test name
Test status
Simulation time 22343861752 ps
CPU time 39.01 seconds
Started Jul 11 05:52:51 PM PDT 24
Finished Jul 11 05:53:31 PM PDT 24
Peak memory 206556 kb
Host smart-3c1ce090-ecba-43e0-a9a9-7aeeb455066f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23466
78942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2346678942
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2975436913
Short name T2034
Test name
Test status
Simulation time 495995934 ps
CPU time 1.35 seconds
Started Jul 11 05:52:41 PM PDT 24
Finished Jul 11 05:52:43 PM PDT 24
Peak memory 206380 kb
Host smart-1dc72050-aeb0-47e8-be18-fe71d8fda662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29754
36913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2975436913
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1855860371
Short name T1735
Test name
Test status
Simulation time 163773755 ps
CPU time 0.78 seconds
Started Jul 11 05:52:50 PM PDT 24
Finished Jul 11 05:52:52 PM PDT 24
Peak memory 206304 kb
Host smart-681d0b7f-161c-4201-b220-62ae6c35db1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18558
60371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1855860371
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.4230853417
Short name T658
Test name
Test status
Simulation time 5110403372 ps
CPU time 41.58 seconds
Started Jul 11 05:52:47 PM PDT 24
Finished Jul 11 05:53:29 PM PDT 24
Peak memory 206652 kb
Host smart-82feaa04-70aa-4008-9390-83378a446d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42308
53417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.4230853417
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1075972094
Short name T1227
Test name
Test status
Simulation time 79534973 ps
CPU time 0.68 seconds
Started Jul 11 05:52:46 PM PDT 24
Finished Jul 11 05:52:47 PM PDT 24
Peak memory 206372 kb
Host smart-b0506f70-c578-4daa-8012-26ac1f088895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10759
72094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1075972094
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2619638191
Short name T993
Test name
Test status
Simulation time 754773913 ps
CPU time 2 seconds
Started Jul 11 05:52:46 PM PDT 24
Finished Jul 11 05:52:49 PM PDT 24
Peak memory 206640 kb
Host smart-2d86b736-4907-4c04-8b53-c67f244b16f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26196
38191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2619638191
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2615612337
Short name T2254
Test name
Test status
Simulation time 187647400 ps
CPU time 1.28 seconds
Started Jul 11 05:53:10 PM PDT 24
Finished Jul 11 05:53:13 PM PDT 24
Peak memory 206512 kb
Host smart-96e346cb-544f-4f10-9d79-56bf99bc3e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26156
12337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2615612337
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.196547616
Short name T362
Test name
Test status
Simulation time 93181118519 ps
CPU time 124.77 seconds
Started Jul 11 05:52:51 PM PDT 24
Finished Jul 11 05:54:57 PM PDT 24
Peak memory 206564 kb
Host smart-8f898bea-1b55-40d5-8897-d770034152bd
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=196547616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.196547616
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2394544413
Short name T337
Test name
Test status
Simulation time 81155078036 ps
CPU time 107.91 seconds
Started Jul 11 05:52:47 PM PDT 24
Finished Jul 11 05:54:36 PM PDT 24
Peak memory 206636 kb
Host smart-4491e481-b083-44ec-be48-df1af1773372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394544413 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2394544413
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.114354222
Short name T1703
Test name
Test status
Simulation time 81119626468 ps
CPU time 103.67 seconds
Started Jul 11 05:52:45 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 206684 kb
Host smart-059fc4f8-0842-4687-98ae-d4aee9a8ef9a
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=114354222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.114354222
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3090502655
Short name T812
Test name
Test status
Simulation time 100122182565 ps
CPU time 139.5 seconds
Started Jul 11 05:53:15 PM PDT 24
Finished Jul 11 05:55:36 PM PDT 24
Peak memory 206572 kb
Host smart-4c972532-aa00-4dfd-bb26-1b87e744fec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090502655 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3090502655
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.2633991613
Short name T2338
Test name
Test status
Simulation time 115168430756 ps
CPU time 163.59 seconds
Started Jul 11 05:52:45 PM PDT 24
Finished Jul 11 05:55:29 PM PDT 24
Peak memory 206596 kb
Host smart-39088285-9c01-4990-a090-9d09cd67fad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339
91613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2633991613
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.214333762
Short name T1613
Test name
Test status
Simulation time 197584030 ps
CPU time 0.84 seconds
Started Jul 11 05:52:52 PM PDT 24
Finished Jul 11 05:52:54 PM PDT 24
Peak memory 206380 kb
Host smart-ee3ca484-9de9-40cd-858e-39a0e2ce48b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21433
3762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.214333762
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3245383457
Short name T2549
Test name
Test status
Simulation time 142962156 ps
CPU time 0.74 seconds
Started Jul 11 05:52:51 PM PDT 24
Finished Jul 11 05:52:53 PM PDT 24
Peak memory 206312 kb
Host smart-fedc9afe-ed65-45b8-a030-4d85d8da9440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32453
83457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3245383457
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.832916751
Short name T2602
Test name
Test status
Simulation time 216316140 ps
CPU time 0.83 seconds
Started Jul 11 05:52:52 PM PDT 24
Finished Jul 11 05:52:54 PM PDT 24
Peak memory 206364 kb
Host smart-9997f384-f98f-42b7-a802-54b12cf24d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83291
6751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.832916751
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1941064839
Short name T2177
Test name
Test status
Simulation time 6274763031 ps
CPU time 58.98 seconds
Started Jul 11 05:52:51 PM PDT 24
Finished Jul 11 05:53:50 PM PDT 24
Peak memory 206676 kb
Host smart-b7271032-271f-4fdd-a4f4-d7b542c16984
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1941064839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1941064839
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1323330050
Short name T1691
Test name
Test status
Simulation time 10562341720 ps
CPU time 91.81 seconds
Started Jul 11 05:52:56 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 206644 kb
Host smart-f2015447-ba49-472a-bfa9-aeb02133bdcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233
30050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1323330050
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3098624208
Short name T1802
Test name
Test status
Simulation time 243044885 ps
CPU time 0.81 seconds
Started Jul 11 05:52:54 PM PDT 24
Finished Jul 11 05:52:55 PM PDT 24
Peak memory 206380 kb
Host smart-ab2b91db-e76b-4524-963d-c46ea67de7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30986
24208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3098624208
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.4141830177
Short name T74
Test name
Test status
Simulation time 485788047 ps
CPU time 1.41 seconds
Started Jul 11 05:53:01 PM PDT 24
Finished Jul 11 05:53:02 PM PDT 24
Peak memory 206392 kb
Host smart-6801a962-4d1e-4988-bad0-7a23dacb61a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41418
30177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.4141830177
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2638010433
Short name T1452
Test name
Test status
Simulation time 23350941913 ps
CPU time 28.63 seconds
Started Jul 11 05:52:56 PM PDT 24
Finished Jul 11 05:53:25 PM PDT 24
Peak memory 206460 kb
Host smart-3ae65d33-0105-4b1b-8d2b-50abc3ce2083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26380
10433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2638010433
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3749979778
Short name T1384
Test name
Test status
Simulation time 3329962300 ps
CPU time 3.86 seconds
Started Jul 11 05:52:56 PM PDT 24
Finished Jul 11 05:53:00 PM PDT 24
Peak memory 206364 kb
Host smart-3f850c88-8a1b-4059-aa6f-4ffd8d958edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37499
79778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3749979778
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3937399967
Short name T2064
Test name
Test status
Simulation time 7669358165 ps
CPU time 53.4 seconds
Started Jul 11 05:52:58 PM PDT 24
Finished Jul 11 05:53:52 PM PDT 24
Peak memory 206660 kb
Host smart-b41d7862-7cf6-4785-8aaa-041d753a0627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39373
99967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3937399967
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1032158918
Short name T2688
Test name
Test status
Simulation time 5583805217 ps
CPU time 51.07 seconds
Started Jul 11 05:52:53 PM PDT 24
Finished Jul 11 05:53:45 PM PDT 24
Peak memory 206664 kb
Host smart-fe967d34-e7db-4877-b101-d44d69c5af2f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1032158918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1032158918
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2831033781
Short name T1232
Test name
Test status
Simulation time 235159287 ps
CPU time 0.93 seconds
Started Jul 11 05:53:00 PM PDT 24
Finished Jul 11 05:53:02 PM PDT 24
Peak memory 206400 kb
Host smart-c2b98e19-b678-4b6e-b7f0-8f5d9cc2a451
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2831033781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2831033781
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1673898885
Short name T625
Test name
Test status
Simulation time 244622276 ps
CPU time 0.86 seconds
Started Jul 11 05:52:57 PM PDT 24
Finished Jul 11 05:52:59 PM PDT 24
Peak memory 206392 kb
Host smart-be120644-49cb-4b92-8b9e-9ea3db2d937d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16738
98885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1673898885
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2236501743
Short name T1022
Test name
Test status
Simulation time 3768739893 ps
CPU time 26.47 seconds
Started Jul 11 05:52:54 PM PDT 24
Finished Jul 11 05:53:22 PM PDT 24
Peak memory 206648 kb
Host smart-17b1c266-cd9c-4a35-a281-23e9cb94d3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
01743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2236501743
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.118864050
Short name T24
Test name
Test status
Simulation time 4296736837 ps
CPU time 117.64 seconds
Started Jul 11 05:52:59 PM PDT 24
Finished Jul 11 05:54:57 PM PDT 24
Peak memory 206648 kb
Host smart-0aa94178-5ec8-4855-90d0-2e4605383266
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=118864050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.118864050
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1880552349
Short name T2280
Test name
Test status
Simulation time 176413143 ps
CPU time 0.81 seconds
Started Jul 11 05:53:08 PM PDT 24
Finished Jul 11 05:53:10 PM PDT 24
Peak memory 206384 kb
Host smart-f7be5c39-d552-4444-81b4-fa6af13c1f2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1880552349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1880552349
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1123506078
Short name T547
Test name
Test status
Simulation time 147372322 ps
CPU time 0.74 seconds
Started Jul 11 05:53:07 PM PDT 24
Finished Jul 11 05:53:08 PM PDT 24
Peak memory 206408 kb
Host smart-0bef2b74-5115-40a6-8ae7-7258d2334fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
06078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1123506078
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.269759414
Short name T72
Test name
Test status
Simulation time 551687255 ps
CPU time 1.39 seconds
Started Jul 11 05:53:08 PM PDT 24
Finished Jul 11 05:53:10 PM PDT 24
Peak memory 206384 kb
Host smart-f939ea80-b3bd-44b8-9182-f67c474032c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26975
9414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.269759414
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3792471683
Short name T756
Test name
Test status
Simulation time 164509566 ps
CPU time 0.8 seconds
Started Jul 11 05:53:10 PM PDT 24
Finished Jul 11 05:53:11 PM PDT 24
Peak memory 206388 kb
Host smart-7cea3617-a98a-46d1-b43f-780b7c3bc821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37924
71683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3792471683
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.387495771
Short name T1054
Test name
Test status
Simulation time 158590166 ps
CPU time 0.75 seconds
Started Jul 11 05:53:06 PM PDT 24
Finished Jul 11 05:53:07 PM PDT 24
Peak memory 206376 kb
Host smart-753fac24-6f22-4d8c-b1c2-299df896fc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749
5771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.387495771
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3217635369
Short name T1617
Test name
Test status
Simulation time 177248109 ps
CPU time 0.83 seconds
Started Jul 11 05:53:04 PM PDT 24
Finished Jul 11 05:53:06 PM PDT 24
Peak memory 206396 kb
Host smart-0d6e5848-460c-410c-a6b7-c03500d33534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32176
35369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3217635369
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3529883126
Short name T1031
Test name
Test status
Simulation time 160927151 ps
CPU time 0.8 seconds
Started Jul 11 05:53:08 PM PDT 24
Finished Jul 11 05:53:09 PM PDT 24
Peak memory 206404 kb
Host smart-c38edb7f-5703-40fe-ba70-dc23c31b282f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35298
83126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3529883126
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2380593976
Short name T1250
Test name
Test status
Simulation time 203067353 ps
CPU time 0.9 seconds
Started Jul 11 05:53:08 PM PDT 24
Finished Jul 11 05:53:10 PM PDT 24
Peak memory 206296 kb
Host smart-a6269774-fa81-4039-b691-a7582ce5391a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23805
93976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2380593976
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2853110874
Short name T2215
Test name
Test status
Simulation time 285282375 ps
CPU time 0.98 seconds
Started Jul 11 05:53:06 PM PDT 24
Finished Jul 11 05:53:07 PM PDT 24
Peak memory 206396 kb
Host smart-78d418d5-c829-4da8-8910-85c87c17ef8f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2853110874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2853110874
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2131226559
Short name T213
Test name
Test status
Simulation time 230288288 ps
CPU time 0.89 seconds
Started Jul 11 05:53:06 PM PDT 24
Finished Jul 11 05:53:07 PM PDT 24
Peak memory 206360 kb
Host smart-4b0ffd50-8459-4d12-96c5-cdef17f35f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21312
26559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2131226559
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1707770376
Short name T2633
Test name
Test status
Simulation time 207204926 ps
CPU time 0.9 seconds
Started Jul 11 05:53:05 PM PDT 24
Finished Jul 11 05:53:06 PM PDT 24
Peak memory 206364 kb
Host smart-70387f29-4a8c-47cb-93f8-15610dc3d1d2
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1707770376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1707770376
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.3784190145
Short name T2565
Test name
Test status
Simulation time 257522110 ps
CPU time 0.91 seconds
Started Jul 11 05:53:04 PM PDT 24
Finished Jul 11 05:53:06 PM PDT 24
Peak memory 206540 kb
Host smart-ce0fc6f0-dc8d-41e2-93c2-3746941edb58
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3784190145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.3784190145
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1083484581
Short name T1920
Test name
Test status
Simulation time 46967706 ps
CPU time 0.62 seconds
Started Jul 11 05:53:14 PM PDT 24
Finished Jul 11 05:53:16 PM PDT 24
Peak memory 206320 kb
Host smart-a847f143-fd9a-4c79-b217-35d9de0bf732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10834
84581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1083484581
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2796896600
Short name T2548
Test name
Test status
Simulation time 7599501041 ps
CPU time 17.97 seconds
Started Jul 11 05:53:14 PM PDT 24
Finished Jul 11 05:53:33 PM PDT 24
Peak memory 206684 kb
Host smart-3efd2b5e-fb41-451c-ad32-44bfb524c4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968
96600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2796896600
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2223839112
Short name T1351
Test name
Test status
Simulation time 214405748 ps
CPU time 0.85 seconds
Started Jul 11 05:53:32 PM PDT 24
Finished Jul 11 05:53:34 PM PDT 24
Peak memory 206320 kb
Host smart-7c5e1856-4446-4bae-b5e6-7ddc681609e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22238
39112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2223839112
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.444940467
Short name T1562
Test name
Test status
Simulation time 219008042 ps
CPU time 0.98 seconds
Started Jul 11 05:53:32 PM PDT 24
Finished Jul 11 05:53:34 PM PDT 24
Peak memory 206312 kb
Host smart-28262ead-9ebd-4c59-bbbe-aa15ae0bafd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44494
0467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.444940467
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2908487980
Short name T2367
Test name
Test status
Simulation time 11995703238 ps
CPU time 78.7 seconds
Started Jul 11 05:53:13 PM PDT 24
Finished Jul 11 05:54:33 PM PDT 24
Peak memory 206672 kb
Host smart-5734e1ac-9df6-4da5-ac49-163bd6e3ec96
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2908487980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2908487980
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.2789096657
Short name T2335
Test name
Test status
Simulation time 15809662521 ps
CPU time 344.66 seconds
Started Jul 11 05:53:32 PM PDT 24
Finished Jul 11 05:59:17 PM PDT 24
Peak memory 206644 kb
Host smart-f3cfdf81-177a-4c6a-b158-6896e70e5292
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2789096657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2789096657
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1145709783
Short name T871
Test name
Test status
Simulation time 249007895 ps
CPU time 0.97 seconds
Started Jul 11 05:53:14 PM PDT 24
Finished Jul 11 05:53:16 PM PDT 24
Peak memory 206316 kb
Host smart-5c27219d-6c19-451d-9358-9dd9e95c9b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11457
09783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1145709783
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.240786291
Short name T1156
Test name
Test status
Simulation time 200698560 ps
CPU time 0.79 seconds
Started Jul 11 05:53:11 PM PDT 24
Finished Jul 11 05:53:12 PM PDT 24
Peak memory 206376 kb
Host smart-d6cce0d7-3042-41d5-a27b-3695c842ff81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24078
6291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.240786291
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2007270342
Short name T1327
Test name
Test status
Simulation time 144945844 ps
CPU time 0.75 seconds
Started Jul 11 05:53:18 PM PDT 24
Finished Jul 11 05:53:21 PM PDT 24
Peak memory 206312 kb
Host smart-99c26f06-77f2-4ba8-9c99-a26e75fe549c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20072
70342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2007270342
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3306031360
Short name T663
Test name
Test status
Simulation time 215618769 ps
CPU time 0.9 seconds
Started Jul 11 05:53:22 PM PDT 24
Finished Jul 11 05:53:24 PM PDT 24
Peak memory 206404 kb
Host smart-b904b299-1cc7-4a6d-9c0f-46a7e19b3f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33060
31360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3306031360
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2482073764
Short name T1261
Test name
Test status
Simulation time 153683547 ps
CPU time 0.74 seconds
Started Jul 11 05:53:17 PM PDT 24
Finished Jul 11 05:53:20 PM PDT 24
Peak memory 206380 kb
Host smart-dc18d67c-720f-42a6-8139-3bff9d8cd98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24820
73764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2482073764
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.220651954
Short name T1845
Test name
Test status
Simulation time 203502395 ps
CPU time 0.78 seconds
Started Jul 11 05:53:26 PM PDT 24
Finished Jul 11 05:53:28 PM PDT 24
Peak memory 206308 kb
Host smart-4434f34e-48be-4b25-972b-26404f9b529b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22065
1954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.220651954
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1606039151
Short name T996
Test name
Test status
Simulation time 244884880 ps
CPU time 0.96 seconds
Started Jul 11 05:53:22 PM PDT 24
Finished Jul 11 05:53:24 PM PDT 24
Peak memory 206396 kb
Host smart-d25fdce6-2e6a-4534-9256-1d37c170974d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16060
39151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1606039151
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.326876064
Short name T1376
Test name
Test status
Simulation time 6192413654 ps
CPU time 170.14 seconds
Started Jul 11 05:53:26 PM PDT 24
Finished Jul 11 05:56:17 PM PDT 24
Peak memory 206572 kb
Host smart-1f4556a5-3ce9-4df1-b7da-0059ce6aae67
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=326876064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.326876064
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2105717548
Short name T2667
Test name
Test status
Simulation time 173260692 ps
CPU time 0.8 seconds
Started Jul 11 05:53:19 PM PDT 24
Finished Jul 11 05:53:21 PM PDT 24
Peak memory 206380 kb
Host smart-6d32da43-a2f1-48c3-9e81-e6614b544b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
17548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2105717548
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1966464725
Short name T1797
Test name
Test status
Simulation time 176409044 ps
CPU time 0.79 seconds
Started Jul 11 05:53:20 PM PDT 24
Finished Jul 11 05:53:22 PM PDT 24
Peak memory 206384 kb
Host smart-ae1a2ee2-583f-4bfe-b6ce-b67baac02008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19664
64725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1966464725
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.287669917
Short name T1026
Test name
Test status
Simulation time 1365468163 ps
CPU time 2.55 seconds
Started Jul 11 05:53:26 PM PDT 24
Finished Jul 11 05:53:30 PM PDT 24
Peak memory 206564 kb
Host smart-1b8725da-e8d5-40ac-8a25-70acb04435b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28766
9917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.287669917
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.570086537
Short name T2504
Test name
Test status
Simulation time 5703021456 ps
CPU time 37.48 seconds
Started Jul 11 05:53:17 PM PDT 24
Finished Jul 11 05:53:56 PM PDT 24
Peak memory 206632 kb
Host smart-0feb4f77-fd27-41bb-b489-61f7fa78d62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57008
6537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.570086537
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2584944749
Short name T1538
Test name
Test status
Simulation time 50179771 ps
CPU time 0.76 seconds
Started Jul 11 05:53:52 PM PDT 24
Finished Jul 11 05:53:54 PM PDT 24
Peak memory 206408 kb
Host smart-661a15b3-7419-4aa2-8363-925b5eadaeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2584944749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2584944749
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3375810921
Short name T1540
Test name
Test status
Simulation time 3550548932 ps
CPU time 4.21 seconds
Started Jul 11 05:53:18 PM PDT 24
Finished Jul 11 05:53:23 PM PDT 24
Peak memory 206428 kb
Host smart-04483193-de86-4375-82ef-2b9f549094d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3375810921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.3375810921
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1382152920
Short name T1091
Test name
Test status
Simulation time 13387089291 ps
CPU time 13.91 seconds
Started Jul 11 05:53:16 PM PDT 24
Finished Jul 11 05:53:31 PM PDT 24
Peak memory 206608 kb
Host smart-3f9b9481-ce64-4541-99da-decf9757ecb9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1382152920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1382152920
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2229470398
Short name T1878
Test name
Test status
Simulation time 23384091562 ps
CPU time 21.34 seconds
Started Jul 11 05:53:17 PM PDT 24
Finished Jul 11 05:53:40 PM PDT 24
Peak memory 206584 kb
Host smart-7bbe4763-40a4-4d9a-a4df-f42d56685546
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2229470398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.2229470398
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3366279551
Short name T421
Test name
Test status
Simulation time 150098135 ps
CPU time 0.78 seconds
Started Jul 11 05:53:26 PM PDT 24
Finished Jul 11 05:53:27 PM PDT 24
Peak memory 206412 kb
Host smart-d38416c9-2c0b-4a59-8527-a6b69108c34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33662
79551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3366279551
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.80159745
Short name T67
Test name
Test status
Simulation time 161279368 ps
CPU time 0.75 seconds
Started Jul 11 05:53:24 PM PDT 24
Finished Jul 11 05:53:26 PM PDT 24
Peak memory 206376 kb
Host smart-42e048ad-160d-49f5-a0e2-a4f1da1e35f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80159
745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.80159745
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2419683381
Short name T925
Test name
Test status
Simulation time 154109531 ps
CPU time 0.78 seconds
Started Jul 11 05:53:23 PM PDT 24
Finished Jul 11 05:53:25 PM PDT 24
Peak memory 206376 kb
Host smart-2da5f43a-4023-4788-8b0d-4955d3e2092d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24196
83381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2419683381
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.4194465465
Short name T118
Test name
Test status
Simulation time 513479639 ps
CPU time 1.49 seconds
Started Jul 11 05:53:23 PM PDT 24
Finished Jul 11 05:53:26 PM PDT 24
Peak memory 206540 kb
Host smart-1db018f8-8511-4fcc-882e-b76e5b1e4964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41944
65465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.4194465465
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2213255631
Short name T799
Test name
Test status
Simulation time 1181583505 ps
CPU time 2.61 seconds
Started Jul 11 05:53:24 PM PDT 24
Finished Jul 11 05:53:28 PM PDT 24
Peak memory 206584 kb
Host smart-dde28a98-556b-4172-ae47-1605dd401040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22132
55631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2213255631
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2471518516
Short name T2629
Test name
Test status
Simulation time 443260390 ps
CPU time 1.23 seconds
Started Jul 11 05:53:28 PM PDT 24
Finished Jul 11 05:53:30 PM PDT 24
Peak memory 206392 kb
Host smart-fee0371b-d34f-4f57-8265-c060906e31c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24715
18516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2471518516
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2724788336
Short name T1262
Test name
Test status
Simulation time 138002725 ps
CPU time 0.72 seconds
Started Jul 11 05:53:41 PM PDT 24
Finished Jul 11 05:53:42 PM PDT 24
Peak memory 206400 kb
Host smart-23e8bb44-f7bf-495f-8274-e5db2b874c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27247
88336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2724788336
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1473747388
Short name T1836
Test name
Test status
Simulation time 39991279 ps
CPU time 0.62 seconds
Started Jul 11 05:53:28 PM PDT 24
Finished Jul 11 05:53:29 PM PDT 24
Peak memory 206364 kb
Host smart-93e8545c-ff36-4e06-975d-260ce8e44c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14737
47388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1473747388
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.4044156498
Short name T2024
Test name
Test status
Simulation time 798786506 ps
CPU time 1.95 seconds
Started Jul 11 05:53:36 PM PDT 24
Finished Jul 11 05:53:39 PM PDT 24
Peak memory 206504 kb
Host smart-ede126f1-9b9f-4b36-bf2c-99bfa9e4fc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40441
56498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.4044156498
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1281840983
Short name T1060
Test name
Test status
Simulation time 85189307263 ps
CPU time 135.03 seconds
Started Jul 11 05:53:26 PM PDT 24
Finished Jul 11 05:55:43 PM PDT 24
Peak memory 206792 kb
Host smart-d906212b-953d-40a6-ab22-2c91289cffb8
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1281840983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1281840983
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.3072735888
Short name T1073
Test name
Test status
Simulation time 117289532052 ps
CPU time 184.14 seconds
Started Jul 11 05:53:30 PM PDT 24
Finished Jul 11 05:56:34 PM PDT 24
Peak memory 206580 kb
Host smart-7c2f8707-c775-4c69-891d-1d9596cbff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072735888 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3072735888
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.697810013
Short name T44
Test name
Test status
Simulation time 115111291601 ps
CPU time 157.91 seconds
Started Jul 11 05:53:29 PM PDT 24
Finished Jul 11 05:56:07 PM PDT 24
Peak memory 206652 kb
Host smart-1dced18a-1f82-42bb-a966-2b6273896375
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=697810013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.697810013
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.4171613500
Short name T1263
Test name
Test status
Simulation time 96258432387 ps
CPU time 130.45 seconds
Started Jul 11 05:53:29 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 206580 kb
Host smart-77c8a132-5294-42f1-aa88-eecd40ec75b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171613500 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.4171613500
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1068384324
Short name T1881
Test name
Test status
Simulation time 83152910016 ps
CPU time 104.34 seconds
Started Jul 11 05:53:31 PM PDT 24
Finished Jul 11 05:55:16 PM PDT 24
Peak memory 206692 kb
Host smart-de243325-93d7-42e0-98da-f5b8823f8f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10683
84324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1068384324
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2483305226
Short name T2169
Test name
Test status
Simulation time 208382070 ps
CPU time 0.86 seconds
Started Jul 11 05:53:30 PM PDT 24
Finished Jul 11 05:53:31 PM PDT 24
Peak memory 206312 kb
Host smart-67b0a993-ecb8-45b6-b89e-dc294a87cc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24833
05226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2483305226
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.4104456703
Short name T1428
Test name
Test status
Simulation time 137487160 ps
CPU time 0.78 seconds
Started Jul 11 05:53:30 PM PDT 24
Finished Jul 11 05:53:32 PM PDT 24
Peak memory 206312 kb
Host smart-6d2701b1-d1e6-4451-b71e-de4322034c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41044
56703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.4104456703
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1048970323
Short name T691
Test name
Test status
Simulation time 180355474 ps
CPU time 0.82 seconds
Started Jul 11 05:53:35 PM PDT 24
Finished Jul 11 05:53:37 PM PDT 24
Peak memory 206304 kb
Host smart-bbe5123b-0b48-4bff-8b99-c1126de949de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10489
70323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1048970323
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.4039354663
Short name T1286
Test name
Test status
Simulation time 7654989184 ps
CPU time 53.1 seconds
Started Jul 11 05:53:29 PM PDT 24
Finished Jul 11 05:54:23 PM PDT 24
Peak memory 206632 kb
Host smart-d093dd4d-4ccb-4b9d-a12f-5177033bcb0b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4039354663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.4039354663
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.886890704
Short name T1894
Test name
Test status
Simulation time 11090021484 ps
CPU time 33.28 seconds
Started Jul 11 05:53:35 PM PDT 24
Finished Jul 11 05:54:09 PM PDT 24
Peak memory 206644 kb
Host smart-75038324-bc4f-426a-bcb3-bf8045837394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88689
0704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.886890704
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3688022082
Short name T1912
Test name
Test status
Simulation time 202312421 ps
CPU time 0.79 seconds
Started Jul 11 05:53:33 PM PDT 24
Finished Jul 11 05:53:34 PM PDT 24
Peak memory 206292 kb
Host smart-6b37172e-b079-41cc-8362-5ba63d29d839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36880
22082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3688022082
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3636611782
Short name T916
Test name
Test status
Simulation time 23342856736 ps
CPU time 22.76 seconds
Started Jul 11 05:53:37 PM PDT 24
Finished Jul 11 05:54:01 PM PDT 24
Peak memory 206464 kb
Host smart-5d073b72-c97e-469d-a0f5-ae1e512841c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
11782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3636611782
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1566346365
Short name T1974
Test name
Test status
Simulation time 3286873089 ps
CPU time 3.67 seconds
Started Jul 11 05:53:35 PM PDT 24
Finished Jul 11 05:53:39 PM PDT 24
Peak memory 206424 kb
Host smart-fb816f72-41ad-48f6-9103-dcd271965ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15663
46365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1566346365
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.4038725198
Short name T2079
Test name
Test status
Simulation time 10897694283 ps
CPU time 102.08 seconds
Started Jul 11 05:53:34 PM PDT 24
Finished Jul 11 05:55:17 PM PDT 24
Peak memory 206708 kb
Host smart-d3ad9311-4286-44b3-8214-34499f889f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387
25198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.4038725198
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.917531913
Short name T1333
Test name
Test status
Simulation time 4225450575 ps
CPU time 113.23 seconds
Started Jul 11 05:53:33 PM PDT 24
Finished Jul 11 05:55:27 PM PDT 24
Peak memory 206684 kb
Host smart-b6b1848d-48e6-4b98-8ec4-0b6c178127fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=917531913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.917531913
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.2600396289
Short name T2740
Test name
Test status
Simulation time 244396207 ps
CPU time 0.92 seconds
Started Jul 11 05:53:35 PM PDT 24
Finished Jul 11 05:53:37 PM PDT 24
Peak memory 206332 kb
Host smart-e527e50a-77a4-49e3-b12a-9c499ba014f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2600396289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.2600396289
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.732228069
Short name T2732
Test name
Test status
Simulation time 193119356 ps
CPU time 0.87 seconds
Started Jul 11 05:53:38 PM PDT 24
Finished Jul 11 05:53:39 PM PDT 24
Peak memory 206408 kb
Host smart-e85976fc-a577-40b8-8615-93c0644a4095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73222
8069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.732228069
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2681961198
Short name T2628
Test name
Test status
Simulation time 3312701268 ps
CPU time 23.76 seconds
Started Jul 11 05:54:32 PM PDT 24
Finished Jul 11 05:54:58 PM PDT 24
Peak memory 206540 kb
Host smart-61744355-3c2c-4994-841b-6a8399a89ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26819
61198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2681961198
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3394199644
Short name T364
Test name
Test status
Simulation time 5936079286 ps
CPU time 57.47 seconds
Started Jul 11 05:53:40 PM PDT 24
Finished Jul 11 05:54:38 PM PDT 24
Peak memory 206640 kb
Host smart-b7a6b384-b2d1-4235-8b44-224d6d714fb5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3394199644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3394199644
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2247083821
Short name T1892
Test name
Test status
Simulation time 157196702 ps
CPU time 0.77 seconds
Started Jul 11 05:53:38 PM PDT 24
Finished Jul 11 05:53:40 PM PDT 24
Peak memory 206404 kb
Host smart-878d0d83-a4d1-4b14-ac16-6eacedf566f7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2247083821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2247083821
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.513790723
Short name T1539
Test name
Test status
Simulation time 178819087 ps
CPU time 0.77 seconds
Started Jul 11 05:53:40 PM PDT 24
Finished Jul 11 05:53:42 PM PDT 24
Peak memory 206308 kb
Host smart-be07dc56-9518-4cca-9f79-1dda9f5dba44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51379
0723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.513790723
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1132860412
Short name T2136
Test name
Test status
Simulation time 225669910 ps
CPU time 0.88 seconds
Started Jul 11 05:53:40 PM PDT 24
Finished Jul 11 05:53:42 PM PDT 24
Peak memory 206368 kb
Host smart-8f13fa7f-03d5-4822-a4c6-633a81d82e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11328
60412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1132860412
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3187875874
Short name T2080
Test name
Test status
Simulation time 155636050 ps
CPU time 0.77 seconds
Started Jul 11 05:53:45 PM PDT 24
Finished Jul 11 05:53:47 PM PDT 24
Peak memory 206384 kb
Host smart-89cfd0d5-aec9-4489-9046-7a1472b59849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31878
75874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3187875874
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2572007434
Short name T1440
Test name
Test status
Simulation time 190888504 ps
CPU time 0.88 seconds
Started Jul 11 05:54:01 PM PDT 24
Finished Jul 11 05:54:03 PM PDT 24
Peak memory 206320 kb
Host smart-1cd09ebc-4ad9-4088-ac23-915a800782d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25720
07434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2572007434
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.521762300
Short name T2582
Test name
Test status
Simulation time 139603285 ps
CPU time 0.75 seconds
Started Jul 11 05:53:40 PM PDT 24
Finished Jul 11 05:53:41 PM PDT 24
Peak memory 206392 kb
Host smart-1e563ec7-df7a-4013-93ac-f879675fe7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52176
2300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.521762300
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1485289640
Short name T2547
Test name
Test status
Simulation time 146778010 ps
CPU time 0.79 seconds
Started Jul 11 05:53:43 PM PDT 24
Finished Jul 11 05:53:44 PM PDT 24
Peak memory 206360 kb
Host smart-1a394fab-41b2-4d18-9a61-5f982294d900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14852
89640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1485289640
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.787906330
Short name T727
Test name
Test status
Simulation time 256497385 ps
CPU time 1.04 seconds
Started Jul 11 05:53:49 PM PDT 24
Finished Jul 11 05:53:51 PM PDT 24
Peak memory 206408 kb
Host smart-206662f2-8dbf-49a5-acec-a4458d943736
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=787906330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.787906330
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.970673400
Short name T211
Test name
Test status
Simulation time 231521862 ps
CPU time 0.93 seconds
Started Jul 11 05:53:44 PM PDT 24
Finished Jul 11 05:53:46 PM PDT 24
Peak memory 206388 kb
Host smart-2ca82a3c-34b8-4d13-8315-62d0326bb9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97067
3400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.970673400
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1676647755
Short name T203
Test name
Test status
Simulation time 135324742 ps
CPU time 0.75 seconds
Started Jul 11 05:53:43 PM PDT 24
Finished Jul 11 05:53:45 PM PDT 24
Peak memory 206404 kb
Host smart-8febfccc-ce63-4967-9fc2-2fb1f8e1c4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16766
47755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1676647755
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3647611510
Short name T2094
Test name
Test status
Simulation time 66681788 ps
CPU time 0.67 seconds
Started Jul 11 05:53:44 PM PDT 24
Finished Jul 11 05:53:45 PM PDT 24
Peak memory 206384 kb
Host smart-cfa20ec9-cad3-4ce4-8b02-9fea11de26e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
11510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3647611510
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3592936346
Short name T2309
Test name
Test status
Simulation time 7586110946 ps
CPU time 16.31 seconds
Started Jul 11 05:53:43 PM PDT 24
Finished Jul 11 05:54:01 PM PDT 24
Peak memory 206684 kb
Host smart-827d95c5-1ca4-4d33-a49b-0a7435b0a8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35929
36346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3592936346
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3857366767
Short name T2708
Test name
Test status
Simulation time 141757872 ps
CPU time 0.77 seconds
Started Jul 11 05:53:43 PM PDT 24
Finished Jul 11 05:53:45 PM PDT 24
Peak memory 206388 kb
Host smart-08b80969-898f-49ff-bf7a-a4769f3fd6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38573
66767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3857366767
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1154678625
Short name T1783
Test name
Test status
Simulation time 217542221 ps
CPU time 0.87 seconds
Started Jul 11 05:53:45 PM PDT 24
Finished Jul 11 05:53:47 PM PDT 24
Peak memory 206340 kb
Host smart-ac3e0b3a-3c76-469a-ad78-3b3048797183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11546
78625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1154678625
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1507928741
Short name T702
Test name
Test status
Simulation time 7473573986 ps
CPU time 98.94 seconds
Started Jul 11 05:53:46 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 206736 kb
Host smart-f8f8bf66-9f3d-431d-bd1d-c2381362bd04
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1507928741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1507928741
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.860854471
Short name T552
Test name
Test status
Simulation time 14459964071 ps
CPU time 284.24 seconds
Started Jul 11 05:53:48 PM PDT 24
Finished Jul 11 05:58:33 PM PDT 24
Peak memory 206708 kb
Host smart-35352438-0029-4ce7-8c5b-c1f684d57750
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=860854471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.860854471
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2118540453
Short name T2127
Test name
Test status
Simulation time 256406366 ps
CPU time 0.9 seconds
Started Jul 11 05:53:44 PM PDT 24
Finished Jul 11 05:53:45 PM PDT 24
Peak memory 206392 kb
Host smart-ea2df8c4-cff5-48e9-a7cd-ccce1919870f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
40453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2118540453
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.1632392817
Short name T831
Test name
Test status
Simulation time 161409750 ps
CPU time 0.77 seconds
Started Jul 11 05:53:46 PM PDT 24
Finished Jul 11 05:53:47 PM PDT 24
Peak memory 206388 kb
Host smart-2d0af5c6-b2eb-4357-9fb0-58929f11c6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16323
92817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.1632392817
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.77002004
Short name T653
Test name
Test status
Simulation time 187247878 ps
CPU time 0.84 seconds
Started Jul 11 05:53:49 PM PDT 24
Finished Jul 11 05:53:51 PM PDT 24
Peak memory 206404 kb
Host smart-4aebaf74-1775-41e8-92b9-4f384c176522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77002
004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.77002004
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2628758576
Short name T80
Test name
Test status
Simulation time 175145119 ps
CPU time 0.79 seconds
Started Jul 11 05:53:45 PM PDT 24
Finished Jul 11 05:53:47 PM PDT 24
Peak memory 206536 kb
Host smart-b1a124e0-bc62-4994-a1e8-5aaf3074c3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26287
58576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2628758576
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2255117450
Short name T206
Test name
Test status
Simulation time 232084972 ps
CPU time 1.05 seconds
Started Jul 11 05:53:54 PM PDT 24
Finished Jul 11 05:53:56 PM PDT 24
Peak memory 224252 kb
Host smart-28051a34-c842-4843-bb86-b4ea3be3bf91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2255117450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2255117450
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.248977598
Short name T58
Test name
Test status
Simulation time 423673566 ps
CPU time 1.35 seconds
Started Jul 11 05:53:45 PM PDT 24
Finished Jul 11 05:53:47 PM PDT 24
Peak memory 206492 kb
Host smart-773ef8cc-c2cb-4f9a-9271-27d3342e5a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
7598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.248977598
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3030611445
Short name T2425
Test name
Test status
Simulation time 261759384 ps
CPU time 0.88 seconds
Started Jul 11 05:53:44 PM PDT 24
Finished Jul 11 05:53:46 PM PDT 24
Peak memory 206388 kb
Host smart-74c92134-26d4-4d2d-ab7d-86c8cd59a26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30306
11445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3030611445
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2297910531
Short name T167
Test name
Test status
Simulation time 143724782 ps
CPU time 0.75 seconds
Started Jul 11 05:53:51 PM PDT 24
Finished Jul 11 05:53:53 PM PDT 24
Peak memory 206296 kb
Host smart-ebec645e-e291-40c0-b38b-9cf5fea9d45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
10531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2297910531
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3353058403
Short name T35
Test name
Test status
Simulation time 161174599 ps
CPU time 0.78 seconds
Started Jul 11 05:53:52 PM PDT 24
Finished Jul 11 05:53:54 PM PDT 24
Peak memory 206384 kb
Host smart-a656070b-7cda-4e8a-ab4d-73ed5e424e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33530
58403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3353058403
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2129253705
Short name T2529
Test name
Test status
Simulation time 248895836 ps
CPU time 0.96 seconds
Started Jul 11 05:53:57 PM PDT 24
Finished Jul 11 05:53:59 PM PDT 24
Peak memory 206300 kb
Host smart-6fd704c3-0e9f-443e-a151-e968b5df1105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21292
53705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2129253705
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.4102759490
Short name T2041
Test name
Test status
Simulation time 5816923210 ps
CPU time 55.03 seconds
Started Jul 11 05:53:52 PM PDT 24
Finished Jul 11 05:54:48 PM PDT 24
Peak memory 206608 kb
Host smart-ad1a2df4-c6d8-40fa-8210-860e44704f6b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4102759490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.4102759490
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3695459112
Short name T1956
Test name
Test status
Simulation time 176516610 ps
CPU time 0.76 seconds
Started Jul 11 05:53:50 PM PDT 24
Finished Jul 11 05:53:52 PM PDT 24
Peak memory 206404 kb
Host smart-581735b4-83ba-4ad4-bc7c-023af20a2f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954
59112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3695459112
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1936692295
Short name T753
Test name
Test status
Simulation time 185256722 ps
CPU time 0.78 seconds
Started Jul 11 05:53:51 PM PDT 24
Finished Jul 11 05:53:52 PM PDT 24
Peak memory 206260 kb
Host smart-7c4d88e7-b59d-4c6b-99ad-6fbf2a5fc979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19366
92295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1936692295
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.3575423275
Short name T796
Test name
Test status
Simulation time 552866042 ps
CPU time 1.45 seconds
Started Jul 11 05:53:51 PM PDT 24
Finished Jul 11 05:53:53 PM PDT 24
Peak memory 206400 kb
Host smart-c1d353d2-441a-4515-8b47-30ab0c9f6204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35754
23275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3575423275
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1326138840
Short name T1620
Test name
Test status
Simulation time 6217170795 ps
CPU time 58.27 seconds
Started Jul 11 05:53:52 PM PDT 24
Finished Jul 11 05:54:51 PM PDT 24
Peak memory 206704 kb
Host smart-29ed3037-16d5-4ae0-b98e-6fab47f294ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13261
38840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1326138840
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1712739489
Short name T846
Test name
Test status
Simulation time 48470112 ps
CPU time 0.69 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206332 kb
Host smart-f04153ca-cc4a-46b5-8041-290d25fb1f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1712739489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1712739489
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.317662203
Short name T49
Test name
Test status
Simulation time 13372625598 ps
CPU time 12.22 seconds
Started Jul 11 05:56:15 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 206560 kb
Host smart-c81e08e1-80a2-4f06-81fb-9d59345d2a6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=317662203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.317662203
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3144251350
Short name T2612
Test name
Test status
Simulation time 23478747610 ps
CPU time 28.15 seconds
Started Jul 11 05:56:11 PM PDT 24
Finished Jul 11 05:56:42 PM PDT 24
Peak memory 206648 kb
Host smart-f6310239-1b8f-4e09-9c89-f8c22f2bc335
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3144251350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.3144251350
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.571236502
Short name T697
Test name
Test status
Simulation time 166006854 ps
CPU time 0.82 seconds
Started Jul 11 05:56:14 PM PDT 24
Finished Jul 11 05:56:17 PM PDT 24
Peak memory 206328 kb
Host smart-317540cb-e3cb-4fd0-97b0-dac085150497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57123
6502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.571236502
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1830906276
Short name T2551
Test name
Test status
Simulation time 159888757 ps
CPU time 0.82 seconds
Started Jul 11 05:56:10 PM PDT 24
Finished Jul 11 05:56:13 PM PDT 24
Peak memory 206384 kb
Host smart-4f963d4c-c2b6-4286-8a99-830876c8d5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18309
06276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1830906276
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3307954298
Short name T29
Test name
Test status
Simulation time 353793475 ps
CPU time 0.99 seconds
Started Jul 11 05:56:12 PM PDT 24
Finished Jul 11 05:56:16 PM PDT 24
Peak memory 206388 kb
Host smart-da26b15d-f090-4444-9ab3-4b6ce7ff9931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33079
54298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3307954298
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1927468036
Short name T1553
Test name
Test status
Simulation time 7713813968 ps
CPU time 14.63 seconds
Started Jul 11 05:56:11 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 206696 kb
Host smart-169b33ee-e722-4223-bb51-9ddcdc81912f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19274
68036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1927468036
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1237656396
Short name T2654
Test name
Test status
Simulation time 426937150 ps
CPU time 1.43 seconds
Started Jul 11 05:56:12 PM PDT 24
Finished Jul 11 05:56:16 PM PDT 24
Peak memory 206392 kb
Host smart-80c5f39e-7e46-4aa5-8584-301f5982256a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12376
56396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1237656396
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1034736725
Short name T1944
Test name
Test status
Simulation time 137627508 ps
CPU time 0.76 seconds
Started Jul 11 05:56:16 PM PDT 24
Finished Jul 11 05:56:19 PM PDT 24
Peak memory 206384 kb
Host smart-5e388329-8532-4579-a0d1-ce356eab2b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10347
36725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1034736725
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.2061411397
Short name T672
Test name
Test status
Simulation time 29057186 ps
CPU time 0.67 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206348 kb
Host smart-4cc186b7-f0f1-443d-8677-6936eb0d66d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
11397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2061411397
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.114299693
Short name T614
Test name
Test status
Simulation time 1006404546 ps
CPU time 2.32 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:56:22 PM PDT 24
Peak memory 206668 kb
Host smart-7e38a6f7-3f25-401f-8b2b-bc196b48c1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11429
9693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.114299693
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2945937641
Short name T1725
Test name
Test status
Simulation time 258273229 ps
CPU time 1.9 seconds
Started Jul 11 05:56:21 PM PDT 24
Finished Jul 11 05:56:27 PM PDT 24
Peak memory 206640 kb
Host smart-04bf2f3c-ba26-4e02-9d0c-4cba2eefa171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29459
37641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2945937641
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.707549571
Short name T766
Test name
Test status
Simulation time 170164973 ps
CPU time 0.78 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206288 kb
Host smart-f02b8760-5720-43f9-9470-2ccdb1e4a295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70754
9571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.707549571
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1765126512
Short name T744
Test name
Test status
Simulation time 211335705 ps
CPU time 0.8 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206384 kb
Host smart-9395b1b8-cc89-4d07-a56e-13cd1fcd3775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17651
26512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1765126512
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.123519973
Short name T1027
Test name
Test status
Simulation time 165746720 ps
CPU time 0.8 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206284 kb
Host smart-3c5c5cd1-d2d7-4150-83fb-a5c45bddda66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12351
9973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.123519973
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1870216329
Short name T1128
Test name
Test status
Simulation time 12522361286 ps
CPU time 50.44 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:57:15 PM PDT 24
Peak memory 206640 kb
Host smart-544ecba6-efe9-45f7-963a-b009e889ba5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
16329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1870216329
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3449219310
Short name T1885
Test name
Test status
Simulation time 171377017 ps
CPU time 0.82 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:25 PM PDT 24
Peak memory 206368 kb
Host smart-735dadfb-b108-4891-bd2a-1162618d30df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34492
19310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3449219310
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2801943036
Short name T737
Test name
Test status
Simulation time 23306963148 ps
CPU time 24.03 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 206452 kb
Host smart-f7a009bc-297d-43c7-9851-21db5896480a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28019
43036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2801943036
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1038774757
Short name T2608
Test name
Test status
Simulation time 3315238956 ps
CPU time 3.76 seconds
Started Jul 11 05:56:22 PM PDT 24
Finished Jul 11 05:56:31 PM PDT 24
Peak memory 206376 kb
Host smart-2e945e7b-d395-451c-9d90-b0a9ed70d568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10387
74757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1038774757
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2575427578
Short name T958
Test name
Test status
Simulation time 6905380909 ps
CPU time 64.53 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206620 kb
Host smart-b7a95504-2748-4e7b-8b96-6ffed855aad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25754
27578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2575427578
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1610317984
Short name T2621
Test name
Test status
Simulation time 7210791549 ps
CPU time 52.6 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:57:26 PM PDT 24
Peak memory 206656 kb
Host smart-9cf8437b-c9b7-4bca-8b2b-c84a5a0f2d4f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1610317984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1610317984
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2001795733
Short name T821
Test name
Test status
Simulation time 279930311 ps
CPU time 0.91 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:56:20 PM PDT 24
Peak memory 206328 kb
Host smart-ab4a413c-1901-4959-8a0a-e2a298d7f737
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2001795733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2001795733
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2358303650
Short name T2097
Test name
Test status
Simulation time 193495252 ps
CPU time 0.87 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206388 kb
Host smart-cd6f6455-6e51-492e-91aa-c31b15dfce30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23583
03650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2358303650
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2576074441
Short name T791
Test name
Test status
Simulation time 3918917864 ps
CPU time 37.48 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:57:01 PM PDT 24
Peak memory 206652 kb
Host smart-1ee4b538-7301-4cff-b0a9-fbe1791a0843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25760
74441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2576074441
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1439522188
Short name T2410
Test name
Test status
Simulation time 5648949157 ps
CPU time 161.01 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:59:04 PM PDT 24
Peak memory 206632 kb
Host smart-8bbbe678-b996-4406-ad45-b5c01add3efd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1439522188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1439522188
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3051016998
Short name T1287
Test name
Test status
Simulation time 157669845 ps
CPU time 0.78 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:25 PM PDT 24
Peak memory 206356 kb
Host smart-84cbb58f-acf4-42af-817c-9a72ef778910
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3051016998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3051016998
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1022520228
Short name T2239
Test name
Test status
Simulation time 147091738 ps
CPU time 0.79 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:25 PM PDT 24
Peak memory 206388 kb
Host smart-43f04ad1-0cac-4704-be0a-b8b7b7736294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10225
20228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1022520228
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.4262275048
Short name T2293
Test name
Test status
Simulation time 206985253 ps
CPU time 0.9 seconds
Started Jul 11 05:56:23 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 206308 kb
Host smart-8bde023a-0a01-40c3-9a2f-e3e73aa125dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42622
75048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.4262275048
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2007544996
Short name T2401
Test name
Test status
Simulation time 174045338 ps
CPU time 0.88 seconds
Started Jul 11 05:56:38 PM PDT 24
Finished Jul 11 05:56:42 PM PDT 24
Peak memory 206320 kb
Host smart-c4f5b807-d253-4da0-be47-8eb1a4d5b827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20075
44996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2007544996
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3631229965
Short name T2271
Test name
Test status
Simulation time 162626919 ps
CPU time 0.72 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:56:34 PM PDT 24
Peak memory 206308 kb
Host smart-73d6a14c-419f-482e-9cdf-35d7a4e552e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36312
29965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3631229965
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1172365443
Short name T168
Test name
Test status
Simulation time 173970426 ps
CPU time 0.82 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:56:23 PM PDT 24
Peak memory 206376 kb
Host smart-ce65e58b-f1ff-47d7-9123-3c24ff732539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
65443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1172365443
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3478574297
Short name T433
Test name
Test status
Simulation time 210500704 ps
CPU time 0.98 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:56:34 PM PDT 24
Peak memory 206304 kb
Host smart-31513826-d4de-436f-be78-4339166441e8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3478574297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3478574297
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1509386798
Short name T2528
Test name
Test status
Simulation time 153899811 ps
CPU time 0.77 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206292 kb
Host smart-ad33e258-2035-4467-aa94-e50d1fa0b4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
86798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1509386798
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1987512252
Short name T1790
Test name
Test status
Simulation time 41584761 ps
CPU time 0.66 seconds
Started Jul 11 05:56:18 PM PDT 24
Finished Jul 11 05:56:22 PM PDT 24
Peak memory 206376 kb
Host smart-f0d1310d-e61f-4f49-b802-aa7d77c8fafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19875
12252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1987512252
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.690908582
Short name T427
Test name
Test status
Simulation time 166831847 ps
CPU time 0.79 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206356 kb
Host smart-bc541d24-9675-4cc9-b6b0-2f987f100f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69090
8582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.690908582
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1219516783
Short name T2109
Test name
Test status
Simulation time 212766975 ps
CPU time 0.89 seconds
Started Jul 11 05:56:22 PM PDT 24
Finished Jul 11 05:56:28 PM PDT 24
Peak memory 206372 kb
Host smart-35c0f83c-5553-4288-b1df-3227f914e4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12195
16783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1219516783
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.589806994
Short name T1413
Test name
Test status
Simulation time 261030524 ps
CPU time 0.89 seconds
Started Jul 11 05:56:22 PM PDT 24
Finished Jul 11 05:56:28 PM PDT 24
Peak memory 206384 kb
Host smart-6f016919-7e08-4b33-ae27-36f8a9920b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58980
6994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.589806994
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3636895183
Short name T570
Test name
Test status
Simulation time 195827423 ps
CPU time 0.79 seconds
Started Jul 11 05:56:21 PM PDT 24
Finished Jul 11 05:56:26 PM PDT 24
Peak memory 206380 kb
Host smart-8a3a6a99-c032-44d5-a85d-e543381f8633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368
95183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3636895183
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.9334512
Short name T2423
Test name
Test status
Simulation time 168243620 ps
CPU time 0.78 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206384 kb
Host smart-b4169873-21d0-400d-9043-2c92b482f118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93345
12 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.9334512
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2376346468
Short name T2364
Test name
Test status
Simulation time 148806373 ps
CPU time 0.78 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:56:23 PM PDT 24
Peak memory 206312 kb
Host smart-5c76896d-2f34-4051-85d9-ce99f675a5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23763
46468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2376346468
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3673008677
Short name T556
Test name
Test status
Simulation time 223142850 ps
CPU time 0.88 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:56:20 PM PDT 24
Peak memory 206540 kb
Host smart-dd46b1bd-8609-4c73-be9a-7a671ec155e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36730
08677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3673008677
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2764304417
Short name T1123
Test name
Test status
Simulation time 6295651925 ps
CPU time 55.82 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:57:29 PM PDT 24
Peak memory 206588 kb
Host smart-96a6dd1b-68c6-4c03-8ccb-fda70b313d65
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2764304417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2764304417
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2068300324
Short name T2318
Test name
Test status
Simulation time 173017342 ps
CPU time 0.81 seconds
Started Jul 11 05:56:20 PM PDT 24
Finished Jul 11 05:56:26 PM PDT 24
Peak memory 206360 kb
Host smart-39c5315f-e65a-46c8-8c47-b05eff17baa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20683
00324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2068300324
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3995243392
Short name T1616
Test name
Test status
Simulation time 178590194 ps
CPU time 0.75 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:56:34 PM PDT 24
Peak memory 206300 kb
Host smart-8f428b5a-76f5-41d6-9629-63a2eff500a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39952
43392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3995243392
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1080334055
Short name T497
Test name
Test status
Simulation time 1087182315 ps
CPU time 2.6 seconds
Started Jul 11 05:56:22 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 206640 kb
Host smart-8f4d5921-0fc0-4183-883c-8bba85fc0c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
34055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1080334055
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1151766063
Short name T2607
Test name
Test status
Simulation time 2941793587 ps
CPU time 21.96 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:56:45 PM PDT 24
Peak memory 206612 kb
Host smart-35dc2b18-c9ac-4546-85a6-4621331555af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11517
66063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1151766063
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1772162239
Short name T2001
Test name
Test status
Simulation time 30854619 ps
CPU time 0.67 seconds
Started Jul 11 05:56:32 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 206412 kb
Host smart-65d2b7da-d9b7-4717-8e1a-9de364c3474f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1772162239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1772162239
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2593255807
Short name T1830
Test name
Test status
Simulation time 3434644986 ps
CPU time 4.63 seconds
Started Jul 11 05:56:18 PM PDT 24
Finished Jul 11 05:56:26 PM PDT 24
Peak memory 206440 kb
Host smart-5098c869-6a6c-45cd-a807-c3b955ac4261
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2593255807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.2593255807
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1716356468
Short name T2341
Test name
Test status
Simulation time 13368268240 ps
CPU time 13.55 seconds
Started Jul 11 05:56:21 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206464 kb
Host smart-aa6e4a8e-9e3c-4304-85dc-0b0ce00f4081
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1716356468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1716356468
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.4122959873
Short name T2640
Test name
Test status
Simulation time 23390112322 ps
CPU time 22.31 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:56:52 PM PDT 24
Peak memory 206468 kb
Host smart-c4d38014-44d8-480a-ae60-795d202f4818
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4122959873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.4122959873
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1423248985
Short name T2457
Test name
Test status
Simulation time 217512206 ps
CPU time 0.85 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:56:30 PM PDT 24
Peak memory 206328 kb
Host smart-1417c713-80f9-460f-9f45-f7474cd2eae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14232
48985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1423248985
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1098117416
Short name T2191
Test name
Test status
Simulation time 159669693 ps
CPU time 0.83 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:56:35 PM PDT 24
Peak memory 206364 kb
Host smart-c473e5a9-ed09-47c7-8a73-1b0b9d98d2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10981
17416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1098117416
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3772439860
Short name T258
Test name
Test status
Simulation time 248654593 ps
CPU time 0.95 seconds
Started Jul 11 05:56:21 PM PDT 24
Finished Jul 11 05:56:26 PM PDT 24
Peak memory 206300 kb
Host smart-39d06a6e-9e64-425a-9ef9-523e6c3c8046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37724
39860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3772439860
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.4217777013
Short name T750
Test name
Test status
Simulation time 1286191513 ps
CPU time 2.94 seconds
Started Jul 11 05:56:26 PM PDT 24
Finished Jul 11 05:56:35 PM PDT 24
Peak memory 206636 kb
Host smart-c57b9c63-7cf2-46c9-8376-5e7f28dad669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42177
77013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.4217777013
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1373437435
Short name T1526
Test name
Test status
Simulation time 15948499918 ps
CPU time 30.26 seconds
Started Jul 11 05:56:26 PM PDT 24
Finished Jul 11 05:57:02 PM PDT 24
Peak memory 206688 kb
Host smart-3bc06d77-32c4-4e36-8e69-2a0b9ff9543e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
37435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1373437435
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.996215143
Short name T1807
Test name
Test status
Simulation time 404934909 ps
CPU time 1.37 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:56:31 PM PDT 24
Peak memory 206392 kb
Host smart-5d3fc553-e055-4f1c-8ee9-fd73158cca8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99621
5143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.996215143
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3424856699
Short name T721
Test name
Test status
Simulation time 142593099 ps
CPU time 0.77 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:56:31 PM PDT 24
Peak memory 206372 kb
Host smart-edfdb61f-9c11-40cd-9f56-4614c36039f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
56699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3424856699
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.854456573
Short name T1549
Test name
Test status
Simulation time 40017234 ps
CPU time 0.64 seconds
Started Jul 11 05:56:25 PM PDT 24
Finished Jul 11 05:56:31 PM PDT 24
Peak memory 206280 kb
Host smart-cae1f9bf-a129-48bd-beb5-1dcb83059cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85445
6573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.854456573
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3241683169
Short name T2691
Test name
Test status
Simulation time 937946693 ps
CPU time 2.41 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:56:32 PM PDT 24
Peak memory 206644 kb
Host smart-127123a1-b6fc-49ed-8642-9b19b1290768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32416
83169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3241683169
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3187855830
Short name T1288
Test name
Test status
Simulation time 174622275 ps
CPU time 1.86 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:56:35 PM PDT 24
Peak memory 206588 kb
Host smart-9c33e5da-deee-409c-a054-e34ee82c403e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31878
55830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3187855830
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2619125848
Short name T2237
Test name
Test status
Simulation time 213176742 ps
CPU time 0.91 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:56:31 PM PDT 24
Peak memory 206296 kb
Host smart-0eb1050e-d2c6-499a-ba15-1706363bde3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26191
25848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2619125848
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3957435322
Short name T2604
Test name
Test status
Simulation time 168110339 ps
CPU time 0.76 seconds
Started Jul 11 05:56:23 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 206348 kb
Host smart-33d8d54d-55fe-4c52-87ee-06745bcfd42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39574
35322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3957435322
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2905431391
Short name T546
Test name
Test status
Simulation time 220409512 ps
CPU time 0.89 seconds
Started Jul 11 05:56:26 PM PDT 24
Finished Jul 11 05:56:32 PM PDT 24
Peak memory 206304 kb
Host smart-98d4d86c-e096-4bce-a9c5-ddefba108f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29054
31391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2905431391
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3261494581
Short name T1398
Test name
Test status
Simulation time 7071691969 ps
CPU time 49.29 seconds
Started Jul 11 05:56:25 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206700 kb
Host smart-f4344a06-2d75-4194-a642-afd7c7f68832
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3261494581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3261494581
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.2046663001
Short name T474
Test name
Test status
Simulation time 7608945097 ps
CPU time 29.6 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:57:00 PM PDT 24
Peak memory 206628 kb
Host smart-bb8e0feb-5431-4d78-975c-3a6d9b5a4068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20466
63001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.2046663001
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.822430075
Short name T2432
Test name
Test status
Simulation time 233513388 ps
CPU time 0.97 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:56:31 PM PDT 24
Peak memory 206372 kb
Host smart-3e94866e-ba18-403e-b6c5-90de50a22859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82243
0075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.822430075
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.77034491
Short name T1389
Test name
Test status
Simulation time 23336134857 ps
CPU time 21.48 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:56:55 PM PDT 24
Peak memory 206360 kb
Host smart-a9eba634-ea50-4bf3-887c-7a4e23966448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77034
491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.77034491
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1018553139
Short name T2053
Test name
Test status
Simulation time 3292944698 ps
CPU time 3.95 seconds
Started Jul 11 05:56:29 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206420 kb
Host smart-21211fd9-6451-4150-b4b6-c801e841a753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10185
53139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1018553139
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3109391400
Short name T486
Test name
Test status
Simulation time 6109373754 ps
CPU time 43.75 seconds
Started Jul 11 05:56:23 PM PDT 24
Finished Jul 11 05:57:12 PM PDT 24
Peak memory 206752 kb
Host smart-db99aa1c-912e-454a-b8ce-5846cc63aa96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31093
91400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3109391400
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.15510971
Short name T332
Test name
Test status
Simulation time 4105712803 ps
CPU time 109.92 seconds
Started Jul 11 05:56:22 PM PDT 24
Finished Jul 11 05:58:17 PM PDT 24
Peak memory 206572 kb
Host smart-99e5b152-c28e-4c3d-a32d-062690827cc6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=15510971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.15510971
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1982667443
Short name T2493
Test name
Test status
Simulation time 234526699 ps
CPU time 0.89 seconds
Started Jul 11 05:56:26 PM PDT 24
Finished Jul 11 05:56:32 PM PDT 24
Peak memory 206300 kb
Host smart-6b2a1d78-12b2-4628-931d-1ab2adc404c7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1982667443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1982667443
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3219324365
Short name T1409
Test name
Test status
Simulation time 209160023 ps
CPU time 0.85 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:56:30 PM PDT 24
Peak memory 206388 kb
Host smart-c4f8af77-1a28-4a05-ad60-40b4c6a217dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32193
24365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3219324365
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.4328773
Short name T485
Test name
Test status
Simulation time 5992982302 ps
CPU time 167.18 seconds
Started Jul 11 05:56:25 PM PDT 24
Finished Jul 11 05:59:17 PM PDT 24
Peak memory 206672 kb
Host smart-e415fd0e-a749-489a-b8f6-d1126a08396c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43287
73 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.4328773
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.65356187
Short name T2202
Test name
Test status
Simulation time 4126141984 ps
CPU time 38.97 seconds
Started Jul 11 05:56:24 PM PDT 24
Finished Jul 11 05:57:09 PM PDT 24
Peak memory 206724 kb
Host smart-4b951eed-3412-403b-b378-1a91749b023a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=65356187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.65356187
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2414463643
Short name T1706
Test name
Test status
Simulation time 167516589 ps
CPU time 0.78 seconds
Started Jul 11 05:56:25 PM PDT 24
Finished Jul 11 05:56:32 PM PDT 24
Peak memory 206384 kb
Host smart-dd11f9bf-8432-4d53-9e06-bfb34b04467a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2414463643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2414463643
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.4235623167
Short name T2613
Test name
Test status
Simulation time 144042667 ps
CPU time 0.78 seconds
Started Jul 11 05:56:23 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 206400 kb
Host smart-18777da4-07bb-4fa6-8df8-8d142606de6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42356
23167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.4235623167
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2049804378
Short name T1673
Test name
Test status
Simulation time 226938705 ps
CPU time 0.92 seconds
Started Jul 11 05:56:29 PM PDT 24
Finished Jul 11 05:56:36 PM PDT 24
Peak memory 206380 kb
Host smart-90c812be-dea6-4ed4-9277-83484fc5a270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20498
04378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2049804378
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.4264397007
Short name T2014
Test name
Test status
Simulation time 221319667 ps
CPU time 0.88 seconds
Started Jul 11 05:56:22 PM PDT 24
Finished Jul 11 05:56:28 PM PDT 24
Peak memory 206532 kb
Host smart-d5478df8-e495-4539-a6ab-d555f2fe27fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42643
97007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.4264397007
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2374674560
Short name T340
Test name
Test status
Simulation time 173470263 ps
CPU time 0.78 seconds
Started Jul 11 05:56:30 PM PDT 24
Finished Jul 11 05:56:36 PM PDT 24
Peak memory 206292 kb
Host smart-49934b1e-46df-44b3-88c3-12dbde9a971d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23746
74560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2374674560
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1977509376
Short name T1369
Test name
Test status
Simulation time 175723904 ps
CPU time 0.83 seconds
Started Jul 11 05:56:29 PM PDT 24
Finished Jul 11 05:56:35 PM PDT 24
Peak memory 206392 kb
Host smart-a5186368-6bdc-4d7c-baf8-80881fde533c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19775
09376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1977509376
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.127967644
Short name T1219
Test name
Test status
Simulation time 145451327 ps
CPU time 0.76 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206292 kb
Host smart-b5fe52ee-8f3c-4337-adc7-76636b509be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12796
7644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.127967644
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3960920555
Short name T1450
Test name
Test status
Simulation time 213370845 ps
CPU time 0.86 seconds
Started Jul 11 05:56:29 PM PDT 24
Finished Jul 11 05:56:36 PM PDT 24
Peak memory 206280 kb
Host smart-6b660cc6-d801-4590-8fba-7beb3a822f65
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3960920555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3960920555
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2550487225
Short name T2061
Test name
Test status
Simulation time 140994650 ps
CPU time 0.76 seconds
Started Jul 11 05:56:33 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206376 kb
Host smart-2c970f75-f40d-4c59-93bc-26c2778c480f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25504
87225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2550487225
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.285042600
Short name T1589
Test name
Test status
Simulation time 35825955 ps
CPU time 0.69 seconds
Started Jul 11 05:56:31 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 206296 kb
Host smart-ff83a7c0-b61f-4040-8fed-a25e1e5677a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28504
2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.285042600
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.786844620
Short name T2598
Test name
Test status
Simulation time 7405132893 ps
CPU time 15.8 seconds
Started Jul 11 05:56:32 PM PDT 24
Finished Jul 11 05:56:52 PM PDT 24
Peak memory 206668 kb
Host smart-c74cf2d1-361a-439c-9722-130e42a19e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78684
4620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.786844620
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1617439571
Short name T1074
Test name
Test status
Simulation time 218045083 ps
CPU time 0.93 seconds
Started Jul 11 05:56:31 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 206400 kb
Host smart-641a32a5-36bb-4a5e-8a0d-39cdcabfd45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16174
39571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1617439571
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.953086002
Short name T1214
Test name
Test status
Simulation time 176780016 ps
CPU time 0.87 seconds
Started Jul 11 05:56:26 PM PDT 24
Finished Jul 11 05:56:33 PM PDT 24
Peak memory 206392 kb
Host smart-ffe947e8-4576-4bc6-a71c-7d2bf62a9fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95308
6002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.953086002
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3708036648
Short name T22
Test name
Test status
Simulation time 170046614 ps
CPU time 0.81 seconds
Started Jul 11 05:56:31 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 206360 kb
Host smart-cf20b05b-273d-48df-9815-9c093f6085f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37080
36648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3708036648
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2769143686
Short name T2527
Test name
Test status
Simulation time 186448841 ps
CPU time 0.87 seconds
Started Jul 11 05:56:31 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 206384 kb
Host smart-5461e69b-99d9-4b90-bd85-f2d133f8c6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27691
43686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2769143686
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3979953633
Short name T165
Test name
Test status
Simulation time 150784630 ps
CPU time 0.77 seconds
Started Jul 11 05:56:33 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206388 kb
Host smart-6bc2ea7e-3704-456d-bfd1-6641e48a74e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39799
53633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3979953633
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2131787395
Short name T102
Test name
Test status
Simulation time 174058307 ps
CPU time 0.79 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206288 kb
Host smart-e68430f2-7c38-4427-8a8c-a832471df0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21317
87395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2131787395
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2728308342
Short name T1177
Test name
Test status
Simulation time 195777708 ps
CPU time 0.86 seconds
Started Jul 11 05:56:29 PM PDT 24
Finished Jul 11 05:56:36 PM PDT 24
Peak memory 206380 kb
Host smart-d143e123-c685-4cdf-a06c-724cec6eb4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27283
08342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2728308342
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.569488953
Short name T2178
Test name
Test status
Simulation time 5851703932 ps
CPU time 46.84 seconds
Started Jul 11 05:56:30 PM PDT 24
Finished Jul 11 05:57:22 PM PDT 24
Peak memory 206720 kb
Host smart-89f96d3e-5adb-4400-adfc-fb94f0d614c8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=569488953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.569488953
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.4096179194
Short name T495
Test name
Test status
Simulation time 190310239 ps
CPU time 0.83 seconds
Started Jul 11 05:56:47 PM PDT 24
Finished Jul 11 05:56:51 PM PDT 24
Peak memory 206324 kb
Host smart-ce0084c4-d02e-4177-8cec-4e15f7a18725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40961
79194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.4096179194
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3502837324
Short name T2563
Test name
Test status
Simulation time 187093351 ps
CPU time 0.8 seconds
Started Jul 11 05:56:33 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206340 kb
Host smart-1c6dce6e-fdc8-4967-b6bd-354921b42f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35028
37324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3502837324
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.1728920653
Short name T1186
Test name
Test status
Simulation time 1391574268 ps
CPU time 2.79 seconds
Started Jul 11 05:56:28 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 206624 kb
Host smart-53f7a411-32d5-45ed-919e-ff6b826c4393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
20653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.1728920653
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1036178491
Short name T1772
Test name
Test status
Simulation time 4014148780 ps
CPU time 37.85 seconds
Started Jul 11 05:56:33 PM PDT 24
Finished Jul 11 05:57:15 PM PDT 24
Peak memory 206656 kb
Host smart-db19f296-8d1f-486b-9758-bdd8fbb466e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10361
78491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1036178491
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2452436380
Short name T876
Test name
Test status
Simulation time 41073613 ps
CPU time 0.66 seconds
Started Jul 11 05:56:39 PM PDT 24
Finished Jul 11 05:56:43 PM PDT 24
Peak memory 206424 kb
Host smart-ea39ad44-9e81-471d-aeea-6b9c1943117e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2452436380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2452436380
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3118708064
Short name T1087
Test name
Test status
Simulation time 4157736235 ps
CPU time 4.57 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:56:43 PM PDT 24
Peak memory 206468 kb
Host smart-97b5e58a-9c3f-451a-81ee-6fc8ba31d8bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3118708064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.3118708064
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.151918821
Short name T1422
Test name
Test status
Simulation time 23330629567 ps
CPU time 22.21 seconds
Started Jul 11 06:06:39 PM PDT 24
Finished Jul 11 06:07:03 PM PDT 24
Peak memory 206712 kb
Host smart-db9c3df0-dba1-44fd-8123-d1a91f047f04
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=151918821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.151918821
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1770710405
Short name T804
Test name
Test status
Simulation time 146600346 ps
CPU time 0.8 seconds
Started Jul 11 05:56:36 PM PDT 24
Finished Jul 11 05:56:40 PM PDT 24
Peak memory 206388 kb
Host smart-b5650170-a89c-4415-a167-1d7e6617aa42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17707
10405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1770710405
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.4036603234
Short name T798
Test name
Test status
Simulation time 147069091 ps
CPU time 0.76 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206404 kb
Host smart-c737a5db-89af-4b25-b2a7-f34b0074e9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366
03234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.4036603234
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1514326871
Short name T1062
Test name
Test status
Simulation time 344603625 ps
CPU time 1.24 seconds
Started Jul 11 05:56:43 PM PDT 24
Finished Jul 11 05:56:47 PM PDT 24
Peak memory 206372 kb
Host smart-0d67bf74-33f6-4014-8012-e04bdc44fc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15143
26871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1514326871
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1699404138
Short name T2175
Test name
Test status
Simulation time 455749387 ps
CPU time 1.21 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206388 kb
Host smart-be700711-01cb-40b2-a5d5-e9c1d55bd068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16994
04138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1699404138
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.2231516158
Short name T768
Test name
Test status
Simulation time 22195067740 ps
CPU time 48.09 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:57:26 PM PDT 24
Peak memory 206588 kb
Host smart-3e004688-6d0b-42cd-9fff-ca6f1842e710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22315
16158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2231516158
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.199819721
Short name T1311
Test name
Test status
Simulation time 353995993 ps
CPU time 1.18 seconds
Started Jul 11 05:56:33 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206388 kb
Host smart-7715a1bb-4d22-4574-b537-2dea2a726953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.199819721
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.4135981045
Short name T2382
Test name
Test status
Simulation time 133955078 ps
CPU time 0.76 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:56:48 PM PDT 24
Peak memory 206328 kb
Host smart-e550ae3d-a1c1-4cc4-a50c-43200f55f263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41359
81045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.4135981045
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2439042857
Short name T840
Test name
Test status
Simulation time 37411669 ps
CPU time 0.66 seconds
Started Jul 11 05:56:38 PM PDT 24
Finished Jul 11 05:56:42 PM PDT 24
Peak memory 206388 kb
Host smart-9a4f26f2-90a5-4b17-ace6-eb51720c0a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24390
42857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2439042857
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3015535200
Short name T752
Test name
Test status
Simulation time 919644055 ps
CPU time 2.06 seconds
Started Jul 11 05:56:33 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206512 kb
Host smart-f3e39331-6148-4e8f-ba09-5cac47b93b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30155
35200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3015535200
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1593776554
Short name T1535
Test name
Test status
Simulation time 287767687 ps
CPU time 1.65 seconds
Started Jul 11 05:56:36 PM PDT 24
Finished Jul 11 05:56:41 PM PDT 24
Peak memory 206600 kb
Host smart-67f60050-378f-4f19-91b7-81f8fa302429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
76554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1593776554
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3888355388
Short name T2013
Test name
Test status
Simulation time 270001369 ps
CPU time 0.9 seconds
Started Jul 11 05:56:36 PM PDT 24
Finished Jul 11 05:56:41 PM PDT 24
Peak memory 206344 kb
Host smart-1cd74e98-eee3-45c9-885f-da8512041615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38883
55388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3888355388
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3531688692
Short name T977
Test name
Test status
Simulation time 175595273 ps
CPU time 0.83 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:56:47 PM PDT 24
Peak memory 206396 kb
Host smart-37df6048-6915-4730-af5a-06780bc1b098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35316
88692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3531688692
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2589329393
Short name T1906
Test name
Test status
Simulation time 147047918 ps
CPU time 0.79 seconds
Started Jul 11 05:56:39 PM PDT 24
Finished Jul 11 05:56:43 PM PDT 24
Peak memory 206388 kb
Host smart-caa19913-a065-42c2-8b75-bcec7e781f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25893
29393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2589329393
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1208537707
Short name T1385
Test name
Test status
Simulation time 205056829 ps
CPU time 0.84 seconds
Started Jul 11 05:56:32 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 206388 kb
Host smart-d355475e-6f2b-414c-b33a-7b701c258bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
37707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1208537707
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.593623668
Short name T2324
Test name
Test status
Simulation time 23326531673 ps
CPU time 24.28 seconds
Started Jul 11 05:56:36 PM PDT 24
Finished Jul 11 05:57:04 PM PDT 24
Peak memory 206448 kb
Host smart-6e253540-28ce-42da-94d7-c54b9c144579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59362
3668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.593623668
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.589875057
Short name T651
Test name
Test status
Simulation time 3274903379 ps
CPU time 3.51 seconds
Started Jul 11 05:56:51 PM PDT 24
Finished Jul 11 05:56:58 PM PDT 24
Peak memory 206384 kb
Host smart-50bb50c6-373a-41d8-8269-e241be687d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58987
5057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.589875057
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.674001440
Short name T1485
Test name
Test status
Simulation time 6891481344 ps
CPU time 64.89 seconds
Started Jul 11 05:56:35 PM PDT 24
Finished Jul 11 05:57:44 PM PDT 24
Peak memory 206696 kb
Host smart-df53d00b-f1ce-45ba-afb8-6a17bbda7315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67400
1440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.674001440
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3870440569
Short name T965
Test name
Test status
Simulation time 5701107734 ps
CPU time 40.5 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:57:18 PM PDT 24
Peak memory 206628 kb
Host smart-9d0cd066-8afb-47eb-bcf6-83f3edbc8f86
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3870440569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3870440569
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1424380193
Short name T1810
Test name
Test status
Simulation time 248707472 ps
CPU time 0.87 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206384 kb
Host smart-b5ae489b-32be-41f6-9643-1042fba6f4cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1424380193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1424380193
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1227393290
Short name T349
Test name
Test status
Simulation time 195307675 ps
CPU time 0.87 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206332 kb
Host smart-c3235b83-2b8a-4f73-9fec-49a68793cf9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12273
93290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1227393290
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.148708874
Short name T1874
Test name
Test status
Simulation time 3291155771 ps
CPU time 30.52 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:57:18 PM PDT 24
Peak memory 206656 kb
Host smart-ece31caf-b375-4523-ad33-7d91e05d0b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14870
8874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.148708874
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.4176809299
Short name T1695
Test name
Test status
Simulation time 5324154137 ps
CPU time 148.76 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:59:15 PM PDT 24
Peak memory 206624 kb
Host smart-17bd698c-910b-48bc-97ba-b1710f82dd44
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4176809299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.4176809299
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.355732393
Short name T1340
Test name
Test status
Simulation time 153150922 ps
CPU time 0.75 seconds
Started Jul 11 05:56:36 PM PDT 24
Finished Jul 11 05:56:40 PM PDT 24
Peak memory 206420 kb
Host smart-04933285-9a84-4e11-ad1a-659e4f7aba82
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=355732393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.355732393
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1575740131
Short name T1928
Test name
Test status
Simulation time 149621388 ps
CPU time 0.77 seconds
Started Jul 11 05:56:33 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206296 kb
Host smart-cd5f1cc8-ce6f-429f-82fc-204c47ef3c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15757
40131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1575740131
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3613525005
Short name T1759
Test name
Test status
Simulation time 200329913 ps
CPU time 0.88 seconds
Started Jul 11 05:56:34 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206376 kb
Host smart-3c29fc49-84f7-4c3e-91f9-39f0531680e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36135
25005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3613525005
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.1938145942
Short name T1800
Test name
Test status
Simulation time 172292011 ps
CPU time 0.8 seconds
Started Jul 11 05:56:37 PM PDT 24
Finished Jul 11 05:56:41 PM PDT 24
Peak memory 206328 kb
Host smart-9a244507-6c31-4cd7-bbfb-2f4f12c60ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19381
45942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1938145942
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.159294206
Short name T2620
Test name
Test status
Simulation time 156237382 ps
CPU time 0.85 seconds
Started Jul 11 05:56:39 PM PDT 24
Finished Jul 11 05:56:43 PM PDT 24
Peak memory 206384 kb
Host smart-3589cdc0-2d6a-4d65-88e5-3219b13e6a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15929
4206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.159294206
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.912844278
Short name T1896
Test name
Test status
Simulation time 171684652 ps
CPU time 0.78 seconds
Started Jul 11 05:56:42 PM PDT 24
Finished Jul 11 05:56:45 PM PDT 24
Peak memory 206384 kb
Host smart-e89ae984-53ae-44bf-bcf2-78ca6c42eb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91284
4278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.912844278
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2180407965
Short name T912
Test name
Test status
Simulation time 158189287 ps
CPU time 0.81 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:56:47 PM PDT 24
Peak memory 206332 kb
Host smart-dfed414d-cd50-465d-ba83-f4e83cbf0ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21804
07965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2180407965
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3995125218
Short name T163
Test name
Test status
Simulation time 208230303 ps
CPU time 0.82 seconds
Started Jul 11 05:56:41 PM PDT 24
Finished Jul 11 05:56:44 PM PDT 24
Peak memory 206272 kb
Host smart-f46b2673-e1a1-433a-a721-f97de6194418
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3995125218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3995125218
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3501089092
Short name T616
Test name
Test status
Simulation time 167920454 ps
CPU time 0.84 seconds
Started Jul 11 05:56:54 PM PDT 24
Finished Jul 11 05:56:59 PM PDT 24
Peak memory 206400 kb
Host smart-fbddd1a8-a522-40a7-9440-20eb3720a4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35010
89092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3501089092
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3890925031
Short name T980
Test name
Test status
Simulation time 11761792511 ps
CPU time 27.28 seconds
Started Jul 11 05:56:43 PM PDT 24
Finished Jul 11 05:57:12 PM PDT 24
Peak memory 206752 kb
Host smart-faa02afc-0f1d-49d2-ba40-90aa3e813b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38909
25031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3890925031
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1070853262
Short name T361
Test name
Test status
Simulation time 179255237 ps
CPU time 0.89 seconds
Started Jul 11 05:56:40 PM PDT 24
Finished Jul 11 05:56:44 PM PDT 24
Peak memory 206384 kb
Host smart-20009d44-3c25-4216-a53a-4a5e884998a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10708
53262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1070853262
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1269468586
Short name T751
Test name
Test status
Simulation time 229063460 ps
CPU time 0.89 seconds
Started Jul 11 05:56:38 PM PDT 24
Finished Jul 11 05:56:42 PM PDT 24
Peak memory 206492 kb
Host smart-79b303c3-33a7-4665-9644-3b90f7c9d907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12694
68586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1269468586
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1017372861
Short name T2095
Test name
Test status
Simulation time 180276139 ps
CPU time 0.81 seconds
Started Jul 11 05:56:46 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 206380 kb
Host smart-4689432c-4166-4c12-9d3c-7ab009508a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10173
72861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1017372861
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1462912044
Short name T645
Test name
Test status
Simulation time 182293071 ps
CPU time 0.83 seconds
Started Jul 11 05:56:42 PM PDT 24
Finished Jul 11 05:56:45 PM PDT 24
Peak memory 206392 kb
Host smart-43e8b1f9-9a0c-42fd-97d2-fdafb124b21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14629
12044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1462912044
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1101920806
Short name T1365
Test name
Test status
Simulation time 194075079 ps
CPU time 0.92 seconds
Started Jul 11 05:56:41 PM PDT 24
Finished Jul 11 05:56:44 PM PDT 24
Peak memory 206384 kb
Host smart-3d0fe788-5d75-4833-9fee-84dd79a0f564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11019
20806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1101920806
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.1541615936
Short name T2482
Test name
Test status
Simulation time 185578147 ps
CPU time 0.75 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:56:47 PM PDT 24
Peak memory 206344 kb
Host smart-3b056cb4-11f2-4e00-9893-87217096b984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
15936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1541615936
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3551883374
Short name T1135
Test name
Test status
Simulation time 173498322 ps
CPU time 0.79 seconds
Started Jul 11 05:56:45 PM PDT 24
Finished Jul 11 05:56:48 PM PDT 24
Peak memory 206380 kb
Host smart-0773b980-8a8c-4f5b-9bbe-0677951674a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35518
83374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3551883374
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.809179578
Short name T1403
Test name
Test status
Simulation time 215557587 ps
CPU time 0.91 seconds
Started Jul 11 05:56:37 PM PDT 24
Finished Jul 11 05:56:42 PM PDT 24
Peak memory 206332 kb
Host smart-3c3e662d-d001-48d5-8d72-4b74abaca7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80917
9578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.809179578
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.184866294
Short name T1544
Test name
Test status
Simulation time 6007992119 ps
CPU time 41.19 seconds
Started Jul 11 05:56:43 PM PDT 24
Finished Jul 11 05:57:27 PM PDT 24
Peak memory 206584 kb
Host smart-0bde68bb-b064-4ca4-8953-dbcfeff8aa9d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=184866294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.184866294
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3937777533
Short name T1395
Test name
Test status
Simulation time 200071234 ps
CPU time 0.86 seconds
Started Jul 11 05:56:56 PM PDT 24
Finished Jul 11 05:57:01 PM PDT 24
Peak memory 206324 kb
Host smart-56e8c950-5297-4886-933a-4c4032c7faf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39377
77533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3937777533
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2822427854
Short name T1696
Test name
Test status
Simulation time 189598674 ps
CPU time 0.8 seconds
Started Jul 11 05:56:38 PM PDT 24
Finished Jul 11 05:56:42 PM PDT 24
Peak memory 206372 kb
Host smart-c5afc7be-314b-4de2-ae06-1252862ae3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28224
27854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2822427854
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3622153913
Short name T1639
Test name
Test status
Simulation time 458100462 ps
CPU time 1.3 seconds
Started Jul 11 05:56:55 PM PDT 24
Finished Jul 11 05:57:00 PM PDT 24
Peak memory 206320 kb
Host smart-1a9aae53-c3a0-44d8-b723-4e36de86277e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36221
53913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3622153913
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2665984115
Short name T483
Test name
Test status
Simulation time 4757602817 ps
CPU time 44.33 seconds
Started Jul 11 05:56:41 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206656 kb
Host smart-13f89a12-6cff-4023-b13a-f5e3642493ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
84115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2665984115
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.2528946289
Short name T1005
Test name
Test status
Simulation time 37471230 ps
CPU time 0.67 seconds
Started Jul 11 05:56:52 PM PDT 24
Finished Jul 11 05:56:57 PM PDT 24
Peak memory 206428 kb
Host smart-096e8f91-5fdb-4d7c-9a05-5e4d7c86aff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2528946289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2528946289
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1098127136
Short name T239
Test name
Test status
Simulation time 13392580993 ps
CPU time 14.76 seconds
Started Jul 11 05:56:45 PM PDT 24
Finished Jul 11 05:57:02 PM PDT 24
Peak memory 206668 kb
Host smart-26ca9617-2df7-47a5-8ce2-632b6cb06538
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1098127136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1098127136
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2985191186
Short name T9
Test name
Test status
Simulation time 23446793275 ps
CPU time 21.74 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:57:08 PM PDT 24
Peak memory 206640 kb
Host smart-cbdb4d91-d320-4505-8abc-22da5317c903
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2985191186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.2985191186
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.718410410
Short name T2473
Test name
Test status
Simulation time 153834135 ps
CPU time 0.76 seconds
Started Jul 11 05:56:41 PM PDT 24
Finished Jul 11 05:56:44 PM PDT 24
Peak memory 206328 kb
Host smart-15ee79ab-71e1-42a7-ba48-ce1f5750bb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71841
0410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.718410410
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3706972765
Short name T929
Test name
Test status
Simulation time 171382505 ps
CPU time 0.82 seconds
Started Jul 11 05:56:39 PM PDT 24
Finished Jul 11 05:56:42 PM PDT 24
Peak memory 206380 kb
Host smart-ce98f6f5-ba85-4b32-97c3-e9d667fb8553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37069
72765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3706972765
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2402486118
Short name T117
Test name
Test status
Simulation time 410940856 ps
CPU time 1.23 seconds
Started Jul 11 05:56:46 PM PDT 24
Finished Jul 11 05:56:50 PM PDT 24
Peak memory 206400 kb
Host smart-bd37cdaf-feb2-44a2-b633-c33719cccbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24024
86118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2402486118
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.289222764
Short name T2505
Test name
Test status
Simulation time 478622157 ps
CPU time 1.31 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:56:48 PM PDT 24
Peak memory 206400 kb
Host smart-e4e98a13-3105-4974-ad29-19373eed16cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28922
2764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.289222764
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.4283246984
Short name T178
Test name
Test status
Simulation time 12904283814 ps
CPU time 23.3 seconds
Started Jul 11 05:57:05 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206696 kb
Host smart-ac8ffda0-ea2d-4ea0-9b45-d85f2b9e101f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42832
46984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.4283246984
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1028690305
Short name T444
Test name
Test status
Simulation time 477194805 ps
CPU time 1.4 seconds
Started Jul 11 05:56:50 PM PDT 24
Finished Jul 11 05:56:55 PM PDT 24
Peak memory 206316 kb
Host smart-911f2964-c6c1-4244-b70e-b93a00e231da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10286
90305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1028690305
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_enable.2153352244
Short name T2320
Test name
Test status
Simulation time 43011251 ps
CPU time 0.64 seconds
Started Jul 11 05:56:46 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 206316 kb
Host smart-d3748929-f08a-461b-8cbd-3af475e7a494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
52244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2153352244
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2838696127
Short name T395
Test name
Test status
Simulation time 978136918 ps
CPU time 2.49 seconds
Started Jul 11 05:57:05 PM PDT 24
Finished Jul 11 05:57:14 PM PDT 24
Peak memory 206564 kb
Host smart-5a1ca507-3000-4079-ad3d-07708d620770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28386
96127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2838696127
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1264714977
Short name T1730
Test name
Test status
Simulation time 232750698 ps
CPU time 1.39 seconds
Started Jul 11 05:56:55 PM PDT 24
Finished Jul 11 05:57:01 PM PDT 24
Peak memory 206508 kb
Host smart-6a7c054b-d4b6-4874-a845-fae72c334d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12647
14977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1264714977
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3428915223
Short name T1789
Test name
Test status
Simulation time 238261555 ps
CPU time 0.93 seconds
Started Jul 11 05:56:45 PM PDT 24
Finished Jul 11 05:56:48 PM PDT 24
Peak memory 206264 kb
Host smart-ef30fca3-0ba7-4ab3-8150-6add748d9d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34289
15223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3428915223
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2403737701
Short name T903
Test name
Test status
Simulation time 141897548 ps
CPU time 0.76 seconds
Started Jul 11 05:56:46 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 206384 kb
Host smart-ee453145-e66e-4108-a3e0-f68e36dbd62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24037
37701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2403737701
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2234821552
Short name T998
Test name
Test status
Simulation time 160972653 ps
CPU time 0.8 seconds
Started Jul 11 05:56:45 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 206316 kb
Host smart-be3af91a-1d48-43d8-af21-b99d714a9c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22348
21552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2234821552
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.881193277
Short name T2021
Test name
Test status
Simulation time 3708777412 ps
CPU time 14.01 seconds
Started Jul 11 05:57:04 PM PDT 24
Finished Jul 11 05:57:25 PM PDT 24
Peak memory 206036 kb
Host smart-dd8e9f6b-76a9-4792-abfc-429751b223e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88119
3277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.881193277
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1037655743
Short name T1689
Test name
Test status
Simulation time 225210491 ps
CPU time 0.86 seconds
Started Jul 11 05:56:50 PM PDT 24
Finished Jul 11 05:56:54 PM PDT 24
Peak memory 206384 kb
Host smart-b7d4bc53-2a8e-4af8-9245-a4799302bbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10376
55743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1037655743
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.749032583
Short name T1921
Test name
Test status
Simulation time 23325776412 ps
CPU time 23.84 seconds
Started Jul 11 05:56:45 PM PDT 24
Finished Jul 11 05:57:11 PM PDT 24
Peak memory 206448 kb
Host smart-18ac150d-2b1b-413a-a522-42e934073029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74903
2583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.749032583
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1190026808
Short name T823
Test name
Test status
Simulation time 3274637035 ps
CPU time 3.89 seconds
Started Jul 11 05:56:48 PM PDT 24
Finished Jul 11 05:56:55 PM PDT 24
Peak memory 206416 kb
Host smart-504be05d-d7f8-472d-affe-e4ff95e2a736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11900
26808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1190026808
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.1055066622
Short name T855
Test name
Test status
Simulation time 12198116951 ps
CPU time 113.22 seconds
Started Jul 11 05:56:55 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 206640 kb
Host smart-92977d28-4278-4413-9ea2-3bfd1732d2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10550
66622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.1055066622
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3039059326
Short name T549
Test name
Test status
Simulation time 3915022913 ps
CPU time 107.77 seconds
Started Jul 11 05:56:44 PM PDT 24
Finished Jul 11 05:58:34 PM PDT 24
Peak memory 206556 kb
Host smart-cf950cf8-d7d2-4a0c-bfa8-7ce2fccd3e2e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3039059326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3039059326
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.888994587
Short name T2597
Test name
Test status
Simulation time 242222679 ps
CPU time 0.9 seconds
Started Jul 11 05:57:04 PM PDT 24
Finished Jul 11 05:57:12 PM PDT 24
Peak memory 206356 kb
Host smart-2b8ca788-03c9-49c1-b3d7-3901588a4ec3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=888994587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.888994587
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2322583916
Short name T2591
Test name
Test status
Simulation time 193531423 ps
CPU time 0.92 seconds
Started Jul 11 05:56:50 PM PDT 24
Finished Jul 11 05:56:54 PM PDT 24
Peak memory 206312 kb
Host smart-959bdd42-18d7-4978-922a-e00f3b5e1680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23225
83916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2322583916
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.4185673796
Short name T1368
Test name
Test status
Simulation time 4083565646 ps
CPU time 37.07 seconds
Started Jul 11 05:56:48 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206612 kb
Host smart-1133c2ed-0065-463f-900e-eb7d1f5271fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41856
73796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.4185673796
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2949609262
Short name T1557
Test name
Test status
Simulation time 4056435380 ps
CPU time 39.39 seconds
Started Jul 11 05:56:50 PM PDT 24
Finished Jul 11 05:57:34 PM PDT 24
Peak memory 206688 kb
Host smart-e51d3614-288d-4749-8f82-22f4df3822b5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2949609262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2949609262
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1047129992
Short name T1926
Test name
Test status
Simulation time 151084745 ps
CPU time 0.78 seconds
Started Jul 11 05:56:48 PM PDT 24
Finished Jul 11 05:56:51 PM PDT 24
Peak memory 206340 kb
Host smart-566f4c14-2733-4deb-a04c-5c57eb9c7c83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1047129992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1047129992
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2332779047
Short name T417
Test name
Test status
Simulation time 151449050 ps
CPU time 0.84 seconds
Started Jul 11 05:56:49 PM PDT 24
Finished Jul 11 05:56:53 PM PDT 24
Peak memory 206324 kb
Host smart-001874c9-1866-4229-bb5c-f55bdfd449e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23327
79047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2332779047
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.2664077514
Short name T784
Test name
Test status
Simulation time 179619381 ps
CPU time 0.9 seconds
Started Jul 11 05:56:47 PM PDT 24
Finished Jul 11 05:56:50 PM PDT 24
Peak memory 206372 kb
Host smart-535fcad7-1910-488f-bab2-5a18a5bccc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26640
77514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2664077514
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1399593428
Short name T2198
Test name
Test status
Simulation time 249138237 ps
CPU time 0.92 seconds
Started Jul 11 05:56:52 PM PDT 24
Finished Jul 11 05:56:57 PM PDT 24
Peak memory 206396 kb
Host smart-194455f3-08ad-4526-8b19-c074af904e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13995
93428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1399593428
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1253911178
Short name T1344
Test name
Test status
Simulation time 161837529 ps
CPU time 0.81 seconds
Started Jul 11 05:56:47 PM PDT 24
Finished Jul 11 05:56:50 PM PDT 24
Peak memory 206384 kb
Host smart-3f33cda6-5bdf-41e3-ae2a-7afafcbe321e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12539
11178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1253911178
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1644333943
Short name T1036
Test name
Test status
Simulation time 166891835 ps
CPU time 0.77 seconds
Started Jul 11 05:56:46 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 206308 kb
Host smart-7deaf533-7495-4c8f-a3d2-214cec7aa25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16443
33943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1644333943
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.123978120
Short name T1555
Test name
Test status
Simulation time 241029689 ps
CPU time 0.9 seconds
Started Jul 11 05:56:52 PM PDT 24
Finished Jul 11 05:56:57 PM PDT 24
Peak memory 205984 kb
Host smart-69d1dca6-5786-4543-acfc-ceb7ef248a94
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=123978120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.123978120
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1849619260
Short name T1716
Test name
Test status
Simulation time 160064357 ps
CPU time 0.77 seconds
Started Jul 11 05:56:49 PM PDT 24
Finished Jul 11 05:56:53 PM PDT 24
Peak memory 206352 kb
Host smart-2e14ade6-8adf-48c8-945a-5080651a4d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18496
19260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1849619260
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2775862553
Short name T738
Test name
Test status
Simulation time 6366299602 ps
CPU time 14.4 seconds
Started Jul 11 05:56:49 PM PDT 24
Finished Jul 11 05:57:07 PM PDT 24
Peak memory 206668 kb
Host smart-dc44868e-7650-4379-82ab-4cf137ffeaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27758
62553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2775862553
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2201359929
Short name T1100
Test name
Test status
Simulation time 152563891 ps
CPU time 0.79 seconds
Started Jul 11 05:56:50 PM PDT 24
Finished Jul 11 05:56:54 PM PDT 24
Peak memory 206324 kb
Host smart-5a3e4a9e-85a3-43dd-8f69-0c9a0924702b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22013
59929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2201359929
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1187735136
Short name T2560
Test name
Test status
Simulation time 171236299 ps
CPU time 0.83 seconds
Started Jul 11 05:56:53 PM PDT 24
Finished Jul 11 05:56:58 PM PDT 24
Peak memory 206464 kb
Host smart-a8a03f25-3fda-49c5-ba83-1f0f83c5fb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11877
35136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1187735136
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2745095901
Short name T787
Test name
Test status
Simulation time 172145081 ps
CPU time 0.77 seconds
Started Jul 11 05:56:48 PM PDT 24
Finished Jul 11 05:56:52 PM PDT 24
Peak memory 206400 kb
Host smart-46c15e57-ad0a-41e9-a849-15dcad761896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
95901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2745095901
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.828989968
Short name T2460
Test name
Test status
Simulation time 180188768 ps
CPU time 0.82 seconds
Started Jul 11 05:56:53 PM PDT 24
Finished Jul 11 05:56:58 PM PDT 24
Peak memory 206388 kb
Host smart-cc94d53f-56e0-4f63-812b-49f05ce35486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82898
9968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.828989968
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3602679794
Short name T505
Test name
Test status
Simulation time 156842136 ps
CPU time 0.77 seconds
Started Jul 11 05:56:51 PM PDT 24
Finished Jul 11 05:56:55 PM PDT 24
Peak memory 206308 kb
Host smart-dd3b52a1-64b1-42e0-baf7-d86d91fcea96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36026
79794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3602679794
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3869310684
Short name T904
Test name
Test status
Simulation time 150761071 ps
CPU time 0.78 seconds
Started Jul 11 05:56:51 PM PDT 24
Finished Jul 11 05:56:56 PM PDT 24
Peak memory 206392 kb
Host smart-7e07fb93-d5ad-45ba-acac-4f08ef6cc48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38693
10684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3869310684
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2976778885
Short name T1052
Test name
Test status
Simulation time 239383482 ps
CPU time 0.84 seconds
Started Jul 11 05:56:52 PM PDT 24
Finished Jul 11 05:56:57 PM PDT 24
Peak memory 206400 kb
Host smart-35d41d28-dde2-4a15-9796-f92a3f311bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
78885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2976778885
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3073314478
Short name T1476
Test name
Test status
Simulation time 195594809 ps
CPU time 0.87 seconds
Started Jul 11 05:56:54 PM PDT 24
Finished Jul 11 05:56:58 PM PDT 24
Peak memory 206384 kb
Host smart-1954b003-4d4d-4fe6-9ce7-e385201a0e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30733
14478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3073314478
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1089122258
Short name T2585
Test name
Test status
Simulation time 5512487221 ps
CPU time 157.51 seconds
Started Jul 11 05:56:52 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206620 kb
Host smart-02abb64f-54f6-426e-8dcd-ce23d7ff4aca
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1089122258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1089122258
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3044503384
Short name T893
Test name
Test status
Simulation time 224161870 ps
CPU time 0.81 seconds
Started Jul 11 05:56:51 PM PDT 24
Finished Jul 11 05:56:55 PM PDT 24
Peak memory 206560 kb
Host smart-2d61c2d4-da93-4092-ba54-0de4e8191859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
03384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3044503384
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3329880876
Short name T513
Test name
Test status
Simulation time 244097634 ps
CPU time 0.85 seconds
Started Jul 11 05:56:54 PM PDT 24
Finished Jul 11 05:56:59 PM PDT 24
Peak memory 206384 kb
Host smart-8dfa5b5d-38e8-45c9-92b7-33ef88d97e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33298
80876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3329880876
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3945491887
Short name T1922
Test name
Test status
Simulation time 1346306073 ps
CPU time 2.64 seconds
Started Jul 11 05:56:56 PM PDT 24
Finished Jul 11 05:57:04 PM PDT 24
Peak memory 206556 kb
Host smart-e306154d-03c1-4f0f-ad79-2b3eb3dfd880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
91887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3945491887
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3288579674
Short name T641
Test name
Test status
Simulation time 5579185823 ps
CPU time 51.36 seconds
Started Jul 11 05:56:53 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206728 kb
Host smart-916e8e0c-95c0-4a91-871f-5c4eab5b354e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32885
79674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3288579674
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.1678010500
Short name T910
Test name
Test status
Simulation time 53922429 ps
CPU time 0.66 seconds
Started Jul 11 05:57:08 PM PDT 24
Finished Jul 11 05:57:15 PM PDT 24
Peak memory 206424 kb
Host smart-44181fd3-766f-493f-9c12-e11a8174e9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1678010500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1678010500
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3499506586
Short name T1753
Test name
Test status
Simulation time 3828258162 ps
CPU time 4.74 seconds
Started Jul 11 05:56:54 PM PDT 24
Finished Jul 11 05:57:04 PM PDT 24
Peak memory 206444 kb
Host smart-d7a7c4fe-3fa2-4a89-962f-77631f9ed560
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3499506586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3499506586
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1274559475
Short name T1803
Test name
Test status
Simulation time 13336703169 ps
CPU time 13.62 seconds
Started Jul 11 05:56:49 PM PDT 24
Finished Jul 11 05:57:06 PM PDT 24
Peak memory 206696 kb
Host smart-f0b39fb9-f23f-4f84-888a-60954e3804eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1274559475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1274559475
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1242151429
Short name T1429
Test name
Test status
Simulation time 23380193414 ps
CPU time 22.24 seconds
Started Jul 11 05:56:51 PM PDT 24
Finished Jul 11 05:57:17 PM PDT 24
Peak memory 206572 kb
Host smart-f7c77580-9451-401e-8ccd-e69896d36c23
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1242151429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1242151429
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.545494502
Short name T2276
Test name
Test status
Simulation time 234957161 ps
CPU time 0.89 seconds
Started Jul 11 05:56:54 PM PDT 24
Finished Jul 11 05:56:59 PM PDT 24
Peak memory 206384 kb
Host smart-0b974e82-8683-4c33-bb2c-ce7869d1c333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54549
4502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.545494502
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1280528302
Short name T466
Test name
Test status
Simulation time 225142827 ps
CPU time 0.84 seconds
Started Jul 11 05:56:53 PM PDT 24
Finished Jul 11 05:56:58 PM PDT 24
Peak memory 206388 kb
Host smart-3682baa9-3a34-45d4-98c2-c570c4e0fa50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
28302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1280528302
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2726098498
Short name T2671
Test name
Test status
Simulation time 221588719 ps
CPU time 0.89 seconds
Started Jul 11 05:56:51 PM PDT 24
Finished Jul 11 05:56:56 PM PDT 24
Peak memory 206496 kb
Host smart-ff9320ee-d313-4866-a41a-f4b483926aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27260
98498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2726098498
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2890335373
Short name T1667
Test name
Test status
Simulation time 605563276 ps
CPU time 1.58 seconds
Started Jul 11 05:57:05 PM PDT 24
Finished Jul 11 05:57:13 PM PDT 24
Peak memory 206364 kb
Host smart-44df57a6-b373-4909-943a-a28a522fcca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28903
35373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2890335373
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.865889878
Short name T2454
Test name
Test status
Simulation time 13282431344 ps
CPU time 26.13 seconds
Started Jul 11 05:56:52 PM PDT 24
Finished Jul 11 05:57:23 PM PDT 24
Peak memory 206296 kb
Host smart-8f39a371-0272-4f5d-ace9-2678cf9bf79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86588
9878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.865889878
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1087802675
Short name T1442
Test name
Test status
Simulation time 503787833 ps
CPU time 1.39 seconds
Started Jul 11 05:56:52 PM PDT 24
Finished Jul 11 05:56:57 PM PDT 24
Peak memory 206264 kb
Host smart-16dc638e-8abc-44e5-9f66-8edd920056bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10878
02675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1087802675
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2540431956
Short name T1392
Test name
Test status
Simulation time 134901647 ps
CPU time 0.72 seconds
Started Jul 11 05:56:50 PM PDT 24
Finished Jul 11 05:56:54 PM PDT 24
Peak memory 206388 kb
Host smart-bfbd0fd4-c424-4ae7-b02a-72ed2e7e78dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25404
31956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2540431956
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1019935357
Short name T2714
Test name
Test status
Simulation time 59006997 ps
CPU time 0.67 seconds
Started Jul 11 05:56:49 PM PDT 24
Finished Jul 11 05:56:53 PM PDT 24
Peak memory 206388 kb
Host smart-18062f1d-27c4-432f-b7d9-9d4f03fd4828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10199
35357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1019935357
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.4200064624
Short name T1683
Test name
Test status
Simulation time 958181214 ps
CPU time 2.43 seconds
Started Jul 11 05:56:55 PM PDT 24
Finished Jul 11 05:57:02 PM PDT 24
Peak memory 206584 kb
Host smart-528b1c7f-f297-4a8f-b488-a2020e708733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42000
64624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.4200064624
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3371180757
Short name T1198
Test name
Test status
Simulation time 295262640 ps
CPU time 2.06 seconds
Started Jul 11 05:57:00 PM PDT 24
Finished Jul 11 05:57:09 PM PDT 24
Peak memory 206588 kb
Host smart-5f7a113c-8f24-46d0-8567-d9408713fcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33711
80757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3371180757
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3129547292
Short name T1474
Test name
Test status
Simulation time 186524219 ps
CPU time 0.81 seconds
Started Jul 11 05:56:58 PM PDT 24
Finished Jul 11 05:57:05 PM PDT 24
Peak memory 205340 kb
Host smart-64f62c3d-b4ca-4a4f-96ce-0670f2ae2143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31295
47292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3129547292
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2220145693
Short name T1657
Test name
Test status
Simulation time 136987861 ps
CPU time 0.8 seconds
Started Jul 11 05:57:00 PM PDT 24
Finished Jul 11 05:57:08 PM PDT 24
Peak memory 206408 kb
Host smart-996344ce-b234-4a00-9f1c-1f1b9a2c306c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201
45693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2220145693
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1338167200
Short name T1863
Test name
Test status
Simulation time 231448794 ps
CPU time 0.94 seconds
Started Jul 11 05:57:06 PM PDT 24
Finished Jul 11 05:57:13 PM PDT 24
Peak memory 206364 kb
Host smart-70a69ffe-94e7-4ee4-8096-9a6f2b6be7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13381
67200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1338167200
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.3638679175
Short name T95
Test name
Test status
Simulation time 4387464546 ps
CPU time 15.6 seconds
Started Jul 11 05:56:58 PM PDT 24
Finished Jul 11 05:57:19 PM PDT 24
Peak memory 206708 kb
Host smart-9d89bd40-e566-4cfb-ab8a-ab79e74826eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36386
79175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3638679175
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1705380501
Short name T1923
Test name
Test status
Simulation time 194806805 ps
CPU time 0.81 seconds
Started Jul 11 05:56:56 PM PDT 24
Finished Jul 11 05:57:01 PM PDT 24
Peak memory 206388 kb
Host smart-a9954bc8-c2ea-4d3c-b095-079182cd26a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17053
80501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1705380501
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3635252849
Short name T765
Test name
Test status
Simulation time 23286505871 ps
CPU time 30.72 seconds
Started Jul 11 05:56:57 PM PDT 24
Finished Jul 11 05:57:32 PM PDT 24
Peak memory 206444 kb
Host smart-bb006650-e930-4c8e-a266-066a8743f9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36352
52849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3635252849
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1126134837
Short name T2229
Test name
Test status
Simulation time 3346548099 ps
CPU time 3.71 seconds
Started Jul 11 05:57:00 PM PDT 24
Finished Jul 11 05:57:10 PM PDT 24
Peak memory 206452 kb
Host smart-acedb37f-3e8f-46be-8ecc-57dbd09a38d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11261
34837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1126134837
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3045957453
Short name T2174
Test name
Test status
Simulation time 8976645702 ps
CPU time 257.69 seconds
Started Jul 11 05:57:01 PM PDT 24
Finished Jul 11 06:01:26 PM PDT 24
Peak memory 206680 kb
Host smart-61dafbf1-319a-4c01-890e-4d863ed9f373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30459
57453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3045957453
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3408921366
Short name T89
Test name
Test status
Simulation time 6688729885 ps
CPU time 179.2 seconds
Started Jul 11 05:56:56 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206644 kb
Host smart-7d027848-7b23-4fb3-a784-bc6059d60254
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3408921366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3408921366
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1351181040
Short name T2443
Test name
Test status
Simulation time 242360424 ps
CPU time 0.9 seconds
Started Jul 11 05:57:05 PM PDT 24
Finished Jul 11 05:57:12 PM PDT 24
Peak memory 206384 kb
Host smart-2b3345d3-4d3c-4adc-a03d-a47a966a6487
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1351181040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1351181040
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2262213749
Short name T1407
Test name
Test status
Simulation time 194824205 ps
CPU time 0.9 seconds
Started Jul 11 05:57:01 PM PDT 24
Finished Jul 11 05:57:08 PM PDT 24
Peak memory 206368 kb
Host smart-271bc5e1-f702-4e65-bf42-4ebd25ea9f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22622
13749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2262213749
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3035852665
Short name T377
Test name
Test status
Simulation time 5642637395 ps
CPU time 155.85 seconds
Started Jul 11 05:57:01 PM PDT 24
Finished Jul 11 05:59:43 PM PDT 24
Peak memory 206664 kb
Host smart-54e91e6c-a6a9-4850-8c22-4fc2a3d4b5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30358
52665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3035852665
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2772244473
Short name T473
Test name
Test status
Simulation time 3095391294 ps
CPU time 81.47 seconds
Started Jul 11 05:56:57 PM PDT 24
Finished Jul 11 05:58:24 PM PDT 24
Peak memory 206660 kb
Host smart-37dc3da0-3aaf-43f9-9e80-6471edb4d3dc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2772244473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2772244473
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.3138679009
Short name T1170
Test name
Test status
Simulation time 154522452 ps
CPU time 0.79 seconds
Started Jul 11 05:56:53 PM PDT 24
Finished Jul 11 05:56:58 PM PDT 24
Peak memory 206388 kb
Host smart-39d10f3e-c7f2-4fb9-9afd-5b6bd27198ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3138679009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.3138679009
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1744304545
Short name T1787
Test name
Test status
Simulation time 169112802 ps
CPU time 0.78 seconds
Started Jul 11 05:56:57 PM PDT 24
Finished Jul 11 05:57:03 PM PDT 24
Peak memory 206388 kb
Host smart-56c42f9e-8aec-4ba6-99a0-252dce4a67aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17443
04545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1744304545
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1094179475
Short name T1702
Test name
Test status
Simulation time 194034268 ps
CPU time 0.89 seconds
Started Jul 11 05:56:57 PM PDT 24
Finished Jul 11 05:57:04 PM PDT 24
Peak memory 206384 kb
Host smart-f3218947-1a2b-443e-bd8b-598a211c8112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10941
79475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1094179475
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3008658119
Short name T881
Test name
Test status
Simulation time 194268455 ps
CPU time 0.87 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:57:15 PM PDT 24
Peak memory 206328 kb
Host smart-32ce2a1d-4b2e-488e-87f7-fdcea02329f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30086
58119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3008658119
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1268171139
Short name T2029
Test name
Test status
Simulation time 153226047 ps
CPU time 0.8 seconds
Started Jul 11 05:56:58 PM PDT 24
Finished Jul 11 05:57:05 PM PDT 24
Peak memory 206384 kb
Host smart-d2fd9a4d-d043-449b-a5f2-5676d5dab894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12681
71139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1268171139
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.122996984
Short name T184
Test name
Test status
Simulation time 167944362 ps
CPU time 0.78 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:57:14 PM PDT 24
Peak memory 206064 kb
Host smart-b0bf7377-6864-41d5-8442-82e0b802cd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12299
6984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.122996984
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3798308142
Short name T1512
Test name
Test status
Simulation time 242355098 ps
CPU time 1.04 seconds
Started Jul 11 05:56:57 PM PDT 24
Finished Jul 11 05:57:03 PM PDT 24
Peak memory 206296 kb
Host smart-f0d8cbd2-1e92-4b1e-9aba-d4039c6cb3a1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3798308142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3798308142
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.745182835
Short name T2603
Test name
Test status
Simulation time 189829396 ps
CPU time 0.77 seconds
Started Jul 11 05:56:57 PM PDT 24
Finished Jul 11 05:57:02 PM PDT 24
Peak memory 206392 kb
Host smart-142ed163-c326-481f-ac12-4bcdf223ecae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74518
2835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.745182835
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.424939668
Short name T1796
Test name
Test status
Simulation time 100474404 ps
CPU time 0.71 seconds
Started Jul 11 05:56:58 PM PDT 24
Finished Jul 11 05:57:05 PM PDT 24
Peak memory 205444 kb
Host smart-139081b9-b6ad-41a1-bef3-9dc665e8a194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493
9668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.424939668
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.504277000
Short name T286
Test name
Test status
Simulation time 19843194405 ps
CPU time 46.02 seconds
Started Jul 11 05:57:00 PM PDT 24
Finished Jul 11 05:57:53 PM PDT 24
Peak memory 206716 kb
Host smart-adb3a288-09ab-4b73-9f52-c331e17a6a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50427
7000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.504277000
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3958608347
Short name T1167
Test name
Test status
Simulation time 203242792 ps
CPU time 0.87 seconds
Started Jul 11 05:56:55 PM PDT 24
Finished Jul 11 05:57:01 PM PDT 24
Peak memory 206308 kb
Host smart-27204eda-ee8a-438a-8431-60f30d55bfc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39586
08347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3958608347
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2725723410
Short name T618
Test name
Test status
Simulation time 178117087 ps
CPU time 0.8 seconds
Started Jul 11 05:56:55 PM PDT 24
Finished Jul 11 05:57:01 PM PDT 24
Peak memory 206328 kb
Host smart-6f6f9593-3ccc-4c0d-adab-90292258db34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27257
23410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2725723410
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2312273683
Short name T2065
Test name
Test status
Simulation time 222446357 ps
CPU time 0.88 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:57:14 PM PDT 24
Peak memory 206336 kb
Host smart-059becc7-a828-4c56-8165-6b61cb23ebfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23122
73683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2312273683
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.838498270
Short name T2261
Test name
Test status
Simulation time 177592072 ps
CPU time 0.82 seconds
Started Jul 11 05:57:06 PM PDT 24
Finished Jul 11 05:57:13 PM PDT 24
Peak memory 206368 kb
Host smart-a436c4dd-760d-4581-8ac2-591e449fb967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83849
8270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.838498270
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3891505270
Short name T1329
Test name
Test status
Simulation time 182944275 ps
CPU time 0.78 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:57:14 PM PDT 24
Peak memory 206324 kb
Host smart-5360ff0e-330d-43cd-af5b-33e05115c259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38915
05270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3891505270
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1276020471
Short name T1799
Test name
Test status
Simulation time 143502681 ps
CPU time 0.8 seconds
Started Jul 11 05:56:58 PM PDT 24
Finished Jul 11 05:57:05 PM PDT 24
Peak memory 206296 kb
Host smart-28c1a36d-59ff-4c52-a578-af2b9b57e4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12760
20471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1276020471
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3186503165
Short name T634
Test name
Test status
Simulation time 162523341 ps
CPU time 0.81 seconds
Started Jul 11 05:57:05 PM PDT 24
Finished Jul 11 05:57:12 PM PDT 24
Peak memory 206388 kb
Host smart-f42a4a9d-731a-4e31-9c22-3672015fb893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31865
03165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3186503165
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3671156118
Short name T2475
Test name
Test status
Simulation time 195664075 ps
CPU time 0.88 seconds
Started Jul 11 05:57:00 PM PDT 24
Finished Jul 11 05:57:08 PM PDT 24
Peak memory 206368 kb
Host smart-79fecfc8-505d-4166-9ba9-0ff199557e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36711
56118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3671156118
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2784616092
Short name T1669
Test name
Test status
Simulation time 5273253764 ps
CPU time 36.39 seconds
Started Jul 11 05:57:03 PM PDT 24
Finished Jul 11 05:57:47 PM PDT 24
Peak memory 206664 kb
Host smart-687ac4d7-08ec-4d43-b94e-09e5824c37e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2784616092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2784616092
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1317123650
Short name T2600
Test name
Test status
Simulation time 169440508 ps
CPU time 0.75 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:57:14 PM PDT 24
Peak memory 206256 kb
Host smart-789d6eb9-825b-4881-a4f8-bf206fe86ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
23650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1317123650
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2718785169
Short name T496
Test name
Test status
Simulation time 212232985 ps
CPU time 0.78 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:57:14 PM PDT 24
Peak memory 205940 kb
Host smart-cfb19a38-be43-4cdb-bdfa-43caa9f45e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27187
85169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2718785169
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1370703761
Short name T224
Test name
Test status
Simulation time 288677373 ps
CPU time 0.98 seconds
Started Jul 11 05:56:58 PM PDT 24
Finished Jul 11 05:57:04 PM PDT 24
Peak memory 206316 kb
Host smart-86e6c350-7563-4633-a085-3497346c1c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707
03761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1370703761
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3835871732
Short name T1075
Test name
Test status
Simulation time 2822806401 ps
CPU time 26.81 seconds
Started Jul 11 05:56:56 PM PDT 24
Finished Jul 11 05:57:27 PM PDT 24
Peak memory 206656 kb
Host smart-b9569efc-557b-436a-bac3-2769f4b26ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38358
71732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3835871732
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.287728244
Short name T1888
Test name
Test status
Simulation time 46167085 ps
CPU time 0.74 seconds
Started Jul 11 05:57:22 PM PDT 24
Finished Jul 11 05:57:26 PM PDT 24
Peak memory 206372 kb
Host smart-8f5eb483-82ff-429f-bd46-42871ca2821e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=287728244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.287728244
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.4100004715
Short name T923
Test name
Test status
Simulation time 3659964173 ps
CPU time 4.87 seconds
Started Jul 11 05:57:04 PM PDT 24
Finished Jul 11 05:57:16 PM PDT 24
Peak memory 206648 kb
Host smart-3050d9d2-fc8b-408d-8114-b5e7f336ea01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4100004715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.4100004715
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3050406399
Short name T1983
Test name
Test status
Simulation time 13340505299 ps
CPU time 16.65 seconds
Started Jul 11 05:57:08 PM PDT 24
Finished Jul 11 05:57:31 PM PDT 24
Peak memory 206452 kb
Host smart-e7544187-310c-47bc-9935-738c52e4dff8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3050406399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3050406399
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1920544112
Short name T2523
Test name
Test status
Simulation time 23344191814 ps
CPU time 25.16 seconds
Started Jul 11 05:57:06 PM PDT 24
Finished Jul 11 05:57:37 PM PDT 24
Peak memory 206740 kb
Host smart-62d49bbf-e2f5-401d-b60e-2af7ce50ea20
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1920544112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1920544112
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1912808256
Short name T404
Test name
Test status
Simulation time 204785119 ps
CPU time 0.83 seconds
Started Jul 11 05:57:04 PM PDT 24
Finished Jul 11 05:57:12 PM PDT 24
Peak memory 206344 kb
Host smart-21abd08e-bf4a-427c-a292-a6183a92973a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19128
08256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1912808256
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.459570953
Short name T453
Test name
Test status
Simulation time 172929482 ps
CPU time 0.8 seconds
Started Jul 11 05:57:02 PM PDT 24
Finished Jul 11 05:57:10 PM PDT 24
Peak memory 206400 kb
Host smart-0b1e13bd-46a0-4435-9137-e60ec4af6449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45957
0953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.459570953
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.2441581019
Short name T1749
Test name
Test status
Simulation time 289263638 ps
CPU time 1.01 seconds
Started Jul 11 05:57:03 PM PDT 24
Finished Jul 11 05:57:11 PM PDT 24
Peak memory 206312 kb
Host smart-e6579020-c02d-4ede-ae62-8c9e9532da69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24415
81019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2441581019
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2017303526
Short name T900
Test name
Test status
Simulation time 1021051411 ps
CPU time 2.38 seconds
Started Jul 11 05:57:06 PM PDT 24
Finished Jul 11 05:57:15 PM PDT 24
Peak memory 206552 kb
Host smart-5fdf4a1f-8a06-4ca6-a1ad-426b21658f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20173
03526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2017303526
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3742780831
Short name T1040
Test name
Test status
Simulation time 18045226650 ps
CPU time 34.96 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206660 kb
Host smart-c4138d90-5ab7-4baf-bad7-681f73a6bb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37427
80831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3742780831
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.1904249501
Short name T484
Test name
Test status
Simulation time 352532092 ps
CPU time 1.21 seconds
Started Jul 11 05:57:05 PM PDT 24
Finished Jul 11 05:57:13 PM PDT 24
Peak memory 206396 kb
Host smart-5f13aa47-5bd2-4bc6-887a-5a1689d1b807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19042
49501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1904249501
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3165453442
Short name T749
Test name
Test status
Simulation time 163266927 ps
CPU time 0.82 seconds
Started Jul 11 05:57:07 PM PDT 24
Finished Jul 11 05:57:14 PM PDT 24
Peak memory 206364 kb
Host smart-779fb765-cf52-45be-9409-d3e401cc684d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31654
53442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3165453442
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1475980750
Short name T657
Test name
Test status
Simulation time 30910354 ps
CPU time 0.66 seconds
Started Jul 11 05:57:03 PM PDT 24
Finished Jul 11 05:57:11 PM PDT 24
Peak memory 206360 kb
Host smart-740357ce-4ba2-49da-a90e-d105e2c3bfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14759
80750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1475980750
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.174112664
Short name T20
Test name
Test status
Simulation time 757882738 ps
CPU time 1.8 seconds
Started Jul 11 05:57:20 PM PDT 24
Finished Jul 11 05:57:24 PM PDT 24
Peak memory 206608 kb
Host smart-797b4d10-2934-4028-ac4d-db3539933cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17411
2664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.174112664
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3417655660
Short name T193
Test name
Test status
Simulation time 172267460 ps
CPU time 1.37 seconds
Started Jul 11 05:57:16 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206520 kb
Host smart-dbadc41c-5a1f-43b9-9544-e9ba63cfd79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34176
55660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3417655660
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3419960035
Short name T390
Test name
Test status
Simulation time 293318148 ps
CPU time 0.91 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206364 kb
Host smart-f802591c-c092-4bb8-b0a5-4d8007f091aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34199
60035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3419960035
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3107673379
Short name T450
Test name
Test status
Simulation time 166120411 ps
CPU time 0.78 seconds
Started Jul 11 05:57:18 PM PDT 24
Finished Jul 11 05:57:21 PM PDT 24
Peak memory 206384 kb
Host smart-cc675e34-22a5-4b4d-b98b-44cf24498836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31076
73379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3107673379
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3302867888
Short name T2258
Test name
Test status
Simulation time 235402391 ps
CPU time 0.98 seconds
Started Jul 11 05:57:18 PM PDT 24
Finished Jul 11 05:57:21 PM PDT 24
Peak memory 206384 kb
Host smart-f7d65595-aab9-4793-a226-12c73d388dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33028
67888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3302867888
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1257952359
Short name T1858
Test name
Test status
Simulation time 8393495929 ps
CPU time 59.58 seconds
Started Jul 11 05:57:16 PM PDT 24
Finished Jul 11 05:58:18 PM PDT 24
Peak memory 206692 kb
Host smart-6f340a81-e104-41c4-9d84-896a3ff009d7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1257952359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1257952359
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.1682656656
Short name T1817
Test name
Test status
Simulation time 8563211389 ps
CPU time 27.05 seconds
Started Jul 11 05:57:16 PM PDT 24
Finished Jul 11 05:57:45 PM PDT 24
Peak memory 206724 kb
Host smart-46acc4f9-a1cb-4349-8ab9-53da0832ed06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16826
56656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.1682656656
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3075674569
Short name T1751
Test name
Test status
Simulation time 229153039 ps
CPU time 0.87 seconds
Started Jul 11 05:57:27 PM PDT 24
Finished Jul 11 05:57:34 PM PDT 24
Peak memory 206328 kb
Host smart-1e58e611-dd0e-4fd4-b65c-a55a90570955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30756
74569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3075674569
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.2160027356
Short name T1397
Test name
Test status
Simulation time 23321569829 ps
CPU time 25.07 seconds
Started Jul 11 05:57:20 PM PDT 24
Finished Jul 11 05:57:47 PM PDT 24
Peak memory 206408 kb
Host smart-d7180293-5ef4-47f7-ae70-675f1f66f208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21600
27356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2160027356
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.523315873
Short name T162
Test name
Test status
Simulation time 3301786921 ps
CPU time 4.21 seconds
Started Jul 11 05:57:20 PM PDT 24
Finished Jul 11 05:57:26 PM PDT 24
Peak memory 206364 kb
Host smart-3020752a-bd88-4af0-a094-69bc4ea42f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52331
5873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.523315873
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.217152853
Short name T909
Test name
Test status
Simulation time 7808783638 ps
CPU time 75.28 seconds
Started Jul 11 05:57:19 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206704 kb
Host smart-99eef1a5-94e6-4b1c-bff0-89a71781640a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21715
2853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.217152853
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.317421989
Short name T1545
Test name
Test status
Simulation time 5140750334 ps
CPU time 35.95 seconds
Started Jul 11 05:57:27 PM PDT 24
Finished Jul 11 05:58:09 PM PDT 24
Peak memory 206652 kb
Host smart-d20d61d8-abf9-4542-b40d-e603ba512e30
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=317421989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.317421989
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1147818535
Short name T1664
Test name
Test status
Simulation time 232523279 ps
CPU time 1 seconds
Started Jul 11 05:57:14 PM PDT 24
Finished Jul 11 05:57:17 PM PDT 24
Peak memory 206396 kb
Host smart-1dfe3a74-c308-4e2b-8b18-2f04a29b83cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1147818535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1147818535
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1196029312
Short name T1709
Test name
Test status
Simulation time 194803085 ps
CPU time 0.86 seconds
Started Jul 11 05:57:16 PM PDT 24
Finished Jul 11 05:57:18 PM PDT 24
Peak memory 206400 kb
Host smart-30822c2d-f81b-46fa-9671-0c66e7e74647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11960
29312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1196029312
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.75836406
Short name T1574
Test name
Test status
Simulation time 6298193877 ps
CPU time 45.71 seconds
Started Jul 11 05:59:13 PM PDT 24
Finished Jul 11 06:00:08 PM PDT 24
Peak memory 206692 kb
Host smart-c6d8dfdf-a5f7-4986-aaf9-63c8e199fdde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75836
406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.75836406
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.249389123
Short name T1966
Test name
Test status
Simulation time 6500045327 ps
CPU time 61.38 seconds
Started Jul 11 05:57:18 PM PDT 24
Finished Jul 11 05:58:21 PM PDT 24
Peak memory 206624 kb
Host smart-03394973-c14c-4694-b675-c3ee26878dc9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=249389123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.249389123
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3686839403
Short name T857
Test name
Test status
Simulation time 156729312 ps
CPU time 0.77 seconds
Started Jul 11 05:57:31 PM PDT 24
Finished Jul 11 05:57:38 PM PDT 24
Peak memory 206400 kb
Host smart-e09d9381-b296-4ac3-8527-85f83f0591b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3686839403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3686839403
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1863425878
Short name T1994
Test name
Test status
Simulation time 144372055 ps
CPU time 0.75 seconds
Started Jul 11 05:57:20 PM PDT 24
Finished Jul 11 05:57:23 PM PDT 24
Peak memory 206368 kb
Host smart-c6bb56a1-fabf-4beb-8c3b-3358d90ceda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18634
25878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1863425878
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.479641704
Short name T2569
Test name
Test status
Simulation time 207417658 ps
CPU time 0.91 seconds
Started Jul 11 05:57:17 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206380 kb
Host smart-c051ebdd-6f0a-4cce-afa4-bd6394ba957c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47964
1704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.479641704
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1934981957
Short name T347
Test name
Test status
Simulation time 197344462 ps
CPU time 0.86 seconds
Started Jul 11 05:57:29 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206384 kb
Host smart-4472a125-8d44-48ee-8d81-93c98f0f1742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19349
81957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1934981957
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2080068355
Short name T106
Test name
Test status
Simulation time 195393399 ps
CPU time 0.81 seconds
Started Jul 11 05:57:21 PM PDT 24
Finished Jul 11 05:57:24 PM PDT 24
Peak memory 206392 kb
Host smart-7a6c3adb-1a49-4997-bbbd-3123c8310bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
68355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2080068355
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2160342462
Short name T1717
Test name
Test status
Simulation time 171063888 ps
CPU time 0.85 seconds
Started Jul 11 05:57:28 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206392 kb
Host smart-46f9e750-07f8-4718-8d89-20fb99cf3e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21603
42462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2160342462
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2746714253
Short name T523
Test name
Test status
Simulation time 201057777 ps
CPU time 0.84 seconds
Started Jul 11 05:57:14 PM PDT 24
Finished Jul 11 05:57:17 PM PDT 24
Peak memory 206304 kb
Host smart-7195c920-8e76-4e9c-9a89-8cf4f0cd6e3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2746714253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2746714253
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1511796487
Short name T454
Test name
Test status
Simulation time 150823953 ps
CPU time 0.78 seconds
Started Jul 11 05:57:18 PM PDT 24
Finished Jul 11 05:57:21 PM PDT 24
Peak memory 206388 kb
Host smart-b36b330a-8235-4b7f-8b36-5b975544bf1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15117
96487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1511796487
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.746131407
Short name T2494
Test name
Test status
Simulation time 40791926 ps
CPU time 0.65 seconds
Started Jul 11 05:57:21 PM PDT 24
Finished Jul 11 05:57:24 PM PDT 24
Peak memory 206376 kb
Host smart-582ae309-202c-4d0f-94d2-c7b07500ab6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74613
1407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.746131407
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1306302880
Short name T253
Test name
Test status
Simulation time 18544683748 ps
CPU time 42.17 seconds
Started Jul 11 05:57:16 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206740 kb
Host smart-602f6ed7-d510-4ab1-8fd1-6d978309daae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13063
02880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1306302880
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.620387747
Short name T424
Test name
Test status
Simulation time 164111561 ps
CPU time 0.83 seconds
Started Jul 11 05:57:16 PM PDT 24
Finished Jul 11 05:57:18 PM PDT 24
Peak memory 206344 kb
Host smart-b7d765ae-0187-4de7-9d17-9febbb267027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62038
7747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.620387747
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1052963066
Short name T2393
Test name
Test status
Simulation time 188590977 ps
CPU time 0.91 seconds
Started Jul 11 05:57:18 PM PDT 24
Finished Jul 11 05:57:21 PM PDT 24
Peak memory 206288 kb
Host smart-df33cae9-9387-409a-a056-df0cce3b8e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10529
63066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1052963066
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3765594355
Short name T1268
Test name
Test status
Simulation time 176306693 ps
CPU time 0.9 seconds
Started Jul 11 05:57:17 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206388 kb
Host smart-8d3092d2-47e2-4f17-901f-5856c9453e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37655
94355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3765594355
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2606050146
Short name T2249
Test name
Test status
Simulation time 169542526 ps
CPU time 0.85 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:27 PM PDT 24
Peak memory 206368 kb
Host smart-0ca2fcab-03de-4961-af08-4908dcba912d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26060
50146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2606050146
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2011106045
Short name T2458
Test name
Test status
Simulation time 155768822 ps
CPU time 0.82 seconds
Started Jul 11 05:57:21 PM PDT 24
Finished Jul 11 05:57:25 PM PDT 24
Peak memory 206388 kb
Host smart-fa210f4e-9263-4d28-88b8-a5d50bab9ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20111
06045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2011106045
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.781433495
Short name T1743
Test name
Test status
Simulation time 163012138 ps
CPU time 0.81 seconds
Started Jul 11 05:57:14 PM PDT 24
Finished Jul 11 05:57:17 PM PDT 24
Peak memory 206304 kb
Host smart-d61cd5c4-4e7c-4207-b484-c5fadaca3a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78143
3495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.781433495
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3479388401
Short name T1952
Test name
Test status
Simulation time 155298840 ps
CPU time 0.79 seconds
Started Jul 11 05:57:17 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206388 kb
Host smart-c25baef2-2513-4ebf-99b2-12785000d2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
88401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3479388401
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2007771182
Short name T1872
Test name
Test status
Simulation time 216946735 ps
CPU time 0.92 seconds
Started Jul 11 05:57:22 PM PDT 24
Finished Jul 11 05:57:26 PM PDT 24
Peak memory 206384 kb
Host smart-33c4d689-92b4-4088-bb64-78bd4c763c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20077
71182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2007771182
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1800954086
Short name T2241
Test name
Test status
Simulation time 5679982541 ps
CPU time 147.27 seconds
Started Jul 11 05:57:15 PM PDT 24
Finished Jul 11 05:59:44 PM PDT 24
Peak memory 206564 kb
Host smart-15f3990a-35e7-435c-a5d7-2fba3584a2b2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1800954086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1800954086
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1759157195
Short name T2599
Test name
Test status
Simulation time 153532055 ps
CPU time 0.76 seconds
Started Jul 11 05:57:22 PM PDT 24
Finished Jul 11 05:57:26 PM PDT 24
Peak memory 206332 kb
Host smart-287aec3c-c4f8-4127-ba5f-c476f6901d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17591
57195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1759157195
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3092942065
Short name T2296
Test name
Test status
Simulation time 168785021 ps
CPU time 0.81 seconds
Started Jul 11 05:57:19 PM PDT 24
Finished Jul 11 05:57:22 PM PDT 24
Peak memory 206372 kb
Host smart-6229f41e-69a9-4604-8622-896a0dd8b298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929
42065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3092942065
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.1427992178
Short name T383
Test name
Test status
Simulation time 377466550 ps
CPU time 1.1 seconds
Started Jul 11 05:57:19 PM PDT 24
Finished Jul 11 05:57:22 PM PDT 24
Peak memory 206368 kb
Host smart-2e386009-0c60-4a45-9f1b-9bd3f1d2a7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14279
92178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.1427992178
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1948519682
Short name T2622
Test name
Test status
Simulation time 7411831243 ps
CPU time 51.94 seconds
Started Jul 11 05:57:15 PM PDT 24
Finished Jul 11 05:58:08 PM PDT 24
Peak memory 206516 kb
Host smart-83900892-83fb-4dd0-8f5e-af210fc4ea6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19485
19682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1948519682
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.4217072683
Short name T1423
Test name
Test status
Simulation time 61928421 ps
CPU time 0.71 seconds
Started Jul 11 05:57:37 PM PDT 24
Finished Jul 11 05:57:42 PM PDT 24
Peak memory 206428 kb
Host smart-638deebd-d0c0-495b-8643-da8669d75547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4217072683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.4217072683
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.605745648
Short name T1499
Test name
Test status
Simulation time 4400174629 ps
CPU time 5.39 seconds
Started Jul 11 05:57:22 PM PDT 24
Finished Jul 11 05:57:31 PM PDT 24
Peak memory 206524 kb
Host smart-d23bc640-a17d-4f4e-9eef-55fc4fe3ff9e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=605745648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.605745648
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.4051599397
Short name T607
Test name
Test status
Simulation time 13412622639 ps
CPU time 12.68 seconds
Started Jul 11 05:57:21 PM PDT 24
Finished Jul 11 05:57:36 PM PDT 24
Peak memory 206724 kb
Host smart-980f4586-670d-4ed8-87b1-03078cbbfd5a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4051599397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.4051599397
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2349995083
Short name T2185
Test name
Test status
Simulation time 23328984462 ps
CPU time 30.56 seconds
Started Jul 11 05:57:20 PM PDT 24
Finished Jul 11 05:57:52 PM PDT 24
Peak memory 206468 kb
Host smart-4f3bdb4e-3ce1-4279-a1a3-cd0bd63c6477
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2349995083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2349995083
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.153747712
Short name T419
Test name
Test status
Simulation time 149542451 ps
CPU time 0.83 seconds
Started Jul 11 05:57:17 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206376 kb
Host smart-848fed75-cd50-4cf2-b66c-236189d2995f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15374
7712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.153747712
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1037251964
Short name T64
Test name
Test status
Simulation time 160962862 ps
CPU time 0.79 seconds
Started Jul 11 05:57:16 PM PDT 24
Finished Jul 11 05:57:19 PM PDT 24
Peak memory 206404 kb
Host smart-0cf138e4-dd42-4d49-9dd3-adae863dd9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10372
51964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1037251964
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2798892898
Short name T956
Test name
Test status
Simulation time 509381666 ps
CPU time 1.54 seconds
Started Jul 11 05:57:21 PM PDT 24
Finished Jul 11 05:57:26 PM PDT 24
Peak memory 206656 kb
Host smart-7e872918-843f-490c-976a-b3b6b9e0c21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
92898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2798892898
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1976661498
Short name T1597
Test name
Test status
Simulation time 632594195 ps
CPU time 1.6 seconds
Started Jul 11 05:57:20 PM PDT 24
Finished Jul 11 05:57:23 PM PDT 24
Peak memory 206388 kb
Host smart-7d666180-9f2f-460a-bab0-de7054482b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19766
61498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1976661498
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.2236536169
Short name T2197
Test name
Test status
Simulation time 17600786271 ps
CPU time 33.55 seconds
Started Jul 11 05:57:22 PM PDT 24
Finished Jul 11 05:57:58 PM PDT 24
Peak memory 206568 kb
Host smart-566eeb65-1fb3-46b8-8f77-cd4195a4e35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
36169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.2236536169
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.2731513665
Short name T1873
Test name
Test status
Simulation time 363912943 ps
CPU time 1.14 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206336 kb
Host smart-dee50f96-ebb4-448a-b3ef-93af5aa201c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
13665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.2731513665
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3714571821
Short name T2743
Test name
Test status
Simulation time 134236681 ps
CPU time 0.78 seconds
Started Jul 11 05:57:26 PM PDT 24
Finished Jul 11 05:57:33 PM PDT 24
Peak memory 206400 kb
Host smart-122261e9-a89d-4f7e-8028-c79d89150f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37145
71821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3714571821
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1905018777
Short name T1174
Test name
Test status
Simulation time 51508094 ps
CPU time 0.68 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:27 PM PDT 24
Peak memory 206372 kb
Host smart-346c8288-256b-4f65-a094-fc236ae1b96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19050
18777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1905018777
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2731031721
Short name T1181
Test name
Test status
Simulation time 826408110 ps
CPU time 2.03 seconds
Started Jul 11 05:57:22 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206584 kb
Host smart-8191dd52-1fd5-4714-b8d0-226e299c6063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27310
31721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2731031721
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3273517293
Short name T2078
Test name
Test status
Simulation time 157852158 ps
CPU time 1.35 seconds
Started Jul 11 05:57:24 PM PDT 24
Finished Jul 11 05:57:29 PM PDT 24
Peak memory 206664 kb
Host smart-9a973ea1-520f-4d8d-a7cc-f2c27557257b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32735
17293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3273517293
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3288086199
Short name T575
Test name
Test status
Simulation time 216643875 ps
CPU time 0.88 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206296 kb
Host smart-8476ce57-4468-4b7c-8164-048dd24d1849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
86199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3288086199
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2402054916
Short name T2157
Test name
Test status
Simulation time 173578346 ps
CPU time 0.77 seconds
Started Jul 11 05:57:19 PM PDT 24
Finished Jul 11 05:57:22 PM PDT 24
Peak memory 206380 kb
Host smart-df8e272f-a680-4d8a-a764-0de7fd8ec905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24020
54916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2402054916
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2602546234
Short name T2162
Test name
Test status
Simulation time 178770105 ps
CPU time 0.83 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206316 kb
Host smart-5a8dc981-37e0-4d6f-b91b-d34dae8eb78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26025
46234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2602546234
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.546851620
Short name T1503
Test name
Test status
Simulation time 4019528916 ps
CPU time 15.58 seconds
Started Jul 11 05:57:49 PM PDT 24
Finished Jul 11 05:58:08 PM PDT 24
Peak memory 206708 kb
Host smart-516bb615-9a4b-4ee5-8397-6b79a30cbc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54685
1620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.546851620
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1288698210
Short name T1962
Test name
Test status
Simulation time 178445413 ps
CPU time 0.8 seconds
Started Jul 11 05:57:29 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206380 kb
Host smart-1d375622-4256-4745-85e7-9675addf381c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886
98210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1288698210
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3068363004
Short name T2351
Test name
Test status
Simulation time 23373207062 ps
CPU time 25.25 seconds
Started Jul 11 05:57:28 PM PDT 24
Finished Jul 11 05:57:59 PM PDT 24
Peak memory 206448 kb
Host smart-83bd7dac-7f9f-47cb-8fac-4ef39b12558f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30683
63004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3068363004
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1182251695
Short name T1237
Test name
Test status
Simulation time 3282916240 ps
CPU time 4.33 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:31 PM PDT 24
Peak memory 206408 kb
Host smart-bf83ca66-debb-4679-92bb-f1cd2742357e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11822
51695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1182251695
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.4078773303
Short name T617
Test name
Test status
Simulation time 6790437576 ps
CPU time 61.22 seconds
Started Jul 11 05:57:25 PM PDT 24
Finished Jul 11 05:58:31 PM PDT 24
Peak memory 206744 kb
Host smart-94610d9b-6688-47bc-8784-303dd9950404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40787
73303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.4078773303
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1804772762
Short name T538
Test name
Test status
Simulation time 6754131784 ps
CPU time 190.87 seconds
Started Jul 11 05:57:49 PM PDT 24
Finished Jul 11 06:01:03 PM PDT 24
Peak memory 206620 kb
Host smart-40deb26f-f5d6-4110-b39a-b7daf0ad80a4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1804772762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1804772762
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.447133112
Short name T872
Test name
Test status
Simulation time 237373275 ps
CPU time 0.94 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206380 kb
Host smart-7b844934-f0f4-4b69-aaea-fdeccae37b43
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=447133112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.447133112
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1305914726
Short name T228
Test name
Test status
Simulation time 213031394 ps
CPU time 0.83 seconds
Started Jul 11 05:57:18 PM PDT 24
Finished Jul 11 05:57:21 PM PDT 24
Peak memory 206384 kb
Host smart-6fa59c01-8510-497f-a599-92b466082653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13059
14726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1305914726
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2350354703
Short name T598
Test name
Test status
Simulation time 5123154731 ps
CPU time 136.81 seconds
Started Jul 11 05:57:30 PM PDT 24
Finished Jul 11 05:59:53 PM PDT 24
Peak memory 206764 kb
Host smart-13c6487d-6f40-4ebb-a9b5-3cfa969f8abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23503
54703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2350354703
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2850032820
Short name T2706
Test name
Test status
Simulation time 4748508254 ps
CPU time 33.35 seconds
Started Jul 11 05:57:26 PM PDT 24
Finished Jul 11 05:58:05 PM PDT 24
Peak memory 206664 kb
Host smart-4d239fde-4a82-41bc-9887-29e1f0e003f8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2850032820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2850032820
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1182996783
Short name T1959
Test name
Test status
Simulation time 164182277 ps
CPU time 0.86 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:27 PM PDT 24
Peak memory 206388 kb
Host smart-37b69d7f-766f-4ea7-bbfd-44aa00039996
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1182996783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1182996783
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3061786801
Short name T1685
Test name
Test status
Simulation time 139103060 ps
CPU time 0.86 seconds
Started Jul 11 05:57:26 PM PDT 24
Finished Jul 11 05:57:32 PM PDT 24
Peak memory 206388 kb
Host smart-ed66a2f7-a140-4dd9-8817-6a9b4baf8e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30617
86801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3061786801
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3481222704
Short name T1046
Test name
Test status
Simulation time 188743362 ps
CPU time 0.84 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:27 PM PDT 24
Peak memory 206388 kb
Host smart-a4d655d8-2d1f-498f-aa7f-6eae5a7ef184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34812
22704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3481222704
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2558113554
Short name T1489
Test name
Test status
Simulation time 183041858 ps
CPU time 0.81 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206404 kb
Host smart-b87baefb-4074-4f10-a7d9-75dd46e9e509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25581
13554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2558113554
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3067872890
Short name T359
Test name
Test status
Simulation time 168900393 ps
CPU time 0.8 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206388 kb
Host smart-0b118a88-c19a-433b-a444-d781462c18a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30678
72890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3067872890
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1600916420
Short name T2512
Test name
Test status
Simulation time 180421444 ps
CPU time 0.79 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206324 kb
Host smart-3f7b9cf2-384b-4778-ab41-d81358039c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16009
16420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1600916420
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.4290963394
Short name T179
Test name
Test status
Simulation time 150383754 ps
CPU time 0.81 seconds
Started Jul 11 05:57:27 PM PDT 24
Finished Jul 11 05:57:34 PM PDT 24
Peak memory 206396 kb
Host smart-eece0df0-ec46-4c25-871e-108003cba31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42909
63394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.4290963394
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3845664240
Short name T1996
Test name
Test status
Simulation time 202258351 ps
CPU time 0.87 seconds
Started Jul 11 05:57:25 PM PDT 24
Finished Jul 11 05:57:31 PM PDT 24
Peak memory 206420 kb
Host smart-ac55febf-2bb1-4f33-abd0-ac52bd7db08c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3845664240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3845664240
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3842411347
Short name T2036
Test name
Test status
Simulation time 145676746 ps
CPU time 0.75 seconds
Started Jul 11 05:57:24 PM PDT 24
Finished Jul 11 05:57:29 PM PDT 24
Peak memory 206404 kb
Host smart-e0d54894-7f98-4305-a540-7adff964a94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38424
11347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3842411347
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.409658385
Short name T1291
Test name
Test status
Simulation time 52316808 ps
CPU time 0.68 seconds
Started Jul 11 05:57:26 PM PDT 24
Finished Jul 11 05:57:33 PM PDT 24
Peak memory 206404 kb
Host smart-1dde29e3-97fa-4cf5-bb65-dd7d2700d62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40965
8385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.409658385
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.536707585
Short name T1705
Test name
Test status
Simulation time 17968721768 ps
CPU time 37.72 seconds
Started Jul 11 05:57:24 PM PDT 24
Finished Jul 11 05:58:06 PM PDT 24
Peak memory 206700 kb
Host smart-73160a1a-d71f-4448-b8d4-12aaad202855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53670
7585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.536707585
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3897443671
Short name T974
Test name
Test status
Simulation time 162875875 ps
CPU time 0.77 seconds
Started Jul 11 05:57:28 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206388 kb
Host smart-87f564ee-ad4a-4748-b625-2aa2b8aed8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38974
43671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3897443671
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1795476259
Short name T1143
Test name
Test status
Simulation time 256714553 ps
CPU time 0.97 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206376 kb
Host smart-ad2f5058-b1af-4597-bbed-590cae8e47be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
76259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1795476259
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.201876500
Short name T1871
Test name
Test status
Simulation time 179251658 ps
CPU time 0.83 seconds
Started Jul 11 05:57:30 PM PDT 24
Finished Jul 11 05:57:37 PM PDT 24
Peak memory 206400 kb
Host smart-ebd80502-c357-4bbe-a839-e700b92d8311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20187
6500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.201876500
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3783367837
Short name T456
Test name
Test status
Simulation time 171385973 ps
CPU time 0.88 seconds
Started Jul 11 05:57:27 PM PDT 24
Finished Jul 11 05:57:34 PM PDT 24
Peak memory 206388 kb
Host smart-d221c1a1-e17d-4128-a07d-73356e6f94f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37833
67837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3783367837
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2954809344
Short name T1086
Test name
Test status
Simulation time 179949731 ps
CPU time 0.83 seconds
Started Jul 11 05:57:20 PM PDT 24
Finished Jul 11 05:57:23 PM PDT 24
Peak memory 206348 kb
Host smart-7dc2eb6c-9be4-4e17-b2c8-34b3b6a12e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29548
09344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2954809344
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2296620308
Short name T829
Test name
Test status
Simulation time 158596527 ps
CPU time 0.82 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 206384 kb
Host smart-37fdca65-b9ed-4715-954c-f8a131ffc4e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22966
20308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2296620308
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3505820248
Short name T917
Test name
Test status
Simulation time 151148243 ps
CPU time 0.8 seconds
Started Jul 11 05:57:25 PM PDT 24
Finished Jul 11 05:57:30 PM PDT 24
Peak memory 206328 kb
Host smart-b4bb9ec0-d6ac-4c07-86fd-ad439996bcda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
20248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3505820248
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.4282318635
Short name T891
Test name
Test status
Simulation time 218486473 ps
CPU time 0.91 seconds
Started Jul 11 05:57:24 PM PDT 24
Finished Jul 11 05:57:29 PM PDT 24
Peak memory 206372 kb
Host smart-e3df62f1-04d1-40d8-ba1b-f8202db063c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42823
18635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.4282318635
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.169019073
Short name T1656
Test name
Test status
Simulation time 3220983505 ps
CPU time 23.74 seconds
Started Jul 11 05:57:23 PM PDT 24
Finished Jul 11 05:57:51 PM PDT 24
Peak memory 206676 kb
Host smart-8a26dd4c-cda0-4ea1-a8b7-e44ffade4b78
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=169019073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.169019073
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2852148738
Short name T1584
Test name
Test status
Simulation time 182177253 ps
CPU time 0.83 seconds
Started Jul 11 05:57:26 PM PDT 24
Finished Jul 11 05:57:33 PM PDT 24
Peak memory 206404 kb
Host smart-6c153f7d-e69d-40c9-96b1-911b34058886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28521
48738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2852148738
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1534532750
Short name T2448
Test name
Test status
Simulation time 212675743 ps
CPU time 0.93 seconds
Started Jul 11 05:57:30 PM PDT 24
Finished Jul 11 05:57:37 PM PDT 24
Peak memory 206436 kb
Host smart-3d93b181-7a18-4540-96b7-c3b9081c2393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15345
32750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1534532750
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.235432073
Short name T780
Test name
Test status
Simulation time 543403700 ps
CPU time 1.38 seconds
Started Jul 11 05:57:22 PM PDT 24
Finished Jul 11 05:57:26 PM PDT 24
Peak memory 206400 kb
Host smart-4b1f96b8-1d5d-4b3a-a298-5aca34fb7ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23543
2073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.235432073
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2176149372
Short name T2441
Test name
Test status
Simulation time 3623930129 ps
CPU time 33.45 seconds
Started Jul 11 05:57:21 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 206696 kb
Host smart-a4600422-ef50-4aef-9819-2d5524adb783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21761
49372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2176149372
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3089819321
Short name T994
Test name
Test status
Simulation time 47376826 ps
CPU time 0.67 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206424 kb
Host smart-338124f8-fc0a-471e-aef4-17f0f0b3873c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3089819321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3089819321
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2096770249
Short name T2104
Test name
Test status
Simulation time 3973670100 ps
CPU time 4.52 seconds
Started Jul 11 05:57:26 PM PDT 24
Finished Jul 11 05:57:36 PM PDT 24
Peak memory 206372 kb
Host smart-b9c100a6-abfd-4c90-b4a9-85edbc36d0ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2096770249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2096770249
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1483918454
Short name T2405
Test name
Test status
Simulation time 13446022481 ps
CPU time 12.41 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:58:09 PM PDT 24
Peak memory 206440 kb
Host smart-b12c3731-57b8-4eae-aae5-7f2f787b01a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1483918454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1483918454
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2944746823
Short name T2497
Test name
Test status
Simulation time 23399659214 ps
CPU time 26.17 seconds
Started Jul 11 05:57:29 PM PDT 24
Finished Jul 11 05:58:01 PM PDT 24
Peak memory 206728 kb
Host smart-56d794dc-0295-40e7-b2f9-0f5b5d713aa0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2944746823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2944746823
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3968881130
Short name T1857
Test name
Test status
Simulation time 172750121 ps
CPU time 0.79 seconds
Started Jul 11 05:57:28 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206372 kb
Host smart-216f5115-08b8-4eed-8bcf-e6fd72006afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39688
81130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3968881130
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1777834527
Short name T1303
Test name
Test status
Simulation time 142542709 ps
CPU time 0.82 seconds
Started Jul 11 05:57:32 PM PDT 24
Finished Jul 11 05:57:39 PM PDT 24
Peak memory 206372 kb
Host smart-079e1a43-e6ce-418b-88bf-38e8108687ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17778
34527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1777834527
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2413664874
Short name T119
Test name
Test status
Simulation time 452470926 ps
CPU time 1.4 seconds
Started Jul 11 05:57:31 PM PDT 24
Finished Jul 11 05:57:38 PM PDT 24
Peak memory 206324 kb
Host smart-3e680106-5aa7-4db1-8bdb-e50238522148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24136
64874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2413664874
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1815455909
Short name T1767
Test name
Test status
Simulation time 747541559 ps
CPU time 1.77 seconds
Started Jul 11 05:57:34 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206616 kb
Host smart-90214344-240f-4b25-ac33-aca282d0d3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18154
55909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1815455909
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3076842628
Short name T2073
Test name
Test status
Simulation time 18927524986 ps
CPU time 33.55 seconds
Started Jul 11 05:57:31 PM PDT 24
Finished Jul 11 05:58:11 PM PDT 24
Peak memory 206724 kb
Host smart-0eb00c63-6f03-41ea-a57f-2bcd5bbb94f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30768
42628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3076842628
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.3443180511
Short name T807
Test name
Test status
Simulation time 412143582 ps
CPU time 1.34 seconds
Started Jul 11 05:57:32 PM PDT 24
Finished Jul 11 05:57:39 PM PDT 24
Peak memory 206392 kb
Host smart-be61d9c4-c2fa-4d1b-9814-be421a0162ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34431
80511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.3443180511
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2813441936
Short name T2404
Test name
Test status
Simulation time 209660825 ps
CPU time 0.8 seconds
Started Jul 11 05:57:34 PM PDT 24
Finished Jul 11 05:57:40 PM PDT 24
Peak memory 206308 kb
Host smart-5f38f049-5d5b-48a0-a7a2-988c93720e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28134
41936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2813441936
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1391894738
Short name T1483
Test name
Test status
Simulation time 35685625 ps
CPU time 0.66 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:57:56 PM PDT 24
Peak memory 206368 kb
Host smart-91519046-d4ee-420e-9129-662e1d73489e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13918
94738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1391894738
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.575869990
Short name T2388
Test name
Test status
Simulation time 778894409 ps
CPU time 1.97 seconds
Started Jul 11 05:57:33 PM PDT 24
Finished Jul 11 05:57:40 PM PDT 24
Peak memory 206576 kb
Host smart-d129cb3f-fad9-4c66-a1c7-c987f45d58b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57586
9990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.575869990
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2626658257
Short name T1847
Test name
Test status
Simulation time 159298057 ps
CPU time 1.22 seconds
Started Jul 11 05:57:27 PM PDT 24
Finished Jul 11 05:57:34 PM PDT 24
Peak memory 206512 kb
Host smart-cd4fd8fe-2c99-46b1-8b2b-c4fe4c277edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26266
58257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2626658257
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3962994569
Short name T397
Test name
Test status
Simulation time 208868977 ps
CPU time 0.89 seconds
Started Jul 11 05:57:28 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206384 kb
Host smart-b959e003-cce1-4a66-905e-92d026c59437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39629
94569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3962994569
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3412805933
Short name T1811
Test name
Test status
Simulation time 154237880 ps
CPU time 0.76 seconds
Started Jul 11 05:57:25 PM PDT 24
Finished Jul 11 05:57:31 PM PDT 24
Peak memory 206260 kb
Host smart-631ece6d-838a-4767-b99e-c16007d58534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
05933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3412805933
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.710918033
Short name T477
Test name
Test status
Simulation time 209824294 ps
CPU time 0.88 seconds
Started Jul 11 05:57:26 PM PDT 24
Finished Jul 11 05:57:33 PM PDT 24
Peak memory 206400 kb
Host smart-b1d2f344-6784-4ea6-9c49-a34a92d3948a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71091
8033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.710918033
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3453531965
Short name T2398
Test name
Test status
Simulation time 236276438 ps
CPU time 0.92 seconds
Started Jul 11 05:57:28 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206388 kb
Host smart-9a0097e6-97b0-43be-8391-e87c57711b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34535
31965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3453531965
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.1866359325
Short name T1302
Test name
Test status
Simulation time 23270500988 ps
CPU time 23.49 seconds
Started Jul 11 05:57:33 PM PDT 24
Finished Jul 11 05:58:02 PM PDT 24
Peak memory 206408 kb
Host smart-f084a585-f112-452b-a629-d627cdb3f54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18663
59325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1866359325
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1941406227
Short name T2414
Test name
Test status
Simulation time 3332397664 ps
CPU time 3.93 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:57:44 PM PDT 24
Peak memory 206408 kb
Host smart-f406d945-fbe7-4c75-b678-2d6c4120e21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414
06227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1941406227
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.2078088284
Short name T439
Test name
Test status
Simulation time 11554093424 ps
CPU time 101.35 seconds
Started Jul 11 05:57:26 PM PDT 24
Finished Jul 11 05:59:13 PM PDT 24
Peak memory 206708 kb
Host smart-15dbe25f-47f7-4020-aac9-3e187f2976b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20780
88284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.2078088284
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1686197568
Short name T865
Test name
Test status
Simulation time 4713946583 ps
CPU time 133.23 seconds
Started Jul 11 05:57:34 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206572 kb
Host smart-5432b173-0104-411c-be49-ef553d5040c9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1686197568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1686197568
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.568072602
Short name T1166
Test name
Test status
Simulation time 253915387 ps
CPU time 0.9 seconds
Started Jul 11 05:57:29 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206368 kb
Host smart-5cdfe0eb-d498-4e45-bf0a-a08e80fef6c3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=568072602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.568072602
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2731403747
Short name T406
Test name
Test status
Simulation time 194369640 ps
CPU time 0.91 seconds
Started Jul 11 05:57:30 PM PDT 24
Finished Jul 11 05:57:37 PM PDT 24
Peak memory 206388 kb
Host smart-f458937a-091c-4b8e-950e-e6ef367c6598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27314
03747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2731403747
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2289346592
Short name T1049
Test name
Test status
Simulation time 3950589628 ps
CPU time 110.44 seconds
Started Jul 11 05:57:29 PM PDT 24
Finished Jul 11 05:59:25 PM PDT 24
Peak memory 206656 kb
Host smart-bfd5fc25-ef03-450f-8c0e-977fb2724f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22893
46592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2289346592
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.4276571871
Short name T2595
Test name
Test status
Simulation time 4196144636 ps
CPU time 118.97 seconds
Started Jul 11 05:57:25 PM PDT 24
Finished Jul 11 05:59:30 PM PDT 24
Peak memory 206652 kb
Host smart-d91f1e11-db95-4930-a500-2c9bbe793476
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4276571871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.4276571871
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.2073235447
Short name T2227
Test name
Test status
Simulation time 184795538 ps
CPU time 0.83 seconds
Started Jul 11 05:57:31 PM PDT 24
Finished Jul 11 05:57:38 PM PDT 24
Peak memory 206304 kb
Host smart-0bfcbc7c-e74e-497e-9399-12dfbaf2ddcd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2073235447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.2073235447
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.721338497
Short name T1763
Test name
Test status
Simulation time 205257235 ps
CPU time 0.81 seconds
Started Jul 11 05:57:27 PM PDT 24
Finished Jul 11 05:57:34 PM PDT 24
Peak memory 206380 kb
Host smart-20d3f5e5-1488-4780-889a-673ba2596f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72133
8497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.721338497
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.250920787
Short name T104
Test name
Test status
Simulation time 193677762 ps
CPU time 0.87 seconds
Started Jul 11 05:57:31 PM PDT 24
Finished Jul 11 05:57:37 PM PDT 24
Peak memory 206372 kb
Host smart-0e4b830d-0565-423f-8f43-e5c555072331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25092
0787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.250920787
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.207973446
Short name T560
Test name
Test status
Simulation time 220760811 ps
CPU time 0.88 seconds
Started Jul 11 05:57:38 PM PDT 24
Finished Jul 11 05:57:43 PM PDT 24
Peak memory 206364 kb
Host smart-de1e3a10-3de0-4d9f-8b8f-8adf123ab9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
3446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.207973446
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3180160937
Short name T2707
Test name
Test status
Simulation time 209595188 ps
CPU time 0.86 seconds
Started Jul 11 05:57:40 PM PDT 24
Finished Jul 11 05:57:44 PM PDT 24
Peak memory 206348 kb
Host smart-b284fbb9-fbde-4001-880d-6854b268c571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31801
60937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3180160937
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.255021236
Short name T2334
Test name
Test status
Simulation time 152331912 ps
CPU time 0.81 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206392 kb
Host smart-0286f1dc-c449-49a8-8444-d8a5c8deb6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25502
1236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.255021236
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1256119861
Short name T1951
Test name
Test status
Simulation time 246759095 ps
CPU time 0.94 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206376 kb
Host smart-ec7cc8cd-df6e-4c61-8f90-f3176a31d862
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1256119861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1256119861
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2708405750
Short name T709
Test name
Test status
Simulation time 191611552 ps
CPU time 0.86 seconds
Started Jul 11 05:57:32 PM PDT 24
Finished Jul 11 05:57:39 PM PDT 24
Peak memory 206388 kb
Host smart-3962c2e7-7794-4ed3-98c8-11d1cd0f89d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27084
05750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2708405750
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3412573883
Short name T2355
Test name
Test status
Simulation time 31809599 ps
CPU time 0.64 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206380 kb
Host smart-6851c6b3-517b-4b68-8ac5-29956b402a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
73883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3412573883
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1780327939
Short name T2558
Test name
Test status
Simulation time 14787336401 ps
CPU time 31.96 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:58:12 PM PDT 24
Peak memory 206676 kb
Host smart-578e0925-c694-41c1-b97b-50bb568f159f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17803
27939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1780327939
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1846580237
Short name T1522
Test name
Test status
Simulation time 181039849 ps
CPU time 0.8 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206388 kb
Host smart-01837545-7c50-4a84-b1f2-0b5c2ce68e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18465
80237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1846580237
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.364741827
Short name T2589
Test name
Test status
Simulation time 259651698 ps
CPU time 0.93 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206392 kb
Host smart-d913ba26-2587-43a5-a201-82324bc4c3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36474
1827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.364741827
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2618342755
Short name T2514
Test name
Test status
Simulation time 186458391 ps
CPU time 0.81 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:42 PM PDT 24
Peak memory 206308 kb
Host smart-3c9608e0-76ce-4a49-89d7-83c26d89a2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26183
42755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2618342755
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.205674580
Short name T1769
Test name
Test status
Simulation time 178735546 ps
CPU time 0.83 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206384 kb
Host smart-22cf474e-7f3f-4618-b0bc-42fd2b5982cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20567
4580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.205674580
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2702021796
Short name T601
Test name
Test status
Simulation time 153502684 ps
CPU time 0.84 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:42 PM PDT 24
Peak memory 206396 kb
Host smart-95963365-97e5-47d7-9fd7-57b9f4726d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020
21796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2702021796
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.808737699
Short name T885
Test name
Test status
Simulation time 205120258 ps
CPU time 0.79 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:57:56 PM PDT 24
Peak memory 206396 kb
Host smart-d0901c28-95cb-4a5e-84de-aae87a7cd8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80873
7699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.808737699
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.316897852
Short name T380
Test name
Test status
Simulation time 149059687 ps
CPU time 0.81 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206372 kb
Host smart-c5d16037-7977-425f-90e2-bf0b4629c3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
7852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.316897852
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2509232657
Short name T1518
Test name
Test status
Simulation time 225501814 ps
CPU time 0.92 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206384 kb
Host smart-cb1082a7-7b10-4338-b7ed-1b623a8b1fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25092
32657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2509232657
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3585016
Short name T2008
Test name
Test status
Simulation time 5459959866 ps
CPU time 38.38 seconds
Started Jul 11 05:57:41 PM PDT 24
Finished Jul 11 05:58:23 PM PDT 24
Peak memory 206708 kb
Host smart-0cfff310-a237-4ec1-b84d-21471979fcaf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3585016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3585016
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2281676792
Short name T1598
Test name
Test status
Simulation time 198698594 ps
CPU time 0.8 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206392 kb
Host smart-195b5917-e113-47f4-91b5-304e7fa2fc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22816
76792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2281676792
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3519505408
Short name T622
Test name
Test status
Simulation time 160461307 ps
CPU time 0.84 seconds
Started Jul 11 05:57:37 PM PDT 24
Finished Jul 11 05:57:42 PM PDT 24
Peak memory 206388 kb
Host smart-414cdd82-0671-4d63-be68-c5631de70835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35195
05408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3519505408
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2517896233
Short name T2557
Test name
Test status
Simulation time 554707117 ps
CPU time 1.48 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206376 kb
Host smart-6933a841-7147-4f10-9ce6-99b613a35594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25178
96233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2517896233
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.876106027
Short name T1779
Test name
Test status
Simulation time 7816619122 ps
CPU time 203.25 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206656 kb
Host smart-6e94d402-baeb-424b-90ea-e44522ab7f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87610
6027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.876106027
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.906611545
Short name T1643
Test name
Test status
Simulation time 87796379 ps
CPU time 0.69 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:53 PM PDT 24
Peak memory 205968 kb
Host smart-eff513e9-32ce-4284-9cfd-8558c5d3b151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=906611545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.906611545
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1911262181
Short name T746
Test name
Test status
Simulation time 4128724868 ps
CPU time 4.49 seconds
Started Jul 11 05:57:41 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206464 kb
Host smart-c8907e07-07bd-4cb6-aed8-58ac9577cdc7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1911262181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.1911262181
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4169468502
Short name T2478
Test name
Test status
Simulation time 13369215033 ps
CPU time 15.33 seconds
Started Jul 11 05:57:30 PM PDT 24
Finished Jul 11 05:57:50 PM PDT 24
Peak memory 206716 kb
Host smart-06e63b97-c608-42c1-aaa1-41bbe5fa523e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4169468502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4169468502
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1445810689
Short name T706
Test name
Test status
Simulation time 23357659994 ps
CPU time 24.21 seconds
Started Jul 11 05:57:38 PM PDT 24
Finished Jul 11 05:58:07 PM PDT 24
Peak memory 206696 kb
Host smart-852404fa-b159-4e52-b3c2-de150d16b571
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1445810689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1445810689
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1030090348
Short name T1762
Test name
Test status
Simulation time 177387080 ps
CPU time 0.85 seconds
Started Jul 11 05:57:32 PM PDT 24
Finished Jul 11 05:57:38 PM PDT 24
Peak memory 206368 kb
Host smart-4f9f0eb5-f03b-4782-934e-30ac15df5a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10300
90348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1030090348
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1853583585
Short name T1776
Test name
Test status
Simulation time 214861184 ps
CPU time 0.8 seconds
Started Jul 11 05:57:38 PM PDT 24
Finished Jul 11 05:57:43 PM PDT 24
Peak memory 206296 kb
Host smart-cfc4ffff-7344-4b57-bbfc-6e1fe413fd98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18535
83585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1853583585
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.346644947
Short name T320
Test name
Test status
Simulation time 437042244 ps
CPU time 1.37 seconds
Started Jul 11 05:57:34 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206396 kb
Host smart-1fae50b7-b001-4577-a309-d221cfb09cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34664
4947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.346644947
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.4088685686
Short name T703
Test name
Test status
Simulation time 713537308 ps
CPU time 1.74 seconds
Started Jul 11 05:57:37 PM PDT 24
Finished Jul 11 05:57:43 PM PDT 24
Peak memory 206524 kb
Host smart-751bee98-d749-4205-a620-e0656473cdef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40886
85686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.4088685686
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.316004527
Short name T1120
Test name
Test status
Simulation time 17234042676 ps
CPU time 31.25 seconds
Started Jul 11 05:57:40 PM PDT 24
Finished Jul 11 05:58:15 PM PDT 24
Peak memory 206596 kb
Host smart-5e2eaaa1-112f-4082-ba15-678014309233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31600
4527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.316004527
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3370345509
Short name T2164
Test name
Test status
Simulation time 382641716 ps
CPU time 1.27 seconds
Started Jul 11 05:57:35 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206372 kb
Host smart-163f1e75-169f-437a-884d-3c1b684952ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
45509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3370345509
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1760785512
Short name T1611
Test name
Test status
Simulation time 154614951 ps
CPU time 0.8 seconds
Started Jul 11 05:57:32 PM PDT 24
Finished Jul 11 05:57:38 PM PDT 24
Peak memory 206296 kb
Host smart-95712a59-c961-4f87-bdaf-c7852dd5bc9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17607
85512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1760785512
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.331059919
Short name T1490
Test name
Test status
Simulation time 42964724 ps
CPU time 0.64 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:57:48 PM PDT 24
Peak memory 206368 kb
Host smart-8efdadde-0dc5-4124-b74e-9f417b88b93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33105
9919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.331059919
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1375425270
Short name T1092
Test name
Test status
Simulation time 853094008 ps
CPU time 1.95 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:42 PM PDT 24
Peak memory 206588 kb
Host smart-ab090323-cd44-4993-b74d-57e802e712b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13754
25270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1375425270
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.140583600
Short name T1244
Test name
Test status
Simulation time 295884824 ps
CPU time 2.03 seconds
Started Jul 11 05:57:37 PM PDT 24
Finished Jul 11 05:57:44 PM PDT 24
Peak memory 206504 kb
Host smart-2eb2afeb-b356-41ff-aa0d-6e807dd1f020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14058
3600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.140583600
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.342328153
Short name T1313
Test name
Test status
Simulation time 220946020 ps
CPU time 0.87 seconds
Started Jul 11 05:57:44 PM PDT 24
Finished Jul 11 05:57:48 PM PDT 24
Peak memory 206380 kb
Host smart-570e2473-585f-4d60-806d-fe6f45ac8093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34232
8153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.342328153
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3434725746
Short name T1676
Test name
Test status
Simulation time 151811964 ps
CPU time 0.8 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206380 kb
Host smart-cbdac23f-8b16-4283-aeb5-9b433337aa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34347
25746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3434725746
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.114093441
Short name T318
Test name
Test status
Simulation time 226162698 ps
CPU time 0.9 seconds
Started Jul 11 05:57:41 PM PDT 24
Finished Jul 11 05:57:45 PM PDT 24
Peak memory 206384 kb
Host smart-60770707-5433-44d7-a9cb-d34aca60d58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11409
3441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.114093441
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.1917044790
Short name T2449
Test name
Test status
Simulation time 5822396777 ps
CPU time 53.04 seconds
Started Jul 11 05:57:37 PM PDT 24
Finished Jul 11 05:58:35 PM PDT 24
Peak memory 206708 kb
Host smart-5169b007-9d75-4b3e-a481-277f1b48fcfa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1917044790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.1917044790
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2507580494
Short name T1746
Test name
Test status
Simulation time 199355489 ps
CPU time 0.84 seconds
Started Jul 11 05:57:41 PM PDT 24
Finished Jul 11 05:57:45 PM PDT 24
Peak memory 206292 kb
Host smart-0f651c3e-8293-4a04-af7e-ba46b1d26593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075
80494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2507580494
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.2112794353
Short name T1662
Test name
Test status
Simulation time 23358693037 ps
CPU time 22.08 seconds
Started Jul 11 05:57:42 PM PDT 24
Finished Jul 11 05:58:07 PM PDT 24
Peak memory 206456 kb
Host smart-cd624dd0-13fd-4e41-812d-4f3c000d69a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21127
94353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.2112794353
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1533170586
Short name T41
Test name
Test status
Simulation time 3364001216 ps
CPU time 4.03 seconds
Started Jul 11 05:57:56 PM PDT 24
Finished Jul 11 05:58:06 PM PDT 24
Peak memory 206360 kb
Host smart-79136e28-8725-40ef-bb3f-33073af04957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15331
70586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1533170586
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3777999240
Short name T1770
Test name
Test status
Simulation time 8324456507 ps
CPU time 80.86 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:59:10 PM PDT 24
Peak memory 206700 kb
Host smart-9eff63db-3544-410b-84a7-f86f1f18fb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37779
99240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3777999240
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.4208786949
Short name T1035
Test name
Test status
Simulation time 6022489710 ps
CPU time 44.01 seconds
Started Jul 11 05:57:52 PM PDT 24
Finished Jul 11 05:58:41 PM PDT 24
Peak memory 206648 kb
Host smart-6276caa0-c39a-4560-a753-b13c38868c86
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4208786949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.4208786949
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.385097245
Short name T2147
Test name
Test status
Simulation time 235654112 ps
CPU time 0.87 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:52 PM PDT 24
Peak memory 206384 kb
Host smart-d58b3d8c-0dfe-46f4-98de-1b65b4fb6198
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=385097245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.385097245
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2565489862
Short name T1044
Test name
Test status
Simulation time 192668886 ps
CPU time 0.87 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206320 kb
Host smart-57dc9e8a-61e7-4e9d-946c-0f919d8c9a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25654
89862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2565489862
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.576863265
Short name T988
Test name
Test status
Simulation time 4379307240 ps
CPU time 40.68 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206668 kb
Host smart-31c88afb-db5d-434a-ae7d-7e0ce82c123c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57686
3265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.576863265
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1692572165
Short name T1194
Test name
Test status
Simulation time 2592049170 ps
CPU time 70.13 seconds
Started Jul 11 05:57:40 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 206616 kb
Host smart-aa65b390-28f8-45ea-9829-8f2daa74eadb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1692572165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1692572165
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3175968643
Short name T1813
Test name
Test status
Simulation time 163015513 ps
CPU time 0.83 seconds
Started Jul 11 05:57:54 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206320 kb
Host smart-42e794fe-9cbc-449b-9e22-99c0dcf31594
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3175968643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3175968643
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.4199908052
Short name T321
Test name
Test status
Simulation time 175088410 ps
CPU time 0.77 seconds
Started Jul 11 05:57:44 PM PDT 24
Finished Jul 11 05:57:48 PM PDT 24
Peak memory 206404 kb
Host smart-2ee55424-f54e-4b80-a0bd-de060153b911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41999
08052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.4199908052
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1215288576
Short name T156
Test name
Test status
Simulation time 178505846 ps
CPU time 0.82 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:57:50 PM PDT 24
Peak memory 206468 kb
Host smart-b7d21e55-c498-4467-b52f-efafcaafd5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12152
88576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1215288576
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.1624462439
Short name T1645
Test name
Test status
Simulation time 260232338 ps
CPU time 0.91 seconds
Started Jul 11 05:57:44 PM PDT 24
Finished Jul 11 05:57:48 PM PDT 24
Peak memory 206388 kb
Host smart-f6baef9b-4b3d-456c-89e1-ebbab9f36c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16244
62439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.1624462439
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.695965338
Short name T2649
Test name
Test status
Simulation time 196423946 ps
CPU time 0.83 seconds
Started Jul 11 05:57:40 PM PDT 24
Finished Jul 11 05:57:45 PM PDT 24
Peak memory 206384 kb
Host smart-bc8b9b4a-cea5-47d6-9e6b-a91987350379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69596
5338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.695965338
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1782600773
Short name T2145
Test name
Test status
Simulation time 188092669 ps
CPU time 0.83 seconds
Started Jul 11 05:57:43 PM PDT 24
Finished Jul 11 05:57:47 PM PDT 24
Peak memory 206392 kb
Host smart-4e1a0248-426c-4e7f-9540-ccea177ad5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17826
00773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1782600773
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2516932591
Short name T1068
Test name
Test status
Simulation time 188201009 ps
CPU time 0.8 seconds
Started Jul 11 05:57:54 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206324 kb
Host smart-05ef5866-52c4-48c5-9e4e-444d05c6a136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25169
32591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2516932591
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.417282904
Short name T1624
Test name
Test status
Simulation time 210930811 ps
CPU time 0.87 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 206400 kb
Host smart-3018a2ea-183d-457f-b46b-20d51ecdf508
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=417282904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.417282904
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.969675831
Short name T841
Test name
Test status
Simulation time 155887647 ps
CPU time 0.77 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 206392 kb
Host smart-93328e58-25f0-4796-96a8-464414d41e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96967
5831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.969675831
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2878246985
Short name T2566
Test name
Test status
Simulation time 35493992 ps
CPU time 0.64 seconds
Started Jul 11 05:57:43 PM PDT 24
Finished Jul 11 05:57:47 PM PDT 24
Peak memory 206380 kb
Host smart-6a9a7ff3-d826-42cb-8961-0609963bc761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28782
46985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2878246985
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1420031187
Short name T262
Test name
Test status
Simulation time 15004484631 ps
CPU time 31.24 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:58:20 PM PDT 24
Peak memory 206748 kb
Host smart-a009a68b-c5c8-4063-a11f-de82ac9cf44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14200
31187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1420031187
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2158259634
Short name T2555
Test name
Test status
Simulation time 214421775 ps
CPU time 0.86 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206320 kb
Host smart-603ff227-0ab4-4880-ba20-8ea3e5018688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21582
59634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2158259634
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.565782912
Short name T888
Test name
Test status
Simulation time 161469310 ps
CPU time 0.79 seconds
Started Jul 11 05:57:42 PM PDT 24
Finished Jul 11 05:57:46 PM PDT 24
Peak memory 206372 kb
Host smart-fc18f91d-90f2-4b65-b840-b5a237ad1a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56578
2912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.565782912
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3674256784
Short name T1907
Test name
Test status
Simulation time 247927657 ps
CPU time 0.9 seconds
Started Jul 11 05:57:43 PM PDT 24
Finished Jul 11 05:57:47 PM PDT 24
Peak memory 206392 kb
Host smart-7051abff-7234-4c99-afa6-c795e807768e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36742
56784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3674256784
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3140023074
Short name T360
Test name
Test status
Simulation time 161174382 ps
CPU time 0.8 seconds
Started Jul 11 05:57:43 PM PDT 24
Finished Jul 11 05:57:48 PM PDT 24
Peak memory 206388 kb
Host smart-92910ec9-7756-43de-bba0-23a87faee876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31400
23074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3140023074
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1396773207
Short name T1991
Test name
Test status
Simulation time 140243650 ps
CPU time 0.73 seconds
Started Jul 11 05:57:41 PM PDT 24
Finished Jul 11 05:57:45 PM PDT 24
Peak memory 206288 kb
Host smart-f2c5d6db-baf2-48d6-8be9-811a53efd099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13967
73207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1396773207
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.624043317
Short name T2472
Test name
Test status
Simulation time 215274216 ps
CPU time 0.88 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:53 PM PDT 24
Peak memory 206380 kb
Host smart-7448682f-08fc-44d0-80ba-3c5d16f64e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62404
3317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.624043317
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.431861505
Short name T555
Test name
Test status
Simulation time 162151907 ps
CPU time 0.77 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:53 PM PDT 24
Peak memory 206316 kb
Host smart-fbdcd962-7eec-4a8d-8c1c-74a036ed846f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43186
1505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.431861505
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2806777511
Short name T1168
Test name
Test status
Simulation time 243427525 ps
CPU time 0.96 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:53 PM PDT 24
Peak memory 206308 kb
Host smart-a20b7116-9711-492a-9d70-3c1f18c135d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28067
77511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2806777511
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.917084564
Short name T934
Test name
Test status
Simulation time 4938615517 ps
CPU time 46.08 seconds
Started Jul 11 05:57:40 PM PDT 24
Finished Jul 11 05:58:30 PM PDT 24
Peak memory 206600 kb
Host smart-ba34eca9-5380-4dde-9990-9f17974c5a0e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=917084564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.917084564
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2144759106
Short name T2274
Test name
Test status
Simulation time 164305619 ps
CPU time 0.8 seconds
Started Jul 11 05:57:40 PM PDT 24
Finished Jul 11 05:57:44 PM PDT 24
Peak memory 206316 kb
Host smart-7be9084a-8463-44af-b1aa-6937c17a7aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21447
59106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2144759106
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1439709192
Short name T1604
Test name
Test status
Simulation time 182197330 ps
CPU time 0.84 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:53 PM PDT 24
Peak memory 206296 kb
Host smart-41ddfc63-954a-4d8e-a9d2-59c8a8c54d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14397
09192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1439709192
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.2126145194
Short name T1747
Test name
Test status
Simulation time 325956546 ps
CPU time 1.05 seconds
Started Jul 11 05:57:36 PM PDT 24
Finished Jul 11 05:57:42 PM PDT 24
Peak memory 206400 kb
Host smart-148b852f-af0e-4025-9f44-1d518f385a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21261
45194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.2126145194
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3666499254
Short name T1030
Test name
Test status
Simulation time 4825185118 ps
CPU time 33.48 seconds
Started Jul 11 05:57:44 PM PDT 24
Finished Jul 11 05:58:21 PM PDT 24
Peak memory 206736 kb
Host smart-26cff080-aa50-4961-92ab-04e29a8e39f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36664
99254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3666499254
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.91205697
Short name T1455
Test name
Test status
Simulation time 66597258 ps
CPU time 0.69 seconds
Started Jul 11 05:57:49 PM PDT 24
Finished Jul 11 05:57:53 PM PDT 24
Peak memory 206408 kb
Host smart-967dc765-d2ea-464f-acd9-5c7dd1101b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=91205697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.91205697
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.434161568
Short name T2653
Test name
Test status
Simulation time 3764845776 ps
CPU time 5.29 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 206624 kb
Host smart-e9061001-7dc6-4303-bc7b-200272935cda
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=434161568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.434161568
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2374922708
Short name T1437
Test name
Test status
Simulation time 13447767004 ps
CPU time 13.75 seconds
Started Jul 11 05:57:40 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 206576 kb
Host smart-b2d4fc86-df93-4ee2-895c-dc355ef9ac4b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2374922708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2374922708
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.4152547901
Short name T2516
Test name
Test status
Simulation time 23354725369 ps
CPU time 23.5 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:58:15 PM PDT 24
Peak memory 206380 kb
Host smart-87632812-7a11-4760-8b3a-3073b38f5ee4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4152547901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.4152547901
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3963714178
Short name T999
Test name
Test status
Simulation time 176701622 ps
CPU time 0.78 seconds
Started Jul 11 05:57:39 PM PDT 24
Finished Jul 11 05:57:44 PM PDT 24
Peak memory 206384 kb
Host smart-45258936-2693-4412-8de4-e383817366cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39637
14178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3963714178
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.188177968
Short name T66
Test name
Test status
Simulation time 181784908 ps
CPU time 0.8 seconds
Started Jul 11 05:57:43 PM PDT 24
Finished Jul 11 05:57:47 PM PDT 24
Peak memory 206384 kb
Host smart-4380fd4a-5ad5-4466-a772-c29146467c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18817
7968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.188177968
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2469617357
Short name T1678
Test name
Test status
Simulation time 164888500 ps
CPU time 0.81 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206400 kb
Host smart-6421812e-432a-4669-9a12-2ff88c35725f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24696
17357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2469617357
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3796625087
Short name T1445
Test name
Test status
Simulation time 767938626 ps
CPU time 1.79 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:54 PM PDT 24
Peak memory 206164 kb
Host smart-f7d8f13e-6f87-4ff6-86da-a8e3696ca4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37966
25087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3796625087
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2478485902
Short name T2323
Test name
Test status
Simulation time 17143578100 ps
CPU time 32.87 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:58:22 PM PDT 24
Peak memory 206596 kb
Host smart-6e2f4aec-2c6a-473e-990b-17bce901d59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24784
85902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2478485902
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.121033410
Short name T1312
Test name
Test status
Simulation time 398831499 ps
CPU time 1.19 seconds
Started Jul 11 05:57:52 PM PDT 24
Finished Jul 11 05:57:59 PM PDT 24
Peak memory 206316 kb
Host smart-eb62cab2-80c3-4515-adce-4064325e29ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12103
3410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.121033410
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3493407055
Short name T1025
Test name
Test status
Simulation time 196098186 ps
CPU time 0.76 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 206312 kb
Host smart-6d87b2ff-0bc1-4d7d-a20b-59e99eebe4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34934
07055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3493407055
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.81446132
Short name T2269
Test name
Test status
Simulation time 46069975 ps
CPU time 0.63 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:28 PM PDT 24
Peak memory 206296 kb
Host smart-292c6f0e-cce9-4698-8a39-c235f6d978d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81446
132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.81446132
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1202495428
Short name T2466
Test name
Test status
Simulation time 758990699 ps
CPU time 1.9 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206512 kb
Host smart-d2d8b540-3d0a-4143-abfa-9b2aab83f84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12024
95428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1202495428
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.4218172031
Short name T1542
Test name
Test status
Simulation time 174952686 ps
CPU time 1.85 seconds
Started Jul 11 05:57:43 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206576 kb
Host smart-71ffd5e7-1403-47e7-b000-87e251403a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42181
72031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4218172031
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.939297679
Short name T1647
Test name
Test status
Simulation time 205426742 ps
CPU time 0.85 seconds
Started Jul 11 05:57:50 PM PDT 24
Finished Jul 11 05:57:55 PM PDT 24
Peak memory 206344 kb
Host smart-d58fc134-4070-4b72-9526-7758f86512f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93929
7679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.939297679
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1086633222
Short name T1627
Test name
Test status
Simulation time 161355575 ps
CPU time 0.79 seconds
Started Jul 11 05:57:42 PM PDT 24
Finished Jul 11 05:57:46 PM PDT 24
Peak memory 206328 kb
Host smart-675512ca-9103-4553-942c-f703b1a93b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10866
33222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1086633222
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.388198742
Short name T2068
Test name
Test status
Simulation time 206990538 ps
CPU time 0.93 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206292 kb
Host smart-af9327c4-a246-4ba6-96b9-30d53a56b38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38819
8742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.388198742
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2619823665
Short name T623
Test name
Test status
Simulation time 7848405538 ps
CPU time 221.19 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 06:01:33 PM PDT 24
Peak memory 206540 kb
Host smart-47df691e-03ed-41ee-8475-b542f381b78e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2619823665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2619823665
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.578185221
Short name T1558
Test name
Test status
Simulation time 3866921947 ps
CPU time 31.31 seconds
Started Jul 11 05:57:46 PM PDT 24
Finished Jul 11 05:58:21 PM PDT 24
Peak memory 206664 kb
Host smart-e5fe6dfe-3efc-4ddd-8ab5-66c09ef8e00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57818
5221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.578185221
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2030183835
Short name T1595
Test name
Test status
Simulation time 177536492 ps
CPU time 0.8 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:29 PM PDT 24
Peak memory 206104 kb
Host smart-6848450e-31c2-4a16-809a-8ab346a902a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20301
83835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2030183835
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.129427452
Short name T2278
Test name
Test status
Simulation time 23301933665 ps
CPU time 22.42 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:51 PM PDT 24
Peak memory 206368 kb
Host smart-1b5c874c-bb99-4510-a95d-640e8292ffb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12942
7452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.129427452
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.4253637927
Short name T1175
Test name
Test status
Simulation time 3300567212 ps
CPU time 4.25 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:58:03 PM PDT 24
Peak memory 206364 kb
Host smart-a2580d01-fe4d-4d05-9f5f-fbfc5fdcacd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42536
37927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.4253637927
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.715095530
Short name T2455
Test name
Test status
Simulation time 12655827547 ps
CPU time 352.22 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 06:03:51 PM PDT 24
Peak memory 206640 kb
Host smart-b8873a79-b3b3-49c4-b28d-4d45ac0bd086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71509
5530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.715095530
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1974301887
Short name T1632
Test name
Test status
Simulation time 5933126282 ps
CPU time 43.21 seconds
Started Jul 11 05:57:52 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206556 kb
Host smart-1ff5e3a3-c1af-4559-8b3c-77724863f99e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1974301887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1974301887
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1180364841
Short name T576
Test name
Test status
Simulation time 283482982 ps
CPU time 0.9 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:28 PM PDT 24
Peak memory 206304 kb
Host smart-c6be6701-9d04-400e-9ea4-86c614f29a85
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1180364841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1180364841
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.480593401
Short name T2723
Test name
Test status
Simulation time 231753385 ps
CPU time 0.89 seconds
Started Jul 11 05:57:45 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 206332 kb
Host smart-7a7aee8a-969f-4fd0-b7ed-5c001dede1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48059
3401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.480593401
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2788995506
Short name T1210
Test name
Test status
Simulation time 4937780665 ps
CPU time 44.64 seconds
Started Jul 11 05:57:50 PM PDT 24
Finished Jul 11 05:58:39 PM PDT 24
Peak memory 206668 kb
Host smart-1f162c77-4565-4fa8-a5d4-e272f542030f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27889
95506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2788995506
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3140407907
Short name T342
Test name
Test status
Simulation time 5182604021 ps
CPU time 49.98 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:58:47 PM PDT 24
Peak memory 206584 kb
Host smart-5c3ded4b-66e1-45be-95d7-d44dcac63f20
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3140407907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3140407907
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1727114154
Short name T1722
Test name
Test status
Simulation time 147302616 ps
CPU time 0.81 seconds
Started Jul 11 05:57:44 PM PDT 24
Finished Jul 11 05:57:48 PM PDT 24
Peak memory 206384 kb
Host smart-567ffe0c-5329-4a46-bddf-2ec8e279dbfc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1727114154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1727114154
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2042303317
Short name T256
Test name
Test status
Simulation time 179427702 ps
CPU time 0.78 seconds
Started Jul 11 05:58:16 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206304 kb
Host smart-b9e2abc5-9aec-41b4-8540-b4a7e5ace6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
03317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2042303317
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1512494956
Short name T2300
Test name
Test status
Simulation time 191289462 ps
CPU time 0.84 seconds
Started Jul 11 05:58:16 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206308 kb
Host smart-e19079ff-3987-4ea9-8eaa-a2543f6f4346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
94956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1512494956
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2643935966
Short name T2521
Test name
Test status
Simulation time 170790763 ps
CPU time 0.82 seconds
Started Jul 11 05:58:16 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206296 kb
Host smart-bf895633-ff63-431f-82aa-4c1cb73d1289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26439
35966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2643935966
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.684923733
Short name T21
Test name
Test status
Simulation time 158983968 ps
CPU time 0.8 seconds
Started Jul 11 05:57:44 PM PDT 24
Finished Jul 11 05:57:48 PM PDT 24
Peak memory 206384 kb
Host smart-4c5561fb-d9f8-4472-ab39-32f096254be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68492
3733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.684923733
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1483291953
Short name T2562
Test name
Test status
Simulation time 204529789 ps
CPU time 0.83 seconds
Started Jul 11 05:57:43 PM PDT 24
Finished Jul 11 05:57:47 PM PDT 24
Peak memory 206392 kb
Host smart-a5f40c17-bedb-4072-b5bb-6ac7c75640a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14832
91953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1483291953
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.993297419
Short name T17
Test name
Test status
Simulation time 206629067 ps
CPU time 0.91 seconds
Started Jul 11 05:58:16 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206312 kb
Host smart-3500cec4-af3d-45d3-a8dd-51f48a529250
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=993297419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.993297419
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1662431986
Short name T2485
Test name
Test status
Simulation time 143600823 ps
CPU time 0.81 seconds
Started Jul 11 05:57:50 PM PDT 24
Finished Jul 11 05:57:56 PM PDT 24
Peak memory 206376 kb
Host smart-68c88bec-3829-48cc-94e4-97be1ffd4e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16624
31986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1662431986
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.4121974288
Short name T39
Test name
Test status
Simulation time 63730538 ps
CPU time 0.66 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:14 PM PDT 24
Peak memory 206380 kb
Host smart-744ddfab-8b6d-4c11-8148-039b40bb1561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41219
74288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.4121974288
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1009382059
Short name T259
Test name
Test status
Simulation time 14351525344 ps
CPU time 31.32 seconds
Started Jul 11 05:58:14 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 206644 kb
Host smart-2aae384d-544d-4341-8c28-9213abcce61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
82059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1009382059
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2698641674
Short name T54
Test name
Test status
Simulation time 219261444 ps
CPU time 0.9 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206380 kb
Host smart-8e6b4184-e2df-48a9-a374-8cc5c9e0a857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26986
41674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2698641674
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.4101159755
Short name T1646
Test name
Test status
Simulation time 228324153 ps
CPU time 0.85 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:57:59 PM PDT 24
Peak memory 206376 kb
Host smart-42d6d067-dfea-415a-be2a-1fdb56c8be8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41011
59755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.4101159755
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3419571468
Short name T373
Test name
Test status
Simulation time 158012668 ps
CPU time 0.74 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:28 PM PDT 24
Peak memory 206304 kb
Host smart-a37e526c-2d2a-4fa2-9598-71a7afb91c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34195
71468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3419571468
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3313475308
Short name T1551
Test name
Test status
Simulation time 173928571 ps
CPU time 0.83 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:06 PM PDT 24
Peak memory 206336 kb
Host smart-2aebdecb-767f-4b0a-b20f-c552c7fe1b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33134
75308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3313475308
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2425546322
Short name T880
Test name
Test status
Simulation time 162147498 ps
CPU time 0.8 seconds
Started Jul 11 05:58:19 PM PDT 24
Finished Jul 11 05:58:30 PM PDT 24
Peak memory 206300 kb
Host smart-2a75272c-5cf8-4919-a4e1-804dd7369883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24255
46322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2425546322
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2932067462
Short name T1637
Test name
Test status
Simulation time 151594910 ps
CPU time 0.73 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:29 PM PDT 24
Peak memory 206300 kb
Host smart-da6e8b9a-e43e-48c8-a036-a42d7e0a9de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29320
67462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2932067462
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2689825653
Short name T1229
Test name
Test status
Simulation time 146866900 ps
CPU time 0.77 seconds
Started Jul 11 05:57:51 PM PDT 24
Finished Jul 11 05:57:56 PM PDT 24
Peak memory 206384 kb
Host smart-41012deb-0f2a-4dcf-9cd4-889b0a2e0c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26898
25653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2689825653
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1065515512
Short name T2235
Test name
Test status
Simulation time 228257090 ps
CPU time 0.91 seconds
Started Jul 11 05:57:59 PM PDT 24
Finished Jul 11 05:58:08 PM PDT 24
Peak memory 206384 kb
Host smart-2628573c-15ae-4fb4-90df-554d99d1a658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10655
15512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1065515512
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.261528522
Short name T1270
Test name
Test status
Simulation time 4995307728 ps
CPU time 137.51 seconds
Started Jul 11 05:57:52 PM PDT 24
Finished Jul 11 06:00:15 PM PDT 24
Peak memory 206576 kb
Host smart-63b8ecc3-ea99-4a01-93b3-23a83e5714d8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=261528522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.261528522
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2621834559
Short name T946
Test name
Test status
Simulation time 167733916 ps
CPU time 0.76 seconds
Started Jul 11 05:57:50 PM PDT 24
Finished Jul 11 05:57:55 PM PDT 24
Peak memory 206424 kb
Host smart-8e8bc379-d146-4189-8b9c-337438f4dd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26218
34559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2621834559
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3434355081
Short name T1773
Test name
Test status
Simulation time 163092056 ps
CPU time 0.77 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:52 PM PDT 24
Peak memory 206392 kb
Host smart-45148d1d-8b4c-431e-a1be-fd1bb0101897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34343
55081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3434355081
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.2200386134
Short name T2540
Test name
Test status
Simulation time 1060213579 ps
CPU time 2.49 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:58:01 PM PDT 24
Peak memory 206608 kb
Host smart-30fcf095-b6ba-414d-9001-11722d4b817b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
86134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2200386134
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2247390014
Short name T1898
Test name
Test status
Simulation time 6777565592 ps
CPU time 177.54 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206616 kb
Host smart-6b3833ac-528d-44cc-a659-2fef0b4ee3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22473
90014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2247390014
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3204917732
Short name T862
Test name
Test status
Simulation time 45901261 ps
CPU time 0.65 seconds
Started Jul 11 05:54:15 PM PDT 24
Finished Jul 11 05:54:17 PM PDT 24
Peak memory 206404 kb
Host smart-265e8aab-efec-4611-9218-81a57cbc01e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3204917732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3204917732
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1348175086
Short name T2133
Test name
Test status
Simulation time 3825519351 ps
CPU time 4.4 seconds
Started Jul 11 05:53:55 PM PDT 24
Finished Jul 11 05:54:00 PM PDT 24
Peak memory 206668 kb
Host smart-fcaa958d-f5e6-4fcf-a437-e54957a9a7b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1348175086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1348175086
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3308463811
Short name T817
Test name
Test status
Simulation time 13341115560 ps
CPU time 15.66 seconds
Started Jul 11 05:53:55 PM PDT 24
Finished Jul 11 05:54:12 PM PDT 24
Peak memory 206640 kb
Host smart-b9bdc590-23b7-483a-a5de-d8e624a432f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3308463811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3308463811
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.893750164
Short name T7
Test name
Test status
Simulation time 23373846043 ps
CPU time 22.39 seconds
Started Jul 11 05:53:55 PM PDT 24
Finished Jul 11 05:54:19 PM PDT 24
Peak memory 206436 kb
Host smart-c631b1bc-1f84-41ae-8135-a24c565265ad
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=893750164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.893750164
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2785989856
Short name T640
Test name
Test status
Simulation time 159916593 ps
CPU time 0.79 seconds
Started Jul 11 05:54:06 PM PDT 24
Finished Jul 11 05:54:08 PM PDT 24
Peak memory 206312 kb
Host smart-cc97bbbf-0a92-45ab-b25f-e9df81d7dba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859
89856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2785989856
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2284777989
Short name T63
Test name
Test status
Simulation time 158676028 ps
CPU time 0.78 seconds
Started Jul 11 05:53:55 PM PDT 24
Finished Jul 11 05:53:56 PM PDT 24
Peak memory 206400 kb
Host smart-bcaa36b9-161f-43d5-968c-752f666caf19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22847
77989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2284777989
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2335167775
Short name T93
Test name
Test status
Simulation time 149911837 ps
CPU time 0.79 seconds
Started Jul 11 05:53:59 PM PDT 24
Finished Jul 11 05:54:01 PM PDT 24
Peak memory 206320 kb
Host smart-a6fe3991-adc4-4a07-aaa3-c570bb6ba5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23351
67775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2335167775
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3890561139
Short name T2530
Test name
Test status
Simulation time 155519477 ps
CPU time 0.71 seconds
Started Jul 11 05:53:59 PM PDT 24
Finished Jul 11 05:54:00 PM PDT 24
Peak memory 206388 kb
Host smart-36db1764-1353-4bf9-85e1-e86b005e9a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38905
61139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3890561139
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.4545205
Short name T2015
Test name
Test status
Simulation time 174049328 ps
CPU time 0.84 seconds
Started Jul 11 05:54:02 PM PDT 24
Finished Jul 11 05:54:04 PM PDT 24
Peak memory 206312 kb
Host smart-7bbb8d7d-8e09-471b-8b58-55e30a4b5a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45452
05 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.4545205
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3695317623
Short name T116
Test name
Test status
Simulation time 819914588 ps
CPU time 1.82 seconds
Started Jul 11 05:54:01 PM PDT 24
Finished Jul 11 05:54:04 PM PDT 24
Peak memory 206648 kb
Host smart-4e9c6ed4-edca-4849-b46c-fb1ed3c73046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36953
17623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3695317623
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3507527561
Short name T99
Test name
Test status
Simulation time 9823223866 ps
CPU time 18.07 seconds
Started Jul 11 05:53:57 PM PDT 24
Finished Jul 11 05:54:15 PM PDT 24
Peak memory 206696 kb
Host smart-06b4e9c4-3455-4a6e-9e45-770e7ce9e9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35075
27561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3507527561
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.4286661530
Short name T2431
Test name
Test status
Simulation time 478040441 ps
CPU time 1.56 seconds
Started Jul 11 05:54:06 PM PDT 24
Finished Jul 11 05:54:08 PM PDT 24
Peak memory 206320 kb
Host smart-dcd3ab60-197d-4fb6-be3a-5a8293b7520a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42866
61530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.4286661530
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.807395097
Short name T2070
Test name
Test status
Simulation time 173337555 ps
CPU time 0.77 seconds
Started Jul 11 05:53:56 PM PDT 24
Finished Jul 11 05:53:58 PM PDT 24
Peak memory 206364 kb
Host smart-a3c4b2c5-3ce6-424e-a56c-2c91adf6994b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80739
5097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.807395097
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.4499465
Short name T1249
Test name
Test status
Simulation time 39538333 ps
CPU time 0.72 seconds
Started Jul 11 05:53:59 PM PDT 24
Finished Jul 11 05:54:01 PM PDT 24
Peak memory 206372 kb
Host smart-597b1d94-a50e-4e31-a2be-d5b8e2e7aa48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44994
65 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.4499465
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3796551797
Short name T983
Test name
Test status
Simulation time 800540943 ps
CPU time 1.82 seconds
Started Jul 11 05:53:55 PM PDT 24
Finished Jul 11 05:53:58 PM PDT 24
Peak memory 206556 kb
Host smart-508af7a7-d3ec-41a4-8e45-5850e7362389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
51797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3796551797
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1108879755
Short name T2277
Test name
Test status
Simulation time 185265083 ps
CPU time 1.92 seconds
Started Jul 11 05:53:56 PM PDT 24
Finished Jul 11 05:53:59 PM PDT 24
Peak memory 206620 kb
Host smart-c8016c65-77f9-408a-b019-6f7deec59ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11088
79755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1108879755
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3724197548
Short name T933
Test name
Test status
Simulation time 84193869425 ps
CPU time 130.28 seconds
Started Jul 11 05:53:57 PM PDT 24
Finished Jul 11 05:56:08 PM PDT 24
Peak memory 206676 kb
Host smart-a22c6f9a-fb8f-44f2-ac4f-1cee299dbaa4
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3724197548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3724197548
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1859083278
Short name T814
Test name
Test status
Simulation time 97158355305 ps
CPU time 144.63 seconds
Started Jul 11 05:53:56 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206628 kb
Host smart-aa11c8d3-c3c5-45f5-85da-8452ce20cd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859083278 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1859083278
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.3521899840
Short name T1699
Test name
Test status
Simulation time 111114727815 ps
CPU time 147.06 seconds
Started Jul 11 05:54:02 PM PDT 24
Finished Jul 11 05:56:30 PM PDT 24
Peak memory 206604 kb
Host smart-d8264439-bf02-4142-9e96-733985f585c6
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3521899840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.3521899840
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.4199126540
Short name T569
Test name
Test status
Simulation time 113293647039 ps
CPU time 147.27 seconds
Started Jul 11 05:54:02 PM PDT 24
Finished Jul 11 05:56:30 PM PDT 24
Peak memory 206692 kb
Host smart-69197c5c-ba15-4ec4-89d6-471620dc66de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199126540 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.4199126540
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.2585230012
Short name T2704
Test name
Test status
Simulation time 87134130306 ps
CPU time 119.04 seconds
Started Jul 11 05:54:04 PM PDT 24
Finished Jul 11 05:56:04 PM PDT 24
Peak memory 206704 kb
Host smart-88a2bc7f-40f4-4ee0-87cc-023e5b7670e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
30012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.2585230012
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1215080531
Short name T2663
Test name
Test status
Simulation time 185350408 ps
CPU time 0.84 seconds
Started Jul 11 05:54:01 PM PDT 24
Finished Jul 11 05:54:02 PM PDT 24
Peak memory 206384 kb
Host smart-08911e20-654b-47a7-acad-05e4159d78a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12150
80531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1215080531
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.792644824
Short name T1216
Test name
Test status
Simulation time 150855727 ps
CPU time 0.76 seconds
Started Jul 11 05:54:00 PM PDT 24
Finished Jul 11 05:54:02 PM PDT 24
Peak memory 206380 kb
Host smart-6135a846-5d69-40f0-99b9-c29f41c39996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79264
4824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.792644824
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3823926996
Short name T1761
Test name
Test status
Simulation time 224799423 ps
CPU time 0.9 seconds
Started Jul 11 05:54:01 PM PDT 24
Finished Jul 11 05:54:03 PM PDT 24
Peak memory 206380 kb
Host smart-0f50e17c-24b5-4302-b0b0-73e9101607f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38239
26996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3823926996
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.2180915180
Short name T769
Test name
Test status
Simulation time 5133775292 ps
CPU time 142.41 seconds
Started Jul 11 05:54:02 PM PDT 24
Finished Jul 11 05:56:25 PM PDT 24
Peak memory 206696 kb
Host smart-31dc2ef8-0390-434a-9703-044cff7a5d84
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2180915180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.2180915180
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3908893411
Short name T1758
Test name
Test status
Simulation time 7109931258 ps
CPU time 22.1 seconds
Started Jul 11 05:54:05 PM PDT 24
Finished Jul 11 05:54:28 PM PDT 24
Peak memory 206740 kb
Host smart-01c1d4bb-75b6-4962-ab81-275fc0ac86a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39088
93411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3908893411
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3339662981
Short name T502
Test name
Test status
Simulation time 229298640 ps
CPU time 0.88 seconds
Started Jul 11 05:54:11 PM PDT 24
Finished Jul 11 05:54:13 PM PDT 24
Peak memory 206388 kb
Host smart-22173306-d5fd-4b81-8daf-44fd7065a9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33396
62981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3339662981
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1737811589
Short name T1420
Test name
Test status
Simulation time 23325114342 ps
CPU time 24.07 seconds
Started Jul 11 05:54:04 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 206460 kb
Host smart-5a4f618c-ee3e-47ca-82a2-ec91721c9cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378
11589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1737811589
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2089862198
Short name T1018
Test name
Test status
Simulation time 3352898246 ps
CPU time 4.14 seconds
Started Jul 11 05:54:01 PM PDT 24
Finished Jul 11 05:54:07 PM PDT 24
Peak memory 206452 kb
Host smart-6e290747-a883-42ea-86c7-bd0c60267778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
62198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2089862198
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3854118297
Short name T613
Test name
Test status
Simulation time 11891865410 ps
CPU time 325.41 seconds
Started Jul 11 05:54:01 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206676 kb
Host smart-e86658b2-bd7d-4e6a-819b-72c4196d7c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
18297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3854118297
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1408219798
Short name T2616
Test name
Test status
Simulation time 5257817069 ps
CPU time 48.62 seconds
Started Jul 11 05:54:04 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 206652 kb
Host smart-bdf6f5e5-ef68-4b04-9fc6-728a8296011f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1408219798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1408219798
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.675740997
Short name T2060
Test name
Test status
Simulation time 276591126 ps
CPU time 0.99 seconds
Started Jul 11 05:54:03 PM PDT 24
Finished Jul 11 05:54:05 PM PDT 24
Peak memory 206364 kb
Host smart-67f4ca2d-17a4-42f9-8c3c-3fc1b46fd692
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=675740997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.675740997
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1095194590
Short name T943
Test name
Test status
Simulation time 203380100 ps
CPU time 0.88 seconds
Started Jul 11 05:54:07 PM PDT 24
Finished Jul 11 05:54:09 PM PDT 24
Peak memory 206408 kb
Host smart-8790c8df-0f59-4732-b352-d8de303265be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10951
94590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1095194590
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3143282710
Short name T687
Test name
Test status
Simulation time 6103727105 ps
CPU time 177.22 seconds
Started Jul 11 05:54:19 PM PDT 24
Finished Jul 11 05:57:18 PM PDT 24
Peak memory 206656 kb
Host smart-64f353b5-7c35-472c-b2cb-4e4999727c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
82710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3143282710
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3042762550
Short name T2680
Test name
Test status
Simulation time 4523251209 ps
CPU time 34.74 seconds
Started Jul 11 05:54:12 PM PDT 24
Finished Jul 11 05:54:49 PM PDT 24
Peak memory 206704 kb
Host smart-bb038c7d-e02b-4ce5-8040-43316b402165
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3042762550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3042762550
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.2184914952
Short name T1463
Test name
Test status
Simulation time 156575540 ps
CPU time 0.77 seconds
Started Jul 11 05:54:07 PM PDT 24
Finished Jul 11 05:54:09 PM PDT 24
Peak memory 206296 kb
Host smart-c95f3257-ce4b-4559-a01e-572b5aad4a65
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2184914952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.2184914952
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3010535626
Short name T1289
Test name
Test status
Simulation time 152860395 ps
CPU time 0.76 seconds
Started Jul 11 05:54:10 PM PDT 24
Finished Jul 11 05:54:11 PM PDT 24
Peak memory 206308 kb
Host smart-af6b8001-eaf5-4a33-abed-f1f05b35aaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105
35626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3010535626
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4091202958
Short name T145
Test name
Test status
Simulation time 209997244 ps
CPU time 0.89 seconds
Started Jul 11 05:54:18 PM PDT 24
Finished Jul 11 05:54:20 PM PDT 24
Peak memory 206384 kb
Host smart-c90c2bb2-ae43-442f-8b12-4a029797e2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912
02958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4091202958
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3325138693
Short name T1108
Test name
Test status
Simulation time 212330621 ps
CPU time 0.92 seconds
Started Jul 11 05:54:09 PM PDT 24
Finished Jul 11 05:54:11 PM PDT 24
Peak memory 206388 kb
Host smart-881cd996-a8f7-4f08-a2b7-b3423ee57d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33251
38693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3325138693
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1097923311
Short name T336
Test name
Test status
Simulation time 184852415 ps
CPU time 0.77 seconds
Started Jul 11 05:54:07 PM PDT 24
Finished Jul 11 05:54:09 PM PDT 24
Peak memory 206376 kb
Host smart-8cc18e0d-a7e3-42be-955e-127f9045dd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10979
23311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1097923311
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3652295429
Short name T1189
Test name
Test status
Simulation time 182238671 ps
CPU time 0.82 seconds
Started Jul 11 05:54:19 PM PDT 24
Finished Jul 11 05:54:21 PM PDT 24
Peak memory 206392 kb
Host smart-1203e169-7cb7-4916-a350-baac0be92e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36522
95429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3652295429
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1576943709
Short name T2264
Test name
Test status
Simulation time 183672050 ps
CPU time 0.82 seconds
Started Jul 11 05:54:12 PM PDT 24
Finished Jul 11 05:54:14 PM PDT 24
Peak memory 206404 kb
Host smart-ad5c28c7-f1a5-44ac-bb46-3e5f71c0eca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
43709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1576943709
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3392941741
Short name T2567
Test name
Test status
Simulation time 249680775 ps
CPU time 1.03 seconds
Started Jul 11 05:54:14 PM PDT 24
Finished Jul 11 05:54:17 PM PDT 24
Peak memory 206316 kb
Host smart-312f17cb-16eb-472c-aee9-46ef690fcefa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3392941741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3392941741
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.2068870136
Short name T2219
Test name
Test status
Simulation time 250928450 ps
CPU time 0.97 seconds
Started Jul 11 05:54:08 PM PDT 24
Finished Jul 11 05:54:09 PM PDT 24
Peak memory 206540 kb
Host smart-9c8cc50c-cb90-4dc5-8963-4a5b3527c0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20688
70136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.2068870136
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.280645979
Short name T2230
Test name
Test status
Simulation time 182212289 ps
CPU time 0.8 seconds
Started Jul 11 05:54:09 PM PDT 24
Finished Jul 11 05:54:10 PM PDT 24
Peak memory 206424 kb
Host smart-e4cf0ed7-9837-4c4e-b4d9-305f17a2919c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
5979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.280645979
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.459026775
Short name T1523
Test name
Test status
Simulation time 94903088 ps
CPU time 0.69 seconds
Started Jul 11 05:54:14 PM PDT 24
Finished Jul 11 05:54:17 PM PDT 24
Peak memory 206300 kb
Host smart-c1ce9297-90fc-4e61-b9e2-650ff2255e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45902
6775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.459026775
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3136622079
Short name T287
Test name
Test status
Simulation time 21267992349 ps
CPU time 46.55 seconds
Started Jul 11 05:54:05 PM PDT 24
Finished Jul 11 05:54:52 PM PDT 24
Peak memory 206740 kb
Host smart-0873d707-90cf-40b3-8a42-54c95a85c573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31366
22079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3136622079
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3268088809
Short name T2483
Test name
Test status
Simulation time 186518727 ps
CPU time 0.87 seconds
Started Jul 11 05:54:10 PM PDT 24
Finished Jul 11 05:54:12 PM PDT 24
Peak memory 206388 kb
Host smart-ec2f3134-523d-4a34-ac77-fb4eb080b9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32680
88809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3268088809
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3791569942
Short name T1744
Test name
Test status
Simulation time 213302545 ps
CPU time 0.85 seconds
Started Jul 11 05:54:10 PM PDT 24
Finished Jul 11 05:54:12 PM PDT 24
Peak memory 206380 kb
Host smart-908f787d-41c2-4ad4-929d-1103987fd974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37915
69942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3791569942
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.2493297651
Short name T542
Test name
Test status
Simulation time 9751186115 ps
CPU time 267.24 seconds
Started Jul 11 05:54:19 PM PDT 24
Finished Jul 11 05:58:48 PM PDT 24
Peak memory 206708 kb
Host smart-33755167-6005-4bfe-ab99-f209b4dc39cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2493297651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2493297651
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2162139716
Short name T2365
Test name
Test status
Simulation time 12736397918 ps
CPU time 81.86 seconds
Started Jul 11 05:54:08 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 206748 kb
Host smart-e9ca3140-9c10-4d6c-870d-8e59d691afc0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2162139716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2162139716
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2628798478
Short name T585
Test name
Test status
Simulation time 22794213418 ps
CPU time 516.6 seconds
Started Jul 11 05:54:15 PM PDT 24
Finished Jul 11 06:02:53 PM PDT 24
Peak memory 206648 kb
Host smart-99b6173d-d7ed-4b10-879d-1cfb08f05724
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2628798478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2628798478
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1797373232
Short name T461
Test name
Test status
Simulation time 281601226 ps
CPU time 0.96 seconds
Started Jul 11 05:54:07 PM PDT 24
Finished Jul 11 05:54:08 PM PDT 24
Peak memory 206380 kb
Host smart-0bdcc43e-8ece-4ac0-8134-5fbb3365d516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17973
73232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1797373232
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2635449361
Short name T1190
Test name
Test status
Simulation time 176505322 ps
CPU time 0.83 seconds
Started Jul 11 05:54:19 PM PDT 24
Finished Jul 11 05:54:21 PM PDT 24
Peak memory 206392 kb
Host smart-99531ff2-1854-4e36-99eb-e9f858a5371a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26354
49361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2635449361
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3941393504
Short name T559
Test name
Test status
Simulation time 186207425 ps
CPU time 0.79 seconds
Started Jul 11 05:54:17 PM PDT 24
Finished Jul 11 05:54:19 PM PDT 24
Peak memory 206304 kb
Host smart-a87871ae-d77b-4668-ab00-0c682da12a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39413
93504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3941393504
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2622238793
Short name T82
Test name
Test status
Simulation time 229617795 ps
CPU time 0.92 seconds
Started Jul 11 05:54:11 PM PDT 24
Finished Jul 11 05:54:13 PM PDT 24
Peak memory 206540 kb
Host smart-9014621e-9e8e-40e2-969f-49c22e25ba28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
38793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2622238793
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.746986737
Short name T204
Test name
Test status
Simulation time 217053470 ps
CPU time 1.04 seconds
Started Jul 11 05:54:22 PM PDT 24
Finished Jul 11 05:54:24 PM PDT 24
Peak memory 224152 kb
Host smart-075334f1-0b65-4bf9-be59-f2306c38db59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=746986737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.746986737
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1637367453
Short name T2606
Test name
Test status
Simulation time 474067475 ps
CPU time 1.26 seconds
Started Jul 11 05:54:14 PM PDT 24
Finished Jul 11 05:54:17 PM PDT 24
Peak memory 206384 kb
Host smart-472fc813-c3e5-4406-80fe-83ad82bf841b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16373
67453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1637367453
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2835248723
Short name T1113
Test name
Test status
Simulation time 187172111 ps
CPU time 0.83 seconds
Started Jul 11 05:54:22 PM PDT 24
Finished Jul 11 05:54:24 PM PDT 24
Peak memory 206316 kb
Host smart-7c11142d-90b7-41e2-9a36-4627133ae883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28352
48723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2835248723
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3124921605
Short name T517
Test name
Test status
Simulation time 152905220 ps
CPU time 0.75 seconds
Started Jul 11 05:54:15 PM PDT 24
Finished Jul 11 05:54:17 PM PDT 24
Peak memory 206388 kb
Host smart-e45c62a2-d39c-47a0-8672-8b99dcf66922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31249
21605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3124921605
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3198013001
Short name T2161
Test name
Test status
Simulation time 163193421 ps
CPU time 0.79 seconds
Started Jul 11 05:54:13 PM PDT 24
Finished Jul 11 05:54:15 PM PDT 24
Peak memory 206372 kb
Host smart-b609ced5-9d80-45de-9b91-bed653216df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31980
13001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3198013001
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3160515034
Short name T1318
Test name
Test status
Simulation time 202569465 ps
CPU time 0.87 seconds
Started Jul 11 05:54:14 PM PDT 24
Finished Jul 11 05:54:17 PM PDT 24
Peak memory 206396 kb
Host smart-5f1db5b3-c022-4743-b764-119806b16e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
15034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3160515034
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1911867094
Short name T1125
Test name
Test status
Simulation time 5375226937 ps
CPU time 38.53 seconds
Started Jul 11 05:54:13 PM PDT 24
Finished Jul 11 05:54:53 PM PDT 24
Peak memory 206512 kb
Host smart-d11d79a4-8929-4bee-9a8f-0d09feea0391
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1911867094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1911867094
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3069448155
Short name T1193
Test name
Test status
Simulation time 173913957 ps
CPU time 0.8 seconds
Started Jul 11 05:54:12 PM PDT 24
Finished Jul 11 05:54:15 PM PDT 24
Peak memory 206392 kb
Host smart-8e142f8c-05f1-4917-adad-9e2630d2eba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30694
48155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3069448155
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2274992813
Short name T2051
Test name
Test status
Simulation time 184827220 ps
CPU time 0.87 seconds
Started Jul 11 05:54:17 PM PDT 24
Finished Jul 11 05:54:20 PM PDT 24
Peak memory 206396 kb
Host smart-60afd8da-0465-45de-bda7-f9c906c2445b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
92813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2274992813
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2003173567
Short name T606
Test name
Test status
Simulation time 850679674 ps
CPU time 1.98 seconds
Started Jul 11 05:54:23 PM PDT 24
Finished Jul 11 05:54:26 PM PDT 24
Peak memory 206568 kb
Host smart-c04372f0-8e05-4756-a46a-929f5b2614c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
73567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2003173567
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2856745718
Short name T1961
Test name
Test status
Simulation time 7541877358 ps
CPU time 70.11 seconds
Started Jul 11 05:54:21 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 206556 kb
Host smart-1ab00361-9b61-45dc-b489-015a94bc4454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28567
45718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2856745718
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2297974690
Short name T2325
Test name
Test status
Simulation time 10424980239 ps
CPU time 68.43 seconds
Started Jul 11 05:54:16 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 206588 kb
Host smart-80a5ebf7-9a1d-4260-a7db-b520ca718c3f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2297974690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2297974690
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1860529727
Short name T1745
Test name
Test status
Simulation time 3712299864 ps
CPU time 5.01 seconds
Started Jul 11 05:57:48 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 206692 kb
Host smart-8ec794da-38cc-498e-8c36-0928603a5f00
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1860529727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1860529727
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2846875117
Short name T1945
Test name
Test status
Simulation time 13326403085 ps
CPU time 12.03 seconds
Started Jul 11 05:58:12 PM PDT 24
Finished Jul 11 05:58:34 PM PDT 24
Peak memory 206568 kb
Host smart-1ef8f3e7-f2ab-4816-a600-b3fff15d92e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2846875117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2846875117
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1154212332
Short name T238
Test name
Test status
Simulation time 23524711934 ps
CPU time 23.96 seconds
Started Jul 11 05:57:52 PM PDT 24
Finished Jul 11 05:58:21 PM PDT 24
Peak memory 206656 kb
Host smart-8cf78aac-f770-4f04-b81e-107effc9340c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1154212332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1154212332
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1212929723
Short name T2111
Test name
Test status
Simulation time 203458332 ps
CPU time 0.81 seconds
Started Jul 11 05:57:49 PM PDT 24
Finished Jul 11 05:57:54 PM PDT 24
Peak memory 206368 kb
Host smart-d3638078-f34c-4a1a-95b1-ae23c52668fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12129
29723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1212929723
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2048887308
Short name T2346
Test name
Test status
Simulation time 145768070 ps
CPU time 0.78 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:28 PM PDT 24
Peak memory 206304 kb
Host smart-985105dd-fe03-48a0-978b-f63fa43b9796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20488
87308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2048887308
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2655611892
Short name T1138
Test name
Test status
Simulation time 566460472 ps
CPU time 1.44 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:14 PM PDT 24
Peak memory 206636 kb
Host smart-cae92997-ece1-4d84-96c2-abb4a72a9ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26556
11892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2655611892
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.946611772
Short name T1818
Test name
Test status
Simulation time 1346231645 ps
CPU time 2.86 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:30 PM PDT 24
Peak memory 206504 kb
Host smart-5d9600e0-bedf-44d1-b8be-16c3543f1593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94661
1772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.946611772
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.110938421
Short name T2518
Test name
Test status
Simulation time 18821506213 ps
CPU time 34.86 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206632 kb
Host smart-169412af-870b-4a7e-abea-4af32a764f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11093
8421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.110938421
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.4070373106
Short name T2120
Test name
Test status
Simulation time 370173429 ps
CPU time 1.23 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:30 PM PDT 24
Peak memory 206308 kb
Host smart-7fc0345c-b4a3-43f6-9a81-fb733c80d36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40703
73106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.4070373106
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.916735214
Short name T492
Test name
Test status
Simulation time 193810494 ps
CPU time 0.82 seconds
Started Jul 11 05:57:50 PM PDT 24
Finished Jul 11 05:57:56 PM PDT 24
Peak memory 206380 kb
Host smart-0412e48e-97cf-46c9-825d-a780d7e00c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91673
5214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.916735214
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.4206322023
Short name T2733
Test name
Test status
Simulation time 72659897 ps
CPU time 0.66 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:28 PM PDT 24
Peak memory 206288 kb
Host smart-a8b68c6d-e1ce-47b6-9d2f-9b98a0ee7bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42063
22023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.4206322023
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2541054172
Short name T2700
Test name
Test status
Simulation time 909903667 ps
CPU time 2.07 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:07 PM PDT 24
Peak memory 206528 kb
Host smart-53e6119f-a5e1-483e-949e-0d57803fb625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
54172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2541054172
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2682649107
Short name T901
Test name
Test status
Simulation time 160676506 ps
CPU time 1.4 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:06 PM PDT 24
Peak memory 206516 kb
Host smart-053448ab-3657-4ed0-96b9-ba9c3dc16d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26826
49107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2682649107
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2548251149
Short name T763
Test name
Test status
Simulation time 187445038 ps
CPU time 0.81 seconds
Started Jul 11 05:58:03 PM PDT 24
Finished Jul 11 05:58:13 PM PDT 24
Peak memory 206388 kb
Host smart-300da159-3f60-4c55-aea9-666d90f1220f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
51149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2548251149
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4256991383
Short name T1197
Test name
Test status
Simulation time 145240638 ps
CPU time 0.76 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:04 PM PDT 24
Peak memory 206384 kb
Host smart-da590af1-715c-4833-82fa-9ee5b211e3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42569
91383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4256991383
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1113963492
Short name T2236
Test name
Test status
Simulation time 195850208 ps
CPU time 0.86 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:30 PM PDT 24
Peak memory 206120 kb
Host smart-6304b22a-72a5-46ca-a358-ac0f0462b790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11139
63492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1113963492
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.1876461656
Short name T1687
Test name
Test status
Simulation time 5302850939 ps
CPU time 144.49 seconds
Started Jul 11 05:58:13 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206596 kb
Host smart-7bb1049b-7cd1-4aa1-bdca-81be2f02ad2a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1876461656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.1876461656
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.278371466
Short name T2116
Test name
Test status
Simulation time 12028261376 ps
CPU time 108.41 seconds
Started Jul 11 05:58:14 PM PDT 24
Finished Jul 11 06:00:11 PM PDT 24
Peak memory 206224 kb
Host smart-8b657add-09d9-4c28-abe6-e2fcf8d47c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27837
1466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.278371466
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3083607234
Short name T1265
Test name
Test status
Simulation time 197074844 ps
CPU time 0.86 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:04 PM PDT 24
Peak memory 206368 kb
Host smart-2a85efc6-fb7b-43a8-9c5f-3301eb836954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30836
07234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3083607234
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.3040609152
Short name T1276
Test name
Test status
Simulation time 23286599026 ps
CPU time 28.89 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:34 PM PDT 24
Peak memory 206380 kb
Host smart-16b292a5-1fc3-4d7b-8f18-5dfc2a4ac54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30406
09152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3040609152
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.792235473
Short name T353
Test name
Test status
Simulation time 3284327086 ps
CPU time 3.81 seconds
Started Jul 11 05:58:13 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206368 kb
Host smart-a013524c-cbd6-4b00-b9d6-de8a99041e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79223
5473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.792235473
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.1384899902
Short name T781
Test name
Test status
Simulation time 8528936848 ps
CPU time 78.53 seconds
Started Jul 11 05:57:55 PM PDT 24
Finished Jul 11 05:59:19 PM PDT 24
Peak memory 206720 kb
Host smart-3f6c6e0f-b372-4ac0-b0eb-0b03067f0bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13848
99902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1384899902
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2328431753
Short name T2063
Test name
Test status
Simulation time 7641607682 ps
CPU time 55.35 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:59:11 PM PDT 24
Peak memory 206180 kb
Host smart-9a7f328c-b58f-4bf9-8645-75ad1baf6e04
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2328431753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2328431753
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.164529017
Short name T222
Test name
Test status
Simulation time 242145198 ps
CPU time 0.9 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206304 kb
Host smart-d0547621-f288-43b8-bd94-58fd3ef76aaa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=164529017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.164529017
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.4035403368
Short name T1644
Test name
Test status
Simulation time 241935133 ps
CPU time 0.93 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:58:16 PM PDT 24
Peak memory 206300 kb
Host smart-10b3f819-5693-4591-a2eb-92e26880140a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40354
03368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.4035403368
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3087822089
Short name T482
Test name
Test status
Simulation time 5061954156 ps
CPU time 36.11 seconds
Started Jul 11 05:57:52 PM PDT 24
Finished Jul 11 05:58:33 PM PDT 24
Peak memory 206684 kb
Host smart-1a6ea19d-deb4-43fb-bbb0-e51bfab6e217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30878
22089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3087822089
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.225666548
Short name T2399
Test name
Test status
Simulation time 7121866882 ps
CPU time 48.37 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 05:59:02 PM PDT 24
Peak memory 206700 kb
Host smart-10c77e09-351e-4673-abed-ba9762950047
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=225666548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.225666548
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1774350419
Short name T1815
Test name
Test status
Simulation time 148248750 ps
CPU time 0.77 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 05:58:15 PM PDT 24
Peak memory 206400 kb
Host smart-a8f018cd-e0a3-4b4b-b9da-13c19aa6bb8d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1774350419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1774350419
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2303946769
Short name T870
Test name
Test status
Simulation time 142979184 ps
CPU time 0.79 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:58:16 PM PDT 24
Peak memory 205880 kb
Host smart-855e673f-e179-4cb1-9d62-5a681a467070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
46769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2303946769
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2402618388
Short name T1528
Test name
Test status
Simulation time 185372543 ps
CPU time 0.8 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:14 PM PDT 24
Peak memory 206388 kb
Host smart-e8d3804a-36c9-4bf7-b2b7-7590d3dc9e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24026
18388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2402618388
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2105768459
Short name T1234
Test name
Test status
Simulation time 180957428 ps
CPU time 0.8 seconds
Started Jul 11 05:58:01 PM PDT 24
Finished Jul 11 05:58:10 PM PDT 24
Peak memory 206376 kb
Host smart-f441a5f6-5b05-41f5-a339-380f34fdc317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
68459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2105768459
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.408928072
Short name T589
Test name
Test status
Simulation time 202783995 ps
CPU time 0.87 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206388 kb
Host smart-18166a30-204f-49f6-a1f6-c9efc6bb471a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40892
8072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.408928072
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.4036706736
Short name T1738
Test name
Test status
Simulation time 152525998 ps
CPU time 0.83 seconds
Started Jul 11 05:57:57 PM PDT 24
Finished Jul 11 05:58:04 PM PDT 24
Peak memory 206396 kb
Host smart-4f4b9795-4bc5-4571-afe4-4f1bb3e9ef3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40367
06736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.4036706736
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2131337948
Short name T2270
Test name
Test status
Simulation time 201559928 ps
CPU time 0.88 seconds
Started Jul 11 05:58:03 PM PDT 24
Finished Jul 11 05:58:11 PM PDT 24
Peak memory 206344 kb
Host smart-4f50c04a-6251-45b3-9d1b-89ec699ce8c6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2131337948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2131337948
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1805976441
Short name T921
Test name
Test status
Simulation time 147033810 ps
CPU time 0.81 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 05:58:16 PM PDT 24
Peak memory 206400 kb
Host smart-abe79915-e96c-4a30-8b78-318738e21f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18059
76441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1805976441
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.159980088
Short name T37
Test name
Test status
Simulation time 64119020 ps
CPU time 0.67 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 05:58:15 PM PDT 24
Peak memory 206364 kb
Host smart-ba86a8f7-4b76-4b23-9a3e-9464e0e580ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15998
0088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.159980088
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.4156027155
Short name T777
Test name
Test status
Simulation time 19939863044 ps
CPU time 49.83 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 206660 kb
Host smart-5bd88e0d-05b3-4bae-8ed4-8de7e89990df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41560
27155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.4156027155
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2063450691
Short name T1916
Test name
Test status
Simulation time 168629211 ps
CPU time 0.88 seconds
Started Jul 11 05:57:52 PM PDT 24
Finished Jul 11 05:57:59 PM PDT 24
Peak memory 206388 kb
Host smart-e91cba9f-ece7-4690-a426-b5d28dd5e846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20634
50691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2063450691
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1557700317
Short name T771
Test name
Test status
Simulation time 205418412 ps
CPU time 0.85 seconds
Started Jul 11 05:58:12 PM PDT 24
Finished Jul 11 05:58:22 PM PDT 24
Peak memory 206364 kb
Host smart-4b6843d5-36c1-44e3-9bc6-94fdca6269ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15577
00317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1557700317
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.1704062273
Short name T2554
Test name
Test status
Simulation time 182376104 ps
CPU time 0.87 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:58:17 PM PDT 24
Peak memory 206356 kb
Host smart-cd090985-e8c6-4f79-b7b9-8140269b6d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17040
62273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.1704062273
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3702155904
Short name T792
Test name
Test status
Simulation time 221884641 ps
CPU time 0.85 seconds
Started Jul 11 05:57:53 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 206396 kb
Host smart-1dd6bf6d-cfea-40ab-8404-adc9bda9aaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37021
55904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3702155904
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3116247859
Short name T514
Test name
Test status
Simulation time 154396921 ps
CPU time 0.8 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:58:16 PM PDT 24
Peak memory 206352 kb
Host smart-de6e93a1-7707-4914-a5f5-af09c3a65496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31162
47859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3116247859
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2048947582
Short name T431
Test name
Test status
Simulation time 172124321 ps
CPU time 0.97 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:05 PM PDT 24
Peak memory 206384 kb
Host smart-4fb71c77-57fe-4503-8f6c-a46936ed093c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20489
47582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2048947582
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.586147070
Short name T2396
Test name
Test status
Simulation time 173278974 ps
CPU time 0.78 seconds
Started Jul 11 05:57:54 PM PDT 24
Finished Jul 11 05:58:01 PM PDT 24
Peak memory 206308 kb
Host smart-0bd766ab-4c59-464f-817c-64c0cfb87485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58614
7070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.586147070
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1874411822
Short name T1621
Test name
Test status
Simulation time 206475414 ps
CPU time 0.97 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:58:16 PM PDT 24
Peak memory 206292 kb
Host smart-46e4e4d5-058b-4ebf-91b3-7e29b96b3559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18744
11822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1874411822
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.3732302867
Short name T1973
Test name
Test status
Simulation time 4466739948 ps
CPU time 121.39 seconds
Started Jul 11 05:58:14 PM PDT 24
Finished Jul 11 06:00:24 PM PDT 24
Peak memory 206284 kb
Host smart-46430e37-9d05-449c-866c-7789c2d9728d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3732302867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3732302867
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3099114004
Short name T1058
Test name
Test status
Simulation time 151695208 ps
CPU time 0.76 seconds
Started Jul 11 05:57:56 PM PDT 24
Finished Jul 11 05:58:03 PM PDT 24
Peak memory 206344 kb
Host smart-afbf21b9-003e-4f8e-9eae-03776325158c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30991
14004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3099114004
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.671790791
Short name T1306
Test name
Test status
Simulation time 182344321 ps
CPU time 0.8 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206384 kb
Host smart-96d036fb-7e44-4bb2-b6fe-270ccfe15294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67179
0791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.671790791
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.428211225
Short name T2322
Test name
Test status
Simulation time 269528658 ps
CPU time 0.92 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:05 PM PDT 24
Peak memory 206388 kb
Host smart-5ab4c2d9-ac04-48b6-8731-128eb9e1202c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42821
1225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.428211225
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3296313086
Short name T1007
Test name
Test status
Simulation time 4356538376 ps
CPU time 29.28 seconds
Started Jul 11 05:58:11 PM PDT 24
Finished Jul 11 05:58:50 PM PDT 24
Peak memory 206620 kb
Host smart-646c74b1-ad8f-4d73-b41b-1bbf78897116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32963
13086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3296313086
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.3769366455
Short name T2226
Test name
Test status
Simulation time 43819357 ps
CPU time 0.69 seconds
Started Jul 11 05:58:10 PM PDT 24
Finished Jul 11 05:58:19 PM PDT 24
Peak memory 206344 kb
Host smart-6a683bf4-0424-4123-80f5-55029bb2f2f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3769366455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.3769366455
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.820425679
Short name T1958
Test name
Test status
Simulation time 3428251555 ps
CPU time 4.57 seconds
Started Jul 11 05:58:02 PM PDT 24
Finished Jul 11 05:58:14 PM PDT 24
Peak memory 206508 kb
Host smart-d86534fe-ca33-42f4-bd94-a253d831473e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=820425679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.820425679
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.937562845
Short name T767
Test name
Test status
Simulation time 13347329733 ps
CPU time 11.4 seconds
Started Jul 11 05:58:09 PM PDT 24
Finished Jul 11 05:58:30 PM PDT 24
Peak memory 206680 kb
Host smart-12cf765c-e3d3-4f86-994f-9cce3189dca1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=937562845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.937562845
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.43024055
Short name T1566
Test name
Test status
Simulation time 23380430863 ps
CPU time 25.68 seconds
Started Jul 11 05:58:12 PM PDT 24
Finished Jul 11 05:58:47 PM PDT 24
Peak memory 206432 kb
Host smart-58d06fee-4f53-41ed-abe7-458f6ccd3e8f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=43024055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.43024055
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3316821027
Short name T884
Test name
Test status
Simulation time 158274406 ps
CPU time 0.81 seconds
Started Jul 11 05:57:52 PM PDT 24
Finished Jul 11 05:57:59 PM PDT 24
Peak memory 206304 kb
Host smart-97bc797e-d183-4012-9ac0-ad3c6fcbba58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33168
21027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3316821027
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.669048294
Short name T2093
Test name
Test status
Simulation time 181312242 ps
CPU time 0.82 seconds
Started Jul 11 05:58:00 PM PDT 24
Finished Jul 11 05:58:08 PM PDT 24
Peak memory 206292 kb
Host smart-a5ee0f06-5f77-4763-a24e-01a269827ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66904
8294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.669048294
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2311374414
Short name T720
Test name
Test status
Simulation time 413827033 ps
CPU time 1.24 seconds
Started Jul 11 05:57:54 PM PDT 24
Finished Jul 11 05:58:01 PM PDT 24
Peak memory 206384 kb
Host smart-9715588c-51ec-4ca9-a70b-722a8b628da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
74414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2311374414
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.698708340
Short name T1411
Test name
Test status
Simulation time 1322208749 ps
CPU time 3.09 seconds
Started Jul 11 05:58:00 PM PDT 24
Finished Jul 11 05:58:10 PM PDT 24
Peak memory 206624 kb
Host smart-31b0c564-61dc-4d4e-b056-fdcb84955f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69870
8340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.698708340
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.1764913820
Short name T1728
Test name
Test status
Simulation time 11996727329 ps
CPU time 24.64 seconds
Started Jul 11 05:58:09 PM PDT 24
Finished Jul 11 05:58:43 PM PDT 24
Peak memory 206632 kb
Host smart-1a0d9b28-1504-4b2b-84d8-0c0c28650ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17649
13820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1764913820
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.258523759
Short name T2180
Test name
Test status
Simulation time 406679848 ps
CPU time 1.26 seconds
Started Jul 11 05:57:56 PM PDT 24
Finished Jul 11 05:58:03 PM PDT 24
Peak memory 206380 kb
Host smart-8c375835-fbb7-49db-b264-426b21ec655e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
3759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.258523759
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2623533027
Short name T2033
Test name
Test status
Simulation time 140978518 ps
CPU time 0.77 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206388 kb
Host smart-e246712e-d60f-4288-860f-102904cea161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26235
33027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2623533027
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3639574384
Short name T1593
Test name
Test status
Simulation time 39539612 ps
CPU time 0.7 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:12 PM PDT 24
Peak memory 206384 kb
Host smart-b2497f06-8fca-4597-823c-2fdb22f6bbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36395
74384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3639574384
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1819775563
Short name T637
Test name
Test status
Simulation time 839322515 ps
CPU time 2.05 seconds
Started Jul 11 05:58:03 PM PDT 24
Finished Jul 11 05:58:13 PM PDT 24
Peak memory 206552 kb
Host smart-488de8b9-0681-4dfa-9e4c-eb3b0d42e130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18197
75563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1819775563
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2037225791
Short name T2134
Test name
Test status
Simulation time 328550669 ps
CPU time 1.69 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:15 PM PDT 24
Peak memory 206616 kb
Host smart-242abf24-1c05-4b2d-94ec-27a8c629be38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20372
25791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2037225791
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1877708103
Short name T843
Test name
Test status
Simulation time 211284082 ps
CPU time 0.92 seconds
Started Jul 11 05:58:02 PM PDT 24
Finished Jul 11 05:58:11 PM PDT 24
Peak memory 206384 kb
Host smart-308bc8a8-5d84-4a14-b4d0-97f1192863dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18777
08103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1877708103
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3020039865
Short name T2648
Test name
Test status
Simulation time 137506815 ps
CPU time 0.74 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:58:16 PM PDT 24
Peak memory 206348 kb
Host smart-c8dde4ef-f2e5-4656-8b43-ba240dc43cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30200
39865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3020039865
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2753952314
Short name T758
Test name
Test status
Simulation time 230841523 ps
CPU time 0.92 seconds
Started Jul 11 05:58:01 PM PDT 24
Finished Jul 11 05:58:11 PM PDT 24
Peak memory 206384 kb
Host smart-0780b23d-6e65-4f56-9583-c9d9b2a49054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27539
52314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2753952314
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.622099683
Short name T578
Test name
Test status
Simulation time 12346592840 ps
CPU time 40.28 seconds
Started Jul 11 05:58:03 PM PDT 24
Finished Jul 11 05:58:51 PM PDT 24
Peak memory 206608 kb
Host smart-2a0f9cd4-ad55-4f99-af1e-33a1789cb8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62209
9683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.622099683
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1212446239
Short name T1020
Test name
Test status
Simulation time 206601667 ps
CPU time 0.82 seconds
Started Jul 11 05:58:03 PM PDT 24
Finished Jul 11 05:58:12 PM PDT 24
Peak memory 206400 kb
Host smart-0023622f-e86a-4125-8b62-e5e431699c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
46239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1212446239
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.806932079
Short name T816
Test name
Test status
Simulation time 23336557321 ps
CPU time 26.93 seconds
Started Jul 11 05:58:09 PM PDT 24
Finished Jul 11 05:58:45 PM PDT 24
Peak memory 206412 kb
Host smart-1a3ef6eb-5e4a-411f-b35f-4cc65b315fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80693
2079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.806932079
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.672036230
Short name T573
Test name
Test status
Simulation time 3288827620 ps
CPU time 3.7 seconds
Started Jul 11 05:58:01 PM PDT 24
Finished Jul 11 05:58:14 PM PDT 24
Peak memory 206452 kb
Host smart-23e85517-e9fe-416a-a04f-c75c51b33d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67203
6230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.672036230
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.865581030
Short name T2543
Test name
Test status
Simulation time 8592874941 ps
CPU time 235.56 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206812 kb
Host smart-88072df2-ad5d-4265-8a4f-7b8c5fc0c4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86558
1030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.865581030
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.264659403
Short name T730
Test name
Test status
Simulation time 5428526963 ps
CPU time 49.26 seconds
Started Jul 11 05:58:03 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206652 kb
Host smart-1bce225b-61d8-4dee-9b52-45aed80f5e87
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=264659403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.264659403
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3930726010
Short name T837
Test name
Test status
Simulation time 248366731 ps
CPU time 0.94 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:13 PM PDT 24
Peak memory 206368 kb
Host smart-14bd1d1f-26f8-4594-815b-acecd5a4e4b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3930726010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3930726010
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.618476983
Short name T1083
Test name
Test status
Simulation time 212793786 ps
CPU time 0.87 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 05:58:16 PM PDT 24
Peak memory 206352 kb
Host smart-2c832e8b-40f4-4125-b39a-aa6aeae75563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61847
6983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.618476983
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2882808061
Short name T1890
Test name
Test status
Simulation time 4949486683 ps
CPU time 134.75 seconds
Started Jul 11 05:58:01 PM PDT 24
Finished Jul 11 06:00:23 PM PDT 24
Peak memory 206656 kb
Host smart-70e7d687-e38a-4d85-8768-f6111eb10393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28828
08061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2882808061
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1376260373
Short name T722
Test name
Test status
Simulation time 3511211365 ps
CPU time 97.86 seconds
Started Jul 11 05:58:09 PM PDT 24
Finished Jul 11 05:59:56 PM PDT 24
Peak memory 206664 kb
Host smart-65f2e897-a79b-4965-86c9-47c1fff664e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1376260373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1376260373
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1875093779
Short name T1938
Test name
Test status
Simulation time 186337978 ps
CPU time 0.8 seconds
Started Jul 11 05:58:00 PM PDT 24
Finished Jul 11 05:58:08 PM PDT 24
Peak memory 206384 kb
Host smart-4b337388-1474-43d3-8875-1bd4f108ea0c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1875093779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1875093779
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.634192433
Short name T2210
Test name
Test status
Simulation time 153374779 ps
CPU time 0.84 seconds
Started Jul 11 05:57:57 PM PDT 24
Finished Jul 11 05:58:04 PM PDT 24
Peak memory 206404 kb
Host smart-90099874-e9e8-47a4-840d-4f2296672290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63419
2433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.634192433
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.4159714311
Short name T1781
Test name
Test status
Simulation time 182548738 ps
CPU time 0.87 seconds
Started Jul 11 05:58:12 PM PDT 24
Finished Jul 11 05:58:22 PM PDT 24
Peak memory 206364 kb
Host smart-bf332431-fd63-4f1b-85aa-ea7ac2f0a0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
14311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.4159714311
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.157742961
Short name T1251
Test name
Test status
Simulation time 195934162 ps
CPU time 0.82 seconds
Started Jul 11 05:57:58 PM PDT 24
Finished Jul 11 05:58:04 PM PDT 24
Peak memory 206396 kb
Host smart-1d416f17-f07c-4f40-b9ec-6ba84e77860f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
2961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.157742961
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1477198275
Short name T572
Test name
Test status
Simulation time 188879633 ps
CPU time 0.85 seconds
Started Jul 11 05:58:03 PM PDT 24
Finished Jul 11 05:58:13 PM PDT 24
Peak memory 206404 kb
Host smart-589f1800-3cd5-4d4d-94e1-ea09e51122e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771
98275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1477198275
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.562380543
Short name T1010
Test name
Test status
Simulation time 153647988 ps
CPU time 0.78 seconds
Started Jul 11 05:58:01 PM PDT 24
Finished Jul 11 05:58:10 PM PDT 24
Peak memory 206392 kb
Host smart-9bded20f-88f5-4164-ac38-2e59bfa26d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56238
0543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.562380543
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3688554118
Short name T2480
Test name
Test status
Simulation time 271987919 ps
CPU time 0.96 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:14 PM PDT 24
Peak memory 206372 kb
Host smart-9bbe4ad6-221b-499f-9ee5-3d9eaafc5ebf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3688554118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3688554118
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.4069162123
Short name T642
Test name
Test status
Simulation time 140993136 ps
CPU time 0.76 seconds
Started Jul 11 05:58:00 PM PDT 24
Finished Jul 11 05:58:08 PM PDT 24
Peak memory 206280 kb
Host smart-affaf6a5-927a-4d8f-a2aa-d486a98adf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40691
62123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.4069162123
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3690728909
Short name T1102
Test name
Test status
Simulation time 47576681 ps
CPU time 0.65 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 05:58:14 PM PDT 24
Peak memory 206376 kb
Host smart-4997ce2d-01bf-4aa6-9188-d784584abdf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36907
28909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3690728909
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1573455249
Short name T2726
Test name
Test status
Simulation time 8091929120 ps
CPU time 19.73 seconds
Started Jul 11 05:58:00 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206696 kb
Host smart-39b244ca-3366-4b42-85a4-3741fafca2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15734
55249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1573455249
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2203913861
Short name T2011
Test name
Test status
Simulation time 189558060 ps
CPU time 0.78 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:13 PM PDT 24
Peak memory 206312 kb
Host smart-ab6c27a4-f0bd-41a2-86b9-4ad4888ab9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22039
13861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2203913861
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1134266
Short name T2003
Test name
Test status
Simulation time 219923877 ps
CPU time 0.84 seconds
Started Jul 11 05:58:11 PM PDT 24
Finished Jul 11 05:58:22 PM PDT 24
Peak memory 206372 kb
Host smart-feb9958c-1184-483c-a03e-ba9fc0f58594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11342
66 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1134266
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.902826933
Short name T372
Test name
Test status
Simulation time 225385006 ps
CPU time 0.91 seconds
Started Jul 11 05:58:10 PM PDT 24
Finished Jul 11 05:58:21 PM PDT 24
Peak memory 206400 kb
Host smart-ee74b00d-c6d8-4d2a-8f40-a1bd5cf75a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90282
6933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.902826933
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2206905568
Short name T1104
Test name
Test status
Simulation time 157292973 ps
CPU time 0.87 seconds
Started Jul 11 05:58:14 PM PDT 24
Finished Jul 11 05:58:25 PM PDT 24
Peak memory 206348 kb
Host smart-fd4d63df-2766-41a1-8df5-a65d3d5dcaa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22069
05568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2206905568
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3255006766
Short name T1103
Test name
Test status
Simulation time 136903369 ps
CPU time 0.85 seconds
Started Jul 11 05:58:09 PM PDT 24
Finished Jul 11 05:58:19 PM PDT 24
Peak memory 206396 kb
Host smart-68e17c2e-0ec0-4d06-bcc9-aca6e8c4aece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550
06766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3255006766
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1828944858
Short name T338
Test name
Test status
Simulation time 154341337 ps
CPU time 0.78 seconds
Started Jul 11 05:58:10 PM PDT 24
Finished Jul 11 05:58:21 PM PDT 24
Peak memory 206380 kb
Host smart-611c06d3-a18a-45c7-9cc7-6dcd52d72e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289
44858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1828944858
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3862963224
Short name T2386
Test name
Test status
Simulation time 185233223 ps
CPU time 0.75 seconds
Started Jul 11 05:58:26 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206304 kb
Host smart-bca6f9d2-5f91-440c-bf49-2b9b24d729c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38629
63224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3862963224
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3553208558
Short name T1458
Test name
Test status
Simulation time 219716656 ps
CPU time 0.97 seconds
Started Jul 11 05:58:09 PM PDT 24
Finished Jul 11 05:58:19 PM PDT 24
Peak memory 206380 kb
Host smart-8e4acc80-1ca7-4915-a364-8c554e59a3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35532
08558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3553208558
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2421787729
Short name T1324
Test name
Test status
Simulation time 4788451436 ps
CPU time 44.98 seconds
Started Jul 11 05:58:04 PM PDT 24
Finished Jul 11 05:58:58 PM PDT 24
Peak memory 206620 kb
Host smart-aa36a313-a612-4971-89ea-1cd39a9f9475
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2421787729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2421787729
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1107942582
Short name T944
Test name
Test status
Simulation time 160162213 ps
CPU time 0.79 seconds
Started Jul 11 05:58:16 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206360 kb
Host smart-8923f094-e9ad-4973-8901-ea61932b3250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11079
42582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1107942582
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2549769135
Short name T107
Test name
Test status
Simulation time 242918842 ps
CPU time 0.88 seconds
Started Jul 11 05:58:08 PM PDT 24
Finished Jul 11 05:58:18 PM PDT 24
Peak memory 206328 kb
Host smart-45364d40-d29a-46c3-b5fd-d128b480dff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25497
69135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2549769135
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.4023422266
Short name T866
Test name
Test status
Simulation time 322625245 ps
CPU time 1.01 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206304 kb
Host smart-066dfe89-9333-4419-9c5c-9652ae2ebe94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40234
22266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.4023422266
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3206679946
Short name T1465
Test name
Test status
Simulation time 3954446548 ps
CPU time 36.7 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:59:04 PM PDT 24
Peak memory 206712 kb
Host smart-e926987f-edb8-41a0-b1c4-ee0bc46d841e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
79946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3206679946
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.3383333563
Short name T882
Test name
Test status
Simulation time 33665949 ps
CPU time 0.66 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:28 PM PDT 24
Peak memory 206432 kb
Host smart-6eb45399-71fd-4d8a-850a-c50a9b31e3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3383333563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.3383333563
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1659168787
Short name T2126
Test name
Test status
Simulation time 3707065984 ps
CPU time 4.7 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:58:20 PM PDT 24
Peak memory 206756 kb
Host smart-88ca9efd-cb7d-469e-82ea-71749e847cbb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1659168787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1659168787
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3621640242
Short name T2645
Test name
Test status
Simulation time 13441934886 ps
CPU time 13.04 seconds
Started Jul 11 05:58:07 PM PDT 24
Finished Jul 11 05:58:29 PM PDT 24
Peak memory 206636 kb
Host smart-669aff4d-16b5-4648-adec-c211b9eb4dbe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3621640242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3621640242
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.3415380720
Short name T1891
Test name
Test status
Simulation time 23379791235 ps
CPU time 22.51 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206456 kb
Host smart-6a6a2b4a-af77-46a4-a76f-0e0b22fdfa7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3415380720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.3415380720
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1231768302
Short name T2098
Test name
Test status
Simulation time 169098421 ps
CPU time 0.81 seconds
Started Jul 11 05:58:05 PM PDT 24
Finished Jul 11 05:58:15 PM PDT 24
Peak memory 206400 kb
Host smart-d5a3f084-cefc-4e20-9dbb-53e81ff9ebff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12317
68302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1231768302
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3888291653
Short name T2303
Test name
Test status
Simulation time 147376498 ps
CPU time 0.77 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:29 PM PDT 24
Peak memory 206388 kb
Host smart-f3739301-3e74-45d3-b9e2-23a8a57fb2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38882
91653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3888291653
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2051170329
Short name T1764
Test name
Test status
Simulation time 538400245 ps
CPU time 1.61 seconds
Started Jul 11 05:58:25 PM PDT 24
Finished Jul 11 05:58:39 PM PDT 24
Peak memory 206496 kb
Host smart-756f2f35-4153-41a8-ae05-a5e8b497327c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20511
70329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2051170329
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1488783212
Short name T1510
Test name
Test status
Simulation time 1395587280 ps
CPU time 2.89 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:31 PM PDT 24
Peak memory 206624 kb
Host smart-85cb1791-4d18-40fb-85a3-da6280988895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14887
83212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1488783212
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.4591746
Short name T1346
Test name
Test status
Simulation time 20271157933 ps
CPU time 35.45 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:59:10 PM PDT 24
Peak memory 206700 kb
Host smart-6853b1b9-d4fb-4f4d-926b-2c94bbe2af1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45917
46 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.4591746
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.469504768
Short name T2564
Test name
Test status
Simulation time 509201293 ps
CPU time 1.42 seconds
Started Jul 11 05:58:06 PM PDT 24
Finished Jul 11 05:58:17 PM PDT 24
Peak memory 206336 kb
Host smart-bd0ae1bb-44e8-4864-95ed-cc4f964ee2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46950
4768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.469504768
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.20964288
Short name T1021
Test name
Test status
Simulation time 145226823 ps
CPU time 0.75 seconds
Started Jul 11 05:58:10 PM PDT 24
Finished Jul 11 05:58:20 PM PDT 24
Peak memory 206304 kb
Host smart-310b760d-7222-4005-ac12-34579aedd592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20964
288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.20964288
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2358943064
Short name T1439
Test name
Test status
Simulation time 69972461 ps
CPU time 0.7 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:58:35 PM PDT 24
Peak memory 206380 kb
Host smart-dd295084-f52e-4116-bda6-b6809def518f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
43064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2358943064
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.641610603
Short name T1252
Test name
Test status
Simulation time 1088957014 ps
CPU time 2.61 seconds
Started Jul 11 05:58:10 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206636 kb
Host smart-53edae40-aa91-42cc-b72a-e98e3b50172d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64161
0603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.641610603
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1488765982
Short name T895
Test name
Test status
Simulation time 201562684 ps
CPU time 1.86 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206568 kb
Host smart-cb0fbeba-ff69-48c0-b9b6-281c8a20864e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14887
65982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1488765982
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.509353204
Short name T577
Test name
Test status
Simulation time 190783864 ps
CPU time 0.83 seconds
Started Jul 11 05:58:16 PM PDT 24
Finished Jul 11 05:58:26 PM PDT 24
Peak memory 206400 kb
Host smart-7dccd4b3-c660-42a4-86b8-bab6da5f20de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50935
3204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.509353204
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2426016397
Short name T2647
Test name
Test status
Simulation time 136494860 ps
CPU time 0.75 seconds
Started Jul 11 05:58:03 PM PDT 24
Finished Jul 11 05:58:13 PM PDT 24
Peak memory 206384 kb
Host smart-9a565109-0e5b-41de-a18c-1d984e0de531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24260
16397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2426016397
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.760987275
Short name T1931
Test name
Test status
Simulation time 277815782 ps
CPU time 0.96 seconds
Started Jul 11 05:58:34 PM PDT 24
Finished Jul 11 05:58:47 PM PDT 24
Peak memory 206296 kb
Host smart-f8648af5-dfb0-49c2-8374-7d87838879f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76098
7275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.760987275
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1741297634
Short name T1948
Test name
Test status
Simulation time 8920879632 ps
CPU time 27.07 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 206728 kb
Host smart-7bc04089-3da3-427a-9166-36e93a57397f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17412
97634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1741297634
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2235268966
Short name T510
Test name
Test status
Simulation time 197908544 ps
CPU time 0.82 seconds
Started Jul 11 05:58:13 PM PDT 24
Finished Jul 11 05:58:24 PM PDT 24
Peak memory 206376 kb
Host smart-890dc77b-f772-4c60-b4eb-fbba148d1bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22352
68966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2235268966
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3423560549
Short name T2676
Test name
Test status
Simulation time 23335603103 ps
CPU time 23.1 seconds
Started Jul 11 05:58:11 PM PDT 24
Finished Jul 11 05:58:44 PM PDT 24
Peak memory 206324 kb
Host smart-ce5e4020-0381-40a6-a8cb-a4f80da325ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
60549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3423560549
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.375874399
Short name T2217
Test name
Test status
Simulation time 3339426713 ps
CPU time 3.99 seconds
Started Jul 11 05:58:15 PM PDT 24
Finished Jul 11 05:58:29 PM PDT 24
Peak memory 206408 kb
Host smart-5ffacd27-4294-469e-a8d9-64a7cd9c9e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37587
4399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.375874399
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1262138014
Short name T1388
Test name
Test status
Simulation time 11503139779 ps
CPU time 108.79 seconds
Started Jul 11 05:58:12 PM PDT 24
Finished Jul 11 06:00:11 PM PDT 24
Peak memory 206708 kb
Host smart-6cec5175-79d9-432b-bb2f-77d4f4b24f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
38014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1262138014
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3445948492
Short name T367
Test name
Test status
Simulation time 4837574682 ps
CPU time 133.89 seconds
Started Jul 11 05:58:26 PM PDT 24
Finished Jul 11 06:00:52 PM PDT 24
Peak memory 206588 kb
Host smart-3d251b5c-6d61-4f4b-bdfe-9d2816103cb8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3445948492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3445948492
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1032121960
Short name T1425
Test name
Test status
Simulation time 248002653 ps
CPU time 0.88 seconds
Started Jul 11 05:58:13 PM PDT 24
Finished Jul 11 05:58:24 PM PDT 24
Peak memory 206380 kb
Host smart-14b3c21d-4247-49bf-b172-685d84cdfdb5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1032121960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1032121960
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3872062134
Short name T1934
Test name
Test status
Simulation time 206001517 ps
CPU time 0.89 seconds
Started Jul 11 05:58:21 PM PDT 24
Finished Jul 11 05:58:34 PM PDT 24
Peak memory 206404 kb
Host smart-a481d433-3d03-4fdb-9182-c029dd8f947a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38720
62134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3872062134
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.27458008
Short name T1577
Test name
Test status
Simulation time 4386152719 ps
CPU time 123.53 seconds
Started Jul 11 05:58:15 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 206656 kb
Host smart-50bedaf9-b296-4d4d-8410-3345a72529b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27458
008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.27458008
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1737661176
Short name T422
Test name
Test status
Simulation time 5221880541 ps
CPU time 144.36 seconds
Started Jul 11 05:58:22 PM PDT 24
Finished Jul 11 06:00:58 PM PDT 24
Peak memory 206632 kb
Host smart-c7fd7825-ce77-4129-b739-28b6dbe57ef1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1737661176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1737661176
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1156183401
Short name T2372
Test name
Test status
Simulation time 163169295 ps
CPU time 0.86 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:30 PM PDT 24
Peak memory 206356 kb
Host smart-476d8b35-7ab9-41ac-89ca-c2f9d43839d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1156183401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1156183401
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3728353705
Short name T527
Test name
Test status
Simulation time 154159116 ps
CPU time 0.75 seconds
Started Jul 11 05:58:19 PM PDT 24
Finished Jul 11 05:58:30 PM PDT 24
Peak memory 206328 kb
Host smart-702be2bf-bd08-4124-a29d-e9dd648070b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37283
53705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3728353705
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3251622960
Short name T964
Test name
Test status
Simulation time 214726368 ps
CPU time 0.83 seconds
Started Jul 11 05:58:15 PM PDT 24
Finished Jul 11 05:58:25 PM PDT 24
Peak memory 206332 kb
Host smart-8093ce72-1470-4772-9b49-d0f6a718ad75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32516
22960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3251622960
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3308766020
Short name T1088
Test name
Test status
Simulation time 141437309 ps
CPU time 0.78 seconds
Started Jul 11 05:58:28 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206328 kb
Host smart-1114bda7-7224-4771-a8bc-26407695a6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33087
66020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3308766020
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2570450529
Short name T1176
Test name
Test status
Simulation time 200845982 ps
CPU time 0.83 seconds
Started Jul 11 05:58:15 PM PDT 24
Finished Jul 11 05:58:25 PM PDT 24
Peak memory 206384 kb
Host smart-75bd6cc9-f134-4017-a25d-3df5f539d410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25704
50529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2570450529
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1141159844
Short name T1362
Test name
Test status
Simulation time 160119543 ps
CPU time 0.81 seconds
Started Jul 11 05:58:11 PM PDT 24
Finished Jul 11 05:58:21 PM PDT 24
Peak memory 206392 kb
Host smart-92a011f9-a06e-49d5-9f97-67ee52ac761d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11411
59844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1141159844
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.4068480107
Short name T2224
Test name
Test status
Simulation time 156324149 ps
CPU time 0.75 seconds
Started Jul 11 05:58:15 PM PDT 24
Finished Jul 11 05:58:25 PM PDT 24
Peak memory 206380 kb
Host smart-a3efc8ca-8a9c-45e4-84fc-8aa857515a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40684
80107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.4068480107
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1378305941
Short name T1335
Test name
Test status
Simulation time 229935733 ps
CPU time 0.92 seconds
Started Jul 11 05:58:15 PM PDT 24
Finished Jul 11 05:58:25 PM PDT 24
Peak memory 206376 kb
Host smart-7b932618-e1e7-4a13-a4ff-b9c58b51c5e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1378305941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1378305941
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.4137138760
Short name T1239
Test name
Test status
Simulation time 145532551 ps
CPU time 0.8 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:58:35 PM PDT 24
Peak memory 206388 kb
Host smart-795e0f32-81a9-47ba-95fc-3702471c6bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41371
38760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.4137138760
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.185673765
Short name T2208
Test name
Test status
Simulation time 30026153 ps
CPU time 0.62 seconds
Started Jul 11 05:58:12 PM PDT 24
Finished Jul 11 05:58:22 PM PDT 24
Peak memory 206300 kb
Host smart-0c2cb747-3f72-4ca5-810b-072f238156ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18567
3765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.185673765
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2505474165
Short name T2593
Test name
Test status
Simulation time 17890898238 ps
CPU time 39.8 seconds
Started Jul 11 05:58:13 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206660 kb
Host smart-cbe3ac6f-7fff-4ed2-b192-412febe0eeff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25054
74165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2505474165
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1010109748
Short name T786
Test name
Test status
Simulation time 184374288 ps
CPU time 0.81 seconds
Started Jul 11 05:58:26 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206332 kb
Host smart-67ff8c72-2401-4e45-a3a8-12d4f51e139f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10101
09748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1010109748
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3190745587
Short name T1529
Test name
Test status
Simulation time 190891231 ps
CPU time 0.84 seconds
Started Jul 11 05:58:21 PM PDT 24
Finished Jul 11 05:58:33 PM PDT 24
Peak memory 206400 kb
Host smart-1d919146-570d-4c21-b047-919114815219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31907
45587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3190745587
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2662821177
Short name T932
Test name
Test status
Simulation time 242677703 ps
CPU time 0.87 seconds
Started Jul 11 05:58:26 PM PDT 24
Finished Jul 11 05:58:39 PM PDT 24
Peak memory 206324 kb
Host smart-a0d5c862-6d9b-4c2f-a92b-7cf3cf635e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26628
21177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2662821177
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1321670556
Short name T826
Test name
Test status
Simulation time 156438686 ps
CPU time 0.8 seconds
Started Jul 11 05:58:21 PM PDT 24
Finished Jul 11 05:58:33 PM PDT 24
Peak memory 206324 kb
Host smart-3b37973e-faf2-4882-b040-a321d5e8dd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13216
70556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1321670556
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.235000873
Short name T1122
Test name
Test status
Simulation time 148296706 ps
CPU time 0.74 seconds
Started Jul 11 05:58:13 PM PDT 24
Finished Jul 11 05:58:23 PM PDT 24
Peak memory 206372 kb
Host smart-d7553175-0b99-4a21-ba3c-edeb0684e890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23500
0873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.235000873
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2142404008
Short name T1707
Test name
Test status
Simulation time 150286241 ps
CPU time 0.77 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 206380 kb
Host smart-30b384b8-2eba-4b8c-8e6e-a8d1b6de90e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21424
04008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2142404008
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3909912325
Short name T734
Test name
Test status
Simulation time 153769495 ps
CPU time 0.77 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:29 PM PDT 24
Peak memory 206324 kb
Host smart-1752833a-918e-4d61-8f82-d945dac8f71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39099
12325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3909912325
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1268498665
Short name T1383
Test name
Test status
Simulation time 200248122 ps
CPU time 0.88 seconds
Started Jul 11 05:58:16 PM PDT 24
Finished Jul 11 05:58:26 PM PDT 24
Peak memory 206384 kb
Host smart-9f34a09c-990c-486f-9794-631ab3cf67b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12684
98665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1268498665
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3577920910
Short name T778
Test name
Test status
Simulation time 4287083768 ps
CPU time 123.63 seconds
Started Jul 11 05:58:15 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 206524 kb
Host smart-45b2e2ae-0292-43f5-8438-71f58ada43ca
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3577920910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3577920910
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2593831977
Short name T1605
Test name
Test status
Simulation time 215442244 ps
CPU time 0.8 seconds
Started Jul 11 05:58:26 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206332 kb
Host smart-121a06d8-ee01-4807-8e46-0198ced7dbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25938
31977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2593831977
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.739648556
Short name T648
Test name
Test status
Simulation time 194191998 ps
CPU time 0.81 seconds
Started Jul 11 05:58:13 PM PDT 24
Finished Jul 11 05:58:24 PM PDT 24
Peak memory 206324 kb
Host smart-57c83c28-6302-4d28-a674-af986ac2a8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73964
8556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.739648556
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.917709865
Short name T1756
Test name
Test status
Simulation time 701356658 ps
CPU time 2.02 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206556 kb
Host smart-18dd4ee2-638d-43fc-a536-60a712bfe78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91770
9865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.917709865
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.137242899
Short name T2222
Test name
Test status
Simulation time 3870625109 ps
CPU time 106.92 seconds
Started Jul 11 05:58:22 PM PDT 24
Finished Jul 11 06:00:20 PM PDT 24
Peak memory 206660 kb
Host smart-39474f59-f705-4cd5-8473-1db55a3d312f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13724
2899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.137242899
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3613922090
Short name T197
Test name
Test status
Simulation time 52159299 ps
CPU time 0.69 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206404 kb
Host smart-7a8f6d58-797d-40e4-8664-cf5a03d61bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3613922090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3613922090
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.891474258
Short name T1038
Test name
Test status
Simulation time 4445254121 ps
CPU time 5.11 seconds
Started Jul 11 05:58:19 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206464 kb
Host smart-a6d811d8-1b96-4fec-bf3e-6579ba241ffe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=891474258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.891474258
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.1674666616
Short name T2137
Test name
Test status
Simulation time 13457080904 ps
CPU time 14.78 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 05:58:42 PM PDT 24
Peak memory 206700 kb
Host smart-50f08dcd-e535-47aa-a4ae-d9a69493ec86
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1674666616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.1674666616
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.272209854
Short name T2681
Test name
Test status
Simulation time 23404744692 ps
CPU time 25.67 seconds
Started Jul 11 05:58:37 PM PDT 24
Finished Jul 11 05:59:14 PM PDT 24
Peak memory 206652 kb
Host smart-044fe530-7f0a-477b-b38a-5afe978cd107
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=272209854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.272209854
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.705935190
Short name T655
Test name
Test status
Simulation time 183045509 ps
CPU time 0.82 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206396 kb
Host smart-d9d235df-9f2e-42fc-b8d9-9060af63eb43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70593
5190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.705935190
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3470238399
Short name T2131
Test name
Test status
Simulation time 147965289 ps
CPU time 0.72 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206388 kb
Host smart-db5ad6fc-1eb3-4024-a012-68d6512ada16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34702
38399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3470238399
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1901985902
Short name T2268
Test name
Test status
Simulation time 269011080 ps
CPU time 0.99 seconds
Started Jul 11 05:58:32 PM PDT 24
Finished Jul 11 05:58:44 PM PDT 24
Peak memory 206396 kb
Host smart-965920f8-0068-40c8-9609-ee7eae5809db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19019
85902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1901985902
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.692078812
Short name T2471
Test name
Test status
Simulation time 1458921299 ps
CPU time 3.4 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:39 PM PDT 24
Peak memory 206636 kb
Host smart-ad406aac-92a1-4288-923d-d8eb2cae1e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69207
8812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.692078812
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2486294167
Short name T1736
Test name
Test status
Simulation time 20555988091 ps
CPU time 39.83 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:59:14 PM PDT 24
Peak memory 206708 kb
Host smart-52f5f3b3-7185-4f92-bb6e-0b1e4e3bb850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24862
94167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2486294167
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.135516769
Short name T2407
Test name
Test status
Simulation time 416733845 ps
CPU time 1.27 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206380 kb
Host smart-5d680b45-0d87-483e-99b9-070c95c1ff14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551
6769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.135516769
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.636339873
Short name T2634
Test name
Test status
Simulation time 138930916 ps
CPU time 0.78 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:29 PM PDT 24
Peak memory 206388 kb
Host smart-33e96da6-2862-40d7-9acb-fa923dd08504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63633
9873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.636339873
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3543032509
Short name T229
Test name
Test status
Simulation time 30378210 ps
CPU time 0.68 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:58:32 PM PDT 24
Peak memory 206384 kb
Host smart-5da41338-0936-4930-92d9-1b28a647b1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
32509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3543032509
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.88583088
Short name T1435
Test name
Test status
Simulation time 780330036 ps
CPU time 1.78 seconds
Started Jul 11 05:58:35 PM PDT 24
Finished Jul 11 05:58:48 PM PDT 24
Peak memory 206608 kb
Host smart-7e3264c3-b6b6-41bc-8a8b-99b478d5cbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88583
088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.88583088
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1754197711
Short name T1848
Test name
Test status
Simulation time 183071862 ps
CPU time 1.69 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206576 kb
Host smart-d90bb381-50fa-402b-b576-07282c9e1d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17541
97711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1754197711
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.19294740
Short name T915
Test name
Test status
Simulation time 269042747 ps
CPU time 0.92 seconds
Started Jul 11 05:58:19 PM PDT 24
Finished Jul 11 05:58:32 PM PDT 24
Peak memory 206384 kb
Host smart-b2e17e7f-0228-4dfe-8aae-3424b0209030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19294
740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.19294740
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.278692301
Short name T409
Test name
Test status
Simulation time 190029341 ps
CPU time 0.8 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206316 kb
Host smart-62d72ba0-ae83-4939-98f0-165ce6e5191e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27869
2301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.278692301
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1210747112
Short name T905
Test name
Test status
Simulation time 237515223 ps
CPU time 0.91 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206324 kb
Host smart-df88452c-ad46-40a5-8f10-f09fbcd0197a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
47112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1210747112
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.287301125
Short name T30
Test name
Test status
Simulation time 159641351 ps
CPU time 0.82 seconds
Started Jul 11 05:58:30 PM PDT 24
Finished Jul 11 05:58:43 PM PDT 24
Peak memory 206380 kb
Host smart-8f49ed65-b70a-4c46-ada7-45b6e4e783eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730
1125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.287301125
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3122646709
Short name T2129
Test name
Test status
Simulation time 23314110835 ps
CPU time 30.19 seconds
Started Jul 11 05:58:18 PM PDT 24
Finished Jul 11 05:58:59 PM PDT 24
Peak memory 206444 kb
Host smart-38ad828d-a937-4732-bbee-ae538e9960ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31226
46709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3122646709
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3871443773
Short name T1430
Test name
Test status
Simulation time 3284726172 ps
CPU time 4.11 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:58:35 PM PDT 24
Peak memory 206432 kb
Host smart-7611ea76-7219-4720-b6bc-93fe3b6745fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38714
43773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3871443773
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.589789451
Short name T2069
Test name
Test status
Simulation time 6857722609 ps
CPU time 61.75 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:59:44 PM PDT 24
Peak memory 206656 kb
Host smart-d2d155ab-3744-42f9-9065-9896215b7a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58978
9451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.589789451
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2890890493
Short name T545
Test name
Test status
Simulation time 5609926760 ps
CPU time 53.68 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206616 kb
Host smart-328ded5c-2ceb-47a6-8fe9-d60bcfec67be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2890890493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2890890493
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.15746156
Short name T1659
Test name
Test status
Simulation time 263102335 ps
CPU time 0.9 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206380 kb
Host smart-668a216e-126a-43a7-94c3-03186c85b093
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=15746156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.15746156
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3951272936
Short name T2435
Test name
Test status
Simulation time 183199600 ps
CPU time 0.84 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206404 kb
Host smart-6948d21f-8f08-4aef-8aa6-0351b6c6d900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39512
72936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3951272936
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2487384485
Short name T6
Test name
Test status
Simulation time 4951581024 ps
CPU time 136.31 seconds
Started Jul 11 05:58:17 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206684 kb
Host smart-855776a5-00f0-410a-8e03-aa491ee0b129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24873
84485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2487384485
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2842684342
Short name T2086
Test name
Test status
Simulation time 7081388413 ps
CPU time 50.5 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:59:21 PM PDT 24
Peak memory 206628 kb
Host smart-28ef6e2d-587e-4837-8ae2-7eb7a4c96d18
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2842684342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2842684342
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.876250840
Short name T1788
Test name
Test status
Simulation time 162200603 ps
CPU time 0.85 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206392 kb
Host smart-c205e70b-7734-4b90-946f-97ef0e685531
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=876250840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.876250840
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1886570029
Short name T2394
Test name
Test status
Simulation time 183119788 ps
CPU time 0.8 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:58:32 PM PDT 24
Peak memory 206392 kb
Host smart-b56c989b-e88e-48e2-aa75-a47ab23d9398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
70029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1886570029
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2566510433
Short name T938
Test name
Test status
Simulation time 215871555 ps
CPU time 0.87 seconds
Started Jul 11 05:58:29 PM PDT 24
Finished Jul 11 05:58:42 PM PDT 24
Peak memory 206324 kb
Host smart-3fc0c2e3-1d62-423c-aa19-fcc3ed45e4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25665
10433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2566510433
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.686012657
Short name T2287
Test name
Test status
Simulation time 175542742 ps
CPU time 0.78 seconds
Started Jul 11 05:58:26 PM PDT 24
Finished Jul 11 05:58:39 PM PDT 24
Peak memory 206316 kb
Host smart-3ced48e7-2097-4ed5-9a7f-ec3fcc31ad70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68601
2657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.686012657
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2951021277
Short name T329
Test name
Test status
Simulation time 169807156 ps
CPU time 0.81 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:58:59 PM PDT 24
Peak memory 206384 kb
Host smart-2c5184e2-a3bc-4870-be88-0a5f6679eb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
21277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2951021277
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.4077618018
Short name T2630
Test name
Test status
Simulation time 196952815 ps
CPU time 0.9 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:58:35 PM PDT 24
Peak memory 206380 kb
Host smart-6d3b2df1-4dc7-419a-bfe3-cb0411d3fc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
18018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.4077618018
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.4198364006
Short name T1550
Test name
Test status
Simulation time 152567372 ps
CPU time 0.82 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:58:32 PM PDT 24
Peak memory 206300 kb
Host smart-bf700df0-e204-44ba-9fbe-bc24043015b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41983
64006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.4198364006
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1248196562
Short name T1806
Test name
Test status
Simulation time 183105053 ps
CPU time 0.89 seconds
Started Jul 11 05:58:29 PM PDT 24
Finished Jul 11 05:58:43 PM PDT 24
Peak memory 206344 kb
Host smart-4dee2a97-d1e8-4ee6-9b5e-ef99e2fc0827
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1248196562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1248196562
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.259549523
Short name T2176
Test name
Test status
Simulation time 149998385 ps
CPU time 0.77 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:58:39 PM PDT 24
Peak memory 206472 kb
Host smart-2b735cef-47a2-4fec-a044-a28e3cddbd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25954
9523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.259549523
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2515920240
Short name T1253
Test name
Test status
Simulation time 36119831 ps
CPU time 0.62 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:58:32 PM PDT 24
Peak memory 206360 kb
Host smart-c7059480-7a3d-4157-8e45-88e860f884fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25159
20240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2515920240
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3556705680
Short name T1255
Test name
Test status
Simulation time 12432629006 ps
CPU time 26.64 seconds
Started Jul 11 05:58:19 PM PDT 24
Finished Jul 11 05:58:57 PM PDT 24
Peak memory 206680 kb
Host smart-1c731b70-01d8-441c-bb6f-381f8c4e7f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35567
05680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3556705680
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.4186138383
Short name T2305
Test name
Test status
Simulation time 197278491 ps
CPU time 0.8 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206364 kb
Host smart-d623526a-f048-496c-bcab-8603ddd6e73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41861
38383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.4186138383
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3564796440
Short name T850
Test name
Test status
Simulation time 191818926 ps
CPU time 0.89 seconds
Started Jul 11 05:58:22 PM PDT 24
Finished Jul 11 05:58:34 PM PDT 24
Peak memory 206332 kb
Host smart-1d0f6069-07aa-48cd-9b31-eb1508707dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35647
96440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3564796440
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1500731030
Short name T2193
Test name
Test status
Simulation time 241148861 ps
CPU time 0.99 seconds
Started Jul 11 05:58:30 PM PDT 24
Finished Jul 11 05:58:43 PM PDT 24
Peak memory 206384 kb
Host smart-c9717abb-7a10-474f-bfcc-66cebd34bdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15007
31030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1500731030
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1931724166
Short name T2055
Test name
Test status
Simulation time 185974217 ps
CPU time 0.91 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 206408 kb
Host smart-a74819eb-8ebc-4214-a635-b6332cf29876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19317
24166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1931724166
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3882993979
Short name T2288
Test name
Test status
Simulation time 139868224 ps
CPU time 0.77 seconds
Started Jul 11 05:58:19 PM PDT 24
Finished Jul 11 05:58:31 PM PDT 24
Peak memory 206396 kb
Host smart-d3a3bf94-8eb4-4657-a534-8369412ba78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38829
93979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3882993979
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.4207140395
Short name T1837
Test name
Test status
Simulation time 165007794 ps
CPU time 0.77 seconds
Started Jul 11 05:58:35 PM PDT 24
Finished Jul 11 05:58:48 PM PDT 24
Peak memory 206384 kb
Host smart-3dc3e151-e7bd-4901-8f4a-88074483b784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42071
40395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.4207140395
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2904550074
Short name T1505
Test name
Test status
Simulation time 151011773 ps
CPU time 0.8 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:58:33 PM PDT 24
Peak memory 206396 kb
Host smart-3dfdd7b3-d8ff-469c-8d55-8e42e2f4d28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29045
50074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2904550074
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3687162410
Short name T2509
Test name
Test status
Simulation time 238999979 ps
CPU time 1.02 seconds
Started Jul 11 05:58:20 PM PDT 24
Finished Jul 11 05:58:33 PM PDT 24
Peak memory 206396 kb
Host smart-d9f0f8d5-a1e3-43a8-abeb-2c7289b0560c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36871
62410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3687162410
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3595135845
Short name T388
Test name
Test status
Simulation time 5644414166 ps
CPU time 52 seconds
Started Jul 11 05:58:21 PM PDT 24
Finished Jul 11 05:59:25 PM PDT 24
Peak memory 206604 kb
Host smart-7031e448-59b5-4f93-887d-fdc8321f24c9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3595135845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3595135845
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1014214227
Short name T1233
Test name
Test status
Simulation time 213225003 ps
CPU time 0.84 seconds
Started Jul 11 05:59:08 PM PDT 24
Finished Jul 11 05:59:17 PM PDT 24
Peak memory 206408 kb
Host smart-a977bb39-f599-4422-b6fb-206ae8120dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10142
14227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1014214227
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3089268137
Short name T1939
Test name
Test status
Simulation time 166765547 ps
CPU time 0.8 seconds
Started Jul 11 05:58:29 PM PDT 24
Finished Jul 11 05:58:42 PM PDT 24
Peak memory 206336 kb
Host smart-b97c3c78-3214-419a-8d46-aec82fa45d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892
68137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3089268137
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2810555954
Short name T806
Test name
Test status
Simulation time 1205409108 ps
CPU time 2.38 seconds
Started Jul 11 05:58:25 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206572 kb
Host smart-f1756b31-5771-444e-9870-42bb946f57f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28105
55954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2810555954
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2820364366
Short name T2392
Test name
Test status
Simulation time 4680404786 ps
CPU time 127.58 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206536 kb
Host smart-ba2519c1-6d49-4858-b205-f8bd9fcbbd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28203
64366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2820364366
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.4001548756
Short name T503
Test name
Test status
Simulation time 106857121 ps
CPU time 0.7 seconds
Started Jul 11 05:58:30 PM PDT 24
Finished Jul 11 05:58:43 PM PDT 24
Peak memory 206428 kb
Host smart-b085dd4d-bab9-4249-88a1-88d8f7ccc824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4001548756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.4001548756
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3239257342
Short name T1023
Test name
Test status
Simulation time 4359799021 ps
CPU time 4.72 seconds
Started Jul 11 05:58:35 PM PDT 24
Finished Jul 11 05:58:51 PM PDT 24
Peak memory 206452 kb
Host smart-44357d0e-ce02-44ce-9614-01091a978925
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3239257342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3239257342
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2958401940
Short name T522
Test name
Test status
Simulation time 13412884636 ps
CPU time 13.35 seconds
Started Jul 11 05:58:22 PM PDT 24
Finished Jul 11 05:58:46 PM PDT 24
Peak memory 206456 kb
Host smart-8520f055-3eaa-43dc-b761-80af5ff06416
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2958401940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2958401940
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.842652709
Short name T775
Test name
Test status
Simulation time 23387875957 ps
CPU time 29.57 seconds
Started Jul 11 05:58:28 PM PDT 24
Finished Jul 11 05:59:09 PM PDT 24
Peak memory 206416 kb
Host smart-e3f2f031-2450-46ff-a0bd-28aedf6afe55
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=842652709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.842652709
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3989003986
Short name T366
Test name
Test status
Simulation time 163753750 ps
CPU time 0.8 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206400 kb
Host smart-6db3ebdf-11c7-4b3c-9fa3-5f9b88238032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39890
03986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3989003986
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.315381668
Short name T854
Test name
Test status
Simulation time 141168791 ps
CPU time 0.76 seconds
Started Jul 11 05:58:21 PM PDT 24
Finished Jul 11 05:58:34 PM PDT 24
Peak memory 206404 kb
Host smart-ea0e521b-1028-491e-964d-56992d7cba0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31538
1668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.315381668
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1798237660
Short name T1350
Test name
Test status
Simulation time 208916542 ps
CPU time 0.8 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:58:35 PM PDT 24
Peak memory 206372 kb
Host smart-5113bed0-132a-4744-9221-6f535de32a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17982
37660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1798237660
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.558215504
Short name T1349
Test name
Test status
Simulation time 1331174347 ps
CPU time 2.73 seconds
Started Jul 11 05:58:21 PM PDT 24
Finished Jul 11 05:58:35 PM PDT 24
Peak memory 206512 kb
Host smart-3821c8e3-c82e-46ca-b285-b97c04a1341f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55821
5504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.558215504
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3345480361
Short name T2499
Test name
Test status
Simulation time 16073158935 ps
CPU time 27.71 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206628 kb
Host smart-a9adc4ab-1570-4f3e-a12c-06bf683d93cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33454
80361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3345480361
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.1249646929
Short name T90
Test name
Test status
Simulation time 384190755 ps
CPU time 1.2 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206304 kb
Host smart-43a064f9-3341-44ac-a9d9-63871393a697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12496
46929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.1249646929
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2464630641
Short name T908
Test name
Test status
Simulation time 140229467 ps
CPU time 0.74 seconds
Started Jul 11 05:58:25 PM PDT 24
Finished Jul 11 05:58:38 PM PDT 24
Peak memory 206312 kb
Host smart-e3813859-4e3a-4824-87ff-b4444ba9c93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24646
30641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2464630641
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2974996015
Short name T1739
Test name
Test status
Simulation time 56207854 ps
CPU time 0.72 seconds
Started Jul 11 05:58:43 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 206380 kb
Host smart-1b6c8394-6556-4c01-aa8b-1bf9805ea092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
96015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2974996015
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.949297686
Short name T834
Test name
Test status
Simulation time 1019590898 ps
CPU time 2.25 seconds
Started Jul 11 05:58:33 PM PDT 24
Finished Jul 11 05:58:47 PM PDT 24
Peak memory 206564 kb
Host smart-870a4808-d35e-4d51-96f2-8ff12bcf0e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94929
7686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.949297686
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.951368910
Short name T2125
Test name
Test status
Simulation time 204980722 ps
CPU time 1.94 seconds
Started Jul 11 05:58:43 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 206484 kb
Host smart-cf269c24-d414-41b2-9d87-0fc6cc87a8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95136
8910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.951368910
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3739992302
Short name T1202
Test name
Test status
Simulation time 195659510 ps
CPU time 0.82 seconds
Started Jul 11 05:58:35 PM PDT 24
Finished Jul 11 05:58:48 PM PDT 24
Peak memory 206388 kb
Host smart-1605b79b-2c38-4c2d-8a22-fd3f3fdc95c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37399
92302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3739992302
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1761514874
Short name T1823
Test name
Test status
Simulation time 144686763 ps
CPU time 0.74 seconds
Started Jul 11 05:58:25 PM PDT 24
Finished Jul 11 05:58:37 PM PDT 24
Peak memory 206324 kb
Host smart-f4906d6c-a7c1-4eb5-8966-8108fccc4fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17615
14874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1761514874
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3562000469
Short name T1618
Test name
Test status
Simulation time 163308684 ps
CPU time 0.84 seconds
Started Jul 11 05:58:23 PM PDT 24
Finished Jul 11 05:58:35 PM PDT 24
Peak memory 206364 kb
Host smart-8c06e84d-f937-408c-9e37-55e3a95814cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35620
00469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3562000469
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.3763173870
Short name T2715
Test name
Test status
Simulation time 6434928446 ps
CPU time 62.41 seconds
Started Jul 11 05:58:43 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206612 kb
Host smart-16954b37-f7a2-4011-aa67-53e6fae03dda
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3763173870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3763173870
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2360227277
Short name T574
Test name
Test status
Simulation time 211051227 ps
CPU time 0.86 seconds
Started Jul 11 05:58:31 PM PDT 24
Finished Jul 11 05:58:44 PM PDT 24
Peak memory 206372 kb
Host smart-868db91d-bc4b-4489-89a9-a8305365e0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
27277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2360227277
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.686332160
Short name T979
Test name
Test status
Simulation time 23272481554 ps
CPU time 29.7 seconds
Started Jul 11 05:58:24 PM PDT 24
Finished Jul 11 05:59:05 PM PDT 24
Peak memory 206416 kb
Host smart-3623c07e-29d1-4611-935e-88305d12cc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68633
2160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.686332160
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1905529623
Short name T2397
Test name
Test status
Simulation time 3265232414 ps
CPU time 4.5 seconds
Started Jul 11 05:58:26 PM PDT 24
Finished Jul 11 05:58:43 PM PDT 24
Peak memory 206440 kb
Host smart-c01df0df-21e3-4494-b90e-1cdd61bfc08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19055
29623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1905529623
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1771057518
Short name T1301
Test name
Test status
Simulation time 8086968234 ps
CPU time 226.48 seconds
Started Jul 11 05:58:35 PM PDT 24
Finished Jul 11 06:02:33 PM PDT 24
Peak memory 206744 kb
Host smart-fd6c5057-46e6-4629-972b-c94ba0e04eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17710
57518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1771057518
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3427315528
Short name T2619
Test name
Test status
Simulation time 7410793640 ps
CPU time 50.8 seconds
Started Jul 11 05:58:30 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206632 kb
Host smart-11d34c69-4ae8-40d3-9893-f73f0f6d154a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3427315528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3427315528
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1900028842
Short name T1929
Test name
Test status
Simulation time 247768013 ps
CPU time 0.91 seconds
Started Jul 11 05:58:26 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206376 kb
Host smart-02483093-a355-4ca0-a8a5-3a4fb1603070
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1900028842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1900028842
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3558436696
Short name T1987
Test name
Test status
Simulation time 227433887 ps
CPU time 0.98 seconds
Started Jul 11 05:58:25 PM PDT 24
Finished Jul 11 05:58:38 PM PDT 24
Peak memory 206312 kb
Host smart-6589ed67-e41c-4b33-9059-a8e85897402c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35584
36696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3558436696
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.736316400
Short name T558
Test name
Test status
Simulation time 6066306279 ps
CPU time 44.57 seconds
Started Jul 11 05:58:25 PM PDT 24
Finished Jul 11 05:59:21 PM PDT 24
Peak memory 206720 kb
Host smart-1cf8292d-dfbf-4d5d-8d69-c7a2623e9be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73631
6400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.736316400
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1019052995
Short name T1247
Test name
Test status
Simulation time 3511981254 ps
CPU time 90.05 seconds
Started Jul 11 05:58:56 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 206640 kb
Host smart-dbc9bc51-c56f-4d28-9750-0a4cd0e4c894
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1019052995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1019052995
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3452811148
Short name T2428
Test name
Test status
Simulation time 183291380 ps
CPU time 0.82 seconds
Started Jul 11 05:58:36 PM PDT 24
Finished Jul 11 05:58:48 PM PDT 24
Peak memory 206388 kb
Host smart-94400060-972b-4c4b-b676-2e3e3b88c972
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3452811148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3452811148
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3001702130
Short name T942
Test name
Test status
Simulation time 148162497 ps
CPU time 0.74 seconds
Started Jul 11 05:58:36 PM PDT 24
Finished Jul 11 05:58:48 PM PDT 24
Peak memory 206388 kb
Host smart-fef8e8c3-d24a-4f52-bc8b-6e1b6a0526b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30017
02130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3001702130
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3862674934
Short name T127
Test name
Test status
Simulation time 196195157 ps
CPU time 0.82 seconds
Started Jul 11 05:58:37 PM PDT 24
Finished Jul 11 05:58:49 PM PDT 24
Peak memory 206332 kb
Host smart-c338ca3c-0456-4d5d-89bd-e89cc574e140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626
74934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3862674934
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.752751303
Short name T1601
Test name
Test status
Simulation time 200050241 ps
CPU time 0.82 seconds
Started Jul 11 05:58:34 PM PDT 24
Finished Jul 11 05:58:47 PM PDT 24
Peak memory 206396 kb
Host smart-36c900f9-c922-495c-b7d7-f382cc75f001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75275
1303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.752751303
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1697535169
Short name T1292
Test name
Test status
Simulation time 202956727 ps
CPU time 0.87 seconds
Started Jul 11 05:58:32 PM PDT 24
Finished Jul 11 05:58:44 PM PDT 24
Peak memory 206384 kb
Host smart-06258dcd-0cfe-4d3a-8d47-56ae6afe938d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
35169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1697535169
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.934835810
Short name T408
Test name
Test status
Simulation time 170925328 ps
CPU time 0.77 seconds
Started Jul 11 05:58:36 PM PDT 24
Finished Jul 11 05:58:49 PM PDT 24
Peak memory 206388 kb
Host smart-4266884a-2ec2-4d5b-82ab-e80788a97c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93483
5810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.934835810
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2855059868
Short name T2251
Test name
Test status
Simulation time 162455196 ps
CPU time 0.78 seconds
Started Jul 11 05:58:28 PM PDT 24
Finished Jul 11 05:58:41 PM PDT 24
Peak memory 206408 kb
Host smart-1fab325b-301c-458b-83a7-b8e7b509b67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28550
59868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2855059868
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.857964042
Short name T1153
Test name
Test status
Simulation time 231613551 ps
CPU time 0.96 seconds
Started Jul 11 05:58:39 PM PDT 24
Finished Jul 11 05:58:51 PM PDT 24
Peak memory 206332 kb
Host smart-274ff8df-a05e-44ff-900c-849eb1f5c9ce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=857964042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.857964042
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.4284411025
Short name T1223
Test name
Test status
Simulation time 212462688 ps
CPU time 0.83 seconds
Started Jul 11 05:58:33 PM PDT 24
Finished Jul 11 05:58:46 PM PDT 24
Peak memory 206352 kb
Host smart-51b0ceb1-21ba-4ee0-922e-a7e7f0af504b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42844
11025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.4284411025
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3240522884
Short name T789
Test name
Test status
Simulation time 41372430 ps
CPU time 0.66 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206396 kb
Host smart-897c42f0-bc6f-46f8-bf72-9a936e230a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32405
22884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3240522884
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.509774424
Short name T94
Test name
Test status
Simulation time 11123400579 ps
CPU time 28.64 seconds
Started Jul 11 05:58:39 PM PDT 24
Finished Jul 11 05:59:19 PM PDT 24
Peak memory 206732 kb
Host smart-2cae1ea0-cf84-4ca3-aaf8-a529a25e224a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50977
4424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.509774424
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.4023201081
Short name T591
Test name
Test status
Simulation time 176532612 ps
CPU time 0.81 seconds
Started Jul 11 05:58:43 PM PDT 24
Finished Jul 11 05:58:55 PM PDT 24
Peak memory 206388 kb
Host smart-fbc163b0-bd3c-42a4-9835-f7374276299c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40232
01081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.4023201081
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.97716486
Short name T1008
Test name
Test status
Simulation time 214215327 ps
CPU time 0.84 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:58:41 PM PDT 24
Peak memory 206260 kb
Host smart-1c684de7-3d52-4a2a-8a9e-f9cf53383cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97716
486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.97716486
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.1232396458
Short name T1570
Test name
Test status
Simulation time 202198443 ps
CPU time 0.84 seconds
Started Jul 11 05:58:32 PM PDT 24
Finished Jul 11 05:58:44 PM PDT 24
Peak memory 206384 kb
Host smart-940fe0b8-bec2-4863-8e15-ebb046bef3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
96458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.1232396458
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1708101855
Short name T430
Test name
Test status
Simulation time 178728896 ps
CPU time 0.82 seconds
Started Jul 11 05:58:38 PM PDT 24
Finished Jul 11 05:58:50 PM PDT 24
Peak memory 206392 kb
Host smart-939b5fba-517c-4c4f-9ec1-66076ea118f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17081
01855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1708101855
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3768875818
Short name T96
Test name
Test status
Simulation time 136720194 ps
CPU time 0.74 seconds
Started Jul 11 05:58:28 PM PDT 24
Finished Jul 11 05:58:40 PM PDT 24
Peak memory 206400 kb
Host smart-d0626c7c-4cce-4918-babe-45fb3ff8efbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37688
75818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3768875818
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2692069666
Short name T1150
Test name
Test status
Simulation time 150029944 ps
CPU time 0.77 seconds
Started Jul 11 05:58:32 PM PDT 24
Finished Jul 11 05:58:45 PM PDT 24
Peak memory 206292 kb
Host smart-31510c9f-5c45-466e-b777-e42921867d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26920
69666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2692069666
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3335543713
Short name T1162
Test name
Test status
Simulation time 158406773 ps
CPU time 0.77 seconds
Started Jul 11 05:58:33 PM PDT 24
Finished Jul 11 05:58:45 PM PDT 24
Peak memory 206400 kb
Host smart-db8fc463-5e16-4394-8b3a-315f558eba9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33355
43713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3335543713
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1935571280
Short name T1154
Test name
Test status
Simulation time 306487471 ps
CPU time 1.08 seconds
Started Jul 11 05:58:33 PM PDT 24
Finished Jul 11 05:58:46 PM PDT 24
Peak memory 206340 kb
Host smart-2142c68a-966f-40e9-a462-aeb61fc210ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19355
71280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1935571280
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.4218824832
Short name T1338
Test name
Test status
Simulation time 3551202214 ps
CPU time 33.2 seconds
Started Jul 11 05:58:39 PM PDT 24
Finished Jul 11 05:59:23 PM PDT 24
Peak memory 206560 kb
Host smart-de2a2e94-dd33-44d3-89c5-3c4fbc646782
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4218824832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.4218824832
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3111848737
Short name T2350
Test name
Test status
Simulation time 160340425 ps
CPU time 0.79 seconds
Started Jul 11 05:58:33 PM PDT 24
Finished Jul 11 05:58:46 PM PDT 24
Peak memory 206392 kb
Host smart-01bb8c91-4207-4c08-aef3-c9f592b25bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31118
48737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3111848737
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1453216425
Short name T335
Test name
Test status
Simulation time 177188940 ps
CPU time 0.77 seconds
Started Jul 11 05:58:36 PM PDT 24
Finished Jul 11 05:58:48 PM PDT 24
Peak memory 206380 kb
Host smart-61c23101-c991-4c1f-be93-d80eeb4ad95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14532
16425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1453216425
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1934829019
Short name T1300
Test name
Test status
Simulation time 989818197 ps
CPU time 2.08 seconds
Started Jul 11 05:58:27 PM PDT 24
Finished Jul 11 05:58:41 PM PDT 24
Peak memory 206584 kb
Host smart-777cc120-0aea-4118-9cdb-a80c892f2191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19348
29019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1934829019
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3317118613
Short name T2385
Test name
Test status
Simulation time 5528259988 ps
CPU time 40.45 seconds
Started Jul 11 05:58:37 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206592 kb
Host smart-2368b0dd-78cb-4a03-970c-b2778fe5a713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
18613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3317118613
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.3295202843
Short name T2672
Test name
Test status
Simulation time 33620978 ps
CPU time 0.68 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:58:59 PM PDT 24
Peak memory 206428 kb
Host smart-91d99e8b-f61a-4728-a3d9-9d77dcd7d6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3295202843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.3295202843
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2323198584
Short name T683
Test name
Test status
Simulation time 3696651455 ps
CPU time 4.2 seconds
Started Jul 11 05:58:30 PM PDT 24
Finished Jul 11 05:58:47 PM PDT 24
Peak memory 206704 kb
Host smart-fa737902-9771-403c-bb84-8fc0545bf117
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2323198584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2323198584
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2220372704
Short name T1360
Test name
Test status
Simulation time 13370274655 ps
CPU time 14.37 seconds
Started Jul 11 05:58:38 PM PDT 24
Finished Jul 11 05:59:04 PM PDT 24
Peak memory 206456 kb
Host smart-f8bea487-75a3-41c3-8593-426c6c3939b3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2220372704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2220372704
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1845138027
Short name T13
Test name
Test status
Simulation time 23364741211 ps
CPU time 22.57 seconds
Started Jul 11 05:58:29 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206456 kb
Host smart-a3a349b1-8070-4fdc-be79-492c03902bf7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1845138027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.1845138027
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2447857485
Short name T2
Test name
Test status
Simulation time 200084575 ps
CPU time 0.93 seconds
Started Jul 11 05:58:37 PM PDT 24
Finished Jul 11 05:58:49 PM PDT 24
Peak memory 206400 kb
Host smart-80cc225a-a220-452e-be35-af3031e5b534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24478
57485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2447857485
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2017089509
Short name T1121
Test name
Test status
Simulation time 190395723 ps
CPU time 0.77 seconds
Started Jul 11 05:58:32 PM PDT 24
Finished Jul 11 05:58:45 PM PDT 24
Peak memory 206372 kb
Host smart-d22a5a0b-ca22-4f78-ab1c-8e59c26b90ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20170
89509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2017089509
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.4165413794
Short name T968
Test name
Test status
Simulation time 234026546 ps
CPU time 0.98 seconds
Started Jul 11 05:58:51 PM PDT 24
Finished Jul 11 05:59:04 PM PDT 24
Peak memory 206372 kb
Host smart-8213134a-c91b-4be8-9c77-a65d787ca740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41654
13794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.4165413794
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1505024943
Short name T716
Test name
Test status
Simulation time 790730927 ps
CPU time 1.91 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206644 kb
Host smart-e1892a0f-83b2-4476-a5ed-f1d1b4024c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15050
24943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1505024943
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.511505417
Short name T2223
Test name
Test status
Simulation time 18977409080 ps
CPU time 32.38 seconds
Started Jul 11 05:58:38 PM PDT 24
Finished Jul 11 05:59:22 PM PDT 24
Peak memory 206536 kb
Host smart-cef92230-52df-4eea-b520-87c6199523e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51150
5417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.511505417
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3787575632
Short name T1037
Test name
Test status
Simulation time 459251850 ps
CPU time 1.35 seconds
Started Jul 11 05:58:33 PM PDT 24
Finished Jul 11 05:58:46 PM PDT 24
Peak memory 206348 kb
Host smart-35a30248-1367-43ce-a058-4eccf7a53671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37875
75632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3787575632
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2723651814
Short name T2411
Test name
Test status
Simulation time 148572314 ps
CPU time 0.75 seconds
Started Jul 11 05:58:32 PM PDT 24
Finished Jul 11 05:58:44 PM PDT 24
Peak memory 206384 kb
Host smart-c7dd61f8-f840-4ac5-894a-6a5d5e3ec1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27236
51814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2723651814
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3142361585
Short name T1002
Test name
Test status
Simulation time 35619103 ps
CPU time 0.64 seconds
Started Jul 11 05:58:45 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 206384 kb
Host smart-aff78756-bacd-4e4d-bf56-9a7c0b52b368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31423
61585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3142361585
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.2495500846
Short name T1895
Test name
Test status
Simulation time 976188127 ps
CPU time 2.27 seconds
Started Jul 11 05:58:37 PM PDT 24
Finished Jul 11 05:58:51 PM PDT 24
Peak memory 206568 kb
Host smart-069480ae-4c19-4404-bd69-ed506c134c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24955
00846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2495500846
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.837531112
Short name T710
Test name
Test status
Simulation time 218100757 ps
CPU time 1.59 seconds
Started Jul 11 05:58:38 PM PDT 24
Finished Jul 11 05:58:51 PM PDT 24
Peak memory 206540 kb
Host smart-c01bcb85-2222-42d8-a5bc-1d8f90747878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83753
1112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.837531112
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3926844928
Short name T488
Test name
Test status
Simulation time 267318312 ps
CPU time 1.03 seconds
Started Jul 11 05:58:50 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206280 kb
Host smart-9f9f9c01-21e3-4445-8eef-0b48377693e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39268
44928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3926844928
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3368012588
Short name T534
Test name
Test status
Simulation time 141892062 ps
CPU time 0.75 seconds
Started Jul 11 05:58:33 PM PDT 24
Finished Jul 11 05:58:46 PM PDT 24
Peak memory 206300 kb
Host smart-9d696e75-ba98-4d3c-b98e-6d006ff8e60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33680
12588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3368012588
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3880207957
Short name T2102
Test name
Test status
Simulation time 199482452 ps
CPU time 0.88 seconds
Started Jul 11 05:58:44 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 206344 kb
Host smart-61af7e4d-78f1-45a5-999a-79990f32bfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802
07957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3880207957
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.596501573
Short name T1774
Test name
Test status
Simulation time 185821322 ps
CPU time 0.8 seconds
Started Jul 11 05:58:33 PM PDT 24
Finished Jul 11 05:58:46 PM PDT 24
Peak memory 206372 kb
Host smart-1ee6c511-7813-4d6e-8d43-bf5d6e744b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59650
1573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.596501573
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.400087620
Short name T2114
Test name
Test status
Simulation time 23269625455 ps
CPU time 22.84 seconds
Started Jul 11 05:58:38 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 206368 kb
Host smart-3e426ee5-a6cc-4a61-8db4-cc3de62b5b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40008
7620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.400087620
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2088207073
Short name T528
Test name
Test status
Simulation time 3331869232 ps
CPU time 4.71 seconds
Started Jul 11 05:58:32 PM PDT 24
Finished Jul 11 05:58:49 PM PDT 24
Peak memory 206420 kb
Host smart-dbce3a41-35ea-4c3e-8036-31b798ce6acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20882
07073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2088207073
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.4261862660
Short name T889
Test name
Test status
Simulation time 7140869949 ps
CPU time 64.96 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 06:00:06 PM PDT 24
Peak memory 206708 kb
Host smart-9398f239-9986-4492-8047-cf16fc58be12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42618
62660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.4261862660
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.656102586
Short name T2121
Test name
Test status
Simulation time 4840728267 ps
CPU time 35.94 seconds
Started Jul 11 05:58:36 PM PDT 24
Finished Jul 11 05:59:23 PM PDT 24
Peak memory 206632 kb
Host smart-49998583-9a67-4a1b-9281-73efc6409e8c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=656102586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.656102586
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1337471216
Short name T524
Test name
Test status
Simulation time 251948067 ps
CPU time 0.91 seconds
Started Jul 11 05:58:35 PM PDT 24
Finished Jul 11 05:58:47 PM PDT 24
Peak memory 206388 kb
Host smart-e636e6cf-f852-44a8-b4ae-3eac65918c9a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1337471216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1337471216
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3394331269
Short name T863
Test name
Test status
Simulation time 195847791 ps
CPU time 0.83 seconds
Started Jul 11 05:58:43 PM PDT 24
Finished Jul 11 05:58:55 PM PDT 24
Peak memory 206296 kb
Host smart-581600ff-9795-4359-8817-97c5a2d733e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
31269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3394331269
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2834556196
Short name T1269
Test name
Test status
Simulation time 5297033836 ps
CPU time 49.6 seconds
Started Jul 11 05:58:50 PM PDT 24
Finished Jul 11 05:59:51 PM PDT 24
Peak memory 206564 kb
Host smart-02a593f7-e9eb-4ecd-aa68-824811d2af07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28345
56196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2834556196
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.991247538
Short name T2286
Test name
Test status
Simulation time 5926655375 ps
CPU time 163.23 seconds
Started Jul 11 05:58:35 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206628 kb
Host smart-27ca617a-c601-4319-9275-afbea3b944da
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=991247538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.991247538
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.236974406
Short name T1095
Test name
Test status
Simulation time 156512942 ps
CPU time 0.85 seconds
Started Jul 11 05:58:44 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 206336 kb
Host smart-9e20ceda-c5aa-4f42-915c-f72c0944dd76
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=236974406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.236974406
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3046990841
Short name T1897
Test name
Test status
Simulation time 208255498 ps
CPU time 0.82 seconds
Started Jul 11 05:58:39 PM PDT 24
Finished Jul 11 05:58:51 PM PDT 24
Peak memory 206464 kb
Host smart-996e38ab-2cb0-42cd-b069-2ae05a62ed56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30469
90841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3046990841
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2660771588
Short name T130
Test name
Test status
Simulation time 237453459 ps
CPU time 0.9 seconds
Started Jul 11 05:58:35 PM PDT 24
Finished Jul 11 05:58:47 PM PDT 24
Peak memory 206400 kb
Host smart-c7046ac4-9082-41bc-8c19-d3dd49080c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26607
71588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2660771588
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.933395916
Short name T1334
Test name
Test status
Simulation time 186182156 ps
CPU time 0.82 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206384 kb
Host smart-0199406f-b924-4283-aa46-6556cc53b48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93339
5916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.933395916
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2776528078
Short name T2617
Test name
Test status
Simulation time 152560375 ps
CPU time 0.81 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:58:58 PM PDT 24
Peak memory 206372 kb
Host smart-9ae5686f-dbe5-4ce8-bc76-b7fb579a47b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765
28078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2776528078
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1367574666
Short name T1323
Test name
Test status
Simulation time 177477619 ps
CPU time 0.85 seconds
Started Jul 11 05:58:52 PM PDT 24
Finished Jul 11 05:59:04 PM PDT 24
Peak memory 206404 kb
Host smart-f89adb8e-2ee7-43d9-91a7-144899134504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13675
74666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1367574666
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.409693803
Short name T1765
Test name
Test status
Simulation time 164438033 ps
CPU time 0.81 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:58:59 PM PDT 24
Peak memory 206332 kb
Host smart-903e0844-7886-4af2-a5dc-7f80dfaeee04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40969
3803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.409693803
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.3666947507
Short name T225
Test name
Test status
Simulation time 214224244 ps
CPU time 0.95 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:02 PM PDT 24
Peak memory 206312 kb
Host smart-7d95a290-4ad8-4f70-addf-2e6ad116ce3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3666947507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.3666947507
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3712628797
Short name T991
Test name
Test status
Simulation time 149755265 ps
CPU time 0.77 seconds
Started Jul 11 05:58:50 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206376 kb
Host smart-977c1453-26fb-4d1d-a1d8-0a2c60befb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37126
28797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3712628797
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2877083311
Short name T939
Test name
Test status
Simulation time 47970350 ps
CPU time 0.68 seconds
Started Jul 11 05:58:37 PM PDT 24
Finished Jul 11 05:58:49 PM PDT 24
Peak memory 206380 kb
Host smart-2e92c3b3-3c8c-4bc6-897a-e3ab64196dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28770
83311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2877083311
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.513046938
Short name T1677
Test name
Test status
Simulation time 17075206331 ps
CPU time 38.98 seconds
Started Jul 11 05:58:40 PM PDT 24
Finished Jul 11 05:59:30 PM PDT 24
Peak memory 206680 kb
Host smart-77286d35-da70-4f3a-8d84-3f234fabd4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51304
6938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.513046938
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.125988542
Short name T1133
Test name
Test status
Simulation time 225588129 ps
CPU time 0.86 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206292 kb
Host smart-68f3d83e-13a1-44d8-8d12-942338e6fef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12598
8542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.125988542
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1247175335
Short name T1988
Test name
Test status
Simulation time 233899503 ps
CPU time 0.89 seconds
Started Jul 11 05:58:42 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 206308 kb
Host smart-d7246d97-8990-4f41-97df-db2ffdc1ae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12471
75335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1247175335
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3463427116
Short name T2484
Test name
Test status
Simulation time 227924373 ps
CPU time 0.84 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206352 kb
Host smart-a62cc276-9908-4e7f-b198-9f4267bca0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34634
27116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3463427116
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.1117639921
Short name T2032
Test name
Test status
Simulation time 163698670 ps
CPU time 0.83 seconds
Started Jul 11 05:58:42 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 206404 kb
Host smart-21eddae3-caa1-449a-b6f6-98318ba2e65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
39921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1117639921
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.2075943544
Short name T1137
Test name
Test status
Simulation time 169294917 ps
CPU time 0.81 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:58:58 PM PDT 24
Peak memory 206368 kb
Host smart-e9430e6a-4981-4a34-a4c3-3edaa6971ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20759
43544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.2075943544
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2505693011
Short name T1061
Test name
Test status
Simulation time 149527842 ps
CPU time 0.81 seconds
Started Jul 11 05:58:43 PM PDT 24
Finished Jul 11 05:58:55 PM PDT 24
Peak memory 206300 kb
Host smart-95cfdce2-8560-4b6a-b9d2-433abb48e298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25056
93011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2505693011
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3296392715
Short name T1748
Test name
Test status
Simulation time 160251631 ps
CPU time 0.78 seconds
Started Jul 11 05:58:42 PM PDT 24
Finished Jul 11 05:58:53 PM PDT 24
Peak memory 206388 kb
Host smart-367b2ec7-4481-4989-826b-7ba824bd2f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32963
92715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3296392715
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2616487495
Short name T2234
Test name
Test status
Simulation time 214988084 ps
CPU time 0.87 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206380 kb
Host smart-c8914619-d8d9-4722-afbc-4ef6ba5ec3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26164
87495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2616487495
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1381020921
Short name T489
Test name
Test status
Simulation time 2741824310 ps
CPU time 71.93 seconds
Started Jul 11 06:04:34 PM PDT 24
Finished Jul 11 06:05:48 PM PDT 24
Peak memory 206500 kb
Host smart-23f636ae-ea61-4d54-a4e8-85b67b75e94c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1381020921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1381020921
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.446432163
Short name T1740
Test name
Test status
Simulation time 176513971 ps
CPU time 0.79 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:01 PM PDT 24
Peak memory 206400 kb
Host smart-7a66c035-34a5-40ab-9dc0-c91910250928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44643
2163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.446432163
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2332312894
Short name T2360
Test name
Test status
Simulation time 174223590 ps
CPU time 0.84 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:01 PM PDT 24
Peak memory 206340 kb
Host smart-d95f413d-08f4-4401-a23f-f02646493df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23323
12894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2332312894
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.713734484
Short name T2450
Test name
Test status
Simulation time 761089386 ps
CPU time 1.65 seconds
Started Jul 11 05:58:46 PM PDT 24
Finished Jul 11 05:58:59 PM PDT 24
Peak memory 206628 kb
Host smart-cc0042d5-57fc-4271-95cb-197d676730c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71373
4484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.713734484
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.678281374
Short name T1918
Test name
Test status
Simulation time 6598101914 ps
CPU time 186.97 seconds
Started Jul 11 05:58:46 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 206648 kb
Host smart-98102ebb-3128-4432-b64d-1a2c3d58645d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67828
1374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.678281374
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2244978628
Short name T196
Test name
Test status
Simulation time 91774455 ps
CPU time 0.75 seconds
Started Jul 11 05:58:54 PM PDT 24
Finished Jul 11 05:59:06 PM PDT 24
Peak memory 206448 kb
Host smart-8f709b02-aba8-4d8f-80f5-1b2f978ecb37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2244978628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2244978628
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3622704279
Short name T506
Test name
Test status
Simulation time 3616700849 ps
CPU time 4.92 seconds
Started Jul 11 05:58:46 PM PDT 24
Finished Jul 11 05:59:02 PM PDT 24
Peak memory 206648 kb
Host smart-210a5c32-5922-4806-a74f-3466032bdb40
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3622704279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.3622704279
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3435614982
Short name T2406
Test name
Test status
Simulation time 13421176559 ps
CPU time 16.36 seconds
Started Jul 11 05:58:42 PM PDT 24
Finished Jul 11 05:59:10 PM PDT 24
Peak memory 206664 kb
Host smart-661eca29-f525-42ab-a9eb-808d98983402
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3435614982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3435614982
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.215450481
Short name T955
Test name
Test status
Simulation time 23378367859 ps
CPU time 28.69 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:59:27 PM PDT 24
Peak memory 206376 kb
Host smart-761b5663-437c-4664-a65f-2ad0e5d0affb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=215450481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.215450481
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1844413617
Short name T1071
Test name
Test status
Simulation time 162889496 ps
CPU time 0.8 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:58:59 PM PDT 24
Peak memory 206372 kb
Host smart-a412c029-4cb3-4ec9-8977-cfcc60eecf23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18444
13617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1844413617
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3951293677
Short name T1713
Test name
Test status
Simulation time 142382288 ps
CPU time 0.79 seconds
Started Jul 11 05:58:51 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206372 kb
Host smart-b06a0659-a585-4d1b-b7c2-6492f6983101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39512
93677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3951293677
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.864110796
Short name T1016
Test name
Test status
Simulation time 207615398 ps
CPU time 0.87 seconds
Started Jul 11 05:58:45 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 206296 kb
Host smart-6b226416-df0a-4ff4-9d8a-ea354c73d506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86411
0796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.864110796
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3725546543
Short name T1771
Test name
Test status
Simulation time 532181241 ps
CPU time 1.51 seconds
Started Jul 11 05:58:51 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206368 kb
Host smart-2875bc43-3209-4df9-85de-1e1dd2548b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37255
46543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3725546543
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2657783832
Short name T760
Test name
Test status
Simulation time 22869061238 ps
CPU time 45.52 seconds
Started Jul 11 05:58:45 PM PDT 24
Finished Jul 11 05:59:41 PM PDT 24
Peak memory 206644 kb
Host smart-e8bc706e-fa43-42e9-870b-8bd41eea3b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26577
83832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2657783832
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.593404155
Short name T1285
Test name
Test status
Simulation time 372505671 ps
CPU time 1.2 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206404 kb
Host smart-25611051-b5fd-49a1-a2bb-752d8f998694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59340
4155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.593404155
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2224852168
Short name T2486
Test name
Test status
Simulation time 154949257 ps
CPU time 0.79 seconds
Started Jul 11 05:58:44 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 206384 kb
Host smart-d4edf1b2-5fe6-4ad9-a928-4c28fbb916f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22248
52168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2224852168
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1246440785
Short name T1491
Test name
Test status
Simulation time 39011082 ps
CPU time 0.64 seconds
Started Jul 11 05:58:43 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 206388 kb
Host smart-fdc8a3cc-8738-4f36-aec5-6135f8a060ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12464
40785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1246440785
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3137376477
Short name T2196
Test name
Test status
Simulation time 1001556595 ps
CPU time 2.26 seconds
Started Jul 11 05:58:44 PM PDT 24
Finished Jul 11 05:58:57 PM PDT 24
Peak memory 206584 kb
Host smart-df02d751-952e-4bf9-baad-372220de814c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31373
76477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3137376477
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3828746264
Short name T2250
Test name
Test status
Simulation time 282195830 ps
CPU time 1.57 seconds
Started Jul 11 05:58:53 PM PDT 24
Finished Jul 11 05:59:06 PM PDT 24
Peak memory 206664 kb
Host smart-06066601-9b14-4812-ad36-b154ab4ad652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38287
46264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3828746264
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3694735473
Short name T23
Test name
Test status
Simulation time 165669394 ps
CPU time 0.78 seconds
Started Jul 11 05:58:45 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 206388 kb
Host smart-c069046f-a2bb-43f3-8e37-99caa925cf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36947
35473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3694735473
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1359576775
Short name T440
Test name
Test status
Simulation time 141295465 ps
CPU time 0.79 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:01 PM PDT 24
Peak memory 206308 kb
Host smart-e5693cd5-8fd0-4be1-acd0-7efb0cf60893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13595
76775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1359576775
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3145760766
Short name T1391
Test name
Test status
Simulation time 251673011 ps
CPU time 1 seconds
Started Jul 11 05:58:42 PM PDT 24
Finished Jul 11 05:58:55 PM PDT 24
Peak memory 206396 kb
Host smart-e3a4a695-29d6-48a7-9921-6debd979993a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
60766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3145760766
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.3994504894
Short name T2644
Test name
Test status
Simulation time 12260906486 ps
CPU time 46.18 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206644 kb
Host smart-31b4a73d-60f5-431d-ba97-42f5dddbf155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39945
04894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3994504894
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.634695918
Short name T978
Test name
Test status
Simulation time 217447192 ps
CPU time 0.9 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:02 PM PDT 24
Peak memory 206364 kb
Host smart-c18c1b57-3727-441f-994f-296fbfc88e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63469
5918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.634695918
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.1784529991
Short name T2326
Test name
Test status
Simulation time 23335437488 ps
CPU time 21.54 seconds
Started Jul 11 05:58:46 PM PDT 24
Finished Jul 11 05:59:18 PM PDT 24
Peak memory 206364 kb
Host smart-0459c71f-d5c1-420f-95c2-cff9278ebfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17845
29991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1784529991
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2510043302
Short name T1581
Test name
Test status
Simulation time 3338525669 ps
CPU time 4.9 seconds
Started Jul 11 05:58:46 PM PDT 24
Finished Jul 11 05:59:02 PM PDT 24
Peak memory 206452 kb
Host smart-15b8153f-b22f-4bd6-a6aa-6da3297991ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25100
43302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2510043302
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.1797765308
Short name T827
Test name
Test status
Simulation time 7879047992 ps
CPU time 74.93 seconds
Started Jul 11 05:58:46 PM PDT 24
Finished Jul 11 06:00:12 PM PDT 24
Peak memory 206724 kb
Host smart-84ee88c8-ce3e-4060-98ae-d72db9efceec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977
65308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.1797765308
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1630982594
Short name T386
Test name
Test status
Simulation time 4803127673 ps
CPU time 34.32 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206688 kb
Host smart-d9e43b61-f66c-4b08-a95c-7b11bf1c562f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1630982594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1630982594
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1854708539
Short name T1650
Test name
Test status
Simulation time 254740570 ps
CPU time 0.88 seconds
Started Jul 11 05:58:45 PM PDT 24
Finished Jul 11 05:58:57 PM PDT 24
Peak memory 206272 kb
Host smart-f152fc88-aba3-48aa-8a9c-1131089850bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1854708539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1854708539
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3001066217
Short name T1520
Test name
Test status
Simulation time 198861735 ps
CPU time 0.9 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:02 PM PDT 24
Peak memory 206312 kb
Host smart-41b5f0cc-1d5b-46aa-bf69-d3c4fdbd2bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30010
66217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3001066217
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.222297789
Short name T2002
Test name
Test status
Simulation time 5146058876 ps
CPU time 137.69 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 06:01:16 PM PDT 24
Peak memory 206652 kb
Host smart-26df3667-1afa-4de4-86ec-d1fba61602b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22229
7789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.222297789
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2462716378
Short name T2438
Test name
Test status
Simulation time 5379743018 ps
CPU time 38.99 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:59:37 PM PDT 24
Peak memory 206632 kb
Host smart-4c98548d-7044-4a2e-aa14-90a8f0438960
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2462716378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2462716378
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.496278923
Short name T1460
Test name
Test status
Simulation time 178338372 ps
CPU time 0.8 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206332 kb
Host smart-dd83ffc1-e5cf-4ab2-9ec9-d6a9f7edde22
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=496278923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.496278923
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1713324998
Short name T847
Test name
Test status
Simulation time 147201275 ps
CPU time 0.75 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:58:59 PM PDT 24
Peak memory 206332 kb
Host smart-59909205-6962-4b1a-9d93-b75692a2b1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17133
24998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1713324998
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1667337871
Short name T2541
Test name
Test status
Simulation time 169859533 ps
CPU time 0.81 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:00 PM PDT 24
Peak memory 206388 kb
Host smart-c6f5ef43-57d5-4af9-9ed6-ef7995f9cb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16673
37871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1667337871
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2169359940
Short name T2513
Test name
Test status
Simulation time 172943811 ps
CPU time 0.84 seconds
Started Jul 11 05:58:46 PM PDT 24
Finished Jul 11 05:58:58 PM PDT 24
Peak memory 206392 kb
Host smart-b0ee94d3-ff48-45c2-8ef0-46c3e0e6402b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
59940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2169359940
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.4215949030
Short name T2387
Test name
Test status
Simulation time 214383662 ps
CPU time 0.89 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:58:58 PM PDT 24
Peak memory 206296 kb
Host smart-c2160ade-1555-43a7-9719-1c7a48c38eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42159
49030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.4215949030
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1878704936
Short name T564
Test name
Test status
Simulation time 154074998 ps
CPU time 0.81 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:01 PM PDT 24
Peak memory 206392 kb
Host smart-48533d58-d984-4bf7-b61a-61e718fcaae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18787
04936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1878704936
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.537930694
Short name T51
Test name
Test status
Simulation time 253886025 ps
CPU time 0.99 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:01 PM PDT 24
Peak memory 206380 kb
Host smart-dc4a9fde-f697-48f6-9de4-96045bb8ffbf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=537930694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.537930694
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2461512191
Short name T476
Test name
Test status
Simulation time 154584501 ps
CPU time 0.79 seconds
Started Jul 11 05:58:49 PM PDT 24
Finished Jul 11 05:59:01 PM PDT 24
Peak memory 206344 kb
Host smart-0c6fd186-3fcb-4830-abd4-160a69e64f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24615
12191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2461512191
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.4131592875
Short name T1406
Test name
Test status
Simulation time 37783109 ps
CPU time 0.64 seconds
Started Jul 11 05:59:02 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 206308 kb
Host smart-5e989beb-6674-47b8-abde-b3980e2855e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
92875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.4131592875
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1790006902
Short name T267
Test name
Test status
Simulation time 20419607841 ps
CPU time 44.55 seconds
Started Jul 11 05:58:56 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206736 kb
Host smart-9927e457-e3f5-4416-906e-5c1d44e6aa04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17900
06902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1790006902
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.4052448666
Short name T819
Test name
Test status
Simulation time 202432849 ps
CPU time 0.85 seconds
Started Jul 11 05:58:50 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206384 kb
Host smart-7758bf2c-8a68-4280-90f6-bc3605e70a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40524
48666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.4052448666
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.4031843817
Short name T327
Test name
Test status
Simulation time 177558171 ps
CPU time 0.83 seconds
Started Jul 11 05:58:50 PM PDT 24
Finished Jul 11 05:59:02 PM PDT 24
Peak memory 206380 kb
Host smart-471edf92-42c8-4b31-8cea-138631b92498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40318
43817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.4031843817
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.199344501
Short name T449
Test name
Test status
Simulation time 202657999 ps
CPU time 0.83 seconds
Started Jul 11 05:58:54 PM PDT 24
Finished Jul 11 05:59:06 PM PDT 24
Peak memory 206260 kb
Host smart-b5c38bb1-76b6-4293-b267-a125217527aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19934
4501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.199344501
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2640970439
Short name T990
Test name
Test status
Simulation time 186437924 ps
CPU time 0.84 seconds
Started Jul 11 05:58:48 PM PDT 24
Finished Jul 11 05:59:01 PM PDT 24
Peak memory 206408 kb
Host smart-050c257c-b1ff-40c6-81f1-c0cf0f51aabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26409
70439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2640970439
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.117305706
Short name T53
Test name
Test status
Simulation time 176193397 ps
CPU time 0.8 seconds
Started Jul 11 05:58:58 PM PDT 24
Finished Jul 11 05:59:09 PM PDT 24
Peak memory 206392 kb
Host smart-3bdd6ada-9c58-4e14-aa12-85e7a3f7ab80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11730
5706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.117305706
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3224759379
Short name T1868
Test name
Test status
Simulation time 174380299 ps
CPU time 0.78 seconds
Started Jul 11 05:58:55 PM PDT 24
Finished Jul 11 05:59:07 PM PDT 24
Peak memory 206328 kb
Host smart-a772f3ef-0c32-4d36-a6e4-643a8b78697a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32247
59379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3224759379
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1084365637
Short name T2146
Test name
Test status
Simulation time 151262689 ps
CPU time 0.8 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 206324 kb
Host smart-c6e82a2a-7f87-4417-afa1-b3b33f50d8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
65637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1084365637
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2438111962
Short name T675
Test name
Test status
Simulation time 259347399 ps
CPU time 1 seconds
Started Jul 11 05:58:57 PM PDT 24
Finished Jul 11 05:59:09 PM PDT 24
Peak memory 206388 kb
Host smart-773f514d-cec9-45b3-89e6-488449752a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24381
11962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2438111962
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1052079706
Short name T481
Test name
Test status
Simulation time 5908382996 ps
CPU time 57.12 seconds
Started Jul 11 05:58:51 PM PDT 24
Finished Jul 11 05:59:59 PM PDT 24
Peak memory 206696 kb
Host smart-ff3334c9-65c5-421c-be96-690f802cc5dc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1052079706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1052079706
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2924296252
Short name T333
Test name
Test status
Simulation time 155944605 ps
CPU time 0.79 seconds
Started Jul 11 05:58:58 PM PDT 24
Finished Jul 11 05:59:09 PM PDT 24
Peak memory 206360 kb
Host smart-40d6e90d-c836-4218-aa4d-0544a24168e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29242
96252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2924296252
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2104763559
Short name T2712
Test name
Test status
Simulation time 168460712 ps
CPU time 0.82 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 206328 kb
Host smart-d62dbc55-3fb4-4fb2-ba7b-91cba30593ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21047
63559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2104763559
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.779009575
Short name T1101
Test name
Test status
Simulation time 1100926276 ps
CPU time 2.33 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 05:59:13 PM PDT 24
Peak memory 206572 kb
Host smart-a7b0176a-c002-41a7-9408-34f5afe7c543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77900
9575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.779009575
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2563553604
Short name T982
Test name
Test status
Simulation time 3107388622 ps
CPU time 28.43 seconds
Started Jul 11 05:58:47 PM PDT 24
Finished Jul 11 05:59:27 PM PDT 24
Peak memory 206664 kb
Host smart-b651973f-6af4-4886-b78b-6177689cbef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25635
53604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2563553604
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.408800505
Short name T2533
Test name
Test status
Simulation time 33500443 ps
CPU time 0.66 seconds
Started Jul 11 05:59:09 PM PDT 24
Finished Jul 11 05:59:19 PM PDT 24
Peak memory 206400 kb
Host smart-eb7f8e6f-9d3b-4d6c-8463-6aa5e0c2ba79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=408800505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.408800505
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1314450741
Short name T2153
Test name
Test status
Simulation time 3693423440 ps
CPU time 4.29 seconds
Started Jul 11 05:59:02 PM PDT 24
Finished Jul 11 05:59:16 PM PDT 24
Peak memory 206520 kb
Host smart-eaa8ad43-cbf3-4b2f-8645-3a6714bbaadd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1314450741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1314450741
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.795875729
Short name T1441
Test name
Test status
Simulation time 13313095452 ps
CPU time 12.26 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 05:59:23 PM PDT 24
Peak memory 206368 kb
Host smart-2572f06e-e61c-4f8e-b343-34f0efdab848
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=795875729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.795875729
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1469685521
Short name T1448
Test name
Test status
Simulation time 23417237701 ps
CPU time 24.42 seconds
Started Jul 11 05:58:59 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206616 kb
Host smart-486082b2-45cd-4c06-b9fd-c994a1074b00
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1469685521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1469685521
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1531281421
Short name T1000
Test name
Test status
Simulation time 166551334 ps
CPU time 0.82 seconds
Started Jul 11 05:59:02 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 206308 kb
Host smart-a7819030-18b3-4639-b9a7-6837b6dcfb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15312
81421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1531281421
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2663796610
Short name T1076
Test name
Test status
Simulation time 177760754 ps
CPU time 0.79 seconds
Started Jul 11 05:58:57 PM PDT 24
Finished Jul 11 05:59:09 PM PDT 24
Peak memory 206380 kb
Host smart-54db95e7-d984-4ffc-afbb-9f1e551d6822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26637
96610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2663796610
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3310958248
Short name T1839
Test name
Test status
Simulation time 230434589 ps
CPU time 0.94 seconds
Started Jul 11 05:58:51 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 206396 kb
Host smart-6a8d9f96-217d-4856-a251-bd7741c7b573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33109
58248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3310958248
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1453370293
Short name T2545
Test name
Test status
Simulation time 1344225784 ps
CPU time 2.87 seconds
Started Jul 11 05:58:51 PM PDT 24
Finished Jul 11 05:59:05 PM PDT 24
Peak memory 206584 kb
Host smart-62cc035b-1b16-4de3-8860-8ecee59c67e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14533
70293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1453370293
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3223796147
Short name T2570
Test name
Test status
Simulation time 21651765227 ps
CPU time 42.18 seconds
Started Jul 11 05:58:55 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206700 kb
Host smart-b231a68d-5676-4ad9-801f-12bd11ed85a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32237
96147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3223796147
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3430301307
Short name T1211
Test name
Test status
Simulation time 359505627 ps
CPU time 1.13 seconds
Started Jul 11 05:58:59 PM PDT 24
Finished Jul 11 05:59:10 PM PDT 24
Peak memory 206340 kb
Host smart-058e76d2-4178-4579-932f-cd550d531795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34303
01307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3430301307
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1409672679
Short name T898
Test name
Test status
Simulation time 156153656 ps
CPU time 0.77 seconds
Started Jul 11 05:58:57 PM PDT 24
Finished Jul 11 05:59:09 PM PDT 24
Peak memory 206372 kb
Host smart-e22a88bd-a9f5-4649-aa76-4944c0c81ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14096
72679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1409672679
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2717959472
Short name T2697
Test name
Test status
Simulation time 81045450 ps
CPU time 0.68 seconds
Started Jul 11 05:58:54 PM PDT 24
Finished Jul 11 05:59:06 PM PDT 24
Peak memory 206372 kb
Host smart-cc54874c-17a9-4625-ab09-1445078db9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179
59472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2717959472
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2565732288
Short name T541
Test name
Test status
Simulation time 910411171 ps
CPU time 2.31 seconds
Started Jul 11 05:58:57 PM PDT 24
Finished Jul 11 05:59:10 PM PDT 24
Peak memory 206624 kb
Host smart-8c68f90e-f71e-4ff8-9585-063a970ec3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25657
32288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2565732288
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1516370567
Short name T595
Test name
Test status
Simulation time 320394436 ps
CPU time 2.27 seconds
Started Jul 11 05:59:09 PM PDT 24
Finished Jul 11 05:59:21 PM PDT 24
Peak memory 206604 kb
Host smart-fc87afa1-dbd9-488b-9116-e626a53ee084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15163
70567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1516370567
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.274221487
Short name T2370
Test name
Test status
Simulation time 240294512 ps
CPU time 0.87 seconds
Started Jul 11 05:59:12 PM PDT 24
Finished Jul 11 05:59:22 PM PDT 24
Peak memory 206412 kb
Host smart-50d4a4f0-c0c8-4a18-91f8-de1fca3ff895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
1487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.274221487
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.4033460543
Short name T2328
Test name
Test status
Simulation time 154270283 ps
CPU time 0.76 seconds
Started Jul 11 05:58:55 PM PDT 24
Finished Jul 11 05:59:07 PM PDT 24
Peak memory 206384 kb
Host smart-eb770d7e-5d98-477a-9d23-5f7e9d179e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
60543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.4033460543
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2659993311
Short name T926
Test name
Test status
Simulation time 176402933 ps
CPU time 0.83 seconds
Started Jul 11 05:59:10 PM PDT 24
Finished Jul 11 05:59:19 PM PDT 24
Peak memory 206372 kb
Host smart-a8101bda-6670-4c48-a884-923ff4392d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26599
93311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2659993311
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.409464743
Short name T1009
Test name
Test status
Simulation time 5165889889 ps
CPU time 46.28 seconds
Started Jul 11 05:58:59 PM PDT 24
Finished Jul 11 05:59:56 PM PDT 24
Peak memory 206596 kb
Host smart-56237772-2c1a-4683-b62e-83829e917051
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=409464743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.409464743
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.667200247
Short name T2684
Test name
Test status
Simulation time 7316780178 ps
CPU time 60.36 seconds
Started Jul 11 05:58:58 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206628 kb
Host smart-8d2026d4-273a-45c5-a798-d8ace937b97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66720
0247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.667200247
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.414608748
Short name T1129
Test name
Test status
Simulation time 201797915 ps
CPU time 0.86 seconds
Started Jul 11 05:58:55 PM PDT 24
Finished Jul 11 05:59:08 PM PDT 24
Peak memory 206384 kb
Host smart-0d97f6b2-0012-48ef-b16f-480a05f239b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41460
8748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.414608748
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3637440719
Short name T1243
Test name
Test status
Simulation time 23335425256 ps
CPU time 24.4 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 206384 kb
Host smart-ac8e1e80-21cd-4d5d-a448-867ef768ec63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36374
40719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3637440719
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.766985356
Short name T33
Test name
Test status
Simulation time 3283398592 ps
CPU time 3.69 seconds
Started Jul 11 05:58:59 PM PDT 24
Finished Jul 11 05:59:13 PM PDT 24
Peak memory 206372 kb
Host smart-cf79e477-14a6-4deb-81ca-1628fb396147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76698
5356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.766985356
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2014456408
Short name T5
Test name
Test status
Simulation time 8018266199 ps
CPU time 75.95 seconds
Started Jul 11 05:58:53 PM PDT 24
Finished Jul 11 06:00:21 PM PDT 24
Peak memory 206600 kb
Host smart-1aced544-3b89-45a7-9681-13732d4b35b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20144
56408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2014456408
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3125497424
Short name T611
Test name
Test status
Simulation time 6352220671 ps
CPU time 48.23 seconds
Started Jul 11 05:59:00 PM PDT 24
Finished Jul 11 05:59:59 PM PDT 24
Peak memory 206676 kb
Host smart-c161a635-c5a5-4ef0-bab2-54546d91bca1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3125497424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3125497424
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.4016435084
Short name T1965
Test name
Test status
Simulation time 246137983 ps
CPU time 0.91 seconds
Started Jul 11 05:59:07 PM PDT 24
Finished Jul 11 05:59:16 PM PDT 24
Peak memory 206416 kb
Host smart-91c379ca-c822-4a9f-a860-93de98af0d64
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4016435084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.4016435084
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1745484400
Short name T1464
Test name
Test status
Simulation time 199140773 ps
CPU time 0.87 seconds
Started Jul 11 05:59:00 PM PDT 24
Finished Jul 11 05:59:11 PM PDT 24
Peak memory 206468 kb
Host smart-0b690090-923a-4cf7-9859-67fe661859be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17454
84400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1745484400
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3725184384
Short name T712
Test name
Test status
Simulation time 5669481863 ps
CPU time 152.75 seconds
Started Jul 11 05:59:03 PM PDT 24
Finished Jul 11 06:01:45 PM PDT 24
Peak memory 206632 kb
Host smart-ae8b83d4-8f6d-4db5-b41f-9c161a28397e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37251
84384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3725184384
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1592991944
Short name T2302
Test name
Test status
Simulation time 4317478003 ps
CPU time 121.07 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206648 kb
Host smart-acb67167-3d92-470b-80c6-25f80756f945
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1592991944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1592991944
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2564822792
Short name T1281
Test name
Test status
Simulation time 158856405 ps
CPU time 0.8 seconds
Started Jul 11 05:59:07 PM PDT 24
Finished Jul 11 05:59:16 PM PDT 24
Peak memory 206420 kb
Host smart-e47303f6-e464-4569-98d3-86bfbf2a5132
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2564822792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2564822792
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2532908042
Short name T2536
Test name
Test status
Simulation time 143126479 ps
CPU time 0.8 seconds
Started Jul 11 05:58:54 PM PDT 24
Finished Jul 11 05:59:07 PM PDT 24
Peak memory 206400 kb
Host smart-1bb531e6-f520-4094-b361-1fcd0902edf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
08042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2532908042
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1047045067
Short name T151
Test name
Test status
Simulation time 197402417 ps
CPU time 0.85 seconds
Started Jul 11 05:59:04 PM PDT 24
Finished Jul 11 05:59:14 PM PDT 24
Peak memory 206360 kb
Host smart-767bb9d3-c908-419b-8a5a-3812ac2ffb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10470
45067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1047045067
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1865074831
Short name T579
Test name
Test status
Simulation time 177672895 ps
CPU time 0.91 seconds
Started Jul 11 05:59:10 PM PDT 24
Finished Jul 11 05:59:19 PM PDT 24
Peak memory 206376 kb
Host smart-a5fe91b8-d018-4271-92cf-28d06e918f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18650
74831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1865074831
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3985413472
Short name T1537
Test name
Test status
Simulation time 175012593 ps
CPU time 0.79 seconds
Started Jul 11 05:58:55 PM PDT 24
Finished Jul 11 05:59:07 PM PDT 24
Peak memory 206332 kb
Host smart-0c9428d7-0853-44fe-ba52-7cf9250a5798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39854
13472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3985413472
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.4210588218
Short name T1700
Test name
Test status
Simulation time 205352834 ps
CPU time 0.83 seconds
Started Jul 11 05:59:02 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 206272 kb
Host smart-6fa945bb-b056-4d81-80be-ccc12ccdfbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42105
88218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.4210588218
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1330800584
Short name T2056
Test name
Test status
Simulation time 222544984 ps
CPU time 0.85 seconds
Started Jul 11 05:58:56 PM PDT 24
Finished Jul 11 05:59:08 PM PDT 24
Peak memory 206372 kb
Host smart-22e8e302-c307-4559-a810-9b7d236111bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13308
00584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1330800584
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.674970245
Short name T2461
Test name
Test status
Simulation time 243274904 ps
CPU time 0.94 seconds
Started Jul 11 05:58:56 PM PDT 24
Finished Jul 11 05:59:08 PM PDT 24
Peak memory 206372 kb
Host smart-18e43c92-df87-45ee-9f59-614130d8b81a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=674970245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.674970245
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.119216515
Short name T1527
Test name
Test status
Simulation time 155308383 ps
CPU time 0.83 seconds
Started Jul 11 05:59:04 PM PDT 24
Finished Jul 11 05:59:14 PM PDT 24
Peak memory 206380 kb
Host smart-55f26bbb-5030-472a-b2b1-493330e7dd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11921
6515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.119216515
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2256080523
Short name T2444
Test name
Test status
Simulation time 63307364 ps
CPU time 0.68 seconds
Started Jul 11 05:59:08 PM PDT 24
Finished Jul 11 05:59:18 PM PDT 24
Peak memory 206368 kb
Host smart-7e599440-72b0-457e-ace4-fd4e2b713d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22560
80523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2256080523
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3370353154
Short name T1859
Test name
Test status
Simulation time 14755247863 ps
CPU time 31.91 seconds
Started Jul 11 05:59:04 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 214884 kb
Host smart-d508008d-25a4-43a3-82b9-7fcbaad09526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
53154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3370353154
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3651759003
Short name T1116
Test name
Test status
Simulation time 183246835 ps
CPU time 0.81 seconds
Started Jul 11 05:58:54 PM PDT 24
Finished Jul 11 05:59:06 PM PDT 24
Peak memory 206384 kb
Host smart-3518f522-37bf-4c4f-abb3-16a5ac756995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36517
59003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3651759003
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.604229316
Short name T52
Test name
Test status
Simulation time 229236843 ps
CPU time 0.93 seconds
Started Jul 11 05:58:58 PM PDT 24
Finished Jul 11 05:59:09 PM PDT 24
Peak memory 206392 kb
Host smart-05fe93c3-f0a5-4c43-bab1-76892ac28703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60422
9316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.604229316
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1935721839
Short name T2426
Test name
Test status
Simulation time 226287865 ps
CPU time 0.93 seconds
Started Jul 11 05:59:10 PM PDT 24
Finished Jul 11 05:59:20 PM PDT 24
Peak memory 206364 kb
Host smart-f17b0aac-f95d-47dc-9e49-689393795138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19357
21839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1935721839
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3270229930
Short name T324
Test name
Test status
Simulation time 204515155 ps
CPU time 0.86 seconds
Started Jul 11 05:59:08 PM PDT 24
Finished Jul 11 05:59:17 PM PDT 24
Peak memory 206392 kb
Host smart-19419cab-a6aa-4cc4-8f16-fac11108f131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
29930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3270229930
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1653502287
Short name T1443
Test name
Test status
Simulation time 167939623 ps
CPU time 0.82 seconds
Started Jul 11 05:59:07 PM PDT 24
Finished Jul 11 05:59:16 PM PDT 24
Peak memory 206384 kb
Host smart-3d19031e-c47d-42d1-93e4-4a087ae59ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16535
02287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1653502287
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3220981260
Short name T1940
Test name
Test status
Simulation time 168486046 ps
CPU time 0.79 seconds
Started Jul 11 05:59:02 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 206268 kb
Host smart-c63f5b70-54cf-4c3a-88c7-4a39332a98ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32209
81260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3220981260
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3121018383
Short name T732
Test name
Test status
Simulation time 164803800 ps
CPU time 0.84 seconds
Started Jul 11 05:59:06 PM PDT 24
Finished Jul 11 05:59:15 PM PDT 24
Peak memory 206400 kb
Host smart-43489d5f-b40b-458f-8297-143740d143c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
18383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3121018383
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2517536962
Short name T1449
Test name
Test status
Simulation time 206300253 ps
CPU time 0.9 seconds
Started Jul 11 05:59:02 PM PDT 24
Finished Jul 11 05:59:13 PM PDT 24
Peak memory 206400 kb
Host smart-b40a031c-613d-41d4-a244-012baae8fe89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25175
36962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2517536962
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.4022100732
Short name T646
Test name
Test status
Simulation time 4052171477 ps
CPU time 107.38 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 06:00:58 PM PDT 24
Peak memory 206652 kb
Host smart-f56d7467-d9e5-407f-92b3-fc4b9df88fde
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4022100732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.4022100732
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1192698123
Short name T1681
Test name
Test status
Simulation time 181395698 ps
CPU time 0.84 seconds
Started Jul 11 05:59:00 PM PDT 24
Finished Jul 11 05:59:11 PM PDT 24
Peak memory 206380 kb
Host smart-b58f29ac-b2fe-452a-9a78-4036bae9c40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11926
98123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1192698123
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2333827642
Short name T1482
Test name
Test status
Simulation time 211030701 ps
CPU time 0.86 seconds
Started Jul 11 05:59:04 PM PDT 24
Finished Jul 11 05:59:14 PM PDT 24
Peak memory 206296 kb
Host smart-7b9e71a4-2a75-4c0f-93f6-dd412ce9aa21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23338
27642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2333827642
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2352284698
Short name T2317
Test name
Test status
Simulation time 1210663526 ps
CPU time 2.6 seconds
Started Jul 11 05:59:08 PM PDT 24
Finished Jul 11 05:59:18 PM PDT 24
Peak memory 206624 kb
Host smart-fbb2b332-1b15-4402-95f4-ed1420c1ce41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23522
84698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2352284698
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.412961520
Short name T1179
Test name
Test status
Simulation time 6023029185 ps
CPU time 42.01 seconds
Started Jul 11 05:59:07 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206676 kb
Host smart-a7ea2d37-bcbc-42c3-a07b-0434f983516c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41296
1520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.412961520
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.497120185
Short name T195
Test name
Test status
Simulation time 54727179 ps
CPU time 0.68 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206388 kb
Host smart-28355220-03f9-498f-b867-127bac4d9c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=497120185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.497120185
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1070401813
Short name T1078
Test name
Test status
Simulation time 3913995576 ps
CPU time 4.66 seconds
Started Jul 11 05:59:00 PM PDT 24
Finished Jul 11 05:59:15 PM PDT 24
Peak memory 206376 kb
Host smart-aaa338ee-5840-4310-b2b4-840eaf650b86
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1070401813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1070401813
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1007188142
Short name T1822
Test name
Test status
Simulation time 13341050451 ps
CPU time 15.16 seconds
Started Jul 11 05:59:02 PM PDT 24
Finished Jul 11 05:59:27 PM PDT 24
Peak memory 206396 kb
Host smart-0f870556-ac64-4039-8807-3431c1560c97
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1007188142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1007188142
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.780733875
Short name T8
Test name
Test status
Simulation time 23352600290 ps
CPU time 22.39 seconds
Started Jul 11 05:59:02 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206452 kb
Host smart-84cd0c15-a467-4ccf-b7c5-f3a34f4183e7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=780733875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.780733875
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2422684271
Short name T1816
Test name
Test status
Simulation time 178385567 ps
CPU time 0.8 seconds
Started Jul 11 05:59:07 PM PDT 24
Finished Jul 11 05:59:17 PM PDT 24
Peak memory 206416 kb
Host smart-1cdb181a-e3ac-4bd5-aeff-5324bd9398d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24226
84271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2422684271
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1016090321
Short name T1373
Test name
Test status
Simulation time 145639145 ps
CPU time 0.77 seconds
Started Jul 11 05:59:09 PM PDT 24
Finished Jul 11 05:59:18 PM PDT 24
Peak memory 206344 kb
Host smart-33299212-6745-4ac6-9dd0-2eb17acdb82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10160
90321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1016090321
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.151560192
Short name T960
Test name
Test status
Simulation time 475673681 ps
CPU time 1.41 seconds
Started Jul 11 05:59:03 PM PDT 24
Finished Jul 11 05:59:14 PM PDT 24
Peak memory 206388 kb
Host smart-baa3c06d-63dd-4bb0-b227-78b0b69f4f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15156
0192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.151560192
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_device_address.4129644837
Short name T100
Test name
Test status
Simulation time 19223511710 ps
CPU time 36.47 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 05:59:47 PM PDT 24
Peak memory 206704 kb
Host smart-2eac9928-a25b-4da1-8034-83560dfa47fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41296
44837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.4129644837
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3781040015
Short name T1461
Test name
Test status
Simulation time 421614381 ps
CPU time 1.21 seconds
Started Jul 11 05:59:01 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 206280 kb
Host smart-0afefb2a-5c30-4770-9b8f-ed956ea09eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37810
40015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3781040015
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2836786702
Short name T1336
Test name
Test status
Simulation time 144883854 ps
CPU time 0.76 seconds
Started Jul 11 05:59:19 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206324 kb
Host smart-7ffb347c-6999-4f17-a066-216a94823734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28367
86702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2836786702
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2779119823
Short name T2048
Test name
Test status
Simulation time 47549180 ps
CPU time 0.68 seconds
Started Jul 11 05:59:17 PM PDT 24
Finished Jul 11 05:59:27 PM PDT 24
Peak memory 206372 kb
Host smart-cbc66b35-fc25-4464-b9cb-b22b56e23234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27791
19823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2779119823
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1655500919
Short name T1208
Test name
Test status
Simulation time 924366397 ps
CPU time 2.08 seconds
Started Jul 11 05:59:14 PM PDT 24
Finished Jul 11 05:59:25 PM PDT 24
Peak memory 206576 kb
Host smart-e37255ed-48fe-409e-a678-639e7aed7a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16555
00919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1655500919
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.666229063
Short name T1658
Test name
Test status
Simulation time 179968912 ps
CPU time 1.16 seconds
Started Jul 11 05:59:09 PM PDT 24
Finished Jul 11 05:59:20 PM PDT 24
Peak memory 206608 kb
Host smart-360b8a35-7ae3-4d0e-ada9-710e6e0b9470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66622
9063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.666229063
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3863736770
Short name T1248
Test name
Test status
Simulation time 226191542 ps
CPU time 0.88 seconds
Started Jul 11 05:59:16 PM PDT 24
Finished Jul 11 05:59:25 PM PDT 24
Peak memory 206328 kb
Host smart-128bfd06-1a8d-4cd7-92b5-6ad41097f630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38637
36770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3863736770
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2626153140
Short name T1378
Test name
Test status
Simulation time 155575329 ps
CPU time 0.78 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206204 kb
Host smart-dc858d15-3e40-40e9-81db-d6ef6563b130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26261
53140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2626153140
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.4134739750
Short name T1041
Test name
Test status
Simulation time 301031036 ps
CPU time 1.01 seconds
Started Jul 11 05:59:19 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206396 kb
Host smart-b3b02868-5211-427d-aba8-fcd0510f2fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41347
39750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4134739750
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.2483843001
Short name T2611
Test name
Test status
Simulation time 5717524839 ps
CPU time 160.72 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 06:02:08 PM PDT 24
Peak memory 206632 kb
Host smart-7fa26263-de02-4320-8dff-48589d0e8aca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2483843001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.2483843001
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.3735673903
Short name T2354
Test name
Test status
Simulation time 5523710762 ps
CPU time 17.15 seconds
Started Jul 11 05:59:13 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206664 kb
Host smart-972d6ee7-92ea-4df9-97f8-77d18851d090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37356
73903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.3735673903
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1640465113
Short name T571
Test name
Test status
Simulation time 188602110 ps
CPU time 0.81 seconds
Started Jul 11 05:59:14 PM PDT 24
Finished Jul 11 05:59:23 PM PDT 24
Peak memory 206304 kb
Host smart-58abd5c5-e859-4f1a-9534-e1a2a3d7c364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16404
65113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1640465113
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.3271534161
Short name T500
Test name
Test status
Simulation time 23302362184 ps
CPU time 22.81 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:50 PM PDT 24
Peak memory 206392 kb
Host smart-f4682850-32c6-4c5b-88fb-75308e5c1f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32715
34161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.3271534161
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.270957728
Short name T1339
Test name
Test status
Simulation time 3346786553 ps
CPU time 3.9 seconds
Started Jul 11 05:59:19 PM PDT 24
Finished Jul 11 05:59:31 PM PDT 24
Peak memory 206460 kb
Host smart-418547ab-621e-4f28-8003-33abb8411518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27095
7728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.270957728
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1337356050
Short name T166
Test name
Test status
Simulation time 6938984481 ps
CPU time 186.42 seconds
Started Jul 11 05:59:12 PM PDT 24
Finished Jul 11 06:02:28 PM PDT 24
Peak memory 206684 kb
Host smart-6624aee5-f29e-4418-8d62-7808f363b6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13373
56050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1337356050
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3781575280
Short name T1732
Test name
Test status
Simulation time 5557895085 ps
CPU time 147.35 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 06:02:00 PM PDT 24
Peak memory 206552 kb
Host smart-d009cc11-1a73-474a-891e-0beb6f32a9ca
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3781575280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3781575280
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2343286923
Short name T859
Test name
Test status
Simulation time 237694248 ps
CPU time 0.96 seconds
Started Jul 11 05:59:17 PM PDT 24
Finished Jul 11 05:59:27 PM PDT 24
Peak memory 206380 kb
Host smart-6fc3d51e-6f38-416e-9d0e-45e2c41c8c90
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2343286923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2343286923
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3199834907
Short name T499
Test name
Test status
Simulation time 190630867 ps
CPU time 0.85 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206388 kb
Host smart-870cf48c-180d-46e9-9671-e5e2efd30e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31998
34907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3199834907
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2384590747
Short name T399
Test name
Test status
Simulation time 6711096325 ps
CPU time 46.16 seconds
Started Jul 11 05:59:16 PM PDT 24
Finished Jul 11 06:00:11 PM PDT 24
Peak memory 206632 kb
Host smart-377a90bf-3e4f-47a4-8e60-7487fdcf17da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23845
90747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2384590747
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.571632752
Short name T677
Test name
Test status
Simulation time 7489254484 ps
CPU time 56.68 seconds
Started Jul 11 05:59:15 PM PDT 24
Finished Jul 11 06:00:21 PM PDT 24
Peak memory 206588 kb
Host smart-b2f62c25-a9f7-4755-8479-c36828d37144
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=571632752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.571632752
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1054330470
Short name T679
Test name
Test status
Simulation time 161555390 ps
CPU time 0.78 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206388 kb
Host smart-e55559bc-2841-423e-afbf-d89f006e1921
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1054330470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1054330470
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1277982371
Short name T2333
Test name
Test status
Simulation time 137183719 ps
CPU time 0.77 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206384 kb
Host smart-288bd625-5c4a-4c6f-8c4a-0837a942534f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12779
82371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1277982371
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3530557499
Short name T2550
Test name
Test status
Simulation time 186994162 ps
CPU time 0.87 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206324 kb
Host smart-dad5c4ec-7478-4956-a649-37de002a426e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35305
57499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3530557499
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1027339579
Short name T1521
Test name
Test status
Simulation time 193656215 ps
CPU time 0.87 seconds
Started Jul 11 05:59:14 PM PDT 24
Finished Jul 11 05:59:25 PM PDT 24
Peak memory 206392 kb
Host smart-895469d0-42ae-4312-b7fe-2b956e269384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10273
39579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1027339579
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.4016800919
Short name T330
Test name
Test status
Simulation time 140340467 ps
CPU time 0.77 seconds
Started Jul 11 05:59:12 PM PDT 24
Finished Jul 11 05:59:22 PM PDT 24
Peak memory 206400 kb
Host smart-ec530009-6788-474f-9501-595eaaf3eadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40168
00919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.4016800919
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1445790431
Short name T1256
Test name
Test status
Simulation time 203048271 ps
CPU time 0.91 seconds
Started Jul 11 05:59:12 PM PDT 24
Finished Jul 11 05:59:22 PM PDT 24
Peak memory 206268 kb
Host smart-4114097f-2b5d-469d-9052-26556e9f4ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14457
90431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1445790431
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.59099294
Short name T2469
Test name
Test status
Simulation time 196791206 ps
CPU time 0.82 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206392 kb
Host smart-b3a41e02-ed4c-44e9-ac3b-2e51fcb9cab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59099
294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.59099294
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.2769653389
Short name T1838
Test name
Test status
Simulation time 221319248 ps
CPU time 0.89 seconds
Started Jul 11 05:59:13 PM PDT 24
Finished Jul 11 05:59:23 PM PDT 24
Peak memory 206372 kb
Host smart-0cddd505-dfb5-4b97-8112-74924a51a007
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2769653389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.2769653389
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1921502893
Short name T1226
Test name
Test status
Simulation time 146097712 ps
CPU time 0.82 seconds
Started Jul 11 05:59:13 PM PDT 24
Finished Jul 11 05:59:23 PM PDT 24
Peak memory 206384 kb
Host smart-665ef1b0-50ff-40b1-a1a0-00ea0e65d699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
02893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1921502893
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1565046365
Short name T1708
Test name
Test status
Simulation time 50133989 ps
CPU time 0.66 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206336 kb
Host smart-9d9b13db-4d4c-42e1-8ae0-4d3883dd28c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15650
46365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1565046365
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.427035987
Short name T896
Test name
Test status
Simulation time 10130429949 ps
CPU time 24.1 seconds
Started Jul 11 05:59:15 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206668 kb
Host smart-b77a197b-818c-47b2-b85b-bf97025ac95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42703
5987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.427035987
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1272214197
Short name T2741
Test name
Test status
Simulation time 183140110 ps
CPU time 0.84 seconds
Started Jul 11 05:59:16 PM PDT 24
Finished Jul 11 05:59:26 PM PDT 24
Peak memory 206388 kb
Host smart-c3f59589-46d8-468e-a462-9e693bc065d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12722
14197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1272214197
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.239527253
Short name T873
Test name
Test status
Simulation time 254653651 ps
CPU time 1 seconds
Started Jul 11 05:59:14 PM PDT 24
Finished Jul 11 05:59:24 PM PDT 24
Peak memory 206328 kb
Host smart-fc59b97c-2d0f-4335-83b1-1eb68e124819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952
7253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.239527253
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3448465869
Short name T2638
Test name
Test status
Simulation time 224466124 ps
CPU time 0.84 seconds
Started Jul 11 05:59:17 PM PDT 24
Finished Jul 11 05:59:27 PM PDT 24
Peak memory 206328 kb
Host smart-cd53e970-dadf-4eb3-9046-3cdaa10d2c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34484
65869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3448465869
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1852536010
Short name T1927
Test name
Test status
Simulation time 201290187 ps
CPU time 0.92 seconds
Started Jul 11 05:59:20 PM PDT 24
Finished Jul 11 05:59:30 PM PDT 24
Peak memory 206408 kb
Host smart-1fa2bef9-f1f1-441d-8149-c04bf1f95459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18525
36010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1852536010
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2006434722
Short name T654
Test name
Test status
Simulation time 135819567 ps
CPU time 0.76 seconds
Started Jul 11 05:59:15 PM PDT 24
Finished Jul 11 05:59:25 PM PDT 24
Peak memory 206256 kb
Host smart-4f681ac6-5683-47be-8e31-aecae45c4891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20064
34722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2006434722
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1521487866
Short name T2447
Test name
Test status
Simulation time 179116654 ps
CPU time 0.82 seconds
Started Jul 11 05:59:23 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206308 kb
Host smart-d3d9b850-ad9d-4f66-a47a-15a3f05635cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15214
87866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1521487866
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1273209669
Short name T385
Test name
Test status
Simulation time 161770698 ps
CPU time 0.78 seconds
Started Jul 11 05:59:16 PM PDT 24
Finished Jul 11 05:59:26 PM PDT 24
Peak memory 206356 kb
Host smart-05428ffb-87fa-4217-a574-975dbf4ae449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
09669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1273209669
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1937776717
Short name T1851
Test name
Test status
Simulation time 199643891 ps
CPU time 0.89 seconds
Started Jul 11 05:59:17 PM PDT 24
Finished Jul 11 05:59:27 PM PDT 24
Peak memory 206380 kb
Host smart-3a33fabb-7157-4b67-a77a-40e83b1e4973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19377
76717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1937776717
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3661913213
Short name T726
Test name
Test status
Simulation time 4059727252 ps
CPU time 30.37 seconds
Started Jul 11 05:59:16 PM PDT 24
Finished Jul 11 05:59:55 PM PDT 24
Peak memory 206584 kb
Host smart-75116445-2f7e-418b-8c87-0c4891d5b30f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3661913213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3661913213
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3506354007
Short name T2025
Test name
Test status
Simulation time 137884846 ps
CPU time 0.75 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206304 kb
Host smart-ce735456-c7bc-423b-9fc9-2a9ee559a395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35063
54007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3506354007
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1629346415
Short name T2652
Test name
Test status
Simulation time 138011270 ps
CPU time 0.77 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206248 kb
Host smart-94f7544c-4519-46ca-bdad-04188584644f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16293
46415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1629346415
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.1116747662
Short name T2683
Test name
Test status
Simulation time 329486026 ps
CPU time 1.07 seconds
Started Jul 11 05:59:14 PM PDT 24
Finished Jul 11 05:59:24 PM PDT 24
Peak memory 206400 kb
Host smart-9c0869af-c9d2-4de8-ae38-4bee9b23a3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11167
47662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1116747662
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.4006740652
Short name T2221
Test name
Test status
Simulation time 4788656391 ps
CPU time 124.6 seconds
Started Jul 11 05:59:15 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206644 kb
Host smart-717bc38a-d37d-4beb-8875-8278dcab5c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40067
40652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.4006740652
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.568987576
Short name T199
Test name
Test status
Simulation time 43133681 ps
CPU time 0.64 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206420 kb
Host smart-74ded755-a746-40b1-b94c-3a19af8ee93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=568987576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.568987576
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1520067609
Short name T1096
Test name
Test status
Simulation time 3504298729 ps
CPU time 4.58 seconds
Started Jul 11 05:59:15 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206648 kb
Host smart-c5dc736c-7093-4e03-bb09-c4985160759f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1520067609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1520067609
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.4070011154
Short name T1804
Test name
Test status
Simulation time 13292834792 ps
CPU time 12.42 seconds
Started Jul 11 05:59:11 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206692 kb
Host smart-30510837-91cc-4e3e-a4ef-e103151e15db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4070011154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.4070011154
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2453045338
Short name T16
Test name
Test status
Simulation time 23347899911 ps
CPU time 22.88 seconds
Started Jul 11 05:59:19 PM PDT 24
Finished Jul 11 05:59:50 PM PDT 24
Peak memory 206636 kb
Host smart-2a364176-0fa9-4d95-b46a-cfb0d03b6fa3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2453045338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2453045338
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1369276860
Short name T1317
Test name
Test status
Simulation time 155531921 ps
CPU time 0.8 seconds
Started Jul 11 05:59:17 PM PDT 24
Finished Jul 11 05:59:27 PM PDT 24
Peak memory 206352 kb
Host smart-687c49cd-3a6b-41ef-b9b6-55758cc16420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13692
76860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1369276860
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.895126266
Short name T1408
Test name
Test status
Simulation time 201990373 ps
CPU time 0.82 seconds
Started Jul 11 05:59:19 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206404 kb
Host smart-d757b884-7ccb-4180-b3e2-4ac5752a8ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89512
6266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.895126266
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.2346389845
Short name T2579
Test name
Test status
Simulation time 532142821 ps
CPU time 1.53 seconds
Started Jul 11 05:59:15 PM PDT 24
Finished Jul 11 05:59:25 PM PDT 24
Peak memory 206580 kb
Host smart-565abc93-4bbe-4951-a630-84a05295da2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23463
89845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.2346389845
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2726002401
Short name T1034
Test name
Test status
Simulation time 1195557288 ps
CPU time 2.58 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206620 kb
Host smart-8857091b-53ff-4878-8ffc-3a8df5f528fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27260
02401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2726002401
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1696161404
Short name T113
Test name
Test status
Simulation time 11710813581 ps
CPU time 20.51 seconds
Started Jul 11 05:59:13 PM PDT 24
Finished Jul 11 05:59:43 PM PDT 24
Peak memory 206712 kb
Host smart-e345bf2a-2a68-407f-ab7d-9c739aa4d288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16961
61404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1696161404
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.2081349241
Short name T459
Test name
Test status
Simulation time 376047954 ps
CPU time 1.25 seconds
Started Jul 11 05:59:25 PM PDT 24
Finished Jul 11 05:59:36 PM PDT 24
Peak memory 206336 kb
Host smart-09d6d0b9-9eee-49f6-bbc4-a2885b403183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20813
49241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.2081349241
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.4131701133
Short name T2255
Test name
Test status
Simulation time 142169093 ps
CPU time 0.85 seconds
Started Jul 11 05:59:23 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206368 kb
Host smart-a5ca2ca8-879b-4daa-8cd6-251e2981507f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41317
01133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.4131701133
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.692770279
Short name T457
Test name
Test status
Simulation time 69972992 ps
CPU time 0.65 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206360 kb
Host smart-b57bb814-e244-4549-b680-218b98fdc559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69277
0279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.692770279
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3383076699
Short name T257
Test name
Test status
Simulation time 966313276 ps
CPU time 2.13 seconds
Started Jul 11 05:59:22 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206656 kb
Host smart-444950c8-23f3-4c81-8ea4-e945000f901a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33830
76699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3383076699
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.527638902
Short name T754
Test name
Test status
Simulation time 152531107 ps
CPU time 1.15 seconds
Started Jul 11 05:59:23 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206560 kb
Host smart-7f1310c6-259c-4944-b1e0-c2ec9ce8fc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52763
8902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.527638902
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3221370248
Short name T714
Test name
Test status
Simulation time 197685854 ps
CPU time 0.96 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 05:59:37 PM PDT 24
Peak memory 206340 kb
Host smart-43020b5a-a8d4-41ce-a9c5-7ec00bd3ccbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32213
70248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3221370248
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3384382436
Short name T1171
Test name
Test status
Simulation time 158783130 ps
CPU time 0.84 seconds
Started Jul 11 05:59:21 PM PDT 24
Finished Jul 11 05:59:32 PM PDT 24
Peak memory 206384 kb
Host smart-36a3bcdc-43ff-4b04-99b6-d55098081f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33843
82436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3384382436
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2080652424
Short name T1508
Test name
Test status
Simulation time 210036848 ps
CPU time 0.87 seconds
Started Jul 11 05:59:20 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206368 kb
Host smart-8e586791-66b5-4a90-99ce-2629e0efc555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806
52424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2080652424
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.2724017642
Short name T2682
Test name
Test status
Simulation time 7540999741 ps
CPU time 56.03 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206688 kb
Host smart-f7c7b3bf-9715-49c0-9c5f-6674d81b5097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27240
17642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.2724017642
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.81359416
Short name T109
Test name
Test status
Simulation time 229874533 ps
CPU time 0.84 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206364 kb
Host smart-2af969ce-226c-4f15-a58f-8cbd4a5691ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81359
416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.81359416
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.405863066
Short name T936
Test name
Test status
Simulation time 23262019305 ps
CPU time 22.28 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206184 kb
Host smart-4d17251c-148f-4a7a-94a4-68581306290a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40586
3066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.405863066
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.417344783
Short name T357
Test name
Test status
Simulation time 3341117675 ps
CPU time 4.4 seconds
Started Jul 11 05:59:22 PM PDT 24
Finished Jul 11 05:59:36 PM PDT 24
Peak memory 206452 kb
Host smart-23e6ce84-7332-4a35-b3b3-eadf3824ae39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
4783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.417344783
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3145006430
Short name T1614
Test name
Test status
Simulation time 11024799323 ps
CPU time 306.02 seconds
Started Jul 11 05:59:19 PM PDT 24
Finished Jul 11 06:04:34 PM PDT 24
Peak memory 206656 kb
Host smart-66a11ea7-990f-4024-9e6a-1f4b12a84938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31450
06430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3145006430
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3926809873
Short name T2284
Test name
Test status
Simulation time 6622453635 ps
CPU time 60.21 seconds
Started Jul 11 05:59:21 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 206580 kb
Host smart-563edffe-0f18-406d-ae07-d8d914b1e33a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3926809873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3926809873
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.872146950
Short name T414
Test name
Test status
Simulation time 234870200 ps
CPU time 0.92 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 05:59:37 PM PDT 24
Peak memory 206400 kb
Host smart-38098965-7d4a-4087-b7ec-afe446379985
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=872146950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.872146950
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2124087857
Short name T87
Test name
Test status
Simulation time 219369854 ps
CPU time 0.85 seconds
Started Jul 11 05:59:36 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 206388 kb
Host smart-f322443f-10c5-4f1a-8089-dbcbbf53faba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21240
87857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2124087857
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2985575416
Short name T1766
Test name
Test status
Simulation time 4582156832 ps
CPU time 128.04 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 06:01:56 PM PDT 24
Peak memory 206652 kb
Host smart-496b8349-dcaa-4711-bd7a-79caff9cac9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29855
75416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2985575416
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3333111617
Short name T415
Test name
Test status
Simulation time 4719484571 ps
CPU time 125.01 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 06:01:38 PM PDT 24
Peak memory 206572 kb
Host smart-55c2ea22-7706-469f-bc2f-291cd9ec7d00
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3333111617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3333111617
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.891819959
Short name T582
Test name
Test status
Simulation time 171499002 ps
CPU time 0.8 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206380 kb
Host smart-c587e66f-ab32-4af0-8dd9-249fa8397ab8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=891819959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.891819959
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2467730749
Short name T1852
Test name
Test status
Simulation time 143487572 ps
CPU time 0.76 seconds
Started Jul 11 05:59:23 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206300 kb
Host smart-270e62ae-2a29-4233-bf22-a07459de181a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
30749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2467730749
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2676312658
Short name T2705
Test name
Test status
Simulation time 191038906 ps
CPU time 0.87 seconds
Started Jul 11 05:59:22 PM PDT 24
Finished Jul 11 05:59:32 PM PDT 24
Peak memory 206388 kb
Host smart-0b6216eb-31fd-4f2d-bb53-3ce41bda7810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26763
12658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2676312658
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3571510749
Short name T1136
Test name
Test status
Simulation time 184051644 ps
CPU time 0.84 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:46 PM PDT 24
Peak memory 206396 kb
Host smart-7249ef08-b11b-462c-a703-8150af0cf0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35715
10749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3571510749
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2166688836
Short name T2115
Test name
Test status
Simulation time 201084173 ps
CPU time 0.79 seconds
Started Jul 11 05:59:25 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 206376 kb
Host smart-fd19c18c-fe84-4c65-ade8-c846522201f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21666
88836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2166688836
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1924270365
Short name T2167
Test name
Test status
Simulation time 214302371 ps
CPU time 0.87 seconds
Started Jul 11 05:59:19 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206392 kb
Host smart-c9f2449a-9e1a-4078-bfdd-d2b1789c3736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19242
70365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1924270365
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2270253686
Short name T1332
Test name
Test status
Simulation time 154759401 ps
CPU time 0.76 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 206332 kb
Host smart-5f63ab6c-20d0-431b-b7e6-cc718470b6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22702
53686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2270253686
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1018897645
Short name T1825
Test name
Test status
Simulation time 215643044 ps
CPU time 0.94 seconds
Started Jul 11 05:59:27 PM PDT 24
Finished Jul 11 05:59:38 PM PDT 24
Peak memory 206344 kb
Host smart-e7390e7c-1379-4335-b057-9055837091d0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1018897645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1018897645
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2490053970
Short name T1900
Test name
Test status
Simulation time 150923623 ps
CPU time 0.75 seconds
Started Jul 11 05:59:32 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 205676 kb
Host smart-0c9a36e5-ce27-41a6-b9d5-710377d034b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24900
53970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2490053970
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3952436984
Short name T1531
Test name
Test status
Simulation time 33772823 ps
CPU time 0.63 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206372 kb
Host smart-653430a1-ec47-4556-bc33-a47838a57ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39524
36984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3952436984
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.4265551644
Short name T263
Test name
Test status
Simulation time 24098633691 ps
CPU time 57.37 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 06:00:34 PM PDT 24
Peak memory 206760 kb
Host smart-0f1f0402-ceb1-4ee7-8e38-926b670d36da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
51644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.4265551644
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.834312682
Short name T2017
Test name
Test status
Simulation time 164616969 ps
CPU time 0.81 seconds
Started Jul 11 05:59:25 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 206368 kb
Host smart-dd9cdfe9-dec4-4c74-98cb-a6a90b1e9151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83431
2682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.834312682
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.290741418
Short name T563
Test name
Test status
Simulation time 234841854 ps
CPU time 0.87 seconds
Started Jul 11 05:59:20 PM PDT 24
Finished Jul 11 05:59:30 PM PDT 24
Peak memory 206464 kb
Host smart-1e0f24af-d2fa-430d-9c8a-e297f9a675b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29074
1418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.290741418
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.703167434
Short name T824
Test name
Test status
Simulation time 290831383 ps
CPU time 0.92 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206380 kb
Host smart-8215dc05-bdee-4804-a5e3-a61f1c1644c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70316
7434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.703167434
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1536094601
Short name T1976
Test name
Test status
Simulation time 171427827 ps
CPU time 0.81 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:46 PM PDT 24
Peak memory 206388 kb
Host smart-3683a5e3-2981-480f-99dc-2c440d5d30c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15360
94601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1536094601
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.407064242
Short name T448
Test name
Test status
Simulation time 155670005 ps
CPU time 0.81 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 05:59:37 PM PDT 24
Peak memory 206404 kb
Host smart-6717bfea-50eb-4137-bf5a-8fb5953e6eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40706
4242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.407064242
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.286699477
Short name T463
Test name
Test status
Simulation time 156759769 ps
CPU time 0.76 seconds
Started Jul 11 05:59:30 PM PDT 24
Finished Jul 11 05:59:42 PM PDT 24
Peak memory 206312 kb
Host smart-57d45611-56fe-456b-bf49-e4adb9cf4233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669
9477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.286699477
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.237184409
Short name T1588
Test name
Test status
Simulation time 163244844 ps
CPU time 0.8 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 206384 kb
Host smart-0343c669-073c-4a0f-a172-f6d68063d90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23718
4409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.237184409
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2732004133
Short name T1043
Test name
Test status
Simulation time 196976300 ps
CPU time 0.86 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206132 kb
Host smart-cdfd1401-1629-44f4-9ca8-b8f792eb82ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27320
04133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2732004133
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2800854128
Short name T2075
Test name
Test status
Simulation time 5778064969 ps
CPU time 41.26 seconds
Started Jul 11 05:59:27 PM PDT 24
Finished Jul 11 06:00:18 PM PDT 24
Peak memory 206552 kb
Host smart-811b9e2d-4ac0-40ca-922a-c214adb5a85e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2800854128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2800854128
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2264486460
Short name T1919
Test name
Test status
Simulation time 193965071 ps
CPU time 0.84 seconds
Started Jul 11 05:59:21 PM PDT 24
Finished Jul 11 05:59:31 PM PDT 24
Peak memory 206408 kb
Host smart-e3e7968d-c04c-42b9-8bcc-ae55fbdbc64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22644
86460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2264486460
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.4225908715
Short name T666
Test name
Test status
Simulation time 203947241 ps
CPU time 0.86 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206304 kb
Host smart-139673ae-64d8-4ef8-a529-ab0429a18ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259
08715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.4225908715
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1196062232
Short name T2118
Test name
Test status
Simulation time 941824159 ps
CPU time 2.07 seconds
Started Jul 11 05:59:22 PM PDT 24
Finished Jul 11 05:59:33 PM PDT 24
Peak memory 206584 kb
Host smart-ede64e97-7fb1-4fc2-b0d9-a77e2b00fd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11960
62232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1196062232
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1923722146
Short name T171
Test name
Test status
Simulation time 4886942365 ps
CPU time 131.64 seconds
Started Jul 11 05:59:22 PM PDT 24
Finished Jul 11 06:01:43 PM PDT 24
Peak memory 206552 kb
Host smart-0a5066d9-6fdf-4080-8330-6ac6ec6d0197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19237
22146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1923722146
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2321973072
Short name T516
Test name
Test status
Simulation time 35522230 ps
CPU time 0.68 seconds
Started Jul 11 05:54:37 PM PDT 24
Finished Jul 11 05:54:39 PM PDT 24
Peak memory 206380 kb
Host smart-67c36465-bc40-4fb3-9095-4d7171f929aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2321973072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2321973072
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.789528965
Short name T10
Test name
Test status
Simulation time 3829505200 ps
CPU time 4.2 seconds
Started Jul 11 05:54:18 PM PDT 24
Finished Jul 11 05:54:23 PM PDT 24
Peak memory 206408 kb
Host smart-10e1d543-0680-4715-8159-0f85b9e2e0e5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=789528965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.789528965
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3081825140
Short name T2290
Test name
Test status
Simulation time 13333177513 ps
CPU time 11.41 seconds
Started Jul 11 05:54:20 PM PDT 24
Finished Jul 11 05:54:32 PM PDT 24
Peak memory 206560 kb
Host smart-25f9fdcb-3a44-44bb-a800-6ee39ae6f2e8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3081825140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3081825140
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.762348862
Short name T1724
Test name
Test status
Simulation time 23435685968 ps
CPU time 24.47 seconds
Started Jul 11 05:54:28 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 206348 kb
Host smart-01a40629-9257-47ad-89ac-feaf64a1b817
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=762348862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.762348862
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1983400090
Short name T952
Test name
Test status
Simulation time 151899298 ps
CPU time 0.78 seconds
Started Jul 11 05:54:27 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 206304 kb
Host smart-cf66074a-e894-49ff-9884-f4212ddc2d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19834
00090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1983400090
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3771236236
Short name T56
Test name
Test status
Simulation time 193692300 ps
CPU time 0.81 seconds
Started Jul 11 05:54:19 PM PDT 24
Finished Jul 11 05:54:21 PM PDT 24
Peak memory 206404 kb
Host smart-f4d1ddb9-c39c-43f1-984b-0d17491201b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37712
36236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3771236236
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3524074740
Short name T2375
Test name
Test status
Simulation time 158394123 ps
CPU time 0.81 seconds
Started Jul 11 05:54:23 PM PDT 24
Finished Jul 11 05:54:25 PM PDT 24
Peak memory 206304 kb
Host smart-12f085e4-856e-462b-81b3-4ddecc006b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35240
74740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3524074740
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.591283115
Short name T1097
Test name
Test status
Simulation time 231111711 ps
CPU time 0.9 seconds
Started Jul 11 05:54:17 PM PDT 24
Finished Jul 11 05:54:19 PM PDT 24
Peak memory 206408 kb
Host smart-9448f4d7-a82b-4759-800f-20f88eda079d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59128
3115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.591283115
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1754951588
Short name T2057
Test name
Test status
Simulation time 914918297 ps
CPU time 2.07 seconds
Started Jul 11 05:54:17 PM PDT 24
Finished Jul 11 05:54:21 PM PDT 24
Peak memory 206596 kb
Host smart-d6bd4b7d-051f-4f80-aa1e-49dcc065cfd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17549
51588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1754951588
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3493832259
Short name T185
Test name
Test status
Simulation time 12617504881 ps
CPU time 21.91 seconds
Started Jul 11 05:54:21 PM PDT 24
Finished Jul 11 05:54:44 PM PDT 24
Peak memory 206556 kb
Host smart-82e1a7f0-c8c6-430b-a948-20c4c713abce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34938
32259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3493832259
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.3096757772
Short name T1380
Test name
Test status
Simulation time 149127993 ps
CPU time 0.78 seconds
Started Jul 11 05:54:27 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 206304 kb
Host smart-8a38469c-e04f-4593-a418-1372f20f04c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30967
57772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.3096757772
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3172566267
Short name T2050
Test name
Test status
Simulation time 513796696 ps
CPU time 1.46 seconds
Started Jul 11 05:54:24 PM PDT 24
Finished Jul 11 05:54:26 PM PDT 24
Peak memory 206388 kb
Host smart-0e45aaa0-cfbf-4d70-ad1a-c3b499e47987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31725
66267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3172566267
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1926982629
Short name T693
Test name
Test status
Simulation time 151335653 ps
CPU time 0.75 seconds
Started Jul 11 05:54:30 PM PDT 24
Finished Jul 11 05:54:32 PM PDT 24
Peak memory 206340 kb
Host smart-241caef0-afe3-43d1-93df-547cc2e0f319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19269
82629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1926982629
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2311353581
Short name T864
Test name
Test status
Simulation time 46718878 ps
CPU time 0.66 seconds
Started Jul 11 05:54:26 PM PDT 24
Finished Jul 11 05:54:28 PM PDT 24
Peak memory 206376 kb
Host smart-8f628e6f-f585-4ff3-9cdc-544729746548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
53581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2311353581
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2647186357
Short name T1834
Test name
Test status
Simulation time 754247389 ps
CPU time 1.95 seconds
Started Jul 11 05:54:24 PM PDT 24
Finished Jul 11 05:54:27 PM PDT 24
Peak memory 206584 kb
Host smart-a95c7315-c40f-414d-b721-59878632e040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26471
86357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2647186357
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.448653212
Short name T935
Test name
Test status
Simulation time 190035157 ps
CPU time 1.34 seconds
Started Jul 11 05:54:23 PM PDT 24
Finished Jul 11 05:54:26 PM PDT 24
Peak memory 206596 kb
Host smart-63838a4f-a060-4151-aeee-cf7d793dbe21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44865
3212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.448653212
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.249737559
Short name T801
Test name
Test status
Simulation time 103193635192 ps
CPU time 138.47 seconds
Started Jul 11 05:54:24 PM PDT 24
Finished Jul 11 05:56:44 PM PDT 24
Peak memory 206696 kb
Host smart-11b55610-4066-47cf-8089-c84a91bbfdf3
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=249737559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.249737559
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.1565727684
Short name T1533
Test name
Test status
Simulation time 99199730928 ps
CPU time 137.47 seconds
Started Jul 11 05:54:30 PM PDT 24
Finished Jul 11 05:56:50 PM PDT 24
Peak memory 206648 kb
Host smart-31bdc881-454f-40d4-a510-fc847fb13cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565727684 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.1565727684
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.2367056663
Short name T43
Test name
Test status
Simulation time 111094339053 ps
CPU time 156.97 seconds
Started Jul 11 05:54:27 PM PDT 24
Finished Jul 11 05:57:05 PM PDT 24
Peak memory 206628 kb
Host smart-293f55d9-add8-4d64-9b04-5aacc3d2ec3f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2367056663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2367056663
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.4006133154
Short name T323
Test name
Test status
Simulation time 97311043953 ps
CPU time 122.24 seconds
Started Jul 11 05:54:24 PM PDT 24
Finished Jul 11 05:56:27 PM PDT 24
Peak memory 206568 kb
Host smart-beec8f79-ec55-4ad8-b9d6-61cdf89fddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006133154 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.4006133154
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.1379137242
Short name T1981
Test name
Test status
Simulation time 102124868974 ps
CPU time 142.91 seconds
Started Jul 11 05:54:23 PM PDT 24
Finished Jul 11 05:56:47 PM PDT 24
Peak memory 206672 kb
Host smart-104567b8-dd02-49c1-9db7-1325d4337ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13791
37242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.1379137242
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.448002388
Short name T2084
Test name
Test status
Simulation time 231381340 ps
CPU time 0.86 seconds
Started Jul 11 05:54:27 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 206384 kb
Host smart-18c883c4-753f-40ca-a38f-2b01e508d3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44800
2388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.448002388
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.93146519
Short name T1718
Test name
Test status
Simulation time 203274783 ps
CPU time 0.8 seconds
Started Jul 11 05:54:25 PM PDT 24
Finished Jul 11 05:54:27 PM PDT 24
Peak memory 206384 kb
Host smart-58a4a4c5-d445-4b1b-9481-016f31ce4535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93146
519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.93146519
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2113927820
Short name T1126
Test name
Test status
Simulation time 238501604 ps
CPU time 0.88 seconds
Started Jul 11 05:54:29 PM PDT 24
Finished Jul 11 05:54:31 PM PDT 24
Peak memory 206388 kb
Host smart-1c33d853-7394-4c4b-95a0-446b05186b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21139
27820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2113927820
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.821319921
Short name T1144
Test name
Test status
Simulation time 225736557 ps
CPU time 0.88 seconds
Started Jul 11 05:54:22 PM PDT 24
Finished Jul 11 05:54:24 PM PDT 24
Peak memory 206532 kb
Host smart-ae28ed48-de3d-4946-aaa5-ee6fa803bab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82131
9921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.821319921
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3787319016
Short name T1889
Test name
Test status
Simulation time 23375086596 ps
CPU time 24.49 seconds
Started Jul 11 05:54:21 PM PDT 24
Finished Jul 11 05:54:46 PM PDT 24
Peak memory 206456 kb
Host smart-9b1b65f9-f26e-4d87-8fd9-79db64cd126f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37873
19016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3787319016
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1124518705
Short name T319
Test name
Test status
Simulation time 3302464023 ps
CPU time 3.7 seconds
Started Jul 11 05:54:22 PM PDT 24
Finished Jul 11 05:54:26 PM PDT 24
Peak memory 206452 kb
Host smart-b57e3420-11cf-45f8-8eef-1237b965c86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11245
18705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1124518705
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.244568775
Short name T2716
Test name
Test status
Simulation time 12914457899 ps
CPU time 97.34 seconds
Started Jul 11 05:54:29 PM PDT 24
Finished Jul 11 05:56:08 PM PDT 24
Peak memory 206732 kb
Host smart-17763861-ccae-4d39-855c-8e8a19c23b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24456
8775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.244568775
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2470533546
Short name T1315
Test name
Test status
Simulation time 3431407391 ps
CPU time 25.26 seconds
Started Jul 11 05:54:29 PM PDT 24
Finished Jul 11 05:54:56 PM PDT 24
Peak memory 206644 kb
Host smart-4d09f8a1-302d-42f6-9361-a8b388da6d70
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2470533546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2470533546
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3664342579
Short name T1438
Test name
Test status
Simulation time 265971555 ps
CPU time 0.9 seconds
Started Jul 11 05:54:28 PM PDT 24
Finished Jul 11 05:54:31 PM PDT 24
Peak memory 206544 kb
Host smart-1aa47d06-5e95-4701-bde9-7efcdc05314f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3664342579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3664342579
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.67701903
Short name T1187
Test name
Test status
Simulation time 240198704 ps
CPU time 0.88 seconds
Started Jul 11 05:54:28 PM PDT 24
Finished Jul 11 05:54:31 PM PDT 24
Peak memory 206368 kb
Host smart-47082d10-8971-419b-8f1c-a4f589bbb532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67701
903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.67701903
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2754396033
Short name T1820
Test name
Test status
Simulation time 4751245597 ps
CPU time 32.31 seconds
Started Jul 11 05:54:31 PM PDT 24
Finished Jul 11 05:55:06 PM PDT 24
Peak memory 206604 kb
Host smart-2c17e9be-d157-42c3-a2a9-5e5e18b328e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27543
96033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2754396033
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3170490678
Short name T1575
Test name
Test status
Simulation time 4013869955 ps
CPU time 114.88 seconds
Started Jul 11 05:54:31 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 206648 kb
Host smart-e98852fa-5313-495b-af55-bdf0e2a49143
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3170490678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3170490678
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3145027617
Short name T1343
Test name
Test status
Simulation time 161042566 ps
CPU time 0.78 seconds
Started Jul 11 05:54:30 PM PDT 24
Finished Jul 11 05:54:34 PM PDT 24
Peak memory 206356 kb
Host smart-a1221980-2dde-480d-902a-10464ffb475a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3145027617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3145027617
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2366408097
Short name T2110
Test name
Test status
Simulation time 160840273 ps
CPU time 0.77 seconds
Started Jul 11 05:54:31 PM PDT 24
Finished Jul 11 05:54:34 PM PDT 24
Peak memory 206360 kb
Host smart-38e4745d-a320-4749-bd78-72f56954358a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23664
08097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2366408097
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.4125026422
Short name T1367
Test name
Test status
Simulation time 209276326 ps
CPU time 0.84 seconds
Started Jul 11 05:54:32 PM PDT 24
Finished Jul 11 05:54:35 PM PDT 24
Peak memory 206340 kb
Host smart-e37c79c2-fe21-4ada-9d58-f04d158ffb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41250
26422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.4125026422
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.642049027
Short name T1066
Test name
Test status
Simulation time 187124947 ps
CPU time 0.83 seconds
Started Jul 11 05:54:31 PM PDT 24
Finished Jul 11 05:54:34 PM PDT 24
Peak memory 206384 kb
Host smart-7d6b4e1e-5235-454f-a785-6b2d50c816c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64204
9027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.642049027
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2244487978
Short name T1224
Test name
Test status
Simulation time 202445401 ps
CPU time 0.86 seconds
Started Jul 11 05:54:32 PM PDT 24
Finished Jul 11 05:54:36 PM PDT 24
Peak memory 206400 kb
Host smart-aa07166e-b1e0-422b-9347-b5b662969577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22444
87978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2244487978
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1222494509
Short name T391
Test name
Test status
Simulation time 255148738 ps
CPU time 0.94 seconds
Started Jul 11 05:54:28 PM PDT 24
Finished Jul 11 05:54:31 PM PDT 24
Peak memory 206332 kb
Host smart-85a1b20d-f96d-4f16-a52a-843d2a2360df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12224
94509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1222494509
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.28410915
Short name T2181
Test name
Test status
Simulation time 152378332 ps
CPU time 0.78 seconds
Started Jul 11 05:54:29 PM PDT 24
Finished Jul 11 05:54:32 PM PDT 24
Peak memory 206388 kb
Host smart-cf71bbc0-541c-4f3e-a0bd-ddb5accd4cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28410
915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.28410915
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.1480344892
Short name T460
Test name
Test status
Simulation time 247302069 ps
CPU time 0.91 seconds
Started Jul 11 05:54:30 PM PDT 24
Finished Jul 11 05:54:33 PM PDT 24
Peak memory 206360 kb
Host smart-f09d2463-ba7d-4de7-8187-edd69b75ed84
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1480344892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.1480344892
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.310046318
Short name T1879
Test name
Test status
Simulation time 217950584 ps
CPU time 0.92 seconds
Started Jul 11 05:54:29 PM PDT 24
Finished Jul 11 05:54:32 PM PDT 24
Peak memory 206384 kb
Host smart-ae96878a-9e8e-4be4-97a4-ce3b2784aad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31004
6318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.310046318
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.670439222
Short name T1911
Test name
Test status
Simulation time 149676939 ps
CPU time 0.75 seconds
Started Jul 11 05:54:33 PM PDT 24
Finished Jul 11 05:54:36 PM PDT 24
Peak memory 206348 kb
Host smart-5603d395-0467-4423-9d51-62f9ca550a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67043
9222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.670439222
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.401366398
Short name T2124
Test name
Test status
Simulation time 35416771 ps
CPU time 0.69 seconds
Started Jul 11 05:54:30 PM PDT 24
Finished Jul 11 05:54:32 PM PDT 24
Peak memory 206372 kb
Host smart-cbe7837b-9d04-4755-9a78-c431f86709bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40136
6398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.401366398
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1511524691
Short name T1151
Test name
Test status
Simulation time 10888957261 ps
CPU time 26.09 seconds
Started Jul 11 05:54:36 PM PDT 24
Finished Jul 11 05:55:03 PM PDT 24
Peak memory 206736 kb
Host smart-65ee441a-f065-430c-81bf-dfcf0786508b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15115
24691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1511524691
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.548280127
Short name T350
Test name
Test status
Simulation time 172868702 ps
CPU time 0.84 seconds
Started Jul 11 05:54:28 PM PDT 24
Finished Jul 11 05:54:31 PM PDT 24
Peak memory 206260 kb
Host smart-55c0b046-f21f-4fbe-ae23-357e7eb5d9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54828
0127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.548280127
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2769215252
Short name T1812
Test name
Test status
Simulation time 227228443 ps
CPU time 0.89 seconds
Started Jul 11 05:54:28 PM PDT 24
Finished Jul 11 05:54:31 PM PDT 24
Peak memory 206376 kb
Host smart-d9ff7422-ec8f-4acb-8794-f66d8d66d9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27692
15252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2769215252
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.536261194
Short name T2329
Test name
Test status
Simulation time 11522889338 ps
CPU time 305.69 seconds
Started Jul 11 05:54:40 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206636 kb
Host smart-8c1afddb-41ec-4079-bfdf-b63b4e5589b9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=536261194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.536261194
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2791202721
Short name T1173
Test name
Test status
Simulation time 7689688759 ps
CPU time 115.31 seconds
Started Jul 11 05:54:43 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206708 kb
Host smart-0cfc3fbc-bd42-4143-b87a-050d1260cd1b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2791202721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2791202721
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3617571080
Short name T1337
Test name
Test status
Simulation time 21432706891 ps
CPU time 164.87 seconds
Started Jul 11 05:54:33 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206744 kb
Host smart-f7224d49-1528-485d-8469-57e4855a80b7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3617571080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3617571080
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.97950982
Short name T638
Test name
Test status
Simulation time 195229509 ps
CPU time 0.85 seconds
Started Jul 11 05:54:38 PM PDT 24
Finished Jul 11 05:54:40 PM PDT 24
Peak memory 206328 kb
Host smart-c47a4aae-8676-4fb4-ad78-05437f857e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97950
982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.97950982
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.591551640
Short name T393
Test name
Test status
Simulation time 223615006 ps
CPU time 0.83 seconds
Started Jul 11 05:54:33 PM PDT 24
Finished Jul 11 05:54:36 PM PDT 24
Peak memory 206372 kb
Host smart-6b5d7315-53ea-4ac5-ac34-d3c70abc1a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59155
1640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.591551640
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.193076779
Short name T976
Test name
Test status
Simulation time 175215709 ps
CPU time 0.79 seconds
Started Jul 11 05:54:40 PM PDT 24
Finished Jul 11 05:54:42 PM PDT 24
Peak memory 206300 kb
Host smart-45c4147d-f71e-437f-b2dc-cfe867ebe3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19307
6779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.193076779
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.4129618290
Short name T81
Test name
Test status
Simulation time 201309844 ps
CPU time 0.88 seconds
Started Jul 11 05:54:36 PM PDT 24
Finished Jul 11 05:54:39 PM PDT 24
Peak memory 206396 kb
Host smart-fe9d53e1-5d4f-4aab-8e61-58a534fad8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41296
18290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.4129618290
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2341310367
Short name T220
Test name
Test status
Simulation time 1160123721 ps
CPU time 1.8 seconds
Started Jul 11 05:54:35 PM PDT 24
Finished Jul 11 05:54:39 PM PDT 24
Peak memory 225252 kb
Host smart-2748a8dc-86ec-4e14-8ab8-c3660b80d4e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2341310367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2341310367
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1146234086
Short name T2679
Test name
Test status
Simulation time 385252845 ps
CPU time 1.31 seconds
Started Jul 11 05:54:38 PM PDT 24
Finished Jul 11 05:54:41 PM PDT 24
Peak memory 206388 kb
Host smart-6a84a674-3c14-4dc3-a103-7d63a1f8e715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11462
34086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1146234086
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.493672512
Short name T2678
Test name
Test status
Simulation time 194948969 ps
CPU time 0.89 seconds
Started Jul 11 05:54:39 PM PDT 24
Finished Jul 11 05:54:42 PM PDT 24
Peak memory 206312 kb
Host smart-efc1c17e-2197-472d-b434-46ad154a252e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49367
2512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.493672512
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1754302114
Short name T2213
Test name
Test status
Simulation time 148845812 ps
CPU time 0.77 seconds
Started Jul 11 05:54:37 PM PDT 24
Finished Jul 11 05:54:40 PM PDT 24
Peak memory 206372 kb
Host smart-f0342617-cdb7-471c-bb78-3285043be340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
02114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1754302114
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3208922593
Short name T1487
Test name
Test status
Simulation time 153450332 ps
CPU time 0.74 seconds
Started Jul 11 05:54:34 PM PDT 24
Finished Jul 11 05:54:36 PM PDT 24
Peak memory 206372 kb
Host smart-2469500e-cdc8-4d20-886f-2d18d28ba0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32089
22593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3208922593
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.333443903
Short name T2535
Test name
Test status
Simulation time 245822306 ps
CPU time 0.93 seconds
Started Jul 11 05:54:36 PM PDT 24
Finished Jul 11 05:54:39 PM PDT 24
Peak memory 206380 kb
Host smart-78d805ee-74ca-425a-995f-549faaeb60f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
3903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.333443903
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.16327746
Short name T1371
Test name
Test status
Simulation time 4092285020 ps
CPU time 29.06 seconds
Started Jul 11 05:54:35 PM PDT 24
Finished Jul 11 05:55:06 PM PDT 24
Peak memory 206744 kb
Host smart-fb92b887-9d12-403b-8f4a-1bbfda989417
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=16327746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.16327746
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2128463253
Short name T1893
Test name
Test status
Simulation time 234061660 ps
CPU time 0.86 seconds
Started Jul 11 05:54:37 PM PDT 24
Finished Jul 11 05:54:40 PM PDT 24
Peak memory 206392 kb
Host smart-32dfde22-af35-4ba2-b955-88a2467f9771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21284
63253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2128463253
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.970686285
Short name T1543
Test name
Test status
Simulation time 228855175 ps
CPU time 0.87 seconds
Started Jul 11 05:54:39 PM PDT 24
Finished Jul 11 05:54:42 PM PDT 24
Peak memory 206384 kb
Host smart-9ba09b7b-749f-4a6e-b202-5f82c962bd88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97068
6285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.970686285
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2926399489
Short name T434
Test name
Test status
Simulation time 328921975 ps
CPU time 1.06 seconds
Started Jul 11 05:54:40 PM PDT 24
Finished Jul 11 05:54:43 PM PDT 24
Peak memory 206388 kb
Host smart-d5cd09d0-7a15-4f9f-859f-79733ae82b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29263
99489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2926399489
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.4110474981
Short name T1511
Test name
Test status
Simulation time 5756824741 ps
CPU time 151.16 seconds
Started Jul 11 05:54:43 PM PDT 24
Finished Jul 11 05:57:15 PM PDT 24
Peak memory 206644 kb
Host smart-863ebc6f-d36e-461b-b8b2-529268849f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41104
74981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.4110474981
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3610743027
Short name T249
Test name
Test status
Simulation time 19018879541 ps
CPU time 170.92 seconds
Started Jul 11 05:54:43 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 206688 kb
Host smart-3c7436f7-e0b9-4686-8bce-7d7f83a37ab6
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3610743027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3610743027
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2101109538
Short name T1909
Test name
Test status
Simulation time 38722180 ps
CPU time 0.68 seconds
Started Jul 11 05:59:25 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 206412 kb
Host smart-6207776e-9fd0-4f0a-b81c-61ed75ebde62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2101109538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2101109538
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3758885252
Short name T913
Test name
Test status
Simulation time 3681940490 ps
CPU time 4.23 seconds
Started Jul 11 05:59:21 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 206376 kb
Host smart-bcfc35fc-b328-4b27-84c4-546f38662593
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3758885252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.3758885252
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.251841437
Short name T237
Test name
Test status
Simulation time 13374276201 ps
CPU time 13.27 seconds
Started Jul 11 05:59:18 PM PDT 24
Finished Jul 11 05:59:40 PM PDT 24
Peak memory 206644 kb
Host smart-2980e3da-884f-45b0-bfad-7966ecdd5adc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=251841437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.251841437
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.3767035951
Short name T1453
Test name
Test status
Simulation time 23325871763 ps
CPU time 22.36 seconds
Started Jul 11 05:59:21 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206708 kb
Host smart-a234cf03-de21-4a80-88ea-60ea65d7ff26
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3767035951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.3767035951
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1151465517
Short name T2578
Test name
Test status
Simulation time 151311098 ps
CPU time 0.82 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206372 kb
Host smart-371303bc-0509-46a0-941d-f0d6655dfbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11514
65517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1151465517
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.549690464
Short name T2492
Test name
Test status
Simulation time 162677829 ps
CPU time 0.76 seconds
Started Jul 11 05:59:23 PM PDT 24
Finished Jul 11 05:59:32 PM PDT 24
Peak memory 206304 kb
Host smart-c3e42435-130c-432e-83a0-ca81d80d386f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54969
0464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.549690464
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.194676374
Short name T1370
Test name
Test status
Simulation time 397055910 ps
CPU time 1.26 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 05:59:38 PM PDT 24
Peak memory 206408 kb
Host smart-c0621aac-57b7-4d90-b71d-29b22bf4dc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19467
6374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.194676374
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2569044953
Short name T849
Test name
Test status
Simulation time 543681464 ps
CPU time 1.49 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206404 kb
Host smart-13c54d20-19a9-41cf-a98d-b2a1aac33cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
44953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2569044953
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3817064918
Short name T192
Test name
Test status
Simulation time 10430008250 ps
CPU time 22.37 seconds
Started Jul 11 05:59:22 PM PDT 24
Finished Jul 11 05:59:54 PM PDT 24
Peak memory 206648 kb
Host smart-2012cb76-8a4f-4fae-af7c-e5569e9c1194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38170
64918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3817064918
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3539587748
Short name T718
Test name
Test status
Simulation time 320254484 ps
CPU time 1.13 seconds
Started Jul 11 05:59:21 PM PDT 24
Finished Jul 11 05:59:32 PM PDT 24
Peak memory 206364 kb
Host smart-1f1536ac-3ad7-4282-b069-d3d5f0d13014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35395
87748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3539587748
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1000072640
Short name T441
Test name
Test status
Simulation time 140892867 ps
CPU time 0.85 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 05:59:37 PM PDT 24
Peak memory 206396 kb
Host smart-04c5d820-9fca-4322-99bd-314123f37c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10000
72640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1000072640
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2170956252
Short name T1567
Test name
Test status
Simulation time 32072179 ps
CPU time 0.67 seconds
Started Jul 11 05:59:20 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206396 kb
Host smart-4085c853-e3ca-4d11-9723-6c5c28f3ab3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21709
56252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2170956252
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1499422113
Short name T537
Test name
Test status
Simulation time 873355559 ps
CPU time 2.01 seconds
Started Jul 11 05:59:25 PM PDT 24
Finished Jul 11 05:59:36 PM PDT 24
Peak memory 206584 kb
Host smart-79f65749-3204-4566-b677-20271b50aeb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14994
22113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1499422113
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.292373435
Short name T85
Test name
Test status
Simulation time 237117211 ps
CPU time 1.62 seconds
Started Jul 11 05:59:20 PM PDT 24
Finished Jul 11 05:59:30 PM PDT 24
Peak memory 206572 kb
Host smart-44f90977-1874-4541-9f65-ccc79a3e9d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29237
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.292373435
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3763312210
Short name T764
Test name
Test status
Simulation time 213369459 ps
CPU time 0.86 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206388 kb
Host smart-48e30632-ebc0-48b5-89dd-209cf65b8024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37633
12210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3763312210
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.388413915
Short name T2301
Test name
Test status
Simulation time 147874825 ps
CPU time 0.75 seconds
Started Jul 11 05:59:25 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 206300 kb
Host smart-ca761915-ee0e-493c-94de-6e22afa82652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841
3915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.388413915
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1033268487
Short name T2074
Test name
Test status
Simulation time 183191566 ps
CPU time 0.84 seconds
Started Jul 11 05:59:27 PM PDT 24
Finished Jul 11 05:59:38 PM PDT 24
Peak memory 206384 kb
Host smart-7cb71c60-9dbd-461b-b8e9-ce5f01427448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10332
68487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1033268487
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2566282771
Short name T2437
Test name
Test status
Simulation time 5204352903 ps
CPU time 48.29 seconds
Started Jul 11 05:59:32 PM PDT 24
Finished Jul 11 06:00:32 PM PDT 24
Peak memory 205936 kb
Host smart-0af40a66-fd4b-4c93-80e8-fa1e53bfa5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25662
82771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2566282771
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.289515773
Short name T1719
Test name
Test status
Simulation time 257406348 ps
CPU time 0.94 seconds
Started Jul 11 05:59:30 PM PDT 24
Finished Jul 11 05:59:40 PM PDT 24
Peak memory 206376 kb
Host smart-36962358-9f51-48c4-a93a-8976c161ba07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28951
5773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.289515773
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.668520787
Short name T1064
Test name
Test status
Simulation time 23331258169 ps
CPU time 30.52 seconds
Started Jul 11 05:59:25 PM PDT 24
Finished Jul 11 06:00:05 PM PDT 24
Peak memory 206448 kb
Host smart-3226df44-1026-4b09-8b90-b27e67be6c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66852
0787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.668520787
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1498553217
Short name T2349
Test name
Test status
Simulation time 3274455461 ps
CPU time 3.65 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 05:59:40 PM PDT 24
Peak memory 206320 kb
Host smart-bfdedbdf-266f-477f-8d2f-d93e2845922f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14985
53217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1498553217
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.528582858
Short name T2204
Test name
Test status
Simulation time 8079275599 ps
CPU time 75.15 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 06:01:00 PM PDT 24
Peak memory 206716 kb
Host smart-705bd9bc-6a44-4ee3-acca-d07c9144f840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52858
2858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.528582858
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.391244861
Short name T1492
Test name
Test status
Simulation time 6591459456 ps
CPU time 178.23 seconds
Started Jul 11 05:59:40 PM PDT 24
Finished Jul 11 06:02:50 PM PDT 24
Peak memory 206600 kb
Host smart-47739ef3-2485-4bce-ae2b-9579c9c69c11
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=391244861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.391244861
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.682878558
Short name T1546
Test name
Test status
Simulation time 237678782 ps
CPU time 0.94 seconds
Started Jul 11 05:59:30 PM PDT 24
Finished Jul 11 05:59:42 PM PDT 24
Peak memory 206300 kb
Host smart-a7cdd45b-9907-4340-ba47-ce91fa801697
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=682878558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.682878558
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3798451956
Short name T2701
Test name
Test status
Simulation time 203967294 ps
CPU time 0.86 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206384 kb
Host smart-615ef1cf-a76c-4f47-9d62-f8ca8b494d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37984
51956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3798451956
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.982486112
Short name T2594
Test name
Test status
Simulation time 6240303849 ps
CPU time 178.47 seconds
Started Jul 11 05:59:27 PM PDT 24
Finished Jul 11 06:02:36 PM PDT 24
Peak memory 206652 kb
Host smart-17292e84-945f-44d9-971b-d64b8a7a145a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98248
6112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.982486112
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3404218664
Short name T1203
Test name
Test status
Simulation time 3931293282 ps
CPU time 29.67 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 06:00:14 PM PDT 24
Peak memory 206628 kb
Host smart-0d0372ab-cade-437f-b08a-2167a35d17cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3404218664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3404218664
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.121888206
Short name T2744
Test name
Test status
Simulation time 165533107 ps
CPU time 0.8 seconds
Started Jul 11 05:59:34 PM PDT 24
Finished Jul 11 05:59:46 PM PDT 24
Peak memory 206384 kb
Host smart-81a0d18d-b1de-4562-a1d2-0cb8e02043bd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=121888206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.121888206
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2737060462
Short name T1861
Test name
Test status
Simulation time 151286865 ps
CPU time 0.79 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206308 kb
Host smart-dac33e2e-2673-4e62-8dc0-e11e91180e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27370
60462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2737060462
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.514567789
Short name T148
Test name
Test status
Simulation time 275036060 ps
CPU time 1.01 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:46 PM PDT 24
Peak memory 206380 kb
Host smart-316a70b1-a890-4fb0-b83e-042f549a9b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51456
7789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.514567789
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.212836144
Short name T554
Test name
Test status
Simulation time 176157648 ps
CPU time 0.84 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 206380 kb
Host smart-7cd7f18c-677f-434e-a85c-07d78e15f241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21283
6144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.212836144
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3476535571
Short name T1932
Test name
Test status
Simulation time 172709939 ps
CPU time 0.8 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 05:59:47 PM PDT 24
Peak memory 206252 kb
Host smart-e9957d4d-5086-4c2a-a037-e614597b7168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34765
35571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3476535571
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1281722239
Short name T852
Test name
Test status
Simulation time 186124391 ps
CPU time 0.84 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206352 kb
Host smart-11414200-578c-4724-b872-3b8753d4c188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12817
22239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1281722239
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.554826103
Short name T1610
Test name
Test status
Simulation time 146497566 ps
CPU time 0.78 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206332 kb
Host smart-c8d4a8bb-0da6-4075-af26-ec88888defee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55482
6103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.554826103
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.2733468745
Short name T1841
Test name
Test status
Simulation time 237017392 ps
CPU time 1.08 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206320 kb
Host smart-620807bd-e273-4b6c-b816-491753e3be2d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2733468745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.2733468745
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1155009971
Short name T1693
Test name
Test status
Simulation time 137892227 ps
CPU time 0.73 seconds
Started Jul 11 05:59:29 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206296 kb
Host smart-521c18f8-e34c-496c-aefa-dcdbcd1547ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11550
09971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1155009971
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2503485687
Short name T1322
Test name
Test status
Simulation time 46835758 ps
CPU time 0.67 seconds
Started Jul 11 05:59:32 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206392 kb
Host smart-a07e7a5d-5e34-439f-814b-05b93907c311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034
85687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2503485687
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2191522994
Short name T995
Test name
Test status
Simulation time 9328432179 ps
CPU time 21.52 seconds
Started Jul 11 05:59:34 PM PDT 24
Finished Jul 11 06:00:07 PM PDT 24
Peak memory 206676 kb
Host smart-c9b56658-6c97-4b24-9018-6b5668224b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21915
22994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2191522994
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1899150915
Short name T1792
Test name
Test status
Simulation time 219646674 ps
CPU time 0.81 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:50 PM PDT 24
Peak memory 206388 kb
Host smart-b81756d5-151f-44b5-bb26-6491f8cb3917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991
50915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1899150915
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.143915283
Short name T2340
Test name
Test status
Simulation time 206333591 ps
CPU time 0.86 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 206344 kb
Host smart-217431eb-65dd-4440-bfb3-4f095193ab10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14391
5283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.143915283
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2283346926
Short name T659
Test name
Test status
Simulation time 172265051 ps
CPU time 0.86 seconds
Started Jul 11 05:59:30 PM PDT 24
Finished Jul 11 05:59:42 PM PDT 24
Peak memory 206396 kb
Host smart-53dab514-9dad-4b93-a8bc-60a3b1205234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22833
46926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2283346926
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.777017910
Short name T2515
Test name
Test status
Simulation time 152534950 ps
CPU time 0.74 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206384 kb
Host smart-5be35f5b-7ac2-41a6-805f-efb9a31cbd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77701
7910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.777017910
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2599543400
Short name T1630
Test name
Test status
Simulation time 163814288 ps
CPU time 0.8 seconds
Started Jul 11 05:59:36 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 206120 kb
Host smart-7f2375b4-fe2b-4098-8633-50ea4069d4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25995
43400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2599543400
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2993579220
Short name T412
Test name
Test status
Simulation time 149355422 ps
CPU time 0.81 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206280 kb
Host smart-bc9d8d24-4e53-4d78-918a-376c38b24532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29935
79220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2993579220
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2001340023
Short name T1517
Test name
Test status
Simulation time 151797024 ps
CPU time 0.8 seconds
Started Jul 11 05:59:29 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206388 kb
Host smart-499a8e49-beb9-49b6-868d-019b5fae433a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20013
40023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2001340023
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1195826736
Short name T1652
Test name
Test status
Simulation time 243890901 ps
CPU time 0.96 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:46 PM PDT 24
Peak memory 206332 kb
Host smart-fe0006c9-3e38-47f0-878f-bee0ef19307a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958
26736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1195826736
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2521291621
Short name T1433
Test name
Test status
Simulation time 5605281324 ps
CPU time 39.95 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 06:00:16 PM PDT 24
Peak memory 206616 kb
Host smart-1df7e35a-de59-4c2c-9fa7-826b06523683
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2521291621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2521291621
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2453332093
Short name T1908
Test name
Test status
Simulation time 164151410 ps
CPU time 0.77 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 05:59:50 PM PDT 24
Peak memory 206388 kb
Host smart-926bec5c-c8c5-404d-92c3-16f4d75af0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24533
32093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2453332093
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.624351560
Short name T2038
Test name
Test status
Simulation time 181738597 ps
CPU time 0.87 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 206328 kb
Host smart-ee1132c7-9937-4c93-9275-43f185e4d6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62435
1560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.624351560
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2152113133
Short name T1484
Test name
Test status
Simulation time 903574331 ps
CPU time 1.91 seconds
Started Jul 11 05:59:31 PM PDT 24
Finished Jul 11 05:59:44 PM PDT 24
Peak memory 206616 kb
Host smart-549e629e-38ca-43f1-95de-f8bdb2b46778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21521
13133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2152113133
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.3383141803
Short name T583
Test name
Test status
Simulation time 5253030992 ps
CPU time 37.45 seconds
Started Jul 11 05:59:40 PM PDT 24
Finished Jul 11 06:00:29 PM PDT 24
Peak memory 206612 kb
Host smart-3833774d-0fcc-4e5b-9349-56572756bae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33831
41803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3383141803
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1379913665
Short name T629
Test name
Test status
Simulation time 35638743 ps
CPU time 0.66 seconds
Started Jul 11 05:59:50 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206416 kb
Host smart-2f7524dc-4678-4675-98b3-b6039b395770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1379913665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1379913665
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3528737239
Short name T215
Test name
Test status
Simulation time 4196991290 ps
CPU time 5.18 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:26 PM PDT 24
Peak memory 206580 kb
Host smart-672ff44b-216d-4054-85b4-199f58920ecc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3528737239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3528737239
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3011882338
Short name T201
Test name
Test status
Simulation time 13328743473 ps
CPU time 13.76 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 06:00:03 PM PDT 24
Peak memory 206396 kb
Host smart-b4b5b4ba-ca6a-4601-8567-557d76a81f60
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3011882338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3011882338
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1519952919
Short name T1559
Test name
Test status
Simulation time 23362923416 ps
CPU time 23.21 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206608 kb
Host smart-ed13e71d-ffbb-488e-bc8c-5aaf273be88a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1519952919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.1519952919
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1690976708
Short name T671
Test name
Test status
Simulation time 237080055 ps
CPU time 0.84 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 05:59:37 PM PDT 24
Peak memory 206392 kb
Host smart-68460f44-c252-4888-b147-f9726b634ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16909
76708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1690976708
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1612173823
Short name T487
Test name
Test status
Simulation time 153331267 ps
CPU time 0.75 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:51 PM PDT 24
Peak memory 206384 kb
Host smart-43be169a-468f-46fc-9387-192bd88384ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16121
73823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1612173823
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1005641246
Short name T1106
Test name
Test status
Simulation time 168468101 ps
CPU time 0.84 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 05:59:39 PM PDT 24
Peak memory 206352 kb
Host smart-ca6b6fa5-0d4b-4d87-a251-d32446c6d8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10056
41246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1005641246
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1129949314
Short name T879
Test name
Test status
Simulation time 282922565 ps
CPU time 0.99 seconds
Started Jul 11 05:59:29 PM PDT 24
Finished Jul 11 05:59:41 PM PDT 24
Peak memory 206388 kb
Host smart-8cbaa5b4-b2cb-4220-a89e-80e6b6f184d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11299
49314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1129949314
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1942899798
Short name T1386
Test name
Test status
Simulation time 18839189717 ps
CPU time 32.24 seconds
Started Jul 11 05:59:27 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206644 kb
Host smart-6e7ef0fe-af2d-46af-95f3-b9fef971ea28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19428
99798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1942899798
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.195672672
Short name T1714
Test name
Test status
Simulation time 484004014 ps
CPU time 1.5 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206256 kb
Host smart-e6a7abce-07b6-4502-a793-e088dda890d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19567
2672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.195672672
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3237849236
Short name T1723
Test name
Test status
Simulation time 197650980 ps
CPU time 0.86 seconds
Started Jul 11 05:59:24 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 206400 kb
Host smart-88cc8cc5-0ba5-4f94-a157-9fcb0b6edcde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32378
49236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3237849236
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3219253534
Short name T1964
Test name
Test status
Simulation time 42429932 ps
CPU time 0.63 seconds
Started Jul 11 05:59:26 PM PDT 24
Finished Jul 11 05:59:37 PM PDT 24
Peak memory 206360 kb
Host smart-374f7f79-6c80-4f35-a6b9-0aaaa9a3fe37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192
53534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3219253534
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3837925376
Short name T2091
Test name
Test status
Simulation time 1021228198 ps
CPU time 2.25 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206624 kb
Host smart-8d39b299-1937-4c6c-9394-c3d7e91bf812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38379
25376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3837925376
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2508638380
Short name T1456
Test name
Test status
Simulation time 238559428 ps
CPU time 1.43 seconds
Started Jul 11 05:59:36 PM PDT 24
Finished Jul 11 05:59:50 PM PDT 24
Peak memory 206368 kb
Host smart-81fc1548-c33b-4112-9ed9-0efdc7c86363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25086
38380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2508638380
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3806354700
Short name T123
Test name
Test status
Simulation time 184196690 ps
CPU time 0.84 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206344 kb
Host smart-27810eb5-b217-413d-852c-98f8486782ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38063
54700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3806354700
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3684463846
Short name T581
Test name
Test status
Simulation time 143211470 ps
CPU time 0.83 seconds
Started Jul 11 05:59:36 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 206384 kb
Host smart-69bd0bcc-77fd-404d-b74e-c5df151e84f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36844
63846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3684463846
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2032111643
Short name T2377
Test name
Test status
Simulation time 202283927 ps
CPU time 0.82 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206384 kb
Host smart-72f5ce16-f2ac-4770-8232-31831538534b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
11643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2032111643
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.982461340
Short name T1999
Test name
Test status
Simulation time 208098485 ps
CPU time 0.89 seconds
Started Jul 11 05:59:40 PM PDT 24
Finished Jul 11 05:59:53 PM PDT 24
Peak memory 206348 kb
Host smart-445c5ee9-5459-4827-b0bb-7e7267d457de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98246
1340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.982461340
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1704631202
Short name T2100
Test name
Test status
Simulation time 23268469743 ps
CPU time 24.43 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 06:00:11 PM PDT 24
Peak memory 206444 kb
Host smart-138987c2-4a47-4173-a5e1-a8b2fcc19671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17046
31202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1704631202
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1054835142
Short name T1012
Test name
Test status
Simulation time 3363017780 ps
CPU time 3.88 seconds
Started Jul 11 05:59:28 PM PDT 24
Finished Jul 11 05:59:42 PM PDT 24
Peak memory 206448 kb
Host smart-de397bca-5597-4d75-a377-8a6ff74820d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548
35142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1054835142
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2399784547
Short name T630
Test name
Test status
Simulation time 5437614213 ps
CPU time 51.32 seconds
Started Jul 11 05:59:31 PM PDT 24
Finished Jul 11 06:00:33 PM PDT 24
Peak memory 206740 kb
Host smart-f92bb004-a58f-4fa4-b5d9-76bcf75afb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23997
84547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2399784547
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2613536192
Short name T446
Test name
Test status
Simulation time 5215536615 ps
CPU time 145.26 seconds
Started Jul 11 05:59:31 PM PDT 24
Finished Jul 11 06:02:08 PM PDT 24
Peak memory 206644 kb
Host smart-565eda3c-5861-4895-ba19-180c917f5adc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2613536192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2613536192
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.696222494
Short name T2573
Test name
Test status
Simulation time 232702001 ps
CPU time 0.88 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206380 kb
Host smart-c5a286e4-b158-4b96-b5c8-8768cfacf41d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=696222494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.696222494
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.95508271
Short name T949
Test name
Test status
Simulation time 194778597 ps
CPU time 0.84 seconds
Started Jul 11 05:59:36 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 206356 kb
Host smart-a1ded9e9-4828-4583-828f-c21f0b899068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95508
271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.95508271
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1974120653
Short name T425
Test name
Test status
Simulation time 3669417208 ps
CPU time 101.24 seconds
Started Jul 11 05:59:30 PM PDT 24
Finished Jul 11 06:01:22 PM PDT 24
Peak memory 206652 kb
Host smart-91891515-7891-4a95-bdb7-52173951ce42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19741
20653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1974120653
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2831078218
Short name T2107
Test name
Test status
Simulation time 4811782469 ps
CPU time 137.91 seconds
Started Jul 11 05:59:32 PM PDT 24
Finished Jul 11 06:02:01 PM PDT 24
Peak memory 206536 kb
Host smart-4e6bf429-bb9c-4089-9843-35c75271cd9b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2831078218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2831078218
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1142704516
Short name T1283
Test name
Test status
Simulation time 155865875 ps
CPU time 0.86 seconds
Started Jul 11 05:59:36 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206388 kb
Host smart-b6dc2e8c-cd35-43b5-9973-533463f68f6d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1142704516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1142704516
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1097733078
Short name T971
Test name
Test status
Simulation time 148738702 ps
CPU time 0.74 seconds
Started Jul 11 05:59:31 PM PDT 24
Finished Jul 11 05:59:42 PM PDT 24
Peak memory 206304 kb
Host smart-98a8af20-c08c-4f8d-89ab-618ddc4f7b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10977
33078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1097733078
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.31874134
Short name T1245
Test name
Test status
Simulation time 229711762 ps
CPU time 0.87 seconds
Started Jul 11 05:59:34 PM PDT 24
Finished Jul 11 05:59:47 PM PDT 24
Peak memory 206364 kb
Host smart-e566058a-be8e-4888-9291-41281175f31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31874
134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.31874134
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2817700030
Short name T1698
Test name
Test status
Simulation time 206277528 ps
CPU time 0.9 seconds
Started Jul 11 05:59:32 PM PDT 24
Finished Jul 11 05:59:44 PM PDT 24
Peak memory 206464 kb
Host smart-986a7f5e-35a6-4f9c-8cae-0fe1ec358114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28177
00030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2817700030
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.460989429
Short name T1564
Test name
Test status
Simulation time 221425832 ps
CPU time 0.85 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206552 kb
Host smart-7f368e9b-bc67-4a66-8931-caf3fe0dda77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46098
9429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.460989429
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.207145460
Short name T2228
Test name
Test status
Simulation time 185253784 ps
CPU time 0.8 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206296 kb
Host smart-2e6d53f6-d010-4b48-9975-0ea96cbaad66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20714
5460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.207145460
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1174168676
Short name T2307
Test name
Test status
Simulation time 153624524 ps
CPU time 0.77 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:46 PM PDT 24
Peak memory 206372 kb
Host smart-d01a5e3c-5e0c-4b73-846e-97c758f457b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11741
68676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1174168676
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3780663468
Short name T743
Test name
Test status
Simulation time 202154676 ps
CPU time 0.88 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206540 kb
Host smart-2feb81e8-69ce-4d69-b3c0-038b13de4103
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3780663468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3780663468
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3210368626
Short name T351
Test name
Test status
Simulation time 149065575 ps
CPU time 0.81 seconds
Started Jul 11 05:59:32 PM PDT 24
Finished Jul 11 05:59:44 PM PDT 24
Peak memory 206384 kb
Host smart-86e7e2f2-83fc-47da-875f-5a39f9ac2d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32103
68626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3210368626
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.999822575
Short name T26
Test name
Test status
Simulation time 59932952 ps
CPU time 0.68 seconds
Started Jul 11 05:59:40 PM PDT 24
Finished Jul 11 05:59:53 PM PDT 24
Peak memory 206344 kb
Host smart-81b17473-f50b-45eb-a180-7675cfb8dc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99982
2575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.999822575
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2121592996
Short name T2344
Test name
Test status
Simulation time 12149931459 ps
CPU time 27.05 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 06:00:15 PM PDT 24
Peak memory 206664 kb
Host smart-9d781675-98f8-4bd9-a5e2-1888af7b170a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21215
92996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2121592996
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1050675016
Short name T2651
Test name
Test status
Simulation time 206486347 ps
CPU time 0.86 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206312 kb
Host smart-8dcfd786-dd2f-4dbe-8a4e-22b50e27dd46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
75016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1050675016
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.166012802
Short name T1734
Test name
Test status
Simulation time 249117620 ps
CPU time 0.92 seconds
Started Jul 11 05:59:34 PM PDT 24
Finished Jul 11 05:59:46 PM PDT 24
Peak memory 206360 kb
Host smart-39e13588-f4db-42b2-875f-4205848f69a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16601
2802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.166012802
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.209830759
Short name T1065
Test name
Test status
Simulation time 220220522 ps
CPU time 0.92 seconds
Started Jul 11 05:59:29 PM PDT 24
Finished Jul 11 05:59:40 PM PDT 24
Peak memory 206400 kb
Host smart-650156d5-e509-4d88-b15f-97abd0899b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20983
0759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.209830759
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1618831256
Short name T2637
Test name
Test status
Simulation time 191149239 ps
CPU time 0.83 seconds
Started Jul 11 05:59:43 PM PDT 24
Finished Jul 11 05:59:55 PM PDT 24
Peak memory 206540 kb
Host smart-648b1c1c-5e51-40e1-ae5b-26dd7146a1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16188
31256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1618831256
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2593455328
Short name T1793
Test name
Test status
Simulation time 188078467 ps
CPU time 0.85 seconds
Started Jul 11 05:59:36 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206332 kb
Host smart-5ded342b-2897-4f6d-9460-1850ced7dc76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
55328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2593455328
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2130508947
Short name T868
Test name
Test status
Simulation time 162684351 ps
CPU time 0.76 seconds
Started Jul 11 05:59:33 PM PDT 24
Finished Jul 11 05:59:45 PM PDT 24
Peak memory 206364 kb
Host smart-4a369716-6c88-4f96-92b7-4a06fbef1623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21305
08947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2130508947
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2951430961
Short name T2315
Test name
Test status
Simulation time 173458421 ps
CPU time 0.89 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206340 kb
Host smart-dd31728b-afae-4576-83d3-501a8a6ed439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29514
30961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2951430961
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1288295611
Short name T1284
Test name
Test status
Simulation time 261388758 ps
CPU time 1.03 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206316 kb
Host smart-e1eaa5f6-a8dc-4dbc-b262-804a4c4f1f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12882
95611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1288295611
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2939753632
Short name T2643
Test name
Test status
Simulation time 4032890882 ps
CPU time 27.26 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 06:00:15 PM PDT 24
Peak memory 206688 kb
Host smart-0c25aaec-e18d-4726-9a9d-fc36f0ee8c73
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2939753632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2939753632
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.372173482
Short name T1568
Test name
Test status
Simulation time 193334113 ps
CPU time 0.79 seconds
Started Jul 11 05:59:40 PM PDT 24
Finished Jul 11 05:59:53 PM PDT 24
Peak memory 206304 kb
Host smart-682649ca-b321-4036-a2b3-5a49676db4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37217
3482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.372173482
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1393565653
Short name T1721
Test name
Test status
Simulation time 181607467 ps
CPU time 0.84 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206368 kb
Host smart-20a5aa5f-5734-4081-a5a3-220b2a77ab5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13935
65653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1393565653
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.1499087891
Short name T2525
Test name
Test status
Simulation time 1019282465 ps
CPU time 2.25 seconds
Started Jul 11 05:59:59 PM PDT 24
Finished Jul 11 06:00:10 PM PDT 24
Peak memory 206724 kb
Host smart-5c763fbe-06ee-409e-9d74-ef707fd6a4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
87891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.1499087891
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3255011097
Short name T1310
Test name
Test status
Simulation time 6125256244 ps
CPU time 42.4 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 06:00:29 PM PDT 24
Peak memory 206648 kb
Host smart-32466dcb-a2c7-410c-97db-01afc60b220d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550
11097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3255011097
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.104022386
Short name T198
Test name
Test status
Simulation time 81598509 ps
CPU time 0.75 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206340 kb
Host smart-4a275f59-6995-4d0b-bbd9-c9fe8ae7e0e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=104022386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.104022386
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.930358545
Short name T667
Test name
Test status
Simulation time 3918155451 ps
CPU time 5.57 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206336 kb
Host smart-3174d23d-971e-4261-bcdd-c75b8551e737
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=930358545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.930358545
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3005327453
Short name T783
Test name
Test status
Simulation time 13366401395 ps
CPU time 12.81 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 06:00:04 PM PDT 24
Peak memory 206380 kb
Host smart-b0f916ec-dd34-42d0-94ec-8dafd2dfd187
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3005327453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3005327453
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.868947885
Short name T2511
Test name
Test status
Simulation time 23325323748 ps
CPU time 22.93 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 06:00:14 PM PDT 24
Peak memory 206460 kb
Host smart-1346999b-3716-47ec-be51-b1e9832f40be
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=868947885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.868947885
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3482635800
Short name T878
Test name
Test status
Simulation time 152084410 ps
CPU time 0.79 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206384 kb
Host smart-8428b62b-a02a-413b-be69-488ae5ae2557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34826
35800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3482635800
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.964648439
Short name T2413
Test name
Test status
Simulation time 165136573 ps
CPU time 0.83 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206384 kb
Host smart-8c1de08d-16f8-437e-b742-b15841a268ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96464
8439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.964648439
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.4205509081
Short name T2400
Test name
Test status
Simulation time 465189654 ps
CPU time 1.43 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 206396 kb
Host smart-98bd448a-6816-408a-8164-57421846646c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
09081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.4205509081
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3431147677
Short name T2159
Test name
Test status
Simulation time 961875293 ps
CPU time 2.22 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 05:59:51 PM PDT 24
Peak memory 206584 kb
Host smart-6c5e6200-a0b2-4310-86b6-b5f748ae4dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311
47677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3431147677
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3470668908
Short name T1498
Test name
Test status
Simulation time 10921232669 ps
CPU time 21.37 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 06:00:12 PM PDT 24
Peak memory 206608 kb
Host smart-0cba7899-fe62-4954-8eac-db8362c9c385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34706
68908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3470668908
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2047390997
Short name T341
Test name
Test status
Simulation time 373320374 ps
CPU time 1.23 seconds
Started Jul 11 05:59:35 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206404 kb
Host smart-f56a4b12-8a9d-4418-96d1-1ebb22851963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20473
90997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2047390997
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.672763579
Short name T46
Test name
Test status
Simulation time 146981980 ps
CPU time 0.75 seconds
Started Jul 11 06:06:24 PM PDT 24
Finished Jul 11 06:06:26 PM PDT 24
Peak memory 206372 kb
Host smart-5c2ba83b-0f82-4ea7-80fa-1b45e7640528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67276
3579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.672763579
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.1853174101
Short name T609
Test name
Test status
Simulation time 42744440 ps
CPU time 0.67 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206344 kb
Host smart-4bf2d41e-4609-42c4-bd32-a61f91983464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18531
74101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1853174101
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1356608721
Short name T1975
Test name
Test status
Simulation time 774415397 ps
CPU time 2.05 seconds
Started Jul 11 05:59:52 PM PDT 24
Finished Jul 11 06:00:04 PM PDT 24
Peak memory 206576 kb
Host smart-7972cde4-bef4-4eea-8c80-c6127414f5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13566
08721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1356608721
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2647306686
Short name T1375
Test name
Test status
Simulation time 244591572 ps
CPU time 1.69 seconds
Started Jul 11 05:59:59 PM PDT 24
Finished Jul 11 06:00:10 PM PDT 24
Peak memory 206760 kb
Host smart-24611947-4b08-4a1a-9328-fed2eb3fb33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26473
06686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2647306686
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2745078543
Short name T2415
Test name
Test status
Simulation time 190741734 ps
CPU time 0.85 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206292 kb
Host smart-8b3dcb07-e50d-49e5-84a7-c90b35626247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
78543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2745078543
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2569355474
Short name T2112
Test name
Test status
Simulation time 154127901 ps
CPU time 0.77 seconds
Started Jul 11 05:59:36 PM PDT 24
Finished Jul 11 05:59:48 PM PDT 24
Peak memory 206380 kb
Host smart-9ee76930-617b-4abf-81ca-c22c4b55a41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25693
55474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2569355474
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.4102279775
Short name T1731
Test name
Test status
Simulation time 197337592 ps
CPU time 0.83 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 206296 kb
Host smart-30b63a60-e943-4893-a7d7-7813efe9bc7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41022
79775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.4102279775
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.4131521422
Short name T2049
Test name
Test status
Simulation time 7437416759 ps
CPU time 68.94 seconds
Started Jul 11 05:59:57 PM PDT 24
Finished Jul 11 06:01:16 PM PDT 24
Peak memory 206856 kb
Host smart-198d83b0-ab5f-4a72-92a4-2ed33a39db10
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4131521422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.4131521422
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.2233420072
Short name T631
Test name
Test status
Simulation time 11830405743 ps
CPU time 102.15 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 06:01:34 PM PDT 24
Peak memory 206616 kb
Host smart-e46982be-2c79-4109-8085-2a712587af66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22334
20072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2233420072
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2249516422
Short name T1576
Test name
Test status
Simulation time 185649647 ps
CPU time 0.84 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206488 kb
Host smart-4f90b8a3-4a9b-466d-a71b-878b569dae3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22495
16422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2249516422
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2323667354
Short name T2690
Test name
Test status
Simulation time 23323595906 ps
CPU time 22.92 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 06:00:14 PM PDT 24
Peak memory 206420 kb
Host smart-af157f10-ccf3-45a7-8708-b8ffb54310c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23236
67354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2323667354
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1918954345
Short name T920
Test name
Test status
Simulation time 3278051174 ps
CPU time 3.7 seconds
Started Jul 11 05:59:42 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206444 kb
Host smart-1e94bcf1-f591-4808-b469-33e4b62b6675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19189
54345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1918954345
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2335947809
Short name T2067
Test name
Test status
Simulation time 10943952985 ps
CPU time 101.84 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 06:01:38 PM PDT 24
Peak memory 206708 kb
Host smart-5e9e22ce-4df5-4f7e-99ac-4718f5e78620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23359
47809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2335947809
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1798879238
Short name T2693
Test name
Test status
Simulation time 6258041846 ps
CPU time 169.99 seconds
Started Jul 11 05:59:39 PM PDT 24
Finished Jul 11 06:02:41 PM PDT 24
Peak memory 206628 kb
Host smart-6c746fea-c3ce-4dc9-834c-beda4493ebd0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1798879238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1798879238
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3583387935
Short name T1486
Test name
Test status
Simulation time 243414335 ps
CPU time 0.9 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:52 PM PDT 24
Peak memory 206304 kb
Host smart-b0424798-30da-4def-a1c7-28d70420668b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3583387935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3583387935
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.487737513
Short name T2265
Test name
Test status
Simulation time 188025610 ps
CPU time 0.9 seconds
Started Jul 11 05:59:50 PM PDT 24
Finished Jul 11 06:00:01 PM PDT 24
Peak memory 206532 kb
Host smart-51936d85-083f-4c45-9ff4-ff690fde5c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48773
7513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.487737513
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2273405068
Short name T2103
Test name
Test status
Simulation time 4298135013 ps
CPU time 30.35 seconds
Started Jul 11 05:59:45 PM PDT 24
Finished Jul 11 06:00:26 PM PDT 24
Peak memory 206568 kb
Host smart-67801c39-7c33-4fe7-9df3-3ba48893ee86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22734
05068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2273405068
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3134767108
Short name T1053
Test name
Test status
Simulation time 4751631701 ps
CPU time 132.32 seconds
Started Jul 11 05:59:37 PM PDT 24
Finished Jul 11 06:02:00 PM PDT 24
Peak memory 206580 kb
Host smart-852eb388-4550-4586-a39d-b8c0d176af4e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3134767108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3134767108
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2242862736
Short name T772
Test name
Test status
Simulation time 154520801 ps
CPU time 0.87 seconds
Started Jul 11 05:59:52 PM PDT 24
Finished Jul 11 06:00:03 PM PDT 24
Peak memory 206380 kb
Host smart-a1eb4d3b-926a-4a64-adae-f0b01f17c056
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2242862736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2242862736
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.4138116023
Short name T1798
Test name
Test status
Simulation time 159865539 ps
CPU time 0.76 seconds
Started Jul 11 05:59:43 PM PDT 24
Finished Jul 11 05:59:55 PM PDT 24
Peak memory 206332 kb
Host smart-758d3b32-3ec6-4e91-8665-27b1d855df37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41381
16023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.4138116023
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3917661233
Short name T128
Test name
Test status
Simulation time 222594503 ps
CPU time 0.82 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206224 kb
Host smart-4f690c93-7d45-4ee5-86de-5f784fd3c6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39176
61233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3917661233
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2495259192
Short name T1569
Test name
Test status
Simulation time 153310062 ps
CPU time 0.82 seconds
Started Jul 11 05:59:48 PM PDT 24
Finished Jul 11 05:59:58 PM PDT 24
Peak memory 206384 kb
Host smart-2666d33b-3199-4aa8-a174-5bb93809aa61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24952
59192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2495259192
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2402546463
Short name T692
Test name
Test status
Simulation time 168381800 ps
CPU time 0.8 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:51 PM PDT 24
Peak memory 206392 kb
Host smart-d499aa1c-61e4-4cda-b40e-dbb8ddac58bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24025
46463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2402546463
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2374647486
Short name T1426
Test name
Test status
Simulation time 201297019 ps
CPU time 0.82 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206144 kb
Host smart-b95930de-e1d8-405a-9e8f-1d82e8efc502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23746
47486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2374647486
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2365953366
Short name T175
Test name
Test status
Simulation time 138810409 ps
CPU time 0.75 seconds
Started Jul 11 05:59:38 PM PDT 24
Finished Jul 11 05:59:50 PM PDT 24
Peak memory 206408 kb
Host smart-8cbc5a98-9ac4-41c8-8e68-370939ad53f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23659
53366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2365953366
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.342428548
Short name T1390
Test name
Test status
Simulation time 196740001 ps
CPU time 0.88 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206312 kb
Host smart-15dba0df-e287-42e3-90c6-2861f2b3b8ed
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=342428548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.342428548
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3712831861
Short name T1070
Test name
Test status
Simulation time 221593723 ps
CPU time 0.84 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206544 kb
Host smart-643b3fb9-f88a-42e6-902d-83b7eaa0204b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37128
31861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3712831861
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.348139170
Short name T2696
Test name
Test status
Simulation time 41197022 ps
CPU time 0.68 seconds
Started Jul 11 05:59:56 PM PDT 24
Finished Jul 11 06:00:07 PM PDT 24
Peak memory 206288 kb
Host smart-6c577465-3c51-4c9e-86c1-e7a8116282f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34813
9170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.348139170
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3485519119
Short name T251
Test name
Test status
Simulation time 18232329782 ps
CPU time 43.6 seconds
Started Jul 11 05:59:54 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206576 kb
Host smart-1cbda9f3-e5d6-4b8c-8df8-609f4fdcf8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34855
19119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3485519119
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.704388928
Short name T368
Test name
Test status
Simulation time 170698152 ps
CPU time 0.83 seconds
Started Jul 11 05:59:42 PM PDT 24
Finished Jul 11 05:59:54 PM PDT 24
Peak memory 206388 kb
Host smart-cbcd7aad-b3ab-49c8-8b17-5c000d19535d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70438
8928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.704388928
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3233049052
Short name T1556
Test name
Test status
Simulation time 194902503 ps
CPU time 0.87 seconds
Started Jul 11 06:00:00 PM PDT 24
Finished Jul 11 06:00:10 PM PDT 24
Peak memory 206384 kb
Host smart-65d087f1-46f4-4cc5-ae56-6cde86843e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32330
49052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3233049052
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.857736832
Short name T343
Test name
Test status
Simulation time 227576825 ps
CPU time 0.89 seconds
Started Jul 11 05:59:47 PM PDT 24
Finished Jul 11 05:59:58 PM PDT 24
Peak memory 206340 kb
Host smart-ab9456b3-3de3-4522-a895-a800e6c3b2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85773
6832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.857736832
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.3014136843
Short name T1633
Test name
Test status
Simulation time 211409890 ps
CPU time 0.88 seconds
Started Jul 11 05:59:47 PM PDT 24
Finished Jul 11 05:59:58 PM PDT 24
Peak memory 206316 kb
Host smart-eb5ab1d6-0c77-42a6-bc85-3084243f0caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30141
36843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.3014136843
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1287409324
Short name T1080
Test name
Test status
Simulation time 155800256 ps
CPU time 0.81 seconds
Started Jul 11 05:59:45 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206400 kb
Host smart-051ba3a5-321b-408e-a50b-86cf7b5caa39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12874
09324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1287409324
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2727229824
Short name T508
Test name
Test status
Simulation time 145081219 ps
CPU time 0.75 seconds
Started Jul 11 05:59:57 PM PDT 24
Finished Jul 11 06:00:07 PM PDT 24
Peak memory 206380 kb
Host smart-243786bd-db16-4551-81d8-4fc538797b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27272
29824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2727229824
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.909375035
Short name T800
Test name
Test status
Simulation time 172160853 ps
CPU time 0.79 seconds
Started Jul 11 05:59:48 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206340 kb
Host smart-86cfec86-62d3-4c2c-b1b3-96d8f979ad25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90937
5035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.909375035
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2861888149
Short name T1903
Test name
Test status
Simulation time 249288472 ps
CPU time 0.95 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206328 kb
Host smart-619ff5d7-8a23-464f-8cd0-dde80d6560dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
88149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2861888149
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1060863545
Short name T2248
Test name
Test status
Simulation time 3453592790 ps
CPU time 33.27 seconds
Started Jul 11 05:59:52 PM PDT 24
Finished Jul 11 06:00:35 PM PDT 24
Peak memory 206636 kb
Host smart-b20891dd-9bd6-44e9-acf7-b7709fab118d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1060863545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1060863545
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1961772900
Short name T1782
Test name
Test status
Simulation time 161414573 ps
CPU time 0.8 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206336 kb
Host smart-99751a82-214f-484e-ab8c-09e60246dafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19617
72900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1961772900
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1829550292
Short name T515
Test name
Test status
Simulation time 194061422 ps
CPU time 0.81 seconds
Started Jul 11 05:59:57 PM PDT 24
Finished Jul 11 06:00:08 PM PDT 24
Peak memory 206396 kb
Host smart-1cef0486-d3f5-46b8-9ee5-6b86e867db95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18295
50292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1829550292
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.3349945970
Short name T708
Test name
Test status
Simulation time 1078966992 ps
CPU time 2.41 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:00:14 PM PDT 24
Peak memory 206580 kb
Host smart-81b4c994-17a9-4f54-a08d-f0c47066343a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33499
45970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.3349945970
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.4065855846
Short name T1977
Test name
Test status
Simulation time 4785510960 ps
CPU time 126.19 seconds
Started Jul 11 05:59:47 PM PDT 24
Finished Jul 11 06:02:03 PM PDT 24
Peak memory 206644 kb
Host smart-f3c3ffa1-f3ca-469c-b551-a68ba41ccd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40658
55846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.4065855846
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.4098371497
Short name T2010
Test name
Test status
Simulation time 38543319 ps
CPU time 0.7 seconds
Started Jul 11 06:00:05 PM PDT 24
Finished Jul 11 06:00:16 PM PDT 24
Peak memory 206368 kb
Host smart-b3d73b6e-4be1-4553-bbe7-88c99c9754da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4098371497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.4098371497
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1190723605
Short name T1109
Test name
Test status
Simulation time 4380791726 ps
CPU time 5.47 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:00:04 PM PDT 24
Peak memory 206712 kb
Host smart-074796cc-6c25-4ce1-9777-0ab056f2988f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1190723605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1190723605
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.931695501
Short name T2456
Test name
Test status
Simulation time 13369038883 ps
CPU time 12.66 seconds
Started Jul 11 05:59:55 PM PDT 24
Finished Jul 11 06:00:18 PM PDT 24
Peak memory 206612 kb
Host smart-8d8b3db2-ad20-47d4-9b32-478f703f5384
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=931695501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.931695501
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1853535175
Short name T2046
Test name
Test status
Simulation time 23402915481 ps
CPU time 22.88 seconds
Started Jul 11 06:00:02 PM PDT 24
Finished Jul 11 06:00:33 PM PDT 24
Peak memory 206712 kb
Host smart-9b34b188-5077-4233-86fd-ecb2efcfce2e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1853535175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1853535175
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2164044521
Short name T2158
Test name
Test status
Simulation time 184778753 ps
CPU time 0.85 seconds
Started Jul 11 05:59:43 PM PDT 24
Finished Jul 11 05:59:55 PM PDT 24
Peak memory 206388 kb
Host smart-20a99f41-a953-45ff-99b5-f3744e7752fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21640
44521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2164044521
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.76935192
Short name T747
Test name
Test status
Simulation time 206250910 ps
CPU time 0.82 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:23 PM PDT 24
Peak memory 206380 kb
Host smart-5791de75-eb0a-4b43-949b-5b9883ec477d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76935
192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.76935192
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3470059106
Short name T2105
Test name
Test status
Simulation time 426554930 ps
CPU time 1.29 seconds
Started Jul 11 05:59:45 PM PDT 24
Finished Jul 11 05:59:56 PM PDT 24
Peak memory 206384 kb
Host smart-320d4641-a298-4001-a644-a951625a5062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34700
59106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3470059106
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.112492410
Short name T110
Test name
Test status
Simulation time 994439496 ps
CPU time 2.55 seconds
Started Jul 11 05:59:50 PM PDT 24
Finished Jul 11 06:00:03 PM PDT 24
Peak memory 206580 kb
Host smart-f57cbfc3-f2de-415a-846e-91ec27637b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11249
2410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.112492410
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1311851298
Short name T1504
Test name
Test status
Simulation time 19438367987 ps
CPU time 33.77 seconds
Started Jul 11 05:59:51 PM PDT 24
Finished Jul 11 06:00:35 PM PDT 24
Peak memory 206688 kb
Host smart-154ba2c6-dbc3-47e9-80f7-678904bfe7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13118
51298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1311851298
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1001417940
Short name T2720
Test name
Test status
Simulation time 496497808 ps
CPU time 1.45 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206380 kb
Host smart-b70d93f4-1c60-4263-b807-a86e5b916032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10014
17940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1001417940
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2874775122
Short name T1417
Test name
Test status
Simulation time 139234336 ps
CPU time 0.77 seconds
Started Jul 11 05:59:45 PM PDT 24
Finished Jul 11 05:59:56 PM PDT 24
Peak memory 206384 kb
Host smart-1ef7f866-593a-4ca2-82bc-77428da1856e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
75122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2874775122
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2736579997
Short name T604
Test name
Test status
Simulation time 43488291 ps
CPU time 0.68 seconds
Started Jul 11 05:59:45 PM PDT 24
Finished Jul 11 05:59:56 PM PDT 24
Peak memory 206396 kb
Host smart-25184dcf-d00e-4156-96ba-9dd346053a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27365
79997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2736579997
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2069322368
Short name T1631
Test name
Test status
Simulation time 807457881 ps
CPU time 1.94 seconds
Started Jul 11 06:00:05 PM PDT 24
Finished Jul 11 06:00:17 PM PDT 24
Peak memory 206656 kb
Host smart-ddf4b31b-14cd-4855-92df-2b71f6aa132d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693
22368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2069322368
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2994272303
Short name T1675
Test name
Test status
Simulation time 259800734 ps
CPU time 1.5 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206580 kb
Host smart-e636902c-9323-4221-9ec9-6be731983e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29942
72303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2994272303
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.4004362635
Short name T376
Test name
Test status
Simulation time 215758183 ps
CPU time 0.85 seconds
Started Jul 11 05:59:50 PM PDT 24
Finished Jul 11 06:00:01 PM PDT 24
Peak memory 206388 kb
Host smart-4c3a96e4-ba80-4ba3-8091-6d83e65d2ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
62635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.4004362635
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3871951495
Short name T432
Test name
Test status
Simulation time 144230761 ps
CPU time 0.82 seconds
Started Jul 11 05:59:58 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206396 kb
Host smart-605e2bcb-e73f-44fd-8971-b8e28ca8c2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38719
51495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3871951495
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.867646747
Short name T992
Test name
Test status
Simulation time 219016940 ps
CPU time 0.91 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206364 kb
Host smart-0b228203-c180-4f2f-83be-0c920192adff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86764
6747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.867646747
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.2955587735
Short name T1199
Test name
Test status
Simulation time 6512102008 ps
CPU time 189.37 seconds
Started Jul 11 05:59:54 PM PDT 24
Finished Jul 11 06:03:13 PM PDT 24
Peak memory 206560 kb
Host smart-ab34b6e9-ed30-4e7d-8a48-cb3301fdca4b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2955587735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.2955587735
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.208126475
Short name T114
Test name
Test status
Simulation time 3836139656 ps
CPU time 28.65 seconds
Started Jul 11 05:59:52 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 206584 kb
Host smart-182e3bde-3e45-4064-9d26-af062f68f6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20812
6475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.208126475
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.4269761427
Short name T1047
Test name
Test status
Simulation time 210338900 ps
CPU time 0.85 seconds
Started Jul 11 05:59:44 PM PDT 24
Finished Jul 11 05:59:56 PM PDT 24
Peak memory 206380 kb
Host smart-50b35c7e-5530-4a99-a288-13be8a1342bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42697
61427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.4269761427
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2147376996
Short name T1993
Test name
Test status
Simulation time 23350226136 ps
CPU time 21.76 seconds
Started Jul 11 05:59:50 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206440 kb
Host smart-5601c6ba-c9a6-4556-80e1-5a8908cfe14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21473
76996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2147376996
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3587591573
Short name T2384
Test name
Test status
Simulation time 3292440671 ps
CPU time 4.7 seconds
Started Jul 11 05:59:51 PM PDT 24
Finished Jul 11 06:00:05 PM PDT 24
Peak memory 206448 kb
Host smart-6adb2f94-ee1e-4fe5-bb90-97ff2850d78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35875
91573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3587591573
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.655301599
Short name T2440
Test name
Test status
Simulation time 10518484825 ps
CPU time 291.42 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:04:50 PM PDT 24
Peak memory 206736 kb
Host smart-02c993c1-2851-4934-a6d3-61f7d556b181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65530
1599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.655301599
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.889039649
Short name T899
Test name
Test status
Simulation time 4958773218 ps
CPU time 34.12 seconds
Started Jul 11 05:59:56 PM PDT 24
Finished Jul 11 06:00:40 PM PDT 24
Peak memory 206652 kb
Host smart-db43365b-a007-4920-b905-228cb09b7ee5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=889039649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.889039649
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.3900416542
Short name T389
Test name
Test status
Simulation time 241290120 ps
CPU time 0.93 seconds
Started Jul 11 05:59:47 PM PDT 24
Finished Jul 11 05:59:58 PM PDT 24
Peak memory 206308 kb
Host smart-b63b648c-d713-4ee9-89ed-03b3226eb67a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3900416542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3900416542
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.4179661395
Short name T1686
Test name
Test status
Simulation time 203698956 ps
CPU time 0.86 seconds
Started Jul 11 05:59:47 PM PDT 24
Finished Jul 11 05:59:58 PM PDT 24
Peak memory 206312 kb
Host smart-ee52fd60-a6b1-4a1e-a0a6-d3f3888fe1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41796
61395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.4179661395
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1949140683
Short name T2171
Test name
Test status
Simulation time 6033662459 ps
CPU time 40.88 seconds
Started Jul 11 05:59:47 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206744 kb
Host smart-a613754c-7714-4f4e-8884-25cf6397da7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19491
40683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1949140683
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2418833533
Short name T1635
Test name
Test status
Simulation time 3934855105 ps
CPU time 111.54 seconds
Started Jul 11 05:59:48 PM PDT 24
Finished Jul 11 06:01:49 PM PDT 24
Peak memory 206632 kb
Host smart-e9729808-702b-40a6-942e-f891d1ec5c40
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2418833533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2418833533
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2294267145
Short name T532
Test name
Test status
Simulation time 198043948 ps
CPU time 0.83 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206396 kb
Host smart-1ffbaf66-2475-4b12-82a8-2e73a86fa31e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2294267145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2294267145
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2312602490
Short name T1980
Test name
Test status
Simulation time 158901900 ps
CPU time 0.78 seconds
Started Jul 11 05:59:45 PM PDT 24
Finished Jul 11 05:59:56 PM PDT 24
Peak memory 206400 kb
Host smart-22ab174e-a291-4a3a-b58a-c757d53b0540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
02490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2312602490
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3068480332
Short name T1319
Test name
Test status
Simulation time 209119071 ps
CPU time 0.89 seconds
Started Jul 11 05:59:50 PM PDT 24
Finished Jul 11 06:00:01 PM PDT 24
Peak memory 206384 kb
Host smart-6371d9bc-4f82-454e-8020-993a3de3c7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30684
80332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3068480332
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.995628668
Short name T723
Test name
Test status
Simulation time 160665299 ps
CPU time 0.78 seconds
Started Jul 11 06:00:12 PM PDT 24
Finished Jul 11 06:00:24 PM PDT 24
Peak memory 206372 kb
Host smart-3e66ce48-cd9f-4651-bcdc-624c4ff7d900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99562
8668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.995628668
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1681996517
Short name T1160
Test name
Test status
Simulation time 253355939 ps
CPU time 0.86 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:00:13 PM PDT 24
Peak memory 206332 kb
Host smart-5c2f2adc-ac10-4a8c-a8fb-bed8a7799503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16819
96517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1681996517
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3497630927
Short name T1180
Test name
Test status
Simulation time 209772583 ps
CPU time 0.89 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 05:59:57 PM PDT 24
Peak memory 206424 kb
Host smart-38f264e6-6ae0-4e7f-97af-3d2a74516653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34976
30927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3497630927
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3029929944
Short name T2240
Test name
Test status
Simulation time 149371766 ps
CPU time 0.77 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206388 kb
Host smart-20eb6792-e4a1-47dd-aefa-e74acb2a97ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30299
29944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3029929944
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2126987915
Short name T84
Test name
Test status
Simulation time 250427502 ps
CPU time 1.01 seconds
Started Jul 11 05:59:59 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206332 kb
Host smart-3dc66bf3-febc-4bd5-871b-21e4dabdba16
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2126987915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2126987915
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1312712196
Short name T42
Test name
Test status
Simulation time 137505284 ps
CPU time 0.76 seconds
Started Jul 11 05:59:56 PM PDT 24
Finished Jul 11 06:00:06 PM PDT 24
Peak memory 206388 kb
Host smart-4b685ecd-cdac-4d57-b54d-316852991478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13127
12196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1312712196
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2794229693
Short name T2610
Test name
Test status
Simulation time 46833936 ps
CPU time 0.69 seconds
Started Jul 11 05:59:47 PM PDT 24
Finished Jul 11 05:59:58 PM PDT 24
Peak memory 206360 kb
Host smart-4b2e150c-012f-4a86-81eb-ef683590507e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942
29693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2794229693
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1295156683
Short name T265
Test name
Test status
Simulation time 18004490230 ps
CPU time 40.61 seconds
Started Jul 11 05:59:48 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206728 kb
Host smart-8ecafeb9-5561-4ace-8285-2a67cd3e7d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12951
56683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1295156683
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1406996539
Short name T1081
Test name
Test status
Simulation time 212109271 ps
CPU time 0.93 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:00:13 PM PDT 24
Peak memory 206328 kb
Host smart-b585b8fc-0216-4bae-b369-fcf44f47773e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14069
96539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1406996539
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2379316992
Short name T2463
Test name
Test status
Simulation time 233094341 ps
CPU time 0.93 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:00:13 PM PDT 24
Peak memory 206320 kb
Host smart-4237eb27-95d7-4d24-9f76-a82b0902a134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
16992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2379316992
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.1035430432
Short name T2200
Test name
Test status
Simulation time 173759134 ps
CPU time 0.84 seconds
Started Jul 11 05:59:58 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206332 kb
Host smart-a8ca0887-9a05-4b78-95bc-5a8e169fb2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10354
30432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1035430432
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2253685249
Short name T2045
Test name
Test status
Simulation time 165506751 ps
CPU time 0.86 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206404 kb
Host smart-4bc7e59a-1298-463b-9cf3-75d0c369f9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22536
85249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2253685249
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.375103245
Short name T462
Test name
Test status
Simulation time 187397075 ps
CPU time 0.8 seconds
Started Jul 11 05:59:48 PM PDT 24
Finished Jul 11 05:59:58 PM PDT 24
Peak memory 206384 kb
Host smart-68d24dc5-3534-4eeb-a270-1e9c21f30220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
3245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.375103245
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3643748027
Short name T2247
Test name
Test status
Simulation time 178479832 ps
CPU time 0.78 seconds
Started Jul 11 05:59:50 PM PDT 24
Finished Jul 11 06:00:01 PM PDT 24
Peak memory 206372 kb
Host smart-e32f7f21-6e31-4a21-b1b6-fdbb25876497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36437
48027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3643748027
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3496527592
Short name T2361
Test name
Test status
Simulation time 144172534 ps
CPU time 0.78 seconds
Started Jul 11 05:59:55 PM PDT 24
Finished Jul 11 06:00:05 PM PDT 24
Peak memory 206388 kb
Host smart-78ed0579-99f3-4310-87d6-02b7ac767658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34965
27592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3496527592
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.418500919
Short name T590
Test name
Test status
Simulation time 211700950 ps
CPU time 0.94 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:00:13 PM PDT 24
Peak memory 206328 kb
Host smart-47b98d29-5f5f-4a46-bd50-b99024ae0ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41850
0919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.418500919
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3212653706
Short name T2297
Test name
Test status
Simulation time 5147341602 ps
CPU time 143.15 seconds
Started Jul 11 05:59:49 PM PDT 24
Finished Jul 11 06:02:22 PM PDT 24
Peak memory 206580 kb
Host smart-77f4c861-5460-4a7d-9230-8010ab4e768f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3212653706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3212653706
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.366765315
Short name T158
Test name
Test status
Simulation time 187533156 ps
CPU time 0.84 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:00:13 PM PDT 24
Peak memory 206332 kb
Host smart-cec7ef36-ebc6-40a8-a1a3-ca773fb2c9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
5315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.366765315
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.349063303
Short name T2081
Test name
Test status
Simulation time 208232422 ps
CPU time 0.86 seconds
Started Jul 11 05:59:55 PM PDT 24
Finished Jul 11 06:00:05 PM PDT 24
Peak memory 206360 kb
Host smart-c173ac4d-2b66-455c-885c-4aab51d51ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34906
3303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.349063303
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.3965426150
Short name T1943
Test name
Test status
Simulation time 1361978250 ps
CPU time 2.74 seconds
Started Jul 11 05:59:48 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 206624 kb
Host smart-b30e132d-3bc2-4440-ade9-7c11e22e14dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39654
26150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3965426150
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1809558536
Short name T339
Test name
Test status
Simulation time 7357779633 ps
CPU time 208.99 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:03:42 PM PDT 24
Peak memory 206620 kb
Host smart-03a68954-2295-4644-9be7-5e031ac6facc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18095
58536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1809558536
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2028212666
Short name T1862
Test name
Test status
Simulation time 49994756 ps
CPU time 0.7 seconds
Started Jul 11 06:00:08 PM PDT 24
Finished Jul 11 06:00:18 PM PDT 24
Peak memory 206448 kb
Host smart-7f0da001-20d1-4f8f-9a93-2e467651db88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2028212666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2028212666
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1910279089
Short name T1548
Test name
Test status
Simulation time 3874703532 ps
CPU time 4.68 seconds
Started Jul 11 05:59:57 PM PDT 24
Finished Jul 11 06:00:12 PM PDT 24
Peak memory 206432 kb
Host smart-c72bd414-1cbe-4955-b548-cbb7f4208ddd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1910279089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1910279089
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1210659421
Short name T214
Test name
Test status
Simulation time 13343204998 ps
CPU time 12.51 seconds
Started Jul 11 05:59:46 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206348 kb
Host smart-4b6ccf73-09c4-4819-9109-fee12565b1e2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1210659421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1210659421
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3165643512
Short name T1478
Test name
Test status
Simulation time 23376332235 ps
CPU time 23.42 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 206612 kb
Host smart-6a6433eb-be7c-4c95-87fa-67e34e9090e0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3165643512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3165643512
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2847914821
Short name T2368
Test name
Test status
Simulation time 153157975 ps
CPU time 0.84 seconds
Started Jul 11 05:59:58 PM PDT 24
Finished Jul 11 06:00:08 PM PDT 24
Peak memory 206364 kb
Host smart-a9e63588-08db-4686-86ad-ca3c527db06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479
14821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2847914821
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2370084600
Short name T2584
Test name
Test status
Simulation time 212427045 ps
CPU time 0.85 seconds
Started Jul 11 05:59:56 PM PDT 24
Finished Jul 11 06:00:07 PM PDT 24
Peak memory 206352 kb
Host smart-06dcbadb-8f3f-4f6b-b34b-fabea6616ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23700
84600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2370084600
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1949343069
Short name T2376
Test name
Test status
Simulation time 296648386 ps
CPU time 1.14 seconds
Started Jul 11 05:59:47 PM PDT 24
Finished Jul 11 05:59:58 PM PDT 24
Peak memory 206260 kb
Host smart-c8022db7-75fa-4bd0-b39c-69efde32f66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19493
43069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1949343069
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2022339775
Short name T1236
Test name
Test status
Simulation time 905110141 ps
CPU time 2.08 seconds
Started Jul 11 06:00:01 PM PDT 24
Finished Jul 11 06:00:12 PM PDT 24
Peak memory 206588 kb
Host smart-ac9467cd-ffbf-46f3-974b-0893d0651426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20223
39775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2022339775
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3927201276
Short name T182
Test name
Test status
Simulation time 6363195249 ps
CPU time 13.36 seconds
Started Jul 11 06:00:02 PM PDT 24
Finished Jul 11 06:00:23 PM PDT 24
Peak memory 206640 kb
Host smart-d1737eb7-0da1-4d82-9fda-facd5d5f401e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39272
01276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3927201276
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.689319078
Short name T344
Test name
Test status
Simulation time 353188187 ps
CPU time 1.19 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:00:26 PM PDT 24
Peak memory 206380 kb
Host smart-cf8a0d77-5146-49cc-92ab-d6a06f15ae90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68931
9078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.689319078
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3487072944
Short name T1560
Test name
Test status
Simulation time 139739456 ps
CPU time 0.76 seconds
Started Jul 11 05:59:59 PM PDT 24
Finished Jul 11 06:00:08 PM PDT 24
Peak memory 206372 kb
Host smart-7bc4d4d3-d987-4a20-8fac-d3c97cfbdfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34870
72944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3487072944
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.274226096
Short name T1914
Test name
Test status
Simulation time 33627979 ps
CPU time 0.69 seconds
Started Jul 11 05:59:57 PM PDT 24
Finished Jul 11 06:00:07 PM PDT 24
Peak memory 206380 kb
Host smart-380dcd4f-045f-402e-8023-71647b8bbd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
6096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.274226096
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3393577068
Short name T1786
Test name
Test status
Simulation time 855296626 ps
CPU time 2.04 seconds
Started Jul 11 05:59:56 PM PDT 24
Finished Jul 11 06:00:07 PM PDT 24
Peak memory 206644 kb
Host smart-7db0f63d-9997-457c-a21b-96e07396660a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33935
77068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3393577068
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1734245071
Short name T820
Test name
Test status
Simulation time 160013307 ps
CPU time 1.47 seconds
Started Jul 11 06:00:22 PM PDT 24
Finished Jul 11 06:00:33 PM PDT 24
Peak memory 206620 kb
Host smart-89abd684-b4b6-4004-91a8-515cf547a8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17342
45071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1734245071
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.607740815
Short name T1502
Test name
Test status
Simulation time 281024627 ps
CPU time 0.94 seconds
Started Jul 11 05:59:57 PM PDT 24
Finished Jul 11 06:00:08 PM PDT 24
Peak memory 206372 kb
Host smart-db136131-c421-45be-ba8c-0a06cc19d1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60774
0815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.607740815
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3037766669
Short name T125
Test name
Test status
Simulation time 146458362 ps
CPU time 0.8 seconds
Started Jul 11 05:59:57 PM PDT 24
Finished Jul 11 06:00:07 PM PDT 24
Peak memory 206396 kb
Host smart-319fc6d0-ab35-426f-a0d4-298f174e6969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30377
66669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3037766669
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.460515121
Short name T355
Test name
Test status
Simulation time 216130917 ps
CPU time 0.9 seconds
Started Jul 11 06:00:05 PM PDT 24
Finished Jul 11 06:00:17 PM PDT 24
Peak memory 206324 kb
Host smart-ddf39757-59b1-47aa-9fd1-bfdddbc45942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46051
5121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.460515121
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.40656956
Short name T1471
Test name
Test status
Simulation time 5091361082 ps
CPU time 46.94 seconds
Started Jul 11 05:59:55 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206644 kb
Host smart-f569285c-bbd6-4fdf-8299-00d6418c2d9d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=40656956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.40656956
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.1877804552
Short name T1305
Test name
Test status
Simulation time 13697480617 ps
CPU time 54.04 seconds
Started Jul 11 05:59:57 PM PDT 24
Finished Jul 11 06:01:01 PM PDT 24
Peak memory 206612 kb
Host smart-2a398f7e-a0ba-4cc3-9bc7-0f5a008cc3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18778
04552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.1877804552
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2239238413
Short name T1240
Test name
Test status
Simulation time 183980372 ps
CPU time 0.85 seconds
Started Jul 11 06:00:02 PM PDT 24
Finished Jul 11 06:00:11 PM PDT 24
Peak memory 206376 kb
Host smart-90b3fea5-0cc9-48fa-9b2c-7cdf13a496de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22392
38413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2239238413
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.772085883
Short name T2299
Test name
Test status
Simulation time 23329819276 ps
CPU time 28.91 seconds
Started Jul 11 05:59:58 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 206520 kb
Host smart-e9ab181e-c44b-48a0-9f27-b085b96da365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77208
5883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.772085883
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.823201253
Short name T1979
Test name
Test status
Simulation time 3274632068 ps
CPU time 4.37 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:33 PM PDT 24
Peak memory 206392 kb
Host smart-1de9a229-7f76-4517-98d0-7ad6d702a50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82320
1253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.823201253
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.430716608
Short name T1821
Test name
Test status
Simulation time 8463766647 ps
CPU time 57.5 seconds
Started Jul 11 06:00:02 PM PDT 24
Finished Jul 11 06:01:09 PM PDT 24
Peak memory 206692 kb
Host smart-81adddeb-4d03-4b39-a78d-bacad3a3905d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43071
6608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.430716608
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1884851530
Short name T2154
Test name
Test status
Simulation time 5459642962 ps
CPU time 145.32 seconds
Started Jul 11 05:59:56 PM PDT 24
Finished Jul 11 06:02:31 PM PDT 24
Peak memory 206636 kb
Host smart-38b4e370-cee6-49b7-81d4-2219fb52dcd7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1884851530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1884851530
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1539583179
Short name T1855
Test name
Test status
Simulation time 257496015 ps
CPU time 0.9 seconds
Started Jul 11 05:59:58 PM PDT 24
Finished Jul 11 06:00:08 PM PDT 24
Peak memory 206380 kb
Host smart-225c9231-4531-4ebf-ae5d-5ccbd6136d42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1539583179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1539583179
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.4213801839
Short name T2734
Test name
Test status
Simulation time 197793590 ps
CPU time 0.88 seconds
Started Jul 11 06:00:01 PM PDT 24
Finished Jul 11 06:00:11 PM PDT 24
Peak memory 206364 kb
Host smart-6f8db49b-4d9a-4397-8630-b9f8f1b8a7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42138
01839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.4213801839
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1706159908
Short name T1552
Test name
Test status
Simulation time 6146428257 ps
CPU time 174.86 seconds
Started Jul 11 05:59:53 PM PDT 24
Finished Jul 11 06:02:57 PM PDT 24
Peak memory 206576 kb
Host smart-8cf1942b-ba69-4009-89b7-472635619870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17061
59908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1706159908
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3868769044
Short name T2294
Test name
Test status
Simulation time 6425385064 ps
CPU time 43.44 seconds
Started Jul 11 05:59:54 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206708 kb
Host smart-b69cff52-a0a5-4c08-b66c-32a6b4888be0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3868769044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3868769044
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1658918927
Short name T947
Test name
Test status
Simulation time 154945310 ps
CPU time 0.78 seconds
Started Jul 11 05:59:58 PM PDT 24
Finished Jul 11 06:00:08 PM PDT 24
Peak memory 206312 kb
Host smart-87501ddf-676b-4804-82d7-e939bf502784
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1658918927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1658918927
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.391153351
Short name T1757
Test name
Test status
Simulation time 144073305 ps
CPU time 0.73 seconds
Started Jul 11 05:59:51 PM PDT 24
Finished Jul 11 06:00:02 PM PDT 24
Peak memory 206388 kb
Host smart-6795f3c9-bfe0-4bc0-a64d-31d481126bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39115
3351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.391153351
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2899168503
Short name T2522
Test name
Test status
Simulation time 231848250 ps
CPU time 0.89 seconds
Started Jul 11 06:00:06 PM PDT 24
Finished Jul 11 06:00:17 PM PDT 24
Peak memory 206380 kb
Host smart-33e53b6d-bf06-4f14-9804-6b8b4308d397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28991
68503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2899168503
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3997502542
Short name T2627
Test name
Test status
Simulation time 209158619 ps
CPU time 0.85 seconds
Started Jul 11 06:00:12 PM PDT 24
Finished Jul 11 06:00:24 PM PDT 24
Peak memory 206356 kb
Host smart-6d6b9482-ee03-44b0-99eb-7e78a3d4dfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39975
02542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3997502542
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1634223490
Short name T874
Test name
Test status
Simulation time 218944168 ps
CPU time 0.91 seconds
Started Jul 11 06:00:05 PM PDT 24
Finished Jul 11 06:00:15 PM PDT 24
Peak memory 206388 kb
Host smart-88faaa6f-cf88-443a-82d1-8c768ccac948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16342
23490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1634223490
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.36240842
Short name T1971
Test name
Test status
Simulation time 155054552 ps
CPU time 0.76 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 206380 kb
Host smart-34152eb3-da09-49e8-9acf-2be7923e723d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36240
842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.36240842
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.614148487
Short name T2646
Test name
Test status
Simulation time 236310863 ps
CPU time 0.95 seconds
Started Jul 11 06:00:03 PM PDT 24
Finished Jul 11 06:00:13 PM PDT 24
Peak memory 206372 kb
Host smart-b7b044bb-f5ff-4c85-8eb4-15bfae064d6f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=614148487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.614148487
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2331358948
Short name T2657
Test name
Test status
Simulation time 166934758 ps
CPU time 0.82 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:40 PM PDT 24
Peak memory 206376 kb
Host smart-2eb96760-9d16-4136-9eae-72a442d7537a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
58948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2331358948
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2257182696
Short name T2436
Test name
Test status
Simulation time 32008448 ps
CPU time 0.69 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:19 PM PDT 24
Peak memory 206396 kb
Host smart-79e67f4f-6821-425b-9bb8-e882fe851b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22571
82696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2257182696
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2432272835
Short name T264
Test name
Test status
Simulation time 17118040791 ps
CPU time 35.41 seconds
Started Jul 11 06:00:02 PM PDT 24
Finished Jul 11 06:00:45 PM PDT 24
Peak memory 206672 kb
Host smart-782d6022-7871-438d-a1c6-fdad58594b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24322
72835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2432272835
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.4278351655
Short name T890
Test name
Test status
Simulation time 211319984 ps
CPU time 0.92 seconds
Started Jul 11 06:00:04 PM PDT 24
Finished Jul 11 06:00:14 PM PDT 24
Peak memory 206336 kb
Host smart-4bc6ca3a-aaf4-412b-866b-e97e06ec6a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42783
51655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.4278351655
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2017565739
Short name T635
Test name
Test status
Simulation time 178245025 ps
CPU time 0.8 seconds
Started Jul 11 06:00:04 PM PDT 24
Finished Jul 11 06:00:14 PM PDT 24
Peak memory 206332 kb
Host smart-8fa79d16-96eb-4146-8b8e-66e07fe12157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20175
65739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2017565739
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2708689393
Short name T647
Test name
Test status
Simulation time 233105907 ps
CPU time 0.88 seconds
Started Jul 11 05:59:59 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206404 kb
Host smart-6d7ef812-72f5-4c8d-872c-41d44a7e926f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27086
89393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2708689393
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2468839072
Short name T1028
Test name
Test status
Simulation time 190456799 ps
CPU time 0.91 seconds
Started Jul 11 05:59:55 PM PDT 24
Finished Jul 11 06:00:05 PM PDT 24
Peak memory 206392 kb
Host smart-dfe023f2-738f-4dd5-b176-d38aefa752fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24688
39072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2468839072
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2713113282
Short name T2267
Test name
Test status
Simulation time 195368670 ps
CPU time 0.86 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206316 kb
Host smart-54c80f14-344b-40c5-81a7-15f114c83759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27131
13282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2713113282
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.215797057
Short name T1309
Test name
Test status
Simulation time 173645168 ps
CPU time 0.77 seconds
Started Jul 11 06:00:07 PM PDT 24
Finished Jul 11 06:00:18 PM PDT 24
Peak memory 206328 kb
Host smart-7a0e218d-ff3a-4e2c-9fa0-6fa52f1e0fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21579
7057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.215797057
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3927226253
Short name T1516
Test name
Test status
Simulation time 204039045 ps
CPU time 0.81 seconds
Started Jul 11 06:00:05 PM PDT 24
Finished Jul 11 06:00:16 PM PDT 24
Peak memory 206344 kb
Host smart-d414bdcb-1ba8-4372-98d7-f23f976eaa88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39272
26253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3927226253
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1105706257
Short name T707
Test name
Test status
Simulation time 249264943 ps
CPU time 0.97 seconds
Started Jul 11 06:00:00 PM PDT 24
Finished Jul 11 06:00:10 PM PDT 24
Peak memory 206400 kb
Host smart-043a37fd-571e-43d1-8686-ae7cc2215d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11057
06257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1105706257
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3217389781
Short name T2731
Test name
Test status
Simulation time 4221436599 ps
CPU time 28.97 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206656 kb
Host smart-469b4059-c566-4a12-b3ba-e4bef335aa7e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3217389781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3217389781
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3307387294
Short name T1955
Test name
Test status
Simulation time 196749902 ps
CPU time 0.86 seconds
Started Jul 11 05:59:58 PM PDT 24
Finished Jul 11 06:00:09 PM PDT 24
Peak memory 206376 kb
Host smart-a0f6630c-c14c-487e-81c4-e2b03bbb11e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33073
87294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3307387294
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.199287600
Short name T883
Test name
Test status
Simulation time 157383962 ps
CPU time 0.79 seconds
Started Jul 11 06:00:07 PM PDT 24
Finished Jul 11 06:00:17 PM PDT 24
Peak memory 206380 kb
Host smart-925c2f8d-ae2d-4722-97ab-ea8db6b294bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19928
7600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.199287600
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1611064778
Short name T1003
Test name
Test status
Simulation time 455111196 ps
CPU time 1.24 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:20 PM PDT 24
Peak memory 206388 kb
Host smart-03887860-368e-4370-87a6-e836e5651376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16110
64778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1611064778
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3904746170
Short name T2452
Test name
Test status
Simulation time 4188770420 ps
CPU time 28.82 seconds
Started Jul 11 06:00:01 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206696 kb
Host smart-08d83b35-64ad-4721-97c0-90b0d31ae521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39047
46170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3904746170
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1655737569
Short name T1164
Test name
Test status
Simulation time 30094846 ps
CPU time 0.69 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:00:25 PM PDT 24
Peak memory 206424 kb
Host smart-d94ba6d6-bd2e-4a72-9f87-10e14b4e11e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1655737569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1655737569
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1486409865
Short name T2012
Test name
Test status
Simulation time 4332559304 ps
CPU time 5.24 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:00:29 PM PDT 24
Peak memory 206452 kb
Host smart-fb84344c-b463-4c28-a23f-ba1aaf7ca56e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1486409865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1486409865
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2309548838
Short name T2173
Test name
Test status
Simulation time 13335828359 ps
CPU time 13.47 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 206440 kb
Host smart-a3745a63-5b6a-4ace-83ee-b2efb7874959
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2309548838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2309548838
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3050177843
Short name T15
Test name
Test status
Simulation time 23355869072 ps
CPU time 21.92 seconds
Started Jul 11 06:00:16 PM PDT 24
Finished Jul 11 06:00:49 PM PDT 24
Peak memory 206708 kb
Host smart-ab2b2017-1171-44e4-90e9-7941e8fc487c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3050177843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3050177843
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1998126487
Short name T2195
Test name
Test status
Simulation time 181412149 ps
CPU time 0.82 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:19 PM PDT 24
Peak memory 206392 kb
Host smart-58993dc9-4cfe-400d-be95-6524ff2badeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981
26487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1998126487
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3283391205
Short name T1266
Test name
Test status
Simulation time 227420785 ps
CPU time 0.82 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:00:25 PM PDT 24
Peak memory 206400 kb
Host smart-031693ac-8754-4ea8-b331-bad062d1a22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32833
91205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3283391205
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3483427395
Short name T626
Test name
Test status
Simulation time 137591897 ps
CPU time 0.8 seconds
Started Jul 11 06:00:21 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206324 kb
Host smart-b80495f9-ddb5-44ff-b776-890d4d5ac7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34834
27395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3483427395
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1791371729
Short name T907
Test name
Test status
Simulation time 1509426776 ps
CPU time 3.12 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206600 kb
Host smart-62a1848a-ef39-4bd3-a554-28ea51c41bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
71729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1791371729
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1560834593
Short name T2152
Test name
Test status
Simulation time 14096496544 ps
CPU time 24.64 seconds
Started Jul 11 06:00:06 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 206704 kb
Host smart-5779c4e8-64f0-41d7-b2ba-1e83880ffc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15608
34593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1560834593
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.375405048
Short name T387
Test name
Test status
Simulation time 393909278 ps
CPU time 1.3 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:20 PM PDT 24
Peak memory 206332 kb
Host smart-d7cfa1d7-8996-482c-9166-e58ca79a0675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37540
5048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.375405048
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3887425203
Short name T724
Test name
Test status
Simulation time 154281348 ps
CPU time 0.83 seconds
Started Jul 11 06:00:07 PM PDT 24
Finished Jul 11 06:00:17 PM PDT 24
Peak memory 206392 kb
Host smart-b8afb7a8-7465-44ed-bd81-a2e6b6f986c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
25203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3887425203
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.567689271
Short name T2673
Test name
Test status
Simulation time 45988017 ps
CPU time 0.68 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 206356 kb
Host smart-65be0f5f-e2d3-4ccf-9bfd-896a8e7962e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56768
9271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.567689271
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2699290515
Short name T254
Test name
Test status
Simulation time 880349908 ps
CPU time 2.03 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:23 PM PDT 24
Peak memory 206596 kb
Host smart-78745d02-500b-4dee-8564-954d92f31d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26992
90515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2699290515
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1946026897
Short name T1069
Test name
Test status
Simulation time 423394604 ps
CPU time 2.44 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:23 PM PDT 24
Peak memory 206632 kb
Host smart-8f6a0c9b-f5e7-4934-b526-91ed9355d8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19460
26897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1946026897
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.4209052475
Short name T1715
Test name
Test status
Simulation time 211297346 ps
CPU time 0.86 seconds
Started Jul 11 06:00:17 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 206384 kb
Host smart-475a3947-21f2-40b9-92eb-f1dece5d1ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42090
52475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.4209052475
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1672707341
Short name T352
Test name
Test status
Simulation time 141501569 ps
CPU time 0.75 seconds
Started Jul 11 06:00:07 PM PDT 24
Finished Jul 11 06:00:17 PM PDT 24
Peak memory 206380 kb
Host smart-b283ed74-050e-4d07-8607-87fb205bf021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16727
07341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1672707341
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.220923033
Short name T1342
Test name
Test status
Simulation time 195297334 ps
CPU time 0.89 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:19 PM PDT 24
Peak memory 206384 kb
Host smart-25fa06b1-1fbf-43f8-9502-95bb9c664960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
3033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.220923033
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.4164441296
Short name T1185
Test name
Test status
Simulation time 5606855024 ps
CPU time 156.65 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:02:56 PM PDT 24
Peak memory 206656 kb
Host smart-55d9ecb8-e6e0-40e9-b654-a93438d925ad
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4164441296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.4164441296
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.1803562847
Short name T1495
Test name
Test status
Simulation time 7371003854 ps
CPU time 58.16 seconds
Started Jul 11 06:00:27 PM PDT 24
Finished Jul 11 06:01:34 PM PDT 24
Peak memory 206680 kb
Host smart-defe515c-624d-4194-95f4-8f694d6a1641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18035
62847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.1803562847
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3669913607
Short name T529
Test name
Test status
Simulation time 237985234 ps
CPU time 0.96 seconds
Started Jul 11 06:00:14 PM PDT 24
Finished Jul 11 06:00:26 PM PDT 24
Peak memory 206328 kb
Host smart-3925a7ad-6e5a-4e49-8856-3e6735bbe9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36699
13607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3669913607
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1108110968
Short name T713
Test name
Test status
Simulation time 23352479040 ps
CPU time 23.93 seconds
Started Jul 11 06:00:05 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206444 kb
Host smart-f69e1329-3423-47a1-b319-4d7ac8fdd0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
10968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1108110968
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2931630553
Short name T467
Test name
Test status
Simulation time 3318746494 ps
CPU time 3.9 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:21 PM PDT 24
Peak memory 206360 kb
Host smart-10752c97-c6c0-451a-bbf3-b97764a36868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29316
30553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2931630553
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.3673303118
Short name T445
Test name
Test status
Simulation time 10347416787 ps
CPU time 92.73 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:01:57 PM PDT 24
Peak memory 206736 kb
Host smart-351ab118-22fd-4dd6-97bb-9dfcb13ae812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36733
03118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.3673303118
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2159710579
Short name T384
Test name
Test status
Simulation time 6031079617 ps
CPU time 41.01 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:01:21 PM PDT 24
Peak memory 206620 kb
Host smart-261c6717-0cfe-4209-aa87-780b2d5a86e5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2159710579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2159710579
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3290530406
Short name T2117
Test name
Test status
Simulation time 273509693 ps
CPU time 0.91 seconds
Started Jul 11 06:00:08 PM PDT 24
Finished Jul 11 06:00:18 PM PDT 24
Peak memory 206364 kb
Host smart-93ecc8c2-e9c3-45f9-873e-19e2897d511f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3290530406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3290530406
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1708065751
Short name T19
Test name
Test status
Simulation time 205562450 ps
CPU time 0.86 seconds
Started Jul 11 06:00:06 PM PDT 24
Finished Jul 11 06:00:17 PM PDT 24
Peak memory 206388 kb
Host smart-372e36a8-af39-489a-8be4-e5713e2bfb4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17080
65751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1708065751
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.1950000499
Short name T937
Test name
Test status
Simulation time 5540551662 ps
CPU time 39.85 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:01:04 PM PDT 24
Peak memory 206576 kb
Host smart-c7930203-c16d-4451-bee2-c364802f5939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19500
00499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.1950000499
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2197787658
Short name T2453
Test name
Test status
Simulation time 7490675718 ps
CPU time 70.28 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 206664 kb
Host smart-874b3c88-fdee-4cff-a947-8afa016f4be5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2197787658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2197787658
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2216931639
Short name T2245
Test name
Test status
Simulation time 170142250 ps
CPU time 0.78 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206376 kb
Host smart-9d1f81af-316e-4ae6-932d-ffaa9fd9e005
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2216931639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2216931639
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.737832013
Short name T2260
Test name
Test status
Simulation time 176295956 ps
CPU time 0.86 seconds
Started Jul 11 06:00:15 PM PDT 24
Finished Jul 11 06:00:27 PM PDT 24
Peak memory 206392 kb
Host smart-fa28bf46-7fc4-44b8-929f-32572e35fa8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73783
2013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.737832013
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.910954630
Short name T137
Test name
Test status
Simulation time 180465270 ps
CPU time 0.86 seconds
Started Jul 11 06:00:12 PM PDT 24
Finished Jul 11 06:00:24 PM PDT 24
Peak memory 206352 kb
Host smart-4e55603b-4b2b-46ea-a7a0-dadd20715916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91095
4630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.910954630
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2023183867
Short name T1488
Test name
Test status
Simulation time 199541605 ps
CPU time 0.85 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:22 PM PDT 24
Peak memory 206396 kb
Host smart-3e6052d5-0b46-43e2-a95d-e2a54f46cb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20231
83867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2023183867
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3977073615
Short name T1098
Test name
Test status
Simulation time 220260494 ps
CPU time 0.81 seconds
Started Jul 11 06:00:12 PM PDT 24
Finished Jul 11 06:00:25 PM PDT 24
Peak memory 206400 kb
Host smart-a6f6b10e-8848-4d61-b2e9-894b22708434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39770
73615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3977073615
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1583694151
Short name T2412
Test name
Test status
Simulation time 187783708 ps
CPU time 0.8 seconds
Started Jul 11 06:00:14 PM PDT 24
Finished Jul 11 06:00:26 PM PDT 24
Peak memory 206468 kb
Host smart-d139a306-a18a-4656-80c8-8bc32c1dca3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15836
94151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1583694151
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1915603671
Short name T860
Test name
Test status
Simulation time 158469179 ps
CPU time 0.78 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:00:23 PM PDT 24
Peak memory 206356 kb
Host smart-212acfe9-1bbc-42d8-ba18-b55a03fd13a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156
03671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1915603671
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.4100682574
Short name T2179
Test name
Test status
Simulation time 223808043 ps
CPU time 0.95 seconds
Started Jul 11 06:00:20 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 206328 kb
Host smart-0faefa08-91c7-4ea4-a40b-bd2190760e8e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4100682574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.4100682574
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2998218112
Short name T1131
Test name
Test status
Simulation time 135682812 ps
CPU time 0.74 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:20 PM PDT 24
Peak memory 206376 kb
Host smart-4125d595-849d-459f-b590-d2d9f87abda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29982
18112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2998218112
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.4074737882
Short name T1421
Test name
Test status
Simulation time 46985781 ps
CPU time 0.66 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206408 kb
Host smart-a47ac413-c08e-428f-b6b2-710c652b732c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40747
37882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.4074737882
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1976462898
Short name T562
Test name
Test status
Simulation time 18958268355 ps
CPU time 46.25 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:01:06 PM PDT 24
Peak memory 206700 kb
Host smart-bdd43b84-cd38-499c-b9e1-27f34f9e4e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
62898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1976462898
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3484088478
Short name T301
Test name
Test status
Simulation time 206201565 ps
CPU time 0.9 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206388 kb
Host smart-8522448e-cdb4-4507-9493-fbe168ad5987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34840
88478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3484088478
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.346415032
Short name T1711
Test name
Test status
Simulation time 207139810 ps
CPU time 0.91 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:00:25 PM PDT 24
Peak memory 206256 kb
Host smart-fa7156e8-bf9e-479d-8cee-c2a5a98428bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34641
5032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.346415032
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.4107537164
Short name T757
Test name
Test status
Simulation time 165501200 ps
CPU time 0.82 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:20 PM PDT 24
Peak memory 206396 kb
Host smart-bde8ba4a-e1c6-4e64-81c8-a0f7cf3c0caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41075
37164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.4107537164
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3244762972
Short name T2686
Test name
Test status
Simulation time 172758621 ps
CPU time 0.81 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:21 PM PDT 24
Peak memory 206268 kb
Host smart-45cccf6f-71bb-46f4-b377-e6c4f7fe3513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32447
62972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3244762972
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3908173124
Short name T2623
Test name
Test status
Simulation time 225267432 ps
CPU time 0.86 seconds
Started Jul 11 06:00:14 PM PDT 24
Finished Jul 11 06:00:26 PM PDT 24
Peak memory 206364 kb
Host smart-d5d5e0a4-d62c-4fbc-8cc5-ca554269fcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
73124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3908173124
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2643120306
Short name T2150
Test name
Test status
Simulation time 206534453 ps
CPU time 0.83 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206384 kb
Host smart-56ab8703-fdd7-4a9b-bcba-26b8a8c4e161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26431
20306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2643120306
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.316610023
Short name T2702
Test name
Test status
Simulation time 162418406 ps
CPU time 0.8 seconds
Started Jul 11 06:00:17 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 206300 kb
Host smart-0dc26cef-effa-4e22-9406-8732808d2790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31661
0023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.316610023
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3675607403
Short name T594
Test name
Test status
Simulation time 250933032 ps
CPU time 0.95 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206384 kb
Host smart-aec221eb-1c43-4b7c-9df3-81c1c9c83753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36756
07403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3675607403
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1857341498
Short name T1843
Test name
Test status
Simulation time 5935112780 ps
CPU time 161.98 seconds
Started Jul 11 06:00:11 PM PDT 24
Finished Jul 11 06:03:04 PM PDT 24
Peak memory 206596 kb
Host smart-f5d4d092-e3c0-4f7c-aeb5-e12fc9140082
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1857341498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1857341498
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1694744273
Short name T1361
Test name
Test status
Simulation time 172844378 ps
CPU time 0.82 seconds
Started Jul 11 06:00:26 PM PDT 24
Finished Jul 11 06:00:36 PM PDT 24
Peak memory 206332 kb
Host smart-e9216f38-a420-475e-93f3-c89e7d23d313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16947
44273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1694744273
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3101349378
Short name T1469
Test name
Test status
Simulation time 186442326 ps
CPU time 0.83 seconds
Started Jul 11 06:00:10 PM PDT 24
Finished Jul 11 06:00:20 PM PDT 24
Peak memory 206260 kb
Host smart-145f1082-0709-429e-bf8f-6e15a2366deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31013
49378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3101349378
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.428988159
Short name T530
Test name
Test status
Simulation time 1086693117 ps
CPU time 2.34 seconds
Started Jul 11 06:00:18 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 206720 kb
Host smart-8b644c31-d7d0-451d-bc30-cf5e7b5e0576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42898
8159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.428988159
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.57132979
Short name T1050
Test name
Test status
Simulation time 6540313083 ps
CPU time 183.86 seconds
Started Jul 11 06:00:22 PM PDT 24
Finished Jul 11 06:03:35 PM PDT 24
Peak memory 206576 kb
Host smart-d7141d3d-1fc2-4cf3-a4e6-199a14090b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57132
979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.57132979
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2664491088
Short name T2724
Test name
Test status
Simulation time 69206851 ps
CPU time 0.67 seconds
Started Jul 11 06:00:34 PM PDT 24
Finished Jul 11 06:00:45 PM PDT 24
Peak memory 206448 kb
Host smart-53b9737c-68b6-4866-b246-1c967ba1277a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2664491088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2664491088
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3103351297
Short name T2123
Test name
Test status
Simulation time 3716920127 ps
CPU time 4.62 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:00:29 PM PDT 24
Peak memory 206632 kb
Host smart-37a9efb2-487d-4f5f-bd03-1fc73cb0a3c1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3103351297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3103351297
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.594623353
Short name T719
Test name
Test status
Simulation time 13520839675 ps
CPU time 12.54 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 206684 kb
Host smart-c339853a-5ebb-4ead-a292-47e02b26245d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=594623353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.594623353
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3985557099
Short name T844
Test name
Test status
Simulation time 23389603652 ps
CPU time 26.67 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206320 kb
Host smart-a0d0da7b-6a01-4b58-8dbd-1581dadc8bd5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3985557099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3985557099
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3976767549
Short name T2642
Test name
Test status
Simulation time 182113844 ps
CPU time 0.89 seconds
Started Jul 11 06:00:09 PM PDT 24
Finished Jul 11 06:00:19 PM PDT 24
Peak memory 206312 kb
Host smart-8163c29a-e4ed-43a6-8502-7ca479366a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
67549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3976767549
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3200173277
Short name T550
Test name
Test status
Simulation time 149834292 ps
CPU time 0.76 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206420 kb
Host smart-b8e8428a-4178-4f50-aadf-becea09d5fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32001
73277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3200173277
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.1179078341
Short name T1864
Test name
Test status
Simulation time 341502881 ps
CPU time 1.07 seconds
Started Jul 11 06:00:12 PM PDT 24
Finished Jul 11 06:00:25 PM PDT 24
Peak memory 206328 kb
Host smart-b98fa7f0-8bcb-4594-be3d-0d2f37723fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11790
78341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.1179078341
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.754092847
Short name T830
Test name
Test status
Simulation time 892850470 ps
CPU time 2.08 seconds
Started Jul 11 06:00:16 PM PDT 24
Finished Jul 11 06:00:29 PM PDT 24
Peak memory 206592 kb
Host smart-07b6626e-4897-492f-8504-cbd958a479f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75409
2847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.754092847
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.496113917
Short name T2538
Test name
Test status
Simulation time 7297663439 ps
CPU time 15.75 seconds
Started Jul 11 06:00:12 PM PDT 24
Finished Jul 11 06:00:40 PM PDT 24
Peak memory 206656 kb
Host smart-da9de663-307a-4e82-8a84-707766177bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49611
3917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.496113917
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2528280921
Short name T322
Test name
Test status
Simulation time 360953869 ps
CPU time 1.26 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206376 kb
Host smart-fdb11502-75dd-4861-909c-e406419776a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25282
80921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2528280921
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.4031930365
Short name T1139
Test name
Test status
Simulation time 153841978 ps
CPU time 0.8 seconds
Started Jul 11 06:00:25 PM PDT 24
Finished Jul 11 06:00:34 PM PDT 24
Peak memory 206388 kb
Host smart-700a73fe-2d08-49e6-a1db-7a29fc62dc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40319
30365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.4031930365
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.366721720
Short name T1530
Test name
Test status
Simulation time 36537872 ps
CPU time 0.65 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206036 kb
Host smart-ada1890e-2a7d-4acc-bf55-b3427c133f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36672
1720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.366721720
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2260143992
Short name T2246
Test name
Test status
Simulation time 909801053 ps
CPU time 2.1 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 206588 kb
Host smart-e451291e-1921-4403-8937-943caf331ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22601
43992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2260143992
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3428105645
Short name T2148
Test name
Test status
Simulation time 252661231 ps
CPU time 1.67 seconds
Started Jul 11 06:00:18 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206556 kb
Host smart-ca614cb0-070a-43ae-a0fd-b709ad3f0891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
05645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3428105645
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.4237604849
Short name T2664
Test name
Test status
Simulation time 204382495 ps
CPU time 0.83 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206344 kb
Host smart-acef281b-75cc-4830-a980-96cc7f02b0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42376
04849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.4237604849
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2273440924
Short name T2526
Test name
Test status
Simulation time 148085258 ps
CPU time 0.83 seconds
Started Jul 11 06:00:24 PM PDT 24
Finished Jul 11 06:00:33 PM PDT 24
Peak memory 206380 kb
Host smart-074b8165-3b52-4afb-a6de-f78b17efbc85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22734
40924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2273440924
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3019198220
Short name T2641
Test name
Test status
Simulation time 189805057 ps
CPU time 0.82 seconds
Started Jul 11 06:00:14 PM PDT 24
Finished Jul 11 06:00:26 PM PDT 24
Peak memory 206380 kb
Host smart-6ed63530-a8d0-422f-bb05-28eb5f25d8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30191
98220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3019198220
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.51451487
Short name T2339
Test name
Test status
Simulation time 5943663564 ps
CPU time 165.32 seconds
Started Jul 11 06:00:13 PM PDT 24
Finished Jul 11 06:03:10 PM PDT 24
Peak memory 206672 kb
Host smart-e8260ce1-32be-4332-aa9f-7a6b1da7b7b8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=51451487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.51451487
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.1703271703
Short name T1755
Test name
Test status
Simulation time 11357807103 ps
CPU time 92.27 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206700 kb
Host smart-160adc32-879b-459c-9822-935b8015567f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17032
71703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.1703271703
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.3538794801
Short name T927
Test name
Test status
Simulation time 291423282 ps
CPU time 0.94 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:30 PM PDT 24
Peak memory 206368 kb
Host smart-bc5fe903-9243-473f-a252-6ce3d5e3c4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35387
94801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3538794801
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.418930155
Short name T2476
Test name
Test status
Simulation time 23352657540 ps
CPU time 22.73 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:00:52 PM PDT 24
Peak memory 206444 kb
Host smart-0cc20db5-3908-4d3a-af1a-0f224f89f5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41893
0155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.418930155
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.4240350542
Short name T632
Test name
Test status
Simulation time 3324897064 ps
CPU time 3.84 seconds
Started Jul 11 06:00:26 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206448 kb
Host smart-505b6de0-c4cd-4d43-8fd5-2e9030dc14bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
50542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.4240350542
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.148630111
Short name T2719
Test name
Test status
Simulation time 8908312115 ps
CPU time 244.75 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:04:43 PM PDT 24
Peak memory 206656 kb
Host smart-b51e703e-82d4-4088-8521-af1426aa1a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14863
0111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.148630111
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1724585193
Short name T2022
Test name
Test status
Simulation time 3923534488 ps
CPU time 104.74 seconds
Started Jul 11 06:00:17 PM PDT 24
Finished Jul 11 06:02:13 PM PDT 24
Peak memory 206632 kb
Host smart-c3faced2-5860-4f5c-b9a2-83da1c7c562b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1724585193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1724585193
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1033320355
Short name T1415
Test name
Test status
Simulation time 262879997 ps
CPU time 0.97 seconds
Started Jul 11 06:00:32 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206376 kb
Host smart-14e8d6f3-e100-46b5-a29e-afddb17247c6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1033320355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1033320355
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2687924468
Short name T1434
Test name
Test status
Simulation time 198077772 ps
CPU time 0.88 seconds
Started Jul 11 06:00:26 PM PDT 24
Finished Jul 11 06:00:36 PM PDT 24
Peak memory 206404 kb
Host smart-51532d36-9524-44b9-bca0-9a0f776a055f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26879
24468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2687924468
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1892813576
Short name T1534
Test name
Test status
Simulation time 5397763735 ps
CPU time 146.93 seconds
Started Jul 11 06:00:21 PM PDT 24
Finished Jul 11 06:02:57 PM PDT 24
Peak memory 206664 kb
Host smart-bb300486-6741-488c-bf07-6ce9420562af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18928
13576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1892813576
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.2033348008
Short name T1684
Test name
Test status
Simulation time 5397767484 ps
CPU time 50.2 seconds
Started Jul 11 06:00:21 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206652 kb
Host smart-2d552b2a-c2b7-41d5-b700-466c60be3aac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2033348008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.2033348008
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2862017548
Short name T1936
Test name
Test status
Simulation time 149502072 ps
CPU time 0.78 seconds
Started Jul 11 06:00:17 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 206388 kb
Host smart-e0b7b963-6554-4111-baab-dac09cb11ebb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2862017548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2862017548
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1695420314
Short name T518
Test name
Test status
Simulation time 190358451 ps
CPU time 0.81 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206340 kb
Host smart-bf0ce3be-f037-4eb8-919c-47d13f9cc175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16954
20314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1695420314
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1392177169
Short name T1990
Test name
Test status
Simulation time 227828177 ps
CPU time 0.94 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 206400 kb
Host smart-0a51c99c-93ae-4975-a074-68b25c389984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13921
77169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1392177169
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3482341736
Short name T828
Test name
Test status
Simulation time 196788589 ps
CPU time 0.85 seconds
Started Jul 11 06:00:24 PM PDT 24
Finished Jul 11 06:00:33 PM PDT 24
Peak memory 206404 kb
Host smart-26fc9c29-2c06-45bf-9559-90be607cd67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34823
41736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3482341736
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3216157198
Short name T401
Test name
Test status
Simulation time 209978973 ps
CPU time 0.84 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206376 kb
Host smart-435a459c-f0af-40c8-abf6-512f2bb9464c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32161
57198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3216157198
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2390888202
Short name T2445
Test name
Test status
Simulation time 153001094 ps
CPU time 0.81 seconds
Started Jul 11 06:00:32 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206408 kb
Host smart-27b829a3-232e-4c7a-9950-1ff1937d6b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23908
88202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2390888202
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2566984338
Short name T177
Test name
Test status
Simulation time 163699823 ps
CPU time 0.79 seconds
Started Jul 11 06:00:26 PM PDT 24
Finished Jul 11 06:00:36 PM PDT 24
Peak memory 206332 kb
Host smart-05a358ac-75f1-4fd0-8d62-efb39a7bfdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25669
84338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2566984338
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2410059292
Short name T2059
Test name
Test status
Simulation time 216945656 ps
CPU time 0.89 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206348 kb
Host smart-99b4047a-1f47-4c1d-9fbc-36c58b65d518
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2410059292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2410059292
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.917546773
Short name T1626
Test name
Test status
Simulation time 135024384 ps
CPU time 0.76 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206404 kb
Host smart-90ee1b2f-87c0-49bb-8b29-dbe7798f6ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91754
6773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.917546773
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1110202234
Short name T2451
Test name
Test status
Simulation time 58823759 ps
CPU time 0.73 seconds
Started Jul 11 06:00:17 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 206360 kb
Host smart-54489b18-4187-4ac9-9f8e-cf29bc1f147b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11102
02234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1110202234
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.4002720988
Short name T2331
Test name
Test status
Simulation time 10625506410 ps
CPU time 22.49 seconds
Started Jul 11 06:00:18 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206616 kb
Host smart-b1a0daed-c4f7-4413-adba-9a52161e1b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40027
20988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.4002720988
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3394567984
Short name T2669
Test name
Test status
Simulation time 221498062 ps
CPU time 0.82 seconds
Started Jul 11 06:00:17 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 206384 kb
Host smart-bd500ccb-f8b5-43a9-9e8c-bc222a22b40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33945
67984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3394567984
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.704603801
Short name T2378
Test name
Test status
Simulation time 149820747 ps
CPU time 0.79 seconds
Started Jul 11 06:00:22 PM PDT 24
Finished Jul 11 06:00:32 PM PDT 24
Peak memory 206384 kb
Host smart-073a623c-06a2-4c84-9df5-53d190a48ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70460
3801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.704603801
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3077961559
Short name T2575
Test name
Test status
Simulation time 158658834 ps
CPU time 0.8 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:00:42 PM PDT 24
Peak memory 206352 kb
Host smart-6e867990-26e8-487c-a23f-ddf7afd1a300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30779
61559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3077961559
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3580426204
Short name T2108
Test name
Test status
Simulation time 172243082 ps
CPU time 0.82 seconds
Started Jul 11 06:00:18 PM PDT 24
Finished Jul 11 06:00:29 PM PDT 24
Peak memory 206404 kb
Host smart-43566c72-fb2c-4d6f-9493-bf5fd426e4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35804
26204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3580426204
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.1715227765
Short name T794
Test name
Test status
Simulation time 139278570 ps
CPU time 0.77 seconds
Started Jul 11 06:00:15 PM PDT 24
Finished Jul 11 06:00:27 PM PDT 24
Peak memory 206332 kb
Host smart-d69881af-9cac-46de-b8c1-6db59b2afe50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17152
27765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1715227765
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1029644130
Short name T1602
Test name
Test status
Simulation time 147271993 ps
CPU time 0.74 seconds
Started Jul 11 06:00:21 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 206400 kb
Host smart-98206802-1f3c-4bab-96d4-708e55f685f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10296
44130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1029644130
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.981947641
Short name T931
Test name
Test status
Simulation time 156838170 ps
CPU time 0.81 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206340 kb
Host smart-2554336b-4b36-4028-a03f-3355284682f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98194
7641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.981947641
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2548285873
Short name T1832
Test name
Test status
Simulation time 261606443 ps
CPU time 0.99 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:46 PM PDT 24
Peak memory 206340 kb
Host smart-ab2ff852-02e2-4c7a-b63c-e6c3b1b2619e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
85873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2548285873
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2224659697
Short name T172
Test name
Test status
Simulation time 5283516559 ps
CPU time 49.06 seconds
Started Jul 11 06:00:19 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206620 kb
Host smart-56e052ea-fdd4-409b-9565-36ddfd1e73d3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2224659697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2224659697
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3602445966
Short name T548
Test name
Test status
Simulation time 185783665 ps
CPU time 0.81 seconds
Started Jul 11 06:00:25 PM PDT 24
Finished Jul 11 06:00:35 PM PDT 24
Peak memory 206408 kb
Host smart-af4c03aa-e98b-4eb8-8a8e-1d4e0b5d2333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
45966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3602445966
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3605555162
Short name T593
Test name
Test status
Simulation time 161087270 ps
CPU time 0.81 seconds
Started Jul 11 06:00:24 PM PDT 24
Finished Jul 11 06:00:34 PM PDT 24
Peak memory 206308 kb
Host smart-783ee760-1c3a-4907-b7b5-ee67151766cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36055
55162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3605555162
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.786056172
Short name T2066
Test name
Test status
Simulation time 1238134875 ps
CPU time 2.79 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:50 PM PDT 24
Peak memory 206656 kb
Host smart-6277bd02-4ae6-46ed-98b0-617928e48af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78605
6172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.786056172
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1099731649
Short name T2605
Test name
Test status
Simulation time 7393818534 ps
CPU time 193.99 seconds
Started Jul 11 06:00:20 PM PDT 24
Finished Jul 11 06:03:44 PM PDT 24
Peak memory 206624 kb
Host smart-5f7925f8-965d-41cb-be7b-b5e35482ba3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10997
31649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1099731649
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.1900944093
Short name T437
Test name
Test status
Simulation time 53466561 ps
CPU time 0.68 seconds
Started Jul 11 06:00:34 PM PDT 24
Finished Jul 11 06:00:45 PM PDT 24
Peak memory 206408 kb
Host smart-3fa083e7-c957-4b18-9218-7e754b367ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1900944093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1900944093
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1833358821
Short name T1805
Test name
Test status
Simulation time 3863041948 ps
CPU time 4.68 seconds
Started Jul 11 06:00:24 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206648 kb
Host smart-f00e67b2-5b5c-405a-9260-2e634e1394a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1833358821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1833358821
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.254280147
Short name T686
Test name
Test status
Simulation time 13422624160 ps
CPU time 13.49 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:00:54 PM PDT 24
Peak memory 206504 kb
Host smart-bd8a0196-d54d-475c-9e4c-4586164b18fa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=254280147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.254280147
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.4018005978
Short name T1579
Test name
Test status
Simulation time 23332714642 ps
CPU time 24.29 seconds
Started Jul 11 06:00:34 PM PDT 24
Finished Jul 11 06:01:09 PM PDT 24
Peak memory 206436 kb
Host smart-8e5a83f1-4b19-462b-b27c-0c4027073de3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4018005978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.4018005978
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3842818117
Short name T553
Test name
Test status
Simulation time 156761020 ps
CPU time 0.77 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 206404 kb
Host smart-7c17f049-1ead-4397-a539-ddf968f4a96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38428
18117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3842818117
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3675831579
Short name T2244
Test name
Test status
Simulation time 227083861 ps
CPU time 0.83 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:40 PM PDT 24
Peak memory 206396 kb
Host smart-60f9d5da-e554-4104-80ec-f43ce83ac81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36758
31579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3675831579
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.4044258289
Short name T1382
Test name
Test status
Simulation time 377010528 ps
CPU time 1.22 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206260 kb
Host smart-a7011870-f298-4e79-9774-2f938e78b274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40442
58289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.4044258289
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3246450978
Short name T2481
Test name
Test status
Simulation time 719518842 ps
CPU time 2.01 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:48 PM PDT 24
Peak memory 206612 kb
Host smart-aa7cb251-a8c7-4b58-a507-f6f09208c6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32464
50978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3246450978
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.498712905
Short name T1899
Test name
Test status
Simulation time 17744329590 ps
CPU time 30.48 seconds
Started Jul 11 06:00:24 PM PDT 24
Finished Jul 11 06:01:03 PM PDT 24
Peak memory 206736 kb
Host smart-63167a3a-cd34-4b55-b092-ac66b162e27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49871
2905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.498712905
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2924546627
Short name T2576
Test name
Test status
Simulation time 430700774 ps
CPU time 1.31 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 206408 kb
Host smart-14942c85-0f42-4baf-862c-5ea562b59bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29245
46627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2924546627
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1190944721
Short name T1850
Test name
Test status
Simulation time 135806777 ps
CPU time 0.8 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:48 PM PDT 24
Peak memory 206420 kb
Host smart-79554580-0fcd-4848-9cf1-5c90fb317358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11909
44721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1190944721
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1114944864
Short name T403
Test name
Test status
Simulation time 71555722 ps
CPU time 0.68 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206368 kb
Host smart-ad784754-6578-4a1e-988f-ddc8629d0766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11149
44864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1114944864
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3720336850
Short name T160
Test name
Test status
Simulation time 901370170 ps
CPU time 2.05 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:49 PM PDT 24
Peak memory 206620 kb
Host smart-2e46514c-e9b5-4666-bf4a-fe3f9dca3cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37203
36850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3720336850
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1379206366
Short name T2189
Test name
Test status
Simulation time 264793395 ps
CPU time 1.9 seconds
Started Jul 11 06:00:27 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 206600 kb
Host smart-8251a130-af5e-47cd-a4de-bb446c28a505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13792
06366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1379206366
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.102933590
Short name T755
Test name
Test status
Simulation time 161971848 ps
CPU time 0.83 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206292 kb
Host smart-63a9af9f-d093-4a2b-a136-4baf2551793b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10293
3590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.102933590
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3090407894
Short name T396
Test name
Test status
Simulation time 140057829 ps
CPU time 0.77 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:40 PM PDT 24
Peak memory 206392 kb
Host smart-c81c8416-b672-4a5b-8123-ebd6d45e49c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30904
07894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3090407894
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3448870095
Short name T334
Test name
Test status
Simulation time 184335399 ps
CPU time 0.94 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 206304 kb
Host smart-9aac9ba1-e67c-48cb-9f58-9baa7efa558b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
70095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3448870095
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2252128404
Short name T79
Test name
Test status
Simulation time 7559329730 ps
CPU time 210.67 seconds
Started Jul 11 06:00:39 PM PDT 24
Finished Jul 11 06:04:21 PM PDT 24
Peak memory 206620 kb
Host smart-d43f6f79-c8c5-4da3-9b33-b527609c74fd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2252128404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2252128404
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.1777610128
Short name T1801
Test name
Test status
Simulation time 5259814105 ps
CPU time 18.05 seconds
Started Jul 11 06:00:25 PM PDT 24
Finished Jul 11 06:00:52 PM PDT 24
Peak memory 206656 kb
Host smart-2e59c095-2727-4155-a791-5133dbe1ae06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17776
10128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.1777610128
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1080657341
Short name T2636
Test name
Test status
Simulation time 273079201 ps
CPU time 0.9 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 206364 kb
Host smart-beb2ef2a-7a12-4619-a3fa-c762b9435457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10806
57341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1080657341
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2618660180
Short name T836
Test name
Test status
Simulation time 23316692055 ps
CPU time 24.54 seconds
Started Jul 11 06:00:38 PM PDT 24
Finished Jul 11 06:01:14 PM PDT 24
Peak memory 206436 kb
Host smart-ce039b65-319f-4983-b6e4-d4ea1a17a43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26186
60180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2618660180
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.679761900
Short name T1363
Test name
Test status
Simulation time 3262159875 ps
CPU time 3.68 seconds
Started Jul 11 06:00:25 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 206432 kb
Host smart-72935736-6e93-487f-bc01-f3f150422409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67976
1900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.679761900
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.443618816
Short name T2727
Test name
Test status
Simulation time 8770856431 ps
CPU time 65.27 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:01:46 PM PDT 24
Peak memory 206660 kb
Host smart-8d940e73-72c8-48b4-a62c-967c953fc088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44361
8816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.443618816
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3541118278
Short name T2310
Test name
Test status
Simulation time 3649523995 ps
CPU time 25.47 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:01:03 PM PDT 24
Peak memory 206628 kb
Host smart-86ac32c0-8b58-4a1f-a64d-02bbb88fc743
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3541118278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3541118278
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.3314347208
Short name T959
Test name
Test status
Simulation time 274104428 ps
CPU time 0.94 seconds
Started Jul 11 06:00:34 PM PDT 24
Finished Jul 11 06:00:46 PM PDT 24
Peak memory 206160 kb
Host smart-f3502118-5e92-4483-aba8-cf940475bc2b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3314347208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.3314347208
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.4051087995
Short name T400
Test name
Test status
Simulation time 191743730 ps
CPU time 0.9 seconds
Started Jul 11 06:00:39 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206376 kb
Host smart-f36d3474-8938-45a4-a1cd-e3d6b37396b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40510
87995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.4051087995
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3635506770
Short name T2285
Test name
Test status
Simulation time 4789755256 ps
CPU time 42.39 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206656 kb
Host smart-6c67359c-5ee4-40fc-9ed7-347424c99a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36355
06770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3635506770
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2916201296
Short name T1642
Test name
Test status
Simulation time 5450781907 ps
CPU time 153.89 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:03:12 PM PDT 24
Peak memory 206592 kb
Host smart-db608fe5-8eeb-499c-a928-4378d8c4074d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2916201296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2916201296
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1177419049
Short name T326
Test name
Test status
Simulation time 172784968 ps
CPU time 0.83 seconds
Started Jul 11 06:00:25 PM PDT 24
Finished Jul 11 06:00:35 PM PDT 24
Peak memory 206384 kb
Host smart-3c7031f6-5a4e-4b6e-8be7-42c35d1238eb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1177419049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1177419049
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2000586498
Short name T1220
Test name
Test status
Simulation time 138373940 ps
CPU time 0.74 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 206388 kb
Host smart-52bfb6b1-bf7d-4dd3-8cae-86d683060255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
86498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2000586498
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3606543590
Short name T141
Test name
Test status
Simulation time 253864727 ps
CPU time 0.95 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 206308 kb
Host smart-c94c8444-70b5-44f9-af11-718b15e2b8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36065
43590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3606543590
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.460936576
Short name T2659
Test name
Test status
Simulation time 242336761 ps
CPU time 0.86 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 206364 kb
Host smart-1aef756e-586e-46ac-813d-c14fed2b3f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46093
6576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.460936576
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.385500884
Short name T1299
Test name
Test status
Simulation time 198640753 ps
CPU time 0.9 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 206296 kb
Host smart-4a28fab0-c1ac-4000-bd69-83f12339d2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38550
0884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.385500884
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3628934181
Short name T429
Test name
Test status
Simulation time 174661621 ps
CPU time 0.84 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206396 kb
Host smart-9a6cb541-973f-4844-95f3-a107e4b60e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289
34181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3628934181
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.111149530
Short name T1254
Test name
Test status
Simulation time 152300181 ps
CPU time 0.75 seconds
Started Jul 11 06:00:26 PM PDT 24
Finished Jul 11 06:00:36 PM PDT 24
Peak memory 206308 kb
Host smart-1028716b-35ca-4d7f-a562-ef035c120b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11114
9530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.111149530
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.3543684265
Short name T472
Test name
Test status
Simulation time 196910446 ps
CPU time 0.88 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206400 kb
Host smart-cc26bc2a-2231-4f8f-94fd-44d82d2ae35f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3543684265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.3543684265
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.689035534
Short name T1752
Test name
Test status
Simulation time 189879844 ps
CPU time 0.85 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 206336 kb
Host smart-7f7a7507-83fb-4262-8901-ca1cb30e445c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68903
5534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.689035534
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3517377874
Short name T28
Test name
Test status
Simulation time 36491291 ps
CPU time 0.64 seconds
Started Jul 11 06:00:34 PM PDT 24
Finished Jul 11 06:00:45 PM PDT 24
Peak memory 206168 kb
Host smart-f3239a0c-9e44-4025-b240-8ad84f3da7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35173
77874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3517377874
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3595893418
Short name T2730
Test name
Test status
Simulation time 194281067 ps
CPU time 0.87 seconds
Started Jul 11 06:00:21 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 206296 kb
Host smart-bbe5110b-abbf-4df3-945f-39f5fc36729e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35958
93418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3595893418
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1535906413
Short name T226
Test name
Test status
Simulation time 239516736 ps
CPU time 0.89 seconds
Started Jul 11 06:00:27 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 206384 kb
Host smart-db4a217b-4ce9-47fd-9156-87c935106b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15359
06413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1535906413
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1995488292
Short name T1515
Test name
Test status
Simulation time 192248876 ps
CPU time 0.88 seconds
Started Jul 11 06:00:34 PM PDT 24
Finished Jul 11 06:00:46 PM PDT 24
Peak memory 206392 kb
Host smart-1019cdb6-d1ba-4033-8766-d4ac198474cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19954
88292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1995488292
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.354083518
Short name T665
Test name
Test status
Simulation time 200758016 ps
CPU time 0.9 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 206312 kb
Host smart-741355e7-e5d6-4b42-a659-b337f99f6cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35408
3518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.354083518
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3959827073
Short name T1127
Test name
Test status
Simulation time 142483175 ps
CPU time 0.76 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:42 PM PDT 24
Peak memory 206364 kb
Host smart-e6ab0c51-df2e-4819-b7e9-9158fefe82a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
27073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3959827073
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3037018095
Short name T436
Test name
Test status
Simulation time 150165884 ps
CPU time 0.75 seconds
Started Jul 11 06:00:33 PM PDT 24
Finished Jul 11 06:00:45 PM PDT 24
Peak memory 206332 kb
Host smart-06d96ba5-82fc-4cbf-ab42-a47744a716c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30370
18095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3037018095
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2890326392
Short name T1953
Test name
Test status
Simulation time 176856473 ps
CPU time 0.8 seconds
Started Jul 11 06:01:03 PM PDT 24
Finished Jul 11 06:01:09 PM PDT 24
Peak memory 206304 kb
Host smart-01a7ff94-885f-46bb-a032-e77cecec278d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28903
26392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2890326392
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2351660297
Short name T1869
Test name
Test status
Simulation time 255650395 ps
CPU time 0.97 seconds
Started Jul 11 06:00:32 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206396 kb
Host smart-c3c420df-1654-4c33-a6f9-2973be9a59c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23516
60297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2351660297
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1554349106
Short name T88
Test name
Test status
Simulation time 4201566123 ps
CPU time 38.97 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:01:19 PM PDT 24
Peak memory 206616 kb
Host smart-87a853e2-d3d3-4bd4-835d-3631d7a2a24c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1554349106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1554349106
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2240105334
Short name T1880
Test name
Test status
Simulation time 186638023 ps
CPU time 0.8 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:46 PM PDT 24
Peak memory 206388 kb
Host smart-52f243a1-a823-4100-81e9-5a65b165b1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22401
05334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2240105334
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4149491510
Short name T1357
Test name
Test status
Simulation time 153016534 ps
CPU time 0.82 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:39 PM PDT 24
Peak memory 206384 kb
Host smart-2bffb775-d81c-43f0-8f18-bd00d03cce98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41494
91510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4149491510
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.336248470
Short name T2420
Test name
Test status
Simulation time 1023592214 ps
CPU time 2.13 seconds
Started Jul 11 06:00:43 PM PDT 24
Finished Jul 11 06:00:55 PM PDT 24
Peak memory 206636 kb
Host smart-b10f5e1d-62f1-43f9-a895-c32605df12b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624
8470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.336248470
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3015505122
Short name T2182
Test name
Test status
Simulation time 6084448072 ps
CPU time 56.76 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:01:39 PM PDT 24
Peak memory 206636 kb
Host smart-0cd04dbb-1dad-4ef5-b80a-a47ba216d6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30155
05122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3015505122
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.3041150688
Short name T605
Test name
Test status
Simulation time 53308442 ps
CPU time 0.7 seconds
Started Jul 11 06:00:38 PM PDT 24
Finished Jul 11 06:00:50 PM PDT 24
Peak memory 206408 kb
Host smart-9a5fd9ae-20ab-44da-8c2b-986b2a246ab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3041150688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3041150688
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2592019986
Short name T1111
Test name
Test status
Simulation time 4311065438 ps
CPU time 4.94 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206428 kb
Host smart-3ceb48ed-02b5-4d2a-a738-35929afba102
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2592019986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2592019986
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1529125969
Short name T668
Test name
Test status
Simulation time 13401293896 ps
CPU time 14.08 seconds
Started Jul 11 06:00:38 PM PDT 24
Finished Jul 11 06:01:04 PM PDT 24
Peak memory 206648 kb
Host smart-b919131a-4f45-42a5-a0fb-da3eba5e941f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1529125969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1529125969
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3356005358
Short name T2308
Test name
Test status
Simulation time 23384048767 ps
CPU time 29.79 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206444 kb
Host smart-cb7dff1f-172e-4e43-b989-b51bebc00a5e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3356005358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3356005358
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1852350303
Short name T1986
Test name
Test status
Simulation time 158271040 ps
CPU time 0.75 seconds
Started Jul 11 06:00:33 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206384 kb
Host smart-89351915-3811-4b9a-87f1-8866ef599fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18523
50303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1852350303
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2285250447
Short name T948
Test name
Test status
Simulation time 155377167 ps
CPU time 0.77 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:16 PM PDT 24
Peak memory 206364 kb
Host smart-dcdac01d-3981-45b8-bd62-43a0c5438495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22852
50447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2285250447
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.538016393
Short name T1989
Test name
Test status
Simulation time 156628487 ps
CPU time 0.87 seconds
Started Jul 11 06:00:36 PM PDT 24
Finished Jul 11 06:00:49 PM PDT 24
Peak memory 206392 kb
Host smart-d984cf13-5447-4740-90f5-1876b612b11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53801
6393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.538016393
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1299448113
Short name T115
Test name
Test status
Simulation time 524260214 ps
CPU time 1.37 seconds
Started Jul 11 06:00:32 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206376 kb
Host smart-72a12760-f871-4027-9608-0a470ee2006a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12994
48113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1299448113
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.54251292
Short name T2272
Test name
Test status
Simulation time 10997518679 ps
CPU time 21.13 seconds
Started Jul 11 06:00:42 PM PDT 24
Finished Jul 11 06:01:14 PM PDT 24
Peak memory 206700 kb
Host smart-31a4172e-8a53-4607-81b3-badc6481007c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54251
292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.54251292
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.4140839676
Short name T696
Test name
Test status
Simulation time 306141787 ps
CPU time 1.1 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206384 kb
Host smart-4567c9a8-4683-4956-b6fb-44b5488ec6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41408
39676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.4140839676
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.766782128
Short name T2503
Test name
Test status
Simulation time 174402541 ps
CPU time 0.79 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206380 kb
Host smart-2864ee05-811c-4028-8c87-014886184739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76678
2128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.766782128
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.245592194
Short name T1475
Test name
Test status
Simulation time 55249675 ps
CPU time 0.66 seconds
Started Jul 11 06:00:34 PM PDT 24
Finished Jul 11 06:00:45 PM PDT 24
Peak memory 206364 kb
Host smart-840f54c6-37ea-41b2-a86d-707aa5d04146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24559
2194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.245592194
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2853941525
Short name T2710
Test name
Test status
Simulation time 907157889 ps
CPU time 2 seconds
Started Jul 11 06:00:41 PM PDT 24
Finished Jul 11 06:00:54 PM PDT 24
Peak memory 206620 kb
Host smart-7bc55241-f84e-4c5e-a72b-59b9c4c9d04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
41525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2853941525
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1732119582
Short name T2306
Test name
Test status
Simulation time 178495228 ps
CPU time 2.02 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:01:00 PM PDT 24
Peak memory 206644 kb
Host smart-28ae1657-be1d-43dd-bd15-e98bdaf22c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17321
19582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1732119582
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2038858359
Short name T970
Test name
Test status
Simulation time 193946916 ps
CPU time 0.82 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:44 PM PDT 24
Peak memory 206376 kb
Host smart-fda34822-ba19-42df-93fa-1bf106be0187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20388
58359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2038858359
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.4152756143
Short name T1467
Test name
Test status
Simulation time 147953303 ps
CPU time 0.78 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 206400 kb
Host smart-30518272-3790-4f10-8d0b-4e56ef95d5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41527
56143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.4152756143
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.869467093
Short name T2096
Test name
Test status
Simulation time 243126139 ps
CPU time 0.86 seconds
Started Jul 11 06:00:28 PM PDT 24
Finished Jul 11 06:00:38 PM PDT 24
Peak memory 206368 kb
Host smart-9e9825bd-c304-4794-b521-6c599bed4418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86946
7093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.869467093
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.1360031516
Short name T1042
Test name
Test status
Simulation time 5990985664 ps
CPU time 19.26 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:35 PM PDT 24
Peak memory 206604 kb
Host smart-646e5aa6-7836-44f0-bddf-1360b6fd088b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13600
31516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.1360031516
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3520966779
Short name T984
Test name
Test status
Simulation time 192616387 ps
CPU time 0.81 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 206388 kb
Host smart-4d557ca3-d7d0-4675-a129-705fe4321ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35209
66779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3520966779
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1076208950
Short name T416
Test name
Test status
Simulation time 23318721032 ps
CPU time 28.01 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:01:08 PM PDT 24
Peak memory 206364 kb
Host smart-f14282ea-0a16-4df3-a1a2-17ae502a9083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
08950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1076208950
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2234586548
Short name T2430
Test name
Test status
Simulation time 3273049140 ps
CPU time 4.09 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:42 PM PDT 24
Peak memory 206360 kb
Host smart-54a61dd8-f2fb-4fee-bab3-e27e3c18ff2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22345
86548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2234586548
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1621615569
Short name T2446
Test name
Test status
Simulation time 8403324850 ps
CPU time 55.63 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:02:00 PM PDT 24
Peak memory 206620 kb
Host smart-d626c1a1-bf15-425c-a811-28b08865260a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
15569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1621615569
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2704398187
Short name T2389
Test name
Test status
Simulation time 4451958941 ps
CPU time 116.1 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:02:37 PM PDT 24
Peak memory 206800 kb
Host smart-98e026a5-0f5d-4d9d-bf38-b79bf165fb38
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2704398187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2704398187
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1835775779
Short name T2477
Test name
Test status
Simulation time 239020844 ps
CPU time 1.02 seconds
Started Jul 11 06:00:34 PM PDT 24
Finished Jul 11 06:00:46 PM PDT 24
Peak memory 206372 kb
Host smart-c3cae275-1ca1-45fa-befc-8ea134ebd2d2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1835775779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1835775779
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1086155716
Short name T1741
Test name
Test status
Simulation time 209507595 ps
CPU time 0.89 seconds
Started Jul 11 06:00:30 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 206544 kb
Host smart-409731cb-4a7f-428d-adae-dba51762d3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
55716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1086155716
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3471799315
Short name T670
Test name
Test status
Simulation time 4588240053 ps
CPU time 127.12 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:02:49 PM PDT 24
Peak memory 206656 kb
Host smart-9aef340f-6410-4902-95a5-3e4de23f9f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34717
99315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3471799315
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1521917434
Short name T773
Test name
Test status
Simulation time 4753691998 ps
CPU time 34.98 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:01:21 PM PDT 24
Peak memory 206688 kb
Host smart-11f79335-8fb7-40c8-ae3a-c7a13e8d9cf2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1521917434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1521917434
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.89412322
Short name T493
Test name
Test status
Simulation time 155637731 ps
CPU time 0.78 seconds
Started Jul 11 06:00:43 PM PDT 24
Finished Jul 11 06:00:54 PM PDT 24
Peak memory 206388 kb
Host smart-b5615001-179c-405d-9304-3d31ef63fdbe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=89412322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.89412322
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2712411426
Short name T1201
Test name
Test status
Simulation time 150475545 ps
CPU time 0.77 seconds
Started Jul 11 06:00:29 PM PDT 24
Finished Jul 11 06:00:40 PM PDT 24
Peak memory 206332 kb
Host smart-777bf44e-07f5-4dc0-8643-086cbf79bf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27124
11426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2712411426
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.255432432
Short name T136
Test name
Test status
Simulation time 197632648 ps
CPU time 0.85 seconds
Started Jul 11 06:00:46 PM PDT 24
Finished Jul 11 06:00:56 PM PDT 24
Peak memory 206384 kb
Host smart-a2765bbc-8cb7-4b84-8531-fbf41ede13e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25543
2432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.255432432
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3142966786
Short name T2099
Test name
Test status
Simulation time 175542797 ps
CPU time 0.82 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206400 kb
Host smart-6829bbcb-d5ca-46bd-9e32-e7d278e04cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31429
66786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3142966786
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1126186739
Short name T540
Test name
Test status
Simulation time 153930094 ps
CPU time 0.8 seconds
Started Jul 11 06:00:38 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206384 kb
Host smart-f1a1c878-5d89-4d3e-a294-89e2f91039e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11261
86739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1126186739
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3792253258
Short name T2434
Test name
Test status
Simulation time 182065488 ps
CPU time 0.77 seconds
Started Jul 11 06:00:33 PM PDT 24
Finished Jul 11 06:00:45 PM PDT 24
Peak memory 206376 kb
Host smart-b59d6eed-556f-4ae2-ad62-b084b63316ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37922
53258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3792253258
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1252377028
Short name T170
Test name
Test status
Simulation time 147612495 ps
CPU time 0.78 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:16 PM PDT 24
Peak memory 206368 kb
Host smart-06a42c90-ca2f-4ecb-b95b-9867c7f5363f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12523
77028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1252377028
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.1794132373
Short name T2539
Test name
Test status
Simulation time 279030508 ps
CPU time 0.93 seconds
Started Jul 11 06:00:46 PM PDT 24
Finished Jul 11 06:00:56 PM PDT 24
Peak memory 206364 kb
Host smart-a5a2a57a-6c36-4b4d-8089-5f45b759bf30
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1794132373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.1794132373
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2150279380
Short name T1586
Test name
Test status
Simulation time 143222901 ps
CPU time 0.79 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:16 PM PDT 24
Peak memory 206360 kb
Host smart-1eddccb7-a71b-4d5b-a0db-e4495a3ecd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21502
79380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2150279380
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.786362717
Short name T2571
Test name
Test status
Simulation time 43738460 ps
CPU time 0.68 seconds
Started Jul 11 06:00:42 PM PDT 24
Finished Jul 11 06:00:53 PM PDT 24
Peak memory 206380 kb
Host smart-de936210-66c4-4549-8c6f-c803f78afb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78636
2717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.786362717
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1037520893
Short name T159
Test name
Test status
Simulation time 22123104460 ps
CPU time 50 seconds
Started Jul 11 06:00:37 PM PDT 24
Finished Jul 11 06:01:39 PM PDT 24
Peak memory 206668 kb
Host smart-f9c9a720-c275-452b-b180-b915b4b32744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10375
20893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1037520893
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3375612396
Short name T1547
Test name
Test status
Simulation time 180838695 ps
CPU time 0.82 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 206364 kb
Host smart-99bd1acf-49ae-49a6-a012-a7a5f2427754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33756
12396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3375612396
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1673947268
Short name T1572
Test name
Test status
Simulation time 181672783 ps
CPU time 0.8 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206384 kb
Host smart-102e780c-9796-421a-bb2a-f3dcabf60b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16739
47268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1673947268
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3261200391
Short name T161
Test name
Test status
Simulation time 274363255 ps
CPU time 0.92 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:00:57 PM PDT 24
Peak memory 206340 kb
Host smart-5d8dbf24-20fd-4806-b5f0-0d2559ded05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32612
00391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3261200391
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3082163919
Short name T1649
Test name
Test status
Simulation time 178004294 ps
CPU time 0.79 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:00:57 PM PDT 24
Peak memory 206388 kb
Host smart-6a0db80b-d277-42de-b7b2-e099df4d5422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30821
63919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3082163919
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.205647020
Short name T2128
Test name
Test status
Simulation time 200121564 ps
CPU time 0.79 seconds
Started Jul 11 06:00:41 PM PDT 24
Finished Jul 11 06:00:52 PM PDT 24
Peak memory 206352 kb
Host smart-605f14be-11c9-4855-83b8-7a5ce33154b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20564
7020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.205647020
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1153436379
Short name T2000
Test name
Test status
Simulation time 154527365 ps
CPU time 0.8 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206372 kb
Host smart-f7a007f0-5012-46d4-beaa-59a6dd7cd439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11534
36379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1153436379
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3496811010
Short name T1866
Test name
Test status
Simulation time 162216068 ps
CPU time 0.8 seconds
Started Jul 11 06:00:46 PM PDT 24
Finished Jul 11 06:00:56 PM PDT 24
Peak memory 206328 kb
Host smart-5256b076-a2c8-41db-9f01-4e3c1aae002a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34968
11010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3496811010
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3062923729
Short name T1400
Test name
Test status
Simulation time 238451641 ps
CPU time 0.99 seconds
Started Jul 11 06:00:41 PM PDT 24
Finished Jul 11 06:00:52 PM PDT 24
Peak memory 206324 kb
Host smart-29d9296e-47ba-40ef-850a-00f7de59371c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30629
23729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3062923729
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1489157419
Short name T1280
Test name
Test status
Simulation time 4088392200 ps
CPU time 108.08 seconds
Started Jul 11 06:00:36 PM PDT 24
Finished Jul 11 06:02:36 PM PDT 24
Peak memory 206592 kb
Host smart-129749c5-0013-4e74-b699-c50c2473d448
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1489157419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1489157419
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1126607980
Short name T2082
Test name
Test status
Simulation time 179693001 ps
CPU time 0.85 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206560 kb
Host smart-e8857498-80e2-4748-ba72-5800a91a62d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11266
07980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1126607980
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.869697223
Short name T2660
Test name
Test status
Simulation time 235655281 ps
CPU time 0.92 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:00:57 PM PDT 24
Peak memory 206244 kb
Host smart-ccdd150d-3405-4b59-a0e2-c3976786767c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86969
7223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.869697223
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2467477352
Short name T394
Test name
Test status
Simulation time 570574284 ps
CPU time 1.44 seconds
Started Jul 11 06:00:39 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206352 kb
Host smart-294a0b19-1638-406e-bde2-aa5f92094278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24674
77352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2467477352
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.246011232
Short name T567
Test name
Test status
Simulation time 2828009800 ps
CPU time 74.99 seconds
Started Jul 11 06:00:44 PM PDT 24
Finished Jul 11 06:02:08 PM PDT 24
Peak memory 206568 kb
Host smart-308c0e1e-c789-4c59-afd0-2d55c9806d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24601
1232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.246011232
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.2588707468
Short name T2519
Test name
Test status
Simulation time 43364243 ps
CPU time 0.69 seconds
Started Jul 11 06:00:43 PM PDT 24
Finished Jul 11 06:00:54 PM PDT 24
Peak memory 206420 kb
Host smart-db7c5cda-c926-4ed7-afa9-ed7699b5311a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2588707468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.2588707468
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3382593284
Short name T2635
Test name
Test status
Simulation time 3682592522 ps
CPU time 4.11 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:01:00 PM PDT 24
Peak memory 206648 kb
Host smart-58a3390f-851d-4c3c-bf91-b3d79518c1a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3382593284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.3382593284
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3073188473
Short name T1831
Test name
Test status
Simulation time 13303049114 ps
CPU time 16.25 seconds
Started Jul 11 06:00:42 PM PDT 24
Finished Jul 11 06:01:09 PM PDT 24
Peak memory 206596 kb
Host smart-6932a62a-33c2-4ff9-b178-a82952c7fdf4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3073188473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3073188473
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1833112386
Short name T1514
Test name
Test status
Simulation time 23501489478 ps
CPU time 26.74 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:27 PM PDT 24
Peak memory 206612 kb
Host smart-566c4e99-2a52-454f-9b83-e11f8393e752
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1833112386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1833112386
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2007628653
Short name T1901
Test name
Test status
Simulation time 179465278 ps
CPU time 0.89 seconds
Started Jul 11 06:00:39 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206308 kb
Host smart-1ddcfa15-e6f6-47f1-9bf1-f2d185f9827d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20076
28653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2007628653
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.821760576
Short name T1596
Test name
Test status
Simulation time 204577669 ps
CPU time 0.8 seconds
Started Jul 11 06:00:46 PM PDT 24
Finished Jul 11 06:00:56 PM PDT 24
Peak memory 206404 kb
Host smart-77e076f2-53ef-4c56-922f-a743a4146c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82176
0576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.821760576
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3720443596
Short name T1607
Test name
Test status
Simulation time 308390795 ps
CPU time 1.09 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:14 PM PDT 24
Peak memory 206464 kb
Host smart-fc7b7e50-87dc-497c-9d08-461a4b5040a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37204
43596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3720443596
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3363451612
Short name T1314
Test name
Test status
Simulation time 852743613 ps
CPU time 2.01 seconds
Started Jul 11 06:00:44 PM PDT 24
Finished Jul 11 06:01:00 PM PDT 24
Peak memory 206660 kb
Host smart-490c2266-f553-4a4a-906b-0f5ae34701d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33634
51612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3363451612
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.745651133
Short name T2295
Test name
Test status
Simulation time 20128049446 ps
CPU time 33.03 seconds
Started Jul 11 06:00:41 PM PDT 24
Finished Jul 11 06:01:25 PM PDT 24
Peak memory 206668 kb
Host smart-debb94ff-347d-421e-b677-f073d308c48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74565
1133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.745651133
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.366146036
Short name T678
Test name
Test status
Simulation time 343039565 ps
CPU time 1.16 seconds
Started Jul 11 06:00:53 PM PDT 24
Finished Jul 11 06:01:03 PM PDT 24
Peak memory 206372 kb
Host smart-ac2d8e9f-5e87-4654-91e2-bf668976640c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36614
6036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.366146036
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1020725909
Short name T1077
Test name
Test status
Simulation time 140265952 ps
CPU time 0.78 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:00:57 PM PDT 24
Peak memory 206392 kb
Host smart-1468c725-4045-43e6-9d5d-61f25156411c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
25909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1020725909
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.193182891
Short name T584
Test name
Test status
Simulation time 88211426 ps
CPU time 0.68 seconds
Started Jul 11 06:00:35 PM PDT 24
Finished Jul 11 06:00:47 PM PDT 24
Peak memory 206372 kb
Host smart-3ae00510-861a-46d3-a4b2-90f6b7111734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19318
2891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.193182891
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3700431618
Short name T815
Test name
Test status
Simulation time 906112805 ps
CPU time 2.21 seconds
Started Jul 11 06:00:43 PM PDT 24
Finished Jul 11 06:00:55 PM PDT 24
Peak memory 206568 kb
Host smart-d6a633d1-80a0-40ad-9d9b-a0b3fb099e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37004
31618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3700431618
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2308616316
Short name T2142
Test name
Test status
Simulation time 203105288 ps
CPU time 1.61 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206500 kb
Host smart-2b8adcf2-5674-4b8f-ba21-a826374eb266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
16316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2308616316
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1492946689
Short name T2380
Test name
Test status
Simulation time 207249309 ps
CPU time 0.91 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206388 kb
Host smart-ff22d877-c9b7-4456-9047-d5c371ce6166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14929
46689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1492946689
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.580043320
Short name T2282
Test name
Test status
Simulation time 140788392 ps
CPU time 0.77 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:01 PM PDT 24
Peak memory 206356 kb
Host smart-c4ca57c9-87a1-4fc1-b0b7-5907096448d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58004
3320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.580043320
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3290476974
Short name T521
Test name
Test status
Simulation time 180983807 ps
CPU time 0.92 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206360 kb
Host smart-44cdf1d3-d6fc-4043-b907-f1f2d7941fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32904
76974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3290476974
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.3049987734
Short name T1188
Test name
Test status
Simulation time 5365454817 ps
CPU time 42.24 seconds
Started Jul 11 06:00:39 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 206664 kb
Host smart-747422de-a96e-4e03-bc85-f2ee64eb75a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30499
87734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.3049987734
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.4143496179
Short name T2670
Test name
Test status
Simulation time 179614814 ps
CPU time 0.84 seconds
Started Jul 11 06:00:46 PM PDT 24
Finished Jul 11 06:00:57 PM PDT 24
Peak memory 206384 kb
Host smart-8d0545a7-2573-4d49-92e4-c7cb5599e5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41434
96179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.4143496179
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.3004423877
Short name T922
Test name
Test status
Simulation time 23332615250 ps
CPU time 22.9 seconds
Started Jul 11 06:00:45 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 206372 kb
Host smart-1aaf990f-75c9-40f1-8b49-49bd7b77ce19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30044
23877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.3004423877
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3394888828
Short name T1307
Test name
Test status
Simulation time 3274594982 ps
CPU time 4.43 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:01:01 PM PDT 24
Peak memory 206448 kb
Host smart-b0ec52ee-2484-45b7-85c2-b3b5a3ba4431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33948
88828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3394888828
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3595776557
Short name T1354
Test name
Test status
Simulation time 7616173108 ps
CPU time 222.11 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:04:40 PM PDT 24
Peak memory 206556 kb
Host smart-9cb54e19-ede9-404e-a84a-fe0e9d858bb3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3595776557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3595776557
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2653636779
Short name T374
Test name
Test status
Simulation time 241062219 ps
CPU time 0.91 seconds
Started Jul 11 06:00:41 PM PDT 24
Finished Jul 11 06:00:52 PM PDT 24
Peak memory 206376 kb
Host smart-acd73140-e72c-4485-a758-cfc052973469
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2653636779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2653636779
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3203752936
Short name T745
Test name
Test status
Simulation time 210713348 ps
CPU time 0.93 seconds
Started Jul 11 06:00:38 PM PDT 24
Finished Jul 11 06:00:50 PM PDT 24
Peak memory 206404 kb
Host smart-7f07bdbe-84ce-451b-8840-d77f27b74659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32037
52936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3203752936
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.4128806400
Short name T1641
Test name
Test status
Simulation time 5466828637 ps
CPU time 145.32 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:03:23 PM PDT 24
Peak memory 206412 kb
Host smart-b9b08839-0269-4ca5-98f1-769c225cf610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41288
06400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.4128806400
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3505350546
Short name T2058
Test name
Test status
Simulation time 6728376746 ps
CPU time 186.66 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:04:04 PM PDT 24
Peak memory 206368 kb
Host smart-b897a71b-357c-4df0-b7a3-c68264aadfa8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3505350546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3505350546
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.1730456302
Short name T2031
Test name
Test status
Simulation time 166889241 ps
CPU time 0.81 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206344 kb
Host smart-fabe4f12-771d-4fae-be8e-9dc3f690deb1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1730456302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.1730456302
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3056499570
Short name T1110
Test name
Test status
Simulation time 199593463 ps
CPU time 0.82 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206344 kb
Host smart-14fecc76-7123-42f4-b487-4e228dfe50ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
99570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3056499570
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2356614198
Short name T147
Test name
Test status
Simulation time 174107149 ps
CPU time 0.79 seconds
Started Jul 11 06:00:39 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206356 kb
Host smart-a6503ce1-bfa9-49d4-a12a-12f1453e7f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23566
14198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2356614198
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3520001819
Short name T1590
Test name
Test status
Simulation time 187536299 ps
CPU time 0.83 seconds
Started Jul 11 06:00:41 PM PDT 24
Finished Jul 11 06:00:53 PM PDT 24
Peak memory 206384 kb
Host smart-179beb12-ce97-40b2-a895-23313d913423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
01819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3520001819
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2985030495
Short name T2537
Test name
Test status
Simulation time 155499897 ps
CPU time 0.78 seconds
Started Jul 11 06:00:39 PM PDT 24
Finished Jul 11 06:00:51 PM PDT 24
Peak memory 206384 kb
Host smart-ea00a536-814f-4725-bc45-842ef6855277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29850
30495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2985030495
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3228680993
Short name T2044
Test name
Test status
Simulation time 169026669 ps
CPU time 0.84 seconds
Started Jul 11 06:00:50 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206424 kb
Host smart-a0c27bf4-1dcb-49f2-9861-9b3533a15e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32286
80993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3228680993
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.99912666
Short name T2568
Test name
Test status
Simulation time 234172658 ps
CPU time 0.85 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206344 kb
Host smart-e31b6951-716e-450e-9e21-5de319c4e7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99912
666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.99912666
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3675002549
Short name T803
Test name
Test status
Simulation time 214162578 ps
CPU time 0.88 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206368 kb
Host smart-1a54a3c5-9008-4ccf-8e09-d15ab47b8ce7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3675002549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3675002549
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.169576308
Short name T1004
Test name
Test status
Simulation time 140502646 ps
CPU time 0.78 seconds
Started Jul 11 06:00:50 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206424 kb
Host smart-d63a35fb-8fa5-42c0-a0c7-4c26c8546321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
6308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.169576308
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.4217701090
Short name T1200
Test name
Test status
Simulation time 41074657 ps
CPU time 0.72 seconds
Started Jul 11 06:01:03 PM PDT 24
Finished Jul 11 06:01:09 PM PDT 24
Peak memory 206356 kb
Host smart-466e055b-0f86-4334-96a3-f28c7de81559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42177
01090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.4217701090
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2052037351
Short name T1978
Test name
Test status
Simulation time 18608743569 ps
CPU time 38.46 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:01:42 PM PDT 24
Peak memory 206604 kb
Host smart-2cb27a74-d233-4ce4-a3a5-3d1539f904a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20520
37351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2052037351
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.637528778
Short name T1479
Test name
Test status
Simulation time 175545055 ps
CPU time 0.92 seconds
Started Jul 11 06:00:43 PM PDT 24
Finished Jul 11 06:00:54 PM PDT 24
Peak memory 206380 kb
Host smart-27dc2bc7-a67a-4a44-88c5-0c7463e6a393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63752
8778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.637528778
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1375740904
Short name T1674
Test name
Test status
Simulation time 154744442 ps
CPU time 0.79 seconds
Started Jul 11 06:00:56 PM PDT 24
Finished Jul 11 06:01:04 PM PDT 24
Peak memory 206400 kb
Host smart-9df3416b-3a77-4ad0-b631-9e9a3bd6e860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757
40904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1375740904
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3086460233
Short name T856
Test name
Test status
Simulation time 186736074 ps
CPU time 0.83 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206388 kb
Host smart-faf65e4f-4612-417f-a6f1-9f564159b989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30864
60233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3086460233
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3906532847
Short name T2738
Test name
Test status
Simulation time 150867646 ps
CPU time 0.82 seconds
Started Jul 11 06:00:53 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206360 kb
Host smart-bcf0c151-6177-425e-afe2-99073bb3d865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39065
32847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3906532847
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.1802850720
Short name T78
Test name
Test status
Simulation time 155652523 ps
CPU time 0.8 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206332 kb
Host smart-160762c4-7a56-4982-bc16-205e02d44ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18028
50720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.1802850720
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2326861017
Short name T1242
Test name
Test status
Simulation time 151561996 ps
CPU time 0.75 seconds
Started Jul 11 06:00:44 PM PDT 24
Finished Jul 11 06:00:54 PM PDT 24
Peak memory 206396 kb
Host smart-61be08a2-5875-4f6c-9731-2943c12ff2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23268
61017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2326861017
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1666016404
Short name T2062
Test name
Test status
Simulation time 146633063 ps
CPU time 0.81 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206540 kb
Host smart-d96346b3-99a1-43e9-915c-95f0d631ba71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16660
16404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1666016404
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2150247266
Short name T615
Test name
Test status
Simulation time 218541831 ps
CPU time 0.92 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:01:01 PM PDT 24
Peak memory 206380 kb
Host smart-9e3cd6ce-dd38-4ddb-8887-64edc6471121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21502
47266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2150247266
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3558649091
Short name T1925
Test name
Test status
Simulation time 6387929220 ps
CPU time 43.8 seconds
Started Jul 11 06:00:48 PM PDT 24
Finished Jul 11 06:01:40 PM PDT 24
Peak memory 206676 kb
Host smart-dbb643d2-9373-4bc9-9069-e45ad563b377
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3558649091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3558649091
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.4122829022
Short name T2037
Test name
Test status
Simulation time 188283226 ps
CPU time 0.84 seconds
Started Jul 11 06:00:46 PM PDT 24
Finished Jul 11 06:00:56 PM PDT 24
Peak memory 206336 kb
Host smart-58537648-eb22-4b92-af66-bd086017fd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41228
29022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.4122829022
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1914406135
Short name T1946
Test name
Test status
Simulation time 189278320 ps
CPU time 0.85 seconds
Started Jul 11 06:00:50 PM PDT 24
Finished Jul 11 06:01:00 PM PDT 24
Peak memory 206384 kb
Host smart-e408552e-6397-4f35-ad26-4917cb5d86ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19144
06135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1914406135
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3678348765
Short name T661
Test name
Test status
Simulation time 1354145401 ps
CPU time 2.66 seconds
Started Jul 11 06:00:58 PM PDT 24
Finished Jul 11 06:01:07 PM PDT 24
Peak memory 206612 kb
Host smart-14fd0bc6-3f9a-44ad-b338-6bba993d3d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36783
48765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3678348765
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3825955079
Short name T695
Test name
Test status
Simulation time 3377747026 ps
CPU time 25.08 seconds
Started Jul 11 06:00:44 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206708 kb
Host smart-81508e99-4457-44da-9f42-1a0fdaf044e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38259
55079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3825955079
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3678031227
Short name T2470
Test name
Test status
Simulation time 87539645 ps
CPU time 0.72 seconds
Started Jul 11 05:55:05 PM PDT 24
Finished Jul 11 05:55:07 PM PDT 24
Peak memory 206364 kb
Host smart-3f3b7989-2b2f-42dd-96e9-536df2b01d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3678031227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3678031227
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1133837060
Short name T1278
Test name
Test status
Simulation time 4166848184 ps
CPU time 5.33 seconds
Started Jul 11 05:54:36 PM PDT 24
Finished Jul 11 05:54:43 PM PDT 24
Peak memory 206696 kb
Host smart-827f7870-55a9-41c4-881a-d6c219721e30
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1133837060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.1133837060
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1529302642
Short name T599
Test name
Test status
Simulation time 13385827918 ps
CPU time 12.84 seconds
Started Jul 11 05:54:37 PM PDT 24
Finished Jul 11 05:54:52 PM PDT 24
Peak memory 206364 kb
Host smart-3d9c22ee-8067-4c2b-b300-90a16397e1e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1529302642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1529302642
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3045001547
Short name T1536
Test name
Test status
Simulation time 23406604446 ps
CPU time 27.95 seconds
Started Jul 11 05:54:43 PM PDT 24
Finished Jul 11 05:55:12 PM PDT 24
Peak memory 206364 kb
Host smart-bcf96e2e-6dfa-495b-a3ce-92908b3a49d3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3045001547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3045001547
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2972146016
Short name T1623
Test name
Test status
Simulation time 195035317 ps
CPU time 0.81 seconds
Started Jul 11 05:54:41 PM PDT 24
Finished Jul 11 05:54:44 PM PDT 24
Peak memory 206372 kb
Host smart-f3f10c9e-0e36-4fc7-b7ea-f748e6a8cbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29721
46016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2972146016
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2672456188
Short name T62
Test name
Test status
Simulation time 153403412 ps
CPU time 0.76 seconds
Started Jul 11 05:54:43 PM PDT 24
Finished Jul 11 05:54:46 PM PDT 24
Peak memory 206396 kb
Host smart-91451b1d-da4d-4a1d-b190-40687a84f244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26724
56188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2672456188
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.3520965551
Short name T91
Test name
Test status
Simulation time 133377070 ps
CPU time 0.72 seconds
Started Jul 11 05:54:40 PM PDT 24
Finished Jul 11 05:54:42 PM PDT 24
Peak memory 206376 kb
Host smart-833a0ef9-923a-42f1-bf4f-54da5d0fa375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35209
65551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.3520965551
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2948779609
Short name T1506
Test name
Test status
Simulation time 159914158 ps
CPU time 0.78 seconds
Started Jul 11 05:54:43 PM PDT 24
Finished Jul 11 05:54:45 PM PDT 24
Peak memory 206344 kb
Host smart-a1b47b05-2700-4c44-ac5b-58ed83e3c6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29487
79609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2948779609
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3694863365
Short name T2531
Test name
Test status
Simulation time 540221688 ps
CPU time 1.44 seconds
Started Jul 11 05:54:44 PM PDT 24
Finished Jul 11 05:54:47 PM PDT 24
Peak memory 206548 kb
Host smart-f3aad29d-3284-4ad0-b4f8-49b97ce8001c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
63365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3694863365
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.354123933
Short name T660
Test name
Test status
Simulation time 979601518 ps
CPU time 2.3 seconds
Started Jul 11 05:54:40 PM PDT 24
Finished Jul 11 05:54:45 PM PDT 24
Peak memory 206620 kb
Host smart-1b2a4259-0d09-4381-b136-80c706418c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412
3933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.354123933
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3706733638
Short name T2143
Test name
Test status
Simulation time 7158254939 ps
CPU time 11.98 seconds
Started Jul 11 05:54:41 PM PDT 24
Finished Jul 11 05:54:55 PM PDT 24
Peak memory 206644 kb
Host smart-12b492c0-6c60-41dd-aba1-0e43b094b789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37067
33638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3706733638
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.2243071022
Short name T325
Test name
Test status
Simulation time 490318179 ps
CPU time 1.4 seconds
Started Jul 11 05:54:40 PM PDT 24
Finished Jul 11 05:54:43 PM PDT 24
Peak memory 206376 kb
Host smart-83d5af34-91ed-4136-bbf5-6e18634bdb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22430
71022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.2243071022
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2005069981
Short name T2357
Test name
Test status
Simulation time 147744891 ps
CPU time 0.75 seconds
Started Jul 11 05:54:44 PM PDT 24
Finished Jul 11 05:54:46 PM PDT 24
Peak memory 206332 kb
Host smart-806094c0-1b51-46c7-9f1b-59bd27aa8af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20050
69981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2005069981
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1914299729
Short name T531
Test name
Test status
Simulation time 44860954 ps
CPU time 0.65 seconds
Started Jul 11 05:54:38 PM PDT 24
Finished Jul 11 05:54:41 PM PDT 24
Peak memory 206308 kb
Host smart-5c8ba890-1aec-4e2e-8cdf-e422eb9952c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19142
99729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1914299729
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.968652660
Short name T478
Test name
Test status
Simulation time 735493527 ps
CPU time 1.68 seconds
Started Jul 11 05:54:40 PM PDT 24
Finished Jul 11 05:54:44 PM PDT 24
Peak memory 206588 kb
Host smart-fa47a58e-0b83-4504-97ab-063caaea361a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96865
2660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.968652660
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.286897404
Short name T194
Test name
Test status
Simulation time 249356408 ps
CPU time 1.44 seconds
Started Jul 11 05:54:38 PM PDT 24
Finished Jul 11 05:54:41 PM PDT 24
Peak memory 206620 kb
Host smart-037f7a8e-274a-4170-8dbf-f0731c2b1257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28689
7404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.286897404
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2671585987
Short name T711
Test name
Test status
Simulation time 110181063062 ps
CPU time 180.73 seconds
Started Jul 11 05:54:41 PM PDT 24
Finished Jul 11 05:57:43 PM PDT 24
Peak memory 206528 kb
Host smart-52f8bac0-fdec-40f1-a42b-0f17f6296f10
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2671585987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2671585987
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.1999347982
Short name T2352
Test name
Test status
Simulation time 107410875121 ps
CPU time 139.06 seconds
Started Jul 11 05:54:39 PM PDT 24
Finished Jul 11 05:57:00 PM PDT 24
Peak memory 206696 kb
Host smart-62d81789-acd3-41ad-8fbd-5fb16e7578f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999347982 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.1999347982
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1401357005
Short name T1840
Test name
Test status
Simulation time 96119702215 ps
CPU time 125.92 seconds
Started Jul 11 05:54:45 PM PDT 24
Finished Jul 11 05:56:52 PM PDT 24
Peak memory 206528 kb
Host smart-b1f619dd-d777-4303-a92e-9425338bd4f5
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1401357005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1401357005
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.141766607
Short name T1356
Test name
Test status
Simulation time 80991740656 ps
CPU time 106.61 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:56:41 PM PDT 24
Peak memory 206628 kb
Host smart-f9b5f155-9d38-4c7f-8e37-32cb63413b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141766607 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.141766607
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.1627119573
Short name T1431
Test name
Test status
Simulation time 94139956632 ps
CPU time 141.13 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:57:16 PM PDT 24
Peak memory 206640 kb
Host smart-9b5d72bf-93bd-4b2a-b7b5-eaabff0dfb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16271
19573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.1627119573
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3265589330
Short name T1215
Test name
Test status
Simulation time 194885697 ps
CPU time 0.83 seconds
Started Jul 11 05:54:51 PM PDT 24
Finished Jul 11 05:54:53 PM PDT 24
Peak memory 206372 kb
Host smart-98f23006-a8ca-4f0a-aad3-7aeb314fab8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32655
89330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3265589330
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.451796693
Short name T328
Test name
Test status
Simulation time 137390204 ps
CPU time 0.77 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:54:56 PM PDT 24
Peak memory 206416 kb
Host smart-bf7c95e5-8e46-4ce8-8414-4fda6937f445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45179
6693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.451796693
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2319445155
Short name T1039
Test name
Test status
Simulation time 211312669 ps
CPU time 0.9 seconds
Started Jul 11 05:54:54 PM PDT 24
Finished Jul 11 05:54:57 PM PDT 24
Peak memory 206388 kb
Host smart-c63d0cf3-7c14-43d7-8802-4a1eeb2372c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23194
45155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2319445155
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3625919741
Short name T2427
Test name
Test status
Simulation time 4431639040 ps
CPU time 40.18 seconds
Started Jul 11 05:54:56 PM PDT 24
Finished Jul 11 05:55:38 PM PDT 24
Peak memory 206652 kb
Host smart-f5066881-145f-4059-aec9-fe28efefcabd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3625919741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3625919741
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.1489844951
Short name T1883
Test name
Test status
Simulation time 9291761542 ps
CPU time 32.84 seconds
Started Jul 11 05:54:56 PM PDT 24
Finished Jul 11 05:55:30 PM PDT 24
Peak memory 206632 kb
Host smart-f7eb851b-22b0-4c29-ac5c-31fc3f165528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14898
44951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.1489844951
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1797067080
Short name T1582
Test name
Test status
Simulation time 193721696 ps
CPU time 0.83 seconds
Started Jul 11 05:54:50 PM PDT 24
Finished Jul 11 05:54:52 PM PDT 24
Peak memory 206260 kb
Host smart-d6c5b424-8df8-4f49-8b1f-afd2d17b6054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17970
67080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1797067080
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3588990944
Short name T2345
Test name
Test status
Simulation time 23319713549 ps
CPU time 25.13 seconds
Started Jul 11 05:54:56 PM PDT 24
Finished Jul 11 05:55:23 PM PDT 24
Peak memory 206444 kb
Host smart-a227a2ef-5e2a-4d71-a85b-df1dd2754514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35889
90944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3588990944
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2037836376
Short name T2546
Test name
Test status
Simulation time 3347542592 ps
CPU time 3.74 seconds
Started Jul 11 05:54:50 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 206376 kb
Host smart-22ff571c-0f54-4318-b41d-95ba3e442d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20378
36376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2037836376
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.4039955087
Short name T1609
Test name
Test status
Simulation time 10784782292 ps
CPU time 77.88 seconds
Started Jul 11 05:54:57 PM PDT 24
Finished Jul 11 05:56:16 PM PDT 24
Peak memory 206708 kb
Host smart-9d509f06-2f4e-4077-a60c-87fe9cd64b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40399
55087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.4039955087
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1916365579
Short name T1599
Test name
Test status
Simulation time 8082787699 ps
CPU time 74.59 seconds
Started Jul 11 05:54:55 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 206688 kb
Host smart-12620b52-f07b-4854-b06e-b2f40a05a085
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1916365579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1916365579
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.71753625
Short name T402
Test name
Test status
Simulation time 271624024 ps
CPU time 0.93 seconds
Started Jul 11 05:54:51 PM PDT 24
Finished Jul 11 05:54:53 PM PDT 24
Peak memory 206364 kb
Host smart-b88204bd-317a-42af-9411-57c1ea06cef6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=71753625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.71753625
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.4027697085
Short name T2626
Test name
Test status
Simulation time 189264062 ps
CPU time 0.84 seconds
Started Jul 11 05:54:52 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 206392 kb
Host smart-3876cba6-e4f9-41c7-92fe-97361cfbe9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40276
97085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.4027697085
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3018775731
Short name T2186
Test name
Test status
Simulation time 5019703215 ps
CPU time 135.69 seconds
Started Jul 11 05:54:56 PM PDT 24
Finished Jul 11 05:57:13 PM PDT 24
Peak memory 206684 kb
Host smart-07fde175-5062-4fed-a196-7fadc49f0097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
75731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3018775731
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2283277510
Short name T2336
Test name
Test status
Simulation time 4005469714 ps
CPU time 106.12 seconds
Started Jul 11 05:54:51 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206676 kb
Host smart-485ec579-aaae-4c0a-9b1d-714c981f5b10
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2283277510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2283277510
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.732938935
Short name T2232
Test name
Test status
Simulation time 183495784 ps
CPU time 0.8 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:54:55 PM PDT 24
Peak memory 206404 kb
Host smart-fdaed671-d138-4f35-93bc-349a19e7feaa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=732938935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.732938935
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.693971647
Short name T2510
Test name
Test status
Simulation time 156867748 ps
CPU time 0.78 seconds
Started Jul 11 05:54:57 PM PDT 24
Finished Jul 11 05:54:59 PM PDT 24
Peak memory 206324 kb
Host smart-0d260b55-9f7f-415b-a014-27baa007eb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69397
1647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.693971647
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.278777284
Short name T2508
Test name
Test status
Simulation time 193263460 ps
CPU time 0.87 seconds
Started Jul 11 05:55:40 PM PDT 24
Finished Jul 11 05:55:46 PM PDT 24
Peak memory 206320 kb
Host smart-b6b61323-9e35-441b-b3e1-a1e186cf0ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
7284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.278777284
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1093658638
Short name T1826
Test name
Test status
Simulation time 165439835 ps
CPU time 0.81 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:54:56 PM PDT 24
Peak memory 206400 kb
Host smart-16d54761-26ce-45dc-a52a-a55a77b00cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10936
58638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1093658638
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3892923847
Short name T1230
Test name
Test status
Simulation time 177356821 ps
CPU time 0.77 seconds
Started Jul 11 05:54:51 PM PDT 24
Finished Jul 11 05:54:53 PM PDT 24
Peak memory 206328 kb
Host smart-76a0b9ab-343d-4f40-8976-1d6796fe4025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38929
23847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3892923847
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3097478732
Short name T2639
Test name
Test status
Simulation time 184461331 ps
CPU time 0.79 seconds
Started Jul 11 05:54:56 PM PDT 24
Finished Jul 11 05:54:58 PM PDT 24
Peak memory 206400 kb
Host smart-ad7c0c0d-d7c0-48fd-aff0-ac2ed361f766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30974
78732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3097478732
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3217920793
Short name T1470
Test name
Test status
Simulation time 213593620 ps
CPU time 0.87 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:54:56 PM PDT 24
Peak memory 206304 kb
Host smart-cc819aa6-c4ed-4faa-b551-57f6a040892f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32179
20793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3217920793
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1248829171
Short name T2601
Test name
Test status
Simulation time 247360204 ps
CPU time 0.92 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:54:56 PM PDT 24
Peak memory 206328 kb
Host smart-0d401ce8-9bc7-462c-828d-888d470504a9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1248829171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1248829171
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.508538146
Short name T212
Test name
Test status
Simulation time 186654629 ps
CPU time 0.89 seconds
Started Jul 11 05:54:52 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 206384 kb
Host smart-92b57498-cefc-445f-bd70-b1b069e7d5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50853
8146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.508538146
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.543266746
Short name T1541
Test name
Test status
Simulation time 163234126 ps
CPU time 0.81 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:54:55 PM PDT 24
Peak memory 206396 kb
Host smart-16c2376a-e2ec-4a79-94b6-80a339d84de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54326
6746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.543266746
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.760883004
Short name T2089
Test name
Test status
Simulation time 59703189 ps
CPU time 0.7 seconds
Started Jul 11 05:54:52 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 206324 kb
Host smart-db623d8a-8569-4c41-839d-bbfd74fd0b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76088
3004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.760883004
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3968364177
Short name T1524
Test name
Test status
Simulation time 6206715320 ps
CPU time 12.74 seconds
Started Jul 11 05:54:53 PM PDT 24
Finished Jul 11 05:55:08 PM PDT 24
Peak memory 206624 kb
Host smart-ce4e08bc-b076-40e2-9b71-b5402435d369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39683
64177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3968364177
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3735236020
Short name T2106
Test name
Test status
Simulation time 223133402 ps
CPU time 0.95 seconds
Started Jul 11 05:54:54 PM PDT 24
Finished Jul 11 05:54:56 PM PDT 24
Peak memory 206388 kb
Host smart-e652e39a-162c-49af-ac4d-b6831463733c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37352
36020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3735236020
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1762654233
Short name T2043
Test name
Test status
Simulation time 172526872 ps
CPU time 0.78 seconds
Started Jul 11 05:54:54 PM PDT 24
Finished Jul 11 05:54:57 PM PDT 24
Peak memory 206368 kb
Host smart-2ff6b87f-7f4b-4d47-b1ca-962d51b9c476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17626
54233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1762654233
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.4161164581
Short name T961
Test name
Test status
Simulation time 17813601014 ps
CPU time 153.52 seconds
Started Jul 11 05:55:09 PM PDT 24
Finished Jul 11 05:57:45 PM PDT 24
Peak memory 206684 kb
Host smart-0d416467-5cc3-46de-820a-29957ab0e6d7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4161164581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.4161164581
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3973224698
Short name T174
Test name
Test status
Simulation time 9225307000 ps
CPU time 62.1 seconds
Started Jul 11 05:55:06 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 206700 kb
Host smart-3591f2e0-188c-4859-84fc-aa4fa04e9d40
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3973224698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3973224698
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1576815207
Short name T1902
Test name
Test status
Simulation time 13115341942 ps
CPU time 88.67 seconds
Started Jul 11 05:55:07 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206624 kb
Host smart-9b48834a-ef38-4e26-a89c-d283a9dac6d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1576815207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1576815207
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.176625959
Short name T1628
Test name
Test status
Simulation time 221999232 ps
CPU time 0.9 seconds
Started Jul 11 05:54:56 PM PDT 24
Finished Jul 11 05:54:59 PM PDT 24
Peak memory 206384 kb
Host smart-30a0c3c0-5ed1-482c-8ded-539cc9e8afb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17662
5959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.176625959
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3230202188
Short name T869
Test name
Test status
Simulation time 177772327 ps
CPU time 0.84 seconds
Started Jul 11 05:55:07 PM PDT 24
Finished Jul 11 05:55:11 PM PDT 24
Peak memory 206404 kb
Host smart-6540e4e9-0c1d-4d4c-8722-b5f3c285d5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32302
02188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3230202188
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3350839959
Short name T2275
Test name
Test status
Simulation time 166891572 ps
CPU time 0.82 seconds
Started Jul 11 05:55:12 PM PDT 24
Finished Jul 11 05:55:14 PM PDT 24
Peak memory 206320 kb
Host smart-26535e6c-3b45-4928-8f2b-d64e1be6073f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33508
39959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3350839959
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2102369254
Short name T250
Test name
Test status
Simulation time 161159047 ps
CPU time 0.77 seconds
Started Jul 11 05:55:08 PM PDT 24
Finished Jul 11 05:55:11 PM PDT 24
Peak memory 206372 kb
Host smart-3720c86d-8486-4c0d-8fde-70751d7a4f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21023
69254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2102369254
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.553991790
Short name T205
Test name
Test status
Simulation time 621352824 ps
CPU time 1.45 seconds
Started Jul 11 05:55:08 PM PDT 24
Finished Jul 11 05:55:12 PM PDT 24
Peak memory 225212 kb
Host smart-e55a0062-8dc2-4cbc-8861-2954c103cf05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=553991790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.553991790
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.1810273585
Short name T59
Test name
Test status
Simulation time 416908894 ps
CPU time 1.36 seconds
Started Jul 11 05:55:08 PM PDT 24
Finished Jul 11 05:55:12 PM PDT 24
Peak memory 206416 kb
Host smart-e32a3cad-6aba-4502-bca1-66a2caeaf4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18102
73585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1810273585
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.871265333
Short name T2090
Test name
Test status
Simulation time 297013005 ps
CPU time 1 seconds
Started Jul 11 05:55:04 PM PDT 24
Finished Jul 11 05:55:06 PM PDT 24
Peak memory 206400 kb
Host smart-80e7f4d7-efda-4943-9b08-b21685b6ba67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87126
5333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.871265333
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.614301889
Short name T2072
Test name
Test status
Simulation time 152930820 ps
CPU time 0.74 seconds
Started Jul 11 05:55:10 PM PDT 24
Finished Jul 11 05:55:13 PM PDT 24
Peak memory 206380 kb
Host smart-1f1198e6-1d65-4436-bf3b-176e99dd7ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61430
1889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.614301889
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.780473357
Short name T1447
Test name
Test status
Simulation time 210847390 ps
CPU time 0.82 seconds
Started Jul 11 05:55:10 PM PDT 24
Finished Jul 11 05:55:13 PM PDT 24
Peak memory 206308 kb
Host smart-f317b944-ed6e-4168-a51a-3912f0f2545c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78047
3357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.780473357
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3996867786
Short name T1377
Test name
Test status
Simulation time 196469346 ps
CPU time 0.83 seconds
Started Jul 11 05:55:08 PM PDT 24
Finished Jul 11 05:55:12 PM PDT 24
Peak memory 206384 kb
Host smart-8c63d819-5683-4452-9934-12ce864fc594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39968
67786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3996867786
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1250542875
Short name T1205
Test name
Test status
Simulation time 3490741602 ps
CPU time 33.86 seconds
Started Jul 11 05:55:11 PM PDT 24
Finished Jul 11 05:55:46 PM PDT 24
Peak memory 206628 kb
Host smart-6a4f997a-5b88-4fb9-b72a-0d199655c5e3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1250542875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1250542875
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3993067385
Short name T2583
Test name
Test status
Simulation time 164926482 ps
CPU time 0.78 seconds
Started Jul 11 05:55:08 PM PDT 24
Finished Jul 11 05:55:11 PM PDT 24
Peak memory 206376 kb
Host smart-25fde6f5-69ac-449d-a2f2-39662f663e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39930
67385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3993067385
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3146373254
Short name T1963
Test name
Test status
Simulation time 145046318 ps
CPU time 0.75 seconds
Started Jul 11 05:55:06 PM PDT 24
Finished Jul 11 05:55:09 PM PDT 24
Peak memory 206372 kb
Host smart-39a2b351-4f1e-4a02-8a6f-cfcdd80da24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31463
73254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3146373254
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.4060028894
Short name T682
Test name
Test status
Simulation time 585574892 ps
CPU time 1.56 seconds
Started Jul 11 05:55:07 PM PDT 24
Finished Jul 11 05:55:11 PM PDT 24
Peak memory 206376 kb
Host smart-b79e0076-fcbc-46fc-88b4-d922326477e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40600
28894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.4060028894
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2708853204
Short name T1374
Test name
Test status
Simulation time 7469574086 ps
CPU time 51.55 seconds
Started Jul 11 05:55:10 PM PDT 24
Finished Jul 11 05:56:03 PM PDT 24
Peak memory 206624 kb
Host smart-b0fac834-d3af-4138-8285-3711570248cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27088
53204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2708853204
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3477642938
Short name T1937
Test name
Test status
Simulation time 12201349486 ps
CPU time 77.82 seconds
Started Jul 11 05:55:06 PM PDT 24
Finished Jul 11 05:56:27 PM PDT 24
Peak memory 206740 kb
Host smart-97efddf9-247a-4b50-aae3-3370e12d9947
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3477642938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3477642938
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.567482412
Short name T845
Test name
Test status
Simulation time 49536298 ps
CPU time 0.69 seconds
Started Jul 11 06:01:12 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206432 kb
Host smart-10639f28-e7c9-455e-926f-d194a96eb7ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=567482412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.567482412
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.4289356784
Short name T1472
Test name
Test status
Simulation time 4238282188 ps
CPU time 5.58 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:01:04 PM PDT 24
Peak memory 206452 kb
Host smart-c9887b6a-8ed9-4a9e-bd29-419ff315142f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4289356784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.4289356784
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.4176827079
Short name T1057
Test name
Test status
Simulation time 13397818756 ps
CPU time 16.05 seconds
Started Jul 11 06:00:44 PM PDT 24
Finished Jul 11 06:01:09 PM PDT 24
Peak memory 206420 kb
Host smart-213b723e-3a22-4783-91ae-e24b9d032ec3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4176827079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.4176827079
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3929185752
Short name T2739
Test name
Test status
Simulation time 23375780432 ps
CPU time 25.45 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206652 kb
Host smart-66af8b0f-afc9-4256-9a3e-752fe7ca4900
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3929185752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3929185752
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.554738138
Short name T2187
Test name
Test status
Simulation time 175793049 ps
CPU time 0.84 seconds
Started Jul 11 06:01:03 PM PDT 24
Finished Jul 11 06:01:09 PM PDT 24
Peak memory 206376 kb
Host smart-2c9279f3-f230-4ba4-83d7-b237efb7adca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55473
8138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.554738138
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.445628666
Short name T2028
Test name
Test status
Simulation time 175609938 ps
CPU time 0.82 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206536 kb
Host smart-6dffa037-e601-4c63-ada7-88750f67cd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44562
8666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.445628666
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.916096978
Short name T2343
Test name
Test status
Simulation time 1139131935 ps
CPU time 2.68 seconds
Started Jul 11 06:00:46 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206652 kb
Host smart-4f3ebc8b-66d3-4bbf-9a8c-5f0acb165164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91609
6978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.916096978
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1821776948
Short name T1519
Test name
Test status
Simulation time 15410684615 ps
CPU time 28.44 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:01:24 PM PDT 24
Peak memory 206660 kb
Host smart-6b4fd892-59f0-4846-be9e-3dccd7086fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18217
76948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1821776948
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1303582904
Short name T423
Test name
Test status
Simulation time 443372624 ps
CPU time 1.23 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206296 kb
Host smart-ca04ad3c-cd38-4fa7-b5da-db441868713a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13035
82904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1303582904
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1163845255
Short name T633
Test name
Test status
Simulation time 135710101 ps
CPU time 0.76 seconds
Started Jul 11 06:00:46 PM PDT 24
Finished Jul 11 06:00:56 PM PDT 24
Peak memory 206308 kb
Host smart-3aaeed86-5b4b-441f-bdfc-6d557e26277a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11638
45255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1163845255
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3949478828
Short name T1410
Test name
Test status
Simulation time 69516956 ps
CPU time 0.67 seconds
Started Jul 11 06:00:51 PM PDT 24
Finished Jul 11 06:01:01 PM PDT 24
Peak memory 206296 kb
Host smart-998c0c9a-f7ad-489f-bf79-321300492340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39494
78828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3949478828
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3693934261
Short name T1330
Test name
Test status
Simulation time 863454687 ps
CPU time 2.22 seconds
Started Jul 11 06:00:47 PM PDT 24
Finished Jul 11 06:00:58 PM PDT 24
Peak memory 206580 kb
Host smart-5390b7ec-80bb-4976-9174-e831d2ae8840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36939
34261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3693934261
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1843216102
Short name T1165
Test name
Test status
Simulation time 167970399 ps
CPU time 1.76 seconds
Started Jul 11 06:00:45 PM PDT 24
Finished Jul 11 06:00:57 PM PDT 24
Peak memory 206500 kb
Host smart-a7b195b9-4510-415e-bc7e-e115026fcc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18432
16102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1843216102
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.826535548
Short name T2685
Test name
Test status
Simulation time 161260910 ps
CPU time 0.79 seconds
Started Jul 11 06:01:13 PM PDT 24
Finished Jul 11 06:01:22 PM PDT 24
Peak memory 206292 kb
Host smart-3710b524-b673-4edc-abd0-7078bc373ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82653
5548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.826535548
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2452721109
Short name T2581
Test name
Test status
Simulation time 161924612 ps
CPU time 0.81 seconds
Started Jul 11 06:01:12 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206396 kb
Host smart-4ee1dd96-4332-45a7-a71c-f6a4c38beba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24527
21109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2452721109
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2952940613
Short name T875
Test name
Test status
Simulation time 185710292 ps
CPU time 0.85 seconds
Started Jul 11 06:00:56 PM PDT 24
Finished Jul 11 06:01:04 PM PDT 24
Peak memory 206352 kb
Host smart-6fdab3d2-fb81-431a-adce-e0b3e235276b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29529
40613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2952940613
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.3040506402
Short name T420
Test name
Test status
Simulation time 6923195125 ps
CPU time 59.13 seconds
Started Jul 11 06:01:10 PM PDT 24
Finished Jul 11 06:02:18 PM PDT 24
Peak memory 206668 kb
Host smart-36409362-a4cb-466d-847d-2c0fd95714d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30405
06402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.3040506402
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1717354988
Short name T624
Test name
Test status
Simulation time 202204739 ps
CPU time 0.87 seconds
Started Jul 11 06:01:04 PM PDT 24
Finished Jul 11 06:01:10 PM PDT 24
Peak memory 206400 kb
Host smart-7c27d04b-7761-4ce5-8385-e5cca748ece5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17173
54988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1717354988
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3905226033
Short name T981
Test name
Test status
Simulation time 23273478539 ps
CPU time 22.72 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:23 PM PDT 24
Peak memory 206464 kb
Host smart-0f480f77-2627-4afb-8b45-ad7015b10324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39052
26033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3905226033
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2870190786
Short name T1207
Test name
Test status
Simulation time 3307284330 ps
CPU time 3.63 seconds
Started Jul 11 06:00:56 PM PDT 24
Finished Jul 11 06:01:06 PM PDT 24
Peak memory 206344 kb
Host smart-14db3192-c156-439e-b775-f3b78bb8045d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
90786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2870190786
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2470869552
Short name T2259
Test name
Test status
Simulation time 11673126694 ps
CPU time 81.58 seconds
Started Jul 11 06:00:53 PM PDT 24
Finished Jul 11 06:02:24 PM PDT 24
Peak memory 206708 kb
Host smart-9cc2b7b7-1faf-4b12-99f9-7fb0fe78a78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24708
69552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2470869552
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1646008568
Short name T1454
Test name
Test status
Simulation time 5583383785 ps
CPU time 55.61 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:56 PM PDT 24
Peak memory 206592 kb
Host smart-82688efb-0c0c-45cb-95c2-fb6923374757
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1646008568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1646008568
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.672932042
Short name T2524
Test name
Test status
Simulation time 240235348 ps
CPU time 0.92 seconds
Started Jul 11 06:00:58 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206396 kb
Host smart-209267c0-237b-43af-91a7-9841bc6810c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=672932042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.672932042
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.954907726
Short name T656
Test name
Test status
Simulation time 190439593 ps
CPU time 0.83 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206396 kb
Host smart-eddc7eee-c85f-483d-80dc-54f5b24f7e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95490
7726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.954907726
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2358416078
Short name T2491
Test name
Test status
Simulation time 3140662193 ps
CPU time 83.3 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:02:38 PM PDT 24
Peak memory 206640 kb
Host smart-99b41afd-9adc-4167-9a3a-210f9cd6c702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23584
16078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2358416078
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1474645950
Short name T2007
Test name
Test status
Simulation time 4914042027 ps
CPU time 34.56 seconds
Started Jul 11 06:01:03 PM PDT 24
Finished Jul 11 06:01:43 PM PDT 24
Peak memory 206696 kb
Host smart-e0ef31d6-42d2-4d26-b810-d65d921c2f63
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1474645950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1474645950
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.4166856075
Short name T1466
Test name
Test status
Simulation time 159979226 ps
CPU time 0.84 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206304 kb
Host smart-1fc1a1f6-986d-4b83-bde6-4bae0006bc60
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4166856075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.4166856075
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.288190651
Short name T972
Test name
Test status
Simulation time 142782148 ps
CPU time 0.73 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206380 kb
Host smart-e55683a9-007e-4a97-8bc2-452f7f08cb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28819
0651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.288190651
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1238153126
Short name T2409
Test name
Test status
Simulation time 177583606 ps
CPU time 0.82 seconds
Started Jul 11 06:00:50 PM PDT 24
Finished Jul 11 06:00:59 PM PDT 24
Peak memory 206312 kb
Host smart-001826f8-363e-473a-bd00-b7780e9427d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12381
53126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1238153126
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2327300462
Short name T379
Test name
Test status
Simulation time 192665949 ps
CPU time 0.81 seconds
Started Jul 11 06:00:54 PM PDT 24
Finished Jul 11 06:01:03 PM PDT 24
Peak memory 206388 kb
Host smart-5673b6ac-1c13-499b-a704-5c7c1c5782a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23273
00462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2327300462
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2716767413
Short name T2416
Test name
Test status
Simulation time 171895208 ps
CPU time 0.85 seconds
Started Jul 11 06:00:53 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206392 kb
Host smart-1881afa1-9153-4577-a25c-e44cc89f96e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
67413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2716767413
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2586336680
Short name T701
Test name
Test status
Simulation time 155193266 ps
CPU time 0.82 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206336 kb
Host smart-49965d5d-5ec8-4153-aed9-5310a405eb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25863
36680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2586336680
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.890020841
Short name T2273
Test name
Test status
Simulation time 275267026 ps
CPU time 0.99 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206404 kb
Host smart-737d4936-bf3c-4e02-abb3-06f0c74198fa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=890020841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.890020841
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3107382366
Short name T557
Test name
Test status
Simulation time 148133832 ps
CPU time 0.81 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 206392 kb
Host smart-e3a5e277-2f5f-46a1-8e29-3833bd141a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31073
82366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3107382366
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.983448403
Short name T2674
Test name
Test status
Simulation time 49104577 ps
CPU time 0.66 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:01 PM PDT 24
Peak memory 206296 kb
Host smart-118003c7-608b-42cd-87de-815fae56526b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98344
8403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.983448403
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1182008689
Short name T413
Test name
Test status
Simulation time 18090501490 ps
CPU time 38.6 seconds
Started Jul 11 06:00:49 PM PDT 24
Finished Jul 11 06:01:36 PM PDT 24
Peak memory 206696 kb
Host smart-de20116e-25f8-4c49-81fa-34a1d0ce85c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11820
08689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1182008689
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.807727861
Short name T2212
Test name
Test status
Simulation time 217290003 ps
CPU time 0.87 seconds
Started Jul 11 06:01:00 PM PDT 24
Finished Jul 11 06:01:07 PM PDT 24
Peak memory 206388 kb
Host smart-f0131d7c-2adb-4bd1-bbfe-9742dff7a0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80772
7861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.807727861
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2925333450
Short name T1218
Test name
Test status
Simulation time 216977501 ps
CPU time 0.92 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:11 PM PDT 24
Peak memory 206372 kb
Host smart-21afd101-e3a0-4846-bfef-2d2731781334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29253
33450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2925333450
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2082339836
Short name T1184
Test name
Test status
Simulation time 195101498 ps
CPU time 0.84 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206304 kb
Host smart-f560bd52-5b06-4a26-a487-d635a169c94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20823
39836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2082339836
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.958347174
Short name T511
Test name
Test status
Simulation time 199789629 ps
CPU time 0.79 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206376 kb
Host smart-b7eb2766-366e-421e-b588-789dcf4d75c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95834
7174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.958347174
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.955028104
Short name T2205
Test name
Test status
Simulation time 191513769 ps
CPU time 0.81 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:01 PM PDT 24
Peak memory 206304 kb
Host smart-e51547f9-ac8a-45cd-93dd-33be5ef41385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95502
8104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.955028104
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3827714337
Short name T1328
Test name
Test status
Simulation time 197760613 ps
CPU time 0.8 seconds
Started Jul 11 06:00:53 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206400 kb
Host smart-518e28a7-07a8-4ceb-a8f2-1a21a91622f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38277
14337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3827714337
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3312598834
Short name T2495
Test name
Test status
Simulation time 147262939 ps
CPU time 0.79 seconds
Started Jul 11 06:00:53 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206332 kb
Host smart-22a70574-cb2c-49f6-9b29-fca099966c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33125
98834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3312598834
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2631190340
Short name T2042
Test name
Test status
Simulation time 245108664 ps
CPU time 0.93 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206384 kb
Host smart-3aecb124-3f81-4466-8196-c4628c67fb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26311
90340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2631190340
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2833345778
Short name T735
Test name
Test status
Simulation time 4033921804 ps
CPU time 28.1 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206676 kb
Host smart-349c1927-0fe7-46cb-88fa-2240670d7e84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2833345778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2833345778
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3151435174
Short name T1712
Test name
Test status
Simulation time 186602113 ps
CPU time 0.81 seconds
Started Jul 11 06:01:13 PM PDT 24
Finished Jul 11 06:01:22 PM PDT 24
Peak memory 206264 kb
Host smart-f5f40e9f-91d2-4e21-8e0d-a162be80c147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31514
35174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3151435174
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1836745155
Short name T561
Test name
Test status
Simulation time 167758860 ps
CPU time 0.77 seconds
Started Jul 11 06:00:52 PM PDT 24
Finished Jul 11 06:01:02 PM PDT 24
Peak memory 206396 kb
Host smart-1d6341b0-10b3-436e-9163-4476bd264a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18367
45155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1836745155
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3862636539
Short name T1140
Test name
Test status
Simulation time 1022053178 ps
CPU time 2.28 seconds
Started Jul 11 06:00:55 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206584 kb
Host smart-2a00f204-8e55-4ac3-97e8-61a6d0ad82ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626
36539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3862636539
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.310421694
Short name T1293
Test name
Test status
Simulation time 7103296604 ps
CPU time 48.21 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:02:05 PM PDT 24
Peak memory 206560 kb
Host smart-6cde6e22-80ec-4475-b827-cdfaa269d3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31042
1694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.310421694
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3806627835
Short name T1394
Test name
Test status
Simulation time 98883466 ps
CPU time 0.73 seconds
Started Jul 11 06:01:12 PM PDT 24
Finished Jul 11 06:01:21 PM PDT 24
Peak memory 206424 kb
Host smart-8ab4366c-fde6-45df-8510-1089079ea061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3806627835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3806627835
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1628896231
Short name T1660
Test name
Test status
Simulation time 4153569867 ps
CPU time 5.76 seconds
Started Jul 11 06:00:53 PM PDT 24
Finished Jul 11 06:01:07 PM PDT 24
Peak memory 206612 kb
Host smart-1b8bf17c-948a-460c-abdc-4fff22eddaef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1628896231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1628896231
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1875896639
Short name T930
Test name
Test status
Simulation time 13436815649 ps
CPU time 12.28 seconds
Started Jul 11 06:01:13 PM PDT 24
Finished Jul 11 06:01:34 PM PDT 24
Peak memory 206156 kb
Host smart-a5f3cc91-4533-418c-8364-e19b4ec3cf0a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1875896639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1875896639
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2966729324
Short name T2337
Test name
Test status
Simulation time 23365823941 ps
CPU time 21.39 seconds
Started Jul 11 06:00:54 PM PDT 24
Finished Jul 11 06:01:24 PM PDT 24
Peak memory 206652 kb
Host smart-c1f54b87-97bb-4632-9f28-8fe33d46f439
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2966729324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2966729324
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.4183012813
Short name T501
Test name
Test status
Simulation time 164531463 ps
CPU time 0.85 seconds
Started Jul 11 06:00:57 PM PDT 24
Finished Jul 11 06:01:05 PM PDT 24
Peak memory 206324 kb
Host smart-dbe4d78a-ed0f-4dba-b89f-817f15bc5f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41830
12813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.4183012813
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1569348365
Short name T953
Test name
Test status
Simulation time 184302423 ps
CPU time 0.81 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206328 kb
Host smart-f516ce2a-e9ed-47b8-9eed-318d691702fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15693
48365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1569348365
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2818191880
Short name T892
Test name
Test status
Simulation time 148169258 ps
CPU time 0.79 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:11 PM PDT 24
Peak memory 206384 kb
Host smart-87d80cee-b2df-42b7-bafc-a7ca163d546b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181
91880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2818191880
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.2022046781
Short name T1876
Test name
Test status
Simulation time 1537701659 ps
CPU time 3.1 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 206584 kb
Host smart-46d759b8-db22-4037-8e48-30c1698fab93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20220
46781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.2022046781
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1492646800
Short name T101
Test name
Test status
Simulation time 7459324878 ps
CPU time 13.92 seconds
Started Jul 11 06:00:58 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206696 kb
Host smart-175048a7-eb69-412f-9a9c-3ef78fe284c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14926
46800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1492646800
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.1848347136
Short name T2030
Test name
Test status
Simulation time 334789253 ps
CPU time 1.17 seconds
Started Jul 11 06:01:04 PM PDT 24
Finished Jul 11 06:01:10 PM PDT 24
Peak memory 206364 kb
Host smart-2691c8fb-19dc-452d-9d12-672eb4372678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18483
47136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.1848347136
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.4067458894
Short name T509
Test name
Test status
Simulation time 143700307 ps
CPU time 0.74 seconds
Started Jul 11 06:01:02 PM PDT 24
Finished Jul 11 06:01:09 PM PDT 24
Peak memory 206304 kb
Host smart-fbf38627-e654-4a26-9074-5c6005019981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40674
58894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.4067458894
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3324744017
Short name T1341
Test name
Test status
Simulation time 92218373 ps
CPU time 0.72 seconds
Started Jul 11 06:01:15 PM PDT 24
Finished Jul 11 06:01:23 PM PDT 24
Peak memory 206388 kb
Host smart-56e53cce-bba1-43b5-ae52-75d762baa505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33247
44017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3324744017
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2171166547
Short name T1849
Test name
Test status
Simulation time 872164858 ps
CPU time 2.02 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:16 PM PDT 24
Peak memory 206588 kb
Host smart-c4fc97be-562f-4031-84e8-ae9a33b4f68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711
66547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2171166547
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.83711510
Short name T2465
Test name
Test status
Simulation time 244569927 ps
CPU time 1.45 seconds
Started Jul 11 06:01:02 PM PDT 24
Finished Jul 11 06:01:08 PM PDT 24
Peak memory 206580 kb
Host smart-8c3643c3-61ad-4136-807c-ce53aa1d81c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83711
510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.83711510
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.4005636552
Short name T1950
Test name
Test status
Simulation time 175929574 ps
CPU time 0.81 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206376 kb
Host smart-409975f3-cf7b-44a8-b8e7-8e01dcf4c50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40056
36552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.4005636552
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3492718937
Short name T685
Test name
Test status
Simulation time 145819598 ps
CPU time 0.75 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206396 kb
Host smart-eb358644-b9fb-454e-bdab-8e77b5bac5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34927
18937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3492718937
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.4243202076
Short name T356
Test name
Test status
Simulation time 224971893 ps
CPU time 0.87 seconds
Started Jul 11 06:01:04 PM PDT 24
Finished Jul 11 06:01:10 PM PDT 24
Peak memory 206360 kb
Host smart-dcba02de-04bb-4a53-8e9d-18d8c5d67a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42432
02076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.4243202076
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2057300609
Short name T2717
Test name
Test status
Simulation time 8889560559 ps
CPU time 250.36 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:05:29 PM PDT 24
Peak memory 206636 kb
Host smart-081847ef-d5d4-4bfb-91b9-8a43ccd65019
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2057300609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2057300609
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2227243922
Short name T650
Test name
Test status
Simulation time 6925146011 ps
CPU time 24.5 seconds
Started Jul 11 06:01:01 PM PDT 24
Finished Jul 11 06:01:31 PM PDT 24
Peak memory 206568 kb
Host smart-1eaeb7d6-f68d-4c4e-a506-eb25f94f3777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22272
43922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2227243922
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.383884451
Short name T1997
Test name
Test status
Simulation time 252397194 ps
CPU time 0.92 seconds
Started Jul 11 06:01:26 PM PDT 24
Finished Jul 11 06:01:39 PM PDT 24
Peak memory 206308 kb
Host smart-39457927-426b-4a1a-a432-c40fcd1ce788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
4451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.383884451
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1086102295
Short name T776
Test name
Test status
Simulation time 23330878890 ps
CPU time 21.38 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:01:40 PM PDT 24
Peak memory 206388 kb
Host smart-94584204-bbc3-476d-8087-8565de2f38df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
02295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1086102295
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.154345623
Short name T700
Test name
Test status
Simulation time 3301270411 ps
CPU time 3.6 seconds
Started Jul 11 06:01:06 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 206376 kb
Host smart-e43401e6-d01a-41d7-9d2a-2e3624fb0883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15434
5623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.154345623
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1565439607
Short name T2689
Test name
Test status
Simulation time 12010248315 ps
CPU time 108.49 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:03:08 PM PDT 24
Peak memory 206648 kb
Host smart-18a3e957-d66a-40d6-a682-a9998ba459d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15654
39607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1565439607
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3125306532
Short name T1638
Test name
Test status
Simulation time 4950165541 ps
CPU time 129.44 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:03:22 PM PDT 24
Peak memory 206572 kb
Host smart-1f8f8c26-8d56-49ba-b8ed-49a331de79d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3125306532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3125306532
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3595629561
Short name T1808
Test name
Test status
Simulation time 240729263 ps
CPU time 0.92 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206300 kb
Host smart-5f43fdf0-6f1d-47fa-9618-765e0ae98dd9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3595629561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3595629561
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.591385219
Short name T2119
Test name
Test status
Simulation time 190215080 ps
CPU time 0.84 seconds
Started Jul 11 06:01:04 PM PDT 24
Finished Jul 11 06:01:10 PM PDT 24
Peak memory 206380 kb
Host smart-f6a796f9-4ddb-4e1d-a629-2b8b8485903b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59138
5219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.591385219
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.417461620
Short name T410
Test name
Test status
Simulation time 5197769020 ps
CPU time 37.76 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:48 PM PDT 24
Peak memory 206580 kb
Host smart-dc9ed128-f661-4bb4-96ef-acdc7480042b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41746
1620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.417461620
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.4020574869
Short name T2353
Test name
Test status
Simulation time 5768554327 ps
CPU time 155.85 seconds
Started Jul 11 06:01:19 PM PDT 24
Finished Jul 11 06:04:03 PM PDT 24
Peak memory 206624 kb
Host smart-8ae34198-06c5-43ee-bbb0-e1aba3cb1d88
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4020574869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.4020574869
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.80523829
Short name T1295
Test name
Test status
Simulation time 154617297 ps
CPU time 0.76 seconds
Started Jul 11 06:01:00 PM PDT 24
Finished Jul 11 06:01:07 PM PDT 24
Peak memory 206384 kb
Host smart-eafb5cfc-be93-481a-b41f-54da3fafcfc8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=80523829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.80523829
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1771663102
Short name T924
Test name
Test status
Simulation time 156331146 ps
CPU time 0.84 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206388 kb
Host smart-92075ccc-898c-4878-ba5b-9b8f4b17eb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17716
63102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1771663102
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.3866455395
Short name T1984
Test name
Test status
Simulation time 137466862 ps
CPU time 0.75 seconds
Started Jul 11 06:00:59 PM PDT 24
Finished Jul 11 06:01:06 PM PDT 24
Peak memory 206296 kb
Host smart-6fa0284d-cc7a-4c12-bda8-9ec63c0edc41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38664
55395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3866455395
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3270229267
Short name T2462
Test name
Test status
Simulation time 168981255 ps
CPU time 0.77 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206304 kb
Host smart-de0fc565-18f4-44bc-b2dd-de669576931f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
29267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3270229267
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.915476448
Short name T906
Test name
Test status
Simulation time 168159915 ps
CPU time 0.8 seconds
Started Jul 11 06:01:10 PM PDT 24
Finished Jul 11 06:01:19 PM PDT 24
Peak memory 206384 kb
Host smart-d7328fd0-1ecc-4671-9f4a-27c11bb39451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91547
6448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.915476448
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3171010647
Short name T1494
Test name
Test status
Simulation time 145491644 ps
CPU time 0.76 seconds
Started Jul 11 06:01:10 PM PDT 24
Finished Jul 11 06:01:19 PM PDT 24
Peak memory 206396 kb
Host smart-42ab503b-7840-4a6e-b078-766687fccb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31710
10647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3171010647
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1976355254
Short name T1029
Test name
Test status
Simulation time 217835169 ps
CPU time 1.05 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:01:27 PM PDT 24
Peak memory 206256 kb
Host smart-571f7f1c-9648-4b65-a532-1a6ac2086844
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1976355254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1976355254
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2422969005
Short name T2209
Test name
Test status
Simulation time 213622830 ps
CPU time 0.8 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:01:26 PM PDT 24
Peak memory 206336 kb
Host smart-d1159a68-ed94-4ee7-8964-78bf4f2109ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24229
69005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2422969005
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.742998004
Short name T2165
Test name
Test status
Simulation time 40619578 ps
CPU time 0.71 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 206108 kb
Host smart-71e9f785-c44f-46c3-bbcb-3278065f45d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74299
8004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.742998004
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1206638396
Short name T1690
Test name
Test status
Simulation time 13684605653 ps
CPU time 28.51 seconds
Started Jul 11 06:01:16 PM PDT 24
Finished Jul 11 06:01:52 PM PDT 24
Peak memory 206728 kb
Host smart-9ab51231-ba02-40e9-b0c8-bbfe8eaa4109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12066
38396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1206638396
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1045384925
Short name T2170
Test name
Test status
Simulation time 179440879 ps
CPU time 0.88 seconds
Started Jul 11 06:01:06 PM PDT 24
Finished Jul 11 06:01:13 PM PDT 24
Peak memory 206532 kb
Host smart-c32a9f7c-0cf5-417f-a6bd-086eb2728831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10453
84925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1045384925
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2273617359
Short name T1947
Test name
Test status
Simulation time 263998925 ps
CPU time 0.94 seconds
Started Jul 11 06:01:26 PM PDT 24
Finished Jul 11 06:01:39 PM PDT 24
Peak memory 206360 kb
Host smart-088c711e-d31b-4b98-9165-4110a86c76d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22736
17359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2273617359
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1396501451
Short name T2027
Test name
Test status
Simulation time 199816568 ps
CPU time 0.84 seconds
Started Jul 11 06:01:06 PM PDT 24
Finished Jul 11 06:01:13 PM PDT 24
Peak memory 206268 kb
Host smart-e9a6e8ec-d6d5-4b65-b0fd-54376f9b977c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13965
01451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1396501451
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.704568251
Short name T2496
Test name
Test status
Simulation time 204520983 ps
CPU time 0.82 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 206368 kb
Host smart-f537bee6-ffcb-4c84-91cc-d6394b31e213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70456
8251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.704568251
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1050643538
Short name T1625
Test name
Test status
Simulation time 186602161 ps
CPU time 0.86 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:14 PM PDT 24
Peak memory 206384 kb
Host smart-49d8219c-4f2d-4a90-90be-da63d12b8a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
43538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1050643538
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2873109530
Short name T1298
Test name
Test status
Simulation time 168596705 ps
CPU time 0.79 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:16 PM PDT 24
Peak memory 206396 kb
Host smart-09e02bb4-7db6-4243-b708-517aefd0afe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28731
09530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2873109530
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3560687668
Short name T2459
Test name
Test status
Simulation time 153295842 ps
CPU time 0.82 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:01:19 PM PDT 24
Peak memory 206384 kb
Host smart-99662dbb-8cc7-437d-9e58-cc0c8bb6ca54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
87668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3560687668
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3318401363
Short name T911
Test name
Test status
Simulation time 194978372 ps
CPU time 0.86 seconds
Started Jul 11 06:01:13 PM PDT 24
Finished Jul 11 06:01:22 PM PDT 24
Peak memory 206384 kb
Host smart-7b4b0b25-5052-4e9a-b1db-0d68c701ec9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33184
01363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3318401363
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.805164884
Short name T1594
Test name
Test status
Simulation time 3056266290 ps
CPU time 22.08 seconds
Started Jul 11 06:01:10 PM PDT 24
Finished Jul 11 06:01:40 PM PDT 24
Peak memory 206572 kb
Host smart-84207dd4-64f6-491e-9412-c2f5a3fb6246
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=805164884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.805164884
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3437939963
Short name T985
Test name
Test status
Simulation time 214708975 ps
CPU time 0.84 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206348 kb
Host smart-c5ef7247-9943-438d-b2e5-5303786deb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
39963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3437939963
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.528972068
Short name T861
Test name
Test status
Simulation time 199929384 ps
CPU time 0.82 seconds
Started Jul 11 06:01:06 PM PDT 24
Finished Jul 11 06:01:13 PM PDT 24
Peak memory 206308 kb
Host smart-6fdb5fce-1492-456c-b26f-4006649ab1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52897
2068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.528972068
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.162135649
Short name T782
Test name
Test status
Simulation time 289085941 ps
CPU time 0.95 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:14 PM PDT 24
Peak memory 206388 kb
Host smart-db89d58c-96a4-4b7b-a77e-34a3c11a7851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16213
5649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.162135649
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2092212387
Short name T2694
Test name
Test status
Simulation time 2869728884 ps
CPU time 79.95 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:02:35 PM PDT 24
Peak memory 206596 kb
Host smart-ee10f08d-eee3-4b2a-9c73-05499b32a090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20922
12387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2092212387
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2010870329
Short name T1063
Test name
Test status
Simulation time 57351151 ps
CPU time 0.68 seconds
Started Jul 11 06:01:24 PM PDT 24
Finished Jul 11 06:01:35 PM PDT 24
Peak memory 206392 kb
Host smart-e435bb81-e30a-43d4-a0e9-a8bff32476c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2010870329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2010870329
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2823589399
Short name T1304
Test name
Test status
Simulation time 3858896224 ps
CPU time 5.55 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 206316 kb
Host smart-395cb3cd-509a-43c4-afb1-e2a78e938c8a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2823589399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.2823589399
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2118831570
Short name T1134
Test name
Test status
Simulation time 13406233123 ps
CPU time 14.85 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:48 PM PDT 24
Peak memory 206724 kb
Host smart-8d484ace-0758-4abd-b658-cfdc1e061340
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2118831570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2118831570
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1214709642
Short name T1402
Test name
Test status
Simulation time 23405575212 ps
CPU time 22.56 seconds
Started Jul 11 06:01:10 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206440 kb
Host smart-814374ca-5c7c-47e6-8403-4e0f5bd23987
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1214709642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1214709642
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2256190282
Short name T348
Test name
Test status
Simulation time 155003619 ps
CPU time 0.76 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 206376 kb
Host smart-35fd2547-25df-48ca-8526-575064572350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22561
90282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2256190282
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3423753107
Short name T1571
Test name
Test status
Simulation time 171255186 ps
CPU time 0.8 seconds
Started Jul 11 06:01:12 PM PDT 24
Finished Jul 11 06:01:21 PM PDT 24
Peak memory 206360 kb
Host smart-b71a2165-1a5f-4d2c-8c5c-bd2a001d5146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34237
53107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3423753107
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.375046230
Short name T690
Test name
Test status
Simulation time 194932310 ps
CPU time 0.89 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 205520 kb
Host smart-abb8d406-0ad8-409e-8b49-1be2d7987f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37504
6230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.375046230
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1995566192
Short name T636
Test name
Test status
Simulation time 667282263 ps
CPU time 1.71 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:01:21 PM PDT 24
Peak memory 206544 kb
Host smart-f44a0e5e-9550-4315-97fe-453d3aeb370c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19955
66192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1995566192
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.71105921
Short name T620
Test name
Test status
Simulation time 23215705483 ps
CPU time 40.58 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:52 PM PDT 24
Peak memory 206720 kb
Host smart-ea25595d-9181-4559-8372-9f9a151d27ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71105
921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.71105921
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.540109512
Short name T1195
Test name
Test status
Simulation time 479390171 ps
CPU time 1.32 seconds
Started Jul 11 06:01:06 PM PDT 24
Finished Jul 11 06:01:13 PM PDT 24
Peak memory 206528 kb
Host smart-c71fb4be-0211-48ca-971c-880714888028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54010
9512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.540109512
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1204788074
Short name T1648
Test name
Test status
Simulation time 212429794 ps
CPU time 0.81 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:14 PM PDT 24
Peak memory 206468 kb
Host smart-24364a05-b1bb-4909-a089-8608f05ca910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12047
88074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1204788074
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1769954753
Short name T1013
Test name
Test status
Simulation time 64190491 ps
CPU time 0.67 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:14 PM PDT 24
Peak memory 206372 kb
Host smart-6e14eb3c-f250-4ab1-ab32-a216313b8368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17699
54753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1769954753
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3236410353
Short name T1525
Test name
Test status
Simulation time 857521718 ps
CPU time 1.97 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:16 PM PDT 24
Peak memory 206588 kb
Host smart-82e4cf72-16c4-4289-a695-a18732a38bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32364
10353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3236410353
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1293271487
Short name T810
Test name
Test status
Simulation time 180982481 ps
CPU time 2.06 seconds
Started Jul 11 06:01:34 PM PDT 24
Finished Jul 11 06:01:48 PM PDT 24
Peak memory 206616 kb
Host smart-da4dd8a0-a6cd-473d-b48b-b6038b23f47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12932
71487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1293271487
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2106579579
Short name T1726
Test name
Test status
Simulation time 188715302 ps
CPU time 0.79 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:12 PM PDT 24
Peak memory 206376 kb
Host smart-21a13ceb-c358-42cb-a094-28a9e24cbeae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21065
79579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2106579579
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1516895518
Short name T392
Test name
Test status
Simulation time 143120204 ps
CPU time 0.78 seconds
Started Jul 11 06:01:05 PM PDT 24
Finished Jul 11 06:01:11 PM PDT 24
Peak memory 206384 kb
Host smart-3a086cac-acd1-45f8-86ad-13f6f7904ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15168
95518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1516895518
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2433645643
Short name T951
Test name
Test status
Simulation time 220054033 ps
CPU time 0.94 seconds
Started Jul 11 06:01:12 PM PDT 24
Finished Jul 11 06:01:21 PM PDT 24
Peak memory 206364 kb
Host smart-cacffae8-15de-4376-90f0-05de6d433fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24336
45643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2433645643
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1219336248
Short name T2184
Test name
Test status
Simulation time 8503261300 ps
CPU time 237.28 seconds
Started Jul 11 06:01:06 PM PDT 24
Finished Jul 11 06:05:09 PM PDT 24
Peak memory 206624 kb
Host smart-0ce10a57-bb83-4302-b4f8-a1ea2a9750b1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1219336248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1219336248
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.3255229842
Short name T2155
Test name
Test status
Simulation time 7428546187 ps
CPU time 28.5 seconds
Started Jul 11 06:01:28 PM PDT 24
Finished Jul 11 06:02:08 PM PDT 24
Peak memory 206564 kb
Host smart-0fcd8bf7-23f2-4dda-a1a1-64cc3cc90001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32552
29842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3255229842
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1835169295
Short name T2699
Test name
Test status
Simulation time 180215072 ps
CPU time 0.81 seconds
Started Jul 11 06:01:56 PM PDT 24
Finished Jul 11 06:02:14 PM PDT 24
Peak memory 206176 kb
Host smart-5aabb1d8-af4b-4417-bc46-82beaa9fecfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18351
69295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1835169295
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3575242458
Short name T1915
Test name
Test status
Simulation time 23327428658 ps
CPU time 24.04 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206324 kb
Host smart-53b8d51f-426f-478c-a31b-4ec50d814447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35752
42458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3575242458
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1760388151
Short name T354
Test name
Test status
Simulation time 3287605108 ps
CPU time 3.82 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 206464 kb
Host smart-9b2884f0-3c8e-4dee-a774-9959d50ef802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17603
88151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1760388151
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3575603266
Short name T2138
Test name
Test status
Simulation time 8452551129 ps
CPU time 236.55 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:05:12 PM PDT 24
Peak memory 206696 kb
Host smart-b0c75e14-0e13-4129-bb53-0d492dfd7764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35756
03266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3575603266
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.4120509166
Short name T592
Test name
Test status
Simulation time 4117333754 ps
CPU time 30.62 seconds
Started Jul 11 06:01:06 PM PDT 24
Finished Jul 11 06:01:43 PM PDT 24
Peak memory 206644 kb
Host smart-f1d9df2d-9964-4d1e-9c4e-13788b763590
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4120509166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.4120509166
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2942619238
Short name T1941
Test name
Test status
Simulation time 291440705 ps
CPU time 0.94 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 206380 kb
Host smart-0f0af91f-d39e-416a-a8c4-0493c9ca53f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2942619238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2942619238
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3082695776
Short name T1094
Test name
Test status
Simulation time 210897722 ps
CPU time 0.97 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 206096 kb
Host smart-675f13bf-1b8b-489a-b923-9d185a92e22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30826
95776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3082695776
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.4031492809
Short name T967
Test name
Test status
Simulation time 5215517550 ps
CPU time 35.92 seconds
Started Jul 11 06:01:07 PM PDT 24
Finished Jul 11 06:01:49 PM PDT 24
Peak memory 206648 kb
Host smart-7b46d1b9-2fd9-4565-af59-17ea0b677eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40314
92809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.4031492809
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3483923055
Short name T1272
Test name
Test status
Simulation time 4331338195 ps
CPU time 30.09 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:59 PM PDT 24
Peak memory 206676 kb
Host smart-1aea1554-c327-4863-bdce-662197ee6942
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3483923055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3483923055
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3764761665
Short name T729
Test name
Test status
Simulation time 178697023 ps
CPU time 0.81 seconds
Started Jul 11 06:01:24 PM PDT 24
Finished Jul 11 06:01:36 PM PDT 24
Peak memory 206388 kb
Host smart-714431ee-26c8-4117-a4b2-f19b5a1dd6f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3764761665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3764761665
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.308797994
Short name T596
Test name
Test status
Simulation time 148026475 ps
CPU time 0.77 seconds
Started Jul 11 06:01:08 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 205528 kb
Host smart-9100053a-8007-4955-9cbe-e7fd37be04fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
7994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.308797994
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3238937464
Short name T154
Test name
Test status
Simulation time 260733769 ps
CPU time 0.92 seconds
Started Jul 11 06:01:13 PM PDT 24
Finished Jul 11 06:01:22 PM PDT 24
Peak memory 206364 kb
Host smart-a9a0fd5e-644c-4b2f-91b1-8c6b62c26776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32389
37464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3238937464
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2992332936
Short name T2553
Test name
Test status
Simulation time 215420867 ps
CPU time 0.84 seconds
Started Jul 11 06:01:10 PM PDT 24
Finished Jul 11 06:01:19 PM PDT 24
Peak memory 206368 kb
Host smart-bcca4807-6ad1-43c6-8e30-17aeac4dcfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29923
32936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2992332936
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1706479749
Short name T728
Test name
Test status
Simulation time 181711930 ps
CPU time 0.82 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206328 kb
Host smart-6c55a8b3-352d-4281-b7c3-4cf9da39028a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17064
79749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1706479749
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3468029991
Short name T1917
Test name
Test status
Simulation time 174330439 ps
CPU time 0.8 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:01:36 PM PDT 24
Peak memory 206340 kb
Host smart-b6cc60ee-03a0-40ce-971c-52cee5038b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34680
29991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3468029991
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3770395933
Short name T1079
Test name
Test status
Simulation time 147117343 ps
CPU time 0.78 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:34 PM PDT 24
Peak memory 206392 kb
Host smart-07ebbc30-ec40-474c-a005-994156a3769b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37703
95933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3770395933
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.271032788
Short name T1829
Test name
Test status
Simulation time 204786437 ps
CPU time 0.91 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:40 PM PDT 24
Peak memory 206308 kb
Host smart-7f05e4ee-be10-49b4-90d3-39595dd1c13f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=271032788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.271032788
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1491885728
Short name T2666
Test name
Test status
Simulation time 183780858 ps
CPU time 0.83 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:33 PM PDT 24
Peak memory 206332 kb
Host smart-97077579-5dbf-4dfa-9996-7131d0ced481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14918
85728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1491885728
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.259769017
Short name T1651
Test name
Test status
Simulation time 69786520 ps
CPU time 0.68 seconds
Started Jul 11 06:01:20 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206380 kb
Host smart-e1613e7e-8a05-4381-96fd-7a17d5d46f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25976
9017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.259769017
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2152519206
Short name T1768
Test name
Test status
Simulation time 8355148258 ps
CPU time 20.25 seconds
Started Jul 11 06:01:19 PM PDT 24
Finished Jul 11 06:01:47 PM PDT 24
Peak memory 206716 kb
Host smart-15b25852-899a-4107-aef9-32a3bc5bef82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21525
19206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2152519206
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3843280797
Short name T1238
Test name
Test status
Simulation time 204515689 ps
CPU time 0.85 seconds
Started Jul 11 06:01:28 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206464 kb
Host smart-6ecbbbd9-9a25-46c7-91d7-f048681e38b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38432
80797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3843280797
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.667201809
Short name T673
Test name
Test status
Simulation time 235776773 ps
CPU time 0.88 seconds
Started Jul 11 06:01:28 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206300 kb
Host smart-760213ed-4d11-41c5-acd7-0dde947a3378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66720
1809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.667201809
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2296759269
Short name T451
Test name
Test status
Simulation time 237247637 ps
CPU time 0.96 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:01:27 PM PDT 24
Peak memory 206380 kb
Host smart-fe7899b0-c03a-42a1-af08-28404ec88292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22967
59269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2296759269
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2036094085
Short name T1274
Test name
Test status
Simulation time 157525701 ps
CPU time 0.81 seconds
Started Jul 11 06:01:13 PM PDT 24
Finished Jul 11 06:01:22 PM PDT 24
Peak memory 206308 kb
Host smart-96903cc4-66db-40a8-b90a-7ec937c537e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20360
94085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2036094085
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3755569432
Short name T568
Test name
Test status
Simulation time 160743688 ps
CPU time 0.79 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:01:26 PM PDT 24
Peak memory 206384 kb
Host smart-71e6cb0b-f5f2-4d31-b093-01d7a9214968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
69432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3755569432
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2315991205
Short name T838
Test name
Test status
Simulation time 165096098 ps
CPU time 0.77 seconds
Started Jul 11 06:01:20 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206384 kb
Host smart-002c1753-98ea-4ca7-b93a-1524dc54f0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23159
91205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2315991205
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.201554055
Short name T2395
Test name
Test status
Simulation time 148056541 ps
CPU time 0.77 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:01:27 PM PDT 24
Peak memory 206248 kb
Host smart-272ba60e-d3a8-47a5-8246-6626a829f156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20155
4055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.201554055
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2131015975
Short name T1780
Test name
Test status
Simulation time 208267749 ps
CPU time 0.93 seconds
Started Jul 11 06:01:19 PM PDT 24
Finished Jul 11 06:01:28 PM PDT 24
Peak memory 206352 kb
Host smart-c15204e2-2c7a-4ef1-a0b6-a29fbad40dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21310
15975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2131015975
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.816413158
Short name T1794
Test name
Test status
Simulation time 4335786660 ps
CPU time 30.26 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:02:07 PM PDT 24
Peak memory 206548 kb
Host smart-5c52bc2e-ec6b-4edb-9260-0c181e9552a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=816413158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.816413158
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2141784378
Short name T680
Test name
Test status
Simulation time 203140825 ps
CPU time 0.82 seconds
Started Jul 11 06:01:17 PM PDT 24
Finished Jul 11 06:01:26 PM PDT 24
Peak memory 206376 kb
Host smart-c350ddec-fc20-4215-9f85-2a06c92c9fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21417
84378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2141784378
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2951009854
Short name T676
Test name
Test status
Simulation time 192999351 ps
CPU time 0.81 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:33 PM PDT 24
Peak memory 206332 kb
Host smart-fe15bff1-6db1-470b-9688-f8c0a3892ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
09854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2951009854
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3578840354
Short name T2220
Test name
Test status
Simulation time 582853321 ps
CPU time 1.44 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:40 PM PDT 24
Peak memory 206304 kb
Host smart-b5124d3b-db36-495b-8256-72b82504cea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35788
40354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3578840354
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.260237185
Short name T704
Test name
Test status
Simulation time 5341390487 ps
CPU time 146.86 seconds
Started Jul 11 06:01:17 PM PDT 24
Finished Jul 11 06:03:52 PM PDT 24
Peak memory 206640 kb
Host smart-1efdf6b3-e2d6-4ba8-bcf5-075c9d1e2656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26023
7185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.260237185
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.2085011028
Short name T2687
Test name
Test status
Simulation time 42520030 ps
CPU time 0.7 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:42 PM PDT 24
Peak memory 206348 kb
Host smart-96f02565-a471-413e-9727-f55ecefbff8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2085011028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2085011028
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3432788508
Short name T1084
Test name
Test status
Simulation time 3502212707 ps
CPU time 4.03 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:34 PM PDT 24
Peak memory 206440 kb
Host smart-5c36cb03-3ba8-465d-8c08-bb0197f5d7e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3432788508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.3432788508
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.4244156635
Short name T2211
Test name
Test status
Simulation time 13298947402 ps
CPU time 15.35 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:48 PM PDT 24
Peak memory 206404 kb
Host smart-c64e6539-19a8-4b1c-b6a2-4a947c1edd19
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4244156635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.4244156635
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.2558407721
Short name T1913
Test name
Test status
Simulation time 23336122301 ps
CPU time 24.2 seconds
Started Jul 11 06:01:47 PM PDT 24
Finished Jul 11 06:02:23 PM PDT 24
Peak memory 206580 kb
Host smart-9e9b77f7-b241-498a-9f03-9efe4cad51cc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2558407721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.2558407721
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3511007549
Short name T120
Test name
Test status
Simulation time 144203060 ps
CPU time 0.76 seconds
Started Jul 11 06:01:24 PM PDT 24
Finished Jul 11 06:01:36 PM PDT 24
Peak memory 206416 kb
Host smart-c77310a9-1145-45da-b112-2854899a8e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35110
07549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3511007549
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.646547644
Short name T2577
Test name
Test status
Simulation time 151520139 ps
CPU time 0.81 seconds
Started Jul 11 06:01:20 PM PDT 24
Finished Jul 11 06:01:28 PM PDT 24
Peak memory 206400 kb
Host smart-0c190fc4-f063-401c-a3f5-c3c737ca989c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64654
7644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.646547644
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2536920649
Short name T1968
Test name
Test status
Simulation time 393979340 ps
CPU time 1.26 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:40 PM PDT 24
Peak memory 206300 kb
Host smart-cd323240-869b-41e8-b81f-0d107addf319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25369
20649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2536920649
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2078077137
Short name T822
Test name
Test status
Simulation time 752948384 ps
CPU time 1.67 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:01:19 PM PDT 24
Peak memory 206640 kb
Host smart-d15f7097-3431-4701-bf3a-257787080cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20780
77137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2078077137
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3097283382
Short name T2675
Test name
Test status
Simulation time 10859390932 ps
CPU time 20.46 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:52 PM PDT 24
Peak memory 206700 kb
Host smart-48d26346-7341-4be3-a679-2b2931a6ed17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30972
83382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3097283382
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1432210703
Short name T2225
Test name
Test status
Simulation time 454491368 ps
CPU time 1.44 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:01:21 PM PDT 24
Peak memory 206300 kb
Host smart-8d9d8291-73fb-4e98-a4d9-171b54789a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14322
10703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1432210703
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.4166363500
Short name T2468
Test name
Test status
Simulation time 142439569 ps
CPU time 0.75 seconds
Started Jul 11 06:01:17 PM PDT 24
Finished Jul 11 06:01:25 PM PDT 24
Peak memory 206388 kb
Host smart-e33840ff-9055-4167-a67a-2fadc9d54270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41663
63500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.4166363500
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3264180276
Short name T2231
Test name
Test status
Simulation time 50189387 ps
CPU time 0.66 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 206372 kb
Host smart-5e3d763e-3a6d-4465-8be1-0ef5e66e8b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32641
80276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3264180276
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3056222888
Short name T1366
Test name
Test status
Simulation time 953829819 ps
CPU time 2.29 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:01:28 PM PDT 24
Peak memory 206644 kb
Host smart-b7ff7151-8471-45b6-86c9-0ceaa607ef7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30562
22888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3056222888
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1920430957
Short name T1493
Test name
Test status
Simulation time 195654823 ps
CPU time 1.42 seconds
Started Jul 11 06:01:20 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 206612 kb
Host smart-cb8b7906-c182-4e92-a05c-4a6faa8c1bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19204
30957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1920430957
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.618387144
Short name T914
Test name
Test status
Simulation time 191126361 ps
CPU time 0.89 seconds
Started Jul 11 06:01:56 PM PDT 24
Finished Jul 11 06:02:14 PM PDT 24
Peak memory 206188 kb
Host smart-eb049c72-6d26-4789-991d-6801f8f4520b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61838
7144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.618387144
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.693720295
Short name T1321
Test name
Test status
Simulation time 178046653 ps
CPU time 0.81 seconds
Started Jul 11 06:01:20 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206308 kb
Host smart-6ca0ec41-19a9-4f9f-9408-cdc93bc9951f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69372
0295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.693720295
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1239605578
Short name T1585
Test name
Test status
Simulation time 221920037 ps
CPU time 0.89 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206348 kb
Host smart-170d3355-53ef-4acc-b7e3-31ef07623732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12396
05578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1239605578
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.719291191
Short name T1432
Test name
Test status
Simulation time 10324670416 ps
CPU time 88.56 seconds
Started Jul 11 06:01:11 PM PDT 24
Finished Jul 11 06:02:48 PM PDT 24
Peak memory 206552 kb
Host smart-ff47fa4c-c035-44db-ab5c-72e64dffd078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71929
1191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.719291191
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.4244123579
Short name T2677
Test name
Test status
Simulation time 188968967 ps
CPU time 0.89 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:39 PM PDT 24
Peak memory 206372 kb
Host smart-724ed2f3-eb2b-4f3c-be6a-970eab1c053f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42441
23579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.4244123579
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2944170690
Short name T1833
Test name
Test status
Simulation time 23285620627 ps
CPU time 26.78 seconds
Started Jul 11 06:01:09 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206460 kb
Host smart-15bc29b5-0a68-485a-a225-e2dc98c5d8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
70690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2944170690
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.669784485
Short name T1024
Test name
Test status
Simulation time 3326372399 ps
CPU time 3.61 seconds
Started Jul 11 06:01:20 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 206452 kb
Host smart-0b5f378e-17f6-4ffe-a46d-388c866b0cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66978
4485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.669784485
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2263362635
Short name T2088
Test name
Test status
Simulation time 7769743633 ps
CPU time 216.53 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:05:03 PM PDT 24
Peak memory 206736 kb
Host smart-a9725947-67ca-4e19-9636-ec38ec66f807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22633
62635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2263362635
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1408871282
Short name T1348
Test name
Test status
Simulation time 3900710498 ps
CPU time 36.71 seconds
Started Jul 11 06:01:29 PM PDT 24
Finished Jul 11 06:02:18 PM PDT 24
Peak memory 206568 kb
Host smart-741b0a21-d9bf-4f3b-8ada-26eae0d2e977
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1408871282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1408871282
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2022482269
Short name T2655
Test name
Test status
Simulation time 262709124 ps
CPU time 0.93 seconds
Started Jul 11 06:01:20 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206380 kb
Host smart-ada2c464-1431-4939-bc37-109cf2fb5fe7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2022482269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2022482269
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.106363591
Short name T1459
Test name
Test status
Simulation time 182124502 ps
CPU time 0.84 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 206408 kb
Host smart-0be19b48-acf8-4d07-bfbe-9cf30610bf4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10636
3591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.106363591
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.916072635
Short name T2188
Test name
Test status
Simulation time 3837359588 ps
CPU time 96.29 seconds
Started Jul 11 06:01:37 PM PDT 24
Finished Jul 11 06:03:26 PM PDT 24
Peak memory 206648 kb
Host smart-cb2f613b-3e2d-45e4-a355-f8c2d354bd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91607
2635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.916072635
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.129551974
Short name T848
Test name
Test status
Simulation time 2821631096 ps
CPU time 76.57 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:03:33 PM PDT 24
Peak memory 206592 kb
Host smart-6ecaf9ed-241e-409d-8e70-ccf1ca83a17a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=129551974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.129551974
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.228258515
Short name T1629
Test name
Test status
Simulation time 162206821 ps
CPU time 0.8 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:01:37 PM PDT 24
Peak memory 206336 kb
Host smart-fd9a0e95-bee1-4d3c-a770-67499ebaad22
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=228258515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.228258515
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2666075630
Short name T2130
Test name
Test status
Simulation time 155220054 ps
CPU time 0.77 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:01:37 PM PDT 24
Peak memory 206380 kb
Host smart-f496468a-f1f6-49f6-bef7-cc3d75f006c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
75630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2666075630
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3395512237
Short name T138
Test name
Test status
Simulation time 219934324 ps
CPU time 0.91 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 206388 kb
Host smart-8f8ef252-328a-43f1-9296-49c555e3b82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
12237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3395512237
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2936326933
Short name T1124
Test name
Test status
Simulation time 235494707 ps
CPU time 0.89 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206388 kb
Host smart-5ed3cd9f-f752-4b5d-949f-13407b308be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29363
26933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2936326933
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1522642249
Short name T2113
Test name
Test status
Simulation time 186556114 ps
CPU time 0.8 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 206324 kb
Host smart-7a5d4507-bfc4-44a2-bff5-7257daaa4aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15226
42249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1522642249
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.58688872
Short name T1665
Test name
Test status
Simulation time 219225337 ps
CPU time 0.86 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:01:37 PM PDT 24
Peak memory 206380 kb
Host smart-b5bb28bf-4160-4bd7-a8eb-5b907ad5619c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58688
872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.58688872
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.82640991
Short name T835
Test name
Test status
Simulation time 151095854 ps
CPU time 0.76 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 206388 kb
Host smart-a3be5d61-ae11-4f8d-aa7d-15c5ab132661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82640
991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.82640991
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3815441410
Short name T2359
Test name
Test status
Simulation time 268814616 ps
CPU time 0.95 seconds
Started Jul 11 06:01:34 PM PDT 24
Finished Jul 11 06:01:47 PM PDT 24
Peak memory 206404 kb
Host smart-278ab4f0-55e9-4318-8185-de7bfbad9dbf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3815441410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3815441410
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.4251831551
Short name T1972
Test name
Test status
Simulation time 149343940 ps
CPU time 0.78 seconds
Started Jul 11 06:01:19 PM PDT 24
Finished Jul 11 06:01:27 PM PDT 24
Peak memory 206260 kb
Host smart-744d71ac-42b8-40d6-902a-206829137f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42518
31551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.4251831551
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2234498856
Short name T1118
Test name
Test status
Simulation time 91228540 ps
CPU time 0.68 seconds
Started Jul 11 06:01:40 PM PDT 24
Finished Jul 11 06:01:53 PM PDT 24
Peak memory 206332 kb
Host smart-70cf123e-6234-4198-b4ba-3e32ceed9834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22344
98856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2234498856
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2297930694
Short name T2047
Test name
Test status
Simulation time 6327236117 ps
CPU time 14.79 seconds
Started Jul 11 06:01:19 PM PDT 24
Finished Jul 11 06:01:42 PM PDT 24
Peak memory 206660 kb
Host smart-a2d41732-7e4a-4242-989c-db5de0e55c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
30694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2297930694
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3501564575
Short name T954
Test name
Test status
Simulation time 147506173 ps
CPU time 0.76 seconds
Started Jul 11 06:01:20 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206400 kb
Host smart-61e39378-48f0-478d-a07f-c53f00816744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35015
64575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3501564575
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2950147090
Short name T1935
Test name
Test status
Simulation time 177124658 ps
CPU time 0.82 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206396 kb
Host smart-67e4dda4-3eba-4c0d-9cad-f52b8d0d8ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501
47090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2950147090
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1949926304
Short name T1587
Test name
Test status
Simulation time 256251372 ps
CPU time 0.9 seconds
Started Jul 11 06:01:28 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206388 kb
Host smart-81ac3dfd-f622-489e-8fea-ef8748ca69d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19499
26304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1949926304
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2571845547
Short name T2279
Test name
Test status
Simulation time 185930960 ps
CPU time 0.8 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:02:17 PM PDT 24
Peak memory 205876 kb
Host smart-8dbaf1e2-237b-40ca-b693-9cc08f5f9daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25718
45547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2571845547
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3526832645
Short name T2016
Test name
Test status
Simulation time 168812486 ps
CPU time 0.83 seconds
Started Jul 11 06:01:31 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206300 kb
Host smart-e10ea3fc-95fb-4ff2-a444-a8b6df546bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35268
32645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3526832645
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.603468328
Short name T551
Test name
Test status
Simulation time 187732544 ps
CPU time 0.79 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:40 PM PDT 24
Peak memory 206328 kb
Host smart-0e3bcdd0-96a6-48a1-a487-0cb6c4ba5aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60346
8328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.603468328
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2874012080
Short name T2281
Test name
Test status
Simulation time 151153937 ps
CPU time 0.75 seconds
Started Jul 11 06:07:07 PM PDT 24
Finished Jul 11 06:07:10 PM PDT 24
Peak memory 206384 kb
Host smart-511209fd-2d14-4f39-a092-96409aa6b26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28740
12080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2874012080
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1696590940
Short name T1427
Test name
Test status
Simulation time 207009989 ps
CPU time 0.88 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 206400 kb
Host smart-7e609cfe-f7b5-4c8d-b76c-623c4d05cf8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16965
90940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1696590940
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.137252078
Short name T2327
Test name
Test status
Simulation time 3005269470 ps
CPU time 77.07 seconds
Started Jul 11 06:01:35 PM PDT 24
Finished Jul 11 06:03:05 PM PDT 24
Peak memory 206564 kb
Host smart-b423647c-a23e-4b5a-9256-b1272a4e5eec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=137252078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.137252078
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3310032914
Short name T739
Test name
Test status
Simulation time 166733365 ps
CPU time 0.76 seconds
Started Jul 11 06:02:12 PM PDT 24
Finished Jul 11 06:02:31 PM PDT 24
Peak memory 206324 kb
Host smart-501f9df4-afa0-4037-aad6-689a9ac1e39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33100
32914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3310032914
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2933528346
Short name T1655
Test name
Test status
Simulation time 157889058 ps
CPU time 0.8 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 206416 kb
Host smart-53a96363-f35b-4657-a5cc-c7822c9829a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29335
28346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2933528346
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1909065133
Short name T2168
Test name
Test status
Simulation time 1088407147 ps
CPU time 2.15 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:45 PM PDT 24
Peak memory 206584 kb
Host smart-98649cd0-da9e-4b73-b4aa-97ffbd5cffe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19090
65133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1909065133
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3455053473
Short name T1760
Test name
Test status
Simulation time 3547882638 ps
CPU time 33.53 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206648 kb
Host smart-1bc706f0-f112-4f0d-b4b5-94beea4cc757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34550
53473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3455053473
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2969716449
Short name T699
Test name
Test status
Simulation time 33473350 ps
CPU time 0.65 seconds
Started Jul 11 06:01:31 PM PDT 24
Finished Jul 11 06:01:43 PM PDT 24
Peak memory 206344 kb
Host smart-a7b731fe-8b0a-4194-84fc-86e417282c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2969716449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2969716449
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1759668427
Short name T1192
Test name
Test status
Simulation time 3748792676 ps
CPU time 4.85 seconds
Started Jul 11 06:01:28 PM PDT 24
Finished Jul 11 06:01:45 PM PDT 24
Peak memory 206392 kb
Host smart-d199083c-93be-4d78-84b4-a24867b2108f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1759668427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.1759668427
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3194752696
Short name T1942
Test name
Test status
Simulation time 13337412314 ps
CPU time 12.28 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:51 PM PDT 24
Peak memory 206596 kb
Host smart-d2bfd359-106f-48a5-9ec0-03f50bcfe426
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3194752696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3194752696
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.4216031666
Short name T539
Test name
Test status
Simulation time 23314716723 ps
CPU time 22.47 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:52 PM PDT 24
Peak memory 206456 kb
Host smart-27231c88-03b3-4288-ae7a-e518dfa85694
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4216031666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.4216031666
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2221742362
Short name T2374
Test name
Test status
Simulation time 146876518 ps
CPU time 0.8 seconds
Started Jul 11 06:01:19 PM PDT 24
Finished Jul 11 06:01:28 PM PDT 24
Peak memory 206308 kb
Host smart-ac93587b-3212-4611-9a4d-bb31356c751e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22217
42362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2221742362
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2922385954
Short name T428
Test name
Test status
Simulation time 142264002 ps
CPU time 0.76 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:15 PM PDT 24
Peak memory 206316 kb
Host smart-1cb83330-7fb2-42ad-8290-1bbd0041df97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29223
85954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2922385954
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1412805809
Short name T519
Test name
Test status
Simulation time 398465489 ps
CPU time 1.29 seconds
Started Jul 11 06:01:35 PM PDT 24
Finished Jul 11 06:01:49 PM PDT 24
Peak memory 206396 kb
Host smart-55f04768-3905-4b9e-8037-8ab78db92b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14128
05809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1412805809
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2095110978
Short name T2698
Test name
Test status
Simulation time 1435928855 ps
CPU time 3.15 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:33 PM PDT 24
Peak memory 206548 kb
Host smart-5f73f335-4d58-4e50-a0e9-dd9d1ef7a3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20951
10978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2095110978
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2762831210
Short name T2467
Test name
Test status
Simulation time 9525653509 ps
CPU time 17.97 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:02:01 PM PDT 24
Peak memory 206648 kb
Host smart-51b908f8-98e9-4711-80b3-efa2365102b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27628
31210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2762831210
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1404985194
Short name T1051
Test name
Test status
Simulation time 468305676 ps
CPU time 1.38 seconds
Started Jul 11 06:01:44 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 206424 kb
Host smart-324392b5-4c98-4233-a482-bb0addd33728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14049
85194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1404985194
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.584717901
Short name T1191
Test name
Test status
Simulation time 153290694 ps
CPU time 0.78 seconds
Started Jul 11 06:01:39 PM PDT 24
Finished Jul 11 06:01:53 PM PDT 24
Peak memory 206388 kb
Host smart-971aafb3-3754-45e4-8e5c-555ee544cbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58471
7901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.584717901
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.689046084
Short name T1157
Test name
Test status
Simulation time 55122011 ps
CPU time 0.67 seconds
Started Jul 11 06:01:26 PM PDT 24
Finished Jul 11 06:01:38 PM PDT 24
Peak memory 206316 kb
Host smart-3f33a651-03df-4d3c-b62e-4710aac27307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68904
6084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.689046084
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.582501932
Short name T741
Test name
Test status
Simulation time 984101567 ps
CPU time 2.35 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:01:39 PM PDT 24
Peak memory 206608 kb
Host smart-5831675a-999c-4066-855a-891dd1f877ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58250
1932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.582501932
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3356230105
Short name T1117
Test name
Test status
Simulation time 400705764 ps
CPU time 2.38 seconds
Started Jul 11 06:01:57 PM PDT 24
Finished Jul 11 06:02:16 PM PDT 24
Peak memory 206576 kb
Host smart-bd7c5271-5ba5-4291-9386-745d5b3d9055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562
30105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3356230105
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2830412898
Short name T628
Test name
Test status
Simulation time 225320210 ps
CPU time 0.95 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:33 PM PDT 24
Peak memory 206404 kb
Host smart-176bcda1-7d25-4b7e-97ec-436f9d059e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28304
12898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2830412898
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3557311339
Short name T1634
Test name
Test status
Simulation time 187861546 ps
CPU time 0.79 seconds
Started Jul 11 06:01:29 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206388 kb
Host smart-543996f2-a5ab-4632-b274-4a82a62b145b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35573
11339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3557311339
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2655523188
Short name T684
Test name
Test status
Simulation time 158904627 ps
CPU time 0.8 seconds
Started Jul 11 06:01:34 PM PDT 24
Finished Jul 11 06:01:47 PM PDT 24
Peak memory 206388 kb
Host smart-17054d36-7cb5-425e-9f3d-c7921fefce8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26555
23188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2655523188
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1897137378
Short name T1704
Test name
Test status
Simulation time 9241216053 ps
CPU time 83.43 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:02:56 PM PDT 24
Peak memory 206564 kb
Host smart-3dba93a3-1141-4e3b-b2f8-6b0cd74417d7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1897137378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1897137378
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3130916
Short name T2517
Test name
Test status
Simulation time 9060772549 ps
CPU time 27.78 seconds
Started Jul 11 06:01:35 PM PDT 24
Finished Jul 11 06:02:16 PM PDT 24
Peak memory 206644 kb
Host smart-362e97e2-b695-4acf-b946-151d74ca5113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31309
16 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3130916
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2853878038
Short name T1824
Test name
Test status
Simulation time 172859115 ps
CPU time 0.86 seconds
Started Jul 11 06:01:37 PM PDT 24
Finished Jul 11 06:01:51 PM PDT 24
Peak memory 206392 kb
Host smart-ed3643c2-8b10-4f22-90d5-0a46efac5818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28538
78038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2853878038
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2709647515
Short name T1692
Test name
Test status
Simulation time 23327886089 ps
CPU time 27.63 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:02:09 PM PDT 24
Peak memory 206360 kb
Host smart-19fbc441-a58b-4b1b-ba08-aa5804a0b333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27096
47515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2709647515
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1957291056
Short name T498
Test name
Test status
Simulation time 3283376099 ps
CPU time 4.12 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:43 PM PDT 24
Peak memory 206408 kb
Host smart-3a540cb6-4b1d-4c11-99a9-f55b4cfb6781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19572
91056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1957291056
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.774344827
Short name T1017
Test name
Test status
Simulation time 9455488789 ps
CPU time 264.55 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:06:00 PM PDT 24
Peak memory 206712 kb
Host smart-b356793d-b6b9-452a-a178-a6c75f2c329c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77434
4827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.774344827
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.739204967
Short name T2071
Test name
Test status
Simulation time 4085999975 ps
CPU time 112.42 seconds
Started Jul 11 06:01:34 PM PDT 24
Finished Jul 11 06:03:39 PM PDT 24
Peak memory 206620 kb
Host smart-ec7130ef-bc2c-4a0a-8d5f-87733e118df3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=739204967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.739204967
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2375685103
Short name T587
Test name
Test status
Simulation time 248036518 ps
CPU time 0.9 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:33 PM PDT 24
Peak memory 206380 kb
Host smart-78897e22-b272-47dc-9fb2-0d79afbb26c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2375685103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2375685103
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1993254049
Short name T2076
Test name
Test status
Simulation time 184532518 ps
CPU time 0.87 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206296 kb
Host smart-307055a1-f4cb-4e98-92fe-2d9d55a9b1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
54049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1993254049
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1244599784
Short name T1663
Test name
Test status
Simulation time 3958216927 ps
CPU time 27.37 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:02:02 PM PDT 24
Peak memory 206760 kb
Host smart-c9717076-f101-49e7-8d44-8768d862eb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12445
99784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1244599784
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.198180948
Short name T2721
Test name
Test status
Simulation time 4254314770 ps
CPU time 40.67 seconds
Started Jul 11 06:01:18 PM PDT 24
Finished Jul 11 06:02:07 PM PDT 24
Peak memory 206640 kb
Host smart-92215f9f-531b-48db-a091-55664f5aaa87
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=198180948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.198180948
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3885656144
Short name T2151
Test name
Test status
Simulation time 188659935 ps
CPU time 0.82 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 206388 kb
Host smart-8bbacd23-6a61-438e-a916-e76b4e435327
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3885656144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3885656144
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1347000688
Short name T2160
Test name
Test status
Simulation time 197015248 ps
CPU time 0.82 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206264 kb
Host smart-8f62b506-0085-4b21-a201-92f88bfa35bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13470
00688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1347000688
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2961091767
Short name T2141
Test name
Test status
Simulation time 249506771 ps
CPU time 0.9 seconds
Started Jul 11 06:01:24 PM PDT 24
Finished Jul 11 06:01:36 PM PDT 24
Peak memory 206384 kb
Host smart-8ee9a7a7-170d-49ac-af2d-3b900eae8823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29610
91767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2961091767
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2433243520
Short name T105
Test name
Test status
Simulation time 212311266 ps
CPU time 0.85 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206348 kb
Host smart-ba299dab-a2cd-4c31-8b34-e9afbf34c381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24332
43520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2433243520
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2506102781
Short name T1206
Test name
Test status
Simulation time 160123820 ps
CPU time 0.79 seconds
Started Jul 11 06:01:19 PM PDT 24
Finished Jul 11 06:01:28 PM PDT 24
Peak memory 206392 kb
Host smart-a7b2eec0-5688-4e7c-b5b3-723fc8403266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061
02781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2506102781
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3146880426
Short name T1653
Test name
Test status
Simulation time 152911243 ps
CPU time 0.79 seconds
Started Jul 11 06:01:45 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 206348 kb
Host smart-2bc0765a-3000-412b-8ed2-21e5466233ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31468
80426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3146880426
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1850647172
Short name T536
Test name
Test status
Simulation time 162908964 ps
CPU time 0.8 seconds
Started Jul 11 06:01:27 PM PDT 24
Finished Jul 11 06:01:39 PM PDT 24
Peak memory 206392 kb
Host smart-4c66290d-7488-42a9-8f3a-d975a661d8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18506
47172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1850647172
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1433487978
Short name T1697
Test name
Test status
Simulation time 205686768 ps
CPU time 0.91 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 206400 kb
Host smart-0261ce41-9688-40f3-88d0-f44a1fa32136
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1433487978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1433487978
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2170525297
Short name T2658
Test name
Test status
Simulation time 144743875 ps
CPU time 0.77 seconds
Started Jul 11 06:01:24 PM PDT 24
Finished Jul 11 06:01:36 PM PDT 24
Peak memory 206400 kb
Host smart-047030fa-7f1f-4c73-a450-ee5891191d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21705
25297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2170525297
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3945229400
Short name T36
Test name
Test status
Simulation time 93108648 ps
CPU time 0.71 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:33 PM PDT 24
Peak memory 206352 kb
Host smart-36db0ad1-ffca-4944-9c1c-f8ad68aa30f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
29400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3945229400
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3272305601
Short name T1668
Test name
Test status
Simulation time 20540962034 ps
CPU time 42.3 seconds
Started Jul 11 06:01:31 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206616 kb
Host smart-1b38bfb1-15bd-42d4-ad77-6c43b90fcd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32723
05601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3272305601
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1274184258
Short name T2662
Test name
Test status
Simulation time 181431817 ps
CPU time 0.8 seconds
Started Jul 11 06:01:34 PM PDT 24
Finished Jul 11 06:01:47 PM PDT 24
Peak memory 206392 kb
Host smart-2112d7b0-6b0c-4086-8fac-fcb01255c9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12741
84258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1274184258
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1630886777
Short name T1147
Test name
Test status
Simulation time 278772906 ps
CPU time 0.94 seconds
Started Jul 11 06:01:53 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206384 kb
Host smart-701ec64a-8e01-488b-8ba4-fcd2d4047eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16308
86777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1630886777
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3812793830
Short name T1320
Test name
Test status
Simulation time 293278598 ps
CPU time 0.94 seconds
Started Jul 11 06:01:34 PM PDT 24
Finished Jul 11 06:01:47 PM PDT 24
Peak memory 206404 kb
Host smart-3d84e7db-a570-4c68-9bff-623a79fc8ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38127
93830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3812793830
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.627674420
Short name T565
Test name
Test status
Simulation time 191170712 ps
CPU time 0.88 seconds
Started Jul 11 06:01:32 PM PDT 24
Finished Jul 11 06:01:46 PM PDT 24
Peak memory 206468 kb
Host smart-9aebf19c-9fb4-4f34-a9b2-1c694ba3e480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62767
4420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.627674420
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.916807785
Short name T1159
Test name
Test status
Simulation time 191087560 ps
CPU time 1.02 seconds
Started Jul 11 06:01:22 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 206540 kb
Host smart-7239d65c-f2c6-43cc-89c1-153b609b0c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91680
7785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.916807785
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3135762679
Short name T2358
Test name
Test status
Simulation time 188172496 ps
CPU time 0.86 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206396 kb
Host smart-ba42f3c1-b07b-482b-a492-637b0e690a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
62679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3135762679
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2817018570
Short name T1737
Test name
Test status
Simulation time 165351815 ps
CPU time 0.86 seconds
Started Jul 11 06:01:26 PM PDT 24
Finished Jul 11 06:01:38 PM PDT 24
Peak memory 206332 kb
Host smart-e24d1dd5-4904-4b03-989c-260ab349018e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28170
18570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2817018570
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2406413893
Short name T1418
Test name
Test status
Simulation time 234537954 ps
CPU time 0.9 seconds
Started Jul 11 06:01:21 PM PDT 24
Finished Jul 11 06:01:29 PM PDT 24
Peak memory 206400 kb
Host smart-b67e5a48-cf6f-4855-a392-3944260c95d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064
13893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2406413893
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.245630725
Short name T2542
Test name
Test status
Simulation time 4896137331 ps
CPU time 33.97 seconds
Started Jul 11 06:02:01 PM PDT 24
Finished Jul 11 06:02:53 PM PDT 24
Peak memory 206552 kb
Host smart-7bb94771-64f9-47b2-b4cf-59b4fec1adec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=245630725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.245630725
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2227244737
Short name T2252
Test name
Test status
Simulation time 174215451 ps
CPU time 0.77 seconds
Started Jul 11 06:01:37 PM PDT 24
Finished Jul 11 06:01:51 PM PDT 24
Peak memory 206404 kb
Host smart-ba00f9e3-18ea-491f-aa4d-8820d3a06d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22272
44737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2227244737
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3702123382
Short name T2321
Test name
Test status
Simulation time 172293633 ps
CPU time 0.78 seconds
Started Jul 11 06:01:39 PM PDT 24
Finished Jul 11 06:01:53 PM PDT 24
Peak memory 206340 kb
Host smart-a299ac31-13bf-46ab-9d0a-7cffc51a89c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37021
23382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3702123382
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2339446401
Short name T2009
Test name
Test status
Simulation time 988098626 ps
CPU time 2.21 seconds
Started Jul 11 06:01:42 PM PDT 24
Finished Jul 11 06:01:57 PM PDT 24
Peak memory 206572 kb
Host smart-4878f4cd-b652-4adf-97f5-bf184a2e28ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23394
46401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2339446401
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1678855578
Short name T1750
Test name
Test status
Simulation time 4910436317 ps
CPU time 134.25 seconds
Started Jul 11 06:01:28 PM PDT 24
Finished Jul 11 06:03:55 PM PDT 24
Peak memory 206560 kb
Host smart-ae41fad5-76c2-4cc2-8fbf-814935c2ff8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16788
55578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1678855578
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3239363736
Short name T2330
Test name
Test status
Simulation time 37932716 ps
CPU time 0.65 seconds
Started Jul 11 06:01:51 PM PDT 24
Finished Jul 11 06:02:07 PM PDT 24
Peak memory 206424 kb
Host smart-e9c91c84-6508-4a6a-a4f4-54b02b436147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3239363736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3239363736
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2646163964
Short name T2574
Test name
Test status
Simulation time 4151854185 ps
CPU time 4.74 seconds
Started Jul 11 06:01:38 PM PDT 24
Finished Jul 11 06:01:56 PM PDT 24
Peak memory 206648 kb
Host smart-bee5a9d4-2857-4d58-a46a-2043b0a7165b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2646163964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.2646163964
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.948122195
Short name T2534
Test name
Test status
Simulation time 13371572900 ps
CPU time 11.79 seconds
Started Jul 11 06:01:45 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206352 kb
Host smart-cf7d6e12-49b9-4655-bbf5-32b85e32c00f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=948122195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.948122195
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3099006817
Short name T2311
Test name
Test status
Simulation time 23407010850 ps
CPU time 26.34 seconds
Started Jul 11 06:01:31 PM PDT 24
Finished Jul 11 06:02:09 PM PDT 24
Peak memory 206372 kb
Host smart-20214f21-2573-4a0a-b24b-4a5b58aebab5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3099006817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3099006817
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1065852591
Short name T2163
Test name
Test status
Simulation time 158454307 ps
CPU time 0.77 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:43 PM PDT 24
Peak memory 206328 kb
Host smart-eae78e41-d163-4486-aa07-cfa42714701f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10658
52591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1065852591
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1743439446
Short name T1603
Test name
Test status
Simulation time 158884914 ps
CPU time 0.88 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 206276 kb
Host smart-ef8f254a-ae8b-4e06-9d59-42265a0fa0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17434
39446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1743439446
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.4067033448
Short name T1998
Test name
Test status
Simulation time 232526885 ps
CPU time 0.88 seconds
Started Jul 11 06:01:37 PM PDT 24
Finished Jul 11 06:01:51 PM PDT 24
Peak memory 206400 kb
Host smart-ebdefa82-2425-4ede-8cb5-d7121d3ee1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40670
33448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.4067033448
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3021469814
Short name T2718
Test name
Test status
Simulation time 388581719 ps
CPU time 1.28 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 206372 kb
Host smart-d434948a-0c73-45c6-be10-b9e16778aa0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30214
69814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3021469814
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3112526583
Short name T186
Test name
Test status
Simulation time 15190540866 ps
CPU time 31.14 seconds
Started Jul 11 06:01:42 PM PDT 24
Finished Jul 11 06:02:26 PM PDT 24
Peak memory 206632 kb
Host smart-91885726-2075-4b14-bfe2-14b6f3b20186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31125
26583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3112526583
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.2950512746
Short name T1424
Test name
Test status
Simulation time 462593570 ps
CPU time 1.36 seconds
Started Jul 11 06:01:23 PM PDT 24
Finished Jul 11 06:01:34 PM PDT 24
Peak memory 206392 kb
Host smart-a328896b-910e-41c5-a1f4-983a6a215b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29505
12746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.2950512746
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.454105069
Short name T2199
Test name
Test status
Simulation time 150640058 ps
CPU time 0.78 seconds
Started Jul 11 06:01:45 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 206404 kb
Host smart-94a5bcdb-a744-4aca-b017-eb95e13f9735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45410
5069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.454105069
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.340336294
Short name T1500
Test name
Test status
Simulation time 61419601 ps
CPU time 0.7 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:43 PM PDT 24
Peak memory 206356 kb
Host smart-51ca90a6-532c-4c15-8ffa-22a0e8379f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34033
6294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.340336294
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3867462319
Short name T2218
Test name
Test status
Simulation time 739771986 ps
CPU time 1.93 seconds
Started Jul 11 06:01:36 PM PDT 24
Finished Jul 11 06:01:51 PM PDT 24
Peak memory 206664 kb
Host smart-b8097a35-3a3a-49d7-96e5-e5c9850bed61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38674
62319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3867462319
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2174403947
Short name T1225
Test name
Test status
Simulation time 173378783 ps
CPU time 1.35 seconds
Started Jul 11 06:01:31 PM PDT 24
Finished Jul 11 06:01:45 PM PDT 24
Peak memory 206616 kb
Host smart-b614a9af-a585-40ac-94dd-1bd48e777122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21744
03947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2174403947
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2268338414
Short name T1496
Test name
Test status
Simulation time 221283841 ps
CPU time 0.88 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 206280 kb
Host smart-1e45adb3-4e95-4598-9eea-f4eca696a916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22683
38414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2268338414
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1347796991
Short name T124
Test name
Test status
Simulation time 136521733 ps
CPU time 0.74 seconds
Started Jul 11 06:01:25 PM PDT 24
Finished Jul 11 06:01:36 PM PDT 24
Peak memory 206384 kb
Host smart-99540229-7c60-49b0-8ef5-65c322d27ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13477
96991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1347796991
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3247248701
Short name T2039
Test name
Test status
Simulation time 247586651 ps
CPU time 0.92 seconds
Started Jul 11 06:01:45 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 206344 kb
Host smart-cd47cd09-64c2-4628-8a35-e74c8d85ed7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472
48701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3247248701
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3199617376
Short name T1148
Test name
Test status
Simulation time 221310072 ps
CPU time 0.85 seconds
Started Jul 11 06:01:45 PM PDT 24
Finished Jul 11 06:01:59 PM PDT 24
Peak memory 206372 kb
Host smart-c8bbd956-e0ef-4fa4-bf94-b10781d76900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31996
17376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3199617376
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.1427721008
Short name T2709
Test name
Test status
Simulation time 23334999800 ps
CPU time 22.74 seconds
Started Jul 11 06:01:34 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206440 kb
Host smart-c045560d-5a1a-4d1e-8bab-a916b344bfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14277
21008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1427721008
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.832539097
Short name T2391
Test name
Test status
Simulation time 3331912529 ps
CPU time 3.8 seconds
Started Jul 11 06:01:28 PM PDT 24
Finished Jul 11 06:01:43 PM PDT 24
Peak memory 206440 kb
Host smart-b7018253-1818-4659-85af-32572e3ea609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83253
9097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.832539097
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.3957109211
Short name T1970
Test name
Test status
Simulation time 10070760684 ps
CPU time 81.8 seconds
Started Jul 11 06:01:29 PM PDT 24
Finished Jul 11 06:03:02 PM PDT 24
Peak memory 206612 kb
Host smart-d7380023-d88c-4281-a107-c2f494aa9136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39571
09211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.3957109211
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2246428513
Short name T1666
Test name
Test status
Simulation time 7071848998 ps
CPU time 201.81 seconds
Started Jul 11 06:01:31 PM PDT 24
Finished Jul 11 06:05:05 PM PDT 24
Peak memory 206652 kb
Host smart-26d8a9f6-2baa-4d56-8ff4-7d9ef9d98a45
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2246428513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2246428513
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2574440096
Short name T2122
Test name
Test status
Simulation time 286759367 ps
CPU time 0.99 seconds
Started Jul 11 06:01:43 PM PDT 24
Finished Jul 11 06:01:56 PM PDT 24
Peak memory 206392 kb
Host smart-1aa14343-4214-4cc6-a4e7-4d56569f8f51
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2574440096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2574440096
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.61223537
Short name T2316
Test name
Test status
Simulation time 202361430 ps
CPU time 0.86 seconds
Started Jul 11 06:01:26 PM PDT 24
Finished Jul 11 06:01:39 PM PDT 24
Peak memory 206372 kb
Host smart-8e1a56f6-9966-4a49-92a4-f548f2412cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61223
537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.61223537
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.209258476
Short name T588
Test name
Test status
Simulation time 5501722144 ps
CPU time 156.4 seconds
Started Jul 11 06:01:38 PM PDT 24
Finished Jul 11 06:04:27 PM PDT 24
Peak memory 206668 kb
Host smart-c76f9689-d158-4dc9-aebb-953275bdecfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20925
8476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.209258476
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2795384259
Short name T1331
Test name
Test status
Simulation time 4814409242 ps
CPU time 134.39 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:03:56 PM PDT 24
Peak memory 206628 kb
Host smart-abf45899-f089-4967-942c-9a6739a5b0a3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2795384259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2795384259
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.2906128965
Short name T619
Test name
Test status
Simulation time 153565340 ps
CPU time 0.75 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:16 PM PDT 24
Peak memory 206384 kb
Host smart-9eb6509c-ba2c-457b-bc3b-d51ca511fa70
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2906128965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2906128965
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1694684843
Short name T1778
Test name
Test status
Simulation time 158213714 ps
CPU time 0.77 seconds
Started Jul 11 06:01:40 PM PDT 24
Finished Jul 11 06:01:53 PM PDT 24
Peak memory 206372 kb
Host smart-748640ba-df2b-4ab4-a96d-8696d1d97039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
84843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1694684843
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1404447220
Short name T132
Test name
Test status
Simulation time 220654167 ps
CPU time 0.92 seconds
Started Jul 11 06:01:47 PM PDT 24
Finished Jul 11 06:02:01 PM PDT 24
Peak memory 206388 kb
Host smart-2da8fbbf-377b-41fd-8b89-9019cecb5555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14044
47220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1404447220
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2673141543
Short name T2203
Test name
Test status
Simulation time 187792257 ps
CPU time 0.88 seconds
Started Jul 11 06:01:47 PM PDT 24
Finished Jul 11 06:02:00 PM PDT 24
Peak memory 206420 kb
Host smart-160ce54c-4325-44e1-8876-62917daa249b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26731
41543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2673141543
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1781544334
Short name T108
Test name
Test status
Simulation time 161938350 ps
CPU time 0.79 seconds
Started Jul 11 06:01:40 PM PDT 24
Finished Jul 11 06:01:54 PM PDT 24
Peak memory 206384 kb
Host smart-14d7250c-cc2b-455e-825f-16f788b5b8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17815
44334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1781544334
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3913254438
Short name T32
Test name
Test status
Simulation time 157720771 ps
CPU time 0.75 seconds
Started Jul 11 06:01:29 PM PDT 24
Finished Jul 11 06:01:41 PM PDT 24
Peak memory 206332 kb
Host smart-a1b96190-e651-4e17-ab85-01d5fd5cbf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39132
54438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3913254438
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2953435001
Short name T471
Test name
Test status
Simulation time 196891837 ps
CPU time 0.82 seconds
Started Jul 11 06:01:44 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 206388 kb
Host smart-1a628c25-5762-475b-893f-3f2b05d2bf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29534
35001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2953435001
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.1562299799
Short name T1785
Test name
Test status
Simulation time 218085579 ps
CPU time 0.92 seconds
Started Jul 11 06:01:30 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206264 kb
Host smart-4dc9d81e-31aa-4e55-ab10-3f08526ef5b8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1562299799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.1562299799
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1049375889
Short name T1615
Test name
Test status
Simulation time 134506070 ps
CPU time 0.76 seconds
Started Jul 11 06:01:31 PM PDT 24
Finished Jul 11 06:01:44 PM PDT 24
Peak memory 206384 kb
Host smart-eda12b3a-2ea2-4e03-8f7c-d877e4b6a7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10493
75889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1049375889
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.363111994
Short name T1513
Test name
Test status
Simulation time 33309424 ps
CPU time 0.66 seconds
Started Jul 11 06:01:42 PM PDT 24
Finished Jul 11 06:01:55 PM PDT 24
Peak memory 206316 kb
Host smart-6c8730ee-f932-45a9-b787-848f6c953ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36311
1994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.363111994
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2055799289
Short name T1045
Test name
Test status
Simulation time 9635029690 ps
CPU time 22.19 seconds
Started Jul 11 06:01:43 PM PDT 24
Finished Jul 11 06:02:17 PM PDT 24
Peak memory 206668 kb
Host smart-2f58a0a7-5934-4037-b4f0-a4e1652e6d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
99289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2055799289
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.558979160
Short name T1364
Test name
Test status
Simulation time 163504640 ps
CPU time 0.84 seconds
Started Jul 11 06:01:36 PM PDT 24
Finished Jul 11 06:01:50 PM PDT 24
Peak memory 206400 kb
Host smart-c3cf5d72-f5fe-4bfe-9fde-7a358b43c1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55897
9160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.558979160
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2214507747
Short name T1754
Test name
Test status
Simulation time 209854020 ps
CPU time 0.87 seconds
Started Jul 11 06:01:44 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 206308 kb
Host smart-e9023e39-b342-47a2-a684-12eb4759a6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22145
07747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2214507747
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2065423244
Short name T748
Test name
Test status
Simulation time 243278365 ps
CPU time 0.88 seconds
Started Jul 11 06:01:55 PM PDT 24
Finished Jul 11 06:02:12 PM PDT 24
Peak memory 206312 kb
Host smart-638f6de8-9f14-4095-bb64-f6735f3a704a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20654
23244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2065423244
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.608502095
Short name T2735
Test name
Test status
Simulation time 187000868 ps
CPU time 0.88 seconds
Started Jul 11 06:01:39 PM PDT 24
Finished Jul 11 06:01:53 PM PDT 24
Peak memory 206368 kb
Host smart-67407f4a-1190-478f-a957-e28b898b6ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60850
2095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.608502095
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2719198213
Short name T77
Test name
Test status
Simulation time 178454093 ps
CPU time 0.8 seconds
Started Jul 11 06:01:38 PM PDT 24
Finished Jul 11 06:01:52 PM PDT 24
Peak memory 206380 kb
Host smart-cb8cd2e0-30cb-4eb1-b016-fe38f1b809b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27191
98213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2719198213
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1089783196
Short name T2292
Test name
Test status
Simulation time 193362238 ps
CPU time 0.8 seconds
Started Jul 11 06:01:43 PM PDT 24
Finished Jul 11 06:01:56 PM PDT 24
Peak memory 206380 kb
Host smart-510bf74f-e8bb-4b93-934c-d8186f4cfb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10897
83196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1089783196
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1649340257
Short name T1960
Test name
Test status
Simulation time 193269760 ps
CPU time 0.82 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:23 PM PDT 24
Peak memory 206368 kb
Host smart-315ce456-b91e-4b89-9c3e-2177af99a183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16493
40257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1649340257
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3581095046
Short name T1870
Test name
Test status
Simulation time 268257800 ps
CPU time 1.03 seconds
Started Jul 11 06:01:41 PM PDT 24
Finished Jul 11 06:01:55 PM PDT 24
Peak memory 206396 kb
Host smart-3175c965-0b93-46b8-bd5a-4bd136c5a1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35810
95046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3581095046
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.655687743
Short name T1982
Test name
Test status
Simulation time 6211284395 ps
CPU time 171.78 seconds
Started Jul 11 06:01:52 PM PDT 24
Finished Jul 11 06:04:59 PM PDT 24
Peak memory 206652 kb
Host smart-106c838e-cea8-4fac-bed3-fb6d6fa2c525
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=655687743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.655687743
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1522577035
Short name T1791
Test name
Test status
Simulation time 151646706 ps
CPU time 0.76 seconds
Started Jul 11 06:01:50 PM PDT 24
Finished Jul 11 06:02:05 PM PDT 24
Peak memory 206424 kb
Host smart-3c40e06f-caed-4337-aca5-ca7dc01bef7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15225
77035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1522577035
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1545582834
Short name T426
Test name
Test status
Simulation time 177057737 ps
CPU time 0.84 seconds
Started Jul 11 06:01:42 PM PDT 24
Finished Jul 11 06:01:55 PM PDT 24
Peak memory 206308 kb
Host smart-29f139d4-70b3-4497-a872-b295471f6609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15455
82834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1545582834
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.851707158
Short name T1001
Test name
Test status
Simulation time 839973857 ps
CPU time 1.88 seconds
Started Jul 11 06:01:42 PM PDT 24
Finished Jul 11 06:01:56 PM PDT 24
Peak memory 206652 kb
Host smart-f4913e8d-4c2a-4f27-ba58-c8cf7e7c00a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85170
7158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.851707158
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3078384632
Short name T1694
Test name
Test status
Simulation time 6016723392 ps
CPU time 173.19 seconds
Started Jul 11 06:01:53 PM PDT 24
Finished Jul 11 06:05:02 PM PDT 24
Peak memory 206652 kb
Host smart-aee338c7-3bd1-49f7-8f37-5df9006f82bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30783
84632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3078384632
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1632752145
Short name T2489
Test name
Test status
Simulation time 73114343 ps
CPU time 0.7 seconds
Started Jul 11 06:01:56 PM PDT 24
Finished Jul 11 06:02:14 PM PDT 24
Peak memory 206396 kb
Host smart-054e1053-7936-4090-93d0-77d7674cde26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1632752145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1632752145
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1258465191
Short name T2238
Test name
Test status
Simulation time 3794700021 ps
CPU time 4.44 seconds
Started Jul 11 06:01:38 PM PDT 24
Finished Jul 11 06:01:55 PM PDT 24
Peak memory 206628 kb
Host smart-68d77699-8501-417a-8198-aff2d0d6a65c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1258465191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1258465191
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1359976520
Short name T805
Test name
Test status
Simulation time 13346806312 ps
CPU time 13.55 seconds
Started Jul 11 06:01:56 PM PDT 24
Finished Jul 11 06:02:27 PM PDT 24
Peak memory 206632 kb
Host smart-8dae3034-d754-460c-b7bc-6774b015cb87
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1359976520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1359976520
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3109945331
Short name T1720
Test name
Test status
Simulation time 23357084782 ps
CPU time 25.48 seconds
Started Jul 11 06:01:37 PM PDT 24
Finished Jul 11 06:02:15 PM PDT 24
Peak memory 206704 kb
Host smart-47d697fa-4b44-4d2d-aeea-c26a84989b09
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3109945331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3109945331
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3176986033
Short name T1178
Test name
Test status
Simulation time 226177743 ps
CPU time 0.92 seconds
Started Jul 11 06:01:53 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206384 kb
Host smart-fe8a6432-7cfb-4000-8995-c324be5607c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
86033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3176986033
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3885739052
Short name T378
Test name
Test status
Simulation time 180302187 ps
CPU time 0.76 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206312 kb
Host smart-2eeda223-cfc8-4a7d-a00d-5a26415f87e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38857
39052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3885739052
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3412660718
Short name T1457
Test name
Test status
Simulation time 487411515 ps
CPU time 1.54 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206308 kb
Host smart-5a49d55a-71c0-4f6f-b557-8d558b0f8f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34126
60718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3412660718
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1607496663
Short name T2242
Test name
Test status
Simulation time 1063723686 ps
CPU time 2.31 seconds
Started Jul 11 06:01:39 PM PDT 24
Finished Jul 11 06:01:55 PM PDT 24
Peak memory 206676 kb
Host smart-8ddfe30e-0e91-48fd-aadc-a3350c98e5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16074
96663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1607496663
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.4202689782
Short name T1273
Test name
Test status
Simulation time 8641854206 ps
CPU time 15.12 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:30 PM PDT 24
Peak memory 206696 kb
Host smart-be2f5e13-6774-4244-8230-6cfdeba50f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42026
89782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.4202689782
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1295619397
Short name T2149
Test name
Test status
Simulation time 417950442 ps
CPU time 1.31 seconds
Started Jul 11 06:01:51 PM PDT 24
Finished Jul 11 06:02:07 PM PDT 24
Peak memory 206392 kb
Host smart-eacdde59-cd6d-480f-b268-a80aad1574ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12956
19397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1295619397
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2215040606
Short name T2312
Test name
Test status
Simulation time 143334395 ps
CPU time 0.76 seconds
Started Jul 11 06:01:57 PM PDT 24
Finished Jul 11 06:02:15 PM PDT 24
Peak memory 206320 kb
Host smart-aa10bb81-93d3-4996-97c0-eee9c95f7452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22150
40606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2215040606
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3866122686
Short name T1416
Test name
Test status
Simulation time 107677150 ps
CPU time 0.73 seconds
Started Jul 11 06:01:54 PM PDT 24
Finished Jul 11 06:02:11 PM PDT 24
Peak memory 206392 kb
Host smart-19e58454-518d-44b7-80a4-d39259c71372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38661
22686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3866122686
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.2757849605
Short name T1182
Test name
Test status
Simulation time 912961144 ps
CPU time 2.21 seconds
Started Jul 11 06:02:01 PM PDT 24
Finished Jul 11 06:02:21 PM PDT 24
Peak memory 206668 kb
Host smart-a4253ec8-9506-4e8b-89da-9293c5615e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27578
49605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2757849605
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.521013935
Short name T1399
Test name
Test status
Simulation time 188126528 ps
CPU time 2.1 seconds
Started Jul 11 06:01:45 PM PDT 24
Finished Jul 11 06:02:00 PM PDT 24
Peak memory 206552 kb
Host smart-6f579464-4118-4a2b-925d-ba98673e1b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52101
3935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.521013935
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2243656768
Short name T1072
Test name
Test status
Simulation time 174862367 ps
CPU time 0.79 seconds
Started Jul 11 06:02:01 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 206388 kb
Host smart-8cd11a25-251b-4057-a450-4f29a6ab7c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22436
56768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2243656768
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1705603480
Short name T2233
Test name
Test status
Simulation time 133628687 ps
CPU time 0.79 seconds
Started Jul 11 06:01:52 PM PDT 24
Finished Jul 11 06:02:08 PM PDT 24
Peak memory 206324 kb
Host smart-c24128dc-1dd1-4cfe-b909-f18a50771f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17056
03480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1705603480
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3024279096
Short name T2190
Test name
Test status
Simulation time 197345169 ps
CPU time 0.81 seconds
Started Jul 11 06:01:43 PM PDT 24
Finished Jul 11 06:01:56 PM PDT 24
Peak memory 206400 kb
Host smart-ea130c7a-6260-49ef-ba80-7193b07ce2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30242
79096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3024279096
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3525698458
Short name T230
Test name
Test status
Simulation time 7259259801 ps
CPU time 50.14 seconds
Started Jul 11 06:01:48 PM PDT 24
Finished Jul 11 06:02:52 PM PDT 24
Peak memory 206676 kb
Host smart-8ddd1341-e622-40a2-8e90-9b781810ea5f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3525698458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3525698458
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.528584015
Short name T2650
Test name
Test status
Simulation time 281851636 ps
CPU time 0.99 seconds
Started Jul 11 06:01:44 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 206380 kb
Host smart-55486995-49bb-4a07-b55d-848f3ed2baf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52858
4015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.528584015
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.179717335
Short name T902
Test name
Test status
Simulation time 23286577616 ps
CPU time 26.96 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:52 PM PDT 24
Peak memory 206372 kb
Host smart-164dabc3-e2d8-41d0-bec8-089aa708618b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17971
7335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.179717335
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.3085451589
Short name T1842
Test name
Test status
Simulation time 8545522265 ps
CPU time 234.03 seconds
Started Jul 11 06:01:48 PM PDT 24
Finished Jul 11 06:05:56 PM PDT 24
Peak memory 206740 kb
Host smart-d7850437-4156-4468-b465-1288afb20296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30854
51589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3085451589
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.146500674
Short name T725
Test name
Test status
Simulation time 7696150686 ps
CPU time 73.99 seconds
Started Jul 11 06:01:47 PM PDT 24
Finished Jul 11 06:03:13 PM PDT 24
Peak memory 206628 kb
Host smart-1318039f-540f-4068-b480-7dfae353717e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=146500674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.146500674
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2214283685
Short name T1297
Test name
Test status
Simulation time 252776778 ps
CPU time 0.89 seconds
Started Jul 11 06:01:46 PM PDT 24
Finished Jul 11 06:02:00 PM PDT 24
Peak memory 206380 kb
Host smart-2a82010f-4d34-4c6f-a755-702d3c7c082d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2214283685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2214283685
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3205661067
Short name T639
Test name
Test status
Simulation time 181929022 ps
CPU time 0.82 seconds
Started Jul 11 06:01:48 PM PDT 24
Finished Jul 11 06:02:02 PM PDT 24
Peak memory 206388 kb
Host smart-d0acc7a3-74ef-4336-a204-93b6c2269a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32056
61067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3205661067
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.3102323286
Short name T1085
Test name
Test status
Simulation time 5192128442 ps
CPU time 133.65 seconds
Started Jul 11 06:01:38 PM PDT 24
Finished Jul 11 06:04:05 PM PDT 24
Peak memory 206664 kb
Host smart-095299bc-7d62-405e-a85b-c80e9d4ac378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31023
23286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.3102323286
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1863195516
Short name T1396
Test name
Test status
Simulation time 6426802530 ps
CPU time 181.67 seconds
Started Jul 11 06:01:44 PM PDT 24
Finished Jul 11 06:04:58 PM PDT 24
Peak memory 206620 kb
Host smart-6265da2e-280d-4d70-8cbe-31a5c5cab531
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1863195516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1863195516
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3899243676
Short name T455
Test name
Test status
Simulation time 150343892 ps
CPU time 0.8 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:02:17 PM PDT 24
Peak memory 206404 kb
Host smart-059a4da5-69af-494e-b5d2-ff338f58a3dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3899243676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3899243676
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4018565262
Short name T2054
Test name
Test status
Simulation time 148032770 ps
CPU time 0.75 seconds
Started Jul 11 06:01:50 PM PDT 24
Finished Jul 11 06:02:05 PM PDT 24
Peak memory 206300 kb
Host smart-b5084a00-3450-4ec3-bc3a-e16e262f6073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40185
65262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4018565262
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1143877111
Short name T140
Test name
Test status
Simulation time 169387226 ps
CPU time 0.83 seconds
Started Jul 11 06:01:47 PM PDT 24
Finished Jul 11 06:02:00 PM PDT 24
Peak memory 206388 kb
Host smart-1c25c4c8-ad2e-4bf5-b490-f5f79a144676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11438
77111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1143877111
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3829862122
Short name T809
Test name
Test status
Simulation time 171149860 ps
CPU time 0.77 seconds
Started Jul 11 06:01:44 PM PDT 24
Finished Jul 11 06:01:57 PM PDT 24
Peak memory 206348 kb
Host smart-86aa4100-b9a8-4a6e-ba14-f60e56370e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38298
62122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3829862122
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1359965472
Short name T694
Test name
Test status
Simulation time 266701882 ps
CPU time 0.92 seconds
Started Jul 11 06:01:41 PM PDT 24
Finished Jul 11 06:01:55 PM PDT 24
Peak memory 206388 kb
Host smart-d559fb5d-3d39-4e3d-8956-a6917fae2546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13599
65472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1359965472
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2856024563
Short name T1682
Test name
Test status
Simulation time 171945628 ps
CPU time 0.84 seconds
Started Jul 11 06:01:44 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 206372 kb
Host smart-8a052feb-a0a1-4c97-a905-edf3d7266022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28560
24563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2856024563
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.586674996
Short name T1729
Test name
Test status
Simulation time 157691044 ps
CPU time 0.8 seconds
Started Jul 11 06:01:36 PM PDT 24
Finished Jul 11 06:01:50 PM PDT 24
Peak memory 206404 kb
Host smart-fac4d817-d696-4f9a-bdd4-c529a84a54ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58667
4996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.586674996
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3462660875
Short name T1161
Test name
Test status
Simulation time 210464700 ps
CPU time 0.9 seconds
Started Jul 11 06:01:53 PM PDT 24
Finished Jul 11 06:02:09 PM PDT 24
Peak memory 206388 kb
Host smart-2bf4975d-0e72-4397-9c94-17b1e4c32d81
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3462660875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3462660875
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1964009219
Short name T2040
Test name
Test status
Simulation time 138289933 ps
CPU time 0.75 seconds
Started Jul 11 06:01:46 PM PDT 24
Finished Jul 11 06:01:59 PM PDT 24
Peak memory 206336 kb
Host smart-92dec25a-43e6-4ae8-a038-dd1d7a80df4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19640
09219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1964009219
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.13363931
Short name T1501
Test name
Test status
Simulation time 89900619 ps
CPU time 0.71 seconds
Started Jul 11 06:01:55 PM PDT 24
Finished Jul 11 06:02:13 PM PDT 24
Peak memory 206384 kb
Host smart-9576bb8f-8352-40d9-8780-e89d0047608c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.13363931
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3445596303
Short name T2214
Test name
Test status
Simulation time 16633345114 ps
CPU time 40.65 seconds
Started Jul 11 06:01:45 PM PDT 24
Finished Jul 11 06:02:38 PM PDT 24
Peak memory 206620 kb
Host smart-16a7dc38-ac04-43a1-b635-19a3596169e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34455
96303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3445596303
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3964317048
Short name T788
Test name
Test status
Simulation time 181237603 ps
CPU time 0.86 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:24 PM PDT 24
Peak memory 206388 kb
Host smart-44c70b32-8187-4dbc-a3db-84739026f440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39643
17048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3964317048
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1709233303
Short name T1169
Test name
Test status
Simulation time 215887594 ps
CPU time 0.86 seconds
Started Jul 11 06:01:50 PM PDT 24
Finished Jul 11 06:02:05 PM PDT 24
Peak memory 206300 kb
Host smart-e98e56b4-18c1-419e-97a5-2ec9ba18f4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092
33303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1709233303
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3928511162
Short name T2192
Test name
Test status
Simulation time 208969186 ps
CPU time 0.9 seconds
Started Jul 11 06:01:42 PM PDT 24
Finished Jul 11 06:01:55 PM PDT 24
Peak memory 206372 kb
Host smart-90d75aaa-129d-4bd4-94e9-125e06a78ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39285
11162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3928511162
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3074290037
Short name T1326
Test name
Test status
Simulation time 221979795 ps
CPU time 0.9 seconds
Started Jul 11 06:02:09 PM PDT 24
Finished Jul 11 06:02:28 PM PDT 24
Peak memory 206316 kb
Host smart-035954df-90a5-4c67-a6cf-9e3e22ddfc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742
90037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3074290037
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1997718799
Short name T612
Test name
Test status
Simulation time 171066436 ps
CPU time 0.83 seconds
Started Jul 11 06:02:05 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206552 kb
Host smart-b4cc9b14-9909-4694-b20c-63ed0ecaaae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19977
18799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1997718799
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.215689102
Short name T940
Test name
Test status
Simulation time 156309394 ps
CPU time 0.76 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206300 kb
Host smart-383b19a1-5bd2-49fb-b4ef-aff4ef3d23a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568
9102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.215689102
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2332670304
Short name T1856
Test name
Test status
Simulation time 155616816 ps
CPU time 0.78 seconds
Started Jul 11 06:01:54 PM PDT 24
Finished Jul 11 06:02:12 PM PDT 24
Peak memory 206312 kb
Host smart-70faf5ad-642c-41e4-8259-c7d847638ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23326
70304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2332670304
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1452865765
Short name T669
Test name
Test status
Simulation time 277644592 ps
CPU time 0.96 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:24 PM PDT 24
Peak memory 206556 kb
Host smart-08cb1ae0-e99a-4f78-b10e-4571734c3033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14528
65765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1452865765
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3446842162
Short name T1014
Test name
Test status
Simulation time 4371058125 ps
CPU time 40.76 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:44 PM PDT 24
Peak memory 206600 kb
Host smart-ae4bd367-9c66-45fb-bd97-2b7d8f6474c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3446842162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3446842162
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3764107184
Short name T468
Test name
Test status
Simulation time 220021868 ps
CPU time 0.89 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 206560 kb
Host smart-a13ab9f8-a242-43c9-bfe8-553d74fead29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37641
07184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3764107184
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.564579271
Short name T1011
Test name
Test status
Simulation time 180376468 ps
CPU time 0.81 seconds
Started Jul 11 06:01:54 PM PDT 24
Finished Jul 11 06:02:11 PM PDT 24
Peak memory 206384 kb
Host smart-f2ff23bd-e98c-40ea-843e-49199ab2e147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56457
9271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.564579271
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3338496629
Short name T2313
Test name
Test status
Simulation time 705765000 ps
CPU time 1.69 seconds
Started Jul 11 06:01:51 PM PDT 24
Finished Jul 11 06:02:08 PM PDT 24
Peak memory 206640 kb
Host smart-52e89592-0f6e-4ac2-9281-8c8c0597fecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33384
96629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3338496629
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1738379718
Short name T858
Test name
Test status
Simulation time 3477929506 ps
CPU time 32.91 seconds
Started Jul 11 06:01:42 PM PDT 24
Finished Jul 11 06:02:27 PM PDT 24
Peak memory 206832 kb
Host smart-acefdc10-7963-4a1b-8952-cc136d9eb852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17383
79718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1738379718
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.883620434
Short name T1209
Test name
Test status
Simulation time 73178022 ps
CPU time 0.72 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:16 PM PDT 24
Peak memory 206436 kb
Host smart-7db27935-fd1c-4dd1-a722-70e98f996503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=883620434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.883620434
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2024024139
Short name T1904
Test name
Test status
Simulation time 3676624200 ps
CPU time 4.57 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:29 PM PDT 24
Peak memory 206392 kb
Host smart-78adcb20-2de3-408c-8024-90c4817384b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2024024139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2024024139
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.146966413
Short name T1930
Test name
Test status
Simulation time 13330819980 ps
CPU time 13.5 seconds
Started Jul 11 06:02:01 PM PDT 24
Finished Jul 11 06:02:32 PM PDT 24
Peak memory 206580 kb
Host smart-24de03c0-40b2-4446-b6cd-c926d9f800fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=146966413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.146966413
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1883781551
Short name T731
Test name
Test status
Simulation time 23391162478 ps
CPU time 23.06 seconds
Started Jul 11 06:01:57 PM PDT 24
Finished Jul 11 06:02:37 PM PDT 24
Peak memory 206728 kb
Host smart-0668aee5-daec-4df9-853c-653a00c076cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1883781551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1883781551
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.4214124429
Short name T1196
Test name
Test status
Simulation time 151120008 ps
CPU time 0.79 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 206396 kb
Host smart-9a614b92-d19e-4f35-ad55-35190c9bb56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42141
24429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.4214124429
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3593153012
Short name T1967
Test name
Test status
Simulation time 149280063 ps
CPU time 0.81 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:02:17 PM PDT 24
Peak memory 206312 kb
Host smart-5ab04772-e942-4acf-b5c5-c6eb3c401332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931
53012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3593153012
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2689665915
Short name T813
Test name
Test status
Simulation time 370993248 ps
CPU time 1.14 seconds
Started Jul 11 06:02:05 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206364 kb
Host smart-536d8eae-a171-4471-b08d-4226cb841e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26896
65915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2689665915
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1804560374
Short name T1480
Test name
Test status
Simulation time 1195463281 ps
CPU time 2.58 seconds
Started Jul 11 06:02:01 PM PDT 24
Finished Jul 11 06:02:21 PM PDT 24
Peak memory 206588 kb
Host smart-822458d4-eb14-4ae7-97d8-b4c6b8344893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18045
60374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1804560374
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.1328345114
Short name T1969
Test name
Test status
Simulation time 19829734037 ps
CPU time 35 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:38 PM PDT 24
Peak memory 206684 kb
Host smart-b92b1ad1-8c36-4e5f-897c-1c396eca1560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13283
45114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1328345114
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1862659785
Short name T957
Test name
Test status
Simulation time 408667501 ps
CPU time 1.21 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 206316 kb
Host smart-14433985-bad1-4b96-a844-85c86a3b6460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18626
59785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1862659785
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3760133597
Short name T381
Test name
Test status
Simulation time 188744926 ps
CPU time 0.76 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:02:18 PM PDT 24
Peak memory 206304 kb
Host smart-dbc31167-72fe-4eb5-92c8-09cabe8eb283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37601
33597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3760133597
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2332457233
Short name T248
Test name
Test status
Simulation time 49035839 ps
CPU time 0.65 seconds
Started Jul 11 06:02:07 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206340 kb
Host smart-f454c834-3390-45b3-b06f-f62ecab2678e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23324
57233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2332457233
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.4164349908
Short name T842
Test name
Test status
Simulation time 785061012 ps
CPU time 1.86 seconds
Started Jul 11 06:01:50 PM PDT 24
Finished Jul 11 06:02:06 PM PDT 24
Peak memory 206488 kb
Host smart-4b5a5c55-f583-4f34-825f-a6b7b812b439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643
49908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.4164349908
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1126167015
Short name T2156
Test name
Test status
Simulation time 184056049 ps
CPU time 2.14 seconds
Started Jul 11 06:01:54 PM PDT 24
Finished Jul 11 06:02:12 PM PDT 24
Peak memory 206636 kb
Host smart-0cbc0518-9664-40b6-b088-ca1298287eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11261
67015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1126167015
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1523793294
Short name T662
Test name
Test status
Simulation time 252127489 ps
CPU time 0.86 seconds
Started Jul 11 06:01:55 PM PDT 24
Finished Jul 11 06:02:13 PM PDT 24
Peak memory 206300 kb
Host smart-991eb969-6cd2-4919-b29e-428b213bb2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15237
93294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1523793294
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3594921819
Short name T1446
Test name
Test status
Simulation time 161705093 ps
CPU time 0.73 seconds
Started Jul 11 06:01:54 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206396 kb
Host smart-3563c060-90f3-48dc-8c4b-4aa0d6e6eae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35949
21819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3594921819
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2956527247
Short name T1228
Test name
Test status
Simulation time 262011076 ps
CPU time 1.01 seconds
Started Jul 11 06:02:12 PM PDT 24
Finished Jul 11 06:02:31 PM PDT 24
Peak memory 206364 kb
Host smart-5264018a-401d-4cdf-b2db-9d30cdaee68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29565
27247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2956527247
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.300630191
Short name T2332
Test name
Test status
Simulation time 6869636089 ps
CPU time 188.24 seconds
Started Jul 11 06:01:50 PM PDT 24
Finished Jul 11 06:05:12 PM PDT 24
Peak memory 206656 kb
Host smart-a89406bf-7b68-4472-8769-6dc9de500263
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=300630191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.300630191
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.757582801
Short name T1828
Test name
Test status
Simulation time 268466897 ps
CPU time 0.94 seconds
Started Jul 11 06:01:46 PM PDT 24
Finished Jul 11 06:02:05 PM PDT 24
Peak memory 206388 kb
Host smart-02959c0e-2a01-4bcf-8d40-081351e76fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75758
2801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.757582801
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.325872211
Short name T2256
Test name
Test status
Simulation time 23261073832 ps
CPU time 27.52 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:52 PM PDT 24
Peak memory 206352 kb
Host smart-63a875a7-81bd-4941-8d97-7f03bcb1022c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32587
2211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.325872211
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2880185646
Short name T1688
Test name
Test status
Simulation time 3274759723 ps
CPU time 3.92 seconds
Started Jul 11 06:01:50 PM PDT 24
Finished Jul 11 06:02:08 PM PDT 24
Peak memory 206368 kb
Host smart-38cb1ef1-ce8f-4f0e-87b0-c6805f1d5d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28801
85646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2880185646
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3074373218
Short name T2077
Test name
Test status
Simulation time 10501204095 ps
CPU time 76.42 seconds
Started Jul 11 06:01:52 PM PDT 24
Finished Jul 11 06:03:24 PM PDT 24
Peak memory 206708 kb
Host smart-d845e330-1eab-4052-bc78-5b257f35f74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30743
73218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3074373218
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2368687190
Short name T2502
Test name
Test status
Simulation time 4446829516 ps
CPU time 128.81 seconds
Started Jul 11 06:01:47 PM PDT 24
Finished Jul 11 06:04:08 PM PDT 24
Peak memory 206632 kb
Host smart-d0e49398-08f3-4913-92a4-aa247d458d4a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2368687190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2368687190
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.605608454
Short name T1257
Test name
Test status
Simulation time 255830499 ps
CPU time 0.92 seconds
Started Jul 11 06:02:10 PM PDT 24
Finished Jul 11 06:02:30 PM PDT 24
Peak memory 206364 kb
Host smart-92a64dcd-4fe0-462c-abce-a1c051df7b84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=605608454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.605608454
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3049021977
Short name T1221
Test name
Test status
Simulation time 192735526 ps
CPU time 0.87 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:03 PM PDT 24
Peak memory 206404 kb
Host smart-afe598c2-9757-4f0a-8a10-9a2d2abd65b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30490
21977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3049021977
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.4024300718
Short name T2624
Test name
Test status
Simulation time 5724007795 ps
CPU time 161.6 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:05:05 PM PDT 24
Peak memory 206668 kb
Host smart-1192f26b-2543-4f09-9b07-4a828d2aff38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40243
00718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.4024300718
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.885405121
Short name T2132
Test name
Test status
Simulation time 7829975124 ps
CPU time 74.03 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:03:39 PM PDT 24
Peak memory 206684 kb
Host smart-c65cc480-3e0d-4ff0-9cb9-477add95039e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=885405121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.885405121
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2535863079
Short name T2373
Test name
Test status
Simulation time 156208297 ps
CPU time 0.82 seconds
Started Jul 11 06:01:56 PM PDT 24
Finished Jul 11 06:02:14 PM PDT 24
Peak memory 206356 kb
Host smart-495db2b0-3bab-455f-81b3-6b324a75a1c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2535863079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2535863079
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3051975991
Short name T1877
Test name
Test status
Simulation time 222044904 ps
CPU time 0.81 seconds
Started Jul 11 06:01:55 PM PDT 24
Finished Jul 11 06:02:14 PM PDT 24
Peak memory 206304 kb
Host smart-13abf602-8ebc-497c-a0c3-d4cc7b3fc517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30519
75991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3051975991
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.724258809
Short name T133
Test name
Test status
Simulation time 173155075 ps
CPU time 0.83 seconds
Started Jul 11 06:01:53 PM PDT 24
Finished Jul 11 06:02:09 PM PDT 24
Peak memory 206380 kb
Host smart-70fb4eec-682b-494e-a25f-41e7ac8b0508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72425
8809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.724258809
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.895404338
Short name T2422
Test name
Test status
Simulation time 168453224 ps
CPU time 0.8 seconds
Started Jul 11 06:01:57 PM PDT 24
Finished Jul 11 06:02:14 PM PDT 24
Peak memory 206340 kb
Host smart-41c5aac4-9600-4f68-b1a5-3f02317cae88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89540
4338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.895404338
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1819580360
Short name T507
Test name
Test status
Simulation time 230060266 ps
CPU time 0.89 seconds
Started Jul 11 06:02:12 PM PDT 24
Finished Jul 11 06:02:31 PM PDT 24
Peak memory 206384 kb
Host smart-95e4d58c-eef5-4558-b4a3-b0e001974113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
80360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1819580360
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.4204970441
Short name T1451
Test name
Test status
Simulation time 179838156 ps
CPU time 0.82 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206392 kb
Host smart-4fbd4e26-f6bf-4239-b70f-f6cd8dc96d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42049
70441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.4204970441
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.483923654
Short name T1784
Test name
Test status
Simulation time 162264544 ps
CPU time 0.78 seconds
Started Jul 11 06:02:05 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206380 kb
Host smart-b939880c-c940-462b-b035-f7fa9ebd1ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48392
3654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.483923654
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.920210525
Short name T1260
Test name
Test status
Simulation time 239702346 ps
CPU time 0.93 seconds
Started Jul 11 06:01:51 PM PDT 24
Finished Jul 11 06:02:08 PM PDT 24
Peak memory 206308 kb
Host smart-39d6575a-cf8c-46e6-8b40-66a0774a25a2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=920210525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.920210525
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3047547562
Short name T1462
Test name
Test status
Simulation time 135753839 ps
CPU time 0.74 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:03 PM PDT 24
Peak memory 206332 kb
Host smart-abf73499-35dd-472e-a238-38c266489e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30475
47562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3047547562
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2078895490
Short name T1231
Test name
Test status
Simulation time 32375297 ps
CPU time 0.69 seconds
Started Jul 11 06:01:54 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206380 kb
Host smart-253af22a-75db-405c-842b-e6fa524ba79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20788
95490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2078895490
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1930676250
Short name T1795
Test name
Test status
Simulation time 12409438986 ps
CPU time 26.48 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:02:43 PM PDT 24
Peak memory 206860 kb
Host smart-d50b66b2-77ae-49d7-86ee-35c7fe5df0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19306
76250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1930676250
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2760873037
Short name T2725
Test name
Test status
Simulation time 160211446 ps
CPU time 0.78 seconds
Started Jul 11 06:02:05 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206380 kb
Host smart-056d9725-a3c3-4929-9372-a8c1f4efde26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27608
73037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2760873037
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2201091106
Short name T533
Test name
Test status
Simulation time 206683625 ps
CPU time 0.86 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 206392 kb
Host smart-6de071ef-b8f1-41f2-a05a-4780d8b3b346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22010
91106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2201091106
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3229270291
Short name T1661
Test name
Test status
Simulation time 216906642 ps
CPU time 0.83 seconds
Started Jul 11 06:02:10 PM PDT 24
Finished Jul 11 06:02:35 PM PDT 24
Peak memory 206404 kb
Host smart-68816ec3-9774-4521-bdbc-1e687b0ce2a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32292
70291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3229270291
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.2511205611
Short name T2207
Test name
Test status
Simulation time 146460071 ps
CPU time 0.8 seconds
Started Jul 11 06:02:02 PM PDT 24
Finished Jul 11 06:02:20 PM PDT 24
Peak memory 206424 kb
Host smart-614d4082-e071-4003-8006-94ede7bddee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25112
05611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.2511205611
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3255242222
Short name T986
Test name
Test status
Simulation time 138810574 ps
CPU time 0.76 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:24 PM PDT 24
Peak memory 206352 kb
Host smart-5e322839-530c-4512-95a1-79b54248b4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32552
42222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3255242222
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.4193943646
Short name T2194
Test name
Test status
Simulation time 235464012 ps
CPU time 0.8 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:24 PM PDT 24
Peak memory 206396 kb
Host smart-d8d58916-7dd1-4ef1-bccb-589b0d7b5023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41939
43646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.4193943646
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2451995173
Short name T779
Test name
Test status
Simulation time 153572632 ps
CPU time 0.76 seconds
Started Jul 11 06:01:50 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 206332 kb
Host smart-e70eb292-b5e4-4353-944c-9d18b29880cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24519
95173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2451995173
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2321506793
Short name T1142
Test name
Test status
Simulation time 233849443 ps
CPU time 0.93 seconds
Started Jul 11 06:01:55 PM PDT 24
Finished Jul 11 06:02:14 PM PDT 24
Peak memory 206276 kb
Host smart-7003a480-dc6d-4107-aa33-1b0784111f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23215
06793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2321506793
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2750026640
Short name T1612
Test name
Test status
Simulation time 6122700725 ps
CPU time 55.85 seconds
Started Jul 11 06:02:10 PM PDT 24
Finished Jul 11 06:03:25 PM PDT 24
Peak memory 206648 kb
Host smart-5ea5e88c-fecf-4c79-86ae-bb1dfe5227de
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2750026640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2750026640
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.551269015
Short name T1775
Test name
Test status
Simulation time 160887867 ps
CPU time 0.8 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:15 PM PDT 24
Peak memory 206312 kb
Host smart-73824aab-a65f-4f11-8a02-82c526e00381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55126
9015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.551269015
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.18941071
Short name T1056
Test name
Test status
Simulation time 223609132 ps
CPU time 0.84 seconds
Started Jul 11 06:01:49 PM PDT 24
Finished Jul 11 06:02:03 PM PDT 24
Peak memory 206328 kb
Host smart-e1faa626-9434-4057-933f-7b157dc77387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18941
071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.18941071
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.2081754609
Short name T649
Test name
Test status
Simulation time 713006652 ps
CPU time 1.7 seconds
Started Jul 11 06:01:48 PM PDT 24
Finished Jul 11 06:02:03 PM PDT 24
Peak memory 206584 kb
Host smart-37e36ff5-2972-422b-93b1-5d06d94c1882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20817
54609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.2081754609
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1724864425
Short name T475
Test name
Test status
Simulation time 3427170698 ps
CPU time 89.49 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:03:53 PM PDT 24
Peak memory 206676 kb
Host smart-665ca6a4-1c91-44d4-91aa-596abecf62e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
64425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1724864425
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3263091483
Short name T1093
Test name
Test status
Simulation time 30060246 ps
CPU time 0.65 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:02:17 PM PDT 24
Peak memory 206412 kb
Host smart-0cd12143-64da-4389-b46a-ec165aa823cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3263091483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3263091483
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3190292814
Short name T705
Test name
Test status
Simulation time 3990826798 ps
CPU time 5.48 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:20 PM PDT 24
Peak memory 206872 kb
Host smart-a95d4c39-5812-4bf3-b0aa-53a9d1338f12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3190292814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3190292814
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1700671700
Short name T1622
Test name
Test status
Simulation time 13304399069 ps
CPU time 12.19 seconds
Started Jul 11 06:01:57 PM PDT 24
Finished Jul 11 06:02:26 PM PDT 24
Peak memory 206368 kb
Host smart-10864720-4746-486e-acdb-b31a4237cf75
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1700671700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1700671700
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.1610203335
Short name T1532
Test name
Test status
Simulation time 23391369129 ps
CPU time 30.14 seconds
Started Jul 11 06:01:53 PM PDT 24
Finished Jul 11 06:02:40 PM PDT 24
Peak memory 206448 kb
Host smart-b7f5b36e-a452-45d3-ad5d-65d8d799b992
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1610203335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.1610203335
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2455987989
Short name T1379
Test name
Test status
Simulation time 187127599 ps
CPU time 0.86 seconds
Started Jul 11 06:02:10 PM PDT 24
Finished Jul 11 06:02:30 PM PDT 24
Peak memory 206400 kb
Host smart-e8649c76-5ae2-45a3-8e8d-fd06713080b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24559
87989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2455987989
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.474281479
Short name T997
Test name
Test status
Simulation time 150178841 ps
CPU time 0.76 seconds
Started Jul 11 06:02:17 PM PDT 24
Finished Jul 11 06:02:37 PM PDT 24
Peak memory 206400 kb
Host smart-1d69205d-6402-4f61-9db0-31d15ac8f332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47428
1479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.474281479
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2312530186
Short name T2172
Test name
Test status
Simulation time 396653249 ps
CPU time 1.38 seconds
Started Jul 11 06:01:53 PM PDT 24
Finished Jul 11 06:02:11 PM PDT 24
Peak memory 206380 kb
Host smart-dbed9cbf-b157-49a6-95d9-a31a7d35f9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23125
30186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2312530186
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.530135243
Short name T2596
Test name
Test status
Simulation time 1443879145 ps
CPU time 3.25 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:18 PM PDT 24
Peak memory 206812 kb
Host smart-30bbc795-8c80-4fe1-bef7-7612cdb6ace0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53013
5243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.530135243
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1562860392
Short name T1347
Test name
Test status
Simulation time 15895183986 ps
CPU time 25.39 seconds
Started Jul 11 06:02:12 PM PDT 24
Finished Jul 11 06:02:56 PM PDT 24
Peak memory 206580 kb
Host smart-190f0bdd-0bb2-4220-b3c7-dc12a478edbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15628
60392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1562860392
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1173509998
Short name T491
Test name
Test status
Simulation time 350253555 ps
CPU time 1.19 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:16 PM PDT 24
Peak memory 206408 kb
Host smart-08def94b-8645-4a3e-9031-e5cb7a6869e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11735
09998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1173509998
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1773685216
Short name T398
Test name
Test status
Simulation time 177623475 ps
CPU time 0.78 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 206396 kb
Host smart-9d3c38cc-b311-4dde-b649-d84ce7b4de52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17736
85216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1773685216
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1423481823
Short name T2544
Test name
Test status
Simulation time 37440456 ps
CPU time 0.65 seconds
Started Jul 11 06:02:14 PM PDT 24
Finished Jul 11 06:02:34 PM PDT 24
Peak memory 206340 kb
Host smart-be54ceab-4326-428d-a8da-a2d5506433df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234
81823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1423481823
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3211845815
Short name T1345
Test name
Test status
Simulation time 906273948 ps
CPU time 2.13 seconds
Started Jul 11 06:02:09 PM PDT 24
Finished Jul 11 06:02:29 PM PDT 24
Peak memory 206540 kb
Host smart-bb7bca86-8a82-48a7-925b-34ef05692604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
45815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3211845815
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3499862677
Short name T2139
Test name
Test status
Simulation time 255288397 ps
CPU time 1.7 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:17 PM PDT 24
Peak memory 206500 kb
Host smart-b75374ae-9c65-4264-bb2b-fe4d3539d5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34998
62677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3499862677
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3790379839
Short name T2609
Test name
Test status
Simulation time 222143086 ps
CPU time 0.89 seconds
Started Jul 11 06:01:50 PM PDT 24
Finished Jul 11 06:02:05 PM PDT 24
Peak memory 206380 kb
Host smart-7a36a8d0-ba36-4831-8c01-c2bdc72827bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37903
79839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3790379839
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2608358743
Short name T1325
Test name
Test status
Simulation time 139228020 ps
CPU time 0.78 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:02:17 PM PDT 24
Peak memory 206308 kb
Host smart-f4a18cd3-5d3c-4045-9b9d-55d943d9c5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26083
58743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2608358743
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2295256641
Short name T1235
Test name
Test status
Simulation time 194823919 ps
CPU time 0.85 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 206396 kb
Host smart-53a1468c-e1b6-4f01-afaa-637bc7ed913d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22952
56641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2295256641
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1742231999
Short name T1275
Test name
Test status
Simulation time 6769251625 ps
CPU time 47.35 seconds
Started Jul 11 06:02:20 PM PDT 24
Finished Jul 11 06:03:25 PM PDT 24
Peak memory 206680 kb
Host smart-34de8964-ecbc-42cd-ba3f-da1db15c1762
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1742231999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1742231999
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.2128417012
Short name T1308
Test name
Test status
Simulation time 12216748390 ps
CPU time 44.08 seconds
Started Jul 11 06:01:57 PM PDT 24
Finished Jul 11 06:02:58 PM PDT 24
Peak memory 206576 kb
Host smart-01015840-6da7-49e5-b473-4fab8b3b0a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21284
17012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.2128417012
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.4099894161
Short name T2083
Test name
Test status
Simulation time 181233260 ps
CPU time 0.85 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206288 kb
Host smart-01724f63-1dcf-48b8-a59d-eafdf29a4cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998
94161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.4099894161
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.9523343
Short name T1089
Test name
Test status
Simulation time 23326340030 ps
CPU time 24.07 seconds
Started Jul 11 06:01:57 PM PDT 24
Finished Jul 11 06:02:37 PM PDT 24
Peak memory 206460 kb
Host smart-6b6b4a33-b2bf-40e8-9001-4d7367889f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95233
43 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.9523343
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3565369889
Short name T382
Test name
Test status
Simulation time 3347554180 ps
CPU time 3.63 seconds
Started Jul 11 06:02:16 PM PDT 24
Finished Jul 11 06:02:38 PM PDT 24
Peak memory 206364 kb
Host smart-d255ecc6-8693-4f99-a71f-eabd49fc18b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35653
69889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3565369889
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.97633739
Short name T887
Test name
Test status
Simulation time 7237210085 ps
CPU time 66.09 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:03:31 PM PDT 24
Peak memory 206704 kb
Host smart-a1f77007-5757-490b-a4f2-854032c1aa9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97633
739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.97633739
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3733571694
Short name T797
Test name
Test status
Simulation time 5705958195 ps
CPU time 42.04 seconds
Started Jul 11 06:02:13 PM PDT 24
Finished Jul 11 06:03:13 PM PDT 24
Peak memory 206628 kb
Host smart-adaf4fd0-94a9-4384-a4e4-33d7aa85198f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3733571694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3733571694
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2344169256
Short name T469
Test name
Test status
Simulation time 258635014 ps
CPU time 0.94 seconds
Started Jul 11 06:02:05 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206380 kb
Host smart-87be7ea6-14f7-49b3-924d-6fb2558693bc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2344169256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2344169256
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3243023443
Short name T2356
Test name
Test status
Simulation time 201973636 ps
CPU time 0.87 seconds
Started Jul 11 06:02:02 PM PDT 24
Finished Jul 11 06:02:20 PM PDT 24
Peak memory 206384 kb
Host smart-ab919abd-b16f-4c4e-927b-5a3e7ea2c59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32430
23443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3243023443
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.473302987
Short name T2085
Test name
Test status
Simulation time 4324170139 ps
CPU time 117.27 seconds
Started Jul 11 06:02:13 PM PDT 24
Finished Jul 11 06:04:29 PM PDT 24
Peak memory 206592 kb
Host smart-d9a3be22-dc05-42d1-b977-f28d3532d774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47330
2987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.473302987
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3387390070
Short name T2408
Test name
Test status
Simulation time 4663102254 ps
CPU time 32.44 seconds
Started Jul 11 06:02:32 PM PDT 24
Finished Jul 11 06:03:22 PM PDT 24
Peak memory 206684 kb
Host smart-368b77fd-9840-4cd9-8a26-73990a96631e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3387390070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3387390070
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2581577987
Short name T1082
Test name
Test status
Simulation time 147945513 ps
CPU time 0.81 seconds
Started Jul 11 06:02:02 PM PDT 24
Finished Jul 11 06:02:20 PM PDT 24
Peak memory 206400 kb
Host smart-c844cfb2-1cb8-418b-b37f-d8ab7482a533
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2581577987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2581577987
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1943722751
Short name T989
Test name
Test status
Simulation time 156944535 ps
CPU time 0.73 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206376 kb
Host smart-38574b70-a9e8-4919-a5be-43d99b906ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19437
22751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1943722751
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.4004255986
Short name T153
Test name
Test status
Simulation time 177196913 ps
CPU time 0.77 seconds
Started Jul 11 06:01:54 PM PDT 24
Finished Jul 11 06:02:11 PM PDT 24
Peak memory 206380 kb
Host smart-688801be-790d-4264-938a-090d6e6e5911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
55986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.4004255986
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1004642535
Short name T1509
Test name
Test status
Simulation time 179877094 ps
CPU time 0.87 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:15 PM PDT 24
Peak memory 206540 kb
Host smart-b1b52717-aa53-49cd-a0c5-8dcc032c86c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10046
42535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1004642535
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.4065996902
Short name T2403
Test name
Test status
Simulation time 191522469 ps
CPU time 0.86 seconds
Started Jul 11 06:02:02 PM PDT 24
Finished Jul 11 06:02:20 PM PDT 24
Peak memory 206312 kb
Host smart-818b8388-6790-4e9a-bb76-117f10ecb75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40659
96902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.4065996902
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1663577799
Short name T443
Test name
Test status
Simulation time 226825778 ps
CPU time 0.87 seconds
Started Jul 11 06:02:18 PM PDT 24
Finished Jul 11 06:02:37 PM PDT 24
Peak memory 206392 kb
Host smart-a326421c-3bf7-4d6e-ab47-45f9f9467935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16635
77799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1663577799
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.198732417
Short name T1145
Test name
Test status
Simulation time 146873154 ps
CPU time 0.77 seconds
Started Jul 11 06:02:10 PM PDT 24
Finished Jul 11 06:02:30 PM PDT 24
Peak memory 206392 kb
Host smart-62763fd0-9aba-4868-a0c7-06d8fa01911c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19873
2417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.198732417
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1847939114
Short name T894
Test name
Test status
Simulation time 205309438 ps
CPU time 0.89 seconds
Started Jul 11 06:02:20 PM PDT 24
Finished Jul 11 06:02:39 PM PDT 24
Peak memory 206384 kb
Host smart-5c8568fa-ba43-4718-89aa-ec2c277f47b1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1847939114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1847939114
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2451170986
Short name T1992
Test name
Test status
Simulation time 157748499 ps
CPU time 0.77 seconds
Started Jul 11 06:02:17 PM PDT 24
Finished Jul 11 06:02:36 PM PDT 24
Peak memory 206364 kb
Host smart-43b6d075-1577-4d27-aecc-ee78836f8736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24511
70986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2451170986
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.545561672
Short name T762
Test name
Test status
Simulation time 55594134 ps
CPU time 0.65 seconds
Started Jul 11 06:02:03 PM PDT 24
Finished Jul 11 06:02:24 PM PDT 24
Peak memory 206368 kb
Host smart-b1d6902c-251d-4217-acbb-9bfd48ca93e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54556
1672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.545561672
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.829407195
Short name T2498
Test name
Test status
Simulation time 9341493465 ps
CPU time 24.32 seconds
Started Jul 11 06:02:13 PM PDT 24
Finished Jul 11 06:02:56 PM PDT 24
Peak memory 206620 kb
Host smart-957eb6b4-9282-4be1-a821-5c3069bf6cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82940
7195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.829407195
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3185988019
Short name T1819
Test name
Test status
Simulation time 161053365 ps
CPU time 0.79 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 206372 kb
Host smart-151eb93c-c78e-43f6-b6c3-d4e0701aca48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31859
88019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3185988019
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3105178341
Short name T2369
Test name
Test status
Simulation time 289600510 ps
CPU time 0.95 seconds
Started Jul 11 06:01:52 PM PDT 24
Finished Jul 11 06:02:09 PM PDT 24
Peak memory 206384 kb
Host smart-ffe62a2a-8dbf-4f1e-9f4b-b869e61e6640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31051
78341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3105178341
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1062845511
Short name T580
Test name
Test status
Simulation time 211191148 ps
CPU time 0.88 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:16 PM PDT 24
Peak memory 206332 kb
Host smart-a5a94728-b2b5-4003-a8bf-cb5a0ba846fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10628
45511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1062845511
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1868038013
Short name T808
Test name
Test status
Simulation time 200023873 ps
CPU time 0.84 seconds
Started Jul 11 06:02:15 PM PDT 24
Finished Jul 11 06:02:35 PM PDT 24
Peak memory 206392 kb
Host smart-c79aba9d-a1b5-43d0-a893-df03ca9de8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18680
38013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1868038013
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.364066134
Short name T369
Test name
Test status
Simulation time 182603562 ps
CPU time 0.82 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:15 PM PDT 24
Peak memory 206540 kb
Host smart-7320cb98-a1cd-4ca8-b841-c4ce629f6945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
6134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.364066134
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3639322459
Short name T365
Test name
Test status
Simulation time 166583068 ps
CPU time 0.83 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:16 PM PDT 24
Peak memory 206492 kb
Host smart-ecf23bac-ee60-4336-95ec-6fef229d7b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36393
22459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3639322459
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3921766532
Short name T1591
Test name
Test status
Simulation time 158852587 ps
CPU time 0.81 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206388 kb
Host smart-bad2605e-5f5e-498f-9359-931a9c0c121e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39217
66532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3921766532
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2686356278
Short name T2556
Test name
Test status
Simulation time 258675672 ps
CPU time 0.97 seconds
Started Jul 11 06:01:58 PM PDT 24
Finished Jul 11 06:02:16 PM PDT 24
Peak memory 206308 kb
Host smart-a97d2ec8-a5e0-42e2-8a35-10690bd06c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
56278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2686356278
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3746131186
Short name T759
Test name
Test status
Simulation time 6244303116 ps
CPU time 56.06 seconds
Started Jul 11 06:02:01 PM PDT 24
Finished Jul 11 06:03:15 PM PDT 24
Peak memory 206620 kb
Host smart-17b86997-4614-4f16-aa62-971288a7d63f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3746131186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3746131186
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2214730995
Short name T2006
Test name
Test status
Simulation time 165933268 ps
CPU time 0.77 seconds
Started Jul 11 06:02:02 PM PDT 24
Finished Jul 11 06:02:20 PM PDT 24
Peak memory 206308 kb
Host smart-1310c36e-e909-48db-86ca-0a06017b7f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22147
30995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2214730995
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3053311735
Short name T1264
Test name
Test status
Simulation time 166686543 ps
CPU time 0.81 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:23 PM PDT 24
Peak memory 206384 kb
Host smart-a2165eef-441a-4331-bf0d-78403e851552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30533
11735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3053311735
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.1913247857
Short name T1277
Test name
Test status
Simulation time 1311971845 ps
CPU time 2.64 seconds
Started Jul 11 06:02:11 PM PDT 24
Finished Jul 11 06:02:32 PM PDT 24
Peak memory 206624 kb
Host smart-a80d6edf-1c59-4986-9f10-f88e4be587e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19132
47857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1913247857
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1194372338
Short name T1933
Test name
Test status
Simulation time 4674176160 ps
CPU time 130.89 seconds
Started Jul 11 06:02:09 PM PDT 24
Finished Jul 11 06:04:38 PM PDT 24
Peak memory 206548 kb
Host smart-15d6d6fb-10cc-4695-816e-84493984cc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11943
72338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1194372338
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3812921292
Short name T2501
Test name
Test status
Simulation time 86250757 ps
CPU time 0.72 seconds
Started Jul 11 06:02:22 PM PDT 24
Finished Jul 11 06:02:40 PM PDT 24
Peak memory 206412 kb
Host smart-f88f0c09-e8cd-4be9-a3a9-788ff1dc15c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3812921292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3812921292
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3915935572
Short name T1860
Test name
Test status
Simulation time 4278215175 ps
CPU time 5.62 seconds
Started Jul 11 06:02:14 PM PDT 24
Finished Jul 11 06:02:39 PM PDT 24
Peak memory 206632 kb
Host smart-b5727e7f-2641-4fb8-8ced-47d1f12eac67
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3915935572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3915935572
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2235980302
Short name T644
Test name
Test status
Simulation time 13369424284 ps
CPU time 16.54 seconds
Started Jul 11 06:02:03 PM PDT 24
Finished Jul 11 06:02:37 PM PDT 24
Peak memory 206396 kb
Host smart-1f972c84-8995-44a0-bf1a-414a7436d4a5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2235980302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2235980302
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.2700505874
Short name T1444
Test name
Test status
Simulation time 23355035786 ps
CPU time 24.67 seconds
Started Jul 11 06:02:12 PM PDT 24
Finished Jul 11 06:02:54 PM PDT 24
Peak memory 206460 kb
Host smart-dee0e52e-4376-4a3e-8ebe-c5698c889160
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2700505874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.2700505874
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3470417403
Short name T1827
Test name
Test status
Simulation time 160208944 ps
CPU time 0.89 seconds
Started Jul 11 06:02:07 PM PDT 24
Finished Jul 11 06:02:26 PM PDT 24
Peak memory 206388 kb
Host smart-b3229d6f-fbea-4a0b-a1df-f37cbe7f06e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
17403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3470417403
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.325585457
Short name T543
Test name
Test status
Simulation time 170333785 ps
CPU time 0.78 seconds
Started Jul 11 06:02:10 PM PDT 24
Finished Jul 11 06:02:30 PM PDT 24
Peak memory 206308 kb
Host smart-1a64d62f-1da7-4f10-b8dd-a50f47585e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32558
5457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.325585457
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1004185730
Short name T2479
Test name
Test status
Simulation time 305424085 ps
CPU time 1.15 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:02:18 PM PDT 24
Peak memory 206372 kb
Host smart-e5dc7f29-f08c-4bc0-97de-9f9258094255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10041
85730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1004185730
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.1317529084
Short name T715
Test name
Test status
Simulation time 1029157330 ps
CPU time 2.45 seconds
Started Jul 11 06:02:20 PM PDT 24
Finished Jul 11 06:02:40 PM PDT 24
Peak memory 206592 kb
Host smart-2ce6d10f-c383-429b-9898-83a069b4f5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13175
29084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.1317529084
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1061027706
Short name T98
Test name
Test status
Simulation time 14184317453 ps
CPU time 25.31 seconds
Started Jul 11 06:02:32 PM PDT 24
Finished Jul 11 06:03:15 PM PDT 24
Peak memory 206660 kb
Host smart-c09f8804-6422-4239-93f7-27d78073afcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10610
27706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1061027706
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.650428115
Short name T945
Test name
Test status
Simulation time 542165653 ps
CPU time 1.47 seconds
Started Jul 11 06:02:06 PM PDT 24
Finished Jul 11 06:02:26 PM PDT 24
Peak memory 206380 kb
Host smart-16386df3-e72d-47a2-8489-c20461b620ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65042
8115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.650428115
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2199025452
Short name T1910
Test name
Test status
Simulation time 138903324 ps
CPU time 0.77 seconds
Started Jul 11 06:02:07 PM PDT 24
Finished Jul 11 06:02:26 PM PDT 24
Peak memory 206368 kb
Host smart-f19f4ae0-a31a-45f4-b866-ea1b10363262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21990
25452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2199025452
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3370490576
Short name T652
Test name
Test status
Simulation time 41917766 ps
CPU time 0.65 seconds
Started Jul 11 06:02:21 PM PDT 24
Finished Jul 11 06:02:39 PM PDT 24
Peak memory 206372 kb
Host smart-b698a816-2591-4f56-81df-32a09c85c799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33704
90576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3370490576
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1583315846
Short name T331
Test name
Test status
Simulation time 990289278 ps
CPU time 2.25 seconds
Started Jul 11 06:02:04 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206544 kb
Host smart-00ee6724-c365-47e5-b427-71404c759ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15833
15846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1583315846
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1740958874
Short name T2342
Test name
Test status
Simulation time 262883365 ps
CPU time 1.82 seconds
Started Jul 11 06:02:13 PM PDT 24
Finished Jul 11 06:02:33 PM PDT 24
Peak memory 206632 kb
Host smart-3a07ae97-d5f7-452e-9844-7473a5f2c395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17409
58874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1740958874
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1182264552
Short name T2559
Test name
Test status
Simulation time 201101184 ps
CPU time 0.91 seconds
Started Jul 11 06:02:15 PM PDT 24
Finished Jul 11 06:02:35 PM PDT 24
Peak memory 206464 kb
Host smart-111d47c2-8911-4826-a9c8-090658f17c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11822
64552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1182264552
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.961509287
Short name T1055
Test name
Test status
Simulation time 147491576 ps
CPU time 0.75 seconds
Started Jul 11 06:02:05 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 206380 kb
Host smart-404ddb0c-ba75-4bd8-8d6b-85cca1d92b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96150
9287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.961509287
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3604419769
Short name T1436
Test name
Test status
Simulation time 211324810 ps
CPU time 0.89 seconds
Started Jul 11 06:02:20 PM PDT 24
Finished Jul 11 06:02:39 PM PDT 24
Peak memory 206376 kb
Host smart-3c71c895-a193-488f-a9d5-aecb5ac6116c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36044
19769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3604419769
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.2549764937
Short name T1006
Test name
Test status
Simulation time 8831577856 ps
CPU time 76.07 seconds
Started Jul 11 06:02:13 PM PDT 24
Finished Jul 11 06:03:47 PM PDT 24
Peak memory 206620 kb
Host smart-c5acfc87-b5fd-4c63-b13a-61b840df9783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25497
64937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.2549764937
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2672437923
Short name T470
Test name
Test status
Simulation time 178835157 ps
CPU time 0.8 seconds
Started Jul 11 06:02:09 PM PDT 24
Finished Jul 11 06:02:28 PM PDT 24
Peak memory 206380 kb
Host smart-8c337a56-0476-42b4-9a42-84cbeae6493b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26724
37923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2672437923
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.4250220110
Short name T1985
Test name
Test status
Simulation time 23348662068 ps
CPU time 22.63 seconds
Started Jul 11 06:02:20 PM PDT 24
Finished Jul 11 06:03:01 PM PDT 24
Peak memory 206416 kb
Host smart-9d220889-125d-44f0-be21-211a1a239057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42502
20110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.4250220110
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1120013400
Short name T1995
Test name
Test status
Simulation time 3303222888 ps
CPU time 4.24 seconds
Started Jul 11 06:02:12 PM PDT 24
Finished Jul 11 06:02:35 PM PDT 24
Peak memory 206452 kb
Host smart-62b00625-8d74-4a20-af10-111c19436678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11200
13400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1120013400
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.4140427326
Short name T435
Test name
Test status
Simulation time 10902615410 ps
CPU time 307.34 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:07:24 PM PDT 24
Peak memory 206644 kb
Host smart-7db32779-1019-4d17-881a-b8c5450215fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404
27326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.4140427326
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.2977984499
Short name T1419
Test name
Test status
Simulation time 5007247055 ps
CPU time 137.95 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:04:36 PM PDT 24
Peak memory 206556 kb
Host smart-b78eec57-6875-4f76-b77a-5d8f7a5c4053
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2977984499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.2977984499
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3526749708
Short name T465
Test name
Test status
Simulation time 239606033 ps
CPU time 1.05 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 206356 kb
Host smart-722c9d8f-3e2e-425e-950f-1b5e3f66ec52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3526749708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3526749708
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1669302830
Short name T975
Test name
Test status
Simulation time 241114293 ps
CPU time 0.85 seconds
Started Jul 11 06:02:24 PM PDT 24
Finished Jul 11 06:02:42 PM PDT 24
Peak memory 206304 kb
Host smart-e5f1145f-1f06-4ad8-9b6d-3687e880e30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16693
02830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1669302830
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.520253184
Short name T1353
Test name
Test status
Simulation time 3969394437 ps
CPU time 114.71 seconds
Started Jul 11 06:02:11 PM PDT 24
Finished Jul 11 06:04:24 PM PDT 24
Peak memory 206664 kb
Host smart-f4484d2a-699c-4b4c-900d-ca51e8d6759d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52025
3184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.520253184
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.759726244
Short name T1882
Test name
Test status
Simulation time 4373282208 ps
CPU time 123.82 seconds
Started Jul 11 06:02:31 PM PDT 24
Finished Jul 11 06:04:52 PM PDT 24
Peak memory 206604 kb
Host smart-23c66bff-3455-408e-a42f-8799ca0ef76c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=759726244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.759726244
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.964544834
Short name T774
Test name
Test status
Simulation time 192959092 ps
CPU time 0.81 seconds
Started Jul 11 06:01:59 PM PDT 24
Finished Jul 11 06:02:18 PM PDT 24
Peak memory 206376 kb
Host smart-fdcf75d4-d760-4863-b30f-89ce24bef40a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=964544834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.964544834
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1398980489
Short name T2614
Test name
Test status
Simulation time 147402466 ps
CPU time 0.77 seconds
Started Jul 11 06:02:00 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 206356 kb
Host smart-d161092c-40dc-422b-b6bb-11168343ce07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13989
80489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1398980489
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1398192388
Short name T134
Test name
Test status
Simulation time 214434149 ps
CPU time 0.84 seconds
Started Jul 11 06:02:05 PM PDT 24
Finished Jul 11 06:02:24 PM PDT 24
Peak memory 206396 kb
Host smart-5f3c9453-837c-4a11-984d-493e7996b49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13981
92388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1398192388
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1042773580
Short name T1146
Test name
Test status
Simulation time 147930855 ps
CPU time 0.78 seconds
Started Jul 11 06:02:20 PM PDT 24
Finished Jul 11 06:02:39 PM PDT 24
Peak memory 206380 kb
Host smart-92fd326c-b1b6-4d45-a84f-c0bb4aa7d858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10427
73580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1042773580
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3412965789
Short name T2587
Test name
Test status
Simulation time 204197028 ps
CPU time 0.83 seconds
Started Jul 11 06:02:03 PM PDT 24
Finished Jul 11 06:02:22 PM PDT 24
Peak memory 206404 kb
Host smart-a8630d47-174c-41a7-b23c-4c8151250c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34129
65789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3412965789
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1017576734
Short name T1152
Test name
Test status
Simulation time 180192396 ps
CPU time 0.8 seconds
Started Jul 11 06:02:20 PM PDT 24
Finished Jul 11 06:02:39 PM PDT 24
Peak memory 206344 kb
Host smart-9a6a952a-4e9a-43e6-b80c-7742416801b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10175
76734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1017576734
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3659690863
Short name T832
Test name
Test status
Simulation time 156561108 ps
CPU time 0.78 seconds
Started Jul 11 06:02:11 PM PDT 24
Finished Jul 11 06:02:30 PM PDT 24
Peak memory 206392 kb
Host smart-3af53f87-7ae7-42ca-908f-f631909f326e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36596
90863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3659690863
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1918473375
Short name T785
Test name
Test status
Simulation time 199158608 ps
CPU time 0.87 seconds
Started Jul 11 06:02:36 PM PDT 24
Finished Jul 11 06:02:54 PM PDT 24
Peak memory 206324 kb
Host smart-96df6121-5a67-49e5-ac2a-397032b72f7b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1918473375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1918473375
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1366318684
Short name T597
Test name
Test status
Simulation time 140942986 ps
CPU time 0.76 seconds
Started Jul 11 06:02:11 PM PDT 24
Finished Jul 11 06:02:30 PM PDT 24
Peak memory 206388 kb
Host smart-d688c269-7b0e-43c4-aa44-53c199d7762a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13663
18684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1366318684
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3614234290
Short name T2703
Test name
Test status
Simulation time 47929672 ps
CPU time 0.66 seconds
Started Jul 11 06:02:22 PM PDT 24
Finished Jul 11 06:02:41 PM PDT 24
Peak memory 206352 kb
Host smart-96e4e22e-6452-445a-94f8-352965d8ddd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36142
34290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3614234290
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1140957930
Short name T1163
Test name
Test status
Simulation time 6951956332 ps
CPU time 15.59 seconds
Started Jul 11 06:02:15 PM PDT 24
Finished Jul 11 06:02:50 PM PDT 24
Peak memory 206728 kb
Host smart-6c740095-bd5d-4bb7-ae13-d4e86cfd48d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11409
57930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1140957930
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.34589876
Short name T1316
Test name
Test status
Simulation time 162778134 ps
CPU time 0.79 seconds
Started Jul 11 06:02:16 PM PDT 24
Finished Jul 11 06:02:35 PM PDT 24
Peak memory 206392 kb
Host smart-e0227981-bd22-41e9-96bc-9118e4835f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34589
876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.34589876
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3775175656
Short name T442
Test name
Test status
Simulation time 251438132 ps
CPU time 0.89 seconds
Started Jul 11 06:02:29 PM PDT 24
Finished Jul 11 06:02:48 PM PDT 24
Peak memory 206388 kb
Host smart-7cc30485-4540-42e3-8d7a-c5bdf1208f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37751
75656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3775175656
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1505850318
Short name T2018
Test name
Test status
Simulation time 205147879 ps
CPU time 0.82 seconds
Started Jul 11 06:02:22 PM PDT 24
Finished Jul 11 06:02:41 PM PDT 24
Peak memory 206396 kb
Host smart-d161f2b2-effe-41c8-a703-0d39709eab9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15058
50318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1505850318
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3668393091
Short name T1279
Test name
Test status
Simulation time 186779582 ps
CPU time 0.84 seconds
Started Jul 11 06:02:52 PM PDT 24
Finished Jul 11 06:03:13 PM PDT 24
Peak memory 206372 kb
Host smart-c2e31d89-52f7-49e7-be82-3c8f9170df47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36683
93091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3668393091
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.522578627
Short name T1565
Test name
Test status
Simulation time 192710442 ps
CPU time 0.84 seconds
Started Jul 11 06:02:13 PM PDT 24
Finished Jul 11 06:02:32 PM PDT 24
Peak memory 206392 kb
Host smart-98c8ddd4-4bd4-44b6-b0e0-fe4f0ad2bf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52257
8627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.522578627
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.183721144
Short name T1290
Test name
Test status
Simulation time 148863998 ps
CPU time 0.73 seconds
Started Jul 11 06:02:16 PM PDT 24
Finished Jul 11 06:02:35 PM PDT 24
Peak memory 206380 kb
Host smart-cdb64a1f-f2bd-4d5d-9cc5-d52aed39f76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18372
1144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.183721144
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3595009362
Short name T941
Test name
Test status
Simulation time 164815837 ps
CPU time 0.81 seconds
Started Jul 11 06:02:23 PM PDT 24
Finished Jul 11 06:02:42 PM PDT 24
Peak memory 206244 kb
Host smart-5452298e-169b-4a01-ace7-9ee79abb685c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
09362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3595009362
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3045146982
Short name T345
Test name
Test status
Simulation time 200225794 ps
CPU time 0.9 seconds
Started Jul 11 06:02:14 PM PDT 24
Finished Jul 11 06:02:34 PM PDT 24
Peak memory 206380 kb
Host smart-55bd21a9-b8e7-4325-bbe0-a81a6a386bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451
46982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3045146982
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.4081523481
Short name T2289
Test name
Test status
Simulation time 4393269005 ps
CPU time 112.19 seconds
Started Jul 11 06:02:23 PM PDT 24
Finished Jul 11 06:04:33 PM PDT 24
Peak memory 206652 kb
Host smart-8671e0dd-2c01-48ce-8b34-3a377de1133f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4081523481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.4081523481
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2140888254
Short name T1592
Test name
Test status
Simulation time 220349851 ps
CPU time 0.82 seconds
Started Jul 11 06:02:12 PM PDT 24
Finished Jul 11 06:02:32 PM PDT 24
Peak memory 206340 kb
Host smart-3cc10ec2-fdff-45c1-b273-1aa3a08d637a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21408
88254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2140888254
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1651938953
Short name T2632
Test name
Test status
Simulation time 206851603 ps
CPU time 0.81 seconds
Started Jul 11 06:02:13 PM PDT 24
Finished Jul 11 06:02:32 PM PDT 24
Peak memory 206384 kb
Host smart-02d10412-e3dd-4b38-a6d1-21eee6979598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16519
38953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1651938953
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1795484450
Short name T2507
Test name
Test status
Simulation time 490615029 ps
CPU time 1.32 seconds
Started Jul 11 06:02:25 PM PDT 24
Finished Jul 11 06:02:45 PM PDT 24
Peak memory 206312 kb
Host smart-406affda-ac4a-4142-acc8-73a646044045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
84450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1795484450
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1307978714
Short name T1259
Test name
Test status
Simulation time 4170073990 ps
CPU time 39.92 seconds
Started Jul 11 06:02:19 PM PDT 24
Finished Jul 11 06:03:17 PM PDT 24
Peak memory 206700 kb
Host smart-41823d5f-2bc2-4f1b-897e-1219fef5c2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13079
78714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1307978714
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3869436316
Short name T2019
Test name
Test status
Simulation time 62902535 ps
CPU time 0.69 seconds
Started Jul 11 05:55:25 PM PDT 24
Finished Jul 11 05:55:29 PM PDT 24
Peak memory 206436 kb
Host smart-9f59b072-db94-4368-8ce7-51ccabf10815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3869436316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3869436316
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1680655474
Short name T2729
Test name
Test status
Simulation time 4036562015 ps
CPU time 4.76 seconds
Started Jul 11 05:55:06 PM PDT 24
Finished Jul 11 05:55:13 PM PDT 24
Peak memory 206712 kb
Host smart-7fe40a87-64e0-42e6-8138-65d0f71e8f5a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1680655474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1680655474
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.1926505761
Short name T1481
Test name
Test status
Simulation time 13303391541 ps
CPU time 11.69 seconds
Started Jul 11 05:55:07 PM PDT 24
Finished Jul 11 05:55:22 PM PDT 24
Peak memory 206624 kb
Host smart-4204c65c-500f-4270-af18-7422ce344bee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1926505761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.1926505761
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.4261834464
Short name T1112
Test name
Test status
Simulation time 23331028646 ps
CPU time 30.33 seconds
Started Jul 11 05:55:07 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 206452 kb
Host smart-6ec70d50-a256-4840-9e78-1b959eca657d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4261834464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.4261834464
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3569403070
Short name T1954
Test name
Test status
Simulation time 173416127 ps
CPU time 0.83 seconds
Started Jul 11 05:55:08 PM PDT 24
Finished Jul 11 05:55:12 PM PDT 24
Peak memory 206364 kb
Host smart-b9642ae6-f53e-4ba2-9a8d-b201475e5cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35694
03070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3569403070
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3402388353
Short name T1158
Test name
Test status
Simulation time 190764853 ps
CPU time 0.86 seconds
Started Jul 11 05:55:08 PM PDT 24
Finished Jul 11 05:55:12 PM PDT 24
Peak memory 206388 kb
Host smart-6fd3e7b5-e42b-4020-8d88-f1b22b9e0b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34023
88353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3402388353
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.2952441870
Short name T31
Test name
Test status
Simulation time 357180525 ps
CPU time 1.16 seconds
Started Jul 11 05:55:07 PM PDT 24
Finished Jul 11 05:55:11 PM PDT 24
Peak memory 206324 kb
Host smart-7d1d149e-cb5a-4918-9f68-ca8385d5e1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29524
41870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.2952441870
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2063957746
Short name T438
Test name
Test status
Simulation time 550662597 ps
CPU time 1.38 seconds
Started Jul 11 05:55:08 PM PDT 24
Finished Jul 11 05:55:12 PM PDT 24
Peak memory 206384 kb
Host smart-d55bb56a-9492-48b8-bee0-4b11cdbcc0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20639
57746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2063957746
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3027729785
Short name T2052
Test name
Test status
Simulation time 21441174077 ps
CPU time 36.75 seconds
Started Jul 11 05:55:05 PM PDT 24
Finished Jul 11 05:55:45 PM PDT 24
Peak memory 206648 kb
Host smart-d82a562d-91b9-4992-a3f0-6800c0a00daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30277
29785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3027729785
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.684702640
Short name T2586
Test name
Test status
Simulation time 460383888 ps
CPU time 1.47 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:55:23 PM PDT 24
Peak memory 206332 kb
Host smart-ef3c6602-be29-4f10-bfbd-9c88d29a1e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68470
2640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.684702640
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.347058969
Short name T48
Test name
Test status
Simulation time 162444937 ps
CPU time 0.79 seconds
Started Jul 11 05:55:20 PM PDT 24
Finished Jul 11 05:55:23 PM PDT 24
Peak memory 206392 kb
Host smart-5eb31c1d-a762-4900-9538-014901f6c192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34705
8969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.347058969
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2342913604
Short name T242
Test name
Test status
Simulation time 38506817 ps
CPU time 0.67 seconds
Started Jul 11 05:55:20 PM PDT 24
Finished Jul 11 05:55:25 PM PDT 24
Peak memory 206396 kb
Host smart-288e15a0-34c7-4fdb-8006-522ac50efb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23429
13604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2342913604
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1707052822
Short name T1372
Test name
Test status
Simulation time 805612312 ps
CPU time 2.01 seconds
Started Jul 11 05:55:18 PM PDT 24
Finished Jul 11 05:55:23 PM PDT 24
Peak memory 206464 kb
Host smart-c1686a2b-8619-4d9c-a3bf-ccd05eaa81a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17070
52822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1707052822
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2071884060
Short name T2665
Test name
Test status
Simulation time 227339651 ps
CPU time 1.86 seconds
Started Jul 11 05:55:15 PM PDT 24
Finished Jul 11 05:55:18 PM PDT 24
Peak memory 206580 kb
Host smart-18003607-a20c-4a3b-98e0-1552c2f84317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20718
84060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2071884060
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.787134863
Short name T1583
Test name
Test status
Simulation time 155917251 ps
CPU time 0.78 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 206396 kb
Host smart-5ee820cd-038b-403b-9057-fad287e70d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78713
4863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.787134863
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3403710772
Short name T2487
Test name
Test status
Simulation time 176932844 ps
CPU time 0.77 seconds
Started Jul 11 05:55:18 PM PDT 24
Finished Jul 11 05:55:21 PM PDT 24
Peak memory 206364 kb
Host smart-ee093c89-eb97-49a1-8991-bb1d39b8e026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34037
10772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3403710772
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3252062315
Short name T1670
Test name
Test status
Simulation time 195465037 ps
CPU time 0.86 seconds
Started Jul 11 05:55:20 PM PDT 24
Finished Jul 11 05:55:23 PM PDT 24
Peak memory 206368 kb
Host smart-845ce776-0398-44bf-9990-481c9492963e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520
62315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3252062315
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.2719426038
Short name T2004
Test name
Test status
Simulation time 7119435447 ps
CPU time 67.57 seconds
Started Jul 11 05:55:17 PM PDT 24
Finished Jul 11 05:56:26 PM PDT 24
Peak memory 206604 kb
Host smart-9f058db0-ea24-4e37-aed1-dd62c42a2444
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2719426038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.2719426038
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1447423601
Short name T1381
Test name
Test status
Simulation time 10715122772 ps
CPU time 86.21 seconds
Started Jul 11 05:55:20 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 206696 kb
Host smart-dea09f08-2778-4c7c-ae0c-04e30b123423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14474
23601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1447423601
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2492913449
Short name T825
Test name
Test status
Simulation time 203311358 ps
CPU time 0.81 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:55:22 PM PDT 24
Peak memory 206292 kb
Host smart-ab35328f-0edc-422f-bcf8-a1e3b965a6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24929
13449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2492913449
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2986206557
Short name T1473
Test name
Test status
Simulation time 23356787690 ps
CPU time 22.19 seconds
Started Jul 11 05:55:22 PM PDT 24
Finished Jul 11 05:55:49 PM PDT 24
Peak memory 206404 kb
Host smart-a2dab3ae-561b-4a64-8e64-1d620b80f964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29862
06557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2986206557
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1031134088
Short name T520
Test name
Test status
Simulation time 3278585926 ps
CPU time 4.54 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:55:30 PM PDT 24
Peak memory 206444 kb
Host smart-5303df53-2a58-4536-9cd2-9737a94f2ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10311
34088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1031134088
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.514316689
Short name T973
Test name
Test status
Simulation time 8948983138 ps
CPU time 61.68 seconds
Started Jul 11 05:56:01 PM PDT 24
Finished Jul 11 05:57:06 PM PDT 24
Peak memory 206704 kb
Host smart-0d5d4706-53a0-49ca-895b-39792ddd8345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51431
6689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.514316689
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1692467832
Short name T2417
Test name
Test status
Simulation time 7109982787 ps
CPU time 68.92 seconds
Started Jul 11 05:55:17 PM PDT 24
Finished Jul 11 05:56:27 PM PDT 24
Peak memory 206632 kb
Host smart-c737bb7f-00dc-4d27-9c57-00ac2c300f0b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1692467832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1692467832
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1373029623
Short name T733
Test name
Test status
Simulation time 297993634 ps
CPU time 0.95 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 206364 kb
Host smart-4f8fcda2-b9c6-4da5-9e6d-9202e8bc0cb5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1373029623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1373029623
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1078839705
Short name T2304
Test name
Test status
Simulation time 214709510 ps
CPU time 0.85 seconds
Started Jul 11 05:55:17 PM PDT 24
Finished Jul 11 05:55:19 PM PDT 24
Peak memory 206392 kb
Host smart-16ebe95f-b01c-490e-8efb-5c443a4e73c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10788
39705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1078839705
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3419963023
Short name T1067
Test name
Test status
Simulation time 4606503709 ps
CPU time 42.83 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:56:10 PM PDT 24
Peak memory 206576 kb
Host smart-7f8ff42c-622f-48ce-8d99-4502a4b6d5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34199
63023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3419963023
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2288680382
Short name T1296
Test name
Test status
Simulation time 3396745250 ps
CPU time 94.41 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:56:56 PM PDT 24
Peak memory 206632 kb
Host smart-955ce7c7-0bb5-4ebc-875a-985c3f5114db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2288680382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2288680382
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2509711745
Short name T918
Test name
Test status
Simulation time 156946207 ps
CPU time 0.85 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 206380 kb
Host smart-f75733b3-1a80-4205-a51e-71021f6fb7e6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2509711745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2509711745
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.4038927713
Short name T2695
Test name
Test status
Simulation time 147064042 ps
CPU time 0.77 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:55:22 PM PDT 24
Peak memory 206332 kb
Host smart-91c56976-7a8f-4f93-8022-2a108833161b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40389
27713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.4038927713
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2465567228
Short name T144
Test name
Test status
Simulation time 175915641 ps
CPU time 0.8 seconds
Started Jul 11 05:55:20 PM PDT 24
Finished Jul 11 05:55:24 PM PDT 24
Peak memory 206384 kb
Host smart-fde0d0b9-1a87-4c63-ba17-014c8c2804c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24655
67228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2465567228
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3519763457
Short name T504
Test name
Test status
Simulation time 199397481 ps
CPU time 0.84 seconds
Started Jul 11 05:55:18 PM PDT 24
Finished Jul 11 05:55:21 PM PDT 24
Peak memory 206388 kb
Host smart-c4f6e5d6-0f53-4a8d-8678-25c97dcc221e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197
63457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3519763457
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1811746584
Short name T674
Test name
Test status
Simulation time 164508012 ps
CPU time 0.84 seconds
Started Jul 11 05:55:27 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 206272 kb
Host smart-52ee6493-7ab0-446b-ac31-6fe9d0d0f18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18117
46584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1811746584
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3946332825
Short name T698
Test name
Test status
Simulation time 169480124 ps
CPU time 0.89 seconds
Started Jul 11 05:55:23 PM PDT 24
Finished Jul 11 05:55:28 PM PDT 24
Peak memory 206352 kb
Host smart-947f9b1c-57fb-44f4-8380-b95dfa6ee30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39463
32825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3946332825
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3103981497
Short name T190
Test name
Test status
Simulation time 147684591 ps
CPU time 0.75 seconds
Started Jul 11 05:55:22 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 206392 kb
Host smart-36ae4672-2283-4b49-a936-4abea51164f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31039
81497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3103981497
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1842612506
Short name T2035
Test name
Test status
Simulation time 213121699 ps
CPU time 0.9 seconds
Started Jul 11 05:55:18 PM PDT 24
Finished Jul 11 05:55:21 PM PDT 24
Peak memory 206396 kb
Host smart-a51f9e84-548c-4546-9573-ba267be6a54b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1842612506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1842612506
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1099813592
Short name T202
Test name
Test status
Simulation time 152753572 ps
CPU time 0.8 seconds
Started Jul 11 05:55:45 PM PDT 24
Finished Jul 11 05:55:50 PM PDT 24
Peak memory 206388 kb
Host smart-fcc58d26-a1be-445b-913a-10209df88b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10998
13592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1099813592
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2976721007
Short name T1814
Test name
Test status
Simulation time 40224861 ps
CPU time 0.65 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 206296 kb
Host smart-f3cb537b-9a10-420a-ab6f-41d397343164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
21007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2976721007
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3189063340
Short name T261
Test name
Test status
Simulation time 10770088616 ps
CPU time 23.25 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:55:44 PM PDT 24
Peak memory 206752 kb
Host smart-d2e73b5f-e48a-41f2-8a41-a09f51e31d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31890
63340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3189063340
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3165120419
Short name T969
Test name
Test status
Simulation time 158815650 ps
CPU time 0.83 seconds
Started Jul 11 05:55:27 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 206268 kb
Host smart-fb575929-2d25-4d3a-a1cb-b6aa54523216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31651
20419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3165120419
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1618749129
Short name T1149
Test name
Test status
Simulation time 191300415 ps
CPU time 0.85 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:55:29 PM PDT 24
Peak memory 206380 kb
Host smart-d795b1ca-fb86-41fc-9cae-b2256261c632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16187
49129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1618749129
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.270857823
Short name T1212
Test name
Test status
Simulation time 4999961689 ps
CPU time 118.98 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 206704 kb
Host smart-09b0bd16-8e08-4d56-8a78-58c5d760af90
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=270857823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.270857823
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3912773381
Short name T183
Test name
Test status
Simulation time 8487118087 ps
CPU time 129.68 seconds
Started Jul 11 05:55:18 PM PDT 24
Finished Jul 11 05:57:30 PM PDT 24
Peak memory 206708 kb
Host smart-8ce00d4e-2546-44fe-af3b-fe355e0a76cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3912773381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3912773381
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1298758521
Short name T2424
Test name
Test status
Simulation time 8109315492 ps
CPU time 41.58 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:56:07 PM PDT 24
Peak memory 206680 kb
Host smart-e97a673e-a9ee-4b52-b883-3b4a4bca2e9c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1298758521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1298758521
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2205236997
Short name T2371
Test name
Test status
Simulation time 170353594 ps
CPU time 0.81 seconds
Started Jul 11 05:55:20 PM PDT 24
Finished Jul 11 05:55:23 PM PDT 24
Peak memory 206388 kb
Host smart-3af94efc-9eae-4b64-9bd7-c4c49bbb1e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
36997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2205236997
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1258914119
Short name T86
Test name
Test status
Simulation time 195847797 ps
CPU time 0.89 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:55:22 PM PDT 24
Peak memory 206388 kb
Host smart-34b4c69d-0ab2-421e-8977-4d5fb7e1d621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12589
14119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1258914119
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3366727930
Short name T1854
Test name
Test status
Simulation time 240227807 ps
CPU time 0.93 seconds
Started Jul 11 05:55:22 PM PDT 24
Finished Jul 11 05:55:28 PM PDT 24
Peak memory 206392 kb
Host smart-a8861a58-aebb-47dd-b32b-9ecd288ed245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33667
27930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3366727930
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1068805923
Short name T1032
Test name
Test status
Simulation time 157532459 ps
CPU time 0.79 seconds
Started Jul 11 05:55:20 PM PDT 24
Finished Jul 11 05:55:24 PM PDT 24
Peak memory 206372 kb
Host smart-efecd3cf-20f8-4636-95a1-e51d5bdc9f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
05923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1068805923
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.464849572
Short name T1949
Test name
Test status
Simulation time 163003157 ps
CPU time 0.76 seconds
Started Jul 11 05:55:17 PM PDT 24
Finished Jul 11 05:55:20 PM PDT 24
Peak memory 206372 kb
Host smart-50030c14-ffea-483f-b46d-f68ded793459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46484
9572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.464849572
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1977459024
Short name T1777
Test name
Test status
Simulation time 261447793 ps
CPU time 0.92 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:55:22 PM PDT 24
Peak memory 206324 kb
Host smart-6d0b090c-5861-4b8f-aa26-787d288a2efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19774
59024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1977459024
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.340580135
Short name T833
Test name
Test status
Simulation time 3899975454 ps
CPU time 27.38 seconds
Started Jul 11 05:55:17 PM PDT 24
Finished Jul 11 05:55:46 PM PDT 24
Peak memory 206640 kb
Host smart-8ae4760c-0ce7-4bcc-bc9a-e7b7d1523ce8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=340580135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.340580135
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3629885431
Short name T602
Test name
Test status
Simulation time 191821544 ps
CPU time 0.84 seconds
Started Jul 11 05:55:23 PM PDT 24
Finished Jul 11 05:55:28 PM PDT 24
Peak memory 206396 kb
Host smart-c8d55999-dc1f-4762-b50a-ec98d69064ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36298
85431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3629885431
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2915575919
Short name T2263
Test name
Test status
Simulation time 187577818 ps
CPU time 0.82 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 206372 kb
Host smart-dd265c11-f5fa-403e-8426-9705eae3cd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29155
75919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2915575919
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.4194852766
Short name T407
Test name
Test status
Simulation time 696178512 ps
CPU time 1.89 seconds
Started Jul 11 05:55:19 PM PDT 24
Finished Jul 11 05:55:23 PM PDT 24
Peak memory 206632 kb
Host smart-f9bddbd5-d969-43e0-86e8-0c2b00d0f3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41948
52766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.4194852766
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3904551187
Short name T2283
Test name
Test status
Simulation time 6779573272 ps
CPU time 186.26 seconds
Started Jul 11 05:55:34 PM PDT 24
Finished Jul 11 05:58:43 PM PDT 24
Peak memory 206564 kb
Host smart-c506f8d6-a1fd-458e-b1e9-5862c8d2c907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39045
51187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3904551187
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1239078459
Short name T1497
Test name
Test status
Simulation time 41636459 ps
CPU time 0.64 seconds
Started Jul 11 05:55:33 PM PDT 24
Finished Jul 11 05:55:36 PM PDT 24
Peak memory 206424 kb
Host smart-7eb4b91d-2958-4967-996c-3423ab321f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1239078459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1239078459
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3655471946
Short name T2020
Test name
Test status
Simulation time 3673652412 ps
CPU time 4.35 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:55:30 PM PDT 24
Peak memory 206424 kb
Host smart-48029d75-c9d3-4707-ad44-ce0cf29d9b9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3655471946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3655471946
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.4208052794
Short name T717
Test name
Test status
Simulation time 13380293382 ps
CPU time 13.39 seconds
Started Jul 11 05:55:26 PM PDT 24
Finished Jul 11 05:55:42 PM PDT 24
Peak memory 206420 kb
Host smart-b24c435e-3ef6-4065-b9cc-8288b08720f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4208052794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.4208052794
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.4051945973
Short name T2442
Test name
Test status
Simulation time 23386498210 ps
CPU time 23.25 seconds
Started Jul 11 05:55:22 PM PDT 24
Finished Jul 11 05:55:50 PM PDT 24
Peak memory 206488 kb
Host smart-4a1484db-03b7-45d6-8597-9341150d402a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4051945973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.4051945973
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3693401278
Short name T405
Test name
Test status
Simulation time 166359524 ps
CPU time 0.81 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:55:25 PM PDT 24
Peak memory 206384 kb
Host smart-1b0c65a9-c828-4526-9a22-d932bb4287e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36934
01278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3693401278
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3732545150
Short name T877
Test name
Test status
Simulation time 153556738 ps
CPU time 0.75 seconds
Started Jul 11 05:55:26 PM PDT 24
Finished Jul 11 05:55:30 PM PDT 24
Peak memory 206320 kb
Host smart-9c8ac491-a541-4bd2-a6d6-39f765ecbadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
45150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3732545150
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.590814359
Short name T1222
Test name
Test status
Simulation time 435480623 ps
CPU time 1.34 seconds
Started Jul 11 05:55:21 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 206392 kb
Host smart-42ecfbdc-a9eb-41de-8e91-79a181c40696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59081
4359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.590814359
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3699373598
Short name T2266
Test name
Test status
Simulation time 1394002616 ps
CPU time 2.97 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:55:30 PM PDT 24
Peak memory 206632 kb
Host smart-4c4f8dc6-5212-42db-9729-d56a8fb59230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
73598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3699373598
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.4013945181
Short name T1401
Test name
Test status
Simulation time 6200660139 ps
CPU time 10.97 seconds
Started Jul 11 05:55:23 PM PDT 24
Finished Jul 11 05:55:38 PM PDT 24
Peak memory 206720 kb
Host smart-f330061d-33ef-45cc-a738-bcaecc945b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40139
45181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.4013945181
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.4053958552
Short name T358
Test name
Test status
Simulation time 403452576 ps
CPU time 1.22 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 05:55:33 PM PDT 24
Peak memory 206400 kb
Host smart-5e1022db-e84f-43fa-89ce-f562ac54ec3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40539
58552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.4053958552
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1896453131
Short name T1924
Test name
Test status
Simulation time 179931199 ps
CPU time 0.85 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:55:29 PM PDT 24
Peak memory 206352 kb
Host smart-196dc663-1479-4205-a7d8-ef59b3f2d348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18964
53131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1896453131
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2596119180
Short name T1059
Test name
Test status
Simulation time 35544716 ps
CPU time 0.66 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:55:29 PM PDT 24
Peak memory 206340 kb
Host smart-c29cbdc0-ba39-4036-8c78-598b63553ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25961
19180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2596119180
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.4151280280
Short name T1563
Test name
Test status
Simulation time 931791493 ps
CPU time 2.11 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:55:30 PM PDT 24
Peak memory 206656 kb
Host smart-d9df065a-9b4d-4c19-b159-0dcb22f02514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41512
80280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.4151280280
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2371972274
Short name T2366
Test name
Test status
Simulation time 365425703 ps
CPU time 2.08 seconds
Started Jul 11 05:55:22 PM PDT 24
Finished Jul 11 05:55:28 PM PDT 24
Peak memory 206628 kb
Host smart-4f7bfadc-232b-4e93-bdff-6218ae01e4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23719
72274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2371972274
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3408667797
Short name T1414
Test name
Test status
Simulation time 235174566 ps
CPU time 0.87 seconds
Started Jul 11 05:55:34 PM PDT 24
Finished Jul 11 05:55:37 PM PDT 24
Peak memory 206312 kb
Host smart-6268f837-03ef-4de6-9b9e-b4ad78263041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34086
67797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3408667797
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.567567173
Short name T1258
Test name
Test status
Simulation time 144543212 ps
CPU time 0.76 seconds
Started Jul 11 05:55:31 PM PDT 24
Finished Jul 11 05:55:35 PM PDT 24
Peak memory 206352 kb
Host smart-ad4e06b1-6985-4cb5-a6c6-51e343519dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56756
7173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.567567173
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1262391261
Short name T375
Test name
Test status
Simulation time 201112026 ps
CPU time 0.84 seconds
Started Jul 11 05:55:29 PM PDT 24
Finished Jul 11 05:55:34 PM PDT 24
Peak memory 206344 kb
Host smart-f99b2bc4-5f59-4d08-991b-0bdd6e195033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
91261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1262391261
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.2143850933
Short name T1957
Test name
Test status
Simulation time 5929235308 ps
CPU time 46.83 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:56:15 PM PDT 24
Peak memory 206624 kb
Host smart-7aa37fa1-27bf-4aac-8b86-e960dd60179c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21438
50933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.2143850933
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2086344389
Short name T1701
Test name
Test status
Simulation time 177692284 ps
CPU time 0.81 seconds
Started Jul 11 05:55:22 PM PDT 24
Finished Jul 11 05:55:27 PM PDT 24
Peak memory 206384 kb
Host smart-cbc8aef2-e79e-4d5c-84b5-cb8173a36203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20863
44389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2086344389
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1389994795
Short name T610
Test name
Test status
Simulation time 23353183043 ps
CPU time 23.14 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:55:52 PM PDT 24
Peak memory 206428 kb
Host smart-99a05422-e21f-4291-821b-74c4cfd994c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13899
94795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1389994795
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3105320333
Short name T1884
Test name
Test status
Simulation time 3265977698 ps
CPU time 4.01 seconds
Started Jul 11 05:55:34 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 206376 kb
Host smart-8eb8b0ab-897d-4693-a30f-5833520762bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31053
20333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3105320333
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.4174832712
Short name T97
Test name
Test status
Simulation time 11661455220 ps
CPU time 323.87 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 06:00:56 PM PDT 24
Peak memory 206664 kb
Host smart-c37b4daf-d9af-45e1-991b-0c12563a40de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
32712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.4174832712
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.90733987
Short name T2506
Test name
Test status
Simulation time 5598429695 ps
CPU time 50.61 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 05:56:23 PM PDT 24
Peak memory 206664 kb
Host smart-18504feb-27e3-453f-8bcc-11ad797400e8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=90733987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.90733987
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.789960561
Short name T1578
Test name
Test status
Simulation time 233966620 ps
CPU time 0.9 seconds
Started Jul 11 05:55:35 PM PDT 24
Finished Jul 11 05:55:39 PM PDT 24
Peak memory 206308 kb
Host smart-11a16d7e-49df-4894-9a37-1af09bdfe83b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=789960561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.789960561
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.609371545
Short name T452
Test name
Test status
Simulation time 195535868 ps
CPU time 0.88 seconds
Started Jul 11 05:55:35 PM PDT 24
Finished Jul 11 05:55:38 PM PDT 24
Peak memory 206316 kb
Host smart-45bc82c9-3fea-4490-868f-986716cf1d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60937
1545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.609371545
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.1702479867
Short name T742
Test name
Test status
Simulation time 4839450823 ps
CPU time 43.54 seconds
Started Jul 11 05:55:35 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206596 kb
Host smart-0b316bbb-e397-4dd0-9f82-abd705994372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17024
79867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.1702479867
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.440697881
Short name T1654
Test name
Test status
Simulation time 6006901969 ps
CPU time 166.8 seconds
Started Jul 11 05:55:23 PM PDT 24
Finished Jul 11 05:58:14 PM PDT 24
Peak memory 206640 kb
Host smart-1b35fda5-20e9-4748-9a8b-365585c566ce
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=440697881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.440697881
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2033885039
Short name T2742
Test name
Test status
Simulation time 148244195 ps
CPU time 0.79 seconds
Started Jul 11 05:55:24 PM PDT 24
Finished Jul 11 05:55:28 PM PDT 24
Peak memory 206404 kb
Host smart-79309fcf-7760-4620-a92f-fada69ace51c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2033885039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2033885039
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3146760324
Short name T897
Test name
Test status
Simulation time 143907565 ps
CPU time 0.74 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 206348 kb
Host smart-0167c31d-6bfa-4bd9-ac9b-9d76fc9a37ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31467
60324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3146760324
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.789935254
Short name T131
Test name
Test status
Simulation time 205324676 ps
CPU time 0.83 seconds
Started Jul 11 05:55:32 PM PDT 24
Finished Jul 11 05:55:35 PM PDT 24
Peak memory 206356 kb
Host smart-bd61af17-a81d-49c1-8c7d-30a59c271a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78993
5254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.789935254
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.817528653
Short name T2439
Test name
Test status
Simulation time 158680968 ps
CPU time 0.77 seconds
Started Jul 11 05:55:32 PM PDT 24
Finished Jul 11 05:55:35 PM PDT 24
Peak memory 206352 kb
Host smart-4e8b46ca-24cd-4f5d-bee7-23a02b7c3405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81752
8653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.817528653
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3179934921
Short name T2201
Test name
Test status
Simulation time 195958797 ps
CPU time 0.86 seconds
Started Jul 11 05:55:30 PM PDT 24
Finished Jul 11 05:55:35 PM PDT 24
Peak memory 206352 kb
Host smart-514c9629-6cc5-4365-b331-d09ef7b2d063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31799
34921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3179934921
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3714327863
Short name T1217
Test name
Test status
Simulation time 188772932 ps
CPU time 0.84 seconds
Started Jul 11 05:55:43 PM PDT 24
Finished Jul 11 05:55:48 PM PDT 24
Peak memory 206328 kb
Host smart-fa84d4b2-e9cc-4dbd-9371-117860913a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37143
27863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3714327863
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.925320660
Short name T2216
Test name
Test status
Simulation time 188764445 ps
CPU time 0.77 seconds
Started Jul 11 05:55:33 PM PDT 24
Finished Jul 11 05:55:36 PM PDT 24
Peak memory 206308 kb
Host smart-5bbd51ba-05d8-486e-89ff-b586fdddffae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92532
0660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.925320660
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.147778610
Short name T1099
Test name
Test status
Simulation time 286988924 ps
CPU time 0.95 seconds
Started Jul 11 05:55:42 PM PDT 24
Finished Jul 11 05:55:48 PM PDT 24
Peak memory 206336 kb
Host smart-d691b5b6-2a08-4c86-a0cb-0b31c6c06614
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=147778610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.147778610
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.4159288985
Short name T1213
Test name
Test status
Simulation time 150773054 ps
CPU time 0.73 seconds
Started Jul 11 05:55:27 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 206332 kb
Host smart-794826de-e270-4868-83ab-4f8f1923ea6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41592
88985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.4159288985
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4201171251
Short name T1733
Test name
Test status
Simulation time 42802161 ps
CPU time 0.69 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 206300 kb
Host smart-c01ce19e-48fb-40db-a70b-faec7cf8db56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42011
71251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4201171251
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1343986952
Short name T1844
Test name
Test status
Simulation time 17765504907 ps
CPU time 37.12 seconds
Started Jul 11 05:55:30 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 214876 kb
Host smart-9099a330-d584-4ffc-acb0-56d130bde62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13439
86952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1343986952
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2565275939
Short name T2402
Test name
Test status
Simulation time 228101104 ps
CPU time 0.85 seconds
Started Jul 11 05:55:27 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 206396 kb
Host smart-514a2b0b-031b-4dbd-99ed-e611bee7edb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25652
75939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2565275939
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.669142282
Short name T2206
Test name
Test status
Simulation time 236267673 ps
CPU time 0.87 seconds
Started Jul 11 05:55:33 PM PDT 24
Finished Jul 11 05:55:37 PM PDT 24
Peak memory 206364 kb
Host smart-f2214355-ee52-4381-b550-27b7ef94b074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66914
2282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.669142282
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1965718262
Short name T1130
Test name
Test status
Simulation time 15384817646 ps
CPU time 396.34 seconds
Started Jul 11 05:55:30 PM PDT 24
Finished Jul 11 06:02:10 PM PDT 24
Peak memory 206608 kb
Host smart-2f52c2d6-2d31-4a88-99cd-e472fdbed500
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1965718262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1965718262
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.1803778167
Short name T187
Test name
Test status
Simulation time 12793777170 ps
CPU time 68.14 seconds
Started Jul 11 05:55:30 PM PDT 24
Finished Jul 11 05:56:42 PM PDT 24
Peak memory 206684 kb
Host smart-c32232a5-9932-45dc-9bd4-2f33b4c00b60
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1803778167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.1803778167
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2199724056
Short name T2433
Test name
Test status
Simulation time 7829358361 ps
CPU time 35.18 seconds
Started Jul 11 05:55:30 PM PDT 24
Finished Jul 11 05:56:09 PM PDT 24
Peak memory 206644 kb
Host smart-18b29bf9-43f0-448d-ba76-4f65eeff38b2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2199724056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2199724056
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2870256701
Short name T1875
Test name
Test status
Simulation time 244621827 ps
CPU time 0.97 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 206408 kb
Host smart-a43eec83-ad2c-4bc1-9011-f0ebc48dbff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28702
56701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2870256701
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2631896745
Short name T2314
Test name
Test status
Simulation time 154628694 ps
CPU time 0.77 seconds
Started Jul 11 05:55:30 PM PDT 24
Finished Jul 11 05:55:34 PM PDT 24
Peak memory 206372 kb
Host smart-2b7c2559-2633-4b75-a71b-26066a41983e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26318
96745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2631896745
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2696376058
Short name T1606
Test name
Test status
Simulation time 209792104 ps
CPU time 0.8 seconds
Started Jul 11 05:55:27 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 206264 kb
Host smart-388f212a-9956-4d18-bce2-d976b887280d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26963
76058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2696376058
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3882640065
Short name T1619
Test name
Test status
Simulation time 153177030 ps
CPU time 0.73 seconds
Started Jul 11 05:55:37 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 206396 kb
Host smart-3a74e52f-3eb5-4234-8b86-bf3b805bfa2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38826
40065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3882640065
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1175382215
Short name T1853
Test name
Test status
Simulation time 166474344 ps
CPU time 0.78 seconds
Started Jul 11 05:55:41 PM PDT 24
Finished Jul 11 05:55:46 PM PDT 24
Peak memory 206328 kb
Host smart-69d8013d-8307-49fb-bbba-0e5c1a49d49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11753
82215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1175382215
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1524633277
Short name T1405
Test name
Test status
Simulation time 249454505 ps
CPU time 0.94 seconds
Started Jul 11 05:55:27 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 206328 kb
Host smart-83c2027e-739e-4aef-b541-a66c81c2c939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15246
33277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1524633277
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3697380223
Short name T2419
Test name
Test status
Simulation time 3652608723 ps
CPU time 99.97 seconds
Started Jul 11 05:55:34 PM PDT 24
Finished Jul 11 05:57:16 PM PDT 24
Peak memory 206524 kb
Host smart-7e6d0d04-f023-4944-aada-8a3925437546
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3697380223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3697380223
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.4131629646
Short name T1358
Test name
Test status
Simulation time 179136399 ps
CPU time 0.82 seconds
Started Jul 11 05:55:26 PM PDT 24
Finished Jul 11 05:55:30 PM PDT 24
Peak memory 206392 kb
Host smart-1151cfa7-9799-4659-8853-6db379d807aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41316
29646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.4131629646
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.4143162476
Short name T1835
Test name
Test status
Simulation time 190369408 ps
CPU time 0.87 seconds
Started Jul 11 05:55:27 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 206360 kb
Host smart-7d7b3c54-1a5e-4973-9348-29f542e2bff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41431
62476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.4143162476
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.309009879
Short name T2615
Test name
Test status
Simulation time 204011091 ps
CPU time 0.91 seconds
Started Jul 11 05:55:34 PM PDT 24
Finished Jul 11 05:55:37 PM PDT 24
Peak memory 206388 kb
Host smart-156e976a-15b6-4576-a65a-dd33886d4085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
9879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.309009879
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2503048460
Short name T1507
Test name
Test status
Simulation time 6806506563 ps
CPU time 48.48 seconds
Started Jul 11 05:55:33 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206720 kb
Host smart-39033bbd-115e-4a7b-b259-74e068915178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25030
48460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2503048460
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.702137676
Short name T1019
Test name
Test status
Simulation time 72114362 ps
CPU time 0.73 seconds
Started Jul 11 05:56:00 PM PDT 24
Finished Jul 11 05:56:03 PM PDT 24
Peak memory 206424 kb
Host smart-ec98141f-3e20-41f8-90b7-a88fe5c1a407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=702137676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.702137676
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2354007506
Short name T2488
Test name
Test status
Simulation time 4287405236 ps
CPU time 4.71 seconds
Started Jul 11 05:55:34 PM PDT 24
Finished Jul 11 05:55:41 PM PDT 24
Peak memory 206428 kb
Host smart-353fdc9b-c5dd-4ce2-a269-8c79a6d899ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2354007506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2354007506
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3876967212
Short name T1114
Test name
Test status
Simulation time 13336246500 ps
CPU time 15.75 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 05:55:48 PM PDT 24
Peak memory 206624 kb
Host smart-19cadcad-558b-4a0c-923f-d6fb93085691
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3876967212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3876967212
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2054577991
Short name T1867
Test name
Test status
Simulation time 23400807531 ps
CPU time 25.04 seconds
Started Jul 11 05:55:32 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 206392 kb
Host smart-ba6a6338-9389-4d0b-a67d-1f9ba12495d8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2054577991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2054577991
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2317870162
Short name T18
Test name
Test status
Simulation time 195565631 ps
CPU time 0.86 seconds
Started Jul 11 05:55:28 PM PDT 24
Finished Jul 11 05:55:33 PM PDT 24
Peak memory 206308 kb
Host smart-332f1477-3661-4cd1-a9eb-bacfbfe5fda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23178
70162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2317870162
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3370348307
Short name T1865
Test name
Test status
Simulation time 153156752 ps
CPU time 0.75 seconds
Started Jul 11 05:55:30 PM PDT 24
Finished Jul 11 05:55:34 PM PDT 24
Peak memory 206404 kb
Host smart-8ad6d05d-bba1-439f-8e22-6bbe757dbef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
48307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3370348307
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.693634757
Short name T2588
Test name
Test status
Simulation time 320164175 ps
CPU time 1.15 seconds
Started Jul 11 05:55:36 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 206396 kb
Host smart-b266e928-2f74-43a7-9b34-a61433a00f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69363
4757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.693634757
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2310302934
Short name T34
Test name
Test status
Simulation time 306526335 ps
CPU time 0.96 seconds
Started Jul 11 05:55:36 PM PDT 24
Finished Jul 11 05:55:41 PM PDT 24
Peak memory 206328 kb
Host smart-676517d3-a934-405a-8ef4-3e70f381ed82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23103
02934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2310302934
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2750869232
Short name T1359
Test name
Test status
Simulation time 21666858409 ps
CPU time 39.05 seconds
Started Jul 11 05:55:38 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206664 kb
Host smart-c3380785-7c6e-4c00-8075-98333764a9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27508
69232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2750869232
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3229116947
Short name T227
Test name
Test status
Simulation time 433211843 ps
CPU time 1.34 seconds
Started Jul 11 05:55:38 PM PDT 24
Finished Jul 11 05:55:43 PM PDT 24
Peak memory 206368 kb
Host smart-463b4a1e-2804-4bb8-a57c-85464b5f0004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32291
16947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3229116947
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3537788102
Short name T2421
Test name
Test status
Simulation time 167972628 ps
CPU time 0.78 seconds
Started Jul 11 05:55:37 PM PDT 24
Finished Jul 11 05:55:41 PM PDT 24
Peak memory 206388 kb
Host smart-fc206ee3-73ed-4ba0-880f-40f46ae9387f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377
88102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3537788102
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2131587422
Short name T962
Test name
Test status
Simulation time 44436083 ps
CPU time 0.67 seconds
Started Jul 11 05:55:35 PM PDT 24
Finished Jul 11 05:55:38 PM PDT 24
Peak memory 206384 kb
Host smart-034ff8ec-3ad9-4f42-a444-14a987658793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21315
87422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2131587422
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3149280254
Short name T1404
Test name
Test status
Simulation time 780909954 ps
CPU time 1.9 seconds
Started Jul 11 05:55:34 PM PDT 24
Finished Jul 11 05:55:39 PM PDT 24
Peak memory 206588 kb
Host smart-902f886d-ef0a-4b2f-af87-0fcb8816dd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31492
80254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3149280254
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3950707751
Short name T950
Test name
Test status
Simulation time 183502968 ps
CPU time 1.96 seconds
Started Jul 11 05:55:46 PM PDT 24
Finished Jul 11 05:55:53 PM PDT 24
Peak memory 206524 kb
Host smart-399d0f67-fa19-4bf0-b8f6-c6da3181e114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39507
07751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3950707751
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3689914060
Short name T740
Test name
Test status
Simulation time 202403561 ps
CPU time 0.8 seconds
Started Jul 11 05:55:46 PM PDT 24
Finished Jul 11 05:55:51 PM PDT 24
Peak memory 206328 kb
Host smart-de18af35-e914-4dbd-acef-5430b32f0c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36899
14060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3689914060
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.4231432720
Short name T790
Test name
Test status
Simulation time 138934748 ps
CPU time 0.78 seconds
Started Jul 11 05:55:41 PM PDT 24
Finished Jul 11 05:55:47 PM PDT 24
Peak memory 206376 kb
Host smart-6fa1b7a2-15ec-4570-a556-474e89f48875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42314
32720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.4231432720
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1243181887
Short name T2572
Test name
Test status
Simulation time 173416918 ps
CPU time 0.84 seconds
Started Jul 11 05:55:36 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 206388 kb
Host smart-f9e4f345-4fe8-4f4c-8efd-e27988fabe16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12431
81887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1243181887
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.3183382563
Short name T1580
Test name
Test status
Simulation time 5474301196 ps
CPU time 20.07 seconds
Started Jul 11 05:55:39 PM PDT 24
Finished Jul 11 05:56:03 PM PDT 24
Peak memory 206660 kb
Host smart-c744f308-486e-4e7d-aab7-1b473255f622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31833
82563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.3183382563
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3227194728
Short name T1561
Test name
Test status
Simulation time 250558129 ps
CPU time 0.85 seconds
Started Jul 11 05:55:39 PM PDT 24
Finished Jul 11 05:55:44 PM PDT 24
Peak memory 206292 kb
Host smart-e929bb67-7f2e-48e9-b0d0-04a7b6036197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32271
94728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3227194728
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3788313629
Short name T1241
Test name
Test status
Simulation time 23298441195 ps
CPU time 21.12 seconds
Started Jul 11 05:55:39 PM PDT 24
Finished Jul 11 05:56:04 PM PDT 24
Peak memory 206356 kb
Host smart-6b398913-0f7f-4495-93c0-08a644916cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37883
13629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3788313629
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1357210177
Short name T2429
Test name
Test status
Simulation time 3299004075 ps
CPU time 3.5 seconds
Started Jul 11 05:55:37 PM PDT 24
Finished Jul 11 05:55:43 PM PDT 24
Peak memory 206452 kb
Host smart-249ce2c8-d99a-4065-a1dd-f1ea23710c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
10177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1357210177
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1084014960
Short name T839
Test name
Test status
Simulation time 7457338089 ps
CPU time 200.73 seconds
Started Jul 11 05:55:46 PM PDT 24
Finished Jul 11 05:59:11 PM PDT 24
Peak memory 206652 kb
Host smart-a5d259da-c533-4d19-a415-473242d44cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10840
14960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1084014960
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3168924419
Short name T2418
Test name
Test status
Simulation time 6522901253 ps
CPU time 190.46 seconds
Started Jul 11 05:55:38 PM PDT 24
Finished Jul 11 05:58:52 PM PDT 24
Peak memory 206628 kb
Host smart-7e15c43a-8b0b-4eae-9136-5bc110300454
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3168924419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3168924419
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2354866053
Short name T411
Test name
Test status
Simulation time 250814467 ps
CPU time 0.96 seconds
Started Jul 11 05:55:39 PM PDT 24
Finished Jul 11 05:55:45 PM PDT 24
Peak memory 206288 kb
Host smart-d6aec560-8024-43aa-b46f-1981b05809cb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2354866053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2354866053
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2801422651
Short name T1267
Test name
Test status
Simulation time 182438201 ps
CPU time 0.85 seconds
Started Jul 11 05:55:46 PM PDT 24
Finished Jul 11 05:55:52 PM PDT 24
Peak memory 206332 kb
Host smart-8ed35df1-e2dc-4522-a2ba-40a65629f06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28014
22651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2801422651
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3184953314
Short name T2140
Test name
Test status
Simulation time 6463947323 ps
CPU time 183.53 seconds
Started Jul 11 05:55:36 PM PDT 24
Finished Jul 11 05:58:42 PM PDT 24
Peak memory 206640 kb
Host smart-a942e95b-e9ef-4439-86bd-08865120d963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31849
53314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3184953314
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1649146064
Short name T1636
Test name
Test status
Simulation time 8039696382 ps
CPU time 56.49 seconds
Started Jul 11 05:55:36 PM PDT 24
Finished Jul 11 05:56:35 PM PDT 24
Peak memory 206744 kb
Host smart-1ddd400a-26c4-43cc-a690-d6ebf146666a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1649146064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1649146064
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.4185660377
Short name T2618
Test name
Test status
Simulation time 170316325 ps
CPU time 0.84 seconds
Started Jul 11 05:55:35 PM PDT 24
Finished Jul 11 05:55:38 PM PDT 24
Peak memory 206328 kb
Host smart-e1abc491-f815-4136-908e-d55581be3365
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4185660377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.4185660377
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1655354873
Short name T479
Test name
Test status
Simulation time 145286197 ps
CPU time 0.79 seconds
Started Jul 11 05:55:37 PM PDT 24
Finished Jul 11 05:55:42 PM PDT 24
Peak memory 206404 kb
Host smart-075eeffd-9e0a-499c-a9aa-6033afd95b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16553
54873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1655354873
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2687684972
Short name T146
Test name
Test status
Simulation time 175250162 ps
CPU time 0.87 seconds
Started Jul 11 05:55:39 PM PDT 24
Finished Jul 11 05:55:44 PM PDT 24
Peak memory 206352 kb
Host smart-daf2b6f8-fcf7-4cc7-bbb9-d4639d9aa217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26876
84972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2687684972
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1987755118
Short name T1119
Test name
Test status
Simulation time 180105800 ps
CPU time 0.8 seconds
Started Jul 11 05:55:39 PM PDT 24
Finished Jul 11 05:55:44 PM PDT 24
Peak memory 206400 kb
Host smart-692a9d58-e544-41e3-819d-624be3e76636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19877
55118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1987755118
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2009508640
Short name T1387
Test name
Test status
Simulation time 187433298 ps
CPU time 0.82 seconds
Started Jul 11 05:55:37 PM PDT 24
Finished Jul 11 05:55:41 PM PDT 24
Peak memory 206376 kb
Host smart-fd98ed89-7877-4d36-adfa-100120ec90a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20095
08640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2009508640
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2906807282
Short name T867
Test name
Test status
Simulation time 156341010 ps
CPU time 0.75 seconds
Started Jul 11 05:55:39 PM PDT 24
Finished Jul 11 05:55:43 PM PDT 24
Peak memory 206296 kb
Host smart-d0fb5ea1-bca5-4df7-829b-5c1966885118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
07282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2906807282
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3849681744
Short name T2722
Test name
Test status
Simulation time 174742708 ps
CPU time 0.78 seconds
Started Jul 11 05:55:45 PM PDT 24
Finished Jul 11 05:55:51 PM PDT 24
Peak memory 206332 kb
Host smart-135f328a-a13e-412a-83a5-117e13161168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38496
81744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3849681744
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.344425623
Short name T2144
Test name
Test status
Simulation time 227273708 ps
CPU time 0.91 seconds
Started Jul 11 05:55:37 PM PDT 24
Finished Jul 11 05:55:42 PM PDT 24
Peak memory 206388 kb
Host smart-78686469-6fac-4a80-9b9b-6ece98a12048
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=344425623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.344425623
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2616965643
Short name T2101
Test name
Test status
Simulation time 149013498 ps
CPU time 0.8 seconds
Started Jul 11 05:55:35 PM PDT 24
Finished Jul 11 05:55:38 PM PDT 24
Peak memory 206368 kb
Host smart-7cb3c071-f406-4884-9385-e54eab3a2520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26169
65643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2616965643
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.4284616263
Short name T27
Test name
Test status
Simulation time 44968912 ps
CPU time 0.66 seconds
Started Jul 11 05:55:46 PM PDT 24
Finished Jul 11 05:55:51 PM PDT 24
Peak memory 206324 kb
Host smart-5ad49b5d-fe54-41c8-b010-6aecf6f20ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42846
16263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.4284616263
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.111748820
Short name T255
Test name
Test status
Simulation time 15764970674 ps
CPU time 37.75 seconds
Started Jul 11 05:55:38 PM PDT 24
Finished Jul 11 05:56:20 PM PDT 24
Peak memory 206736 kb
Host smart-d14a155f-9ec7-441c-a813-96fbe70e687c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11174
8820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.111748820
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2670529800
Short name T544
Test name
Test status
Simulation time 180083921 ps
CPU time 0.86 seconds
Started Jul 11 05:55:37 PM PDT 24
Finished Jul 11 05:55:42 PM PDT 24
Peak memory 206356 kb
Host smart-c14ea1bc-085f-47fe-b29b-780789e490a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26705
29800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2670529800
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4177978243
Short name T1294
Test name
Test status
Simulation time 240525659 ps
CPU time 0.91 seconds
Started Jul 11 05:55:44 PM PDT 24
Finished Jul 11 05:55:49 PM PDT 24
Peak memory 206280 kb
Host smart-4b7d76ff-c7b8-401a-98b6-53d3fbc16fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41779
78243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4177978243
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2675774393
Short name T987
Test name
Test status
Simulation time 11558698668 ps
CPU time 220.37 seconds
Started Jul 11 05:55:44 PM PDT 24
Finished Jul 11 05:59:29 PM PDT 24
Peak memory 206652 kb
Host smart-a7ed9fa9-1697-459a-ab3c-560764e6b5c7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2675774393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2675774393
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.369288730
Short name T181
Test name
Test status
Simulation time 7732199768 ps
CPU time 191.2 seconds
Started Jul 11 05:55:42 PM PDT 24
Finished Jul 11 05:58:58 PM PDT 24
Peak memory 206696 kb
Host smart-be878a24-7998-4de5-a47b-cba18494b992
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=369288730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.369288730
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2554446167
Short name T45
Test name
Test status
Simulation time 12057363042 ps
CPU time 75.79 seconds
Started Jul 11 05:55:44 PM PDT 24
Finished Jul 11 05:57:04 PM PDT 24
Peak memory 206680 kb
Host smart-a7df51e1-f677-4cf6-b5f5-1d4d472824dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2554446167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2554446167
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1623121432
Short name T2381
Test name
Test status
Simulation time 252507640 ps
CPU time 0.91 seconds
Started Jul 11 05:55:43 PM PDT 24
Finished Jul 11 05:55:49 PM PDT 24
Peak memory 206396 kb
Host smart-514a99db-09a2-4831-83aa-865ffc338879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16231
21432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1623121432
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3638220670
Short name T1271
Test name
Test status
Simulation time 236337773 ps
CPU time 0.88 seconds
Started Jul 11 05:55:44 PM PDT 24
Finished Jul 11 05:55:49 PM PDT 24
Peak memory 206304 kb
Host smart-5a0c4f32-9da4-46fe-8710-27b7691d5eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36382
20670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3638220670
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.482345657
Short name T2023
Test name
Test status
Simulation time 193084908 ps
CPU time 0.82 seconds
Started Jul 11 05:55:45 PM PDT 24
Finished Jul 11 05:55:50 PM PDT 24
Peak memory 206352 kb
Host smart-c7e0ebad-3bf0-46c2-99e1-7097832ea4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48234
5657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.482345657
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3168924506
Short name T2668
Test name
Test status
Simulation time 180825199 ps
CPU time 0.8 seconds
Started Jul 11 05:55:44 PM PDT 24
Finished Jul 11 05:55:49 PM PDT 24
Peak memory 206372 kb
Host smart-c67f4f89-e6e7-4484-b162-1ab5300ddd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
24506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3168924506
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1877035120
Short name T2379
Test name
Test status
Simulation time 160368606 ps
CPU time 0.76 seconds
Started Jul 11 05:55:40 PM PDT 24
Finished Jul 11 05:55:45 PM PDT 24
Peak memory 206396 kb
Host smart-03aaef75-6e95-4439-8562-9b1266257dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18770
35120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1877035120
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.224298007
Short name T1355
Test name
Test status
Simulation time 252117953 ps
CPU time 0.94 seconds
Started Jul 11 05:55:44 PM PDT 24
Finished Jul 11 05:55:49 PM PDT 24
Peak memory 206312 kb
Host smart-c288d6e3-f9e8-43c0-85a2-6b2aaf663dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22429
8007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.224298007
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2200584245
Short name T621
Test name
Test status
Simulation time 5799799919 ps
CPU time 43.3 seconds
Started Jul 11 05:55:51 PM PDT 24
Finished Jul 11 05:56:38 PM PDT 24
Peak memory 206608 kb
Host smart-e765cd7c-2550-428a-a1a1-64e63fbdd97c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2200584245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2200584245
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1047952428
Short name T600
Test name
Test status
Simulation time 155576663 ps
CPU time 0.77 seconds
Started Jul 11 05:55:43 PM PDT 24
Finished Jul 11 05:55:48 PM PDT 24
Peak memory 206392 kb
Host smart-8c503875-5e1b-467e-babe-b0f3ef24c9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10479
52428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1047952428
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.630329997
Short name T371
Test name
Test status
Simulation time 158977219 ps
CPU time 0.77 seconds
Started Jul 11 05:55:47 PM PDT 24
Finished Jul 11 05:55:53 PM PDT 24
Peak memory 206396 kb
Host smart-62ed71c4-9d6e-4a90-8997-1b3855fcd498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63032
9997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.630329997
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2028273154
Short name T1905
Test name
Test status
Simulation time 1305063375 ps
CPU time 2.5 seconds
Started Jul 11 05:55:56 PM PDT 24
Finished Jul 11 05:56:01 PM PDT 24
Peak memory 206624 kb
Host smart-d2fe676d-274c-4af7-8284-00d25cd67ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20282
73154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2028273154
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3213416452
Short name T2500
Test name
Test status
Simulation time 4833296884 ps
CPU time 33.19 seconds
Started Jul 11 05:55:45 PM PDT 24
Finished Jul 11 05:56:23 PM PDT 24
Peak memory 206696 kb
Host smart-44aa7ce8-7c21-40b4-8ce8-baa4398f0c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32134
16452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3213416452
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1391985653
Short name T2561
Test name
Test status
Simulation time 66507157 ps
CPU time 0.68 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 206424 kb
Host smart-0703d602-a641-43fb-90b1-b4d41bddb9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1391985653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1391985653
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2926061003
Short name T2520
Test name
Test status
Simulation time 3831252790 ps
CPU time 4.36 seconds
Started Jul 11 05:55:52 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 206344 kb
Host smart-7bdaf02e-0e28-423f-a503-1a0d1b30696c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2926061003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.2926061003
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2041181274
Short name T664
Test name
Test status
Simulation time 13380408719 ps
CPU time 14.75 seconds
Started Jul 11 05:55:52 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 206564 kb
Host smart-d3230e3f-e5c8-4829-bc63-4caf58d06bd5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2041181274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2041181274
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.733948156
Short name T14
Test name
Test status
Simulation time 23322649421 ps
CPU time 20.81 seconds
Started Jul 11 05:55:52 PM PDT 24
Finished Jul 11 05:56:17 PM PDT 24
Peak memory 206708 kb
Host smart-cc7231ec-9bbe-4a34-ad5d-baf61f8e76f1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=733948156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.733948156
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3217562929
Short name T966
Test name
Test status
Simulation time 183153486 ps
CPU time 0.84 seconds
Started Jul 11 05:55:50 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 206304 kb
Host smart-3e108772-5f89-4127-9855-a88fe89f9019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32175
62929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3217562929
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2318618029
Short name T811
Test name
Test status
Simulation time 151522933 ps
CPU time 0.75 seconds
Started Jul 11 05:55:51 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 206384 kb
Host smart-831b8a7a-7201-4a86-bc9f-f04799dfbac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
18029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2318618029
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3184649505
Short name T418
Test name
Test status
Simulation time 208963636 ps
CPU time 0.86 seconds
Started Jul 11 05:55:52 PM PDT 24
Finished Jul 11 05:55:57 PM PDT 24
Peak memory 206396 kb
Host smart-590a7f54-d228-4028-8c99-817c890505c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31846
49505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3184649505
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.4261098954
Short name T494
Test name
Test status
Simulation time 960840588 ps
CPU time 2.4 seconds
Started Jul 11 05:55:49 PM PDT 24
Finished Jul 11 05:55:56 PM PDT 24
Peak memory 206620 kb
Host smart-49b352f1-c1d0-4198-a501-6888e9592086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42610
98954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.4261098954
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.4256725777
Short name T1352
Test name
Test status
Simulation time 12286806933 ps
CPU time 23.68 seconds
Started Jul 11 05:55:53 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206608 kb
Host smart-c378eb8f-5008-4e61-adc0-c7a8bb2df764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42567
25777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.4256725777
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1699739102
Short name T681
Test name
Test status
Simulation time 388514158 ps
CPU time 1.34 seconds
Started Jul 11 05:55:50 PM PDT 24
Finished Jul 11 05:55:56 PM PDT 24
Peak memory 206380 kb
Host smart-fce069b2-4e7b-4f01-8196-f7953bd3e142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16997
39102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1699739102
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2064896594
Short name T1846
Test name
Test status
Simulation time 136561988 ps
CPU time 0.77 seconds
Started Jul 11 05:55:55 PM PDT 24
Finished Jul 11 05:55:59 PM PDT 24
Peak memory 206364 kb
Host smart-a5f44cce-92c9-4f8f-94de-94fe30451b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
96594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2064896594
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3707043722
Short name T2243
Test name
Test status
Simulation time 39223030 ps
CPU time 0.67 seconds
Started Jul 11 05:55:52 PM PDT 24
Finished Jul 11 05:55:56 PM PDT 24
Peak memory 206416 kb
Host smart-31d7e396-fbb9-461d-8e85-3c1b8af35498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37070
43722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3707043722
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1312648381
Short name T2262
Test name
Test status
Simulation time 925033232 ps
CPU time 2.15 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 206664 kb
Host smart-2f1cf8b5-abbd-473d-9f5b-9acf11ffb85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13126
48381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1312648381
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2258720708
Short name T566
Test name
Test status
Simulation time 188488548 ps
CPU time 2.08 seconds
Started Jul 11 05:55:52 PM PDT 24
Finished Jul 11 05:55:58 PM PDT 24
Peak memory 206532 kb
Host smart-e4743714-3007-4ed7-90ec-bf0aae0d474e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22587
20708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2258720708
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.588748252
Short name T1015
Test name
Test status
Simulation time 158668745 ps
CPU time 0.78 seconds
Started Jul 11 05:55:52 PM PDT 24
Finished Jul 11 05:55:57 PM PDT 24
Peak memory 206372 kb
Host smart-94c05200-e199-496d-97d5-e9e9fcf52b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58874
8252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.588748252
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.448937293
Short name T1115
Test name
Test status
Simulation time 177886416 ps
CPU time 0.83 seconds
Started Jul 11 05:55:48 PM PDT 24
Finished Jul 11 05:55:54 PM PDT 24
Peak memory 206396 kb
Host smart-e5cacf2c-4cba-478a-8e10-d6a8e914a524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44893
7293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.448937293
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3620000543
Short name T928
Test name
Test status
Simulation time 287484094 ps
CPU time 0.97 seconds
Started Jul 11 05:55:51 PM PDT 24
Finished Jul 11 05:55:56 PM PDT 24
Peak memory 206388 kb
Host smart-a48ee348-0a0a-41ec-ab25-48552160322b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36200
00543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3620000543
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.95696092
Short name T121
Test name
Test status
Simulation time 7833436603 ps
CPU time 67.89 seconds
Started Jul 11 05:55:50 PM PDT 24
Finished Jul 11 05:57:02 PM PDT 24
Peak memory 206568 kb
Host smart-3f2020f4-c7c9-49fb-8b1f-2907722c1974
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=95696092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.95696092
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3096707704
Short name T1393
Test name
Test status
Simulation time 188613809 ps
CPU time 0.85 seconds
Started Jul 11 05:55:52 PM PDT 24
Finished Jul 11 05:55:56 PM PDT 24
Peak memory 206376 kb
Host smart-f34cbdb5-5228-433e-b599-f26f02cd6e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30967
07704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3096707704
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2938373224
Short name T1727
Test name
Test status
Simulation time 23362397977 ps
CPU time 24.78 seconds
Started Jul 11 05:55:55 PM PDT 24
Finished Jul 11 05:56:23 PM PDT 24
Peak memory 206428 kb
Host smart-b18dfe47-278a-4dcc-9580-d2131f0f10ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29383
73224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2938373224
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.559755599
Short name T770
Test name
Test status
Simulation time 3340284463 ps
CPU time 4.11 seconds
Started Jul 11 05:55:53 PM PDT 24
Finished Jul 11 05:56:01 PM PDT 24
Peak memory 206392 kb
Host smart-c729a378-601e-4a19-9aa7-f97a6e42fa01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55975
5599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.559755599
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.738588370
Short name T1155
Test name
Test status
Simulation time 10564427620 ps
CPU time 103.51 seconds
Started Jul 11 05:55:54 PM PDT 24
Finished Jul 11 05:57:41 PM PDT 24
Peak memory 206732 kb
Host smart-e67284bb-daf5-459d-ba86-11839000081b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73858
8370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.738588370
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.95749196
Short name T363
Test name
Test status
Simulation time 6710058550 ps
CPU time 63.23 seconds
Started Jul 11 05:55:54 PM PDT 24
Finished Jul 11 05:57:01 PM PDT 24
Peak memory 206712 kb
Host smart-ef4d91cc-d034-4b98-ad38-7f94598061d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=95749196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.95749196
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3680463800
Short name T1809
Test name
Test status
Simulation time 251743996 ps
CPU time 0.98 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 206388 kb
Host smart-9f42ac59-d8bb-43d3-838b-9bf9cc548df4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3680463800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3680463800
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2393196805
Short name T25
Test name
Test status
Simulation time 192211719 ps
CPU time 0.87 seconds
Started Jul 11 05:55:53 PM PDT 24
Finished Jul 11 05:55:57 PM PDT 24
Peak memory 206388 kb
Host smart-759b08ae-fcd7-4d2b-9194-d29b4abb4f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23931
96805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2393196805
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3483427477
Short name T1887
Test name
Test status
Simulation time 5277567726 ps
CPU time 37.9 seconds
Started Jul 11 05:55:58 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 206660 kb
Host smart-e8c6d7ac-9038-432e-bdc5-08a165331175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34834
27477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3483427477
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3827719076
Short name T2580
Test name
Test status
Simulation time 5327226332 ps
CPU time 40.15 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:45 PM PDT 24
Peak memory 206704 kb
Host smart-34ffff68-d304-459e-b33c-df746a089502
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3827719076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3827719076
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.583013124
Short name T370
Test name
Test status
Simulation time 205578706 ps
CPU time 0.82 seconds
Started Jul 11 05:55:58 PM PDT 24
Finished Jul 11 05:56:01 PM PDT 24
Peak memory 206388 kb
Host smart-b3602d99-90b5-4ad5-8f15-8c2dccc8b589
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=583013124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.583013124
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2158049142
Short name T2253
Test name
Test status
Simulation time 166125657 ps
CPU time 0.81 seconds
Started Jul 11 05:55:59 PM PDT 24
Finished Jul 11 05:56:02 PM PDT 24
Peak memory 206540 kb
Host smart-566ef690-3cf8-4da8-bebe-a010d0fcd1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21580
49142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2158049142
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.315922498
Short name T1640
Test name
Test status
Simulation time 219386668 ps
CPU time 0.95 seconds
Started Jul 11 05:55:57 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 206384 kb
Host smart-052a7fda-8962-4bc4-90c9-c24a65ad70ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31592
2498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.315922498
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4123985629
Short name T2348
Test name
Test status
Simulation time 202147651 ps
CPU time 0.86 seconds
Started Jul 11 05:55:57 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 205184 kb
Host smart-9089b9e2-6a92-4660-bb1e-cac0e67e238f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41239
85629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4123985629
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2476467908
Short name T1573
Test name
Test status
Simulation time 235294093 ps
CPU time 0.86 seconds
Started Jul 11 05:56:00 PM PDT 24
Finished Jul 11 05:56:04 PM PDT 24
Peak memory 206312 kb
Host smart-88d9287f-a1b5-4a8b-b907-0983e3b89dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24764
67908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2476467908
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1054801049
Short name T1600
Test name
Test status
Simulation time 154763739 ps
CPU time 0.79 seconds
Started Jul 11 05:55:57 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 206384 kb
Host smart-72ecfd3f-4913-479e-afd4-915c0bc1380a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548
01049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1054801049
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3387937618
Short name T191
Test name
Test status
Simulation time 150275440 ps
CPU time 0.76 seconds
Started Jul 11 05:55:56 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 206408 kb
Host smart-e8729a15-4c46-4d82-bcbf-f5df0b995286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33879
37618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3387937618
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3128366911
Short name T586
Test name
Test status
Simulation time 285110376 ps
CPU time 1.11 seconds
Started Jul 11 05:55:59 PM PDT 24
Finished Jul 11 05:56:03 PM PDT 24
Peak memory 206332 kb
Host smart-4d4aeb95-6c7c-4714-849f-6dc898898675
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3128366911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3128366911
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2979782642
Short name T2183
Test name
Test status
Simulation time 147306537 ps
CPU time 0.76 seconds
Started Jul 11 05:55:57 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 206380 kb
Host smart-3ca7526e-a147-4e4b-b0f3-91aea780dfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29797
82642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2979782642
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3575377648
Short name T963
Test name
Test status
Simulation time 44875765 ps
CPU time 0.67 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 206304 kb
Host smart-dccd9dee-a652-4211-896f-5e006d1d6795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
77648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3575377648
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3638828758
Short name T1477
Test name
Test status
Simulation time 9880895890 ps
CPU time 22.05 seconds
Started Jul 11 05:56:00 PM PDT 24
Finished Jul 11 05:56:25 PM PDT 24
Peak memory 206732 kb
Host smart-ad18c1b4-0cc7-4325-a847-5bc10ab778d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388
28758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3638828758
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2649396712
Short name T2383
Test name
Test status
Simulation time 167713602 ps
CPU time 0.94 seconds
Started Jul 11 05:55:58 PM PDT 24
Finished Jul 11 05:56:02 PM PDT 24
Peak memory 206384 kb
Host smart-8f2551e5-cd20-4a3d-af12-9d3232ee433d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26493
96712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2649396712
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.969076964
Short name T2092
Test name
Test status
Simulation time 215774792 ps
CPU time 0.89 seconds
Started Jul 11 05:55:56 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 206360 kb
Host smart-c8bd5bb0-dbf4-47c5-a766-e867914f8d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96907
6964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.969076964
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2152291238
Short name T2347
Test name
Test status
Simulation time 14960538393 ps
CPU time 77.66 seconds
Started Jul 11 05:55:58 PM PDT 24
Finished Jul 11 05:57:18 PM PDT 24
Peak memory 206736 kb
Host smart-532a4f23-d1eb-4d25-948f-cf87343cb6c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2152291238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2152291238
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.4013588000
Short name T2692
Test name
Test status
Simulation time 13832105120 ps
CPU time 130.58 seconds
Started Jul 11 05:55:56 PM PDT 24
Finished Jul 11 05:58:10 PM PDT 24
Peak memory 206656 kb
Host smart-16e243c1-ecbf-4d66-81a7-6544937410e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4013588000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.4013588000
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1826133914
Short name T736
Test name
Test status
Simulation time 23496933476 ps
CPU time 180.54 seconds
Started Jul 11 05:55:59 PM PDT 24
Finished Jul 11 05:59:02 PM PDT 24
Peak memory 206616 kb
Host smart-593c4eb6-6e4a-45f4-9ca5-8db67a100488
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1826133914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1826133914
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2627105447
Short name T1141
Test name
Test status
Simulation time 279138506 ps
CPU time 0.94 seconds
Started Jul 11 05:56:00 PM PDT 24
Finished Jul 11 05:56:03 PM PDT 24
Peak memory 206536 kb
Host smart-84ffea7e-8788-4172-8a19-7952f718e169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26271
05447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2627105447
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3273632537
Short name T2474
Test name
Test status
Simulation time 158873189 ps
CPU time 0.78 seconds
Started Jul 11 05:56:00 PM PDT 24
Finished Jul 11 05:56:03 PM PDT 24
Peak memory 206304 kb
Host smart-b9236516-b41e-4264-bdc2-cfaf7ab35c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32736
32537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3273632537
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2618335208
Short name T2656
Test name
Test status
Simulation time 179324198 ps
CPU time 0.77 seconds
Started Jul 11 05:55:58 PM PDT 24
Finished Jul 11 05:56:01 PM PDT 24
Peak memory 206348 kb
Host smart-644315c5-3e62-484b-8d67-67641149e62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26183
35208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2618335208
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1957569473
Short name T2298
Test name
Test status
Simulation time 141758529 ps
CPU time 0.75 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 206288 kb
Host smart-91b4e2cf-3743-425c-ab87-3cb28042bf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19575
69473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1957569473
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.419973365
Short name T2390
Test name
Test status
Simulation time 161522447 ps
CPU time 0.84 seconds
Started Jul 11 05:56:01 PM PDT 24
Finished Jul 11 05:56:05 PM PDT 24
Peak memory 206540 kb
Host smart-8d369727-b0d4-44de-832c-5f0c7fc009f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41997
3365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.419973365
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2130443262
Short name T2166
Test name
Test status
Simulation time 266064726 ps
CPU time 0.95 seconds
Started Jul 11 05:55:59 PM PDT 24
Finished Jul 11 05:56:03 PM PDT 24
Peak memory 206540 kb
Host smart-01d9c2fc-4a28-4df9-bd59-cf9c7d96abda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304
43262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2130443262
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.906421492
Short name T2291
Test name
Test status
Simulation time 3529197231 ps
CPU time 26.03 seconds
Started Jul 11 05:55:57 PM PDT 24
Finished Jul 11 05:56:26 PM PDT 24
Peak memory 205432 kb
Host smart-4fc5a016-24ce-4891-8ea9-5260b780d9bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=906421492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.906421492
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.985076052
Short name T761
Test name
Test status
Simulation time 189278876 ps
CPU time 0.82 seconds
Started Jul 11 05:56:05 PM PDT 24
Finished Jul 11 05:56:08 PM PDT 24
Peak memory 206400 kb
Host smart-0e28cbd9-54b7-484b-80b6-21b2f431cd7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98507
6052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.985076052
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1013736754
Short name T886
Test name
Test status
Simulation time 154540167 ps
CPU time 0.74 seconds
Started Jul 11 05:56:06 PM PDT 24
Finished Jul 11 05:56:09 PM PDT 24
Peak memory 206368 kb
Host smart-c2e98c41-8495-45ee-a013-426bbc7f07af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10137
36754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1013736754
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2869479186
Short name T2464
Test name
Test status
Simulation time 911713839 ps
CPU time 1.93 seconds
Started Jul 11 05:56:03 PM PDT 24
Finished Jul 11 05:56:08 PM PDT 24
Peak memory 206636 kb
Host smart-8899fc04-aeca-44f5-bbb4-feb6d273702a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28694
79186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2869479186
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3723331768
Short name T1468
Test name
Test status
Simulation time 4779312660 ps
CPU time 133.73 seconds
Started Jul 11 05:56:11 PM PDT 24
Finished Jul 11 05:58:28 PM PDT 24
Peak memory 206616 kb
Host smart-45ab374c-ea19-43cd-8828-81442e678322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37233
31768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3723331768
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.331669682
Short name T458
Test name
Test status
Simulation time 90384699 ps
CPU time 0.7 seconds
Started Jul 11 05:56:10 PM PDT 24
Finished Jul 11 05:56:14 PM PDT 24
Peak memory 206412 kb
Host smart-87ad7f25-011c-4958-8907-c6b73580b982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=331669682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.331669682
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2505028644
Short name T1033
Test name
Test status
Simulation time 3912985071 ps
CPU time 4.73 seconds
Started Jul 11 05:56:06 PM PDT 24
Finished Jul 11 05:56:14 PM PDT 24
Peak memory 206412 kb
Host smart-0cbdb951-4d21-42d8-8755-4a19ad8428c1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2505028644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2505028644
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1495460801
Short name T603
Test name
Test status
Simulation time 13372150226 ps
CPU time 12.52 seconds
Started Jul 11 05:56:06 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206416 kb
Host smart-61b511a2-e255-40d7-8d96-4f1c2e882645
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1495460801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1495460801
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3607708693
Short name T853
Test name
Test status
Simulation time 23570069316 ps
CPU time 27.9 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:33 PM PDT 24
Peak memory 206632 kb
Host smart-a32e48d3-ecd8-4a17-a4c3-def74bbaa348
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3607708693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.3607708693
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3253926251
Short name T1107
Test name
Test status
Simulation time 201733600 ps
CPU time 0.85 seconds
Started Jul 11 05:56:09 PM PDT 24
Finished Jul 11 05:56:13 PM PDT 24
Peak memory 206380 kb
Host smart-cbf9520c-403f-4422-a1c7-4d43105a3cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32539
26251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3253926251
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3638898208
Short name T447
Test name
Test status
Simulation time 175911874 ps
CPU time 0.8 seconds
Started Jul 11 05:56:04 PM PDT 24
Finished Jul 11 05:56:08 PM PDT 24
Peak memory 206324 kb
Host smart-2d0761df-a153-483e-8a4f-4076150435e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388
98208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3638898208
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.4164872081
Short name T1710
Test name
Test status
Simulation time 331131067 ps
CPU time 1.07 seconds
Started Jul 11 05:56:07 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 206368 kb
Host smart-2985c2d0-29fe-4d3e-a796-a419e7b10fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41648
72081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.4164872081
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3749548000
Short name T1183
Test name
Test status
Simulation time 846715817 ps
CPU time 2 seconds
Started Jul 11 05:56:09 PM PDT 24
Finished Jul 11 05:56:14 PM PDT 24
Peak memory 206656 kb
Host smart-597659a9-86c7-46e5-bc35-b3ab6f125419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37495
48000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3749548000
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1805640355
Short name T189
Test name
Test status
Simulation time 7034094344 ps
CPU time 12.44 seconds
Started Jul 11 05:56:03 PM PDT 24
Finished Jul 11 05:56:19 PM PDT 24
Peak memory 206704 kb
Host smart-1359a2f8-7916-4233-8621-95bb967eb88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
40355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1805640355
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.2542056788
Short name T2711
Test name
Test status
Simulation time 529813595 ps
CPU time 1.49 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 206332 kb
Host smart-1bd7b630-52f2-41d2-ab23-66981f3298a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25420
56788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2542056788
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2153835669
Short name T793
Test name
Test status
Simulation time 147540609 ps
CPU time 0.73 seconds
Started Jul 11 05:56:06 PM PDT 24
Finished Jul 11 05:56:10 PM PDT 24
Peak memory 206368 kb
Host smart-220bb52a-9297-4e62-96e1-79d6aeaebc27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21538
35669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2153835669
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2991366834
Short name T2631
Test name
Test status
Simulation time 49350473 ps
CPU time 0.66 seconds
Started Jul 11 05:56:09 PM PDT 24
Finished Jul 11 05:56:12 PM PDT 24
Peak memory 206384 kb
Host smart-eac1d5a8-8d0c-4aec-8f53-46fdf80eb62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
66834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2991366834
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.4006262424
Short name T802
Test name
Test status
Simulation time 779977566 ps
CPU time 1.93 seconds
Started Jul 11 05:56:01 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 206604 kb
Host smart-bb3b82e3-1a44-400e-a011-d6c255e8c647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40062
62424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.4006262424
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2722750930
Short name T2319
Test name
Test status
Simulation time 347633824 ps
CPU time 2.09 seconds
Started Jul 11 05:56:01 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 206512 kb
Host smart-e5aac1f2-17a4-4a9f-ae47-cee22cb2d0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27227
50930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2722750930
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3619883067
Short name T346
Test name
Test status
Simulation time 171706960 ps
CPU time 0.83 seconds
Started Jul 11 05:56:09 PM PDT 24
Finished Jul 11 05:56:13 PM PDT 24
Peak memory 206364 kb
Host smart-7e231c33-b4fc-4431-a9a2-10d27228f85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36198
83067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3619883067
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3940086868
Short name T688
Test name
Test status
Simulation time 139333105 ps
CPU time 0.8 seconds
Started Jul 11 05:56:07 PM PDT 24
Finished Jul 11 05:56:10 PM PDT 24
Peak memory 206356 kb
Host smart-75279ba5-1b98-43c4-bfba-a4363c82375a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39400
86868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3940086868
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2184601276
Short name T1282
Test name
Test status
Simulation time 170993674 ps
CPU time 0.84 seconds
Started Jul 11 05:56:05 PM PDT 24
Finished Jul 11 05:56:09 PM PDT 24
Peak memory 206324 kb
Host smart-d05022bb-4187-4ba5-b7aa-75dd25944157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
01276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2184601276
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.480964068
Short name T231
Test name
Test status
Simulation time 7389039353 ps
CPU time 65.4 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:57:11 PM PDT 24
Peak memory 206660 kb
Host smart-516089bf-4286-4453-9033-a7144b5b6252
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=480964068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.480964068
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.813770374
Short name T1679
Test name
Test status
Simulation time 10798829796 ps
CPU time 39.07 seconds
Started Jul 11 05:56:09 PM PDT 24
Finished Jul 11 05:56:51 PM PDT 24
Peak memory 206700 kb
Host smart-e4a4646b-f96d-490a-b120-65323041e902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81377
0374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.813770374
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1732529010
Short name T1246
Test name
Test status
Simulation time 229377391 ps
CPU time 0.93 seconds
Started Jul 11 05:56:08 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 206368 kb
Host smart-a3a202b0-34e0-4fc9-bdbb-2b97ce37066c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325
29010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1732529010
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1946979734
Short name T200
Test name
Test status
Simulation time 23279865188 ps
CPU time 23.08 seconds
Started Jul 11 05:56:05 PM PDT 24
Finished Jul 11 05:56:31 PM PDT 24
Peak memory 206456 kb
Host smart-b4090639-7d90-4c8c-ba3a-5a55356a4dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19469
79734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1946979734
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.4124239582
Short name T2532
Test name
Test status
Simulation time 3272558924 ps
CPU time 3.74 seconds
Started Jul 11 05:56:06 PM PDT 24
Finished Jul 11 05:56:12 PM PDT 24
Peak memory 206452 kb
Host smart-a25f1cec-1207-4fcf-9493-6b36f8a8a2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41242
39582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.4124239582
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.867181913
Short name T2661
Test name
Test status
Simulation time 8176537896 ps
CPU time 226.32 seconds
Started Jul 11 05:56:06 PM PDT 24
Finished Jul 11 05:59:55 PM PDT 24
Peak memory 206700 kb
Host smart-6b99cd35-b3a0-40a4-b809-2f7160ab52df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86718
1913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.867181913
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.1811207041
Short name T1132
Test name
Test status
Simulation time 3141605893 ps
CPU time 29.02 seconds
Started Jul 11 05:56:02 PM PDT 24
Finished Jul 11 05:56:34 PM PDT 24
Peak memory 206628 kb
Host smart-7dc33d87-ca0c-4d12-9c44-4fbf7e22c33e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1811207041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.1811207041
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3436233959
Short name T2713
Test name
Test status
Simulation time 265970714 ps
CPU time 0.94 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206388 kb
Host smart-a573f32b-e15f-40c3-9fdc-4cf9755c9cc0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3436233959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3436233959
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.933677427
Short name T643
Test name
Test status
Simulation time 208601334 ps
CPU time 0.87 seconds
Started Jul 11 05:56:14 PM PDT 24
Finished Jul 11 05:56:17 PM PDT 24
Peak memory 206372 kb
Host smart-c5cc380a-45c0-4f88-b436-8bc78d97f334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93367
7427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.933677427
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3416382193
Short name T1090
Test name
Test status
Simulation time 4853255850 ps
CPU time 42.24 seconds
Started Jul 11 05:56:14 PM PDT 24
Finished Jul 11 05:56:59 PM PDT 24
Peak memory 206724 kb
Host smart-259a83f8-2add-4d1a-b0b1-4009bfec0196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34163
82193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3416382193
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3609230056
Short name T1886
Test name
Test status
Simulation time 3890332537 ps
CPU time 109.31 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:58:09 PM PDT 24
Peak memory 206564 kb
Host smart-b6037a94-c26b-4a80-bf11-6ebd11692869
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3609230056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3609230056
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.4185588681
Short name T2005
Test name
Test status
Simulation time 155315103 ps
CPU time 0.81 seconds
Started Jul 11 05:56:13 PM PDT 24
Finished Jul 11 05:56:17 PM PDT 24
Peak memory 206332 kb
Host smart-56a487b3-7707-4b81-9dc6-84b03162ac64
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4185588681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.4185588681
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1120393258
Short name T1412
Test name
Test status
Simulation time 144406494 ps
CPU time 0.73 seconds
Started Jul 11 05:56:23 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 206308 kb
Host smart-3e0e1afc-8f75-401a-a331-ec28ef06a007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11203
93258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1120393258
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.156224006
Short name T149
Test name
Test status
Simulation time 195703641 ps
CPU time 0.9 seconds
Started Jul 11 05:56:18 PM PDT 24
Finished Jul 11 05:56:22 PM PDT 24
Peak memory 206364 kb
Host smart-e75a01df-3c6d-4edb-90e3-708905d7ada0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15622
4006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.156224006
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.1432416231
Short name T1672
Test name
Test status
Simulation time 193151129 ps
CPU time 0.86 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206356 kb
Host smart-3012cf50-1ecb-4b37-bdb8-eb9f6af40e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
16231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.1432416231
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.187990096
Short name T2728
Test name
Test status
Simulation time 159673953 ps
CPU time 0.75 seconds
Started Jul 11 05:56:16 PM PDT 24
Finished Jul 11 05:56:19 PM PDT 24
Peak memory 206304 kb
Host smart-e0065faa-3bfd-4687-8eb9-cacdc056e505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18799
0096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.187990096
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2081880409
Short name T2362
Test name
Test status
Simulation time 156019955 ps
CPU time 0.76 seconds
Started Jul 11 05:56:15 PM PDT 24
Finished Jul 11 05:56:19 PM PDT 24
Peak memory 206368 kb
Host smart-487c6fc4-45a5-47fe-ac4b-084c74d8b605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20818
80409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2081880409
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2528214969
Short name T2135
Test name
Test status
Simulation time 152788137 ps
CPU time 0.81 seconds
Started Jul 11 05:56:12 PM PDT 24
Finished Jul 11 05:56:16 PM PDT 24
Peak memory 206388 kb
Host smart-36392652-4f92-4d1f-b196-21e99f9fe69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25282
14969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2528214969
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.599970029
Short name T1554
Test name
Test status
Simulation time 211927371 ps
CPU time 0.93 seconds
Started Jul 11 05:56:10 PM PDT 24
Finished Jul 11 05:56:14 PM PDT 24
Peak memory 206388 kb
Host smart-eacbdfa9-6534-47dd-a6af-ab027512d39d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=599970029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.599970029
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1205954022
Short name T818
Test name
Test status
Simulation time 201922737 ps
CPU time 0.88 seconds
Started Jul 11 05:56:12 PM PDT 24
Finished Jul 11 05:56:16 PM PDT 24
Peak memory 206300 kb
Host smart-6c56298d-7ab2-4df8-b318-683412355790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059
54022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1205954022
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3253991948
Short name T2736
Test name
Test status
Simulation time 100430044 ps
CPU time 0.71 seconds
Started Jul 11 05:56:11 PM PDT 24
Finished Jul 11 05:56:15 PM PDT 24
Peak memory 206460 kb
Host smart-eb51596d-22a8-46d6-be15-7b4b9a6a15eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32539
91948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3253991948
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1641582780
Short name T260
Test name
Test status
Simulation time 14103991070 ps
CPU time 32.67 seconds
Started Jul 11 05:56:14 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 206592 kb
Host smart-e18b9c23-fba1-4439-a7c5-86603406b965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16415
82780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1641582780
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.698705526
Short name T1742
Test name
Test status
Simulation time 159159290 ps
CPU time 0.81 seconds
Started Jul 11 05:56:13 PM PDT 24
Finished Jul 11 05:56:16 PM PDT 24
Peak memory 206400 kb
Host smart-ff09d721-778b-4c16-adb6-b0a2bce20101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69870
5526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.698705526
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.956024779
Short name T851
Test name
Test status
Simulation time 270852735 ps
CPU time 0.93 seconds
Started Jul 11 05:56:12 PM PDT 24
Finished Jul 11 05:56:16 PM PDT 24
Peak memory 206380 kb
Host smart-40193a28-f861-417d-bac4-9f637a81e550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95602
4779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.956024779
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2339627651
Short name T169
Test name
Test status
Simulation time 4682053603 ps
CPU time 29.9 seconds
Started Jul 11 05:56:12 PM PDT 24
Finished Jul 11 05:56:45 PM PDT 24
Peak memory 206572 kb
Host smart-e2a509f0-c983-41f6-aa13-18378814cec8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2339627651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2339627651
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3058561890
Short name T176
Test name
Test status
Simulation time 15043727314 ps
CPU time 85.52 seconds
Started Jul 11 05:56:16 PM PDT 24
Finished Jul 11 05:57:44 PM PDT 24
Peak memory 206664 kb
Host smart-c8a13477-9722-4e5c-8c8c-a721d41d04bd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3058561890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3058561890
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2525230970
Short name T2552
Test name
Test status
Simulation time 7625351314 ps
CPU time 30.21 seconds
Started Jul 11 05:56:11 PM PDT 24
Finished Jul 11 05:56:44 PM PDT 24
Peak memory 206604 kb
Host smart-f0109085-4c5d-4ebf-8f3b-ad3b06d2175e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2525230970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2525230970
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2002483979
Short name T795
Test name
Test status
Simulation time 253255755 ps
CPU time 0.93 seconds
Started Jul 11 05:56:10 PM PDT 24
Finished Jul 11 05:56:14 PM PDT 24
Peak memory 206384 kb
Host smart-7e8f73f9-dc79-4531-984d-db12138e2f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20024
83979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2002483979
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3883925531
Short name T223
Test name
Test status
Simulation time 234435438 ps
CPU time 0.87 seconds
Started Jul 11 05:56:16 PM PDT 24
Finished Jul 11 05:56:19 PM PDT 24
Peak memory 206420 kb
Host smart-b88600b5-1a17-4d25-8d6d-119cb0d01823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
25531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3883925531
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2989033668
Short name T608
Test name
Test status
Simulation time 137454616 ps
CPU time 0.69 seconds
Started Jul 11 05:56:13 PM PDT 24
Finished Jul 11 05:56:16 PM PDT 24
Peak memory 206312 kb
Host smart-2b0b9d02-45c9-4186-8992-1b0365709209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29890
33668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2989033668
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.811022847
Short name T2490
Test name
Test status
Simulation time 151537339 ps
CPU time 0.77 seconds
Started Jul 11 05:56:14 PM PDT 24
Finished Jul 11 05:56:18 PM PDT 24
Peak memory 206380 kb
Host smart-63f07f66-5f3f-426b-97b4-42a9d0ca7b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81102
2847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.811022847
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2635498459
Short name T2625
Test name
Test status
Simulation time 146748058 ps
CPU time 0.78 seconds
Started Jul 11 05:56:16 PM PDT 24
Finished Jul 11 05:56:19 PM PDT 24
Peak memory 206384 kb
Host smart-a0c1861e-e037-46d2-b656-34eb0988519c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26354
98459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2635498459
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.57414784
Short name T1105
Test name
Test status
Simulation time 291122388 ps
CPU time 1.01 seconds
Started Jul 11 05:56:22 PM PDT 24
Finished Jul 11 05:56:28 PM PDT 24
Peak memory 206304 kb
Host smart-a62b12bd-d915-47dc-af8a-6727c859b95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57414
784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.57414784
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.157260694
Short name T627
Test name
Test status
Simulation time 3746405987 ps
CPU time 35.78 seconds
Started Jul 11 05:56:15 PM PDT 24
Finished Jul 11 05:56:54 PM PDT 24
Peak memory 206680 kb
Host smart-0dd596e3-46ba-4fe6-b0b2-72052d8a52b8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=157260694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.157260694
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3303265866
Short name T1680
Test name
Test status
Simulation time 156289149 ps
CPU time 0.82 seconds
Started Jul 11 05:56:17 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 206396 kb
Host smart-f7062807-8532-415e-8ff7-f9821e44bc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33032
65866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3303265866
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3499728100
Short name T689
Test name
Test status
Simulation time 142996526 ps
CPU time 0.78 seconds
Started Jul 11 05:56:19 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 206360 kb
Host smart-697822f2-cb72-438b-affb-03099e5c37ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34997
28100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3499728100
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.4274650576
Short name T1172
Test name
Test status
Simulation time 494270467 ps
CPU time 1.41 seconds
Started Jul 11 05:56:15 PM PDT 24
Finished Jul 11 05:56:19 PM PDT 24
Peak memory 206376 kb
Host smart-687616bb-19c7-41fc-87b1-68ca933831bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42746
50576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.4274650576
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1515542641
Short name T92
Test name
Test status
Simulation time 3888761973 ps
CPU time 103.31 seconds
Started Jul 11 05:56:11 PM PDT 24
Finished Jul 11 05:57:57 PM PDT 24
Peak memory 206520 kb
Host smart-2d0ab9e3-4107-41fc-9260-93d396a7a02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15155
42641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1515542641
Directory /workspace/9.usbdev_streaming_out/latest
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