Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	169411	1		T1	4		T2	3		T3	2
all_values[1]	169411	1		T1	4		T2	3		T3	2
all_values[2]	169411	1		T1	4		T2	3		T3	2
all_values[3]	169411	1		T1	4		T2	3		T3	2
all_values[4]	169411	1		T1	4		T2	3		T3	2
all_values[5]	169411	1		T1	4		T2	3		T3	2
all_values[6]	169411	1		T1	4		T2	3		T3	2
all_values[7]	169411	1		T1	4		T2	3		T3	2
all_values[8]	169411	1		T1	4		T2	3		T3	2
all_values[9]	169411	1		T1	4		T2	3		T3	2
all_values[10]	169411	1		T1	4		T2	3		T3	2
all_values[11]	169411	1		T1	4		T2	3		T3	2
all_values[12]	169411	1		T1	4		T2	3		T3	2
all_values[13]	169411	1		T1	4		T2	3		T3	2
all_values[14]	169411	1		T1	4		T2	3		T3	2
all_values[15]	169411	1		T1	4		T2	3		T3	2
all_values[16]	169411	1		T1	4		T2	3		T3	2
all_values[17]	169411	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3042596	1		T1	72		T2	51		T3	36
auto[1]	6802	1		T2	3		T26	2		T6	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3044289	1		T1	72		T2	54		T3	36
auto[1]	5109	1		T199	127		T200	118		T201	122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	168427	1		T1	4		T3	2		T26	2
all_values[0]	auto[0]	auto[1]	151	1		T199	6		T200	6		T201	3
all_values[0]	auto[1]	auto[0]	701	1		T2	3		T22	3		T43	3
all_values[0]	auto[1]	auto[1]	132	1		T199	2		T200	2		T201	1
all_values[1]	auto[0]	auto[0]	167606	1		T1	4		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	121	1		T199	5		T201	2		T283	1
all_values[1]	auto[1]	auto[0]	1532	1		T6	2		T19	2		T20	2
all_values[1]	auto[1]	auto[1]	152	1		T199	3		T201	5		T283	6
all_values[2]	auto[0]	auto[0]	169002	1		T1	4		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	153	1		T199	3		T200	5		T201	1
all_values[2]	auto[1]	auto[0]	120	1		T26	2		T31	2		T39	2
all_values[2]	auto[1]	auto[1]	136	1		T199	4		T200	3		T201	6
all_values[3]	auto[0]	auto[0]	167702	1		T1	4		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	141	1		T199	3		T200	6		T201	2
all_values[3]	auto[1]	auto[0]	1426	1		T61	1396		T284	1		T286	1
all_values[3]	auto[1]	auto[1]	142	1		T199	5		T200	2		T201	6
all_values[4]	auto[0]	auto[0]	169098	1		T1	4		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	144	1		T199	5		T200	4		T201	5
all_values[4]	auto[1]	auto[0]	26	1		T62	2		T200	1		T283	2
all_values[4]	auto[1]	auto[1]	143	1		T199	2		T200	2		T201	3
all_values[5]	auto[0]	auto[0]	169102	1		T1	4		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	169	1		T199	4		T200	4		T201	2
all_values[5]	auto[1]	auto[0]	29	1		T201	1		T283	1		T202	4
all_values[5]	auto[1]	auto[1]	111	1		T199	4		T200	4		T201	5
all_values[6]	auto[0]	auto[0]	169103	1		T1	4		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	166	1		T200	3		T201	5		T202	4
all_values[6]	auto[1]	auto[0]	25	1		T200	3		T201	1		T283	3
all_values[6]	auto[1]	auto[1]	117	1		T199	8		T200	1		T201	1
all_values[7]	auto[0]	auto[0]	169107	1		T1	4		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	138	1		T199	4		T200	7		T201	4
all_values[7]	auto[1]	auto[0]	29	1		T45	2		T46	2		T199	1
all_values[7]	auto[1]	auto[1]	137	1		T199	1		T200	1		T201	4
all_values[8]	auto[0]	auto[0]	169090	1		T1	4		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	165	1		T199	8		T200	6		T201	5
all_values[8]	auto[1]	auto[0]	39	1		T50	11		T200	1		T287	4
all_values[8]	auto[1]	auto[1]	117	1		T201	3		T283	4		T202	3
all_values[9]	auto[0]	auto[0]	169070	1		T1	4		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	135	1		T199	1		T200	4		T201	3
all_values[9]	auto[1]	auto[0]	42	1		T58	5		T59	5		T60	5
all_values[9]	auto[1]	auto[1]	164	1		T199	6		T200	2		T201	4
all_values[10]	auto[0]	auto[0]	169103	1		T1	4		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	147	1		T199	1		T200	4		T201	3
all_values[10]	auto[1]	auto[0]	22	1		T201	1		T283	1		T287	4
all_values[10]	auto[1]	auto[1]	139	1		T199	5		T200	4		T201	1
all_values[11]	auto[0]	auto[0]	169016	1		T1	4		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	144	1		T199	4		T200	6		T201	6
all_values[11]	auto[1]	auto[0]	126	1		T42	2		T67	2		T68	2
all_values[11]	auto[1]	auto[1]	125	1		T199	3		T200	2		T201	1
all_values[12]	auto[0]	auto[0]	169082	1		T1	4		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	149	1		T199	3		T201	7		T283	1
all_values[12]	auto[1]	auto[0]	41	1		T69	3		T72	3		T73	3
all_values[12]	auto[1]	auto[1]	139	1		T199	5		T200	4		T283	4
all_values[13]	auto[0]	auto[0]	169096	1		T1	4		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	132	1		T199	1		T200	5		T201	1
all_values[13]	auto[1]	auto[0]	29	1		T283	3		T287	4		T288	1
all_values[13]	auto[1]	auto[1]	154	1		T199	6		T200	3		T201	5
all_values[14]	auto[0]	auto[0]	169101	1		T1	4		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	132	1		T199	3		T200	5		T201	2
all_values[14]	auto[1]	auto[0]	28	1		T200	1		T283	3		T289	4
all_values[14]	auto[1]	auto[1]	150	1		T199	5		T200	2		T201	5
all_values[15]	auto[0]	auto[0]	169096	1		T1	4		T2	3		T3	2
all_values[15]	auto[0]	auto[1]	138	1		T199	2		T200	5		T201	5
all_values[15]	auto[1]	auto[0]	24	1		T199	2		T283	1		T284	1
all_values[15]	auto[1]	auto[1]	153	1		T199	3		T200	1		T201	3
all_values[16]	auto[0]	auto[0]	169077	1		T1	4		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	153	1		T199	2		T200	8		T201	6
all_values[16]	auto[1]	auto[0]	47	1		T64	8		T65	8		T66	8
all_values[16]	auto[1]	auto[1]	134	1		T199	6		T201	2		T283	5
all_values[17]	auto[0]	auto[0]	169089	1		T1	4		T2	3		T3	2
all_values[17]	auto[0]	auto[1]	151	1		T199	4		T200	2		T201	1
all_values[17]	auto[1]	auto[0]	36	1		T51	2		T52	2		T53	2
all_values[17]	auto[1]	auto[1]	135	1		T200	5		T201	4		T283	7