Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	169411	1		T1	4		T2	3		T3	2
all_pins[1]	169411	1		T1	4		T2	3		T3	2
all_pins[2]	169411	1		T1	4		T2	3		T3	2
all_pins[3]	169411	1		T1	4		T2	3		T3	2
all_pins[4]	169411	1		T1	4		T2	3		T3	2
all_pins[5]	169411	1		T1	4		T2	3		T3	2
all_pins[6]	169411	1		T1	4		T2	3		T3	2
all_pins[7]	169411	1		T1	4		T2	3		T3	2
all_pins[8]	169411	1		T1	4		T2	3		T3	2
all_pins[9]	169411	1		T1	4		T2	3		T3	2
all_pins[10]	169411	1		T1	4		T2	3		T3	2
all_pins[11]	169411	1		T1	4		T2	3		T3	2
all_pins[12]	169411	1		T1	4		T2	3		T3	2
all_pins[13]	169411	1		T1	4		T2	3		T3	2
all_pins[14]	169411	1		T1	4		T2	3		T3	2
all_pins[15]	169411	1		T1	4		T2	3		T3	2
all_pins[16]	169411	1		T1	4		T2	3		T3	2
all_pins[17]	169411	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3047117	1		T1	72		T2	54		T3	36
values[0x1]	2281	1		T26	1		T6	1		T19	1
transitions[0x0=>0x1]	1985	1		T26	1		T6	1		T19	1
transitions[0x1=>0x0]	1995	1		T26	1		T6	1		T19	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	169312	1		T1	4		T2	3		T3	2
all_pins[0]	values[0x1]	99	1		T290	1		T291	1		T292	1
all_pins[0]	transitions[0x0=>0x1]	82	1		T290	1		T291	1		T292	1
all_pins[0]	transitions[0x1=>0x0]	1003	1		T6	1		T19	1		T20	1
all_pins[1]	values[0x0]	168391	1		T1	4		T2	3		T3	2
all_pins[1]	values[0x1]	1020	1		T6	1		T19	1		T20	1
all_pins[1]	transitions[0x0=>0x1]	999	1		T6	1		T19	1		T20	1
all_pins[1]	transitions[0x1=>0x0]	106	1		T26	1		T31	1		T39	1
all_pins[2]	values[0x0]	169284	1		T1	4		T2	3		T3	2
all_pins[2]	values[0x1]	127	1		T26	1		T31	1		T39	1
all_pins[2]	transitions[0x0=>0x1]	106	1		T26	1		T31	1		T39	1
all_pins[2]	transitions[0x1=>0x0]	52	1		T61	1		T199	3		T200	1
all_pins[3]	values[0x0]	169338	1		T1	4		T2	3		T3	2
all_pins[3]	values[0x1]	73	1		T61	1		T199	4		T200	1
all_pins[3]	transitions[0x0=>0x1]	49	1		T61	1		T199	3		T200	1
all_pins[3]	transitions[0x1=>0x0]	49	1		T62	1		T199	1		T200	1
all_pins[4]	values[0x0]	169338	1		T1	4		T2	3		T3	2
all_pins[4]	values[0x1]	73	1		T62	1		T199	2		T200	1
all_pins[4]	transitions[0x0=>0x1]	58	1		T62	1		T199	2		T200	1
all_pins[4]	transitions[0x1=>0x0]	33	1		T199	1		T200	1		T283	1
all_pins[5]	values[0x0]	169363	1		T1	4		T2	3		T3	2
all_pins[5]	values[0x1]	48	1		T199	1		T200	1		T201	1
all_pins[5]	transitions[0x0=>0x1]	38	1		T200	1		T201	1		T283	1
all_pins[5]	transitions[0x1=>0x0]	55	1		T199	5		T200	1		T283	2
all_pins[6]	values[0x0]	169346	1		T1	4		T2	3		T3	2
all_pins[6]	values[0x1]	65	1		T199	6		T200	1		T283	2
all_pins[6]	transitions[0x0=>0x1]	51	1		T199	6		T200	1		T283	2
all_pins[6]	transitions[0x1=>0x0]	48	1		T45	1		T46	1		T199	1
all_pins[7]	values[0x0]	169349	1		T1	4		T2	3		T3	2
all_pins[7]	values[0x1]	62	1		T45	1		T46	1		T199	1
all_pins[7]	transitions[0x0=>0x1]	48	1		T45	1		T46	1		T199	1
all_pins[7]	transitions[0x1=>0x0]	31	1		T50	1		T201	2		T284	1
all_pins[8]	values[0x0]	169366	1		T1	4		T2	3		T3	2
all_pins[8]	values[0x1]	45	1		T50	1		T201	2		T284	1
all_pins[8]	transitions[0x0=>0x1]	36	1		T50	1		T201	2		T284	1
all_pins[8]	transitions[0x1=>0x0]	60	1		T58	2		T59	2		T60	2
all_pins[9]	values[0x0]	169342	1		T1	4		T2	3		T3	2
all_pins[9]	values[0x1]	69	1		T58	2		T59	2		T60	2
all_pins[9]	transitions[0x0=>0x1]	58	1		T58	2		T59	2		T60	2
all_pins[9]	transitions[0x1=>0x0]	60	1		T200	3		T201	1		T289	2
all_pins[10]	values[0x0]	169340	1		T1	4		T2	3		T3	2
all_pins[10]	values[0x1]	71	1		T199	3		T200	3		T201	1
all_pins[10]	transitions[0x0=>0x1]	56	1		T199	3		T200	2		T283	1
all_pins[10]	transitions[0x1=>0x0]	101	1		T42	1		T67	1		T68	1
all_pins[11]	values[0x0]	169295	1		T1	4		T2	3		T3	2
all_pins[11]	values[0x1]	116	1		T42	1		T67	1		T68	1
all_pins[11]	transitions[0x0=>0x1]	94	1		T42	1		T67	1		T68	1
all_pins[11]	transitions[0x1=>0x0]	50	1		T69	1		T72	1		T73	1
all_pins[12]	values[0x0]	169339	1		T1	4		T2	3		T3	2
all_pins[12]	values[0x1]	72	1		T69	1		T72	1		T73	1
all_pins[12]	transitions[0x0=>0x1]	52	1		T69	1		T72	1		T73	1
all_pins[12]	transitions[0x1=>0x0]	52	1		T199	5		T200	2		T201	3
all_pins[13]	values[0x0]	169339	1		T1	4		T2	3		T3	2
all_pins[13]	values[0x1]	72	1		T199	5		T200	2		T201	3
all_pins[13]	transitions[0x0=>0x1]	56	1		T199	4		T200	2		T201	1
all_pins[13]	transitions[0x1=>0x0]	48	1		T202	3		T285	1		T286	2
all_pins[14]	values[0x0]	169347	1		T1	4		T2	3		T3	2
all_pins[14]	values[0x1]	64	1		T199	1		T201	2		T202	3
all_pins[14]	transitions[0x0=>0x1]	41	1		T199	1		T201	2		T202	1
all_pins[14]	transitions[0x1=>0x0]	59	1		T199	2		T200	1		T201	3
all_pins[15]	values[0x0]	169329	1		T1	4		T2	3		T3	2
all_pins[15]	values[0x1]	82	1		T199	2		T200	1		T201	3
all_pins[15]	transitions[0x0=>0x1]	61	1		T199	2		T200	1		T201	2
all_pins[15]	transitions[0x1=>0x0]	50	1		T64	4		T65	4		T66	4
all_pins[16]	values[0x0]	169340	1		T1	4		T2	3		T3	2
all_pins[16]	values[0x1]	71	1		T64	4		T65	4		T66	4
all_pins[16]	transitions[0x0=>0x1]	62	1		T64	4		T65	4		T66	4
all_pins[16]	transitions[0x1=>0x0]	43	1		T51	1		T52	1		T53	1
all_pins[17]	values[0x0]	169359	1		T1	4		T2	3		T3	2
all_pins[17]	values[0x1]	52	1		T51	1		T52	1		T53	1
all_pins[17]	transitions[0x0=>0x1]	38	1		T51	1		T52	1		T53	1
all_pins[17]	transitions[0x1=>0x0]	95	1		T290	1		T291	1		T292	1