Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00
Crosses 108 0 108 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 18 0 18 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 108 0 108 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 18 0 18 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 284 1 T199 7 T200 7 T201 7
all_values[1] 284 1 T199 7 T200 7 T201 7
all_values[2] 284 1 T199 7 T200 7 T201 7
all_values[3] 284 1 T199 7 T200 7 T201 7
all_values[4] 284 1 T199 7 T200 7 T201 7
all_values[5] 284 1 T199 7 T200 7 T201 7
all_values[6] 284 1 T199 7 T200 7 T201 7
all_values[7] 284 1 T199 7 T200 7 T201 7
all_values[8] 284 1 T199 7 T200 7 T201 7
all_values[9] 284 1 T199 7 T200 7 T201 7
all_values[10] 284 1 T199 7 T200 7 T201 7
all_values[11] 284 1 T199 7 T200 7 T201 7
all_values[12] 284 1 T199 7 T200 7 T201 7
all_values[13] 284 1 T199 7 T200 7 T201 7
all_values[14] 284 1 T199 7 T200 7 T201 7
all_values[15] 284 1 T199 7 T200 7 T201 7
all_values[16] 284 1 T199 7 T200 7 T201 7
all_values[17] 284 1 T199 7 T200 7 T201 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2816 1 T199 62 T200 84 T201 71
auto[1] 2296 1 T199 64 T200 42 T201 55



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 861 1 T199 17 T200 25 T201 22
auto[1] 4251 1 T199 109 T200 101 T201 104



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3027 1 T199 78 T200 78 T201 73
auto[1] 2085 1 T199 48 T200 48 T201 53



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 108 0 108 100.00
Automatically Generated Cross Bins 108 0 108 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 25 1 T201 2 T283 1 T284 1
all_values[0] auto[0] auto[0] auto[1] 56 1 T199 2 T200 3 T201 1
all_values[0] auto[0] auto[1] auto[0] 23 1 T201 2 T283 2 T293 2
all_values[0] auto[0] auto[1] auto[1] 62 1 T199 1 T200 2 T283 1
all_values[0] auto[1] auto[0] auto[1] 71 1 T199 3 T200 1 T201 1
all_values[0] auto[1] auto[1] auto[1] 47 1 T199 1 T200 1 T201 1
all_values[1] auto[0] auto[0] auto[0] 35 1 T200 4 T201 1 T284 1
all_values[1] auto[0] auto[0] auto[1] 47 1 T199 2 T202 1 T289 2
all_values[1] auto[0] auto[1] auto[0] 22 1 T200 3 T283 1 T293 1
all_values[1] auto[0] auto[1] auto[1] 60 1 T199 2 T201 3 T283 3
all_values[1] auto[1] auto[0] auto[1] 63 1 T199 2 T201 3 T283 1
all_values[1] auto[1] auto[1] auto[1] 57 1 T199 1 T283 2 T202 1
all_values[2] auto[0] auto[0] auto[0] 29 1 T199 1 T201 1 T285 1
all_values[2] auto[0] auto[0] auto[1] 59 1 T199 1 T200 2 T201 1
all_values[2] auto[0] auto[1] auto[0] 15 1 T284 1 T286 2 T288 1
all_values[2] auto[0] auto[1] auto[1] 61 1 T199 2 T200 2 T201 3
all_values[2] auto[1] auto[0] auto[1] 70 1 T199 2 T200 3 T201 1
all_values[2] auto[1] auto[1] auto[1] 50 1 T199 1 T201 1 T283 2
all_values[3] auto[0] auto[0] auto[0] 29 1 T202 1 T286 1 T294 1
all_values[3] auto[0] auto[0] auto[1] 53 1 T199 1 T200 1 T201 1
all_values[3] auto[0] auto[1] auto[0] 17 1 T284 1 T295 1 T296 4
all_values[3] auto[0] auto[1] auto[1] 59 1 T199 4 T200 2 T201 1
all_values[3] auto[1] auto[0] auto[1] 74 1 T199 2 T200 4 T201 2
all_values[3] auto[1] auto[1] auto[1] 52 1 T201 3 T283 3 T284 2
all_values[4] auto[0] auto[0] auto[0] 27 1 T199 1 T200 2 T283 1
all_values[4] auto[0] auto[0] auto[1] 65 1 T199 3 T200 3 T201 2
all_values[4] auto[0] auto[1] auto[0] 19 1 T283 3 T202 1 T286 1
all_values[4] auto[0] auto[1] auto[1] 68 1 T199 1 T201 2 T202 2
all_values[4] auto[1] auto[0] auto[1] 62 1 T199 1 T201 3 T283 1
all_values[4] auto[1] auto[1] auto[1] 43 1 T199 1 T200 2 T202 1
all_values[5] auto[0] auto[0] auto[0] 28 1 T289 3 T284 1 T287 2
all_values[5] auto[0] auto[0] auto[1] 61 1 T199 2 T283 2 T284 3
all_values[5] auto[0] auto[1] auto[0] 21 1 T201 1 T283 1 T202 4
all_values[5] auto[0] auto[1] auto[1] 52 1 T199 3 T200 1 T201 4
all_values[5] auto[1] auto[0] auto[1] 89 1 T199 1 T200 5 T201 1
all_values[5] auto[1] auto[1] auto[1] 33 1 T199 1 T200 1 T201 1
all_values[6] auto[0] auto[0] auto[0] 29 1 T200 1 T201 2 T283 3
all_values[6] auto[0] auto[0] auto[1] 75 1 T200 1 T201 1 T202 3
all_values[6] auto[0] auto[1] auto[0] 20 1 T200 3 T283 2 T288 3
all_values[6] auto[0] auto[1] auto[1] 53 1 T199 3 T201 1 T283 1
all_values[6] auto[1] auto[0] auto[1] 61 1 T200 1 T201 2 T283 1
all_values[6] auto[1] auto[1] auto[1] 46 1 T199 4 T200 1 T201 1
all_values[7] auto[0] auto[0] auto[0] 36 1 T199 2 T289 1 T285 2
all_values[7] auto[0] auto[0] auto[1] 60 1 T199 2 T200 4 T201 2
all_values[7] auto[0] auto[1] auto[0] 19 1 T199 1 T289 3 T287 2
all_values[7] auto[0] auto[1] auto[1] 54 1 T200 1 T201 2 T202 1
all_values[7] auto[1] auto[0] auto[1] 67 1 T199 1 T200 2 T201 3
all_values[7] auto[1] auto[1] auto[1] 48 1 T199 1 T283 2 T202 1
all_values[8] auto[0] auto[0] auto[0] 29 1 T284 1 T286 2 T287 2
all_values[8] auto[0] auto[0] auto[1] 71 1 T199 4 T200 3 T201 4
all_values[8] auto[0] auto[1] auto[0] 21 1 T200 2 T287 2 T297 2
all_values[8] auto[0] auto[1] auto[1] 54 1 T283 1 T202 2 T284 3
all_values[8] auto[1] auto[0] auto[1] 70 1 T199 3 T200 2 T283 2
all_values[8] auto[1] auto[1] auto[1] 39 1 T201 3 T288 2 T293 1
all_values[9] auto[0] auto[0] auto[0] 20 1 T199 1 T284 2 T294 2
all_values[9] auto[0] auto[0] auto[1] 64 1 T200 3 T201 2 T283 2
all_values[9] auto[0] auto[1] auto[0] 14 1 T200 2 T201 1 T283 1
all_values[9] auto[0] auto[1] auto[1] 73 1 T199 1 T200 1 T201 2
all_values[9] auto[1] auto[0] auto[1] 60 1 T199 1 T200 1 T201 1
all_values[9] auto[1] auto[1] auto[1] 53 1 T199 4 T201 1 T283 1
all_values[10] auto[0] auto[0] auto[0] 31 1 T199 2 T201 3 T283 2
all_values[10] auto[0] auto[0] auto[1] 67 1 T200 1 T201 1 T202 2
all_values[10] auto[0] auto[1] auto[0] 15 1 T201 1 T283 1 T287 2
all_values[10] auto[0] auto[1] auto[1] 49 1 T199 3 T283 1 T289 1
all_values[10] auto[1] auto[0] auto[1] 65 1 T199 1 T200 3 T201 1
all_values[10] auto[1] auto[1] auto[1] 57 1 T199 1 T200 3 T201 1
all_values[11] auto[0] auto[0] auto[0] 45 1 T201 1 T283 1 T289 1
all_values[11] auto[0] auto[0] auto[1] 61 1 T199 2 T200 3 T201 3
all_values[11] auto[0] auto[1] auto[0] 17 1 T199 1 T202 2 T294 2
all_values[11] auto[0] auto[1] auto[1] 50 1 T199 1 T200 2 T283 5
all_values[11] auto[1] auto[0] auto[1] 58 1 T199 1 T200 2 T201 2
all_values[11] auto[1] auto[1] auto[1] 53 1 T199 2 T201 1 T283 1
all_values[12] auto[0] auto[0] auto[0] 26 1 T200 4 T283 1 T284 1
all_values[12] auto[0] auto[0] auto[1] 59 1 T199 2 T201 3 T202 1
all_values[12] auto[0] auto[1] auto[0] 19 1 T201 1 T283 2 T294 2
all_values[12] auto[0] auto[1] auto[1] 59 1 T199 3 T200 2 T283 1
all_values[12] auto[1] auto[0] auto[1] 64 1 T199 1 T201 2 T202 1
all_values[12] auto[1] auto[1] auto[1] 57 1 T199 1 T200 1 T201 1
all_values[13] auto[0] auto[0] auto[0] 25 1 T199 1 T201 2 T283 2
all_values[13] auto[0] auto[0] auto[1] 55 1 T200 3 T201 1 T283 2
all_values[13] auto[0] auto[1] auto[0] 21 1 T283 2 T287 2 T288 1
all_values[13] auto[0] auto[1] auto[1] 65 1 T199 3 T200 1 T201 1
all_values[13] auto[1] auto[0] auto[1] 59 1 T199 1 T200 1 T201 1
all_values[13] auto[1] auto[1] auto[1] 59 1 T199 2 T200 2 T201 2
all_values[14] auto[0] auto[0] auto[0] 32 1 T201 1 T283 1 T289 2
all_values[14] auto[0] auto[0] auto[1] 56 1 T200 3 T283 1 T284 2
all_values[14] auto[0] auto[1] auto[0] 18 1 T200 1 T283 4 T289 2
all_values[14] auto[0] auto[1] auto[1] 65 1 T199 3 T200 1 T201 3
all_values[14] auto[1] auto[0] auto[1] 61 1 T199 3 T200 1 T201 3
all_values[14] auto[1] auto[1] auto[1] 52 1 T199 1 T200 1 T283 1
all_values[15] auto[0] auto[0] auto[0] 27 1 T199 1 T200 2 T289 2
all_values[15] auto[0] auto[0] auto[1] 58 1 T200 2 T201 2 T283 1
all_values[15] auto[0] auto[1] auto[0] 16 1 T199 2 T283 1 T284 2
all_values[15] auto[0] auto[1] auto[1] 61 1 T199 2 T201 1 T283 2
all_values[15] auto[1] auto[0] auto[1] 64 1 T199 2 T200 2 T201 2
all_values[15] auto[1] auto[1] auto[1] 58 1 T200 1 T201 2 T283 1
all_values[16] auto[0] auto[0] auto[0] 29 1 T283 1 T284 1 T287 1
all_values[16] auto[0] auto[0] auto[1] 55 1 T199 1 T200 3 T201 2
all_values[16] auto[0] auto[1] auto[0] 16 1 T294 1 T298 1 T299 1
all_values[16] auto[0] auto[1] auto[1] 72 1 T199 5 T283 1 T289 3
all_values[16] auto[1] auto[0] auto[1] 73 1 T199 1 T200 4 T201 2
all_values[16] auto[1] auto[1] auto[1] 39 1 T201 3 T283 2 T284 2
all_values[17] auto[0] auto[0] auto[0] 23 1 T199 2 T200 1 T201 1
all_values[17] auto[0] auto[0] auto[1] 69 1 T199 2 T200 2 T283 1
all_values[17] auto[0] auto[1] auto[0] 23 1 T199 2 T201 2 T286 1
all_values[17] auto[0] auto[1] auto[1] 58 1 T200 1 T201 2 T283 4
all_values[17] auto[1] auto[0] auto[1] 69 1 T199 1 T200 1 T201 1
all_values[17] auto[1] auto[1] auto[1] 42 1 T200 2 T201 1 T283 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%