Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.59 97.84 93.81 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2853
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T2765 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1727903520 Jul 12 06:36:18 PM PDT 24 Jul 12 06:36:23 PM PDT 24 711865085 ps
T265 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1678512921 Jul 12 06:36:19 PM PDT 24 Jul 12 06:36:21 PM PDT 24 117063631 ps
T295 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3822143552 Jul 12 06:36:34 PM PDT 24 Jul 12 06:36:37 PM PDT 24 31595318 ps
T2766 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2418947028 Jul 12 06:36:10 PM PDT 24 Jul 12 06:36:12 PM PDT 24 187275869 ps
T307 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1768358196 Jul 12 06:36:36 PM PDT 24 Jul 12 06:36:45 PM PDT 24 1309011045 ps
T2767 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2108137299 Jul 12 06:36:52 PM PDT 24 Jul 12 06:36:56 PM PDT 24 76959801 ps
T297 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1767996787 Jul 12 06:36:36 PM PDT 24 Jul 12 06:36:39 PM PDT 24 33320773 ps
T2768 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3980414722 Jul 12 06:36:10 PM PDT 24 Jul 12 06:36:12 PM PDT 24 143202169 ps
T296 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2544652177 Jul 12 06:36:40 PM PDT 24 Jul 12 06:36:42 PM PDT 24 49328458 ps
T266 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2493180637 Jul 12 06:36:11 PM PDT 24 Jul 12 06:36:15 PM PDT 24 206596176 ps
T2769 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.237193656 Jul 12 06:36:22 PM PDT 24 Jul 12 06:36:25 PM PDT 24 29270390 ps
T2770 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2491670673 Jul 12 06:36:11 PM PDT 24 Jul 12 06:36:16 PM PDT 24 165486158 ps
T2771 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4191680836 Jul 12 06:36:24 PM PDT 24 Jul 12 06:36:27 PM PDT 24 86184719 ps
T2772 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3971351772 Jul 12 06:36:28 PM PDT 24 Jul 12 06:36:34 PM PDT 24 462296895 ps
T2773 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2231215561 Jul 12 06:36:24 PM PDT 24 Jul 12 06:36:30 PM PDT 24 112076506 ps
T2774 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3521770871 Jul 12 06:36:19 PM PDT 24 Jul 12 06:36:21 PM PDT 24 41096111 ps
T2775 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3451713550 Jul 12 06:36:37 PM PDT 24 Jul 12 06:36:40 PM PDT 24 81061703 ps
T2776 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1210666180 Jul 12 06:36:36 PM PDT 24 Jul 12 06:36:39 PM PDT 24 43045093 ps
T301 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1202979147 Jul 12 06:36:25 PM PDT 24 Jul 12 06:36:32 PM PDT 24 713185409 ps
T2777 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.57857848 Jul 12 06:36:10 PM PDT 24 Jul 12 06:36:12 PM PDT 24 177622487 ps
T2778 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1569966212 Jul 12 06:36:36 PM PDT 24 Jul 12 06:36:40 PM PDT 24 178765430 ps
T267 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1625100775 Jul 12 06:36:32 PM PDT 24 Jul 12 06:36:34 PM PDT 24 60346345 ps
T303 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2647567733 Jul 12 06:36:29 PM PDT 24 Jul 12 06:36:35 PM PDT 24 855422060 ps
T2779 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2717089823 Jul 12 06:36:33 PM PDT 24 Jul 12 06:36:38 PM PDT 24 285518029 ps
T2780 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2467777940 Jul 12 06:36:23 PM PDT 24 Jul 12 06:36:29 PM PDT 24 128966231 ps
T268 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3430054122 Jul 12 06:36:33 PM PDT 24 Jul 12 06:36:36 PM PDT 24 76593557 ps
T2781 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.725334688 Jul 12 06:36:18 PM PDT 24 Jul 12 06:36:20 PM PDT 24 133150242 ps
T299 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.978511445 Jul 12 06:36:37 PM PDT 24 Jul 12 06:36:40 PM PDT 24 38599825 ps
T2782 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2801206081 Jul 12 06:36:33 PM PDT 24 Jul 12 06:36:37 PM PDT 24 156570561 ps
T2783 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3992108525 Jul 12 06:36:33 PM PDT 24 Jul 12 06:36:35 PM PDT 24 72210939 ps
T2784 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3879116616 Jul 12 06:36:22 PM PDT 24 Jul 12 06:36:26 PM PDT 24 64456465 ps
T309 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2495084907 Jul 12 06:36:36 PM PDT 24 Jul 12 06:36:41 PM PDT 24 404326326 ps
T2785 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3173714178 Jul 12 06:36:27 PM PDT 24 Jul 12 06:36:30 PM PDT 24 119086594 ps
T2786 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1598098835 Jul 12 06:36:25 PM PDT 24 Jul 12 06:36:28 PM PDT 24 44146685 ps
T2787 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.743973725 Jul 12 06:36:34 PM PDT 24 Jul 12 06:36:37 PM PDT 24 153465672 ps
T2788 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.39351819 Jul 12 06:36:36 PM PDT 24 Jul 12 06:36:39 PM PDT 24 38487861 ps
T2789 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3398679152 Jul 12 06:36:32 PM PDT 24 Jul 12 06:36:34 PM PDT 24 58053761 ps
T2790 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2036671408 Jul 12 06:36:10 PM PDT 24 Jul 12 06:36:12 PM PDT 24 112134462 ps
T308 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.343891342 Jul 12 06:36:20 PM PDT 24 Jul 12 06:36:27 PM PDT 24 504605861 ps
T2791 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1432243157 Jul 12 06:36:28 PM PDT 24 Jul 12 06:36:36 PM PDT 24 1016982726 ps
T2792 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2385815073 Jul 12 06:36:16 PM PDT 24 Jul 12 06:36:18 PM PDT 24 96339247 ps
T2793 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4287270807 Jul 12 06:36:10 PM PDT 24 Jul 12 06:36:13 PM PDT 24 93087672 ps
T2794 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2901122084 Jul 12 06:36:32 PM PDT 24 Jul 12 06:36:34 PM PDT 24 46658647 ps
T2795 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1576559485 Jul 12 06:36:35 PM PDT 24 Jul 12 06:36:37 PM PDT 24 86246898 ps
T2796 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1636678187 Jul 12 06:36:19 PM PDT 24 Jul 12 06:36:26 PM PDT 24 872131945 ps
T2797 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1612867159 Jul 12 06:36:28 PM PDT 24 Jul 12 06:36:32 PM PDT 24 171993685 ps
T2798 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2534717784 Jul 12 06:36:25 PM PDT 24 Jul 12 06:36:29 PM PDT 24 301011827 ps
T2799 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1761782735 Jul 12 06:36:11 PM PDT 24 Jul 12 06:36:13 PM PDT 24 119776256 ps
T2800 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.846745817 Jul 12 06:36:18 PM PDT 24 Jul 12 06:36:20 PM PDT 24 149988408 ps
T2801 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4216037285 Jul 12 06:36:20 PM PDT 24 Jul 12 06:36:25 PM PDT 24 56988130 ps
T2802 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.339891556 Jul 12 06:36:35 PM PDT 24 Jul 12 06:36:38 PM PDT 24 52485260 ps
T2803 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.771098183 Jul 12 06:36:20 PM PDT 24 Jul 12 06:36:28 PM PDT 24 168283761 ps
T2804 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4085210149 Jul 12 06:36:27 PM PDT 24 Jul 12 06:36:33 PM PDT 24 253270109 ps
T2805 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3508108575 Jul 12 06:36:26 PM PDT 24 Jul 12 06:36:30 PM PDT 24 91346201 ps
T2806 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2161049305 Jul 12 06:36:26 PM PDT 24 Jul 12 06:36:29 PM PDT 24 33291062 ps
T2807 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2387645484 Jul 12 06:36:26 PM PDT 24 Jul 12 06:36:29 PM PDT 24 198424478 ps
T2808 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1566466010 Jul 12 06:36:42 PM PDT 24 Jul 12 06:36:45 PM PDT 24 36130717 ps
T2809 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2802822762 Jul 12 06:36:21 PM PDT 24 Jul 12 06:36:30 PM PDT 24 675880196 ps
T2810 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1825003155 Jul 12 06:36:27 PM PDT 24 Jul 12 06:36:30 PM PDT 24 181594778 ps
T306 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2731511601 Jul 12 06:36:24 PM PDT 24 Jul 12 06:36:32 PM PDT 24 1044566630 ps
T2811 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.879476865 Jul 12 06:36:15 PM PDT 24 Jul 12 06:36:18 PM PDT 24 726712110 ps
T2812 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3554195567 Jul 12 06:36:33 PM PDT 24 Jul 12 06:36:36 PM PDT 24 62414720 ps
T2813 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1977647692 Jul 12 06:36:18 PM PDT 24 Jul 12 06:36:21 PM PDT 24 79611606 ps
T2814 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2988428302 Jul 12 06:36:33 PM PDT 24 Jul 12 06:36:36 PM PDT 24 179681549 ps
T2815 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.436892566 Jul 12 06:36:52 PM PDT 24 Jul 12 06:36:57 PM PDT 24 34911890 ps
T2816 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2300751404 Jul 12 06:36:42 PM PDT 24 Jul 12 06:36:44 PM PDT 24 36254926 ps
T2817 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.45771111 Jul 12 06:36:34 PM PDT 24 Jul 12 06:36:38 PM PDT 24 139578832 ps
T2818 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4084034642 Jul 12 06:36:23 PM PDT 24 Jul 12 06:36:28 PM PDT 24 130071316 ps
T2819 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1602978939 Jul 12 06:36:34 PM PDT 24 Jul 12 06:36:36 PM PDT 24 86416103 ps
T2820 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.480417694 Jul 12 06:36:22 PM PDT 24 Jul 12 06:36:26 PM PDT 24 45711589 ps
T2821 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3037153659 Jul 12 06:36:43 PM PDT 24 Jul 12 06:36:45 PM PDT 24 39251306 ps
T2822 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1941758667 Jul 12 06:36:11 PM PDT 24 Jul 12 06:36:12 PM PDT 24 39194357 ps
T2823 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1651284557 Jul 12 06:36:24 PM PDT 24 Jul 12 06:36:27 PM PDT 24 87259408 ps
T2824 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1822622394 Jul 12 06:36:51 PM PDT 24 Jul 12 06:36:55 PM PDT 24 53422095 ps
T2825 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3936513494 Jul 12 06:36:12 PM PDT 24 Jul 12 06:36:14 PM PDT 24 64737079 ps
T2826 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2474049095 Jul 12 06:36:17 PM PDT 24 Jul 12 06:36:18 PM PDT 24 32541523 ps
T2827 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.670373383 Jul 12 06:36:42 PM PDT 24 Jul 12 06:36:45 PM PDT 24 58361713 ps
T2828 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.701704654 Jul 12 06:36:20 PM PDT 24 Jul 12 06:36:25 PM PDT 24 162242333 ps
T2829 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1018140578 Jul 12 06:36:18 PM PDT 24 Jul 12 06:36:21 PM PDT 24 69746008 ps
T2830 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4059420874 Jul 12 06:36:22 PM PDT 24 Jul 12 06:36:27 PM PDT 24 126185810 ps
T2831 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2467029521 Jul 12 06:36:39 PM PDT 24 Jul 12 06:36:41 PM PDT 24 47148388 ps
T2832 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.362964342 Jul 12 06:36:33 PM PDT 24 Jul 12 06:36:37 PM PDT 24 144872582 ps
T2833 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2263076407 Jul 12 06:36:17 PM PDT 24 Jul 12 06:36:20 PM PDT 24 136561243 ps
T2834 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3434450771 Jul 12 06:36:23 PM PDT 24 Jul 12 06:36:30 PM PDT 24 538638131 ps
T2835 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.658774788 Jul 12 06:36:20 PM PDT 24 Jul 12 06:36:24 PM PDT 24 131676587 ps
T2836 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1790194673 Jul 12 06:36:36 PM PDT 24 Jul 12 06:36:39 PM PDT 24 59843614 ps
T2837 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1992090662 Jul 12 06:36:24 PM PDT 24 Jul 12 06:36:28 PM PDT 24 134134072 ps
T2838 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.880469040 Jul 12 06:36:36 PM PDT 24 Jul 12 06:36:40 PM PDT 24 392459419 ps
T2839 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3573852457 Jul 12 06:36:27 PM PDT 24 Jul 12 06:36:30 PM PDT 24 105878140 ps
T2840 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3333484585 Jul 12 06:36:35 PM PDT 24 Jul 12 06:36:38 PM PDT 24 66687619 ps
T2841 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.342910773 Jul 12 06:36:25 PM PDT 24 Jul 12 06:36:29 PM PDT 24 70481247 ps
T2842 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3380065777 Jul 12 06:36:19 PM PDT 24 Jul 12 06:36:21 PM PDT 24 143151826 ps
T2843 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.168162099 Jul 12 06:36:22 PM PDT 24 Jul 12 06:36:27 PM PDT 24 105582196 ps
T2844 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2202872938 Jul 12 06:36:22 PM PDT 24 Jul 12 06:36:26 PM PDT 24 43317314 ps
T2845 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.160403645 Jul 12 06:36:29 PM PDT 24 Jul 12 06:36:36 PM PDT 24 833082571 ps
T2846 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3343023107 Jul 12 06:36:28 PM PDT 24 Jul 12 06:36:31 PM PDT 24 34623324 ps
T2847 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2946639582 Jul 12 06:36:24 PM PDT 24 Jul 12 06:36:27 PM PDT 24 259164009 ps
T2848 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3118377717 Jul 12 06:36:23 PM PDT 24 Jul 12 06:36:27 PM PDT 24 35906242 ps
T2849 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2056222297 Jul 12 06:36:20 PM PDT 24 Jul 12 06:36:26 PM PDT 24 65207186 ps
T2850 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3875484255 Jul 12 06:36:20 PM PDT 24 Jul 12 06:36:26 PM PDT 24 956363433 ps
T2851 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2566729962 Jul 12 06:36:45 PM PDT 24 Jul 12 06:36:48 PM PDT 24 57033052 ps
T2852 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.705301259 Jul 12 06:36:20 PM PDT 24 Jul 12 06:36:24 PM PDT 24 37625940 ps
T2853 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4231413346 Jul 12 06:36:37 PM PDT 24 Jul 12 06:36:40 PM PDT 24 41897694 ps

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.938505276
Short name T3
Test name
Test status
Simulation time 3932647312 ps
CPU time 38.43 seconds
Started Jul 12 05:26:30 PM PDT 24
Finished Jul 12 05:27:10 PM PDT 24
Peak memory 207024 kb
Host smart-030f9fd1-0633-4a66-9523-60fe5241e8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93850
5276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.938505276
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2844074634
Short name T284
Test name
Test status
Simulation time 57258660 ps
CPU time 0.71 seconds
Started Jul 12 06:36:43 PM PDT 24
Finished Jul 12 06:36:46 PM PDT 24
Peak memory 206320 kb
Host smart-46faf0c1-6820-4a1a-a06d-541eb75e29ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2844074634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2844074634
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2653249971
Short name T77
Test name
Test status
Simulation time 183420839 ps
CPU time 0.85 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 207020 kb
Host smart-19ca9a9f-c66b-403f-ac63-cf3423be5ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26532
49971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2653249971
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2551297726
Short name T6
Test name
Test status
Simulation time 3794324153 ps
CPU time 4.86 seconds
Started Jul 12 05:30:21 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 207180 kb
Host smart-fb8304a8-d84f-4b97-8ed6-e32d6185a4ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2551297726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2551297726
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2884317312
Short name T93
Test name
Test status
Simulation time 14418984593 ps
CPU time 24.88 seconds
Started Jul 12 05:27:14 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 207016 kb
Host smart-4e961935-9e45-444f-aec2-a4548a4e33a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28843
17312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2884317312
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.545998586
Short name T195
Test name
Test status
Simulation time 1121283890 ps
CPU time 4.86 seconds
Started Jul 12 06:36:17 PM PDT 24
Finished Jul 12 06:36:23 PM PDT 24
Peak memory 206576 kb
Host smart-4656eb20-b8e4-4221-95a1-3d4b8d350a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=545998586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.545998586
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2255907188
Short name T85
Test name
Test status
Simulation time 183460461 ps
CPU time 0.84 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206616 kb
Host smart-4d2f7f86-8c2d-4bac-919c-6f24ead82506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22559
07188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2255907188
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1016414017
Short name T283
Test name
Test status
Simulation time 39074797 ps
CPU time 0.69 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 206292 kb
Host smart-626d406a-4084-4288-b30a-7448bb32f42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1016414017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1016414017
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1855000566
Short name T190
Test name
Test status
Simulation time 1701064818 ps
CPU time 2.61 seconds
Started Jul 12 05:26:38 PM PDT 24
Finished Jul 12 05:26:43 PM PDT 24
Peak memory 225468 kb
Host smart-793711be-c38f-431d-b8cc-33c2f88e5931
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1855000566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1855000566
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1785333103
Short name T31
Test name
Test status
Simulation time 140046928 ps
CPU time 0.76 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:32:37 PM PDT 24
Peak memory 206692 kb
Host smart-d97f78d3-840c-41dd-8efd-a42a3609e8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
33103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1785333103
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3421757980
Short name T103
Test name
Test status
Simulation time 438826654 ps
CPU time 1.63 seconds
Started Jul 12 05:32:22 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 206828 kb
Host smart-5e23fd6c-3a62-4c8c-8064-342514e79acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34217
57980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3421757980
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3150777284
Short name T15
Test name
Test status
Simulation time 13489482636 ps
CPU time 14.16 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 206928 kb
Host smart-d33700e8-ecc5-40b4-8ce7-eb84a5b66dab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3150777284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3150777284
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3817281738
Short name T220
Test name
Test status
Simulation time 288046538 ps
CPU time 3.23 seconds
Started Jul 12 06:36:27 PM PDT 24
Finished Jul 12 06:36:33 PM PDT 24
Peak memory 206728 kb
Host smart-b9cc61d9-dc37-4c30-ab5c-1540a684cde4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3817281738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3817281738
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.361441570
Short name T109
Test name
Test status
Simulation time 168774937 ps
CPU time 0.8 seconds
Started Jul 12 05:33:30 PM PDT 24
Finished Jul 12 05:33:38 PM PDT 24
Peak memory 206716 kb
Host smart-bb038b4f-3650-4e80-a5b2-f3fe30acb65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
1570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.361441570
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2697772099
Short name T28
Test name
Test status
Simulation time 48122233 ps
CPU time 0.68 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:28:49 PM PDT 24
Peak memory 206812 kb
Host smart-408b245b-80e7-4a20-88e8-d9eb0066fd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26977
72099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2697772099
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2683431569
Short name T68
Test name
Test status
Simulation time 187239593 ps
CPU time 0.87 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206808 kb
Host smart-cccb5cab-bfb4-480a-b78b-4ffbffd99dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26834
31569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2683431569
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2483098619
Short name T298
Test name
Test status
Simulation time 41764155 ps
CPU time 0.7 seconds
Started Jul 12 06:36:43 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 206296 kb
Host smart-1e332e99-901f-4abe-89cc-d2d4ec172ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2483098619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2483098619
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3321133470
Short name T75
Test name
Test status
Simulation time 301467238 ps
CPU time 1.04 seconds
Started Jul 12 05:26:04 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 206716 kb
Host smart-43c8f8d4-0de3-4a46-bf33-28d72b812b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33211
33470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3321133470
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/22.usbdev_device_address.100173458
Short name T21
Test name
Test status
Simulation time 7258213625 ps
CPU time 15.26 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:30:07 PM PDT 24
Peak memory 207088 kb
Host smart-4a9d9747-3d5a-4e05-b937-ce9ad380b927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10017
3458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.100173458
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.284793743
Short name T38
Test name
Test status
Simulation time 17125406829 ps
CPU time 125.51 seconds
Started Jul 12 05:26:11 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 207068 kb
Host smart-742ce70c-6c40-4df7-96f0-5f34fb6b6d0b
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=284793743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.284793743
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3277741206
Short name T40
Test name
Test status
Simulation time 20174512291 ps
CPU time 23.75 seconds
Started Jul 12 05:26:03 PM PDT 24
Finished Jul 12 05:26:28 PM PDT 24
Peak memory 206872 kb
Host smart-fa275a56-d8fc-4144-889a-15444ed70085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32777
41206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3277741206
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3055656187
Short name T260
Test name
Test status
Simulation time 44419779 ps
CPU time 0.95 seconds
Started Jul 12 06:36:08 PM PDT 24
Finished Jul 12 06:36:09 PM PDT 24
Peak memory 206520 kb
Host smart-33dd9e11-8ca1-4875-af99-3e98e4845a6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3055656187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3055656187
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2158573403
Short name T70
Test name
Test status
Simulation time 202437910 ps
CPU time 0.86 seconds
Started Jul 12 05:26:13 PM PDT 24
Finished Jul 12 05:26:15 PM PDT 24
Peak memory 206776 kb
Host smart-b8fddbcb-fae9-465f-a392-e6035a3f588d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21585
73403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2158573403
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3992108525
Short name T2783
Test name
Test status
Simulation time 72210939 ps
CPU time 0.72 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:35 PM PDT 24
Peak memory 206264 kb
Host smart-20697a9b-e6a5-4cdd-983e-38dcc51331ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3992108525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3992108525
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3802264629
Short name T101
Test name
Test status
Simulation time 1167806269 ps
CPU time 2.69 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 206796 kb
Host smart-c97395dc-03ed-4985-84c9-cc6e41897629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38022
64629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3802264629
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2731511601
Short name T306
Test name
Test status
Simulation time 1044566630 ps
CPU time 5.27 seconds
Started Jul 12 06:36:24 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 206484 kb
Host smart-ed6c4d21-a868-40a3-87a7-05f762304881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2731511601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2731511601
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1842789463
Short name T291
Test name
Test status
Simulation time 171659637 ps
CPU time 0.84 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:07 PM PDT 24
Peak memory 207036 kb
Host smart-9e7c1d57-3aec-440c-a15e-e11f78ee1c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
89463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1842789463
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2229370918
Short name T170
Test name
Test status
Simulation time 8874364337 ps
CPU time 62.09 seconds
Started Jul 12 05:26:03 PM PDT 24
Finished Jul 12 05:27:06 PM PDT 24
Peak memory 206908 kb
Host smart-cc122966-9b3e-4623-ae8e-c3919953c192
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2229370918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2229370918
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3721969562
Short name T149
Test name
Test status
Simulation time 191847352 ps
CPU time 0.87 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206804 kb
Host smart-8b63d305-2f75-49d0-8a67-5594efc97ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37219
69562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3721969562
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.4252065209
Short name T66
Test name
Test status
Simulation time 590176475 ps
CPU time 1.42 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:00 PM PDT 24
Peak memory 206796 kb
Host smart-6402d364-18da-44d4-8b19-9df216d57273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42520
65209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.4252065209
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1898369168
Short name T300
Test name
Test status
Simulation time 1327808883 ps
CPU time 5.65 seconds
Started Jul 12 06:36:17 PM PDT 24
Finished Jul 12 06:36:24 PM PDT 24
Peak memory 206504 kb
Host smart-2bee9c18-e20b-431e-8863-ae726c2e87d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1898369168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1898369168
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.1934948777
Short name T71
Test name
Test status
Simulation time 8203714460 ps
CPU time 227.96 seconds
Started Jul 12 05:28:37 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 207012 kb
Host smart-b20776e7-3130-423b-8bf2-f496d29ee51b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1934948777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1934948777
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2320080841
Short name T182
Test name
Test status
Simulation time 39138792 ps
CPU time 0.69 seconds
Started Jul 12 05:28:55 PM PDT 24
Finished Jul 12 05:28:57 PM PDT 24
Peak memory 206848 kb
Host smart-e24139e9-974b-44a4-9fc3-53e73bb43b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2320080841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2320080841
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3287574781
Short name T143
Test name
Test status
Simulation time 855017875 ps
CPU time 2.07 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:01 PM PDT 24
Peak memory 206836 kb
Host smart-d2fa5c93-bd73-4769-8a7b-59f9144982d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32875
74781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3287574781
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2788617975
Short name T228
Test name
Test status
Simulation time 119756437 ps
CPU time 3.16 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:38 PM PDT 24
Peak memory 214728 kb
Host smart-b93f834c-67ab-4941-9211-231e19803244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2788617975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2788617975
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.4115476108
Short name T155
Test name
Test status
Simulation time 5028201345 ps
CPU time 130.28 seconds
Started Jul 12 05:27:19 PM PDT 24
Finished Jul 12 05:29:31 PM PDT 24
Peak memory 206936 kb
Host smart-87b8e1e8-dc03-458c-a176-7aa92ee274fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4115476108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.4115476108
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2019815141
Short name T50
Test name
Test status
Simulation time 252936206 ps
CPU time 0.97 seconds
Started Jul 12 05:26:09 PM PDT 24
Finished Jul 12 05:26:12 PM PDT 24
Peak memory 206820 kb
Host smart-fe8e83be-1174-454f-9f7c-e2e05de0b70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20198
15141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2019815141
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.936736232
Short name T59
Test name
Test status
Simulation time 206858283 ps
CPU time 0.83 seconds
Started Jul 12 05:25:52 PM PDT 24
Finished Jul 12 05:25:54 PM PDT 24
Peak memory 206800 kb
Host smart-7a107e95-98b0-496e-a7bc-5fa63afeef04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93673
6232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.936736232
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2281109002
Short name T147
Test name
Test status
Simulation time 6877092070 ps
CPU time 60.31 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:34:06 PM PDT 24
Peak memory 207080 kb
Host smart-6041ece6-8d93-4ad4-84bc-a968dc375230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
09002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2281109002
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.723698317
Short name T2758
Test name
Test status
Simulation time 46177628 ps
CPU time 0.75 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:12 PM PDT 24
Peak memory 206300 kb
Host smart-bbbb2ae8-771e-46e0-8b5c-333bf81cff7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=723698317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.723698317
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1768358196
Short name T307
Test name
Test status
Simulation time 1309011045 ps
CPU time 6.13 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 206600 kb
Host smart-4dc0b48e-4d1b-48ec-9a1e-8300f3a8894e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1768358196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1768358196
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2398518964
Short name T189
Test name
Test status
Simulation time 219322892 ps
CPU time 0.84 seconds
Started Jul 12 05:26:18 PM PDT 24
Finished Jul 12 05:26:21 PM PDT 24
Peak memory 206764 kb
Host smart-e731f5c5-37f0-41f0-aa67-7b6f8496badf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23985
18964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2398518964
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.835927660
Short name T2156
Test name
Test status
Simulation time 4050337272 ps
CPU time 4.67 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:22 PM PDT 24
Peak memory 206760 kb
Host smart-50163115-1fdb-4e89-bf2c-f532aa804188
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=835927660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.835927660
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2832270277
Short name T181
Test name
Test status
Simulation time 275356834 ps
CPU time 1.88 seconds
Started Jul 12 05:25:55 PM PDT 24
Finished Jul 12 05:25:58 PM PDT 24
Peak memory 206832 kb
Host smart-428f7a63-14e8-4077-a1ac-dcf42b1b6544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28322
70277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2832270277
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.129465827
Short name T60
Test name
Test status
Simulation time 140929250 ps
CPU time 0.78 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:26:47 PM PDT 24
Peak memory 206752 kb
Host smart-e2326372-e0c2-43f3-888d-15aab5993852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12946
5827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.129465827
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.135959165
Short name T163
Test name
Test status
Simulation time 5615149816 ps
CPU time 44.98 seconds
Started Jul 12 05:26:17 PM PDT 24
Finished Jul 12 05:27:04 PM PDT 24
Peak memory 207064 kb
Host smart-be78847f-33ac-46d6-b0e2-886b69a042e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=135959165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.135959165
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.4214651192
Short name T51
Test name
Test status
Simulation time 156914840 ps
CPU time 0.84 seconds
Started Jul 12 05:25:56 PM PDT 24
Finished Jul 12 05:25:58 PM PDT 24
Peak memory 206720 kb
Host smart-5c6793e7-2510-4697-9a6a-ec6ffc1388fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146
51192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.4214651192
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.557619806
Short name T61
Test name
Test status
Simulation time 4169180681 ps
CPU time 10.35 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:09 PM PDT 24
Peak memory 207016 kb
Host smart-b9c901cd-810f-4b50-a3e4-23a218d0bcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55761
9806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.557619806
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1212649726
Short name T62
Test name
Test status
Simulation time 184780636 ps
CPU time 0.83 seconds
Started Jul 12 05:25:56 PM PDT 24
Finished Jul 12 05:25:58 PM PDT 24
Peak memory 206808 kb
Host smart-22bee1f9-3ecd-4005-a8d1-c8a5a1c96345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12126
49726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1212649726
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3853910454
Short name T73
Test name
Test status
Simulation time 185266189 ps
CPU time 0.79 seconds
Started Jul 12 05:26:05 PM PDT 24
Finished Jul 12 05:26:07 PM PDT 24
Peak memory 206688 kb
Host smart-e0b3d832-bfed-4cc0-8525-a4baad9e09ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38539
10454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3853910454
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2144707643
Short name T90
Test name
Test status
Simulation time 8598604838 ps
CPU time 81.5 seconds
Started Jul 12 05:28:25 PM PDT 24
Finished Jul 12 05:29:49 PM PDT 24
Peak memory 206972 kb
Host smart-a0aaa582-ca6f-4daa-994b-07445549b37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21447
07643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2144707643
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.4292208218
Short name T29
Test name
Test status
Simulation time 83070021 ps
CPU time 0.7 seconds
Started Jul 12 05:28:54 PM PDT 24
Finished Jul 12 05:28:56 PM PDT 24
Peak memory 206804 kb
Host smart-3a8732ce-ffa2-4c54-bd62-5645ffad6fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42922
08218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.4292208218
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1413272846
Short name T45
Test name
Test status
Simulation time 183873896 ps
CPU time 0.85 seconds
Started Jul 12 05:26:21 PM PDT 24
Finished Jul 12 05:26:23 PM PDT 24
Peak memory 206816 kb
Host smart-a805fa48-fbc4-491b-821e-62fbea45fec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14132
72846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1413272846
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2255792873
Short name T158
Test name
Test status
Simulation time 13689532634 ps
CPU time 281.37 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:31:46 PM PDT 24
Peak memory 207076 kb
Host smart-a8752162-9e9e-4593-ab77-f41035f57978
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2255792873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2255792873
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4009217433
Short name T219
Test name
Test status
Simulation time 177645529 ps
CPU time 2.05 seconds
Started Jul 12 06:36:05 PM PDT 24
Finished Jul 12 06:36:08 PM PDT 24
Peak memory 222352 kb
Host smart-7ee0d669-1c6f-4e49-8ed4-23b8a2d36272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4009217433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.4009217433
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3973942845
Short name T193
Test name
Test status
Simulation time 1065184692 ps
CPU time 4.86 seconds
Started Jul 12 06:36:25 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 206508 kb
Host smart-681c1230-0804-4f08-bdd7-420ef79cf505
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3973942845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3973942845
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2719635515
Short name T18
Test name
Test status
Simulation time 228983840 ps
CPU time 0.91 seconds
Started Jul 12 05:26:03 PM PDT 24
Finished Jul 12 05:26:04 PM PDT 24
Peak memory 206804 kb
Host smart-b9ebb87c-6d21-42b0-a7ec-6d424a61635a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27196
35515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2719635515
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.103983040
Short name T49
Test name
Test status
Simulation time 409333289 ps
CPU time 1.32 seconds
Started Jul 12 05:26:09 PM PDT 24
Finished Jul 12 05:26:12 PM PDT 24
Peak memory 206812 kb
Host smart-388aff29-1dd4-4185-8c42-5df7f0d38c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
3040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.103983040
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.828644568
Short name T128
Test name
Test status
Simulation time 245088898 ps
CPU time 0.89 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:26:21 PM PDT 24
Peak memory 206820 kb
Host smart-586a78db-8493-416f-bdc1-80a538a02f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82864
4568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.828644568
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1703246904
Short name T120
Test name
Test status
Simulation time 231334870 ps
CPU time 0.84 seconds
Started Jul 12 05:28:06 PM PDT 24
Finished Jul 12 05:28:09 PM PDT 24
Peak memory 206808 kb
Host smart-b53c6b33-8ba4-46db-b888-ba57daa23b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17032
46904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1703246904
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2730391882
Short name T123
Test name
Test status
Simulation time 224354408 ps
CPU time 0.89 seconds
Started Jul 12 05:28:17 PM PDT 24
Finished Jul 12 05:28:20 PM PDT 24
Peak memory 206828 kb
Host smart-e256e734-8567-4799-8874-f10cda576cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27303
91882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2730391882
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2907238442
Short name T134
Test name
Test status
Simulation time 209817407 ps
CPU time 0.88 seconds
Started Jul 12 05:28:28 PM PDT 24
Finished Jul 12 05:28:32 PM PDT 24
Peak memory 206812 kb
Host smart-68044156-af21-4914-90d1-b63182a4ac38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29072
38442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2907238442
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1350955656
Short name T2509
Test name
Test status
Simulation time 221184848 ps
CPU time 0.9 seconds
Started Jul 12 05:28:38 PM PDT 24
Finished Jul 12 05:28:41 PM PDT 24
Peak memory 206696 kb
Host smart-50a36479-8b3e-439c-b210-4ffa33cdc02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13509
55656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1350955656
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1579937464
Short name T113
Test name
Test status
Simulation time 188885552 ps
CPU time 0.84 seconds
Started Jul 12 05:28:50 PM PDT 24
Finished Jul 12 05:28:52 PM PDT 24
Peak memory 206800 kb
Host smart-95ee7bc6-11cb-4d39-b1bd-743beac16055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15799
37464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1579937464
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.1971373764
Short name T582
Test name
Test status
Simulation time 5816097903 ps
CPU time 45.97 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:46 PM PDT 24
Peak memory 207080 kb
Host smart-0cb4f4e9-50ab-4af1-bdcf-a5aa6b5f503a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19713
73764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.1971373764
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1925818148
Short name T135
Test name
Test status
Simulation time 212518249 ps
CPU time 0.84 seconds
Started Jul 12 05:29:12 PM PDT 24
Finished Jul 12 05:29:15 PM PDT 24
Peak memory 206808 kb
Host smart-2102b69f-d2b3-44bb-a467-09a742cd7c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19258
18148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1925818148
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2445837979
Short name T138
Test name
Test status
Simulation time 225030434 ps
CPU time 0.91 seconds
Started Jul 12 05:26:27 PM PDT 24
Finished Jul 12 05:26:30 PM PDT 24
Peak memory 206796 kb
Host smart-ba699de5-ddd0-47da-970d-13cdac3f46eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24458
37979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2445837979
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.644619424
Short name T126
Test name
Test status
Simulation time 198138049 ps
CPU time 0.81 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:29:59 PM PDT 24
Peak memory 206712 kb
Host smart-a8f6d151-9257-41a4-85b6-7c87fab95a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64461
9424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.644619424
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1332108792
Short name T118
Test name
Test status
Simulation time 252319099 ps
CPU time 0.86 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:06 PM PDT 24
Peak memory 206632 kb
Host smart-6021fac1-f7da-4e77-8801-5ccae99ff2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13321
08792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1332108792
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.2842882066
Short name T106
Test name
Test status
Simulation time 6345253400 ps
CPU time 173.43 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 207008 kb
Host smart-0fdbfbcc-b553-4792-9214-4017e46756bf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2842882066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.2842882066
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2933541148
Short name T159
Test name
Test status
Simulation time 16091549766 ps
CPU time 105.62 seconds
Started Jul 12 05:27:05 PM PDT 24
Finished Jul 12 05:28:52 PM PDT 24
Peak memory 206984 kb
Host smart-8eff2597-639f-461b-80fd-485b55ba3fb3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2933541148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2933541148
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1898476077
Short name T213
Test name
Test status
Simulation time 217736127 ps
CPU time 2.23 seconds
Started Jul 12 06:36:11 PM PDT 24
Finished Jul 12 06:36:15 PM PDT 24
Peak memory 206416 kb
Host smart-0852d7ab-c395-468c-8674-3cfc3957a01b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1898476077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1898476077
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1110578598
Short name T261
Test name
Test status
Simulation time 1769940297 ps
CPU time 11.4 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:22 PM PDT 24
Peak memory 206404 kb
Host smart-e4434d8a-7bf4-4046-82a0-54213b86b648
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1110578598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1110578598
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.57857848
Short name T2777
Test name
Test status
Simulation time 177622487 ps
CPU time 1.09 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:12 PM PDT 24
Peak memory 206316 kb
Host smart-b9738f04-75b4-4dfe-adf0-a60b46854449
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=57857848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.57857848
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3980414722
Short name T2768
Test name
Test status
Simulation time 143202169 ps
CPU time 1.78 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:12 PM PDT 24
Peak memory 214736 kb
Host smart-93b376a5-be8d-47bb-82c9-32f9891b23d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980414722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3980414722
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1941758667
Short name T2822
Test name
Test status
Simulation time 39194357 ps
CPU time 0.69 seconds
Started Jul 12 06:36:11 PM PDT 24
Finished Jul 12 06:36:12 PM PDT 24
Peak memory 206280 kb
Host smart-4c8f5cdc-8a41-454b-ac39-7f2804a1cefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1941758667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1941758667
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2493180637
Short name T266
Test name
Test status
Simulation time 206596176 ps
CPU time 2.47 seconds
Started Jul 12 06:36:11 PM PDT 24
Finished Jul 12 06:36:15 PM PDT 24
Peak memory 214756 kb
Host smart-68da72d4-f627-4728-9cde-376abb170c1a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2493180637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2493180637
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1201039762
Short name T2751
Test name
Test status
Simulation time 159632184 ps
CPU time 2.41 seconds
Started Jul 12 06:36:12 PM PDT 24
Finished Jul 12 06:36:15 PM PDT 24
Peak memory 206412 kb
Host smart-dfa53902-1083-46be-8e78-2363e1f2e581
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1201039762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1201039762
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4123974497
Short name T270
Test name
Test status
Simulation time 190774255 ps
CPU time 1.47 seconds
Started Jul 12 06:36:08 PM PDT 24
Finished Jul 12 06:36:10 PM PDT 24
Peak memory 206480 kb
Host smart-e406ca8c-1cd7-4057-a993-b49f562fd1b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4123974497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.4123974497
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.879476865
Short name T2811
Test name
Test status
Simulation time 726712110 ps
CPU time 2.8 seconds
Started Jul 12 06:36:15 PM PDT 24
Finished Jul 12 06:36:18 PM PDT 24
Peak memory 206512 kb
Host smart-f0fb76c1-e288-46e8-85f9-899107f9e61f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=879476865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.879476865
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2150288733
Short name T2752
Test name
Test status
Simulation time 330014428 ps
CPU time 3.44 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:14 PM PDT 24
Peak memory 206404 kb
Host smart-da2c4855-e24d-47e0-a119-42b44df54830
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2150288733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2150288733
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3365755786
Short name T257
Test name
Test status
Simulation time 527175653 ps
CPU time 4.55 seconds
Started Jul 12 06:36:15 PM PDT 24
Finished Jul 12 06:36:20 PM PDT 24
Peak memory 206444 kb
Host smart-594205f7-defa-42d6-876e-8e51b30310f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3365755786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3365755786
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3000105782
Short name T2753
Test name
Test status
Simulation time 75257302 ps
CPU time 0.82 seconds
Started Jul 12 06:36:11 PM PDT 24
Finished Jul 12 06:36:13 PM PDT 24
Peak memory 206336 kb
Host smart-754ac0c7-f0f5-49cd-bf9d-05f5fc5f6a1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3000105782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3000105782
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1761782735
Short name T2799
Test name
Test status
Simulation time 119776256 ps
CPU time 1.38 seconds
Started Jul 12 06:36:11 PM PDT 24
Finished Jul 12 06:36:13 PM PDT 24
Peak memory 214724 kb
Host smart-84f4bf1c-0fa8-4c4f-ad0a-b7fde8c43796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761782735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1761782735
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3936513494
Short name T2825
Test name
Test status
Simulation time 64737079 ps
CPU time 0.98 seconds
Started Jul 12 06:36:12 PM PDT 24
Finished Jul 12 06:36:14 PM PDT 24
Peak memory 206424 kb
Host smart-f713c095-b2fd-40b9-af44-316c4a282ffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3936513494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3936513494
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2036671408
Short name T2790
Test name
Test status
Simulation time 112134462 ps
CPU time 1.52 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:12 PM PDT 24
Peak memory 222856 kb
Host smart-9c9f3093-bf2b-4a14-ad62-cbd257202eaf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2036671408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2036671408
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2491670673
Short name T2770
Test name
Test status
Simulation time 165486158 ps
CPU time 3.84 seconds
Started Jul 12 06:36:11 PM PDT 24
Finished Jul 12 06:36:16 PM PDT 24
Peak memory 206400 kb
Host smart-ae4e546f-863f-4eda-9d6f-1404f848acde
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2491670673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2491670673
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2418947028
Short name T2766
Test name
Test status
Simulation time 187275869 ps
CPU time 1.66 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:12 PM PDT 24
Peak memory 206432 kb
Host smart-7cb2dc00-8b06-43ae-b5ed-b8ddcd216a53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2418947028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2418947028
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4287270807
Short name T2793
Test name
Test status
Simulation time 93087672 ps
CPU time 2.46 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:13 PM PDT 24
Peak memory 222764 kb
Host smart-e77961a5-ee33-41e4-93b1-2607575507d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4287270807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4287270807
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3943062508
Short name T282
Test name
Test status
Simulation time 1044051061 ps
CPU time 5.53 seconds
Started Jul 12 06:36:10 PM PDT 24
Finished Jul 12 06:36:16 PM PDT 24
Peak memory 206480 kb
Host smart-2c6ae2a1-8835-471e-aa12-314392c8a0be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3943062508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3943062508
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1569966212
Short name T2778
Test name
Test status
Simulation time 178765430 ps
CPU time 1.97 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:40 PM PDT 24
Peak memory 214800 kb
Host smart-f0fb02db-64b7-482a-aa33-72d85ff1728f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569966212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1569966212
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1598098835
Short name T2786
Test name
Test status
Simulation time 44146685 ps
CPU time 0.87 seconds
Started Jul 12 06:36:25 PM PDT 24
Finished Jul 12 06:36:28 PM PDT 24
Peak memory 206348 kb
Host smart-95b81892-3bd6-447b-84bc-cfe66a22d90b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1598098835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1598098835
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2142983325
Short name T2759
Test name
Test status
Simulation time 70980276 ps
CPU time 0.71 seconds
Started Jul 12 06:36:27 PM PDT 24
Finished Jul 12 06:36:30 PM PDT 24
Peak memory 206344 kb
Host smart-ac593279-a48f-4df8-9fe0-3bc511b92d5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2142983325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2142983325
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2988428302
Short name T2814
Test name
Test status
Simulation time 179681549 ps
CPU time 1.67 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:36 PM PDT 24
Peak memory 206472 kb
Host smart-81c0eeae-f334-4ef5-a006-2efcb530c3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2988428302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2988428302
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.256155091
Short name T305
Test name
Test status
Simulation time 1401838440 ps
CPU time 4.94 seconds
Started Jul 12 06:36:27 PM PDT 24
Finished Jul 12 06:36:34 PM PDT 24
Peak memory 206560 kb
Host smart-e4c48e4c-0c9c-4954-9525-01c4a5ad7f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=256155091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.256155091
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1817608532
Short name T232
Test name
Test status
Simulation time 91502078 ps
CPU time 1.24 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:36 PM PDT 24
Peak memory 222828 kb
Host smart-216b998b-998c-49d4-b03a-7f148b9c2091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817608532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1817608532
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3573852457
Short name T2839
Test name
Test status
Simulation time 105878140 ps
CPU time 0.93 seconds
Started Jul 12 06:36:27 PM PDT 24
Finished Jul 12 06:36:30 PM PDT 24
Peak memory 206340 kb
Host smart-911c89b5-112d-4984-b11e-e974d0ea0b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3573852457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3573852457
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3343023107
Short name T2846
Test name
Test status
Simulation time 34623324 ps
CPU time 0.68 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:31 PM PDT 24
Peak memory 206260 kb
Host smart-f5c2c4bd-6970-4a35-a83e-b35c25be4b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3343023107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3343023107
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3263963768
Short name T271
Test name
Test status
Simulation time 132776597 ps
CPU time 1.51 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 206580 kb
Host smart-97475a8d-4028-45e3-8cdc-f1525bf59cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3263963768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3263963768
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2231215561
Short name T2773
Test name
Test status
Simulation time 112076506 ps
CPU time 2.93 seconds
Started Jul 12 06:36:24 PM PDT 24
Finished Jul 12 06:36:30 PM PDT 24
Peak memory 222648 kb
Host smart-f2c0ce8e-0d98-44e4-8a16-310c9b2635ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2231215561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2231215561
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2387645484
Short name T2807
Test name
Test status
Simulation time 198424478 ps
CPU time 1.3 seconds
Started Jul 12 06:36:26 PM PDT 24
Finished Jul 12 06:36:29 PM PDT 24
Peak memory 214684 kb
Host smart-04e0c420-09c5-4fa3-9c9a-c77b9b60dbd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387645484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2387645484
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3430054122
Short name T268
Test name
Test status
Simulation time 76593557 ps
CPU time 1.01 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:36 PM PDT 24
Peak memory 206396 kb
Host smart-b8208fd3-9dcc-4ca9-bafc-8587ff71df9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3430054122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3430054122
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4118847175
Short name T289
Test name
Test status
Simulation time 42479198 ps
CPU time 0.64 seconds
Started Jul 12 06:36:32 PM PDT 24
Finished Jul 12 06:36:33 PM PDT 24
Peak memory 206260 kb
Host smart-c28f7dc1-0dde-4c3a-b440-21510bad9075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4118847175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.4118847175
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.342910773
Short name T2841
Test name
Test status
Simulation time 70481247 ps
CPU time 1.21 seconds
Started Jul 12 06:36:25 PM PDT 24
Finished Jul 12 06:36:29 PM PDT 24
Peak memory 206460 kb
Host smart-4550c6e6-58d6-4ef0-a521-4fa9211fca75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=342910773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.342910773
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1992090662
Short name T2837
Test name
Test status
Simulation time 134134072 ps
CPU time 1.56 seconds
Started Jul 12 06:36:24 PM PDT 24
Finished Jul 12 06:36:28 PM PDT 24
Peak memory 206616 kb
Host smart-d7f51c8d-089d-444f-b5b7-6192be459e56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1992090662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1992090662
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2647567733
Short name T303
Test name
Test status
Simulation time 855422060 ps
CPU time 3.58 seconds
Started Jul 12 06:36:29 PM PDT 24
Finished Jul 12 06:36:35 PM PDT 24
Peak memory 206532 kb
Host smart-b0ec04f8-bebf-4240-8721-8c1bc8616db9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2647567733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2647567733
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3508108575
Short name T2805
Test name
Test status
Simulation time 91346201 ps
CPU time 1.28 seconds
Started Jul 12 06:36:26 PM PDT 24
Finished Jul 12 06:36:30 PM PDT 24
Peak memory 214792 kb
Host smart-c456c027-8712-43dd-8d2a-79820f426602
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508108575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3508108575
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4187162951
Short name T2757
Test name
Test status
Simulation time 56887362 ps
CPU time 0.85 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:31 PM PDT 24
Peak memory 206340 kb
Host smart-0d073202-064e-4613-82ae-85c2eadff185
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4187162951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.4187162951
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1221315612
Short name T293
Test name
Test status
Simulation time 43391574 ps
CPU time 0.69 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:35 PM PDT 24
Peak memory 206260 kb
Host smart-a7b2a23a-eb48-4c55-8bc2-5ca9a8e24ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1221315612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1221315612
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3647028081
Short name T2755
Test name
Test status
Simulation time 65179105 ps
CPU time 1.05 seconds
Started Jul 12 06:36:23 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206552 kb
Host smart-0a027e31-4433-4953-9d43-c03e49bcf190
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3647028081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3647028081
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4085210149
Short name T2804
Test name
Test status
Simulation time 253270109 ps
CPU time 3.23 seconds
Started Jul 12 06:36:27 PM PDT 24
Finished Jul 12 06:36:33 PM PDT 24
Peak memory 214772 kb
Host smart-aa675b62-08f3-4e00-b473-c21cc523f4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4085210149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4085210149
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.160403645
Short name T2845
Test name
Test status
Simulation time 833082571 ps
CPU time 4.79 seconds
Started Jul 12 06:36:29 PM PDT 24
Finished Jul 12 06:36:36 PM PDT 24
Peak memory 206516 kb
Host smart-786e6183-2de0-4164-ac42-9d1615346ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=160403645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.160403645
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2321534029
Short name T239
Test name
Test status
Simulation time 82085687 ps
CPU time 1.66 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 214812 kb
Host smart-3e8b043a-4f40-4f05-86ae-aa7d832f939f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321534029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2321534029
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4191680836
Short name T2771
Test name
Test status
Simulation time 86184719 ps
CPU time 1.07 seconds
Started Jul 12 06:36:24 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206416 kb
Host smart-52d994d7-f28c-4623-8f13-f67082ff71b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4191680836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4191680836
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1969921542
Short name T2763
Test name
Test status
Simulation time 146433840 ps
CPU time 1.26 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 206584 kb
Host smart-cf8e77d6-2e46-41f3-8598-6b887792622a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1969921542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1969921542
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4186078729
Short name T229
Test name
Test status
Simulation time 261382324 ps
CPU time 2.65 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:33 PM PDT 24
Peak memory 222848 kb
Host smart-ad0d912a-12a4-4368-b223-f54271cb1bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4186078729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4186078729
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3971351772
Short name T2772
Test name
Test status
Simulation time 462296895 ps
CPU time 2.77 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:34 PM PDT 24
Peak memory 206580 kb
Host smart-981eb850-2f0e-49e4-9ef9-a64f4e6e7e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3971351772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3971351772
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3738127337
Short name T218
Test name
Test status
Simulation time 91558458 ps
CPU time 1.93 seconds
Started Jul 12 06:36:26 PM PDT 24
Finished Jul 12 06:36:31 PM PDT 24
Peak memory 214740 kb
Host smart-9bca429d-3f9d-416c-99ad-73a3fbf1fa5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738127337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3738127337
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1625100775
Short name T267
Test name
Test status
Simulation time 60346345 ps
CPU time 1.01 seconds
Started Jul 12 06:36:32 PM PDT 24
Finished Jul 12 06:36:34 PM PDT 24
Peak memory 206420 kb
Host smart-3afc024e-8253-4237-87d6-a5a13a3b1f74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1625100775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1625100775
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3118377717
Short name T2848
Test name
Test status
Simulation time 35906242 ps
CPU time 0.66 seconds
Started Jul 12 06:36:23 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206288 kb
Host smart-34259011-54fd-42da-a1c2-edd422f203b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3118377717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3118377717
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1612867159
Short name T2797
Test name
Test status
Simulation time 171993685 ps
CPU time 1.28 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 206488 kb
Host smart-27c0988e-68e3-49b9-af4e-657551a27585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1612867159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1612867159
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2717089823
Short name T2779
Test name
Test status
Simulation time 285518029 ps
CPU time 3.4 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:38 PM PDT 24
Peak memory 222216 kb
Host smart-6dd3dee5-ade8-44c4-929f-412240a59691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2717089823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2717089823
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1432243157
Short name T2791
Test name
Test status
Simulation time 1016982726 ps
CPU time 5.62 seconds
Started Jul 12 06:36:28 PM PDT 24
Finished Jul 12 06:36:36 PM PDT 24
Peak memory 206476 kb
Host smart-e8a0ab22-ff61-4eb6-8ad9-650b08247a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1432243157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1432243157
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2801206081
Short name T2782
Test name
Test status
Simulation time 156570561 ps
CPU time 1.8 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 214740 kb
Host smart-88fa901a-fa0d-4899-b425-76a2e5fef416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801206081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2801206081
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.339891556
Short name T2802
Test name
Test status
Simulation time 52485260 ps
CPU time 0.94 seconds
Started Jul 12 06:36:35 PM PDT 24
Finished Jul 12 06:36:38 PM PDT 24
Peak memory 206400 kb
Host smart-f46ded39-942f-4820-b08a-b0a193181f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=339891556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.339891556
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1210666180
Short name T2776
Test name
Test status
Simulation time 43045093 ps
CPU time 0.72 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 206308 kb
Host smart-c0704366-9769-45dd-8a10-ecc3f216b53c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1210666180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1210666180
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3215910106
Short name T272
Test name
Test status
Simulation time 129054127 ps
CPU time 1.45 seconds
Started Jul 12 06:36:35 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 206476 kb
Host smart-13f7c7ba-6a9b-42bd-b247-37bff1250181
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3215910106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3215910106
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2925057124
Short name T241
Test name
Test status
Simulation time 66757887 ps
CPU time 1.77 seconds
Started Jul 12 06:36:26 PM PDT 24
Finished Jul 12 06:36:31 PM PDT 24
Peak memory 222224 kb
Host smart-c687167e-9816-4e69-8d86-78bd59c3e75d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2925057124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2925057124
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1202979147
Short name T301
Test name
Test status
Simulation time 713185409 ps
CPU time 4.45 seconds
Started Jul 12 06:36:25 PM PDT 24
Finished Jul 12 06:36:32 PM PDT 24
Peak memory 206576 kb
Host smart-1602ed5b-bc6e-4785-94ee-793db117f786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1202979147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1202979147
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2607681900
Short name T212
Test name
Test status
Simulation time 125506529 ps
CPU time 1.47 seconds
Started Jul 12 06:36:35 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 214824 kb
Host smart-7dbd4c8c-158b-4d27-ba37-a08622d55f4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607681900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2607681900
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4045974066
Short name T2761
Test name
Test status
Simulation time 86944311 ps
CPU time 0.82 seconds
Started Jul 12 06:36:39 PM PDT 24
Finished Jul 12 06:36:42 PM PDT 24
Peak memory 206352 kb
Host smart-9290febb-9661-442e-8658-66bc318227b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4045974066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4045974066
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1576559485
Short name T2795
Test name
Test status
Simulation time 86246898 ps
CPU time 0.74 seconds
Started Jul 12 06:36:35 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 206300 kb
Host smart-eb0cf3eb-f1f2-4fe5-9f1f-4d8a34fccb68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1576559485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1576559485
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.880469040
Short name T2838
Test name
Test status
Simulation time 392459419 ps
CPU time 1.69 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:40 PM PDT 24
Peak memory 206584 kb
Host smart-09e95f96-2072-4a5e-bd29-46e48ed8f202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=880469040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.880469040
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2553502417
Short name T227
Test name
Test status
Simulation time 72588693 ps
CPU time 1.93 seconds
Started Jul 12 06:36:37 PM PDT 24
Finished Jul 12 06:36:42 PM PDT 24
Peak memory 206592 kb
Host smart-ee221e9d-e718-43a3-a12b-8e82bfd6a28c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2553502417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2553502417
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2495084907
Short name T309
Test name
Test status
Simulation time 404326326 ps
CPU time 2.66 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:41 PM PDT 24
Peak memory 206516 kb
Host smart-c5fd3a95-04d2-49e8-b31e-b0e06a47f515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2495084907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2495084907
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.743973725
Short name T2787
Test name
Test status
Simulation time 153465672 ps
CPU time 1.56 seconds
Started Jul 12 06:36:34 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 214728 kb
Host smart-ea49fee4-a9ea-420c-8415-356e74db6558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743973725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.743973725
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3398679152
Short name T2789
Test name
Test status
Simulation time 58053761 ps
CPU time 0.83 seconds
Started Jul 12 06:36:32 PM PDT 24
Finished Jul 12 06:36:34 PM PDT 24
Peak memory 206356 kb
Host smart-d921f038-639c-4526-9086-539bd28cb7a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3398679152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3398679152
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3554195567
Short name T2812
Test name
Test status
Simulation time 62414720 ps
CPU time 0.7 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:36 PM PDT 24
Peak memory 206300 kb
Host smart-7bd9a20f-e971-489f-a52b-b422d507ac69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3554195567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3554195567
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.45771111
Short name T2817
Test name
Test status
Simulation time 139578832 ps
CPU time 1.19 seconds
Started Jul 12 06:36:34 PM PDT 24
Finished Jul 12 06:36:38 PM PDT 24
Peak memory 206548 kb
Host smart-b4a4565a-c97e-466a-b50d-a76d3d550935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=45771111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.45771111
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1914842754
Short name T230
Test name
Test status
Simulation time 117266020 ps
CPU time 2.58 seconds
Started Jul 12 06:36:35 PM PDT 24
Finished Jul 12 06:36:40 PM PDT 24
Peak memory 206624 kb
Host smart-70861357-7772-408b-95fa-e6bad82adb92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1914842754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1914842754
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3980514763
Short name T238
Test name
Test status
Simulation time 137069819 ps
CPU time 1.4 seconds
Started Jul 12 06:36:37 PM PDT 24
Finished Jul 12 06:36:41 PM PDT 24
Peak memory 214756 kb
Host smart-8ec3c4a1-72e2-4ccd-92e0-7d368ac61f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980514763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3980514763
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4204582777
Short name T2760
Test name
Test status
Simulation time 64440194 ps
CPU time 0.96 seconds
Started Jul 12 06:36:34 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 206520 kb
Host smart-a62e2863-66a6-4ca0-aba5-e9f59c299ffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4204582777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4204582777
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1767996787
Short name T297
Test name
Test status
Simulation time 33320773 ps
CPU time 0.73 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 206316 kb
Host smart-74b864d8-493d-4c46-98d1-d33f9d7b830c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1767996787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1767996787
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.362964342
Short name T2832
Test name
Test status
Simulation time 144872582 ps
CPU time 1.78 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 206544 kb
Host smart-1100aa9e-2c24-47f2-9881-07b1851f4bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=362964342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.362964342
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4243712663
Short name T226
Test name
Test status
Simulation time 131621602 ps
CPU time 2.48 seconds
Started Jul 12 06:36:34 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 222168 kb
Host smart-43c66853-ab17-47fb-bd8e-e33f2cafb40b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4243712663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4243712663
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.844504587
Short name T304
Test name
Test status
Simulation time 404593535 ps
CPU time 2.51 seconds
Started Jul 12 06:36:34 PM PDT 24
Finished Jul 12 06:36:38 PM PDT 24
Peak memory 206556 kb
Host smart-874e350c-dbd2-4899-bfc1-875ee46667aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=844504587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.844504587
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.44516402
Short name T281
Test name
Test status
Simulation time 221557964 ps
CPU time 2.23 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:24 PM PDT 24
Peak memory 206488 kb
Host smart-a19b727c-1fff-48e1-8ea6-58dccd994409
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=44516402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.44516402
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.165774151
Short name T256
Test name
Test status
Simulation time 951927865 ps
CPU time 7.45 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:31 PM PDT 24
Peak memory 206488 kb
Host smart-148f7251-6b95-40f0-b63e-1ea9dfa95910
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=165774151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.165774151
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.725334688
Short name T2781
Test name
Test status
Simulation time 133150242 ps
CPU time 0.96 seconds
Started Jul 12 06:36:18 PM PDT 24
Finished Jul 12 06:36:20 PM PDT 24
Peak memory 206340 kb
Host smart-cc0c5c2c-0f39-43e8-a9aa-05840b869dbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=725334688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.725334688
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1771161402
Short name T240
Test name
Test status
Simulation time 202639268 ps
CPU time 1.89 seconds
Started Jul 12 06:36:22 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 214752 kb
Host smart-442f7253-ba97-47c6-b2d8-5bb1206263d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771161402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1771161402
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.480417694
Short name T2820
Test name
Test status
Simulation time 45711589 ps
CPU time 0.94 seconds
Started Jul 12 06:36:22 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 206476 kb
Host smart-6ddfd219-1f05-471b-8559-8f2f6de0f574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=480417694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.480417694
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.237193656
Short name T2769
Test name
Test status
Simulation time 29270390 ps
CPU time 0.63 seconds
Started Jul 12 06:36:22 PM PDT 24
Finished Jul 12 06:36:25 PM PDT 24
Peak memory 206296 kb
Host smart-0e4af8f0-2af7-4599-840f-0a6910df17ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=237193656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.237193656
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.658774788
Short name T2835
Test name
Test status
Simulation time 131676587 ps
CPU time 1.44 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:24 PM PDT 24
Peak memory 214696 kb
Host smart-dc463ff3-167e-4e83-bbe0-ee669bcfa092
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=658774788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.658774788
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3434450771
Short name T2834
Test name
Test status
Simulation time 538638131 ps
CPU time 4.61 seconds
Started Jul 12 06:36:23 PM PDT 24
Finished Jul 12 06:36:30 PM PDT 24
Peak memory 206388 kb
Host smart-e9fc9ad2-eddc-4b78-b7a0-07ee94d7b5ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3434450771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3434450771
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3879116616
Short name T2784
Test name
Test status
Simulation time 64456465 ps
CPU time 1.04 seconds
Started Jul 12 06:36:22 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 206520 kb
Host smart-916aaf45-6a86-46bd-8a44-820c3f43ee52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3879116616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3879116616
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1018140578
Short name T2829
Test name
Test status
Simulation time 69746008 ps
CPU time 1.64 seconds
Started Jul 12 06:36:18 PM PDT 24
Finished Jul 12 06:36:21 PM PDT 24
Peak memory 206700 kb
Host smart-1f4f531e-19f6-4a6a-abeb-96dbcac38a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1018140578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1018140578
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3037153659
Short name T2821
Test name
Test status
Simulation time 39251306 ps
CPU time 0.67 seconds
Started Jul 12 06:36:43 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 206296 kb
Host smart-1ed15d40-b799-4751-828e-75c7c03dac2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3037153659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3037153659
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3775642600
Short name T2754
Test name
Test status
Simulation time 65520378 ps
CPU time 0.75 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:35 PM PDT 24
Peak memory 206312 kb
Host smart-57743689-6224-4ff1-af36-b8f9ef2759f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3775642600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3775642600
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.930689949
Short name T201
Test name
Test status
Simulation time 100157836 ps
CPU time 0.75 seconds
Started Jul 12 06:36:34 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 206304 kb
Host smart-2fd6b872-8574-4b6f-8da7-e123cb15ee1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=930689949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.930689949
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1790194673
Short name T2836
Test name
Test status
Simulation time 59843614 ps
CPU time 0.7 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 206300 kb
Host smart-15e668e9-9f92-4d81-82e4-4723b227071e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1790194673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1790194673
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2901122084
Short name T2794
Test name
Test status
Simulation time 46658647 ps
CPU time 0.7 seconds
Started Jul 12 06:36:32 PM PDT 24
Finished Jul 12 06:36:34 PM PDT 24
Peak memory 206308 kb
Host smart-fbccc354-05c5-474d-bbd7-4a2ebd8d0f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2901122084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2901122084
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1602978939
Short name T2819
Test name
Test status
Simulation time 86416103 ps
CPU time 0.7 seconds
Started Jul 12 06:36:34 PM PDT 24
Finished Jul 12 06:36:36 PM PDT 24
Peak memory 206296 kb
Host smart-2512c3a3-6c6f-4a9f-89e5-3a0fdb15ed90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1602978939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1602978939
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3822143552
Short name T295
Test name
Test status
Simulation time 31595318 ps
CPU time 0.65 seconds
Started Jul 12 06:36:34 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 206280 kb
Host smart-5b3715dd-3393-413a-beb8-bffb1886bd8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3822143552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3822143552
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.39351819
Short name T2788
Test name
Test status
Simulation time 38487861 ps
CPU time 0.66 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:39 PM PDT 24
Peak memory 206264 kb
Host smart-05541eec-75ca-4b5a-826e-5821a7b2b749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=39351819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.39351819
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.290571593
Short name T200
Test name
Test status
Simulation time 39599131 ps
CPU time 0.7 seconds
Started Jul 12 06:36:35 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 206312 kb
Host smart-30e2efa6-2668-44f1-a3d5-e6cb3425d22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=290571593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.290571593
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3532407562
Short name T264
Test name
Test status
Simulation time 135945271 ps
CPU time 3.17 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 206492 kb
Host smart-eebac816-a678-44f0-b1f2-35b30f373e2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3532407562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3532407562
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2802822762
Short name T2809
Test name
Test status
Simulation time 675880196 ps
CPU time 5.76 seconds
Started Jul 12 06:36:21 PM PDT 24
Finished Jul 12 06:36:30 PM PDT 24
Peak memory 206428 kb
Host smart-70d5e205-600d-48d3-8f57-eca5cc3e9358
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2802822762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2802822762
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.315271625
Short name T2750
Test name
Test status
Simulation time 66745096 ps
CPU time 0.82 seconds
Started Jul 12 06:36:15 PM PDT 24
Finished Jul 12 06:36:17 PM PDT 24
Peak memory 206308 kb
Host smart-93db516b-8fb1-4217-b502-09a4069008db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=315271625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.315271625
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2385815073
Short name T2792
Test name
Test status
Simulation time 96339247 ps
CPU time 1.26 seconds
Started Jul 12 06:36:16 PM PDT 24
Finished Jul 12 06:36:18 PM PDT 24
Peak memory 214756 kb
Host smart-5c966d04-12fd-42b3-920c-917d77e4f734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385815073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2385815073
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.4148574738
Short name T258
Test name
Test status
Simulation time 58172141 ps
CPU time 0.84 seconds
Started Jul 12 06:44:43 PM PDT 24
Finished Jul 12 06:44:46 PM PDT 24
Peak memory 206396 kb
Host smart-c701ff6d-4ce7-43c2-ad67-ca7d0033de52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4148574738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.4148574738
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2202872938
Short name T2844
Test name
Test status
Simulation time 43317314 ps
CPU time 0.69 seconds
Started Jul 12 06:36:22 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 206276 kb
Host smart-bee8bba6-00f8-41b4-80b4-91f9c32615d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2202872938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2202872938
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1977647692
Short name T2813
Test name
Test status
Simulation time 79611606 ps
CPU time 2.24 seconds
Started Jul 12 06:36:18 PM PDT 24
Finished Jul 12 06:36:21 PM PDT 24
Peak memory 214664 kb
Host smart-005079aa-77f1-431e-bdc7-c30116af2d01
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1977647692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1977647692
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.771098183
Short name T2803
Test name
Test status
Simulation time 168283761 ps
CPU time 4.04 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:28 PM PDT 24
Peak memory 206400 kb
Host smart-45053bc6-1fbb-4bd6-b7f8-31be109104a2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=771098183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.771098183
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2848175568
Short name T269
Test name
Test status
Simulation time 107318619 ps
CPU time 1.73 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:25 PM PDT 24
Peak memory 206492 kb
Host smart-a36210fd-2ca0-4f94-82e4-2a136476ef2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2848175568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2848175568
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2056222297
Short name T2849
Test name
Test status
Simulation time 65207186 ps
CPU time 1.83 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 206600 kb
Host smart-816bad84-d221-4aeb-9703-5a9db4061af2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2056222297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2056222297
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.978511445
Short name T299
Test name
Test status
Simulation time 38599825 ps
CPU time 0.65 seconds
Started Jul 12 06:36:37 PM PDT 24
Finished Jul 12 06:36:40 PM PDT 24
Peak memory 206340 kb
Host smart-b65dbe57-f4fa-42f2-b3a3-715b81640f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=978511445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.978511445
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4231413346
Short name T2853
Test name
Test status
Simulation time 41897694 ps
CPU time 0.68 seconds
Started Jul 12 06:36:37 PM PDT 24
Finished Jul 12 06:36:40 PM PDT 24
Peak memory 206028 kb
Host smart-756150bf-f8b9-4598-a11b-987ffb543553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4231413346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4231413346
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2542515821
Short name T286
Test name
Test status
Simulation time 34621982 ps
CPU time 0.7 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:35 PM PDT 24
Peak memory 206212 kb
Host smart-70828421-b611-476f-a4c0-eba034569562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2542515821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2542515821
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.8804387
Short name T199
Test name
Test status
Simulation time 36454057 ps
CPU time 0.67 seconds
Started Jul 12 06:36:36 PM PDT 24
Finished Jul 12 06:36:40 PM PDT 24
Peak memory 206276 kb
Host smart-e5029657-b14f-4fc9-b18f-c64fdd6472d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=8804387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.8804387
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3333484585
Short name T2840
Test name
Test status
Simulation time 66687619 ps
CPU time 0.75 seconds
Started Jul 12 06:36:35 PM PDT 24
Finished Jul 12 06:36:38 PM PDT 24
Peak memory 206528 kb
Host smart-f4cf772a-6cb1-40bf-94aa-6a2afbd4a755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3333484585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3333484585
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3451713550
Short name T2775
Test name
Test status
Simulation time 81061703 ps
CPU time 0.72 seconds
Started Jul 12 06:36:37 PM PDT 24
Finished Jul 12 06:36:40 PM PDT 24
Peak memory 206000 kb
Host smart-17c9e12f-1d41-4559-a169-509f93d1c424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3451713550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3451713550
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2300751404
Short name T2816
Test name
Test status
Simulation time 36254926 ps
CPU time 0.69 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:36:44 PM PDT 24
Peak memory 206312 kb
Host smart-56c476f2-1296-460a-8d29-93e2d73b4b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2300751404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2300751404
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.137509229
Short name T294
Test name
Test status
Simulation time 45599411 ps
CPU time 0.73 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 206284 kb
Host smart-45bdd0cf-40b4-4132-8a44-3717067dd636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=137509229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.137509229
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2108137299
Short name T2767
Test name
Test status
Simulation time 76959801 ps
CPU time 0.72 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:56 PM PDT 24
Peak memory 206324 kb
Host smart-47b36251-7c96-41d7-9212-803acb913db1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2108137299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2108137299
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2566729962
Short name T2851
Test name
Test status
Simulation time 57033052 ps
CPU time 0.73 seconds
Started Jul 12 06:36:45 PM PDT 24
Finished Jul 12 06:36:48 PM PDT 24
Peak memory 206260 kb
Host smart-1ebfaf8c-d278-4889-8c6f-bc911feb72fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2566729962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2566729962
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4059420874
Short name T2830
Test name
Test status
Simulation time 126185810 ps
CPU time 2.02 seconds
Started Jul 12 06:36:22 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206448 kb
Host smart-109ecaf1-c778-4bca-be7f-b89b0a89708e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4059420874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.4059420874
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1727903520
Short name T2765
Test name
Test status
Simulation time 711865085 ps
CPU time 4.24 seconds
Started Jul 12 06:36:18 PM PDT 24
Finished Jul 12 06:36:23 PM PDT 24
Peak memory 206436 kb
Host smart-716b3dd5-34ca-48a5-8853-d9e1fa46e9d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1727903520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1727903520
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1678512921
Short name T265
Test name
Test status
Simulation time 117063631 ps
CPU time 1.01 seconds
Started Jul 12 06:36:19 PM PDT 24
Finished Jul 12 06:36:21 PM PDT 24
Peak memory 206232 kb
Host smart-d669a2e7-7e4c-40ec-91ce-7529fc3ec915
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1678512921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1678512921
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2430577363
Short name T231
Test name
Test status
Simulation time 130517153 ps
CPU time 2.32 seconds
Started Jul 12 06:36:21 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 214740 kb
Host smart-6367cde7-8ab8-4011-878f-5c05dd49dccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430577363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2430577363
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3022904989
Short name T2756
Test name
Test status
Simulation time 44325342 ps
CPU time 0.81 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:22 PM PDT 24
Peak memory 206144 kb
Host smart-c86b9d82-09fd-4c22-9316-48f2ce795abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3022904989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3022904989
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3521770871
Short name T2774
Test name
Test status
Simulation time 41096111 ps
CPU time 0.7 seconds
Started Jul 12 06:36:19 PM PDT 24
Finished Jul 12 06:36:21 PM PDT 24
Peak memory 206504 kb
Host smart-e20c31ed-1f50-4cf6-b44c-da1ca058b0c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3521770871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3521770871
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.514275238
Short name T263
Test name
Test status
Simulation time 58202755 ps
CPU time 1.39 seconds
Started Jul 12 06:36:19 PM PDT 24
Finished Jul 12 06:36:22 PM PDT 24
Peak memory 214696 kb
Host smart-baa65ec5-0567-402a-a8ae-0164e0ef8842
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=514275238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.514275238
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.168162099
Short name T2843
Test name
Test status
Simulation time 105582196 ps
CPU time 2.24 seconds
Started Jul 12 06:36:22 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206420 kb
Host smart-c5b04867-e6ed-4a39-8dfa-f7c9f65b667e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=168162099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.168162099
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2946639582
Short name T2847
Test name
Test status
Simulation time 259164009 ps
CPU time 1.21 seconds
Started Jul 12 06:36:24 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206432 kb
Host smart-7cbecbd8-39af-443c-882c-647f722491ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2946639582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2946639582
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3716262964
Short name T2764
Test name
Test status
Simulation time 269886751 ps
CPU time 3.41 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 214784 kb
Host smart-bf75e4f0-ebaf-4c0e-a30d-ec14e6c653a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3716262964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3716262964
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1636678187
Short name T2796
Test name
Test status
Simulation time 872131945 ps
CPU time 5.12 seconds
Started Jul 12 06:36:19 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 206504 kb
Host smart-3bd42a10-b42d-4be2-9d8b-0469487fd2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1636678187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1636678187
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2467029521
Short name T2831
Test name
Test status
Simulation time 47148388 ps
CPU time 0.7 seconds
Started Jul 12 06:36:39 PM PDT 24
Finished Jul 12 06:36:41 PM PDT 24
Peak memory 206296 kb
Host smart-faba2e77-13f2-4a9a-b256-82dda5a62aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2467029521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2467029521
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1566466010
Short name T2808
Test name
Test status
Simulation time 36130717 ps
CPU time 0.66 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 206320 kb
Host smart-7b8325f3-4d96-4fa9-b7a3-21bae7c4caa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1566466010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1566466010
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.436892566
Short name T2815
Test name
Test status
Simulation time 34911890 ps
CPU time 0.73 seconds
Started Jul 12 06:36:52 PM PDT 24
Finished Jul 12 06:36:57 PM PDT 24
Peak memory 206416 kb
Host smart-d2aaf37c-b8a4-4bd1-94ee-0a1b45bff40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=436892566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.436892566
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3842712372
Short name T288
Test name
Test status
Simulation time 39392904 ps
CPU time 0.68 seconds
Started Jul 12 06:36:41 PM PDT 24
Finished Jul 12 06:36:44 PM PDT 24
Peak memory 206292 kb
Host smart-8bab3ace-0754-489c-bb20-63d0f0c58fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3842712372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3842712372
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2544652177
Short name T296
Test name
Test status
Simulation time 49328458 ps
CPU time 0.68 seconds
Started Jul 12 06:36:40 PM PDT 24
Finished Jul 12 06:36:42 PM PDT 24
Peak memory 206292 kb
Host smart-66ebfd07-c061-45f3-bb6e-57b62ab8492b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2544652177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2544652177
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1822622394
Short name T2824
Test name
Test status
Simulation time 53422095 ps
CPU time 0.68 seconds
Started Jul 12 06:36:51 PM PDT 24
Finished Jul 12 06:36:55 PM PDT 24
Peak memory 206292 kb
Host smart-cf81c790-5864-4f41-bd1e-be22ca628151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1822622394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1822622394
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1334315775
Short name T285
Test name
Test status
Simulation time 38402954 ps
CPU time 0.69 seconds
Started Jul 12 06:36:41 PM PDT 24
Finished Jul 12 06:36:44 PM PDT 24
Peak memory 206324 kb
Host smart-afc8670f-b236-454c-a629-62327f31ae25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1334315775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1334315775
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.670373383
Short name T2827
Test name
Test status
Simulation time 58361713 ps
CPU time 0.68 seconds
Started Jul 12 06:36:42 PM PDT 24
Finished Jul 12 06:36:45 PM PDT 24
Peak memory 206332 kb
Host smart-6ef2fdb2-6513-4b96-829c-cb403239d0d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=670373383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.670373383
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1385018685
Short name T233
Test name
Test status
Simulation time 92808769 ps
CPU time 2.55 seconds
Started Jul 12 06:36:19 PM PDT 24
Finished Jul 12 06:36:23 PM PDT 24
Peak memory 214836 kb
Host smart-dc698d4d-8629-45c5-b0b9-f9aa55c1e95f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385018685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1385018685
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4216037285
Short name T2801
Test name
Test status
Simulation time 56988130 ps
CPU time 0.99 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:25 PM PDT 24
Peak memory 206512 kb
Host smart-405ef318-ac60-4c54-89af-e0a5676fc473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4216037285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.4216037285
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3108645688
Short name T287
Test name
Test status
Simulation time 54424459 ps
CPU time 0.67 seconds
Started Jul 12 06:36:15 PM PDT 24
Finished Jul 12 06:36:17 PM PDT 24
Peak memory 206288 kb
Host smart-e0fee30b-6089-46b6-a59d-5b848a1ae4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3108645688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3108645688
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1120182788
Short name T273
Test name
Test status
Simulation time 118771135 ps
CPU time 1.14 seconds
Started Jul 12 06:36:18 PM PDT 24
Finished Jul 12 06:36:20 PM PDT 24
Peak memory 206568 kb
Host smart-0e3c53e5-3e3e-4ba2-9386-c7dcbde1af61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1120182788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1120182788
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1365211007
Short name T211
Test name
Test status
Simulation time 175858505 ps
CPU time 2.03 seconds
Started Jul 12 06:36:19 PM PDT 24
Finished Jul 12 06:36:23 PM PDT 24
Peak memory 206604 kb
Host smart-891798f6-091f-4ba6-b7b6-408fc3aead26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1365211007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1365211007
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.343891342
Short name T308
Test name
Test status
Simulation time 504605861 ps
CPU time 2.93 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206512 kb
Host smart-d21dc180-191c-4265-83c3-0a96ee32cade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=343891342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.343891342
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2263076407
Short name T2833
Test name
Test status
Simulation time 136561243 ps
CPU time 1.78 seconds
Started Jul 12 06:36:17 PM PDT 24
Finished Jul 12 06:36:20 PM PDT 24
Peak memory 214760 kb
Host smart-467dbb23-c29f-4660-9638-06745af0a0dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263076407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2263076407
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.705301259
Short name T2852
Test name
Test status
Simulation time 37625940 ps
CPU time 0.81 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:24 PM PDT 24
Peak memory 206348 kb
Host smart-74a0997b-1104-42f4-b293-f9b6e4490d2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=705301259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.705301259
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2474049095
Short name T2826
Test name
Test status
Simulation time 32541523 ps
CPU time 0.68 seconds
Started Jul 12 06:36:17 PM PDT 24
Finished Jul 12 06:36:18 PM PDT 24
Peak memory 206280 kb
Host smart-804741bf-201e-445a-ae7a-38f6d5ba88a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2474049095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2474049095
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4259764983
Short name T2762
Test name
Test status
Simulation time 255343037 ps
CPU time 1.97 seconds
Started Jul 12 06:36:21 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206472 kb
Host smart-d2b51cba-6106-4c57-bbbe-2bb66bd90f76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4259764983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4259764983
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.701704654
Short name T2828
Test name
Test status
Simulation time 162242333 ps
CPU time 2.01 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:25 PM PDT 24
Peak memory 222112 kb
Host smart-09b794e3-8d7e-4443-9419-729ea162d2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701704654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.701704654
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3380065777
Short name T2842
Test name
Test status
Simulation time 143151826 ps
CPU time 1.25 seconds
Started Jul 12 06:36:19 PM PDT 24
Finished Jul 12 06:36:21 PM PDT 24
Peak memory 216500 kb
Host smart-646109ed-7513-4627-8c46-c64fb16155f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380065777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3380065777
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3965457891
Short name T274
Test name
Test status
Simulation time 57130616 ps
CPU time 0.94 seconds
Started Jul 12 06:36:22 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 206476 kb
Host smart-d0198ccf-e13d-4ec7-9133-4b2c95bbf0ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3965457891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3965457891
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1815325901
Short name T202
Test name
Test status
Simulation time 52234790 ps
CPU time 0.69 seconds
Started Jul 12 06:36:17 PM PDT 24
Finished Jul 12 06:36:19 PM PDT 24
Peak memory 206292 kb
Host smart-898eb8d2-5e9e-4243-9c7b-dd4c16d4483c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1815325901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1815325901
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4084034642
Short name T2818
Test name
Test status
Simulation time 130071316 ps
CPU time 1.67 seconds
Started Jul 12 06:36:23 PM PDT 24
Finished Jul 12 06:36:28 PM PDT 24
Peak memory 206548 kb
Host smart-d14bc7ea-ed31-4ca0-990c-f8a61f16d55a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4084034642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.4084034642
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.846745817
Short name T2800
Test name
Test status
Simulation time 149988408 ps
CPU time 1.37 seconds
Started Jul 12 06:36:18 PM PDT 24
Finished Jul 12 06:36:20 PM PDT 24
Peak memory 206532 kb
Host smart-d57ab139-20eb-4798-8131-0b7df4ccffe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=846745817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.846745817
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1413414336
Short name T302
Test name
Test status
Simulation time 543799191 ps
CPU time 2.92 seconds
Started Jul 12 06:36:17 PM PDT 24
Finished Jul 12 06:36:21 PM PDT 24
Peak memory 206544 kb
Host smart-1c724221-b3bf-4f64-92a8-f734c7763a85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1413414336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1413414336
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2534717784
Short name T2798
Test name
Test status
Simulation time 301011827 ps
CPU time 1.85 seconds
Started Jul 12 06:36:25 PM PDT 24
Finished Jul 12 06:36:29 PM PDT 24
Peak memory 214776 kb
Host smart-c2b3f9ec-794e-4bbc-87f3-acf145574632
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534717784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2534717784
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1251595906
Short name T259
Test name
Test status
Simulation time 75420698 ps
CPU time 0.82 seconds
Started Jul 12 06:36:25 PM PDT 24
Finished Jul 12 06:36:29 PM PDT 24
Peak memory 206356 kb
Host smart-58902826-bf01-4dc0-a597-4d9bae5c09dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1251595906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1251595906
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2161049305
Short name T2806
Test name
Test status
Simulation time 33291062 ps
CPU time 0.7 seconds
Started Jul 12 06:36:26 PM PDT 24
Finished Jul 12 06:36:29 PM PDT 24
Peak memory 206260 kb
Host smart-6e6d3fd8-be73-4c2a-9477-8f7fa0a1e165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161049305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2161049305
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1825003155
Short name T2810
Test name
Test status
Simulation time 181594778 ps
CPU time 1.24 seconds
Started Jul 12 06:36:27 PM PDT 24
Finished Jul 12 06:36:30 PM PDT 24
Peak memory 206452 kb
Host smart-884bd013-0b5b-4a92-9831-417edf154521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1825003155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1825003155
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2467777940
Short name T2780
Test name
Test status
Simulation time 128966231 ps
CPU time 2.96 seconds
Started Jul 12 06:36:23 PM PDT 24
Finished Jul 12 06:36:29 PM PDT 24
Peak memory 206720 kb
Host smart-6d7b127d-03f4-4abf-82de-f76fc1ca7c59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2467777940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2467777940
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3875484255
Short name T2850
Test name
Test status
Simulation time 956363433 ps
CPU time 4.88 seconds
Started Jul 12 06:36:20 PM PDT 24
Finished Jul 12 06:36:26 PM PDT 24
Peak memory 206384 kb
Host smart-97fd5b27-6617-4bc5-8d1d-85456ffb63e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3875484255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3875484255
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3886234695
Short name T194
Test name
Test status
Simulation time 186816029 ps
CPU time 2.12 seconds
Started Jul 12 06:36:30 PM PDT 24
Finished Jul 12 06:36:34 PM PDT 24
Peak memory 214796 kb
Host smart-411de0cb-ddfc-4471-9cff-da11bc4f1a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886234695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3886234695
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4130922496
Short name T262
Test name
Test status
Simulation time 106502014 ps
CPU time 0.99 seconds
Started Jul 12 06:36:26 PM PDT 24
Finished Jul 12 06:36:29 PM PDT 24
Peak memory 206512 kb
Host smart-daf4f0b0-8112-48e8-8f9f-101cfb9f271c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4130922496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4130922496
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1651284557
Short name T2823
Test name
Test status
Simulation time 87259408 ps
CPU time 0.72 seconds
Started Jul 12 06:36:24 PM PDT 24
Finished Jul 12 06:36:27 PM PDT 24
Peak memory 206292 kb
Host smart-08c91e5c-a2bf-47d7-b190-564941ddc39c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1651284557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1651284557
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3173714178
Short name T2785
Test name
Test status
Simulation time 119086594 ps
CPU time 1.09 seconds
Started Jul 12 06:36:27 PM PDT 24
Finished Jul 12 06:36:30 PM PDT 24
Peak memory 206512 kb
Host smart-d0230943-63c0-4f52-8079-6f346367013b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3173714178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3173714178
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.871502600
Short name T217
Test name
Test status
Simulation time 359722355 ps
CPU time 2.9 seconds
Started Jul 12 06:36:33 PM PDT 24
Finished Jul 12 06:36:37 PM PDT 24
Peak memory 206308 kb
Host smart-11353f4f-f53e-47f6-9bd5-a35c082010da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=871502600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.871502600
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1781459917
Short name T1748
Test name
Test status
Simulation time 51226982 ps
CPU time 0.69 seconds
Started Jul 12 05:26:13 PM PDT 24
Finished Jul 12 05:26:15 PM PDT 24
Peak memory 206696 kb
Host smart-4f54d286-3e1d-487c-b5ad-ed3ae019cb82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1781459917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1781459917
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3341939018
Short name T477
Test name
Test status
Simulation time 3874559964 ps
CPU time 4.43 seconds
Started Jul 12 05:25:52 PM PDT 24
Finished Jul 12 05:25:57 PM PDT 24
Peak memory 207056 kb
Host smart-38fcfc79-2780-4428-ae9a-8c141fd00f20
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3341939018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3341939018
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2195768928
Short name T847
Test name
Test status
Simulation time 13384622859 ps
CPU time 13.07 seconds
Started Jul 12 05:25:52 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 206848 kb
Host smart-a2a89d9c-1e2e-4164-98c0-ecba15e36909
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2195768928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2195768928
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3578915144
Short name T728
Test name
Test status
Simulation time 23363446819 ps
CPU time 22.81 seconds
Started Jul 12 05:25:52 PM PDT 24
Finished Jul 12 05:26:16 PM PDT 24
Peak memory 206880 kb
Host smart-c90bdedb-b3d4-4c54-a464-880cd593e40e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3578915144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3578915144
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4093398153
Short name T376
Test name
Test status
Simulation time 180603506 ps
CPU time 0.86 seconds
Started Jul 12 05:25:47 PM PDT 24
Finished Jul 12 05:25:49 PM PDT 24
Peak memory 206812 kb
Host smart-a9c22af6-4458-497f-901b-1a6acbe3a4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40933
98153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4093398153
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.398365326
Short name T2474
Test name
Test status
Simulation time 143392502 ps
CPU time 0.76 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:00 PM PDT 24
Peak memory 206804 kb
Host smart-172b06b1-d6c5-4509-a740-2e632152f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39836
5326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.398365326
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1224912626
Short name T1397
Test name
Test status
Simulation time 482087591 ps
CPU time 1.39 seconds
Started Jul 12 05:25:54 PM PDT 24
Finished Jul 12 05:25:56 PM PDT 24
Peak memory 206816 kb
Host smart-f04c9f08-e6f6-441e-a913-439278625de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12249
12626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1224912626
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.4090042075
Short name T35
Test name
Test status
Simulation time 1076042967 ps
CPU time 2.42 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:02 PM PDT 24
Peak memory 206960 kb
Host smart-465b2307-c59d-4955-aaf0-559e40c61c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40900
42075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.4090042075
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2634302259
Short name T1563
Test name
Test status
Simulation time 22579748197 ps
CPU time 40.41 seconds
Started Jul 12 05:25:58 PM PDT 24
Finished Jul 12 05:26:40 PM PDT 24
Peak memory 207104 kb
Host smart-400e0d85-537f-4815-98ac-ec35ce7f9ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26343
02259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2634302259
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2629139310
Short name T2012
Test name
Test status
Simulation time 310874775 ps
CPU time 1.14 seconds
Started Jul 12 05:25:58 PM PDT 24
Finished Jul 12 05:26:02 PM PDT 24
Peak memory 206724 kb
Host smart-4d721ff9-78c2-4038-8e2c-6131a708f506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26291
39310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2629139310
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2701231996
Short name T2107
Test name
Test status
Simulation time 134651392 ps
CPU time 0.74 seconds
Started Jul 12 05:25:59 PM PDT 24
Finished Jul 12 05:26:01 PM PDT 24
Peak memory 206824 kb
Host smart-7de0143c-a424-49d9-935c-7a0f4c4d0664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27012
31996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2701231996
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1211361996
Short name T859
Test name
Test status
Simulation time 5127512298 ps
CPU time 134.74 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:28:13 PM PDT 24
Peak memory 207032 kb
Host smart-9f63ac62-7fa0-4f6d-bbfb-2db1b8809e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12113
61996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1211361996
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.19873418
Short name T1224
Test name
Test status
Simulation time 37465947 ps
CPU time 0.64 seconds
Started Jul 12 05:25:56 PM PDT 24
Finished Jul 12 05:25:58 PM PDT 24
Peak memory 206816 kb
Host smart-aa77f809-b3f9-4a31-bfd2-0b770302ae24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19873
418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.19873418
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.507719368
Short name T2588
Test name
Test status
Simulation time 120189972135 ps
CPU time 169.63 seconds
Started Jul 12 05:25:59 PM PDT 24
Finished Jul 12 05:28:51 PM PDT 24
Peak memory 206928 kb
Host smart-e761231f-ac09-4b40-9deb-706ab591d96a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=507719368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.507719368
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.724873859
Short name T798
Test name
Test status
Simulation time 91164261949 ps
CPU time 119.25 seconds
Started Jul 12 05:25:58 PM PDT 24
Finished Jul 12 05:27:59 PM PDT 24
Peak memory 207016 kb
Host smart-f95b6ca0-20f2-4334-bb5e-5f2c76502626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724873859 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.724873859
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.2307724521
Short name T1691
Test name
Test status
Simulation time 121116453814 ps
CPU time 176.18 seconds
Started Jul 12 05:25:59 PM PDT 24
Finished Jul 12 05:28:57 PM PDT 24
Peak memory 206900 kb
Host smart-61f3e4f0-9d9c-46ab-a709-2c3820f722e5
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2307724521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.2307724521
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3987800339
Short name T2719
Test name
Test status
Simulation time 120235265344 ps
CPU time 194.31 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:29:13 PM PDT 24
Peak memory 206920 kb
Host smart-6c3aa4ac-a984-4aa8-b9a8-8d450b69f654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987800339 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3987800339
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.1524625832
Short name T1967
Test name
Test status
Simulation time 113165256114 ps
CPU time 142.34 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:28:20 PM PDT 24
Peak memory 207180 kb
Host smart-4b0c2953-9d88-48d3-b97a-1ccf82e0f592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15246
25832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.1524625832
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2611534279
Short name T2670
Test name
Test status
Simulation time 233178753 ps
CPU time 0.91 seconds
Started Jul 12 05:25:58 PM PDT 24
Finished Jul 12 05:26:01 PM PDT 24
Peak memory 206760 kb
Host smart-51388e99-7324-4e6f-a477-fcfe5564356f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26115
34279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2611534279
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.4268749220
Short name T1010
Test name
Test status
Simulation time 146335015 ps
CPU time 0.75 seconds
Started Jul 12 05:25:54 PM PDT 24
Finished Jul 12 05:25:56 PM PDT 24
Peak memory 206716 kb
Host smart-1584b565-feb7-4ac5-bf3e-b1463d85d8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42687
49220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.4268749220
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2440981648
Short name T1334
Test name
Test status
Simulation time 247959058 ps
CPU time 0.87 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:00 PM PDT 24
Peak memory 206812 kb
Host smart-711e0d8b-e71a-436d-8c0a-0564ec3068b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24409
81648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2440981648
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.2522800645
Short name T209
Test name
Test status
Simulation time 9049436964 ps
CPU time 66.55 seconds
Started Jul 12 05:26:01 PM PDT 24
Finished Jul 12 05:27:09 PM PDT 24
Peak memory 207068 kb
Host smart-7b6feac2-e3c0-4573-99bd-05c50f1566d0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2522800645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.2522800645
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.2897263627
Short name T1710
Test name
Test status
Simulation time 7607586484 ps
CPU time 61.74 seconds
Started Jul 12 05:25:54 PM PDT 24
Finished Jul 12 05:26:56 PM PDT 24
Peak memory 207076 kb
Host smart-62e1ef84-cf6f-471a-8b8a-f6705d59e04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28972
63627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.2897263627
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2956214878
Short name T1202
Test name
Test status
Simulation time 207980940 ps
CPU time 0.89 seconds
Started Jul 12 05:25:58 PM PDT 24
Finished Jul 12 05:26:01 PM PDT 24
Peak memory 206816 kb
Host smart-3a29ecc5-816c-4522-a87f-c337aa5cfa9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29562
14878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2956214878
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.1777291954
Short name T64
Test name
Test status
Simulation time 499006451 ps
CPU time 1.34 seconds
Started Jul 12 05:25:59 PM PDT 24
Finished Jul 12 05:26:02 PM PDT 24
Peak memory 206832 kb
Host smart-fd965ecb-0544-483a-b9cb-2d64f0fef567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17772
91954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.1777291954
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1811138658
Short name T20
Test name
Test status
Simulation time 23332790281 ps
CPU time 24.88 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:24 PM PDT 24
Peak memory 206868 kb
Host smart-f0bae09b-9022-4180-97a3-ca1f01fb534e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18111
38658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1811138658
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3685071441
Short name T1406
Test name
Test status
Simulation time 3293536648 ps
CPU time 4.05 seconds
Started Jul 12 05:25:59 PM PDT 24
Finished Jul 12 05:26:05 PM PDT 24
Peak memory 206896 kb
Host smart-1fba2f87-8284-41fb-bb9b-05666001c954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36850
71441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3685071441
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.946074944
Short name T721
Test name
Test status
Simulation time 9997510083 ps
CPU time 264.85 seconds
Started Jul 12 05:25:58 PM PDT 24
Finished Jul 12 05:30:25 PM PDT 24
Peak memory 206936 kb
Host smart-df208264-f4eb-4ae4-bace-10b0b4e99086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94607
4944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.946074944
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3258177129
Short name T1796
Test name
Test status
Simulation time 3643698596 ps
CPU time 26.71 seconds
Started Jul 12 05:25:54 PM PDT 24
Finished Jul 12 05:26:22 PM PDT 24
Peak memory 206912 kb
Host smart-92087e0a-93e6-48d2-9573-4624eb45375f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3258177129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3258177129
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3799756052
Short name T468
Test name
Test status
Simulation time 244378151 ps
CPU time 0.98 seconds
Started Jul 12 05:25:55 PM PDT 24
Finished Jul 12 05:25:58 PM PDT 24
Peak memory 206808 kb
Host smart-80b13585-e75d-4ee4-91ce-5b031d74ba8a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3799756052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3799756052
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1980804654
Short name T2110
Test name
Test status
Simulation time 186840968 ps
CPU time 0.9 seconds
Started Jul 12 05:25:55 PM PDT 24
Finished Jul 12 05:25:57 PM PDT 24
Peak memory 206824 kb
Host smart-7629acb0-69fc-4366-89ab-498ac51b3ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19808
04654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1980804654
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.1067299425
Short name T651
Test name
Test status
Simulation time 3403186894 ps
CPU time 24.4 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:24 PM PDT 24
Peak memory 206900 kb
Host smart-1338e6d3-b5d6-4f11-b456-6273327a1771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672
99425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.1067299425
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3953257027
Short name T2472
Test name
Test status
Simulation time 6178083254 ps
CPU time 41.51 seconds
Started Jul 12 05:26:00 PM PDT 24
Finished Jul 12 05:26:43 PM PDT 24
Peak memory 206928 kb
Host smart-e00c4ad7-6be1-4e14-9d38-d1af6c396254
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3953257027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3953257027
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.4187617377
Short name T1588
Test name
Test status
Simulation time 191819126 ps
CPU time 0.82 seconds
Started Jul 12 05:25:55 PM PDT 24
Finished Jul 12 05:25:57 PM PDT 24
Peak memory 206692 kb
Host smart-72990583-2ec0-4339-b74b-41758277640f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4187617377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.4187617377
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1423364266
Short name T2283
Test name
Test status
Simulation time 147732324 ps
CPU time 0.85 seconds
Started Jul 12 05:25:57 PM PDT 24
Finished Jul 12 05:26:00 PM PDT 24
Peak memory 206776 kb
Host smart-726c2ba1-050e-4352-b9dc-f2a681b81dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14233
64266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1423364266
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.198342334
Short name T65
Test name
Test status
Simulation time 480385632 ps
CPU time 1.45 seconds
Started Jul 12 05:25:56 PM PDT 24
Finished Jul 12 05:25:59 PM PDT 24
Peak memory 206916 kb
Host smart-4683efeb-00e3-4be1-a44a-6fcc5f533f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19834
2334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.198342334
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1856596914
Short name T2037
Test name
Test status
Simulation time 192673898 ps
CPU time 0.9 seconds
Started Jul 12 05:26:05 PM PDT 24
Finished Jul 12 05:26:07 PM PDT 24
Peak memory 206816 kb
Host smart-7eafe7bb-9994-4875-b854-e483a3a88b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
96914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1856596914
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2863044688
Short name T1877
Test name
Test status
Simulation time 182838291 ps
CPU time 0.8 seconds
Started Jul 12 05:26:08 PM PDT 24
Finished Jul 12 05:26:10 PM PDT 24
Peak memory 206776 kb
Host smart-1f5065b5-17c9-4d12-9085-7f94544b2b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28630
44688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2863044688
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3063880510
Short name T1019
Test name
Test status
Simulation time 182256120 ps
CPU time 0.83 seconds
Started Jul 12 05:26:23 PM PDT 24
Finished Jul 12 05:26:25 PM PDT 24
Peak memory 206720 kb
Host smart-4d6591c9-a2ad-47dc-9533-1786e571398c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
80510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3063880510
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2263143117
Short name T177
Test name
Test status
Simulation time 148326906 ps
CPU time 0.82 seconds
Started Jul 12 05:26:03 PM PDT 24
Finished Jul 12 05:26:05 PM PDT 24
Peak memory 206696 kb
Host smart-ad14d65e-2908-456c-92be-e054978325cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22631
43117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2263143117
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.633211180
Short name T1270
Test name
Test status
Simulation time 151712120 ps
CPU time 0.82 seconds
Started Jul 12 05:26:04 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 206812 kb
Host smart-3a278f69-8f03-4c8f-aa24-77c35cb412c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63321
1180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.633211180
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2527136293
Short name T519
Test name
Test status
Simulation time 190888174 ps
CPU time 0.88 seconds
Started Jul 12 05:26:06 PM PDT 24
Finished Jul 12 05:26:08 PM PDT 24
Peak memory 206800 kb
Host smart-ef415a21-b4bf-4c4c-9f8e-d0cca78789c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2527136293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2527136293
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3165953743
Short name T1386
Test name
Test status
Simulation time 202430946 ps
CPU time 0.97 seconds
Started Jul 12 05:26:05 PM PDT 24
Finished Jul 12 05:26:07 PM PDT 24
Peak memory 206820 kb
Host smart-fcb174e7-9866-4ed8-af73-b68be15f28db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31659
53743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3165953743
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.2566929242
Short name T1450
Test name
Test status
Simulation time 279447946 ps
CPU time 1.04 seconds
Started Jul 12 05:26:09 PM PDT 24
Finished Jul 12 05:26:12 PM PDT 24
Peak memory 206796 kb
Host smart-b455fed9-8834-47db-97e1-c7d19b322a62
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2566929242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.2566929242
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.433393885
Short name T196
Test name
Test status
Simulation time 234552560 ps
CPU time 0.96 seconds
Started Jul 12 05:26:05 PM PDT 24
Finished Jul 12 05:26:07 PM PDT 24
Peak memory 206820 kb
Host smart-98c9e868-1c1b-45e2-8f0d-19e36dd9601b
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=433393885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.433393885
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.418784805
Short name T974
Test name
Test status
Simulation time 179440101 ps
CPU time 0.8 seconds
Started Jul 12 05:26:06 PM PDT 24
Finished Jul 12 05:26:08 PM PDT 24
Peak memory 206808 kb
Host smart-b25fe1ed-9bdc-4fea-90a7-d9f52e372dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41878
4805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.418784805
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3832254344
Short name T963
Test name
Test status
Simulation time 67865817 ps
CPU time 0.72 seconds
Started Jul 12 05:26:03 PM PDT 24
Finished Jul 12 05:26:04 PM PDT 24
Peak memory 206696 kb
Host smart-14483d95-15e2-4e48-900b-c58445fc31cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38322
54344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3832254344
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3899652396
Short name T1624
Test name
Test status
Simulation time 18669882211 ps
CPU time 46.03 seconds
Started Jul 12 05:26:06 PM PDT 24
Finished Jul 12 05:26:53 PM PDT 24
Peak memory 207092 kb
Host smart-9e01856d-85e7-4bc9-b9d5-8db922e7b917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996
52396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3899652396
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2800912330
Short name T2068
Test name
Test status
Simulation time 181687221 ps
CPU time 0.88 seconds
Started Jul 12 05:26:03 PM PDT 24
Finished Jul 12 05:26:04 PM PDT 24
Peak memory 206704 kb
Host smart-9897370b-56d4-4335-8b7d-946d9097d80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28009
12330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2800912330
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3058452170
Short name T767
Test name
Test status
Simulation time 215229192 ps
CPU time 0.88 seconds
Started Jul 12 05:26:02 PM PDT 24
Finished Jul 12 05:26:03 PM PDT 24
Peak memory 206704 kb
Host smart-03ac3ebd-6086-415d-88e4-9a3cacfebc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30584
52170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3058452170
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.365750009
Short name T1210
Test name
Test status
Simulation time 4460058064 ps
CPU time 99.78 seconds
Started Jul 12 05:26:05 PM PDT 24
Finished Jul 12 05:27:46 PM PDT 24
Peak memory 207064 kb
Host smart-09a3d84d-8a50-4688-9523-b1cb70480eee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=365750009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.365750009
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.2459757292
Short name T650
Test name
Test status
Simulation time 8455379449 ps
CPU time 46.08 seconds
Started Jul 12 05:26:03 PM PDT 24
Finished Jul 12 05:26:49 PM PDT 24
Peak memory 206912 kb
Host smart-ee3d1668-5de7-4737-8453-6b0b3ff77745
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2459757292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2459757292
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3488915614
Short name T1996
Test name
Test status
Simulation time 209983737 ps
CPU time 0.86 seconds
Started Jul 12 05:26:04 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 206824 kb
Host smart-f2a665e0-604f-4901-9687-c5dbd6da93e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34889
15614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3488915614
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.4286795089
Short name T1420
Test name
Test status
Simulation time 170554513 ps
CPU time 0.87 seconds
Started Jul 12 05:26:05 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 206808 kb
Host smart-d8ac8bce-3dd5-4cec-8489-150c4af1257a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42867
95089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.4286795089
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.33895948
Short name T1388
Test name
Test status
Simulation time 202628761 ps
CPU time 0.81 seconds
Started Jul 12 05:26:03 PM PDT 24
Finished Jul 12 05:26:05 PM PDT 24
Peak memory 206668 kb
Host smart-3bcef86f-e6d7-43dd-914c-85c3c1dfcd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.33895948
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2635064135
Short name T191
Test name
Test status
Simulation time 1081902941 ps
CPU time 1.77 seconds
Started Jul 12 05:26:14 PM PDT 24
Finished Jul 12 05:26:17 PM PDT 24
Peak memory 224480 kb
Host smart-3be301a5-2304-4702-a372-72e73ca36e38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2635064135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2635064135
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2047952172
Short name T1923
Test name
Test status
Simulation time 242693471 ps
CPU time 0.87 seconds
Started Jul 12 05:26:08 PM PDT 24
Finished Jul 12 05:26:10 PM PDT 24
Peak memory 206820 kb
Host smart-f1727a83-1a05-4169-96c6-2f24bbdefca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20479
52172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2047952172
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3155951218
Short name T2025
Test name
Test status
Simulation time 154133676 ps
CPU time 0.79 seconds
Started Jul 12 05:26:09 PM PDT 24
Finished Jul 12 05:26:10 PM PDT 24
Peak memory 206808 kb
Host smart-9e9e9871-1772-490a-8762-880f59d536b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31559
51218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3155951218
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.754540314
Short name T1658
Test name
Test status
Simulation time 188902423 ps
CPU time 0.78 seconds
Started Jul 12 05:26:08 PM PDT 24
Finished Jul 12 05:26:10 PM PDT 24
Peak memory 206816 kb
Host smart-19547c67-2583-43d5-b80c-462abf6a781a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75454
0314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.754540314
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3234277488
Short name T347
Test name
Test status
Simulation time 210598193 ps
CPU time 0.86 seconds
Started Jul 12 05:26:05 PM PDT 24
Finished Jul 12 05:26:06 PM PDT 24
Peak memory 206808 kb
Host smart-62ffaa96-30c0-4868-b3ed-e289abf049fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32342
77488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3234277488
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.4116474536
Short name T1848
Test name
Test status
Simulation time 5714431465 ps
CPU time 161.52 seconds
Started Jul 12 05:26:08 PM PDT 24
Finished Jul 12 05:28:50 PM PDT 24
Peak memory 207052 kb
Host smart-b4c7422c-47b4-42aa-9aa8-5a14e48b972b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4116474536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.4116474536
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3283410452
Short name T973
Test name
Test status
Simulation time 174477551 ps
CPU time 0.8 seconds
Started Jul 12 05:26:12 PM PDT 24
Finished Jul 12 05:26:14 PM PDT 24
Peak memory 206824 kb
Host smart-ddc6c5f2-540a-4a7d-981c-dcc051f911fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
10452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3283410452
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2341294155
Short name T2022
Test name
Test status
Simulation time 199712853 ps
CPU time 0.9 seconds
Started Jul 12 05:26:06 PM PDT 24
Finished Jul 12 05:26:08 PM PDT 24
Peak memory 206800 kb
Host smart-c321d5ba-4234-4a8d-8255-881b45d31e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23412
94155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2341294155
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1392457755
Short name T1250
Test name
Test status
Simulation time 517862549 ps
CPU time 1.34 seconds
Started Jul 12 05:26:09 PM PDT 24
Finished Jul 12 05:26:11 PM PDT 24
Peak memory 206808 kb
Host smart-149bc58b-64de-42d7-8253-16d6b7fa447b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13924
57755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1392457755
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.312716147
Short name T1478
Test name
Test status
Simulation time 4806295381 ps
CPU time 47.08 seconds
Started Jul 12 05:26:15 PM PDT 24
Finished Jul 12 05:27:04 PM PDT 24
Peak memory 206972 kb
Host smart-387c7c98-379f-45e4-aaeb-e5c75fcef1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31271
6147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.312716147
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.611977637
Short name T2470
Test name
Test status
Simulation time 40342434 ps
CPU time 0.63 seconds
Started Jul 12 05:26:24 PM PDT 24
Finished Jul 12 05:26:26 PM PDT 24
Peak memory 206860 kb
Host smart-a10c68e0-34f7-49a5-846c-dc109af5a607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=611977637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.611977637
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2611781256
Short name T11
Test name
Test status
Simulation time 3408430745 ps
CPU time 4.12 seconds
Started Jul 12 05:26:11 PM PDT 24
Finished Jul 12 05:26:17 PM PDT 24
Peak memory 206884 kb
Host smart-d7128254-458a-4c61-9bd7-4f3f9f909026
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2611781256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.2611781256
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1976330503
Short name T1853
Test name
Test status
Simulation time 13344182893 ps
CPU time 12.7 seconds
Started Jul 12 05:26:13 PM PDT 24
Finished Jul 12 05:26:27 PM PDT 24
Peak memory 206756 kb
Host smart-d823fbc3-b064-48cb-ac69-47f60be0a755
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1976330503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1976330503
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3589071874
Short name T1285
Test name
Test status
Simulation time 23422702282 ps
CPU time 29.83 seconds
Started Jul 12 05:26:08 PM PDT 24
Finished Jul 12 05:26:38 PM PDT 24
Peak memory 206788 kb
Host smart-2a8a7316-95d3-4407-84f3-4e39d0339d0a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3589071874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.3589071874
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.283356662
Short name T680
Test name
Test status
Simulation time 180237187 ps
CPU time 0.8 seconds
Started Jul 12 05:26:09 PM PDT 24
Finished Jul 12 05:26:12 PM PDT 24
Peak memory 206812 kb
Host smart-c65a6f9a-acbc-430e-bec6-108c8d868d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28335
6662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.283356662
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2560674466
Short name T53
Test name
Test status
Simulation time 196113048 ps
CPU time 0.83 seconds
Started Jul 12 05:26:10 PM PDT 24
Finished Jul 12 05:26:12 PM PDT 24
Peak memory 206832 kb
Host smart-1db8f9d2-7d27-4041-97b5-424381dbc0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25606
74466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2560674466
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.15546602
Short name T58
Test name
Test status
Simulation time 162698152 ps
CPU time 0.82 seconds
Started Jul 12 05:26:10 PM PDT 24
Finished Jul 12 05:26:12 PM PDT 24
Peak memory 206668 kb
Host smart-babeb665-ac27-4500-bfda-36805f81ca80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15546
602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.15546602
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2850806867
Short name T1655
Test name
Test status
Simulation time 239825450 ps
CPU time 0.95 seconds
Started Jul 12 05:26:09 PM PDT 24
Finished Jul 12 05:26:11 PM PDT 24
Peak memory 206804 kb
Host smart-a9d36c87-7df9-4f89-8704-ed9f3fb5c9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28508
06867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2850806867
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1809305004
Short name T351
Test name
Test status
Simulation time 793642718 ps
CPU time 1.78 seconds
Started Jul 12 05:26:11 PM PDT 24
Finished Jul 12 05:26:14 PM PDT 24
Peak memory 206836 kb
Host smart-62f83d0e-cc76-42ee-8f74-57e5dcac7724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18093
05004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1809305004
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.1537484718
Short name T2027
Test name
Test status
Simulation time 21483831769 ps
CPU time 35.46 seconds
Started Jul 12 05:26:14 PM PDT 24
Finished Jul 12 05:26:52 PM PDT 24
Peak memory 207060 kb
Host smart-87a74741-bfbf-4b7f-91dc-d1c9afc8bf66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15374
84718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1537484718
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.549326924
Short name T2672
Test name
Test status
Simulation time 440530939 ps
CPU time 1.19 seconds
Started Jul 12 05:26:11 PM PDT 24
Finished Jul 12 05:26:14 PM PDT 24
Peak memory 206800 kb
Host smart-ceb24e94-b610-43c2-b262-ec43e043eb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54932
6924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.549326924
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1285113762
Short name T2055
Test name
Test status
Simulation time 163523384 ps
CPU time 0.79 seconds
Started Jul 12 05:26:08 PM PDT 24
Finished Jul 12 05:26:10 PM PDT 24
Peak memory 206792 kb
Host smart-eb6fdf49-24b6-401e-9101-6c1bf75f6892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12851
13762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1285113762
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3945247692
Short name T1404
Test name
Test status
Simulation time 36285305 ps
CPU time 0.67 seconds
Started Jul 12 05:26:11 PM PDT 24
Finished Jul 12 05:26:13 PM PDT 24
Peak memory 206828 kb
Host smart-06bbbfb5-382b-41c9-89b4-ebb7eaba501a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
47692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3945247692
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.920963246
Short name T1158
Test name
Test status
Simulation time 797611463 ps
CPU time 1.97 seconds
Started Jul 12 05:26:11 PM PDT 24
Finished Jul 12 05:26:14 PM PDT 24
Peak memory 206944 kb
Host smart-49997646-beab-4a10-b5c8-f0b3acc3b1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92096
3246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.920963246
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2575012805
Short name T327
Test name
Test status
Simulation time 385784152 ps
CPU time 2.06 seconds
Started Jul 12 05:26:12 PM PDT 24
Finished Jul 12 05:26:15 PM PDT 24
Peak memory 207176 kb
Host smart-32eb7fa0-910f-4614-a705-1bbd4e1b3e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25750
12805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2575012805
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.516720382
Short name T1356
Test name
Test status
Simulation time 117189667898 ps
CPU time 165.73 seconds
Started Jul 12 05:26:11 PM PDT 24
Finished Jul 12 05:28:58 PM PDT 24
Peak memory 206900 kb
Host smart-e1eb9166-2436-4c2f-a518-d6975714f520
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=516720382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.516720382
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.994299547
Short name T2528
Test name
Test status
Simulation time 111040913733 ps
CPU time 148.95 seconds
Started Jul 12 05:26:14 PM PDT 24
Finished Jul 12 05:28:45 PM PDT 24
Peak memory 207096 kb
Host smart-3783d32b-28b1-4bde-91cd-063f2d4077d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994299547 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.994299547
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.3647318859
Short name T566
Test name
Test status
Simulation time 115179079249 ps
CPU time 154.57 seconds
Started Jul 12 05:26:14 PM PDT 24
Finished Jul 12 05:28:50 PM PDT 24
Peak memory 207280 kb
Host smart-1c30edea-b01f-4964-b42c-283e790b4a79
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3647318859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3647318859
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.1563627933
Short name T723
Test name
Test status
Simulation time 84947763263 ps
CPU time 103.8 seconds
Started Jul 12 05:26:10 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 207072 kb
Host smart-3e957fe4-c570-44ef-866b-99106047a775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563627933 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1563627933
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3330662215
Short name T1919
Test name
Test status
Simulation time 119130272538 ps
CPU time 158.71 seconds
Started Jul 12 05:26:14 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 207004 kb
Host smart-2dcbebc6-63d9-4aed-a21f-c014e0786d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33306
62215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3330662215
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1338547686
Short name T1262
Test name
Test status
Simulation time 194113889 ps
CPU time 0.84 seconds
Started Jul 12 05:26:10 PM PDT 24
Finished Jul 12 05:26:13 PM PDT 24
Peak memory 206812 kb
Host smart-1749aeaa-66e3-476f-8978-7a52a1c100b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385
47686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1338547686
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1133994122
Short name T108
Test name
Test status
Simulation time 146783975 ps
CPU time 0.72 seconds
Started Jul 12 05:26:11 PM PDT 24
Finished Jul 12 05:26:13 PM PDT 24
Peak memory 206712 kb
Host smart-5d0e6aca-0b21-4147-924d-54d28646e95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11339
94122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1133994122
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3958189983
Short name T1466
Test name
Test status
Simulation time 206278584 ps
CPU time 0.91 seconds
Started Jul 12 05:26:14 PM PDT 24
Finished Jul 12 05:26:16 PM PDT 24
Peak memory 206836 kb
Host smart-5b69aff1-c94b-41ea-83c7-9e17478b5f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581
89983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3958189983
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.3460705885
Short name T210
Test name
Test status
Simulation time 5779725389 ps
CPU time 38.09 seconds
Started Jul 12 05:26:15 PM PDT 24
Finished Jul 12 05:26:55 PM PDT 24
Peak memory 207044 kb
Host smart-83848245-2c7d-47bc-ba02-abedc0605f46
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3460705885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3460705885
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1828209153
Short name T414
Test name
Test status
Simulation time 212142554 ps
CPU time 0.86 seconds
Started Jul 12 05:26:13 PM PDT 24
Finished Jul 12 05:26:15 PM PDT 24
Peak memory 206656 kb
Host smart-d07fdd50-1cf9-4e22-9565-db51e557df03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18282
09153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1828209153
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.679075855
Short name T1950
Test name
Test status
Simulation time 23252621735 ps
CPU time 24.06 seconds
Started Jul 12 05:26:10 PM PDT 24
Finished Jul 12 05:26:35 PM PDT 24
Peak memory 206832 kb
Host smart-d2bf8f9d-0d27-4f88-a86a-f023c8e18684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67907
5855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.679075855
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2875757912
Short name T2532
Test name
Test status
Simulation time 3316214977 ps
CPU time 3.82 seconds
Started Jul 12 05:26:12 PM PDT 24
Finished Jul 12 05:26:17 PM PDT 24
Peak memory 206840 kb
Host smart-cacadf96-b2c2-46de-aaac-78efa868a596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28757
57912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2875757912
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.1198688421
Short name T2183
Test name
Test status
Simulation time 12463439882 ps
CPU time 353.22 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 206972 kb
Host smart-6f1f268f-2f08-4f8e-8c42-fc5d320031b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
88421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1198688421
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2744040770
Short name T2332
Test name
Test status
Simulation time 3637482060 ps
CPU time 99.92 seconds
Started Jul 12 05:26:15 PM PDT 24
Finished Jul 12 05:27:57 PM PDT 24
Peak memory 206996 kb
Host smart-a5a25d65-9f8e-4827-8969-df258087d61b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2744040770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2744040770
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1801756740
Short name T1044
Test name
Test status
Simulation time 233437713 ps
CPU time 0.88 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:26:22 PM PDT 24
Peak memory 206824 kb
Host smart-36b65858-7518-4502-beea-78e8ae30e211
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1801756740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1801756740
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1016053920
Short name T2567
Test name
Test status
Simulation time 188003620 ps
CPU time 0.86 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:26:21 PM PDT 24
Peak memory 206832 kb
Host smart-1d04fbe6-8e05-40ef-b6d5-d4d2663cfd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10160
53920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1016053920
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2466851216
Short name T1834
Test name
Test status
Simulation time 5298864466 ps
CPU time 49.71 seconds
Started Jul 12 05:26:30 PM PDT 24
Finished Jul 12 05:27:20 PM PDT 24
Peak memory 207036 kb
Host smart-4d871aec-fac7-4be6-ae44-666bb40c695f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24668
51216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2466851216
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.814292255
Short name T2005
Test name
Test status
Simulation time 4788249145 ps
CPU time 137 seconds
Started Jul 12 05:26:16 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 206868 kb
Host smart-954c80cb-eb46-4945-88b1-7ca86b86d56c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=814292255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.814292255
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2743277596
Short name T1564
Test name
Test status
Simulation time 182182642 ps
CPU time 0.75 seconds
Started Jul 12 05:26:16 PM PDT 24
Finished Jul 12 05:26:19 PM PDT 24
Peak memory 206716 kb
Host smart-c2985977-85f0-49a3-a686-2aa680e51610
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2743277596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2743277596
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.118889116
Short name T2387
Test name
Test status
Simulation time 148838113 ps
CPU time 0.77 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:26:21 PM PDT 24
Peak memory 206824 kb
Host smart-75fa3a69-cec4-4fc5-b9a6-65eeb66a8d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
9116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.118889116
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1798561450
Short name T500
Test name
Test status
Simulation time 154780931 ps
CPU time 0.85 seconds
Started Jul 12 05:26:16 PM PDT 24
Finished Jul 12 05:26:19 PM PDT 24
Peak memory 206820 kb
Host smart-4b970de2-a7ad-46ed-a871-aa19a16210d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17985
61450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1798561450
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3044316322
Short name T1521
Test name
Test status
Simulation time 169167137 ps
CPU time 0.82 seconds
Started Jul 12 05:26:15 PM PDT 24
Finished Jul 12 05:26:18 PM PDT 24
Peak memory 206820 kb
Host smart-3cec0616-6680-4e77-8564-e18ed47ee4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30443
16322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3044316322
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.242602156
Short name T920
Test name
Test status
Simulation time 182635999 ps
CPU time 0.84 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:26:22 PM PDT 24
Peak memory 206796 kb
Host smart-2b67e17b-e5d7-47e9-980f-d134303fe772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24260
2156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.242602156
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2828978250
Short name T1903
Test name
Test status
Simulation time 167455162 ps
CPU time 0.79 seconds
Started Jul 12 05:26:18 PM PDT 24
Finished Jul 12 05:26:21 PM PDT 24
Peak memory 206800 kb
Host smart-b90a4764-b638-4053-82d7-3419bf0af831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28289
78250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2828978250
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.361065549
Short name T525
Test name
Test status
Simulation time 236772724 ps
CPU time 0.97 seconds
Started Jul 12 05:26:15 PM PDT 24
Finished Jul 12 05:26:18 PM PDT 24
Peak memory 206676 kb
Host smart-85ee2f77-0a5f-4f53-93bd-03cdb867b665
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=361065549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.361065549
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.2761369796
Short name T198
Test name
Test status
Simulation time 267550652 ps
CPU time 1.01 seconds
Started Jul 12 05:26:16 PM PDT 24
Finished Jul 12 05:26:20 PM PDT 24
Peak memory 206824 kb
Host smart-96029f45-dfdc-4c0e-a26f-435d4bff4417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27613
69796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.2761369796
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3303246469
Short name T27
Test name
Test status
Simulation time 34019836 ps
CPU time 0.66 seconds
Started Jul 12 05:26:27 PM PDT 24
Finished Jul 12 05:26:28 PM PDT 24
Peak memory 206816 kb
Host smart-322917e8-ca96-42a4-b911-d4cf6b3c037f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33032
46469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3303246469
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2575676081
Short name T2122
Test name
Test status
Simulation time 17644402554 ps
CPU time 45.17 seconds
Started Jul 12 05:26:16 PM PDT 24
Finished Jul 12 05:27:03 PM PDT 24
Peak memory 206928 kb
Host smart-e4c52e97-3137-4402-aeb4-5cbb26763f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25756
76081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2575676081
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2318141161
Short name T2631
Test name
Test status
Simulation time 154430150 ps
CPU time 0.82 seconds
Started Jul 12 05:26:14 PM PDT 24
Finished Jul 12 05:26:17 PM PDT 24
Peak memory 206820 kb
Host smart-a1131f98-92d5-4f8a-a9c5-e9d8f2ce2900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
41161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2318141161
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.870353866
Short name T1431
Test name
Test status
Simulation time 178590825 ps
CPU time 0.85 seconds
Started Jul 12 05:26:15 PM PDT 24
Finished Jul 12 05:26:18 PM PDT 24
Peak memory 206716 kb
Host smart-7d1f0580-1e15-4301-ae54-6c1bcff66c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87035
3866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.870353866
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.3401200261
Short name T1453
Test name
Test status
Simulation time 6520765020 ps
CPU time 23.93 seconds
Started Jul 12 05:26:17 PM PDT 24
Finished Jul 12 05:26:42 PM PDT 24
Peak memory 207112 kb
Host smart-4ee64dd3-4e98-4161-882f-b6ad0f9e97e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3401200261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3401200261
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3577955287
Short name T2558
Test name
Test status
Simulation time 12355114182 ps
CPU time 237.23 seconds
Started Jul 12 05:26:15 PM PDT 24
Finished Jul 12 05:30:15 PM PDT 24
Peak memory 207092 kb
Host smart-9d59a804-6204-4631-b1a6-99597ae02c7c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3577955287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3577955287
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2614696838
Short name T1556
Test name
Test status
Simulation time 175585144 ps
CPU time 0.85 seconds
Started Jul 12 05:26:17 PM PDT 24
Finished Jul 12 05:26:20 PM PDT 24
Peak memory 206808 kb
Host smart-9623489b-5bf0-4d41-b25e-c17e3993c61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
96838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2614696838
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.3572839616
Short name T2265
Test name
Test status
Simulation time 191082151 ps
CPU time 0.83 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:26:22 PM PDT 24
Peak memory 206820 kb
Host smart-72a56561-9b1d-4d0f-856b-8ba1316600a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35728
39616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.3572839616
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.4128629537
Short name T1777
Test name
Test status
Simulation time 168015655 ps
CPU time 0.85 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:26:21 PM PDT 24
Peak memory 206672 kb
Host smart-45e6f498-268d-4061-a002-6042afbb8303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41286
29537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.4128629537
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2406373109
Short name T72
Test name
Test status
Simulation time 164212448 ps
CPU time 0.84 seconds
Started Jul 12 05:26:23 PM PDT 24
Finished Jul 12 05:26:25 PM PDT 24
Peak memory 206660 kb
Host smart-bdbc71a6-a075-47e2-a989-7b9e3c04cece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063
73109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2406373109
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1976372791
Short name T203
Test name
Test status
Simulation time 441726352 ps
CPU time 1.42 seconds
Started Jul 12 05:26:20 PM PDT 24
Finished Jul 12 05:26:23 PM PDT 24
Peak memory 224416 kb
Host smart-99fd229a-5025-43d7-a4cb-1d89bef1d148
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1976372791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1976372791
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1322388666
Short name T2310
Test name
Test status
Simulation time 356939859 ps
CPU time 1.23 seconds
Started Jul 12 05:26:16 PM PDT 24
Finished Jul 12 05:26:19 PM PDT 24
Peak memory 206820 kb
Host smart-1c58f95e-c321-4673-858c-b6343f93d1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13223
88666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1322388666
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3734256921
Short name T1941
Test name
Test status
Simulation time 315305483 ps
CPU time 0.98 seconds
Started Jul 12 05:26:19 PM PDT 24
Finished Jul 12 05:26:21 PM PDT 24
Peak memory 206756 kb
Host smart-ce3c39c6-85d3-43e4-98a7-e5a611dcb1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37342
56921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3734256921
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.4016947163
Short name T2085
Test name
Test status
Simulation time 160083196 ps
CPU time 0.78 seconds
Started Jul 12 05:26:14 PM PDT 24
Finished Jul 12 05:26:16 PM PDT 24
Peak memory 206816 kb
Host smart-e53e8fb0-a905-4cc7-b46e-fc5f6c230d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40169
47163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.4016947163
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.6149921
Short name T43
Test name
Test status
Simulation time 138549453 ps
CPU time 0.78 seconds
Started Jul 12 05:26:20 PM PDT 24
Finished Jul 12 05:26:22 PM PDT 24
Peak memory 206768 kb
Host smart-269cef55-e79f-4c30-b9b0-ee231d38cf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61499
21 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.6149921
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2163035055
Short name T904
Test name
Test status
Simulation time 187307826 ps
CPU time 0.86 seconds
Started Jul 12 05:26:18 PM PDT 24
Finished Jul 12 05:26:21 PM PDT 24
Peak memory 206760 kb
Host smart-3a6fd297-949f-4627-8f35-e0e1efa716ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21630
35055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2163035055
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2670750011
Short name T2192
Test name
Test status
Simulation time 5927121783 ps
CPU time 166.2 seconds
Started Jul 12 05:26:20 PM PDT 24
Finished Jul 12 05:29:08 PM PDT 24
Peak memory 207020 kb
Host smart-b3d3d9fe-f5eb-4c60-b345-a1ab1886fec6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2670750011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2670750011
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1371411685
Short name T1088
Test name
Test status
Simulation time 152848610 ps
CPU time 0.77 seconds
Started Jul 12 05:26:24 PM PDT 24
Finished Jul 12 05:26:27 PM PDT 24
Peak memory 206824 kb
Host smart-3af5141e-c696-4722-9e0b-052ec22fa472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13714
11685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1371411685
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.4044689221
Short name T100
Test name
Test status
Simulation time 216063682 ps
CPU time 0.88 seconds
Started Jul 12 05:26:20 PM PDT 24
Finished Jul 12 05:26:22 PM PDT 24
Peak memory 206712 kb
Host smart-27ae6c42-88ee-483f-8b7d-d4029d2aa532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40446
89221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.4044689221
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.2965961854
Short name T1358
Test name
Test status
Simulation time 989199360 ps
CPU time 2.29 seconds
Started Jul 12 05:26:23 PM PDT 24
Finished Jul 12 05:26:27 PM PDT 24
Peak memory 207004 kb
Host smart-1aceadaa-ea10-49ed-9bd2-805960e55a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29659
61854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2965961854
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2915364102
Short name T1059
Test name
Test status
Simulation time 3158170464 ps
CPU time 22.34 seconds
Started Jul 12 05:26:24 PM PDT 24
Finished Jul 12 05:26:49 PM PDT 24
Peak memory 207088 kb
Host smart-bcfbd2f4-e100-47b4-b9c5-6210229d371c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
64102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2915364102
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2973960965
Short name T2488
Test name
Test status
Simulation time 11545220892 ps
CPU time 300.3 seconds
Started Jul 12 05:26:22 PM PDT 24
Finished Jul 12 05:31:23 PM PDT 24
Peak memory 207056 kb
Host smart-e3a3ebd4-34dd-4ded-be0c-9f010babdfee
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2973960965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2973960965
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3050899569
Short name T1095
Test name
Test status
Simulation time 84434407 ps
CPU time 0.79 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:11 PM PDT 24
Peak memory 206732 kb
Host smart-222158b8-a580-4ff8-9bae-3bc1155276dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3050899569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3050899569
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2024666897
Short name T560
Test name
Test status
Simulation time 4138642034 ps
CPU time 4.89 seconds
Started Jul 12 05:27:58 PM PDT 24
Finished Jul 12 05:28:05 PM PDT 24
Peak memory 206836 kb
Host smart-8b489f7b-db15-491d-a804-cdcedbf26328
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2024666897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2024666897
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3393923354
Short name T2465
Test name
Test status
Simulation time 13321208595 ps
CPU time 14.63 seconds
Started Jul 12 05:28:03 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 206924 kb
Host smart-049ad431-b8c0-4a34-bb50-74dfc4723260
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3393923354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3393923354
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2894801582
Short name T1455
Test name
Test status
Simulation time 23405292537 ps
CPU time 22.95 seconds
Started Jul 12 05:27:56 PM PDT 24
Finished Jul 12 05:28:20 PM PDT 24
Peak memory 206872 kb
Host smart-0f2c780a-2a19-41e9-bfb4-8155d00bb084
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2894801582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.2894801582
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1913718398
Short name T668
Test name
Test status
Simulation time 206241366 ps
CPU time 0.94 seconds
Started Jul 12 05:28:01 PM PDT 24
Finished Jul 12 05:28:03 PM PDT 24
Peak memory 206816 kb
Host smart-6cb44a61-375e-461f-a575-5e813e0018df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19137
18398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1913718398
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1443773606
Short name T1009
Test name
Test status
Simulation time 146127920 ps
CPU time 0.82 seconds
Started Jul 12 05:27:59 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 206816 kb
Host smart-25854333-52df-4d73-9bbe-49b9fca2b1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14437
73606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1443773606
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1387113630
Short name T895
Test name
Test status
Simulation time 457484369 ps
CPU time 1.47 seconds
Started Jul 12 05:28:03 PM PDT 24
Finished Jul 12 05:28:05 PM PDT 24
Peak memory 206956 kb
Host smart-4c2b5cd5-1abb-49ba-9edc-242dfab3a072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13871
13630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1387113630
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1443405860
Short name T102
Test name
Test status
Simulation time 859728177 ps
CPU time 1.87 seconds
Started Jul 12 05:28:01 PM PDT 24
Finished Jul 12 05:28:05 PM PDT 24
Peak memory 206904 kb
Host smart-e48dee64-a4c9-4f5b-bdad-991e788eb0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14434
05860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1443405860
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1473633842
Short name T2299
Test name
Test status
Simulation time 14505663270 ps
CPU time 30.46 seconds
Started Jul 12 05:28:47 PM PDT 24
Finished Jul 12 05:29:19 PM PDT 24
Peak memory 206972 kb
Host smart-c3da6267-c663-4c9b-9bd1-ddbf8f3a444e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
33842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1473633842
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3154852355
Short name T2304
Test name
Test status
Simulation time 515781002 ps
CPU time 1.41 seconds
Started Jul 12 05:28:01 PM PDT 24
Finished Jul 12 05:28:03 PM PDT 24
Peak memory 206824 kb
Host smart-cc646ee3-6663-4acd-a7f4-5937984e768c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31548
52355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3154852355
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.656033240
Short name T330
Test name
Test status
Simulation time 137318762 ps
CPU time 0.78 seconds
Started Jul 12 05:27:58 PM PDT 24
Finished Jul 12 05:28:00 PM PDT 24
Peak memory 206812 kb
Host smart-2bc19585-18e2-4eb6-a2a4-45f7734b1ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65603
3240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.656033240
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.654527864
Short name T2227
Test name
Test status
Simulation time 42157695 ps
CPU time 0.66 seconds
Started Jul 12 05:27:58 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 206804 kb
Host smart-895d0220-8a65-4c23-9bb0-d9fe4d620112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65452
7864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.654527864
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2362788357
Short name T1774
Test name
Test status
Simulation time 836007132 ps
CPU time 1.9 seconds
Started Jul 12 05:27:57 PM PDT 24
Finished Jul 12 05:28:00 PM PDT 24
Peak memory 206944 kb
Host smart-b8b74ca3-e2eb-4470-8c44-cb69ebefff7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23627
88357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2362788357
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1692129996
Short name T469
Test name
Test status
Simulation time 194880266 ps
CPU time 1.78 seconds
Started Jul 12 05:27:59 PM PDT 24
Finished Jul 12 05:28:02 PM PDT 24
Peak memory 206868 kb
Host smart-472e5a4a-76cd-40bb-8b3b-6e1ad27fe8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16921
29996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1692129996
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.937048186
Short name T2024
Test name
Test status
Simulation time 298176014 ps
CPU time 0.94 seconds
Started Jul 12 05:27:58 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 206740 kb
Host smart-90c4ca44-4309-4dd6-ab81-d0e62816a80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93704
8186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.937048186
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.172332435
Short name T1947
Test name
Test status
Simulation time 142721520 ps
CPU time 0.75 seconds
Started Jul 12 05:28:01 PM PDT 24
Finished Jul 12 05:28:03 PM PDT 24
Peak memory 206972 kb
Host smart-46864273-ea07-43a3-90ba-b20eb8cc5ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17233
2435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.172332435
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3188730528
Short name T694
Test name
Test status
Simulation time 178130030 ps
CPU time 0.83 seconds
Started Jul 12 05:27:57 PM PDT 24
Finished Jul 12 05:27:59 PM PDT 24
Peak memory 206816 kb
Host smart-7ad2f0fc-d5c7-43de-83ca-437258f9949a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887
30528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3188730528
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.735197779
Short name T2611
Test name
Test status
Simulation time 9345921226 ps
CPU time 67.64 seconds
Started Jul 12 05:27:58 PM PDT 24
Finished Jul 12 05:29:07 PM PDT 24
Peak memory 206944 kb
Host smart-85866a1d-1326-40ee-b0c9-4c1e2dc2d524
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=735197779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.735197779
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.3267506333
Short name T2566
Test name
Test status
Simulation time 10303648758 ps
CPU time 39.61 seconds
Started Jul 12 05:27:59 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 207064 kb
Host smart-0ce678fd-a484-4155-bdf1-e33cc23b1bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32675
06333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.3267506333
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.2153069362
Short name T1024
Test name
Test status
Simulation time 219433218 ps
CPU time 0.88 seconds
Started Jul 12 05:27:59 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 206816 kb
Host smart-745064c2-18a0-4561-84e2-6cf8b074bcee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530
69362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2153069362
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.250834281
Short name T893
Test name
Test status
Simulation time 23341164313 ps
CPU time 23.34 seconds
Started Jul 12 05:28:00 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206880 kb
Host smart-a351db07-074c-411f-8e31-876b28c4fc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25083
4281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.250834281
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.4053647359
Short name T2325
Test name
Test status
Simulation time 3263007843 ps
CPU time 4.38 seconds
Started Jul 12 05:27:58 PM PDT 24
Finished Jul 12 05:28:04 PM PDT 24
Peak memory 206876 kb
Host smart-9eab4025-a2ec-4250-b94d-39eabce6790b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40536
47359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.4053647359
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3724981913
Short name T395
Test name
Test status
Simulation time 9815581531 ps
CPU time 69.94 seconds
Started Jul 12 05:28:01 PM PDT 24
Finished Jul 12 05:29:13 PM PDT 24
Peak memory 207092 kb
Host smart-a626f829-dcb1-41f0-afa7-4df21153b4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37249
81913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3724981913
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.2000442214
Short name T716
Test name
Test status
Simulation time 6264816364 ps
CPU time 46.99 seconds
Started Jul 12 05:27:59 PM PDT 24
Finished Jul 12 05:28:47 PM PDT 24
Peak memory 206948 kb
Host smart-1b430371-ef6d-4224-812f-914e6e4f2f53
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2000442214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.2000442214
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.4109456018
Short name T2096
Test name
Test status
Simulation time 241825996 ps
CPU time 0.99 seconds
Started Jul 12 05:28:04 PM PDT 24
Finished Jul 12 05:28:07 PM PDT 24
Peak memory 206804 kb
Host smart-1915035a-17c5-4444-8f0b-a19cfff74980
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4109456018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.4109456018
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2257009884
Short name T393
Test name
Test status
Simulation time 207589084 ps
CPU time 0.87 seconds
Started Jul 12 05:28:04 PM PDT 24
Finished Jul 12 05:28:07 PM PDT 24
Peak memory 206772 kb
Host smart-7020a6d2-5f47-47a2-8d91-f9200b06db11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22570
09884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2257009884
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3147004037
Short name T1613
Test name
Test status
Simulation time 5045676426 ps
CPU time 49.66 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:56 PM PDT 24
Peak memory 207028 kb
Host smart-d3789834-74cd-4b4d-961f-b378a3600791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31470
04037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3147004037
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1867708548
Short name T413
Test name
Test status
Simulation time 3784226750 ps
CPU time 26.21 seconds
Started Jul 12 05:28:06 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 207004 kb
Host smart-ff41f4d8-282c-4fd6-b398-44e53326594c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1867708548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1867708548
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2458571708
Short name T1445
Test name
Test status
Simulation time 149050506 ps
CPU time 0.78 seconds
Started Jul 12 05:28:06 PM PDT 24
Finished Jul 12 05:28:10 PM PDT 24
Peak memory 206936 kb
Host smart-1ebdd299-fc42-4e34-b233-834b67da4a7a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2458571708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2458571708
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.417101615
Short name T2585
Test name
Test status
Simulation time 165438074 ps
CPU time 0.83 seconds
Started Jul 12 05:28:02 PM PDT 24
Finished Jul 12 05:28:04 PM PDT 24
Peak memory 206708 kb
Host smart-426daa4d-d5e6-4795-b100-93299e8af8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41710
1615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.417101615
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3288975336
Short name T588
Test name
Test status
Simulation time 183823938 ps
CPU time 0.85 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:07 PM PDT 24
Peak memory 206808 kb
Host smart-8a1c62b2-6a2e-4d72-87c7-2f59c85fb75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32889
75336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3288975336
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2586114361
Short name T1114
Test name
Test status
Simulation time 161079306 ps
CPU time 0.78 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:08 PM PDT 24
Peak memory 207036 kb
Host smart-d7e67b44-ba51-4820-961b-3749ba85bef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25861
14361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2586114361
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.4074499029
Short name T2023
Test name
Test status
Simulation time 188343483 ps
CPU time 0.83 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 206720 kb
Host smart-56c52021-52cb-4ba4-b186-9c8d9c52b037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40744
99029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.4074499029
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.947163296
Short name T2553
Test name
Test status
Simulation time 153144594 ps
CPU time 0.79 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:08 PM PDT 24
Peak memory 206796 kb
Host smart-8579a651-a4b4-4ddb-ab69-43438538f88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94716
3296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.947163296
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3886134972
Short name T1551
Test name
Test status
Simulation time 196617714 ps
CPU time 0.88 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:09 PM PDT 24
Peak memory 206820 kb
Host smart-25458563-109e-4faf-96d5-674e6cb54483
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3886134972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3886134972
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2558314259
Short name T670
Test name
Test status
Simulation time 190062910 ps
CPU time 0.79 seconds
Started Jul 12 05:28:03 PM PDT 24
Finished Jul 12 05:28:05 PM PDT 24
Peak memory 206804 kb
Host smart-778c042a-cac1-435f-a99c-c75a8574f3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25583
14259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2558314259
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.577448143
Short name T1154
Test name
Test status
Simulation time 45160494 ps
CPU time 0.7 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:10 PM PDT 24
Peak memory 206696 kb
Host smart-9f3d288e-04a2-4838-b9de-11145ee8f48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57744
8143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.577448143
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2368979751
Short name T2388
Test name
Test status
Simulation time 5684617089 ps
CPU time 12.84 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:22 PM PDT 24
Peak memory 207112 kb
Host smart-33f823bf-6d59-46c3-8f40-44974639aef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23689
79751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2368979751
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.542953805
Short name T1570
Test name
Test status
Simulation time 236559681 ps
CPU time 0.92 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:10 PM PDT 24
Peak memory 206808 kb
Host smart-a3ad8836-eeb3-48bb-be47-ba092d97070b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54295
3805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.542953805
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1568147069
Short name T1246
Test name
Test status
Simulation time 187737928 ps
CPU time 0.87 seconds
Started Jul 12 05:28:16 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 206688 kb
Host smart-d5047b1a-2520-4be8-894c-168c2ec0f467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15681
47069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1568147069
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3691871158
Short name T2015
Test name
Test status
Simulation time 171395171 ps
CPU time 0.9 seconds
Started Jul 12 05:28:04 PM PDT 24
Finished Jul 12 05:28:07 PM PDT 24
Peak memory 206796 kb
Host smart-ca237a6f-a9f4-40dd-8f04-335b0ef24de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36918
71158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3691871158
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2355550270
Short name T585
Test name
Test status
Simulation time 157466916 ps
CPU time 0.75 seconds
Started Jul 12 05:28:04 PM PDT 24
Finished Jul 12 05:28:06 PM PDT 24
Peak memory 206824 kb
Host smart-fd827366-7070-4926-be25-ae1de93c04b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23555
50270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2355550270
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2501343154
Short name T1849
Test name
Test status
Simulation time 160333929 ps
CPU time 0.77 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 206712 kb
Host smart-77172b8a-35f9-4a7e-8974-7ffce1df5082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25013
43154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2501343154
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3904796700
Short name T1412
Test name
Test status
Simulation time 203257790 ps
CPU time 0.82 seconds
Started Jul 12 05:28:06 PM PDT 24
Finished Jul 12 05:28:09 PM PDT 24
Peak memory 206820 kb
Host smart-6b0ddb22-3f17-4798-b0b2-b2e3efb5f12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39047
96700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3904796700
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1448419814
Short name T2241
Test name
Test status
Simulation time 256775860 ps
CPU time 1.11 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 206716 kb
Host smart-2add784f-a5e5-469a-bb74-df1536ae225b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14484
19814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1448419814
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2843019057
Short name T617
Test name
Test status
Simulation time 7048624484 ps
CPU time 48.34 seconds
Started Jul 12 05:28:09 PM PDT 24
Finished Jul 12 05:28:59 PM PDT 24
Peak memory 207024 kb
Host smart-c360933d-dcb2-46c7-8c4f-abd863cdf123
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2843019057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2843019057
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.788142919
Short name T2677
Test name
Test status
Simulation time 182160726 ps
CPU time 0.86 seconds
Started Jul 12 05:28:04 PM PDT 24
Finished Jul 12 05:28:05 PM PDT 24
Peak memory 206716 kb
Host smart-8c7ebee2-8fe9-4f12-88fd-970e2f799828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78814
2919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.788142919
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1451458788
Short name T549
Test name
Test status
Simulation time 180566500 ps
CPU time 0.85 seconds
Started Jul 12 05:28:08 PM PDT 24
Finished Jul 12 05:28:11 PM PDT 24
Peak memory 206820 kb
Host smart-96d3afe7-2ed0-4773-a8dd-01514b7ef4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14514
58788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1451458788
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.2914886944
Short name T1579
Test name
Test status
Simulation time 901516343 ps
CPU time 2.02 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:09 PM PDT 24
Peak memory 206916 kb
Host smart-ea48543e-88f4-44a4-80e1-67f53333a9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148
86944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.2914886944
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.732461767
Short name T1215
Test name
Test status
Simulation time 4018211424 ps
CPU time 38.5 seconds
Started Jul 12 05:28:06 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 207076 kb
Host smart-6f3c24c5-0d8b-4288-b958-7c77f9591575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73246
1767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.732461767
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3266588462
Short name T1688
Test name
Test status
Simulation time 41499445 ps
CPU time 0.65 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:16 PM PDT 24
Peak memory 206760 kb
Host smart-d7def687-f3f4-40c1-b3eb-8132050cc8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3266588462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3266588462
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2177330648
Short name T461
Test name
Test status
Simulation time 13522967537 ps
CPU time 12.77 seconds
Started Jul 12 05:28:16 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 206876 kb
Host smart-2f8bd481-15b7-4676-9e95-f583617298dc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2177330648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2177330648
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.2434382304
Short name T2478
Test name
Test status
Simulation time 23314946731 ps
CPU time 22.48 seconds
Started Jul 12 05:28:04 PM PDT 24
Finished Jul 12 05:28:29 PM PDT 24
Peak memory 207072 kb
Host smart-d6e13c44-36fd-4150-9ac8-3d0383229da7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2434382304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.2434382304
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3745939141
Short name T957
Test name
Test status
Simulation time 185002701 ps
CPU time 0.88 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:10 PM PDT 24
Peak memory 206808 kb
Host smart-24063f0d-6be0-4700-86c1-17ea0e9421f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37459
39141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3745939141
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2978187766
Short name T2658
Test name
Test status
Simulation time 147422829 ps
CPU time 0.78 seconds
Started Jul 12 05:28:04 PM PDT 24
Finished Jul 12 05:28:07 PM PDT 24
Peak memory 206820 kb
Host smart-287f5510-d622-478d-9a38-a78fe41ff388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29781
87766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2978187766
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.158067485
Short name T508
Test name
Test status
Simulation time 505100121 ps
CPU time 1.48 seconds
Started Jul 12 05:28:04 PM PDT 24
Finished Jul 12 05:28:06 PM PDT 24
Peak memory 206812 kb
Host smart-52da05a2-cc60-4516-bb2e-78e86f4ff565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
7485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.158067485
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.305796471
Short name T1042
Test name
Test status
Simulation time 772490864 ps
CPU time 1.92 seconds
Started Jul 12 05:28:10 PM PDT 24
Finished Jul 12 05:28:13 PM PDT 24
Peak memory 207008 kb
Host smart-b32224f8-4de2-47be-8b43-d850f1202a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
6471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.305796471
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2254860660
Short name T2243
Test name
Test status
Simulation time 9021989078 ps
CPU time 16.48 seconds
Started Jul 12 05:28:06 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206984 kb
Host smart-b137f9a8-15df-4a9b-9858-255bf7dfa611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22548
60660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2254860660
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2034438291
Short name T1901
Test name
Test status
Simulation time 386730143 ps
CPU time 1.31 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:09 PM PDT 24
Peak memory 206824 kb
Host smart-50f1995b-e5f0-406f-8d96-695adf36cbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20344
38291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2034438291
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.176662636
Short name T786
Test name
Test status
Simulation time 177415266 ps
CPU time 0.82 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:10 PM PDT 24
Peak memory 206816 kb
Host smart-a220df61-42ba-4b3b-8b71-e12b95358a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17666
2636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.176662636
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3875808461
Short name T2638
Test name
Test status
Simulation time 37066598 ps
CPU time 0.66 seconds
Started Jul 12 05:28:06 PM PDT 24
Finished Jul 12 05:28:09 PM PDT 24
Peak memory 206808 kb
Host smart-144cb7f3-9fac-4bbd-8d27-a53e700b96d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38758
08461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3875808461
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2670574200
Short name T2475
Test name
Test status
Simulation time 1085399437 ps
CPU time 2.31 seconds
Started Jul 12 05:28:10 PM PDT 24
Finished Jul 12 05:28:13 PM PDT 24
Peak memory 207016 kb
Host smart-58cb2871-38b8-45e8-aa3a-18be23e4a4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26705
74200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2670574200
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3240670307
Short name T2734
Test name
Test status
Simulation time 184530917 ps
CPU time 2.03 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:11 PM PDT 24
Peak memory 206956 kb
Host smart-a402c406-7d64-4b99-9d36-78628ecfb2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32406
70307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3240670307
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.801695274
Short name T1555
Test name
Test status
Simulation time 193679204 ps
CPU time 0.86 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:10 PM PDT 24
Peak memory 206924 kb
Host smart-77f677de-b63e-4194-a2df-0a8d19b19f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80169
5274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.801695274
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1942166854
Short name T2247
Test name
Test status
Simulation time 141854673 ps
CPU time 0.72 seconds
Started Jul 12 05:28:11 PM PDT 24
Finished Jul 12 05:28:13 PM PDT 24
Peak memory 206760 kb
Host smart-31119fab-b9ec-4749-a80e-66b26f02f352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19421
66854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1942166854
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2986064506
Short name T2212
Test name
Test status
Simulation time 200323889 ps
CPU time 0.87 seconds
Started Jul 12 05:28:13 PM PDT 24
Finished Jul 12 05:28:14 PM PDT 24
Peak memory 206980 kb
Host smart-7d507e9a-79b9-407e-b232-0b4efa20e171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860
64506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2986064506
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.3264342269
Short name T1354
Test name
Test status
Simulation time 12962103520 ps
CPU time 114.4 seconds
Started Jul 12 05:28:16 PM PDT 24
Finished Jul 12 05:30:12 PM PDT 24
Peak memory 207084 kb
Host smart-1325779e-bd24-46d4-bb08-96b7a59b31ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32643
42269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.3264342269
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.4275954558
Short name T1204
Test name
Test status
Simulation time 239397605 ps
CPU time 0.92 seconds
Started Jul 12 05:28:16 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 206812 kb
Host smart-431777eb-7321-497a-ae06-1d5fe2bd8a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42759
54558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.4275954558
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3615595970
Short name T2131
Test name
Test status
Simulation time 23332495542 ps
CPU time 24.5 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 206780 kb
Host smart-6fafc6a4-d703-4bdd-9623-b3b80023121d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36155
95970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3615595970
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.865585842
Short name T1593
Test name
Test status
Simulation time 3308713231 ps
CPU time 4.13 seconds
Started Jul 12 05:28:13 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 206888 kb
Host smart-bafbaf04-4365-4b4d-a0f8-cd26177ae058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86558
5842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.865585842
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2165040391
Short name T2066
Test name
Test status
Simulation time 8098345854 ps
CPU time 59.99 seconds
Started Jul 12 05:28:13 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 207124 kb
Host smart-4996e40e-1d60-48ca-a21b-45a1223ad31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21650
40391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2165040391
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3550432599
Short name T1836
Test name
Test status
Simulation time 4482018208 ps
CPU time 115.8 seconds
Started Jul 12 05:28:13 PM PDT 24
Finished Jul 12 05:30:09 PM PDT 24
Peak memory 207000 kb
Host smart-c96800e6-0808-4f92-a077-fae48184151d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3550432599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3550432599
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.3364886998
Short name T482
Test name
Test status
Simulation time 251471629 ps
CPU time 0.99 seconds
Started Jul 12 05:28:20 PM PDT 24
Finished Jul 12 05:28:22 PM PDT 24
Peak memory 206836 kb
Host smart-92e8e904-ad12-493a-bcac-579af55cf331
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3364886998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.3364886998
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.969223004
Short name T1134
Test name
Test status
Simulation time 191096458 ps
CPU time 0.87 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 206800 kb
Host smart-eb7dc715-5df4-44cb-bafa-f028d4db5c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96922
3004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.969223004
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2008946471
Short name T407
Test name
Test status
Simulation time 7246248373 ps
CPU time 202.77 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:31:40 PM PDT 24
Peak memory 207020 kb
Host smart-c74f3b7d-878c-48b0-907a-136302389c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20089
46471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2008946471
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.2186034723
Short name T1364
Test name
Test status
Simulation time 4445639152 ps
CPU time 38.06 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:53 PM PDT 24
Peak memory 207008 kb
Host smart-b10541d6-37f8-4308-9a7f-7ce8869cab49
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2186034723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.2186034723
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.511020286
Short name T1073
Test name
Test status
Simulation time 146257825 ps
CPU time 0.8 seconds
Started Jul 12 05:28:18 PM PDT 24
Finished Jul 12 05:28:21 PM PDT 24
Peak memory 206684 kb
Host smart-dc5ae951-1a10-405e-a06a-737f588192d9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=511020286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.511020286
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.4108112244
Short name T2190
Test name
Test status
Simulation time 150418774 ps
CPU time 0.81 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:17 PM PDT 24
Peak memory 206820 kb
Host smart-6e3b2cf0-48bf-4e48-b01c-a50f02eec807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41081
12244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.4108112244
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3248996788
Short name T2713
Test name
Test status
Simulation time 210144083 ps
CPU time 0.85 seconds
Started Jul 12 05:28:20 PM PDT 24
Finished Jul 12 05:28:22 PM PDT 24
Peak memory 206816 kb
Host smart-0265c7eb-2612-4af0-a4a6-31548986bf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32489
96788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3248996788
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1921942799
Short name T2656
Test name
Test status
Simulation time 155827772 ps
CPU time 0.79 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:17 PM PDT 24
Peak memory 206924 kb
Host smart-4c2e3700-99c0-4872-8047-26cce04693a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19219
42799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1921942799
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1131812454
Short name T938
Test name
Test status
Simulation time 170772217 ps
CPU time 0.79 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:17 PM PDT 24
Peak memory 206772 kb
Host smart-71d1c733-e8fa-489b-8f23-46aeac37ab72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11318
12454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1131812454
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2055961906
Short name T172
Test name
Test status
Simulation time 157740691 ps
CPU time 0.81 seconds
Started Jul 12 05:28:20 PM PDT 24
Finished Jul 12 05:28:21 PM PDT 24
Peak memory 206696 kb
Host smart-708c142b-9dd5-4556-92f9-608c6fe58794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20559
61906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2055961906
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3047991614
Short name T44
Test name
Test status
Simulation time 196819621 ps
CPU time 0.9 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 206632 kb
Host smart-ef7f0b04-633e-4c86-acd6-d23d4d6e6f0b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3047991614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3047991614
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1661884752
Short name T638
Test name
Test status
Simulation time 147316691 ps
CPU time 0.82 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:16 PM PDT 24
Peak memory 206820 kb
Host smart-917293db-5010-4962-ab4d-e7d847e6bb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16618
84752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1661884752
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1493169843
Short name T2239
Test name
Test status
Simulation time 39280791 ps
CPU time 0.7 seconds
Started Jul 12 05:28:16 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 206816 kb
Host smart-cdc31d74-8c0f-4670-bfab-8ad574824b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14931
69843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1493169843
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.887778795
Short name T2321
Test name
Test status
Simulation time 17113753546 ps
CPU time 36.85 seconds
Started Jul 12 05:28:20 PM PDT 24
Finished Jul 12 05:28:58 PM PDT 24
Peak memory 206964 kb
Host smart-018e0133-cb3b-4e2a-b5de-7880b21c0c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88777
8795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.887778795
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.820793751
Short name T1155
Test name
Test status
Simulation time 172938287 ps
CPU time 0.78 seconds
Started Jul 12 05:28:12 PM PDT 24
Finished Jul 12 05:28:13 PM PDT 24
Peak memory 206776 kb
Host smart-2dce2e4e-8f3b-4b0c-8209-2151a914bac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82079
3751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.820793751
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1305070508
Short name T1028
Test name
Test status
Simulation time 223529903 ps
CPU time 0.89 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 206792 kb
Host smart-5bd8e871-1abf-47d9-9615-c276903e0dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13050
70508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1305070508
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2187557337
Short name T535
Test name
Test status
Simulation time 230348097 ps
CPU time 0.88 seconds
Started Jul 12 05:28:16 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 206796 kb
Host smart-96e4591e-8ee3-4d86-a86f-1045139149ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21875
57337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2187557337
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1999246899
Short name T1181
Test name
Test status
Simulation time 215929267 ps
CPU time 0.86 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:17 PM PDT 24
Peak memory 206716 kb
Host smart-78e4482f-f921-400e-9a3a-d890fd7a6427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19992
46899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1999246899
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2410744949
Short name T1597
Test name
Test status
Simulation time 140426889 ps
CPU time 0.77 seconds
Started Jul 12 05:28:16 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 206804 kb
Host smart-1d0f4ed9-7c1f-4071-9d8d-21a66be93d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
44949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2410744949
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1097067615
Short name T1713
Test name
Test status
Simulation time 155113609 ps
CPU time 0.88 seconds
Started Jul 12 05:28:19 PM PDT 24
Finished Jul 12 05:28:21 PM PDT 24
Peak memory 206692 kb
Host smart-2d75f21f-42d7-4320-afd4-f179f1bc7568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10970
67615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1097067615
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3106150912
Short name T949
Test name
Test status
Simulation time 170536628 ps
CPU time 0.79 seconds
Started Jul 12 05:28:20 PM PDT 24
Finished Jul 12 05:28:21 PM PDT 24
Peak memory 206820 kb
Host smart-8c72c33a-c5c3-4c13-9970-feba725c0493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31061
50912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3106150912
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.469893100
Short name T1290
Test name
Test status
Simulation time 267502482 ps
CPU time 1 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:17 PM PDT 24
Peak memory 206816 kb
Host smart-69912f4e-8368-4c12-8eef-89ac2bba7500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46989
3100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.469893100
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2246852423
Short name T1768
Test name
Test status
Simulation time 4698044197 ps
CPU time 124.88 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:30:20 PM PDT 24
Peak memory 207000 kb
Host smart-320dac48-16fd-4d7c-a101-43b330acbec1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2246852423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2246852423
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2750877812
Short name T275
Test name
Test status
Simulation time 151604005 ps
CPU time 0.77 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:17 PM PDT 24
Peak memory 206824 kb
Host smart-d4e522cd-efd8-4b07-9839-ab7291224ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27508
77812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2750877812
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1874866355
Short name T2031
Test name
Test status
Simulation time 150039230 ps
CPU time 0.77 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 206632 kb
Host smart-460c0650-fa40-4ba3-8b58-0f0e0f2b2dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18748
66355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1874866355
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.2070003392
Short name T331
Test name
Test status
Simulation time 882427358 ps
CPU time 1.87 seconds
Started Jul 12 05:28:13 PM PDT 24
Finished Jul 12 05:28:15 PM PDT 24
Peak memory 206896 kb
Host smart-dc1323a6-0555-4ab2-9c2e-bdee6bc590ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20700
03392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.2070003392
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1925798693
Short name T889
Test name
Test status
Simulation time 7404892050 ps
CPU time 71.95 seconds
Started Jul 12 05:28:16 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 207020 kb
Host smart-274f0ae1-4600-4963-8d2a-1eed2c5af5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19257
98693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1925798693
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.3547718715
Short name T1481
Test name
Test status
Simulation time 59698151 ps
CPU time 0.7 seconds
Started Jul 12 05:28:26 PM PDT 24
Finished Jul 12 05:28:29 PM PDT 24
Peak memory 206848 kb
Host smart-0897a72d-1320-43d4-8d19-758ced50a97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3547718715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3547718715
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.411143260
Short name T521
Test name
Test status
Simulation time 4089603304 ps
CPU time 5.36 seconds
Started Jul 12 05:28:19 PM PDT 24
Finished Jul 12 05:28:26 PM PDT 24
Peak memory 206876 kb
Host smart-7629eee4-0e56-462f-8205-475fa90f3830
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=411143260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.411143260
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1079097116
Short name T2621
Test name
Test status
Simulation time 13411016291 ps
CPU time 11.94 seconds
Started Jul 12 05:28:17 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 207012 kb
Host smart-e9c8ac5f-efb3-4c08-800c-43e1318a5d33
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1079097116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1079097116
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2736095993
Short name T1175
Test name
Test status
Simulation time 23346549592 ps
CPU time 26.49 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 206824 kb
Host smart-e39ff0cd-2b4f-4a30-9220-8fdf7e042af5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2736095993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2736095993
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.9278366
Short name T1665
Test name
Test status
Simulation time 166055324 ps
CPU time 0.84 seconds
Started Jul 12 05:28:19 PM PDT 24
Finished Jul 12 05:28:21 PM PDT 24
Peak memory 206700 kb
Host smart-85101ec8-c9c6-49af-af33-1ace031f124f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92783
66 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.9278366
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3667730882
Short name T916
Test name
Test status
Simulation time 151366323 ps
CPU time 0.78 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:18 PM PDT 24
Peak memory 206792 kb
Host smart-b0cdf1b9-132f-4150-8412-5598ad7a3542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36677
30882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3667730882
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1213538761
Short name T1548
Test name
Test status
Simulation time 209850641 ps
CPU time 0.91 seconds
Started Jul 12 05:28:17 PM PDT 24
Finished Jul 12 05:28:20 PM PDT 24
Peak memory 206756 kb
Host smart-1e8741fd-a422-46cc-aab5-69a676b7d74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12135
38761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1213538761
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3595349002
Short name T2361
Test name
Test status
Simulation time 970669586 ps
CPU time 2.06 seconds
Started Jul 12 05:28:15 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 206884 kb
Host smart-b0a9dbb3-c8d3-4914-94bf-1a9c5923cbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35953
49002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3595349002
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3979986450
Short name T2435
Test name
Test status
Simulation time 16156420451 ps
CPU time 28.75 seconds
Started Jul 12 05:28:14 PM PDT 24
Finished Jul 12 05:28:43 PM PDT 24
Peak memory 207020 kb
Host smart-f01bced6-3ca6-46f9-acf0-f50d46ba3c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39799
86450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3979986450
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.293797659
Short name T941
Test name
Test status
Simulation time 489533065 ps
CPU time 1.38 seconds
Started Jul 12 05:28:21 PM PDT 24
Finished Jul 12 05:28:23 PM PDT 24
Peak memory 206824 kb
Host smart-5a6414a8-fde4-4cd0-9707-cedb3395ffc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
7659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.293797659
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2966016020
Short name T2263
Test name
Test status
Simulation time 154261884 ps
CPU time 0.78 seconds
Started Jul 12 05:28:18 PM PDT 24
Finished Jul 12 05:28:20 PM PDT 24
Peak memory 206836 kb
Host smart-a296df61-9f9c-4d2d-98ad-b2df0c7873c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29660
16020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2966016020
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.927530014
Short name T2551
Test name
Test status
Simulation time 81395639 ps
CPU time 0.7 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:28:23 PM PDT 24
Peak memory 206800 kb
Host smart-cbc1aacd-4ff6-4460-b480-1a80b70ac759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92753
0014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.927530014
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3179788627
Short name T1862
Test name
Test status
Simulation time 810669416 ps
CPU time 1.96 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206956 kb
Host smart-ff3bc22c-8f3c-481c-b680-7766da89333a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31797
88627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3179788627
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1488519130
Short name T656
Test name
Test status
Simulation time 292017090 ps
CPU time 2.17 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206852 kb
Host smart-c957644b-3121-45a2-a0dd-f815c6b42772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885
19130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1488519130
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.339274664
Short name T1401
Test name
Test status
Simulation time 179925353 ps
CPU time 0.84 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:28:23 PM PDT 24
Peak memory 206800 kb
Host smart-6d7ba250-57ac-4573-831b-4fedc3723f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
4664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.339274664
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.479030178
Short name T1300
Test name
Test status
Simulation time 137781342 ps
CPU time 0.77 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206756 kb
Host smart-bd034fb4-e575-4932-87a3-216e6800a103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47903
0178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.479030178
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1317179602
Short name T2675
Test name
Test status
Simulation time 179863403 ps
CPU time 0.82 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:28:24 PM PDT 24
Peak memory 206800 kb
Host smart-d34973e5-e09d-48d5-a591-1cf51a88525b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
79602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1317179602
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.2715768791
Short name T2071
Test name
Test status
Simulation time 6542537357 ps
CPU time 46.15 seconds
Started Jul 12 05:28:25 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 207000 kb
Host smart-e42833c1-4567-418c-976b-491c6b5f0dfa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2715768791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2715768791
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1172599213
Short name T1211
Test name
Test status
Simulation time 8565170933 ps
CPU time 32.23 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:57 PM PDT 24
Peak memory 207004 kb
Host smart-d2c1f032-75cf-4d74-9f55-7b763ceeaa66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11725
99213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1172599213
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1625928264
Short name T443
Test name
Test status
Simulation time 184058805 ps
CPU time 0.83 seconds
Started Jul 12 05:28:27 PM PDT 24
Finished Jul 12 05:28:30 PM PDT 24
Peak memory 206804 kb
Host smart-a57b2eb8-3c8f-4b64-88ad-b887528ad9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16259
28264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1625928264
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.381391085
Short name T1452
Test name
Test status
Simulation time 23383493582 ps
CPU time 22.41 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 206888 kb
Host smart-4a842311-8279-47e1-a3e6-4d6b453fc811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38139
1085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.381391085
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.445635436
Short name T1507
Test name
Test status
Simulation time 3316886577 ps
CPU time 3.81 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:29 PM PDT 24
Peak memory 206756 kb
Host smart-83898b69-57c0-4a54-9d65-2a86478209e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44563
5436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.445635436
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2508521149
Short name T2272
Test name
Test status
Simulation time 3032265731 ps
CPU time 20.96 seconds
Started Jul 12 05:28:24 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 207020 kb
Host smart-3d96724f-ed0c-4d67-a769-24c97461a860
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2508521149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2508521149
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2304473250
Short name T2173
Test name
Test status
Simulation time 239731860 ps
CPU time 0.94 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206808 kb
Host smart-6b714a3d-b829-4b1c-aba3-f5c064b80202
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2304473250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2304473250
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.937266743
Short name T1256
Test name
Test status
Simulation time 191939899 ps
CPU time 0.85 seconds
Started Jul 12 05:28:27 PM PDT 24
Finished Jul 12 05:28:30 PM PDT 24
Peak memory 206816 kb
Host smart-4adaeb35-5724-40e8-bf1d-b77807a984d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93726
6743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.937266743
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2408768226
Short name T764
Test name
Test status
Simulation time 4745518873 ps
CPU time 127.79 seconds
Started Jul 12 05:28:28 PM PDT 24
Finished Jul 12 05:30:38 PM PDT 24
Peak memory 207020 kb
Host smart-0f31ad2d-df94-4f0c-b6e8-c33cfd926852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24087
68226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2408768226
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.742423373
Short name T2643
Test name
Test status
Simulation time 4878710001 ps
CPU time 135.65 seconds
Started Jul 12 05:28:29 PM PDT 24
Finished Jul 12 05:30:47 PM PDT 24
Peak memory 207028 kb
Host smart-c34b1f23-e6a5-455f-8d37-4cb84c818ee7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=742423373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.742423373
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.956580411
Short name T2396
Test name
Test status
Simulation time 179832270 ps
CPU time 0.82 seconds
Started Jul 12 05:28:30 PM PDT 24
Finished Jul 12 05:28:34 PM PDT 24
Peak memory 206676 kb
Host smart-057895e2-354e-4b60-a125-e1153e51e1e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=956580411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.956580411
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2218997120
Short name T2017
Test name
Test status
Simulation time 140538126 ps
CPU time 0.8 seconds
Started Jul 12 05:28:26 PM PDT 24
Finished Jul 12 05:28:30 PM PDT 24
Peak memory 206832 kb
Host smart-1d2962be-4468-45f4-bb37-aa90bdc2c482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22189
97120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2218997120
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3760032809
Short name T119
Test name
Test status
Simulation time 214405229 ps
CPU time 0.94 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:28:24 PM PDT 24
Peak memory 206820 kb
Host smart-81a92d7f-c308-444e-9feb-e324e290754c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37600
32809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3760032809
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2616119754
Short name T640
Test name
Test status
Simulation time 200652864 ps
CPU time 0.77 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:26 PM PDT 24
Peak memory 206668 kb
Host smart-71d7e08e-43b0-4ee7-8aa1-4c105c3288d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26161
19754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2616119754
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3331570509
Short name T1071
Test name
Test status
Simulation time 199395909 ps
CPU time 0.82 seconds
Started Jul 12 05:28:25 PM PDT 24
Finished Jul 12 05:28:28 PM PDT 24
Peak memory 206792 kb
Host smart-9c0d7a9a-74f7-4818-b5d9-11bfabdabcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33315
70509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3331570509
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3712820666
Short name T2089
Test name
Test status
Simulation time 218539749 ps
CPU time 0.83 seconds
Started Jul 12 05:28:25 PM PDT 24
Finished Jul 12 05:28:28 PM PDT 24
Peak memory 206816 kb
Host smart-217ab8a2-2c06-45f4-9250-597098eba2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37128
20666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3712820666
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1140302526
Short name T1441
Test name
Test status
Simulation time 157257236 ps
CPU time 0.86 seconds
Started Jul 12 05:28:24 PM PDT 24
Finished Jul 12 05:28:28 PM PDT 24
Peak memory 206676 kb
Host smart-d1ea3c23-9957-4ee0-a72a-b731e8cd4682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11403
02526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1140302526
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3990414409
Short name T1194
Test name
Test status
Simulation time 237684122 ps
CPU time 0.93 seconds
Started Jul 12 05:28:27 PM PDT 24
Finished Jul 12 05:28:30 PM PDT 24
Peak memory 206688 kb
Host smart-2d726b02-fe0a-4906-8756-19d6a9bc8d07
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3990414409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3990414409
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.821463163
Short name T1524
Test name
Test status
Simulation time 141202532 ps
CPU time 0.75 seconds
Started Jul 12 05:28:24 PM PDT 24
Finished Jul 12 05:28:27 PM PDT 24
Peak memory 206820 kb
Host smart-8692ecc7-7c11-485b-a591-088af3c2a788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82146
3163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.821463163
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4058588876
Short name T1718
Test name
Test status
Simulation time 33132053 ps
CPU time 0.66 seconds
Started Jul 12 05:28:25 PM PDT 24
Finished Jul 12 05:28:28 PM PDT 24
Peak memory 206808 kb
Host smart-8767d381-9f54-49fa-8b58-34a6540a2b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40585
88876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4058588876
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2503176740
Short name T2201
Test name
Test status
Simulation time 22172157115 ps
CPU time 51.42 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 207052 kb
Host smart-c8cd461d-a060-4301-8c8a-eef934b4c9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25031
76740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2503176740
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1962492825
Short name T2467
Test name
Test status
Simulation time 200057607 ps
CPU time 0.81 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206812 kb
Host smart-a9afea56-a44a-43d1-9905-4670d5157f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19624
92825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1962492825
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.997949305
Short name T1102
Test name
Test status
Simulation time 171705930 ps
CPU time 0.86 seconds
Started Jul 12 05:28:25 PM PDT 24
Finished Jul 12 05:28:29 PM PDT 24
Peak memory 206812 kb
Host smart-4e6325d4-fa7e-4dd2-b691-b7aca656a98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99794
9305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.997949305
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3068520185
Short name T318
Test name
Test status
Simulation time 179405606 ps
CPU time 0.89 seconds
Started Jul 12 05:28:26 PM PDT 24
Finished Jul 12 05:28:29 PM PDT 24
Peak memory 206704 kb
Host smart-24d49a07-eaae-4532-9f45-8c465d7abe92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30685
20185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3068520185
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3410173191
Short name T1978
Test name
Test status
Simulation time 227686758 ps
CPU time 1.01 seconds
Started Jul 12 05:28:31 PM PDT 24
Finished Jul 12 05:28:34 PM PDT 24
Peak memory 206796 kb
Host smart-aa01bda9-7ed8-4a7f-8a98-dc6cee08a2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34101
73191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3410173191
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.684621664
Short name T601
Test name
Test status
Simulation time 192705862 ps
CPU time 0.85 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206804 kb
Host smart-73bfd580-741c-449b-89d1-d08ce69286e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68462
1664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.684621664
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.602600074
Short name T2133
Test name
Test status
Simulation time 202972228 ps
CPU time 0.87 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206808 kb
Host smart-9201b931-0e6e-42cb-842a-e61f959e14f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60260
0074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.602600074
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3361341759
Short name T1528
Test name
Test status
Simulation time 149081532 ps
CPU time 0.79 seconds
Started Jul 12 05:28:28 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 206808 kb
Host smart-a7f7ff1c-2c63-4f95-95a8-c7d1e41e0fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33613
41759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3361341759
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.760556516
Short name T2103
Test name
Test status
Simulation time 222981814 ps
CPU time 0.93 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:28:24 PM PDT 24
Peak memory 206788 kb
Host smart-98c1bc69-9466-4537-b90f-b0743722f1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76055
6516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.760556516
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1485104863
Short name T642
Test name
Test status
Simulation time 5002371576 ps
CPU time 135.02 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206976 kb
Host smart-cdb38bc8-5d49-47c9-b4df-5edfd0a0dd20
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1485104863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1485104863
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1535731393
Short name T2653
Test name
Test status
Simulation time 167189188 ps
CPU time 0.79 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:26 PM PDT 24
Peak memory 206776 kb
Host smart-fe37576b-67a9-4e24-b0c2-ca24ab44be87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15357
31393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1535731393
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2439810285
Short name T2155
Test name
Test status
Simulation time 161972189 ps
CPU time 0.79 seconds
Started Jul 12 05:28:23 PM PDT 24
Finished Jul 12 05:28:26 PM PDT 24
Peak memory 206632 kb
Host smart-341e4cdf-22e3-42d2-8cd6-f2cce8f24a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24398
10285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2439810285
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3754978935
Short name T1074
Test name
Test status
Simulation time 1008123435 ps
CPU time 2.29 seconds
Started Jul 12 05:28:29 PM PDT 24
Finished Jul 12 05:28:34 PM PDT 24
Peak memory 206932 kb
Host smart-a616dc51-2ffd-45fa-a040-f4ffed4b0095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
78935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3754978935
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3303614480
Short name T405
Test name
Test status
Simulation time 4543222184 ps
CPU time 42.32 seconds
Started Jul 12 05:28:27 PM PDT 24
Finished Jul 12 05:29:12 PM PDT 24
Peak memory 207072 kb
Host smart-f210f994-7504-41ae-942f-8bf8fc2f211e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33036
14480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3303614480
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3088723367
Short name T2402
Test name
Test status
Simulation time 65408372 ps
CPU time 0.73 seconds
Started Jul 12 05:28:39 PM PDT 24
Finished Jul 12 05:28:41 PM PDT 24
Peak memory 206852 kb
Host smart-d6d02220-5c68-4648-b3dc-9314e84be4ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3088723367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3088723367
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3481558775
Short name T1557
Test name
Test status
Simulation time 3763369239 ps
CPU time 4.24 seconds
Started Jul 12 05:28:24 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 207076 kb
Host smart-4399f24a-2003-4bdd-beef-fbe227eab183
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3481558775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3481558775
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.784083847
Short name T968
Test name
Test status
Simulation time 13363350353 ps
CPU time 13.14 seconds
Started Jul 12 05:28:24 PM PDT 24
Finished Jul 12 05:28:39 PM PDT 24
Peak memory 206860 kb
Host smart-838149f3-c5bf-4ee7-8bff-40435639cded
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=784083847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.784083847
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1487572855
Short name T1220
Test name
Test status
Simulation time 23483689172 ps
CPU time 23.45 seconds
Started Jul 12 05:28:27 PM PDT 24
Finished Jul 12 05:28:53 PM PDT 24
Peak memory 207076 kb
Host smart-8366bead-0cb3-4b49-ab1f-7e830b0cfbb0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1487572855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.1487572855
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3623671937
Short name T861
Test name
Test status
Simulation time 177419386 ps
CPU time 0.75 seconds
Started Jul 12 05:28:21 PM PDT 24
Finished Jul 12 05:28:22 PM PDT 24
Peak memory 206716 kb
Host smart-4e93d01d-28e7-4847-9390-4fde3d84c30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36236
71937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3623671937
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.4133502577
Short name T1795
Test name
Test status
Simulation time 140354342 ps
CPU time 0.75 seconds
Started Jul 12 05:28:30 PM PDT 24
Finished Jul 12 05:28:34 PM PDT 24
Peak memory 206656 kb
Host smart-c3a1bebf-7adf-489e-a0d9-98ec4ac6d089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41335
02577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.4133502577
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.586731699
Short name T888
Test name
Test status
Simulation time 295694990 ps
CPU time 1.08 seconds
Started Jul 12 05:28:24 PM PDT 24
Finished Jul 12 05:28:28 PM PDT 24
Peak memory 206684 kb
Host smart-672a4ace-e678-47b6-a6fe-c9329ed00b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58673
1699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.586731699
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2823071964
Short name T1993
Test name
Test status
Simulation time 941373671 ps
CPU time 2.11 seconds
Started Jul 12 05:28:26 PM PDT 24
Finished Jul 12 05:28:30 PM PDT 24
Peak memory 206828 kb
Host smart-852b89f7-a232-4a51-ba06-692ad880ddaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28230
71964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2823071964
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3743951590
Short name T2161
Test name
Test status
Simulation time 19734354333 ps
CPU time 36.21 seconds
Started Jul 12 05:28:24 PM PDT 24
Finished Jul 12 05:29:02 PM PDT 24
Peak memory 207024 kb
Host smart-7484c6e2-6357-43ed-a0b6-31e3be0b6a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37439
51590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3743951590
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2940875784
Short name T1541
Test name
Test status
Simulation time 402802089 ps
CPU time 1.3 seconds
Started Jul 12 05:28:28 PM PDT 24
Finished Jul 12 05:28:32 PM PDT 24
Peak memory 206812 kb
Host smart-2f645ff7-9d43-48af-abbe-6a3c68284373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29408
75784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2940875784
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.685535813
Short name T2662
Test name
Test status
Simulation time 198189497 ps
CPU time 0.79 seconds
Started Jul 12 05:28:22 PM PDT 24
Finished Jul 12 05:28:23 PM PDT 24
Peak memory 206820 kb
Host smart-accecb24-0c49-47fc-b241-5af800a5a506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68553
5813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.685535813
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2709373125
Short name T2739
Test name
Test status
Simulation time 39399830 ps
CPU time 0.66 seconds
Started Jul 12 05:28:29 PM PDT 24
Finished Jul 12 05:28:32 PM PDT 24
Peak memory 206752 kb
Host smart-436a57ab-61cc-4475-ba69-7440a0e9e859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27093
73125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2709373125
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.4109093248
Short name T454
Test name
Test status
Simulation time 806564664 ps
CPU time 1.88 seconds
Started Jul 12 05:28:27 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 206892 kb
Host smart-67b00f2c-bb10-4d86-8c3d-01067ea94ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41090
93248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.4109093248
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1800011449
Short name T2543
Test name
Test status
Simulation time 239141734 ps
CPU time 1.36 seconds
Started Jul 12 05:28:24 PM PDT 24
Finished Jul 12 05:28:28 PM PDT 24
Peak memory 207004 kb
Host smart-42a8fd4d-2bbf-4dd4-9bb3-2e48beda602d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18000
11449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1800011449
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4172708301
Short name T558
Test name
Test status
Simulation time 175656486 ps
CPU time 0.81 seconds
Started Jul 12 05:28:47 PM PDT 24
Finished Jul 12 05:28:49 PM PDT 24
Peak memory 206768 kb
Host smart-9f354941-e5f0-4763-9fba-443f9272409b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727
08301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4172708301
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.4161133467
Short name T1522
Test name
Test status
Simulation time 145858641 ps
CPU time 0.77 seconds
Started Jul 12 05:28:34 PM PDT 24
Finished Jul 12 05:28:36 PM PDT 24
Peak memory 206828 kb
Host smart-783750fb-815b-48c3-b9e6-1208b8191c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
33467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.4161133467
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3956399467
Short name T2267
Test name
Test status
Simulation time 151929535 ps
CPU time 0.78 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 206804 kb
Host smart-4e3bda20-9b01-4a0a-a176-f67f89b562ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39563
99467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3956399467
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2590258254
Short name T768
Test name
Test status
Simulation time 170171561 ps
CPU time 0.76 seconds
Started Jul 12 05:28:33 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 206828 kb
Host smart-060f3a20-91b2-41db-8ef0-76945d652afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25902
58254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2590258254
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.948767302
Short name T2695
Test name
Test status
Simulation time 23326115640 ps
CPU time 28.63 seconds
Started Jul 12 05:28:39 PM PDT 24
Finished Jul 12 05:29:09 PM PDT 24
Peak memory 206616 kb
Host smart-39d02741-f2c4-4e09-89bf-6b54f95f96fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94876
7302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.948767302
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.227470821
Short name T1157
Test name
Test status
Simulation time 3295080211 ps
CPU time 3.9 seconds
Started Jul 12 05:28:31 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 206868 kb
Host smart-2986581a-b823-47ef-9a8d-e69d0314b507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22747
0821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.227470821
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.4001166400
Short name T1237
Test name
Test status
Simulation time 8866542631 ps
CPU time 63.71 seconds
Started Jul 12 05:28:33 PM PDT 24
Finished Jul 12 05:29:38 PM PDT 24
Peak memory 207104 kb
Host smart-9ac91278-3556-4497-b70a-f6c4e28b2c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40011
66400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.4001166400
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3632046511
Short name T1615
Test name
Test status
Simulation time 5290635303 ps
CPU time 149.24 seconds
Started Jul 12 05:28:31 PM PDT 24
Finished Jul 12 05:31:03 PM PDT 24
Peak memory 206828 kb
Host smart-8cd4f115-f867-4ada-8b3b-da72e1515d55
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3632046511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3632046511
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3320804081
Short name T1015
Test name
Test status
Simulation time 251588240 ps
CPU time 0.96 seconds
Started Jul 12 05:28:33 PM PDT 24
Finished Jul 12 05:28:36 PM PDT 24
Peak memory 206836 kb
Host smart-2463f9ad-a64c-4e00-a0ce-638afe212bed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3320804081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3320804081
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1608141676
Short name T1332
Test name
Test status
Simulation time 200604994 ps
CPU time 0.94 seconds
Started Jul 12 05:28:31 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 206828 kb
Host smart-04fd290a-fd8b-4937-a334-bf65c87a0b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16081
41676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1608141676
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1204506145
Short name T1531
Test name
Test status
Simulation time 6021501250 ps
CPU time 166.89 seconds
Started Jul 12 05:28:30 PM PDT 24
Finished Jul 12 05:31:20 PM PDT 24
Peak memory 207032 kb
Host smart-167d612f-a6e9-4ed0-a5e8-39777d7c7198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12045
06145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1204506145
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3701783483
Short name T383
Test name
Test status
Simulation time 5310549895 ps
CPU time 152.23 seconds
Started Jul 12 05:28:28 PM PDT 24
Finished Jul 12 05:31:03 PM PDT 24
Peak memory 207000 kb
Host smart-49a28bfb-4fd4-4a22-98be-b451878181d2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3701783483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3701783483
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3221000672
Short name T323
Test name
Test status
Simulation time 161380481 ps
CPU time 0.79 seconds
Started Jul 12 05:28:39 PM PDT 24
Finished Jul 12 05:28:41 PM PDT 24
Peak memory 206812 kb
Host smart-c6ef0eb1-6b7b-4e99-98b5-3731adb14868
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3221000672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3221000672
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1292229862
Short name T2303
Test name
Test status
Simulation time 159156289 ps
CPU time 0.8 seconds
Started Jul 12 05:28:34 PM PDT 24
Finished Jul 12 05:28:36 PM PDT 24
Peak memory 206828 kb
Host smart-49eb98e2-681f-4b21-aa6a-8accd66c203e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12922
29862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1292229862
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.2803438882
Short name T2423
Test name
Test status
Simulation time 142766571 ps
CPU time 0.79 seconds
Started Jul 12 05:28:30 PM PDT 24
Finished Jul 12 05:28:34 PM PDT 24
Peak memory 206788 kb
Host smart-d7fccefa-f5ba-482a-bd5e-350cf1ed574e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28034
38882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2803438882
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1763226074
Short name T2609
Test name
Test status
Simulation time 148166506 ps
CPU time 0.85 seconds
Started Jul 12 05:28:28 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 206808 kb
Host smart-8c458980-23d8-403b-8576-63a47925891c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17632
26074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1763226074
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1055833619
Short name T314
Test name
Test status
Simulation time 169956735 ps
CPU time 0.77 seconds
Started Jul 12 05:28:30 PM PDT 24
Finished Jul 12 05:28:34 PM PDT 24
Peak memory 206796 kb
Host smart-affd69d0-8ba0-476e-a0d3-49884b6d67b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10558
33619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1055833619
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3812712186
Short name T1159
Test name
Test status
Simulation time 148720108 ps
CPU time 0.78 seconds
Started Jul 12 05:28:33 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 206832 kb
Host smart-3ed379a6-819d-4cd3-a51f-2f5d07b9be81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38127
12186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3812712186
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3935424097
Short name T1457
Test name
Test status
Simulation time 226644083 ps
CPU time 0.91 seconds
Started Jul 12 05:28:33 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 206828 kb
Host smart-6d622042-a047-4267-b6ae-0ba7c792b691
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3935424097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3935424097
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3993200611
Short name T2118
Test name
Test status
Simulation time 145366748 ps
CPU time 0.76 seconds
Started Jul 12 05:28:28 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 206772 kb
Host smart-27d7f3f9-eaf3-4d3f-bab1-d1917b2fd4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39932
00611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3993200611
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1290831659
Short name T1816
Test name
Test status
Simulation time 43314537 ps
CPU time 0.66 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 206800 kb
Host smart-d7931f02-c308-49ea-a2d8-d487f5112471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12908
31659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1290831659
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1820415136
Short name T1245
Test name
Test status
Simulation time 14662872830 ps
CPU time 30.27 seconds
Started Jul 12 05:28:35 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 206940 kb
Host smart-67de0439-a9ad-4e1d-9448-77cedae00fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18204
15136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1820415136
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.898187596
Short name T703
Test name
Test status
Simulation time 186535665 ps
CPU time 0.84 seconds
Started Jul 12 05:28:31 PM PDT 24
Finished Jul 12 05:28:34 PM PDT 24
Peak memory 206636 kb
Host smart-3d8e6ef6-1fc3-4e67-aa25-418755c4a5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89818
7596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.898187596
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1881198488
Short name T2322
Test name
Test status
Simulation time 211933973 ps
CPU time 0.91 seconds
Started Jul 12 05:28:32 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 206808 kb
Host smart-12a5aa6f-758d-4c76-b9b2-e8096e99072c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
98488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1881198488
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.1536729248
Short name T1672
Test name
Test status
Simulation time 210594915 ps
CPU time 0.92 seconds
Started Jul 12 05:28:29 PM PDT 24
Finished Jul 12 05:28:33 PM PDT 24
Peak memory 206824 kb
Host smart-a40e0e4f-05c6-43fb-a267-cab9049dc76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15367
29248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1536729248
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.984204516
Short name T2506
Test name
Test status
Simulation time 186737740 ps
CPU time 0.81 seconds
Started Jul 12 05:28:39 PM PDT 24
Finished Jul 12 05:28:41 PM PDT 24
Peak memory 206504 kb
Host smart-4731c3a3-4d72-475e-bdc5-c0ef53022728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98420
4516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.984204516
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1101880671
Short name T89
Test name
Test status
Simulation time 156477187 ps
CPU time 0.77 seconds
Started Jul 12 05:28:47 PM PDT 24
Finished Jul 12 05:28:49 PM PDT 24
Peak memory 206584 kb
Host smart-9c4580a3-a4f1-471b-9766-0f73a3f98bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11018
80671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1101880671
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3609423800
Short name T1231
Test name
Test status
Simulation time 179339201 ps
CPU time 0.76 seconds
Started Jul 12 05:28:35 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 206824 kb
Host smart-1464a992-f8c8-406f-ac7e-66b060194c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36094
23800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3609423800
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3137044363
Short name T1611
Test name
Test status
Simulation time 156742405 ps
CPU time 0.77 seconds
Started Jul 12 05:28:30 PM PDT 24
Finished Jul 12 05:28:33 PM PDT 24
Peak memory 206720 kb
Host smart-33675d53-9b63-42f8-a4f4-b70b1f46a239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31370
44363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3137044363
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.4135790802
Short name T1525
Test name
Test status
Simulation time 224647327 ps
CPU time 0.99 seconds
Started Jul 12 05:28:31 PM PDT 24
Finished Jul 12 05:28:34 PM PDT 24
Peak memory 206788 kb
Host smart-e7df848a-797c-41bd-8273-24581c86b8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
90802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.4135790802
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2611533440
Short name T2377
Test name
Test status
Simulation time 4517767610 ps
CPU time 120.75 seconds
Started Jul 12 05:28:29 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 207000 kb
Host smart-8c6d0456-22ec-4fea-a060-784eb4c326d2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2611533440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2611533440
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.243528106
Short name T2464
Test name
Test status
Simulation time 174778669 ps
CPU time 0.79 seconds
Started Jul 12 05:28:29 PM PDT 24
Finished Jul 12 05:28:33 PM PDT 24
Peak memory 206832 kb
Host smart-26d284fa-aecd-4054-aca7-aee9b127838f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24352
8106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.243528106
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1864914388
Short name T1647
Test name
Test status
Simulation time 191031066 ps
CPU time 0.84 seconds
Started Jul 12 05:28:33 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 206800 kb
Host smart-bc14da44-712a-47b8-b394-98f7f4383108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
14388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1864914388
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3704292486
Short name T1516
Test name
Test status
Simulation time 1197955736 ps
CPU time 3.09 seconds
Started Jul 12 05:28:30 PM PDT 24
Finished Jul 12 05:28:36 PM PDT 24
Peak memory 206892 kb
Host smart-a4cea626-ecc0-46b3-bf1c-4259e25909c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37042
92486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3704292486
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3329012489
Short name T1553
Test name
Test status
Simulation time 4622786040 ps
CPU time 32.44 seconds
Started Jul 12 05:28:32 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 207072 kb
Host smart-217c0ef7-24e4-416d-bf45-b4b723df0153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33290
12489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3329012489
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2694975849
Short name T994
Test name
Test status
Simulation time 44727049 ps
CPU time 0.68 seconds
Started Jul 12 05:28:42 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 207084 kb
Host smart-94b2c07a-ddbc-4002-9467-9ce108e1a452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2694975849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2694975849
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2758989266
Short name T2501
Test name
Test status
Simulation time 4170127978 ps
CPU time 4.5 seconds
Started Jul 12 05:28:29 PM PDT 24
Finished Jul 12 05:28:36 PM PDT 24
Peak memory 207088 kb
Host smart-ef7c22f2-60ce-4486-a66b-73460bc66f16
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2758989266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.2758989266
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.4285017464
Short name T710
Test name
Test status
Simulation time 13347037729 ps
CPU time 11.97 seconds
Started Jul 12 05:28:27 PM PDT 24
Finished Jul 12 05:28:42 PM PDT 24
Peak memory 206772 kb
Host smart-6b98860a-b820-423b-a63a-be36a8d0c825
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4285017464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.4285017464
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.243428723
Short name T1240
Test name
Test status
Simulation time 23360695524 ps
CPU time 24.74 seconds
Started Jul 12 05:28:30 PM PDT 24
Finished Jul 12 05:28:58 PM PDT 24
Peak memory 206948 kb
Host smart-53841ba6-276e-49ac-92c5-63bfb771d45c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=243428723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.243428723
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.4238334673
Short name T1676
Test name
Test status
Simulation time 178191436 ps
CPU time 0.85 seconds
Started Jul 12 05:28:32 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 206792 kb
Host smart-fd2e8d9e-01c8-4cf1-95aa-cb355566bdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42383
34673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.4238334673
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2782485990
Short name T1385
Test name
Test status
Simulation time 226258214 ps
CPU time 0.82 seconds
Started Jul 12 05:28:34 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 206804 kb
Host smart-f3adcf37-71f4-4998-8973-a74a0034adb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27824
85990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2782485990
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.982548679
Short name T1825
Test name
Test status
Simulation time 226464972 ps
CPU time 0.98 seconds
Started Jul 12 05:28:34 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 206696 kb
Host smart-7cdaa78b-1177-4bfe-9d98-4b4c938ce749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98254
8679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.982548679
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3442267072
Short name T687
Test name
Test status
Simulation time 378231669 ps
CPU time 1.05 seconds
Started Jul 12 05:28:39 PM PDT 24
Finished Jul 12 05:28:41 PM PDT 24
Peak memory 206816 kb
Host smart-7990665c-afd2-45e1-b94d-7b40254e50ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34422
67072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3442267072
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3395537755
Short name T499
Test name
Test status
Simulation time 7446019969 ps
CPU time 15.47 seconds
Started Jul 12 05:28:47 PM PDT 24
Finished Jul 12 05:29:04 PM PDT 24
Peak memory 206380 kb
Host smart-ebe27a82-f6c8-41d7-9cce-215ecdc6ff24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
37755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3395537755
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1887046598
Short name T1299
Test name
Test status
Simulation time 451810937 ps
CPU time 1.34 seconds
Started Jul 12 05:28:35 PM PDT 24
Finished Jul 12 05:28:38 PM PDT 24
Peak memory 206708 kb
Host smart-18745fb5-88ef-425b-a61b-55f01aa35d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18870
46598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1887046598
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2010479647
Short name T1761
Test name
Test status
Simulation time 184387649 ps
CPU time 0.78 seconds
Started Jul 12 05:28:37 PM PDT 24
Finished Jul 12 05:28:39 PM PDT 24
Peak memory 206808 kb
Host smart-c217a92b-1136-4d4b-b31d-fd40c294e561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20104
79647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2010479647
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.854183422
Short name T2629
Test name
Test status
Simulation time 32869188 ps
CPU time 0.67 seconds
Started Jul 12 05:28:35 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 206808 kb
Host smart-2fdd9b7a-1871-42fb-ab2a-e4058cf62cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85418
3422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.854183422
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3988092501
Short name T2510
Test name
Test status
Simulation time 924704414 ps
CPU time 2.15 seconds
Started Jul 12 05:28:39 PM PDT 24
Finished Jul 12 05:28:42 PM PDT 24
Peak memory 207012 kb
Host smart-cc05a067-93b3-4929-bfa8-3b36afe5646b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39880
92501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3988092501
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2764817174
Short name T561
Test name
Test status
Simulation time 299260726 ps
CPU time 1.72 seconds
Started Jul 12 05:28:44 PM PDT 24
Finished Jul 12 05:28:47 PM PDT 24
Peak memory 207012 kb
Host smart-b37ee8ad-932d-4eca-8801-5894544f62f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
17174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2764817174
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2362682334
Short name T1850
Test name
Test status
Simulation time 180964145 ps
CPU time 0.81 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 206820 kb
Host smart-2057d140-6af0-4542-93f6-10c880b5fed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23626
82334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2362682334
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.4111507274
Short name T1389
Test name
Test status
Simulation time 152711054 ps
CPU time 0.75 seconds
Started Jul 12 05:28:44 PM PDT 24
Finished Jul 12 05:28:46 PM PDT 24
Peak memory 206812 kb
Host smart-d67490d0-9c9b-47c4-a4e2-12dc36dd6852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41115
07274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.4111507274
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3904031037
Short name T2260
Test name
Test status
Simulation time 253239169 ps
CPU time 0.95 seconds
Started Jul 12 05:28:34 PM PDT 24
Finished Jul 12 05:28:36 PM PDT 24
Peak memory 206712 kb
Host smart-d34449ab-50bb-4493-9a3e-0adbdf37ceba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39040
31037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3904031037
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.1100830427
Short name T1616
Test name
Test status
Simulation time 13836698388 ps
CPU time 47.52 seconds
Started Jul 12 05:28:38 PM PDT 24
Finished Jul 12 05:29:26 PM PDT 24
Peak memory 207080 kb
Host smart-d0ab6d8b-d44f-40f9-be3a-c23e15abd887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11008
30427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.1100830427
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.720575845
Short name T1696
Test name
Test status
Simulation time 243308764 ps
CPU time 0.92 seconds
Started Jul 12 05:28:37 PM PDT 24
Finished Jul 12 05:28:39 PM PDT 24
Peak memory 206828 kb
Host smart-ff8f3817-172b-4f46-a3f8-6b56f6ea2c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72057
5845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.720575845
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3573313466
Short name T782
Test name
Test status
Simulation time 23294610451 ps
CPU time 29.22 seconds
Started Jul 12 05:28:38 PM PDT 24
Finished Jul 12 05:29:08 PM PDT 24
Peak memory 206880 kb
Host smart-a74470ea-1ec0-473b-b615-5e2a7cf72f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35733
13466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3573313466
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.72523474
Short name T745
Test name
Test status
Simulation time 3366092070 ps
CPU time 4.12 seconds
Started Jul 12 05:28:37 PM PDT 24
Finished Jul 12 05:28:42 PM PDT 24
Peak memory 206876 kb
Host smart-1bae896e-a101-4c0a-a70d-5a0795959087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72523
474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.72523474
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.612984415
Short name T150
Test name
Test status
Simulation time 8614367963 ps
CPU time 77.19 seconds
Started Jul 12 05:28:37 PM PDT 24
Finished Jul 12 05:29:56 PM PDT 24
Peak memory 206976 kb
Host smart-3b466e68-94d7-4a5d-9e2d-4febb8d429b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61298
4415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.612984415
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2443938849
Short name T1770
Test name
Test status
Simulation time 3475633060 ps
CPU time 26.07 seconds
Started Jul 12 05:28:39 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 207004 kb
Host smart-c53be678-7d5a-49fc-b069-686d1ecf16cd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2443938849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2443938849
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2125694110
Short name T781
Test name
Test status
Simulation time 279658455 ps
CPU time 1.05 seconds
Started Jul 12 05:28:34 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 206824 kb
Host smart-414b8e40-54b4-4703-a2bf-5927e82bddab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2125694110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2125694110
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1483666053
Short name T2571
Test name
Test status
Simulation time 185486417 ps
CPU time 0.87 seconds
Started Jul 12 05:28:38 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 206812 kb
Host smart-dce922ee-eccf-4bde-be4b-c720ba4f7c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14836
66053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1483666053
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3767805627
Short name T2701
Test name
Test status
Simulation time 7383014522 ps
CPU time 69.43 seconds
Started Jul 12 05:28:37 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 207084 kb
Host smart-9c0af090-4075-4207-8f8b-739d4512a97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
05627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3767805627
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.955334283
Short name T1868
Test name
Test status
Simulation time 4265688363 ps
CPU time 109.23 seconds
Started Jul 12 05:28:37 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 206984 kb
Host smart-f4697216-b2a0-43ae-8043-f6e81970e011
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=955334283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.955334283
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1070264664
Short name T2051
Test name
Test status
Simulation time 170816791 ps
CPU time 0.84 seconds
Started Jul 12 05:28:37 PM PDT 24
Finished Jul 12 05:28:39 PM PDT 24
Peak memory 206796 kb
Host smart-366271f3-b734-4505-b134-921d6a25afc7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1070264664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1070264664
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1931215510
Short name T2088
Test name
Test status
Simulation time 148593162 ps
CPU time 0.79 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 206820 kb
Host smart-1c27f763-08fa-4612-852d-2bc10d0a642c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19312
15510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1931215510
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.909675232
Short name T1618
Test name
Test status
Simulation time 187623998 ps
CPU time 0.88 seconds
Started Jul 12 05:28:34 PM PDT 24
Finished Jul 12 05:28:36 PM PDT 24
Peak memory 206676 kb
Host smart-b58e43d9-e557-4019-8630-fdd905d55127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90967
5232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.909675232
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1398050597
Short name T1493
Test name
Test status
Simulation time 167002547 ps
CPU time 0.78 seconds
Started Jul 12 05:28:39 PM PDT 24
Finished Jul 12 05:28:41 PM PDT 24
Peak memory 206684 kb
Host smart-61a364a1-4a29-40a2-ab79-1f3d28459017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13980
50597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1398050597
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3791146620
Short name T752
Test name
Test status
Simulation time 184199237 ps
CPU time 0.83 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:28:49 PM PDT 24
Peak memory 206820 kb
Host smart-d5c14a88-6234-4c76-b9a8-1d31cfff8daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37911
46620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3791146620
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2863140369
Short name T2137
Test name
Test status
Simulation time 164929769 ps
CPU time 0.81 seconds
Started Jul 12 05:28:38 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 206816 kb
Host smart-89766fa7-331b-4e9f-a68c-0337be3ba374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28631
40369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2863140369
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2921136137
Short name T1123
Test name
Test status
Simulation time 240515756 ps
CPU time 0.94 seconds
Started Jul 12 05:28:47 PM PDT 24
Finished Jul 12 05:28:49 PM PDT 24
Peak memory 205832 kb
Host smart-4d8f217e-6f31-4e03-a3a9-952399cf2eaa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2921136137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2921136137
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.208800550
Short name T32
Test name
Test status
Simulation time 181987991 ps
CPU time 0.77 seconds
Started Jul 12 05:28:38 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 206816 kb
Host smart-b95b6147-b5b6-400e-8e54-06983165af5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20880
0550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.208800550
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.4249778199
Short name T2301
Test name
Test status
Simulation time 19797335934 ps
CPU time 46.9 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 207016 kb
Host smart-982a832b-9f0b-463c-83c1-0fc3ff48fd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42497
78199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.4249778199
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1501547426
Short name T2200
Test name
Test status
Simulation time 142956224 ps
CPU time 0.82 seconds
Started Jul 12 05:28:47 PM PDT 24
Finished Jul 12 05:28:50 PM PDT 24
Peak memory 206812 kb
Host smart-c5821905-7cbd-4471-92ed-b4bbaee68137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15015
47426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1501547426
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1897580382
Short name T815
Test name
Test status
Simulation time 197328743 ps
CPU time 0.86 seconds
Started Jul 12 05:28:42 PM PDT 24
Finished Jul 12 05:28:43 PM PDT 24
Peak memory 206760 kb
Host smart-9efb284c-40e7-4aff-928f-ff2aed84b3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18975
80382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1897580382
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.4255561018
Short name T693
Test name
Test status
Simulation time 262801509 ps
CPU time 0.91 seconds
Started Jul 12 05:28:49 PM PDT 24
Finished Jul 12 05:28:51 PM PDT 24
Peak memory 206804 kb
Host smart-7e5900d3-c9c0-4862-99ac-97eec64d65ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42555
61018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.4255561018
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1718037019
Short name T408
Test name
Test status
Simulation time 193361222 ps
CPU time 0.83 seconds
Started Jul 12 05:28:42 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 206688 kb
Host smart-2d4fa640-88f3-4e33-a745-2fb29711f39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17180
37019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1718037019
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3523925220
Short name T456
Test name
Test status
Simulation time 143423720 ps
CPU time 0.78 seconds
Started Jul 12 05:28:43 PM PDT 24
Finished Jul 12 05:28:45 PM PDT 24
Peak memory 206816 kb
Host smart-ec58ef45-2ead-40eb-9b78-626cf65b3912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35239
25220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3523925220
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3867612054
Short name T1422
Test name
Test status
Simulation time 158143816 ps
CPU time 0.78 seconds
Started Jul 12 05:28:41 PM PDT 24
Finished Jul 12 05:28:43 PM PDT 24
Peak memory 206824 kb
Host smart-9ee7a2b7-c309-47b1-9f78-3e652b6b8140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38676
12054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3867612054
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3678879874
Short name T2284
Test name
Test status
Simulation time 139883866 ps
CPU time 0.73 seconds
Started Jul 12 05:28:42 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 206804 kb
Host smart-b0b18303-9b1f-43ca-a240-afbb87fffeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36788
79874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3678879874
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3014527841
Short name T1241
Test name
Test status
Simulation time 286605726 ps
CPU time 1.04 seconds
Started Jul 12 05:28:41 PM PDT 24
Finished Jul 12 05:28:43 PM PDT 24
Peak memory 206692 kb
Host smart-cb606303-6fc4-46b5-937f-c93d0c1d67e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30145
27841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3014527841
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3747636871
Short name T142
Test name
Test status
Simulation time 4501382850 ps
CPU time 123.81 seconds
Started Jul 12 05:28:41 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 207000 kb
Host smart-ec72c9e5-fc68-406e-8ebf-e4ef40e51ded
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3747636871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3747636871
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2557026696
Short name T1575
Test name
Test status
Simulation time 242273269 ps
CPU time 0.85 seconds
Started Jul 12 05:28:42 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 206768 kb
Host smart-cbc46968-a64c-43af-ac3f-a96581e2a90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25570
26696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2557026696
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.747854768
Short name T2238
Test name
Test status
Simulation time 169828887 ps
CPU time 0.85 seconds
Started Jul 12 05:28:44 PM PDT 24
Finished Jul 12 05:28:46 PM PDT 24
Peak memory 206712 kb
Host smart-a2c133db-2262-4fac-8edf-f5bdf6294fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74785
4768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.747854768
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1295188358
Short name T1119
Test name
Test status
Simulation time 803647151 ps
CPU time 1.86 seconds
Started Jul 12 05:28:44 PM PDT 24
Finished Jul 12 05:28:47 PM PDT 24
Peak memory 206984 kb
Host smart-23aedcb4-53a3-4e70-a228-bc696fcaac32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12951
88358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1295188358
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.821494298
Short name T914
Test name
Test status
Simulation time 6596178259 ps
CPU time 62.13 seconds
Started Jul 12 05:28:49 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 207060 kb
Host smart-106dadc4-cdec-436e-b106-b8f62c5ee62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82149
4298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.821494298
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.226322614
Short name T2613
Test name
Test status
Simulation time 4056885016 ps
CPU time 4.38 seconds
Started Jul 12 05:28:49 PM PDT 24
Finished Jul 12 05:28:54 PM PDT 24
Peak memory 206840 kb
Host smart-53c62322-f2bc-4848-9dc6-9bdca073f506
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=226322614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.226322614
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3576471151
Short name T2647
Test name
Test status
Simulation time 13420511760 ps
CPU time 15.63 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:29:03 PM PDT 24
Peak memory 206888 kb
Host smart-2e8814a2-13b1-410a-afbb-e4c34c1c46b4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3576471151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3576471151
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1477387873
Short name T1982
Test name
Test status
Simulation time 23349127704 ps
CPU time 27.63 seconds
Started Jul 12 05:28:43 PM PDT 24
Finished Jul 12 05:29:12 PM PDT 24
Peak memory 207024 kb
Host smart-2d45a3b6-d387-4995-850c-b6b5715f13b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1477387873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1477387873
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2716952045
Short name T988
Test name
Test status
Simulation time 167149454 ps
CPU time 0.82 seconds
Started Jul 12 05:28:43 PM PDT 24
Finished Jul 12 05:28:45 PM PDT 24
Peak memory 206812 kb
Host smart-8c733592-7eab-4194-b1a9-3cdb7f8bba7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27169
52045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2716952045
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.998241592
Short name T540
Test name
Test status
Simulation time 146847399 ps
CPU time 0.79 seconds
Started Jul 12 05:28:41 PM PDT 24
Finished Jul 12 05:28:42 PM PDT 24
Peak memory 206808 kb
Host smart-fdfabde6-ec08-4c10-8c2c-a42243bc1718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99824
1592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.998241592
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.64581371
Short name T80
Test name
Test status
Simulation time 174462208 ps
CPU time 0.83 seconds
Started Jul 12 05:28:45 PM PDT 24
Finished Jul 12 05:28:46 PM PDT 24
Peak memory 206832 kb
Host smart-793938d9-0375-4559-bd83-6cb24a459eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64581
371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.64581371
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1258038095
Short name T735
Test name
Test status
Simulation time 1126260696 ps
CPU time 2.38 seconds
Started Jul 12 05:28:44 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 207012 kb
Host smart-03a353cc-e086-4cb6-a090-8a4e551e8802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12580
38095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1258038095
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.1970758443
Short name T2326
Test name
Test status
Simulation time 20458705452 ps
CPU time 38.08 seconds
Started Jul 12 05:28:41 PM PDT 24
Finished Jul 12 05:29:19 PM PDT 24
Peak memory 207080 kb
Host smart-1883a2d5-4482-4d27-bc78-3b041ef83fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
58443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1970758443
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2148905370
Short name T1429
Test name
Test status
Simulation time 318930715 ps
CPU time 1.11 seconds
Started Jul 12 05:28:48 PM PDT 24
Finished Jul 12 05:28:50 PM PDT 24
Peak memory 206812 kb
Host smart-9c346e17-ddf6-4ad9-a2e9-6c20deb2a7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21489
05370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2148905370
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3578632286
Short name T985
Test name
Test status
Simulation time 137395520 ps
CPU time 0.73 seconds
Started Jul 12 05:28:46 PM PDT 24
Finished Jul 12 05:28:49 PM PDT 24
Peak memory 206704 kb
Host smart-b85b1572-5680-4e88-90b7-4f21716cf835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35786
32286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3578632286
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1197812909
Short name T1343
Test name
Test status
Simulation time 38681886 ps
CPU time 0.68 seconds
Started Jul 12 05:28:43 PM PDT 24
Finished Jul 12 05:28:45 PM PDT 24
Peak memory 206808 kb
Host smart-3f2fb10b-65ed-4d32-a61f-f1e136ef8511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11978
12909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1197812909
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.4138486386
Short name T970
Test name
Test status
Simulation time 861203260 ps
CPU time 2.01 seconds
Started Jul 12 05:28:48 PM PDT 24
Finished Jul 12 05:28:52 PM PDT 24
Peak memory 207000 kb
Host smart-0aa675f0-be44-49b6-9e65-6e0db18ebcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41384
86386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.4138486386
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3864608974
Short name T979
Test name
Test status
Simulation time 216748997 ps
CPU time 1.94 seconds
Started Jul 12 05:28:42 PM PDT 24
Finished Jul 12 05:28:45 PM PDT 24
Peak memory 206932 kb
Host smart-49b7d8d2-a10b-4436-beb7-e4df16f7e637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38646
08974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3864608974
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2048804055
Short name T1667
Test name
Test status
Simulation time 202726477 ps
CPU time 0.86 seconds
Started Jul 12 05:28:42 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 206808 kb
Host smart-79168902-e44e-4347-bf92-a0eb484ffa8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20488
04055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2048804055
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1588682712
Short name T2154
Test name
Test status
Simulation time 145281180 ps
CPU time 0.74 seconds
Started Jul 12 05:28:49 PM PDT 24
Finished Jul 12 05:28:51 PM PDT 24
Peak memory 206792 kb
Host smart-8da40335-a3f2-47e5-a230-e724aff48a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15886
82712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1588682712
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1817709075
Short name T2353
Test name
Test status
Simulation time 215603909 ps
CPU time 0.87 seconds
Started Jul 12 05:28:41 PM PDT 24
Finished Jul 12 05:28:43 PM PDT 24
Peak memory 206820 kb
Host smart-a3011628-071e-4ed1-a021-3fe4c463025f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18177
09075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1817709075
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.2394857738
Short name T1415
Test name
Test status
Simulation time 7902970638 ps
CPU time 68.91 seconds
Started Jul 12 05:28:42 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 207060 kb
Host smart-f946faea-9a89-480a-8418-541b14613ca5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2394857738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.2394857738
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3525514614
Short name T2600
Test name
Test status
Simulation time 220904593 ps
CPU time 0.88 seconds
Started Jul 12 05:28:54 PM PDT 24
Finished Jul 12 05:28:56 PM PDT 24
Peak memory 206688 kb
Host smart-a0f5db9d-b778-4505-b75c-44788d39daf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35255
14614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3525514614
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3725645202
Short name T713
Test name
Test status
Simulation time 23354849192 ps
CPU time 28.93 seconds
Started Jul 12 05:28:56 PM PDT 24
Finished Jul 12 05:29:25 PM PDT 24
Peak memory 206868 kb
Host smart-95eb5525-de57-47df-bf37-0a889dd0d549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37256
45202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3725645202
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3674932602
Short name T635
Test name
Test status
Simulation time 3315843392 ps
CPU time 3.51 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:58 PM PDT 24
Peak memory 207100 kb
Host smart-cced9ae1-be90-4a65-9759-277e6e6a1bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36749
32602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3674932602
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2644117456
Short name T2595
Test name
Test status
Simulation time 11410447143 ps
CPU time 104.7 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 207092 kb
Host smart-ea850658-6ccb-4fd6-8fdb-c1f0d489e4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26441
17456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2644117456
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3851203192
Short name T1642
Test name
Test status
Simulation time 4635027603 ps
CPU time 31.98 seconds
Started Jul 12 05:28:49 PM PDT 24
Finished Jul 12 05:29:22 PM PDT 24
Peak memory 206964 kb
Host smart-6116a214-9405-4cae-a948-30c12598b5ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3851203192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3851203192
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2534407506
Short name T1756
Test name
Test status
Simulation time 258402839 ps
CPU time 1.01 seconds
Started Jul 12 05:28:51 PM PDT 24
Finished Jul 12 05:28:53 PM PDT 24
Peak memory 206816 kb
Host smart-4214c896-d4a3-4aaa-b93a-06516ee37684
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2534407506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2534407506
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3466918386
Short name T1552
Test name
Test status
Simulation time 222784535 ps
CPU time 0.87 seconds
Started Jul 12 05:28:47 PM PDT 24
Finished Jul 12 05:28:49 PM PDT 24
Peak memory 206808 kb
Host smart-cfc369fd-ca37-4948-a90d-f831f111fd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34669
18386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3466918386
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.2786713577
Short name T148
Test name
Test status
Simulation time 4207181162 ps
CPU time 114.91 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:30:49 PM PDT 24
Peak memory 206928 kb
Host smart-4b6e3b0c-4654-4538-8575-ac92fc878b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
13577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.2786713577
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2819668896
Short name T2038
Test name
Test status
Simulation time 4614631189 ps
CPU time 33.68 seconds
Started Jul 12 05:28:58 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 206976 kb
Host smart-c64045bf-d79a-48b6-a514-bdf129a39f96
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2819668896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2819668896
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2831259865
Short name T926
Test name
Test status
Simulation time 161279095 ps
CPU time 0.83 seconds
Started Jul 12 05:28:54 PM PDT 24
Finished Jul 12 05:28:56 PM PDT 24
Peak memory 206812 kb
Host smart-c11cb529-4fcf-4168-b223-aaf2a72d952b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2831259865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2831259865
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.938858523
Short name T2295
Test name
Test status
Simulation time 156791631 ps
CPU time 0.79 seconds
Started Jul 12 05:28:54 PM PDT 24
Finished Jul 12 05:28:56 PM PDT 24
Peak memory 206816 kb
Host smart-e1b11fdd-8570-4daf-890f-293609224328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93885
8523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.938858523
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2322884656
Short name T1874
Test name
Test status
Simulation time 185484706 ps
CPU time 0.82 seconds
Started Jul 12 05:28:55 PM PDT 24
Finished Jul 12 05:28:57 PM PDT 24
Peak memory 206808 kb
Host smart-78e18838-ba54-465a-aa65-94bf6c62bd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228
84656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2322884656
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3323348059
Short name T715
Test name
Test status
Simulation time 150665147 ps
CPU time 0.81 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206808 kb
Host smart-7cf6cb06-da6b-42e6-aefb-7d2dbcf4cf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33233
48059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3323348059
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.4234499273
Short name T899
Test name
Test status
Simulation time 158836673 ps
CPU time 0.81 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206820 kb
Host smart-b546c850-352f-456d-895b-edceebb5ec37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42344
99273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.4234499273
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.645774394
Short name T2623
Test name
Test status
Simulation time 149985932 ps
CPU time 0.81 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206832 kb
Host smart-41e57098-4d10-419b-ada2-edf4a4b8dbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64577
4394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.645774394
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2855408701
Short name T479
Test name
Test status
Simulation time 235482339 ps
CPU time 0.99 seconds
Started Jul 12 05:28:49 PM PDT 24
Finished Jul 12 05:28:51 PM PDT 24
Peak memory 206820 kb
Host smart-1944dd17-6aab-49c8-9d62-9572cce64b16
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2855408701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2855408701
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2268374763
Short name T2362
Test name
Test status
Simulation time 183871115 ps
CPU time 0.79 seconds
Started Jul 12 05:28:50 PM PDT 24
Finished Jul 12 05:28:52 PM PDT 24
Peak memory 206816 kb
Host smart-70556c23-7a47-4020-8309-96333b6d710e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22683
74763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2268374763
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3253372594
Short name T1380
Test name
Test status
Simulation time 21318356177 ps
CPU time 48.52 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:48 PM PDT 24
Peak memory 207172 kb
Host smart-66e74f5b-d1d7-4b72-98d9-e30291cec678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32533
72594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3253372594
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2847813656
Short name T619
Test name
Test status
Simulation time 189560010 ps
CPU time 0.86 seconds
Started Jul 12 05:28:49 PM PDT 24
Finished Jul 12 05:28:51 PM PDT 24
Peak memory 206696 kb
Host smart-188ae9fa-b75f-434d-938e-2103ac0de799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28478
13656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2847813656
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.4253940175
Short name T1368
Test name
Test status
Simulation time 212909794 ps
CPU time 0.89 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206712 kb
Host smart-83cc5b59-cc02-40d7-bba7-9ce002e0dc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42539
40175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.4253940175
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1289508828
Short name T223
Test name
Test status
Simulation time 180368121 ps
CPU time 0.83 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206696 kb
Host smart-c7f57ae8-e9e4-40ce-a77b-54f2c3577494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12895
08828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1289508828
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1957583172
Short name T828
Test name
Test status
Simulation time 217865003 ps
CPU time 0.85 seconds
Started Jul 12 05:29:12 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 206672 kb
Host smart-03e02071-f372-4d04-8158-a7b29421b3dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19575
83172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1957583172
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.4204286895
Short name T2606
Test name
Test status
Simulation time 216542559 ps
CPU time 0.8 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206048 kb
Host smart-78b368ff-6cf6-482f-8ddf-9bdb35ac2468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42042
86895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.4204286895
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3576603232
Short name T1008
Test name
Test status
Simulation time 147942204 ps
CPU time 0.77 seconds
Started Jul 12 05:28:51 PM PDT 24
Finished Jul 12 05:28:53 PM PDT 24
Peak memory 206816 kb
Host smart-48cc2250-eebf-4a1a-86a7-f92e418e33d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766
03232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3576603232
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.542898252
Short name T804
Test name
Test status
Simulation time 154544889 ps
CPU time 0.78 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:28:59 PM PDT 24
Peak memory 206808 kb
Host smart-d40afae0-bc19-452a-8806-0e3c634214f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54289
8252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.542898252
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1733593826
Short name T1025
Test name
Test status
Simulation time 210527269 ps
CPU time 0.89 seconds
Started Jul 12 05:28:51 PM PDT 24
Finished Jul 12 05:28:53 PM PDT 24
Peak memory 206760 kb
Host smart-22794e7e-9c20-423b-adfe-675858bf102c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17335
93826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1733593826
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1827290802
Short name T435
Test name
Test status
Simulation time 5408072913 ps
CPU time 40.51 seconds
Started Jul 12 05:28:55 PM PDT 24
Finished Jul 12 05:29:37 PM PDT 24
Peak memory 207048 kb
Host smart-97170243-b085-4021-b09a-e71e6a6048a8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1827290802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1827290802
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1887780003
Short name T2206
Test name
Test status
Simulation time 173616436 ps
CPU time 0.79 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206148 kb
Host smart-537a0f93-c5c1-48dd-a1a0-2f0583b38eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18877
80003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1887780003
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2681675717
Short name T2358
Test name
Test status
Simulation time 159670596 ps
CPU time 0.75 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206712 kb
Host smart-91b3e565-e75a-47dd-9d1d-36e471ff7da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26816
75717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2681675717
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3717152824
Short name T1168
Test name
Test status
Simulation time 1265128931 ps
CPU time 2.6 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:56 PM PDT 24
Peak memory 206996 kb
Host smart-1220a43b-ff23-4f5d-a087-1fa62e66bf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37171
52824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3717152824
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3329935105
Short name T1080
Test name
Test status
Simulation time 6624724678 ps
CPU time 179.47 seconds
Started Jul 12 05:28:51 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 207028 kb
Host smart-b11fa4bc-c55f-4740-a480-5bbd6d71408b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299
35105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3329935105
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1413315785
Short name T2657
Test name
Test status
Simulation time 42611552 ps
CPU time 0.69 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:05 PM PDT 24
Peak memory 206488 kb
Host smart-c217d96a-fa72-4314-a435-6573c4862e08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1413315785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1413315785
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3666324242
Short name T2203
Test name
Test status
Simulation time 4362421445 ps
CPU time 5.38 seconds
Started Jul 12 05:28:58 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 206884 kb
Host smart-4be9c7d8-b458-408e-86fb-958ff64cf11e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3666324242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3666324242
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.1179397588
Short name T1013
Test name
Test status
Simulation time 23335539907 ps
CPU time 24.41 seconds
Started Jul 12 05:28:55 PM PDT 24
Finished Jul 12 05:29:20 PM PDT 24
Peak memory 207108 kb
Host smart-69183b88-3596-44bf-88b8-b23a1b8a9baf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1179397588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.1179397588
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3676569636
Short name T406
Test name
Test status
Simulation time 196063901 ps
CPU time 0.85 seconds
Started Jul 12 05:28:53 PM PDT 24
Finished Jul 12 05:28:55 PM PDT 24
Peak memory 206804 kb
Host smart-05b6aac6-0e13-4174-bb01-9105be0f82c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36765
69636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3676569636
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.831102826
Short name T2170
Test name
Test status
Simulation time 147441902 ps
CPU time 0.75 seconds
Started Jul 12 05:28:51 PM PDT 24
Finished Jul 12 05:28:53 PM PDT 24
Peak memory 206768 kb
Host smart-f0184098-c0df-44c7-8b34-77b0670dc034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83110
2826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.831102826
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.917931114
Short name T812
Test name
Test status
Simulation time 212953422 ps
CPU time 0.9 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:03 PM PDT 24
Peak memory 206816 kb
Host smart-d0c00943-6ba8-42de-a493-f84d925238b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91793
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.917931114
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1833206378
Short name T1857
Test name
Test status
Simulation time 517534990 ps
CPU time 1.38 seconds
Started Jul 12 05:29:11 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 206720 kb
Host smart-317f77b9-854f-4472-b8bb-8d3838d0b440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
06378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1833206378
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.1203578083
Short name T161
Test name
Test status
Simulation time 16607126636 ps
CPU time 32.89 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:38 PM PDT 24
Peak memory 207084 kb
Host smart-01d3bde4-dad2-41a6-9531-2bb1b979eea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12035
78083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1203578083
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.325825187
Short name T1693
Test name
Test status
Simulation time 411384888 ps
CPU time 1.26 seconds
Started Jul 12 05:29:03 PM PDT 24
Finished Jul 12 05:29:07 PM PDT 24
Peak memory 206724 kb
Host smart-b312e916-8eb4-433f-a89b-4f011c96a850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32582
5187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.325825187
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2205626317
Short name T1243
Test name
Test status
Simulation time 175530460 ps
CPU time 0.73 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:03 PM PDT 24
Peak memory 206820 kb
Host smart-46e050be-175a-4ce6-b9f8-a3604510b462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22056
26317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2205626317
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1765910933
Short name T2144
Test name
Test status
Simulation time 53178017 ps
CPU time 0.72 seconds
Started Jul 12 05:29:01 PM PDT 24
Finished Jul 12 05:29:04 PM PDT 24
Peak memory 206632 kb
Host smart-d1239e45-1e95-4a41-b982-1f471300a502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17659
10933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1765910933
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1751564590
Short name T796
Test name
Test status
Simulation time 1065198500 ps
CPU time 2.45 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:05 PM PDT 24
Peak memory 206996 kb
Host smart-4afa1947-c834-4534-9bd4-a04fb00efca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515
64590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1751564590
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4023907152
Short name T1536
Test name
Test status
Simulation time 354044867 ps
CPU time 2.09 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:05 PM PDT 24
Peak memory 206948 kb
Host smart-64f5429e-0f19-4ee1-829c-fa1249f16979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40239
07152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4023907152
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2250911948
Short name T1238
Test name
Test status
Simulation time 179756925 ps
CPU time 0.85 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:05 PM PDT 24
Peak memory 206872 kb
Host smart-e4f5986c-87be-4fe0-a8b8-118724cdb240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22509
11948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2250911948
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3091162205
Short name T2185
Test name
Test status
Simulation time 158253470 ps
CPU time 0.8 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:00 PM PDT 24
Peak memory 206980 kb
Host smart-d6798675-b3ac-4c09-b02d-a7e152662ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30911
62205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3091162205
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1796537607
Short name T2578
Test name
Test status
Simulation time 222191093 ps
CPU time 0.92 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:04 PM PDT 24
Peak memory 206832 kb
Host smart-21657729-2f5e-4629-802e-d530d550e41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17965
37607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1796537607
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.4292979487
Short name T74
Test name
Test status
Simulation time 8755220155 ps
CPU time 63.27 seconds
Started Jul 12 05:29:05 PM PDT 24
Finished Jul 12 05:30:11 PM PDT 24
Peak memory 206900 kb
Host smart-e25bf3cc-9bb9-427f-a409-682549b2308f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4292979487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.4292979487
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3312247580
Short name T2259
Test name
Test status
Simulation time 169514712 ps
CPU time 0.81 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:28:58 PM PDT 24
Peak memory 206816 kb
Host smart-fa3d3ef3-21ff-43b7-8921-afa568593e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33122
47580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3312247580
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1790782941
Short name T1754
Test name
Test status
Simulation time 23333583550 ps
CPU time 22.01 seconds
Started Jul 12 05:28:58 PM PDT 24
Finished Jul 12 05:29:23 PM PDT 24
Peak memory 206776 kb
Host smart-6d65914f-e547-4fda-93d2-f6b048a93e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17907
82941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1790782941
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3542843157
Short name T380
Test name
Test status
Simulation time 3329805900 ps
CPU time 3.5 seconds
Started Jul 12 05:28:58 PM PDT 24
Finished Jul 12 05:29:05 PM PDT 24
Peak memory 206880 kb
Host smart-63e88bd4-7eda-47bc-bded-6b688d93b9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428
43157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3542843157
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.501100734
Short name T1163
Test name
Test status
Simulation time 9408566549 ps
CPU time 94.14 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 207104 kb
Host smart-fecefdda-aec6-489c-9d3a-2663446f8dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50110
0734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.501100734
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.4020279665
Short name T1327
Test name
Test status
Simulation time 4648719725 ps
CPU time 130.73 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:31:11 PM PDT 24
Peak memory 207012 kb
Host smart-2d24bec8-6cd1-4a4f-9405-32da884cf439
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4020279665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.4020279665
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.3241252344
Short name T2555
Test name
Test status
Simulation time 239963392 ps
CPU time 0.96 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:04 PM PDT 24
Peak memory 206792 kb
Host smart-2ce59318-dedd-4456-8361-7fb7021a7a34
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3241252344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.3241252344
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.144350930
Short name T772
Test name
Test status
Simulation time 203349975 ps
CPU time 0.92 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:02 PM PDT 24
Peak memory 206800 kb
Host smart-c03eb390-6d07-4f5b-837f-9c3cdeeaf061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14435
0930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.144350930
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1590702393
Short name T1945
Test name
Test status
Simulation time 4861864104 ps
CPU time 32.96 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:33 PM PDT 24
Peak memory 206968 kb
Host smart-4ec199f9-c735-4276-8fbc-fe27e2e1e8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15907
02393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1590702393
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.833761986
Short name T1740
Test name
Test status
Simulation time 5089214116 ps
CPU time 37.41 seconds
Started Jul 12 05:28:56 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 207060 kb
Host smart-3f0e7134-b16d-43a4-8a0c-3d419a4cc8c6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=833761986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.833761986
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.4269242337
Short name T1803
Test name
Test status
Simulation time 239897631 ps
CPU time 0.89 seconds
Started Jul 12 05:28:59 PM PDT 24
Finished Jul 12 05:29:03 PM PDT 24
Peak memory 206824 kb
Host smart-a54cc070-60be-4e84-bf76-c19a7fc4834c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4269242337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.4269242337
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3539008655
Short name T438
Test name
Test status
Simulation time 146657530 ps
CPU time 0.77 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:01 PM PDT 24
Peak memory 206820 kb
Host smart-4f90b489-d64c-4592-affc-c890af164d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35390
08655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3539008655
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1828845236
Short name T127
Test name
Test status
Simulation time 223036355 ps
CPU time 0.93 seconds
Started Jul 12 05:28:59 PM PDT 24
Finished Jul 12 05:29:03 PM PDT 24
Peak memory 206804 kb
Host smart-42c970a6-f8d6-46be-9217-4e491e868b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18288
45236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1828845236
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.511272389
Short name T1669
Test name
Test status
Simulation time 196335631 ps
CPU time 0.85 seconds
Started Jul 12 05:29:33 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 206676 kb
Host smart-885eb7db-9700-44bb-9d8b-0cca544fa7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51127
2389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.511272389
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2383364585
Short name T750
Test name
Test status
Simulation time 180624034 ps
CPU time 0.81 seconds
Started Jul 12 05:28:55 PM PDT 24
Finished Jul 12 05:28:57 PM PDT 24
Peak memory 206800 kb
Host smart-9dbfcff4-45ec-43d8-8f9e-809fddee7abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23833
64585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2383364585
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.585219929
Short name T1183
Test name
Test status
Simulation time 149891528 ps
CPU time 0.77 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:04 PM PDT 24
Peak memory 206636 kb
Host smart-9b94ead9-352f-4cdc-a1ed-860551122121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58521
9929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.585219929
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.286667603
Short name T1964
Test name
Test status
Simulation time 146875359 ps
CPU time 0.83 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:01 PM PDT 24
Peak memory 206724 kb
Host smart-d5d5eb70-1f19-4f0b-a692-0fb750a1c238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28666
7603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.286667603
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2030076563
Short name T1677
Test name
Test status
Simulation time 198994116 ps
CPU time 0.93 seconds
Started Jul 12 05:28:56 PM PDT 24
Finished Jul 12 05:28:58 PM PDT 24
Peak memory 206796 kb
Host smart-8db25be1-6689-4ebf-8ff0-c4ad45b45bfc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2030076563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2030076563
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3106676354
Short name T409
Test name
Test status
Simulation time 188907080 ps
CPU time 0.83 seconds
Started Jul 12 05:29:07 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206804 kb
Host smart-3fd1bfe5-2f02-4a99-b98e-8b0246247fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
76354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3106676354
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1579401210
Short name T30
Test name
Test status
Simulation time 70052633 ps
CPU time 0.7 seconds
Started Jul 12 05:28:58 PM PDT 24
Finished Jul 12 05:29:02 PM PDT 24
Peak memory 206812 kb
Host smart-f26e9ec5-1fef-4c13-83d5-0674eba4a506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15794
01210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1579401210
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1335078089
Short name T1949
Test name
Test status
Simulation time 22255851429 ps
CPU time 47.06 seconds
Started Jul 12 05:28:59 PM PDT 24
Finished Jul 12 05:29:49 PM PDT 24
Peak memory 207068 kb
Host smart-ca34a595-fc21-47ec-9a12-d61ff89a99f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13350
78089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1335078089
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2688211192
Short name T1954
Test name
Test status
Simulation time 178084538 ps
CPU time 0.85 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:03 PM PDT 24
Peak memory 206812 kb
Host smart-57344b79-f0c5-497c-b3fa-d790ff06a243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26882
11192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2688211192
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.377301125
Short name T1162
Test name
Test status
Simulation time 192970484 ps
CPU time 0.88 seconds
Started Jul 12 05:28:57 PM PDT 24
Finished Jul 12 05:29:01 PM PDT 24
Peak memory 206816 kb
Host smart-a2d8a485-c7e7-4113-baa2-89a5517ec6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37730
1125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.377301125
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.53391088
Short name T1533
Test name
Test status
Simulation time 176402342 ps
CPU time 0.85 seconds
Started Jul 12 05:28:56 PM PDT 24
Finished Jul 12 05:28:58 PM PDT 24
Peak memory 206700 kb
Host smart-764968f6-e804-4baf-b9b9-cc9d99b2a749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53391
088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.53391088
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3978616355
Short name T463
Test name
Test status
Simulation time 184299044 ps
CPU time 0.88 seconds
Started Jul 12 05:28:58 PM PDT 24
Finished Jul 12 05:29:02 PM PDT 24
Peak memory 206804 kb
Host smart-f8db03c3-1b1e-49a5-8394-0fdb11e51800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39786
16355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3978616355
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1401945404
Short name T2298
Test name
Test status
Simulation time 214784644 ps
CPU time 0.83 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206712 kb
Host smart-13a0a944-5760-4154-8c1a-03055ce67920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14019
45404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1401945404
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3094731077
Short name T2364
Test name
Test status
Simulation time 145618270 ps
CPU time 0.78 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206804 kb
Host smart-2cb49856-baec-42a8-b437-c7a7e77cca00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30947
31077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3094731077
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3623056050
Short name T1608
Test name
Test status
Simulation time 219342095 ps
CPU time 0.86 seconds
Started Jul 12 05:29:01 PM PDT 24
Finished Jul 12 05:29:05 PM PDT 24
Peak memory 206772 kb
Host smart-58c296f6-b6d9-4e5b-a7fb-b16d6c798669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36230
56050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3623056050
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3494764768
Short name T2545
Test name
Test status
Simulation time 214628152 ps
CPU time 0.9 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:08 PM PDT 24
Peak memory 206716 kb
Host smart-e003fcfd-4d3a-40d3-82b2-57e43c89b3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
64768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3494764768
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.4145149621
Short name T1812
Test name
Test status
Simulation time 4351200611 ps
CPU time 32.01 seconds
Started Jul 12 05:29:01 PM PDT 24
Finished Jul 12 05:29:36 PM PDT 24
Peak memory 206728 kb
Host smart-08cdb3e4-3a0d-468e-8e4f-3a2dc3c3c909
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4145149621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.4145149621
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3568980450
Short name T1630
Test name
Test status
Simulation time 146011916 ps
CPU time 0.81 seconds
Started Jul 12 05:29:11 PM PDT 24
Finished Jul 12 05:29:13 PM PDT 24
Peak memory 206816 kb
Host smart-b08da685-ed81-420a-9dc3-4bed7c70dff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35689
80450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3568980450
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2951349299
Short name T1426
Test name
Test status
Simulation time 183219106 ps
CPU time 0.8 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206808 kb
Host smart-66a19e27-2ac0-4716-b27d-d72f5190efcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29513
49299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2951349299
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.1805531156
Short name T933
Test name
Test status
Simulation time 244429387 ps
CPU time 0.97 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:04 PM PDT 24
Peak memory 206836 kb
Host smart-e71d9d4a-bfea-44b9-9973-b8208c797615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18055
31156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1805531156
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.760711985
Short name T2352
Test name
Test status
Simulation time 3155981145 ps
CPU time 29.8 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 207036 kb
Host smart-664355a2-5e5b-48b0-a6bd-53979f17b6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76071
1985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.760711985
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1996478205
Short name T1632
Test name
Test status
Simulation time 93132131 ps
CPU time 0.69 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:17 PM PDT 24
Peak memory 206872 kb
Host smart-181503ee-4b2d-498a-ba18-8d9d0161224f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1996478205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1996478205
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1303663722
Short name T2525
Test name
Test status
Simulation time 4128303935 ps
CPU time 5.04 seconds
Started Jul 12 05:28:58 PM PDT 24
Finished Jul 12 05:29:07 PM PDT 24
Peak memory 207028 kb
Host smart-1f53cc76-97ec-4907-9b71-497819e89111
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1303663722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1303663722
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2665775627
Short name T1830
Test name
Test status
Simulation time 13364971924 ps
CPU time 12.08 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:17 PM PDT 24
Peak memory 206856 kb
Host smart-40178cb7-4e2f-4141-88a7-2d31680d1e03
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2665775627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2665775627
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2981007839
Short name T2581
Test name
Test status
Simulation time 23423287104 ps
CPU time 27.4 seconds
Started Jul 12 05:29:00 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 207084 kb
Host smart-bdcf6ddf-5711-4916-b717-89bb4f9ff97b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2981007839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2981007839
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2858308937
Short name T412
Test name
Test status
Simulation time 187252985 ps
CPU time 0.85 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 206816 kb
Host smart-0493c49f-3dbe-4585-bf78-3b4a56fa985b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
08937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2858308937
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.296920539
Short name T802
Test name
Test status
Simulation time 147684200 ps
CPU time 0.76 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 206780 kb
Host smart-b8eef2aa-2cfd-4a65-b689-a9ffc039c176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29692
0539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.296920539
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2807939846
Short name T1030
Test name
Test status
Simulation time 361654805 ps
CPU time 1.3 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 206820 kb
Host smart-e87542ef-8f25-4fb4-af70-6b9933c2603a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28079
39846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2807939846
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3826656451
Short name T2738
Test name
Test status
Simulation time 347639581 ps
CPU time 1.09 seconds
Started Jul 12 05:29:14 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206820 kb
Host smart-8d6bd1b6-00cb-4063-8a9b-8ab374da8c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38266
56451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3826656451
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.1794834955
Short name T729
Test name
Test status
Simulation time 6232454130 ps
CPU time 12.37 seconds
Started Jul 12 05:29:07 PM PDT 24
Finished Jul 12 05:29:22 PM PDT 24
Peak memory 206904 kb
Host smart-c9595768-2da7-4362-8583-099d97f17b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17948
34955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.1794834955
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1718138322
Short name T688
Test name
Test status
Simulation time 398643069 ps
CPU time 1.34 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:08 PM PDT 24
Peak memory 206796 kb
Host smart-9e318eba-dd11-4723-8752-eb4748b539bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17181
38322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1718138322
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.399457059
Short name T2632
Test name
Test status
Simulation time 167323988 ps
CPU time 0.97 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:09 PM PDT 24
Peak memory 206812 kb
Host smart-aacc69a2-69a7-4309-8472-8bdc0aa5df8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39945
7059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.399457059
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2075114238
Short name T597
Test name
Test status
Simulation time 42217551 ps
CPU time 0.7 seconds
Started Jul 12 05:29:07 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206828 kb
Host smart-155dad49-fbcd-4108-92d6-1c158032996f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20751
14238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2075114238
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3676744387
Short name T1456
Test name
Test status
Simulation time 943788916 ps
CPU time 2.32 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:12 PM PDT 24
Peak memory 206612 kb
Host smart-f9471d4b-264e-43b0-940e-567bda7ca753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36767
44387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3676744387
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.4039975877
Short name T392
Test name
Test status
Simulation time 198735748 ps
CPU time 1.7 seconds
Started Jul 12 05:29:07 PM PDT 24
Finished Jul 12 05:29:12 PM PDT 24
Peak memory 207072 kb
Host smart-10f2ef98-ef80-4e15-86ca-20b45e28f6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40399
75877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4039975877
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.4072084633
Short name T2709
Test name
Test status
Simulation time 287506851 ps
CPU time 0.95 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:07 PM PDT 24
Peak memory 206824 kb
Host smart-c4fee505-4ec5-43ad-a552-4c42ff3f6e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40720
84633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.4072084633
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3369552300
Short name T2363
Test name
Test status
Simulation time 148508336 ps
CPU time 0.77 seconds
Started Jul 12 05:29:07 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206692 kb
Host smart-8835574e-d99e-4f72-bed1-6f1c7bf292d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33695
52300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3369552300
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1500296233
Short name T2569
Test name
Test status
Simulation time 185663269 ps
CPU time 0.88 seconds
Started Jul 12 05:29:05 PM PDT 24
Finished Jul 12 05:29:09 PM PDT 24
Peak memory 206808 kb
Host smart-1b761b1f-9c3b-4643-9c59-3065d8c00641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15002
96233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1500296233
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.932488577
Short name T97
Test name
Test status
Simulation time 6968227767 ps
CPU time 53.73 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:30:00 PM PDT 24
Peak memory 207028 kb
Host smart-11a68cd1-43eb-406e-9b28-b15bca36b130
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=932488577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.932488577
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.2862249110
Short name T1929
Test name
Test status
Simulation time 12338967496 ps
CPU time 49.53 seconds
Started Jul 12 05:29:03 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 207068 kb
Host smart-31849d72-39a9-472f-9334-7047a8b47623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28622
49110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2862249110
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1683070341
Short name T2599
Test name
Test status
Simulation time 193141654 ps
CPU time 0.85 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:07 PM PDT 24
Peak memory 206812 kb
Host smart-f72887fd-3f02-44c6-9883-a93156564aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16830
70341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1683070341
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2025504892
Short name T1728
Test name
Test status
Simulation time 23306456310 ps
CPU time 24.53 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:33 PM PDT 24
Peak memory 206896 kb
Host smart-eb173529-8616-4afc-b113-7608699da759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20255
04892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2025504892
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3826688506
Short name T720
Test name
Test status
Simulation time 3259324267 ps
CPU time 3.4 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:21 PM PDT 24
Peak memory 206724 kb
Host smart-9420c393-4d75-42ea-9e15-e36523101392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38266
88506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3826688506
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.105067794
Short name T491
Test name
Test status
Simulation time 6996537541 ps
CPU time 60.65 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:30:18 PM PDT 24
Peak memory 206936 kb
Host smart-89705b5d-4101-4e08-b020-37199b3498f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
7794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.105067794
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1140454293
Short name T340
Test name
Test status
Simulation time 6361194958 ps
CPU time 47.36 seconds
Started Jul 12 05:29:05 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 207024 kb
Host smart-8cf549d9-12b3-4f82-a294-05de0c160470
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1140454293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1140454293
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.84056533
Short name T504
Test name
Test status
Simulation time 273953121 ps
CPU time 0.93 seconds
Started Jul 12 05:29:08 PM PDT 24
Finished Jul 12 05:29:11 PM PDT 24
Peak memory 206808 kb
Host smart-1fb97fcd-c945-45c4-aebc-a1c7edfd3040
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=84056533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.84056533
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1586614766
Short name T817
Test name
Test status
Simulation time 191388518 ps
CPU time 0.87 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:29:05 PM PDT 24
Peak memory 206700 kb
Host smart-767fe498-89e9-4159-bd86-00bbf4876c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15866
14766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1586614766
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.654631342
Short name T2530
Test name
Test status
Simulation time 5051588127 ps
CPU time 37.58 seconds
Started Jul 12 05:29:03 PM PDT 24
Finished Jul 12 05:29:43 PM PDT 24
Peak memory 207016 kb
Host smart-939d6b5b-4d3d-408e-a8b6-afbdf9354dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65463
1342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.654631342
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3871894687
Short name T1558
Test name
Test status
Simulation time 3700936551 ps
CPU time 28.68 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 207064 kb
Host smart-30ade9e6-7fa3-4d69-8d63-01c149f7eb82
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3871894687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3871894687
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.503349124
Short name T1805
Test name
Test status
Simulation time 170472493 ps
CPU time 0.81 seconds
Started Jul 12 05:29:05 PM PDT 24
Finished Jul 12 05:29:08 PM PDT 24
Peak memory 206820 kb
Host smart-4165adbc-90b8-45c7-9fe2-307c29ce5734
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=503349124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.503349124
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3104755508
Short name T1500
Test name
Test status
Simulation time 215375878 ps
CPU time 0.84 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:16 PM PDT 24
Peak memory 206820 kb
Host smart-091cfd93-ba95-488b-b40c-0b2dd315f73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31047
55508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3104755508
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2461002972
Short name T131
Test name
Test status
Simulation time 218317187 ps
CPU time 0.89 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206716 kb
Host smart-4297870e-3f99-493d-b76e-ecbcf2e3c2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24610
02972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2461002972
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1592184066
Short name T96
Test name
Test status
Simulation time 222450815 ps
CPU time 1 seconds
Started Jul 12 05:29:03 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 206800 kb
Host smart-a1a10fad-1255-4fa8-a267-172284404cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15921
84066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1592184066
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3256756388
Short name T2660
Test name
Test status
Simulation time 150372961 ps
CPU time 0.81 seconds
Started Jul 12 05:29:14 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206820 kb
Host smart-00396b7f-7517-4262-858a-6d2a3a125607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
56388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3256756388
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2579740973
Short name T1067
Test name
Test status
Simulation time 161773873 ps
CPU time 0.8 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:08 PM PDT 24
Peak memory 206804 kb
Host smart-61f65397-fb66-463e-82b7-abd2b946ac1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25797
40973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2579740973
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1644705112
Short name T166
Test name
Test status
Simulation time 159205933 ps
CPU time 0.83 seconds
Started Jul 12 05:29:03 PM PDT 24
Finished Jul 12 05:29:06 PM PDT 24
Peak memory 206704 kb
Host smart-cf728895-274b-479f-93f9-4f72df4a78d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16447
05112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1644705112
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1016381754
Short name T762
Test name
Test status
Simulation time 211720600 ps
CPU time 0.88 seconds
Started Jul 12 05:29:16 PM PDT 24
Finished Jul 12 05:29:19 PM PDT 24
Peak memory 206660 kb
Host smart-37710235-a445-432c-951b-1355991da3f8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1016381754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1016381754
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4250605558
Short name T1931
Test name
Test status
Simulation time 187273974 ps
CPU time 0.84 seconds
Started Jul 12 05:29:05 PM PDT 24
Finished Jul 12 05:29:08 PM PDT 24
Peak memory 206824 kb
Host smart-7cb47792-14a2-4546-a601-024e35d65283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42506
05558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4250605558
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1237813158
Short name T836
Test name
Test status
Simulation time 93869604 ps
CPU time 0.66 seconds
Started Jul 12 05:29:14 PM PDT 24
Finished Jul 12 05:29:17 PM PDT 24
Peak memory 206652 kb
Host smart-6fde50bd-0123-4278-a137-f64f368094d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
13158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1237813158
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3002347214
Short name T2270
Test name
Test status
Simulation time 16875123694 ps
CPU time 40.02 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 207060 kb
Host smart-fd993406-8151-4c28-9ed2-8859e87c68df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023
47214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3002347214
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1619868602
Short name T2036
Test name
Test status
Simulation time 190617943 ps
CPU time 0.85 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206816 kb
Host smart-c8e94200-e714-4af5-b210-4f5cd3698bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
68602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1619868602
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3573398852
Short name T903
Test name
Test status
Simulation time 176586780 ps
CPU time 0.84 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206656 kb
Host smart-24f8667d-cc7d-4bf3-bd09-26a33fd8c231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35733
98852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3573398852
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3854176450
Short name T2007
Test name
Test status
Simulation time 267520443 ps
CPU time 0.91 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206840 kb
Host smart-e07275ef-fbfe-44f7-8790-c071c4fdb69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
76450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3854176450
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.4180456466
Short name T866
Test name
Test status
Simulation time 155138247 ps
CPU time 0.8 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:09 PM PDT 24
Peak memory 206704 kb
Host smart-59667bd8-d1b1-4d75-817a-48caf79697e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41804
56466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.4180456466
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.4122226044
Short name T770
Test name
Test status
Simulation time 210070976 ps
CPU time 0.83 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:07 PM PDT 24
Peak memory 206812 kb
Host smart-b279615a-64be-4490-bcc3-73be1ca268a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41222
26044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.4122226044
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.4156843936
Short name T1116
Test name
Test status
Simulation time 152433715 ps
CPU time 0.8 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:07 PM PDT 24
Peak memory 206792 kb
Host smart-88ccc9d9-3179-4da0-9365-fc92889d0e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41568
43936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.4156843936
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.227185434
Short name T243
Test name
Test status
Simulation time 144602252 ps
CPU time 0.75 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206652 kb
Host smart-b2799b3b-4d92-4c12-bc27-0da6e6d67697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22718
5434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.227185434
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2315613530
Short name T436
Test name
Test status
Simulation time 223822040 ps
CPU time 0.91 seconds
Started Jul 12 05:29:07 PM PDT 24
Finished Jul 12 05:29:11 PM PDT 24
Peak memory 206688 kb
Host smart-715c36e3-f588-4204-b4ed-320a7524940d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23156
13530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2315613530
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.48546782
Short name T373
Test name
Test status
Simulation time 3160931499 ps
CPU time 80 seconds
Started Jul 12 05:29:02 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206928 kb
Host smart-db605a6c-ebbc-4c3f-8514-39119f870741
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=48546782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.48546782
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3417646488
Short name T2459
Test name
Test status
Simulation time 154090051 ps
CPU time 0.78 seconds
Started Jul 12 05:29:06 PM PDT 24
Finished Jul 12 05:29:10 PM PDT 24
Peak memory 206304 kb
Host smart-51cd0c52-d1f2-48fe-abd3-1299081e3c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34176
46488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3417646488
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2224041566
Short name T319
Test name
Test status
Simulation time 169612682 ps
CPU time 0.84 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:08 PM PDT 24
Peak memory 206632 kb
Host smart-afa562fc-8dcb-4d93-9339-7d49c1d5f3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
41566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2224041566
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1064032388
Short name T1937
Test name
Test status
Simulation time 1266433883 ps
CPU time 2.5 seconds
Started Jul 12 05:29:10 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 206880 kb
Host smart-43b8bfb6-d9f0-42da-99e8-116912632023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10640
32388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1064032388
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.275518337
Short name T544
Test name
Test status
Simulation time 5096354491 ps
CPU time 48 seconds
Started Jul 12 05:29:04 PM PDT 24
Finished Jul 12 05:29:54 PM PDT 24
Peak memory 206980 kb
Host smart-eae530a5-6ea0-43a8-a9e1-238ab918af03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27551
8337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.275518337
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.963274370
Short name T2580
Test name
Test status
Simulation time 34884411 ps
CPU time 0.63 seconds
Started Jul 12 05:29:26 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 206752 kb
Host smart-a455e001-2c0d-4abc-93b9-c06f23f03619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=963274370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.963274370
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1770687052
Short name T2242
Test name
Test status
Simulation time 3603317158 ps
CPU time 4.26 seconds
Started Jul 12 05:29:11 PM PDT 24
Finished Jul 12 05:29:17 PM PDT 24
Peak memory 206784 kb
Host smart-0b797638-0de5-454e-a6f0-a398b2286a65
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1770687052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.1770687052
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4051822297
Short name T1201
Test name
Test status
Simulation time 13444988924 ps
CPU time 13.57 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206880 kb
Host smart-d037d265-6d2e-4198-8775-93bcc4e43b27
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4051822297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4051822297
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.450167984
Short name T1205
Test name
Test status
Simulation time 23362703698 ps
CPU time 27.78 seconds
Started Jul 12 05:29:10 PM PDT 24
Finished Jul 12 05:29:39 PM PDT 24
Peak memory 207028 kb
Host smart-96cd943a-a68b-4eb5-a26d-be6a66d8f523
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=450167984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.450167984
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1524765246
Short name T2261
Test name
Test status
Simulation time 185608832 ps
CPU time 0.81 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:16 PM PDT 24
Peak memory 206812 kb
Host smart-e62bc4a9-f048-4059-8d46-b83385d79cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15247
65246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1524765246
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3099986765
Short name T2570
Test name
Test status
Simulation time 204429769 ps
CPU time 0.8 seconds
Started Jul 12 05:29:14 PM PDT 24
Finished Jul 12 05:29:17 PM PDT 24
Peak memory 206720 kb
Host smart-831a62ba-95eb-4f28-ac29-3cf88b2cd26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30999
86765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3099986765
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3659299589
Short name T675
Test name
Test status
Simulation time 389766903 ps
CPU time 1.23 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:16 PM PDT 24
Peak memory 206680 kb
Host smart-dd995767-361d-4a24-a9e7-4d6fdaf0a7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36592
99589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3659299589
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.707289141
Short name T2231
Test name
Test status
Simulation time 473568164 ps
CPU time 1.3 seconds
Started Jul 12 05:29:14 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206832 kb
Host smart-0ffde1d6-8fb3-4209-ba36-df02988b1d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70728
9141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.707289141
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.239605714
Short name T2098
Test name
Test status
Simulation time 20386507345 ps
CPU time 40.35 seconds
Started Jul 12 05:29:10 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 207028 kb
Host smart-7b475c98-f38e-4884-8149-cfeb4f43a769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23960
5714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.239605714
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1655397057
Short name T699
Test name
Test status
Simulation time 425435350 ps
CPU time 1.24 seconds
Started Jul 12 05:29:12 PM PDT 24
Finished Jul 12 05:29:15 PM PDT 24
Peak memory 206804 kb
Host smart-1a2f8ee8-088c-4b4a-8463-cda753b8c61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16553
97057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1655397057
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.701909261
Short name T887
Test name
Test status
Simulation time 149827142 ps
CPU time 0.79 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206832 kb
Host smart-08d17922-1ac4-45ab-a7ea-96ef1e29835b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70190
9261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.701909261
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1823393396
Short name T1814
Test name
Test status
Simulation time 65347679 ps
CPU time 0.7 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206808 kb
Host smart-7a97d3da-9bec-4da1-afb4-229ea3c97ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18233
93396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1823393396
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.462445424
Short name T615
Test name
Test status
Simulation time 843896126 ps
CPU time 2.26 seconds
Started Jul 12 05:29:09 PM PDT 24
Finished Jul 12 05:29:13 PM PDT 24
Peak memory 207028 kb
Host smart-538ea7b2-b2f1-459b-8b6b-5c4e51841a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46244
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.462445424
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1555209119
Short name T876
Test name
Test status
Simulation time 333740011 ps
CPU time 1.92 seconds
Started Jul 12 05:29:14 PM PDT 24
Finished Jul 12 05:29:19 PM PDT 24
Peak memory 207024 kb
Host smart-a8fa0e32-6709-4727-b8fb-cc1d8c263b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15552
09119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1555209119
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2894122119
Short name T1391
Test name
Test status
Simulation time 204036642 ps
CPU time 0.85 seconds
Started Jul 12 05:30:20 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 206796 kb
Host smart-e3c220c1-cb26-4198-a4a8-31068e0cfe97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28941
22119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2894122119
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1220340217
Short name T2197
Test name
Test status
Simulation time 146850458 ps
CPU time 0.77 seconds
Started Jul 12 05:29:19 PM PDT 24
Finished Jul 12 05:29:20 PM PDT 24
Peak memory 206800 kb
Host smart-18c42a6c-607b-4a9d-8262-b9810bf63427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12203
40217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1220340217
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3145766121
Short name T2302
Test name
Test status
Simulation time 209549350 ps
CPU time 0.95 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:17 PM PDT 24
Peak memory 206696 kb
Host smart-dd27804d-70f7-4b11-8864-3b0601f437a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
66121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3145766121
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.1724398118
Short name T981
Test name
Test status
Simulation time 6113809708 ps
CPU time 55.44 seconds
Started Jul 12 05:29:14 PM PDT 24
Finished Jul 12 05:30:12 PM PDT 24
Peak memory 207100 kb
Host smart-1d0011a6-9708-4d93-a7af-5352e8030c1f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1724398118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.1724398118
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.516642249
Short name T592
Test name
Test status
Simulation time 9952108324 ps
CPU time 35.08 seconds
Started Jul 12 05:29:09 PM PDT 24
Finished Jul 12 05:29:46 PM PDT 24
Peak memory 207028 kb
Host smart-216d75ad-3b09-4934-b06e-d8c6b07eeeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51664
2249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.516642249
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4225103426
Short name T2172
Test name
Test status
Simulation time 207126171 ps
CPU time 0.88 seconds
Started Jul 12 05:29:12 PM PDT 24
Finished Jul 12 05:29:15 PM PDT 24
Peak memory 206808 kb
Host smart-2279d965-110f-4cc7-bbe9-f91ddf44063e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42251
03426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4225103426
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.468081246
Short name T1837
Test name
Test status
Simulation time 23313525679 ps
CPU time 23.94 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:39 PM PDT 24
Peak memory 206868 kb
Host smart-c3ace01c-34c2-4c51-9f25-6be4090c8b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46808
1246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.468081246
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2841964063
Short name T1136
Test name
Test status
Simulation time 3315719297 ps
CPU time 4.24 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:19 PM PDT 24
Peak memory 206744 kb
Host smart-8ec73696-ff7c-4ed4-b179-a71a4d159d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28419
64063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2841964063
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3808009882
Short name T350
Test name
Test status
Simulation time 9110605404 ps
CPU time 242.9 seconds
Started Jul 12 05:29:20 PM PDT 24
Finished Jul 12 05:33:24 PM PDT 24
Peak memory 207124 kb
Host smart-966538fd-6504-447b-8739-a45c80b94d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38080
09882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3808009882
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3477830939
Short name T365
Test name
Test status
Simulation time 4687035409 ps
CPU time 34.76 seconds
Started Jul 12 05:29:11 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 206884 kb
Host smart-49cb2c1e-f453-4cd2-a29e-b340d2ccbfc0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3477830939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3477830939
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1296376672
Short name T2355
Test name
Test status
Simulation time 240760013 ps
CPU time 0.92 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206792 kb
Host smart-66bb08b9-71fd-43b1-8135-a9a33222c2b7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1296376672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1296376672
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1925256952
Short name T2222
Test name
Test status
Simulation time 194297637 ps
CPU time 0.9 seconds
Started Jul 12 05:29:19 PM PDT 24
Finished Jul 12 05:29:21 PM PDT 24
Peak memory 206828 kb
Host smart-b4c46402-e644-4043-8d11-2505164b7078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19252
56952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1925256952
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.4108625577
Short name T1167
Test name
Test status
Simulation time 6108355512 ps
CPU time 41.44 seconds
Started Jul 12 05:29:14 PM PDT 24
Finished Jul 12 05:29:58 PM PDT 24
Peak memory 207020 kb
Host smart-c6cffdf5-50c2-4715-914e-8cc911b7cf21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41086
25577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.4108625577
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.14070130
Short name T381
Test name
Test status
Simulation time 6263290891 ps
CPU time 44.52 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:30:02 PM PDT 24
Peak memory 207044 kb
Host smart-0383aa43-304f-4c24-8cfd-497f8493ee9c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=14070130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.14070130
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2653072999
Short name T581
Test name
Test status
Simulation time 157166101 ps
CPU time 0.78 seconds
Started Jul 12 05:29:11 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 206808 kb
Host smart-b8ae8549-3d8b-4d7d-afc2-644a09a88502
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2653072999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2653072999
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.524797996
Short name T2297
Test name
Test status
Simulation time 149597785 ps
CPU time 0.79 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:16 PM PDT 24
Peak memory 206772 kb
Host smart-28eea9db-f72e-4140-94e5-9ecddd3c30c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52479
7996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.524797996
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.860739744
Short name T774
Test name
Test status
Simulation time 169305465 ps
CPU time 0.81 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:15 PM PDT 24
Peak memory 206828 kb
Host smart-aa6f32b2-d52e-4c62-a8e3-df78c877a763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86073
9744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.860739744
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.888391350
Short name T2047
Test name
Test status
Simulation time 146506701 ps
CPU time 0.75 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206808 kb
Host smart-e5b01803-f39e-438f-aaf0-ed0de0ce6809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88839
1350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.888391350
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1589546484
Short name T1303
Test name
Test status
Simulation time 178058203 ps
CPU time 0.82 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:15 PM PDT 24
Peak memory 206824 kb
Host smart-da9022d6-ff46-4c8e-91dd-9a21543e9d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15895
46484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1589546484
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.102574333
Short name T760
Test name
Test status
Simulation time 160448553 ps
CPU time 0.82 seconds
Started Jul 12 05:29:11 PM PDT 24
Finished Jul 12 05:29:13 PM PDT 24
Peak memory 206800 kb
Host smart-526dafd1-3b09-40d8-b5ef-ea630da18f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10257
4333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.102574333
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1297989831
Short name T851
Test name
Test status
Simulation time 220376141 ps
CPU time 0.92 seconds
Started Jul 12 05:29:15 PM PDT 24
Finished Jul 12 05:29:18 PM PDT 24
Peak memory 206828 kb
Host smart-92d9dd00-3aa7-42fe-9cc0-9f513f07db25
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1297989831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1297989831
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1174895206
Short name T2561
Test name
Test status
Simulation time 178075062 ps
CPU time 0.82 seconds
Started Jul 12 05:29:10 PM PDT 24
Finished Jul 12 05:29:12 PM PDT 24
Peak memory 206812 kb
Host smart-a556eabc-1a8b-4e22-bd94-bc23fddc3c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11748
95206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1174895206
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3971286719
Short name T1653
Test name
Test status
Simulation time 53211159 ps
CPU time 0.67 seconds
Started Jul 12 05:29:12 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 206756 kb
Host smart-e179feea-4955-4214-8892-f71768aad9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
86719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3971286719
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2829705915
Short name T2381
Test name
Test status
Simulation time 22244426933 ps
CPU time 50.66 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:30:15 PM PDT 24
Peak memory 207100 kb
Host smart-35c8ca7a-bfc4-4fa4-8f9c-57f761f2e883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28297
05915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2829705915
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1297434668
Short name T1348
Test name
Test status
Simulation time 181444040 ps
CPU time 0.84 seconds
Started Jul 12 05:29:18 PM PDT 24
Finished Jul 12 05:29:20 PM PDT 24
Peak memory 206828 kb
Host smart-702c653e-4e17-49e6-8e59-4477b77b0e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12974
34668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1297434668
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2820789130
Short name T1938
Test name
Test status
Simulation time 262287585 ps
CPU time 1.03 seconds
Started Jul 12 05:29:12 PM PDT 24
Finished Jul 12 05:29:14 PM PDT 24
Peak memory 206792 kb
Host smart-0ca34742-e3a8-43fe-891e-949a6967c87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
89130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2820789130
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3382315527
Short name T2105
Test name
Test status
Simulation time 177042979 ps
CPU time 0.8 seconds
Started Jul 12 05:29:13 PM PDT 24
Finished Jul 12 05:29:15 PM PDT 24
Peak memory 206820 kb
Host smart-bb057d1a-0c06-4aef-9a78-e3e339686a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33823
15527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3382315527
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.987709715
Short name T2514
Test name
Test status
Simulation time 158152389 ps
CPU time 0.97 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:26 PM PDT 24
Peak memory 206792 kb
Host smart-b94840a3-581f-47f7-9a2c-c60af8c4f7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98770
9715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.987709715
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2969079742
Short name T2281
Test name
Test status
Simulation time 142381882 ps
CPU time 0.77 seconds
Started Jul 12 05:29:27 PM PDT 24
Finished Jul 12 05:29:31 PM PDT 24
Peak memory 206828 kb
Host smart-5412cbfa-6743-4606-91a8-78d25c80bccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29690
79742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2969079742
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2831770731
Short name T2249
Test name
Test status
Simulation time 147614885 ps
CPU time 0.79 seconds
Started Jul 12 05:29:27 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206812 kb
Host smart-f235bd63-90bb-43eb-86df-517c0a6cff0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28317
70731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2831770731
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1935555400
Short name T2082
Test name
Test status
Simulation time 152011347 ps
CPU time 0.79 seconds
Started Jul 12 05:29:33 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 206820 kb
Host smart-043794c4-4276-429a-8023-699ad2947e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19355
55400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1935555400
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1217620366
Short name T2294
Test name
Test status
Simulation time 235294054 ps
CPU time 0.92 seconds
Started Jul 12 05:29:21 PM PDT 24
Finished Jul 12 05:29:23 PM PDT 24
Peak memory 206812 kb
Host smart-a27b9ac2-7150-4530-9618-89e3a2065558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12176
20366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1217620366
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3823891262
Short name T1866
Test name
Test status
Simulation time 3398773135 ps
CPU time 24.23 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:49 PM PDT 24
Peak memory 207056 kb
Host smart-e888d530-6c75-4f60-8250-27fb2ff6905d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3823891262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3823891262
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.386118937
Short name T838
Test name
Test status
Simulation time 186877212 ps
CPU time 0.84 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:29:24 PM PDT 24
Peak memory 206804 kb
Host smart-b38134c1-7a16-4c60-ab5b-e1e6afb05412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38611
8937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.386118937
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.189550582
Short name T322
Test name
Test status
Simulation time 148937361 ps
CPU time 0.76 seconds
Started Jul 12 05:29:21 PM PDT 24
Finished Jul 12 05:29:23 PM PDT 24
Peak memory 206804 kb
Host smart-1d7bf59d-1cd1-4a16-87a5-e2ffdac84ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18955
0582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.189550582
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3350662582
Short name T826
Test name
Test status
Simulation time 560938443 ps
CPU time 1.48 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:26 PM PDT 24
Peak memory 206812 kb
Host smart-b069cc09-6ff1-4e97-b834-b162bf9e462c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33506
62582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3350662582
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1607392068
Short name T571
Test name
Test status
Simulation time 4337655904 ps
CPU time 117.12 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:31:21 PM PDT 24
Peak memory 207000 kb
Host smart-a1c91bd2-ace9-4814-aa2e-52ef67792428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16073
92068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1607392068
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.885964188
Short name T1342
Test name
Test status
Simulation time 73866071 ps
CPU time 0.73 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:29:25 PM PDT 24
Peak memory 206844 kb
Host smart-a019d325-e23a-48ff-8f79-5fe13b16a3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=885964188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.885964188
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.419390788
Short name T2590
Test name
Test status
Simulation time 4248437992 ps
CPU time 4.83 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206836 kb
Host smart-9a92e8fc-7d36-4a81-b9d6-00345069df8d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=419390788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.419390788
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2947917779
Short name T496
Test name
Test status
Simulation time 13457061385 ps
CPU time 12.78 seconds
Started Jul 12 05:29:21 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 207032 kb
Host smart-7f27add9-62ff-4adc-a049-e59db8b445b1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2947917779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2947917779
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2599100837
Short name T1375
Test name
Test status
Simulation time 23472776848 ps
CPU time 21.97 seconds
Started Jul 12 05:29:29 PM PDT 24
Finished Jul 12 05:29:53 PM PDT 24
Peak memory 207012 kb
Host smart-f928f855-0e52-4f21-8ea2-4d4b3cdedcce
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2599100837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2599100837
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.393648181
Short name T2373
Test name
Test status
Simulation time 158304270 ps
CPU time 0.79 seconds
Started Jul 12 05:29:25 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 206808 kb
Host smart-2812029f-5fc0-43ce-96a6-618ad9e4e1b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39364
8181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.393648181
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.628850537
Short name T1729
Test name
Test status
Simulation time 142107750 ps
CPU time 0.77 seconds
Started Jul 12 05:29:26 PM PDT 24
Finished Jul 12 05:29:29 PM PDT 24
Peak memory 206796 kb
Host smart-9bf38add-3da0-4204-bf2f-d2c0b9bab182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62885
0537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.628850537
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.755462
Short name T960
Test name
Test status
Simulation time 187425247 ps
CPU time 0.83 seconds
Started Jul 12 05:29:32 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 206816 kb
Host smart-f42dca47-20b7-4603-abd6-c09ad8c1a9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75546
2 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.755462
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.122856126
Short name T665
Test name
Test status
Simulation time 1326709870 ps
CPU time 3.08 seconds
Started Jul 12 05:29:21 PM PDT 24
Finished Jul 12 05:29:24 PM PDT 24
Peak memory 206964 kb
Host smart-8110eb4b-3945-4179-b066-f691aa3594a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12285
6126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.122856126
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2607693544
Short name T1112
Test name
Test status
Simulation time 21635311369 ps
CPU time 41.57 seconds
Started Jul 12 05:29:24 PM PDT 24
Finished Jul 12 05:30:08 PM PDT 24
Peak memory 206956 kb
Host smart-84854729-6ccd-4ba9-b5d9-8e90ad04d761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
93544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2607693544
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.4072873628
Short name T78
Test name
Test status
Simulation time 341655018 ps
CPU time 1.12 seconds
Started Jul 12 05:29:28 PM PDT 24
Finished Jul 12 05:29:31 PM PDT 24
Peak memory 206836 kb
Host smart-07bdb41c-3ed3-4608-a30f-ce4ce3e1912c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40728
73628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.4072873628
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.48699850
Short name T336
Test name
Test status
Simulation time 138924360 ps
CPU time 0.75 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:29:25 PM PDT 24
Peak memory 206720 kb
Host smart-9ae1bf76-ccd3-4854-ab23-fa4fdc026165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48699
850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.48699850
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.4219696305
Short name T2360
Test name
Test status
Simulation time 32766774 ps
CPU time 0.67 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:26 PM PDT 24
Peak memory 206692 kb
Host smart-554021e7-c359-4a4e-a1f7-33c9efd22aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42196
96305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.4219696305
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1966085714
Short name T2029
Test name
Test status
Simulation time 891388341 ps
CPU time 2.12 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 207020 kb
Host smart-29f39089-48bf-44d1-ad56-1a7e6219bd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19660
85714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1966085714
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.4203428767
Short name T952
Test name
Test status
Simulation time 387805416 ps
CPU time 2.39 seconds
Started Jul 12 05:29:25 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206772 kb
Host smart-7fec547d-e2d2-4aa7-8f1e-5f1aefded6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
28767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4203428767
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2833733469
Short name T845
Test name
Test status
Simulation time 266197724 ps
CPU time 0.94 seconds
Started Jul 12 05:29:25 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 206680 kb
Host smart-0c29c103-91ff-4333-a9e3-b2f7063ed1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28337
33469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2833733469
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2079213814
Short name T1267
Test name
Test status
Simulation time 184620834 ps
CPU time 0.85 seconds
Started Jul 12 05:29:24 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 206976 kb
Host smart-c273148a-0c43-44b1-86e4-bb07e993ce8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20792
13814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2079213814
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1720469323
Short name T603
Test name
Test status
Simulation time 262516039 ps
CPU time 0.95 seconds
Started Jul 12 05:29:29 PM PDT 24
Finished Jul 12 05:29:32 PM PDT 24
Peak memory 206796 kb
Host smart-2e76a977-0a27-46a9-8be7-1a3494c6b0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17204
69323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1720469323
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.992708235
Short name T235
Test name
Test status
Simulation time 6925116746 ps
CPU time 67.32 seconds
Started Jul 12 05:29:24 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 207020 kb
Host smart-80bfbfbc-0ba2-4365-a018-a6ac51e1365e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=992708235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.992708235
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.1281738643
Short name T956
Test name
Test status
Simulation time 4495727011 ps
CPU time 15.75 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:29:40 PM PDT 24
Peak memory 206984 kb
Host smart-209a689e-10e5-4861-9301-3ad6f626781c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12817
38643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.1281738643
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1834640684
Short name T518
Test name
Test status
Simulation time 226660109 ps
CPU time 0.88 seconds
Started Jul 12 05:29:26 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206592 kb
Host smart-bf039db3-7cc2-46b1-b674-58fd563a6499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18346
40684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1834640684
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.2911029351
Short name T2009
Test name
Test status
Simulation time 23335319177 ps
CPU time 28.3 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 206864 kb
Host smart-7f7afa07-784d-4901-955f-c322204c5db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110
29351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.2911029351
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2275474200
Short name T1297
Test name
Test status
Simulation time 3304092021 ps
CPU time 4.14 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206760 kb
Host smart-456092ef-0203-438d-bab8-a8e0c92d725b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22754
74200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2275474200
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2141986952
Short name T743
Test name
Test status
Simulation time 9467940222 ps
CPU time 275.3 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:34:00 PM PDT 24
Peak memory 207084 kb
Host smart-6850bf19-01ce-4507-962a-85b61b2a4545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21419
86952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2141986952
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1824745597
Short name T1523
Test name
Test status
Simulation time 4346075775 ps
CPU time 116.46 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:31:21 PM PDT 24
Peak memory 207008 kb
Host smart-cd29383c-dbcd-4e1d-af9b-4c9861bac466
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1824745597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1824745597
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3778843820
Short name T2398
Test name
Test status
Simulation time 258987875 ps
CPU time 0.94 seconds
Started Jul 12 05:29:21 PM PDT 24
Finished Jul 12 05:29:22 PM PDT 24
Peak memory 206812 kb
Host smart-5afaddbb-150d-4e53-b031-9fbe5764b119
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3778843820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3778843820
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1806034402
Short name T1494
Test name
Test status
Simulation time 237093395 ps
CPU time 0.95 seconds
Started Jul 12 05:29:25 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 206828 kb
Host smart-48ba0283-5891-4738-b17e-993e95dff200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18060
34402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1806034402
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1708237188
Short name T1742
Test name
Test status
Simulation time 5140099041 ps
CPU time 35.32 seconds
Started Jul 12 05:29:26 PM PDT 24
Finished Jul 12 05:30:04 PM PDT 24
Peak memory 206836 kb
Host smart-1d2fa38f-ea4d-4eea-a35c-6f74e20da95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17082
37188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1708237188
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.816764333
Short name T730
Test name
Test status
Simulation time 7429696006 ps
CPU time 54.53 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:30:17 PM PDT 24
Peak memory 207008 kb
Host smart-52583021-e92a-4003-9e9b-4e99c0731340
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=816764333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.816764333
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1141186241
Short name T349
Test name
Test status
Simulation time 212382876 ps
CPU time 0.86 seconds
Started Jul 12 05:29:24 PM PDT 24
Finished Jul 12 05:29:27 PM PDT 24
Peak memory 206796 kb
Host smart-a030cf92-d898-4e34-8c9a-14f3f7227058
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1141186241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1141186241
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.550685294
Short name T2730
Test name
Test status
Simulation time 161618583 ps
CPU time 0.77 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:26 PM PDT 24
Peak memory 206808 kb
Host smart-58717a4b-2fca-46a5-8447-58c8ecdaab0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55068
5294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.550685294
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1592779812
Short name T1973
Test name
Test status
Simulation time 198157531 ps
CPU time 0.84 seconds
Started Jul 12 05:29:22 PM PDT 24
Finished Jul 12 05:29:25 PM PDT 24
Peak memory 206816 kb
Host smart-3d584c9d-91f0-4132-af45-fd2fe58441f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15927
79812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1592779812
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3769580025
Short name T1568
Test name
Test status
Simulation time 210124813 ps
CPU time 0.93 seconds
Started Jul 12 05:29:24 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 206716 kb
Host smart-6d9569c4-c244-4bbb-9620-81d741b4a419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37695
80025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3769580025
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2074591999
Short name T604
Test name
Test status
Simulation time 162898436 ps
CPU time 0.84 seconds
Started Jul 12 05:29:41 PM PDT 24
Finished Jul 12 05:29:43 PM PDT 24
Peak memory 206808 kb
Host smart-6b9469f5-8d82-4c16-9186-f32942063bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20745
91999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2074591999
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.325114473
Short name T882
Test name
Test status
Simulation time 182427927 ps
CPU time 0.92 seconds
Started Jul 12 05:29:24 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 206832 kb
Host smart-39708486-3513-40b0-8cb1-8e28f3b9d442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32511
4473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.325114473
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3308109481
Short name T157
Test name
Test status
Simulation time 186003316 ps
CPU time 0.84 seconds
Started Jul 12 05:29:33 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 206816 kb
Host smart-985e144f-6039-4d3f-9aa5-bc2041e3e7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33081
09481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3308109481
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3789036443
Short name T1573
Test name
Test status
Simulation time 177648581 ps
CPU time 0.84 seconds
Started Jul 12 05:29:31 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 206812 kb
Host smart-334153e1-c9e1-4b3e-b0de-a23387d89eca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3789036443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3789036443
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.903242628
Short name T2534
Test name
Test status
Simulation time 157716211 ps
CPU time 0.78 seconds
Started Jul 12 05:29:25 PM PDT 24
Finished Jul 12 05:29:28 PM PDT 24
Peak memory 206824 kb
Host smart-348c58ad-7ce7-4e02-a047-604d26ae1c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90324
2628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.903242628
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2720646043
Short name T1895
Test name
Test status
Simulation time 101874783 ps
CPU time 0.72 seconds
Started Jul 12 05:29:26 PM PDT 24
Finished Jul 12 05:29:29 PM PDT 24
Peak memory 206696 kb
Host smart-225e3014-21d3-4cf3-8507-72be5008352f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27206
46043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2720646043
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2547885019
Short name T2540
Test name
Test status
Simulation time 13914956363 ps
CPU time 30.39 seconds
Started Jul 12 05:29:25 PM PDT 24
Finished Jul 12 05:29:58 PM PDT 24
Peak memory 215304 kb
Host smart-54973c31-b011-45d2-9b40-3aa6733c74a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25478
85019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2547885019
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.4105370364
Short name T1631
Test name
Test status
Simulation time 175210256 ps
CPU time 0.86 seconds
Started Jul 12 05:29:25 PM PDT 24
Finished Jul 12 05:29:29 PM PDT 24
Peak memory 206828 kb
Host smart-f5e98117-9ecb-4677-9964-01c6cd285f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41053
70364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.4105370364
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2515464923
Short name T1486
Test name
Test status
Simulation time 172457701 ps
CPU time 0.82 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:26 PM PDT 24
Peak memory 206816 kb
Host smart-3de6bb93-10dc-4872-82f8-7e485c5d441e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25154
64923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2515464923
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2674326902
Short name T2500
Test name
Test status
Simulation time 205550041 ps
CPU time 0.87 seconds
Started Jul 12 05:29:38 PM PDT 24
Finished Jul 12 05:29:40 PM PDT 24
Peak memory 206760 kb
Host smart-468c7c08-270c-4f16-b03c-890ce8d31171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26743
26902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2674326902
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3844800507
Short name T2282
Test name
Test status
Simulation time 212171898 ps
CPU time 0.83 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:29:39 PM PDT 24
Peak memory 206756 kb
Host smart-b66f12d7-4989-4ae9-8748-475062cd95f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38448
00507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3844800507
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1234657002
Short name T1192
Test name
Test status
Simulation time 133511335 ps
CPU time 0.76 seconds
Started Jul 12 05:29:30 PM PDT 24
Finished Jul 12 05:29:33 PM PDT 24
Peak memory 206800 kb
Host smart-c88a4e9b-0bfb-4185-a247-83ff312d7644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12346
57002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1234657002
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2401790691
Short name T583
Test name
Test status
Simulation time 232312520 ps
CPU time 0.83 seconds
Started Jul 12 05:29:27 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206692 kb
Host smart-cfa114bd-8861-436a-bbc7-a452f1fc7e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24017
90691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2401790691
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3063696034
Short name T734
Test name
Test status
Simulation time 164946051 ps
CPU time 0.78 seconds
Started Jul 12 05:29:27 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206700 kb
Host smart-65624f46-4768-48dc-98bd-4463d48050ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30636
96034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3063696034
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.163556741
Short name T1612
Test name
Test status
Simulation time 258378880 ps
CPU time 0.96 seconds
Started Jul 12 05:29:26 PM PDT 24
Finished Jul 12 05:29:29 PM PDT 24
Peak memory 206676 kb
Host smart-27e099f6-3479-4412-8f0c-bf8d3a030ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16355
6741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.163556741
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1133408783
Short name T517
Test name
Test status
Simulation time 4664991120 ps
CPU time 32.98 seconds
Started Jul 12 05:29:31 PM PDT 24
Finished Jul 12 05:30:05 PM PDT 24
Peak memory 207072 kb
Host smart-534c5a60-5609-47b5-b898-e7572f60ee1d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1133408783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1133408783
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3830668918
Short name T2583
Test name
Test status
Simulation time 158192770 ps
CPU time 0.8 seconds
Started Jul 12 05:29:28 PM PDT 24
Finished Jul 12 05:29:31 PM PDT 24
Peak memory 206836 kb
Host smart-6152e875-bc99-448b-a421-c56632dd11d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
68918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3830668918
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1089826799
Short name T1330
Test name
Test status
Simulation time 230168154 ps
CPU time 0.83 seconds
Started Jul 12 05:29:24 PM PDT 24
Finished Jul 12 05:29:27 PM PDT 24
Peak memory 206808 kb
Host smart-6421b340-70d5-4d7e-b787-7b48270a5f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10898
26799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1089826799
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.3721677156
Short name T1622
Test name
Test status
Simulation time 640148481 ps
CPU time 1.63 seconds
Started Jul 12 05:29:25 PM PDT 24
Finished Jul 12 05:29:29 PM PDT 24
Peak memory 206772 kb
Host smart-b23eeaed-48cc-4aa8-b096-d1ae9778a836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37216
77156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3721677156
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.172241756
Short name T931
Test name
Test status
Simulation time 5451851431 ps
CPU time 48.87 seconds
Started Jul 12 05:29:31 PM PDT 24
Finished Jul 12 05:30:22 PM PDT 24
Peak memory 206904 kb
Host smart-f71b672e-e041-4a0a-bb57-ab320c189b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
1756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.172241756
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.169210290
Short name T2487
Test name
Test status
Simulation time 40716544 ps
CPU time 0.63 seconds
Started Jul 12 05:26:39 PM PDT 24
Finished Jul 12 05:26:43 PM PDT 24
Peak memory 206852 kb
Host smart-052df4ff-5473-4567-998e-5c1529aa9ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=169210290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.169210290
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3349042383
Short name T1826
Test name
Test status
Simulation time 3846964754 ps
CPU time 4.62 seconds
Started Jul 12 05:26:22 PM PDT 24
Finished Jul 12 05:26:28 PM PDT 24
Peak memory 207000 kb
Host smart-73e30b4a-b357-49cb-a74c-f7ae6fcfdd2f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3349042383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.3349042383
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2373683832
Short name T1833
Test name
Test status
Simulation time 13329921013 ps
CPU time 14.22 seconds
Started Jul 12 05:26:22 PM PDT 24
Finished Jul 12 05:26:38 PM PDT 24
Peak memory 207132 kb
Host smart-2109e6e6-849e-45f4-ae9b-8ff45a77362a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2373683832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2373683832
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.518684475
Short name T2179
Test name
Test status
Simulation time 23335484267 ps
CPU time 22.09 seconds
Started Jul 12 05:26:25 PM PDT 24
Finished Jul 12 05:26:49 PM PDT 24
Peak memory 206900 kb
Host smart-28b8a221-9ea4-4811-962a-3efda86256a8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=518684475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.518684475
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.4033466942
Short name T1609
Test name
Test status
Simulation time 153321677 ps
CPU time 0.8 seconds
Started Jul 12 05:26:22 PM PDT 24
Finished Jul 12 05:26:25 PM PDT 24
Peak memory 206824 kb
Host smart-bc2a5d5a-dffb-4bbb-ae5a-3ee9ba5120c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
66942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.4033466942
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3547117622
Short name T863
Test name
Test status
Simulation time 149061028 ps
CPU time 0.77 seconds
Started Jul 12 05:26:23 PM PDT 24
Finished Jul 12 05:26:25 PM PDT 24
Peak memory 207040 kb
Host smart-d232712c-da21-4313-a7a1-b30dcf4e4ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35471
17622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3547117622
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.368925776
Short name T278
Test name
Test status
Simulation time 216788367 ps
CPU time 0.99 seconds
Started Jul 12 05:26:21 PM PDT 24
Finished Jul 12 05:26:23 PM PDT 24
Peak memory 206696 kb
Host smart-67448c6b-9945-4506-bb17-abf654b87945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36892
5776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.368925776
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.73602140
Short name T2168
Test name
Test status
Simulation time 304386442 ps
CPU time 1.05 seconds
Started Jul 12 05:26:31 PM PDT 24
Finished Jul 12 05:26:33 PM PDT 24
Peak memory 206816 kb
Host smart-98c20595-d4aa-475b-b4fe-f131820e9fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73602
140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.73602140
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1651789236
Short name T160
Test name
Test status
Simulation time 19787949375 ps
CPU time 35.65 seconds
Started Jul 12 05:26:21 PM PDT 24
Finished Jul 12 05:26:58 PM PDT 24
Peak memory 207012 kb
Host smart-de632e52-b752-4210-8224-317d6860b963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
89236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1651789236
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1898067423
Short name T1683
Test name
Test status
Simulation time 338962015 ps
CPU time 1.12 seconds
Started Jul 12 05:26:23 PM PDT 24
Finished Jul 12 05:26:26 PM PDT 24
Peak memory 206832 kb
Host smart-100c8664-6485-4a59-a50c-8b7efab040a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18980
67423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1898067423
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.390977694
Short name T382
Test name
Test status
Simulation time 148144270 ps
CPU time 0.74 seconds
Started Jul 12 05:26:24 PM PDT 24
Finished Jul 12 05:26:26 PM PDT 24
Peak memory 206812 kb
Host smart-6719993c-8d14-4fe2-8679-3085784b2c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39097
7694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.390977694
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2058862539
Short name T1540
Test name
Test status
Simulation time 54751067 ps
CPU time 0.67 seconds
Started Jul 12 05:26:23 PM PDT 24
Finished Jul 12 05:26:26 PM PDT 24
Peak memory 206748 kb
Host smart-5397257e-262b-495d-846c-2aed47e0eea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20588
62539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2058862539
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1414271742
Short name T2740
Test name
Test status
Simulation time 1010760190 ps
CPU time 2.36 seconds
Started Jul 12 05:26:24 PM PDT 24
Finished Jul 12 05:26:28 PM PDT 24
Peak memory 207040 kb
Host smart-765031d0-dcad-4325-9ea5-2069ccb97337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14142
71742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1414271742
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.968863446
Short name T2319
Test name
Test status
Simulation time 149399360 ps
CPU time 1.1 seconds
Started Jul 12 05:26:32 PM PDT 24
Finished Jul 12 05:26:34 PM PDT 24
Peak memory 207012 kb
Host smart-9c9bbb35-848a-4631-a313-acbd30a44576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96886
3446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.968863446
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3727490535
Short name T2366
Test name
Test status
Simulation time 105186809497 ps
CPU time 143.47 seconds
Started Jul 12 05:26:31 PM PDT 24
Finished Jul 12 05:28:56 PM PDT 24
Peak memory 207004 kb
Host smart-c7d5b301-cb2f-4695-b862-9ce27fefccbf
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3727490535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3727490535
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1932641529
Short name T2480
Test name
Test status
Simulation time 108134516575 ps
CPU time 137.95 seconds
Started Jul 12 05:26:21 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 207064 kb
Host smart-bdbb1317-b816-4952-8aaa-911ae1f4d95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932641529 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1932641529
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.196466676
Short name T610
Test name
Test status
Simulation time 100152531677 ps
CPU time 149.71 seconds
Started Jul 12 05:26:24 PM PDT 24
Finished Jul 12 05:28:56 PM PDT 24
Peak memory 206988 kb
Host smart-183cdf1f-d4ce-4015-9614-bcf80ff4385c
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=196466676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.196466676
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.4270964064
Short name T2502
Test name
Test status
Simulation time 94030405852 ps
CPU time 123.79 seconds
Started Jul 12 05:26:21 PM PDT 24
Finished Jul 12 05:28:26 PM PDT 24
Peak memory 207016 kb
Host smart-1b0bace2-ed25-4b1e-a99b-4e2ed7b40ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270964064 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.4270964064
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.2416232426
Short name T1800
Test name
Test status
Simulation time 83144451781 ps
CPU time 103.1 seconds
Started Jul 12 05:26:32 PM PDT 24
Finished Jul 12 05:28:16 PM PDT 24
Peak memory 207088 kb
Host smart-9069bca2-5d13-4275-b711-30ea3c43fbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24162
32426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.2416232426
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1146367694
Short name T1792
Test name
Test status
Simulation time 237626744 ps
CPU time 0.94 seconds
Started Jul 12 05:26:22 PM PDT 24
Finished Jul 12 05:26:25 PM PDT 24
Peak memory 206632 kb
Host smart-ca8ba3b0-ba1b-4eb3-ba2f-334ee20aeb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
67694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1146367694
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.112639090
Short name T1117
Test name
Test status
Simulation time 149149051 ps
CPU time 0.76 seconds
Started Jul 12 05:26:32 PM PDT 24
Finished Jul 12 05:26:34 PM PDT 24
Peak memory 206812 kb
Host smart-8901091b-ac80-42b2-b30c-aa35fe1c68b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11263
9090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.112639090
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2581509195
Short name T1520
Test name
Test status
Simulation time 193238960 ps
CPU time 0.84 seconds
Started Jul 12 05:26:23 PM PDT 24
Finished Jul 12 05:26:25 PM PDT 24
Peak memory 206832 kb
Host smart-7ef51139-fd89-424a-835e-4c2d51859ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25815
09195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2581509195
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.1269506537
Short name T2369
Test name
Test status
Simulation time 3793646748 ps
CPU time 14.01 seconds
Started Jul 12 05:26:24 PM PDT 24
Finished Jul 12 05:26:40 PM PDT 24
Peak memory 207068 kb
Host smart-19366e2b-4747-496d-ab5c-bade0ab33357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12695
06537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.1269506537
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1391150081
Short name T312
Test name
Test status
Simulation time 204987030 ps
CPU time 0.82 seconds
Started Jul 12 05:26:23 PM PDT 24
Finished Jul 12 05:26:25 PM PDT 24
Peak memory 206976 kb
Host smart-981b5390-33d6-4df1-9146-3fb7ff3106a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911
50081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1391150081
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.638235152
Short name T2070
Test name
Test status
Simulation time 23309940370 ps
CPU time 20.67 seconds
Started Jul 12 05:26:29 PM PDT 24
Finished Jul 12 05:26:50 PM PDT 24
Peak memory 206700 kb
Host smart-b864ad98-c55b-4e7d-bb45-76b9f08f7ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63823
5152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.638235152
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2166668969
Short name T2749
Test name
Test status
Simulation time 3321987614 ps
CPU time 3.54 seconds
Started Jul 12 05:26:29 PM PDT 24
Finished Jul 12 05:26:34 PM PDT 24
Peak memory 206884 kb
Host smart-bbef76b2-1588-46f1-98cc-28fa032c1452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21666
68969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2166668969
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2902460420
Short name T1209
Test name
Test status
Simulation time 7662792332 ps
CPU time 75.71 seconds
Started Jul 12 05:26:31 PM PDT 24
Finished Jul 12 05:27:48 PM PDT 24
Peak memory 207120 kb
Host smart-0d9b1aea-33a4-4120-8291-8ca6c679d17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29024
60420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2902460420
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.683329370
Short name T971
Test name
Test status
Simulation time 6969591630 ps
CPU time 187.63 seconds
Started Jul 12 05:26:28 PM PDT 24
Finished Jul 12 05:29:37 PM PDT 24
Peak memory 207016 kb
Host smart-1eff4eea-5f4d-4879-9a67-76a93bd4ef6b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=683329370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.683329370
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3772845733
Short name T2414
Test name
Test status
Simulation time 247363813 ps
CPU time 0.92 seconds
Started Jul 12 05:26:28 PM PDT 24
Finished Jul 12 05:26:30 PM PDT 24
Peak memory 206816 kb
Host smart-056e8118-dde4-4723-b8f1-9da945147024
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3772845733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3772845733
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3634585614
Short name T2716
Test name
Test status
Simulation time 190419396 ps
CPU time 0.86 seconds
Started Jul 12 05:26:38 PM PDT 24
Finished Jul 12 05:26:41 PM PDT 24
Peak memory 206812 kb
Host smart-03bc2102-585b-4e27-ac19-fd81e1d44f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36345
85614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3634585614
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.709028367
Short name T862
Test name
Test status
Simulation time 5197351374 ps
CPU time 147.98 seconds
Started Jul 12 05:26:30 PM PDT 24
Finished Jul 12 05:28:59 PM PDT 24
Peak memory 206908 kb
Host smart-0cfa84eb-0046-43ba-bd04-c5c92b5bf688
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=709028367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.709028367
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1311967521
Short name T1222
Test name
Test status
Simulation time 159761733 ps
CPU time 0.79 seconds
Started Jul 12 05:26:27 PM PDT 24
Finished Jul 12 05:26:28 PM PDT 24
Peak memory 206820 kb
Host smart-c6027df9-23fb-4a8e-8f19-7e5ae70689ff
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1311967521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1311967521
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2646204361
Short name T2408
Test name
Test status
Simulation time 156880982 ps
CPU time 0.81 seconds
Started Jul 12 05:26:34 PM PDT 24
Finished Jul 12 05:26:36 PM PDT 24
Peak memory 206824 kb
Host smart-ceabd8ce-4400-494e-a9c2-5974cdae4ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26462
04361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2646204361
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2059643461
Short name T2166
Test name
Test status
Simulation time 170066242 ps
CPU time 0.83 seconds
Started Jul 12 05:26:29 PM PDT 24
Finished Jul 12 05:26:31 PM PDT 24
Peak memory 206808 kb
Host smart-05e6c8ba-2161-4714-81a5-17f56419d7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20596
43461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2059643461
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3112007504
Short name T1207
Test name
Test status
Simulation time 163838572 ps
CPU time 0.81 seconds
Started Jul 12 05:26:30 PM PDT 24
Finished Jul 12 05:26:32 PM PDT 24
Peak memory 206812 kb
Host smart-36090bab-43eb-4259-85d4-a335ddcb2d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31120
07504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3112007504
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1667936895
Short name T2492
Test name
Test status
Simulation time 171926254 ps
CPU time 0.76 seconds
Started Jul 12 05:26:26 PM PDT 24
Finished Jul 12 05:26:28 PM PDT 24
Peak memory 206812 kb
Host smart-c24320d9-3792-4266-ba7e-d8ac04969a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16679
36895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1667936895
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2628956086
Short name T171
Test name
Test status
Simulation time 152179640 ps
CPU time 0.79 seconds
Started Jul 12 05:26:29 PM PDT 24
Finished Jul 12 05:26:32 PM PDT 24
Peak memory 206812 kb
Host smart-cb2d152c-ed81-4ec3-9180-2fc3fbf986c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26289
56086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2628956086
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3218591858
Short name T2040
Test name
Test status
Simulation time 224740057 ps
CPU time 0.9 seconds
Started Jul 12 05:26:27 PM PDT 24
Finished Jul 12 05:26:29 PM PDT 24
Peak memory 206820 kb
Host smart-2e1aa845-9d0b-4ab9-8d96-e52244620ef6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3218591858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3218591858
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.3730862683
Short name T369
Test name
Test status
Simulation time 252882814 ps
CPU time 1.09 seconds
Started Jul 12 05:26:33 PM PDT 24
Finished Jul 12 05:26:34 PM PDT 24
Peak memory 207040 kb
Host smart-5e293cf1-81d6-4c04-a886-996ccb6148f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37308
62683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.3730862683
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.910696582
Short name T1765
Test name
Test status
Simulation time 149343358 ps
CPU time 0.75 seconds
Started Jul 12 05:26:28 PM PDT 24
Finished Jul 12 05:26:30 PM PDT 24
Peak memory 206772 kb
Host smart-998744ac-04ba-469a-a3df-90b920f19c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91069
6582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.910696582
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.292871696
Short name T709
Test name
Test status
Simulation time 44293916 ps
CPU time 0.68 seconds
Started Jul 12 05:26:31 PM PDT 24
Finished Jul 12 05:26:33 PM PDT 24
Peak memory 207036 kb
Host smart-71205594-a9f1-46ed-9fa7-649708f11e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29287
1696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.292871696
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2119512065
Short name T1511
Test name
Test status
Simulation time 12828758546 ps
CPU time 29.71 seconds
Started Jul 12 05:26:31 PM PDT 24
Finished Jul 12 05:27:02 PM PDT 24
Peak memory 206972 kb
Host smart-2daef21c-e282-408e-87cc-8f2a479bca9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21195
12065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2119512065
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1470859148
Short name T704
Test name
Test status
Simulation time 164968690 ps
CPU time 0.82 seconds
Started Jul 12 05:26:28 PM PDT 24
Finished Jul 12 05:26:30 PM PDT 24
Peak memory 206704 kb
Host smart-d78a01eb-30fe-4ed6-a726-bb23f4e270d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708
59148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1470859148
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2215642378
Short name T2426
Test name
Test status
Simulation time 187731946 ps
CPU time 0.9 seconds
Started Jul 12 05:26:30 PM PDT 24
Finished Jul 12 05:26:32 PM PDT 24
Peak memory 206820 kb
Host smart-f0ff4124-b092-454d-8498-8385601efd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22156
42378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2215642378
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1914781156
Short name T1882
Test name
Test status
Simulation time 9383308293 ps
CPU time 85.79 seconds
Started Jul 12 05:26:28 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 207120 kb
Host smart-2afac1d1-5cd3-40f3-bcd8-42e04706d542
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1914781156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1914781156
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3241230103
Short name T944
Test name
Test status
Simulation time 8747283965 ps
CPU time 152.89 seconds
Started Jul 12 05:26:31 PM PDT 24
Finished Jul 12 05:29:05 PM PDT 24
Peak memory 207076 kb
Host smart-0940a364-04c9-4763-9b69-840ecdbf951f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3241230103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3241230103
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.1336699320
Short name T2636
Test name
Test status
Simulation time 20822838296 ps
CPU time 122.12 seconds
Started Jul 12 05:26:34 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 207092 kb
Host smart-d526a177-ffca-4d1a-bfc8-a9212b2507f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1336699320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1336699320
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2380900221
Short name T503
Test name
Test status
Simulation time 209633351 ps
CPU time 0.9 seconds
Started Jul 12 05:26:38 PM PDT 24
Finished Jul 12 05:26:41 PM PDT 24
Peak memory 206812 kb
Host smart-17b6778a-5fcd-4cda-a785-c19fe0a9b93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23809
00221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2380900221
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2707052438
Short name T2560
Test name
Test status
Simulation time 182177650 ps
CPU time 0.85 seconds
Started Jul 12 05:26:29 PM PDT 24
Finished Jul 12 05:26:31 PM PDT 24
Peak memory 206824 kb
Host smart-7d51fb6a-d4d0-4eb4-ba74-e3ce35859e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27070
52438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2707052438
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2121002396
Short name T2287
Test name
Test status
Simulation time 149448499 ps
CPU time 0.77 seconds
Started Jul 12 05:26:29 PM PDT 24
Finished Jul 12 05:26:30 PM PDT 24
Peak memory 206812 kb
Host smart-7c4fa852-9fb9-4212-802b-c6a650440a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21210
02396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2121002396
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1214441515
Short name T2208
Test name
Test status
Simulation time 200583638 ps
CPU time 0.86 seconds
Started Jul 12 05:26:30 PM PDT 24
Finished Jul 12 05:26:32 PM PDT 24
Peak memory 206820 kb
Host smart-79567fa5-dca3-4728-809d-f5a313834404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
41515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1214441515
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3041630542
Short name T48
Test name
Test status
Simulation time 461003985 ps
CPU time 1.39 seconds
Started Jul 12 05:26:29 PM PDT 24
Finished Jul 12 05:26:32 PM PDT 24
Peak memory 206816 kb
Host smart-69a95ef1-f6cf-451f-be4f-9d5feca40183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30416
30542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3041630542
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.1789288966
Short name T1956
Test name
Test status
Simulation time 203759024 ps
CPU time 0.88 seconds
Started Jul 12 05:26:29 PM PDT 24
Finished Jul 12 05:26:31 PM PDT 24
Peak memory 206812 kb
Host smart-95076b98-e3a7-452f-a035-c8392bcdedd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17892
88966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1789288966
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.4057394789
Short name T1922
Test name
Test status
Simulation time 159461335 ps
CPU time 0.77 seconds
Started Jul 12 05:26:36 PM PDT 24
Finished Jul 12 05:26:38 PM PDT 24
Peak memory 206796 kb
Host smart-f3ebc090-21a0-4fc5-9f47-e2d76b45f196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40573
94789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.4057394789
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3090275830
Short name T1645
Test name
Test status
Simulation time 185084717 ps
CPU time 0.87 seconds
Started Jul 12 05:26:38 PM PDT 24
Finished Jul 12 05:26:41 PM PDT 24
Peak memory 206692 kb
Host smart-bd2a90d9-e43e-4501-aa8b-f2b1af77d599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30902
75830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3090275830
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3902600385
Short name T2147
Test name
Test status
Simulation time 228113737 ps
CPU time 0.9 seconds
Started Jul 12 05:26:50 PM PDT 24
Finished Jul 12 05:26:52 PM PDT 24
Peak memory 206808 kb
Host smart-0b07a82c-f780-4876-8ebc-fcc592d941ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026
00385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3902600385
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.4206116488
Short name T1736
Test name
Test status
Simulation time 5776532915 ps
CPU time 54.68 seconds
Started Jul 12 05:26:37 PM PDT 24
Finished Jul 12 05:27:35 PM PDT 24
Peak memory 207064 kb
Host smart-b009e57b-71b9-449b-a2f1-f46d12afa727
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4206116488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.4206116488
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3716203668
Short name T2349
Test name
Test status
Simulation time 164834729 ps
CPU time 0.84 seconds
Started Jul 12 05:26:36 PM PDT 24
Finished Jul 12 05:26:38 PM PDT 24
Peak memory 206808 kb
Host smart-aee4fd75-0a1b-49ed-9581-d7782822d519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37162
03668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3716203668
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3685107668
Short name T2482
Test name
Test status
Simulation time 205771975 ps
CPU time 0.86 seconds
Started Jul 12 05:26:39 PM PDT 24
Finished Jul 12 05:26:43 PM PDT 24
Peak memory 206824 kb
Host smart-86b16e0b-a753-4311-be2b-f5a76e7799dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36851
07668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3685107668
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2738675176
Short name T928
Test name
Test status
Simulation time 927846982 ps
CPU time 1.88 seconds
Started Jul 12 05:26:35 PM PDT 24
Finished Jul 12 05:26:38 PM PDT 24
Peak memory 207020 kb
Host smart-7c816b38-f7be-4608-97bb-e23d1857644a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27386
75176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2738675176
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.904108906
Short name T2722
Test name
Test status
Simulation time 5417746918 ps
CPU time 54.22 seconds
Started Jul 12 05:26:39 PM PDT 24
Finished Jul 12 05:27:35 PM PDT 24
Peak memory 206960 kb
Host smart-7f330c8d-5865-44c3-9601-9ce6718d5318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90410
8906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.904108906
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.4158892372
Short name T168
Test name
Test status
Simulation time 6106341339 ps
CPU time 38.37 seconds
Started Jul 12 05:26:42 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 207024 kb
Host smart-3c7980c6-6971-4fc0-824d-626f5d6e9141
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4158892372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.4158892372
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3834223430
Short name T1451
Test name
Test status
Simulation time 28779795 ps
CPU time 0.65 seconds
Started Jul 12 05:29:44 PM PDT 24
Finished Jul 12 05:29:46 PM PDT 24
Peak memory 206860 kb
Host smart-d7af6e14-99cf-45e9-acec-e52200b0e6ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3834223430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3834223430
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.3963253483
Short name T1096
Test name
Test status
Simulation time 4455441909 ps
CPU time 5.2 seconds
Started Jul 12 05:29:44 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 207072 kb
Host smart-8c96a429-2464-4bad-b184-31bf6c254ed4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3963253483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.3963253483
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1508464191
Short name T2276
Test name
Test status
Simulation time 13430697742 ps
CPU time 13.13 seconds
Started Jul 12 05:29:23 PM PDT 24
Finished Jul 12 05:29:38 PM PDT 24
Peak memory 206888 kb
Host smart-4522d13c-57e7-40b7-9830-1bf6498298a0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1508464191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1508464191
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1805843187
Short name T2093
Test name
Test status
Simulation time 23325397694 ps
CPU time 26.96 seconds
Started Jul 12 05:29:33 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 206880 kb
Host smart-a29c8532-b021-413b-846b-5a0bbfd7f28a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1805843187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1805843187
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3944273947
Short name T2181
Test name
Test status
Simulation time 154174168 ps
CPU time 0.79 seconds
Started Jul 12 05:29:28 PM PDT 24
Finished Jul 12 05:29:31 PM PDT 24
Peak memory 206668 kb
Host smart-40879dda-fd9c-4a8f-912c-66b00e2d7612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39442
73947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3944273947
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.979245246
Short name T389
Test name
Test status
Simulation time 236530201 ps
CPU time 0.89 seconds
Started Jul 12 05:29:30 PM PDT 24
Finished Jul 12 05:29:32 PM PDT 24
Peak memory 205676 kb
Host smart-e0da2d81-b9be-4004-8b38-3bc7963b6a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97924
5246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.979245246
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3310787800
Short name T345
Test name
Test status
Simulation time 174635708 ps
CPU time 0.85 seconds
Started Jul 12 05:37:57 PM PDT 24
Finished Jul 12 05:38:21 PM PDT 24
Peak memory 206704 kb
Host smart-534c38a2-72f9-4cab-8fd0-58a4d0c3e7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33107
87800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3310787800
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.16357027
Short name T2052
Test name
Test status
Simulation time 1311743226 ps
CPU time 2.84 seconds
Started Jul 12 05:29:30 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 205756 kb
Host smart-fad78afa-697d-4466-b874-8f5dfbf7f6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16357
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.16357027
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.415471177
Short name T701
Test name
Test status
Simulation time 21795131212 ps
CPU time 34.51 seconds
Started Jul 12 05:29:29 PM PDT 24
Finished Jul 12 05:30:05 PM PDT 24
Peak memory 207044 kb
Host smart-d587b5dc-8c08-4618-915a-0db9bd4c0be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41547
1177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.415471177
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1199784925
Short name T1384
Test name
Test status
Simulation time 541045039 ps
CPU time 1.43 seconds
Started Jul 12 05:29:43 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 206460 kb
Host smart-8e734d43-0f3d-473b-afb6-58576d01735e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11997
84925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1199784925
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1863793044
Short name T2416
Test name
Test status
Simulation time 170451757 ps
CPU time 0.79 seconds
Started Jul 12 05:29:26 PM PDT 24
Finished Jul 12 05:29:29 PM PDT 24
Peak memory 206820 kb
Host smart-67a3e27e-3bc4-438d-abc3-ada9a21dae99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18637
93044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1863793044
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1979582930
Short name T1875
Test name
Test status
Simulation time 49000695 ps
CPU time 0.67 seconds
Started Jul 12 05:29:30 PM PDT 24
Finished Jul 12 05:29:33 PM PDT 24
Peak memory 206800 kb
Host smart-c4fe23c1-c583-4f86-bda1-a41607b93a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19795
82930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1979582930
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.264177479
Short name T2226
Test name
Test status
Simulation time 716433310 ps
CPU time 1.82 seconds
Started Jul 12 05:35:51 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 206912 kb
Host smart-0920bdc8-2a8f-4166-9d3d-9987704c490c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26417
7479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.264177479
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2637109492
Short name T2687
Test name
Test status
Simulation time 173100912 ps
CPU time 1.19 seconds
Started Jul 12 05:29:44 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 206944 kb
Host smart-e656c315-eaf9-4105-be89-7419c33af9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26371
09492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2637109492
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1669218602
Short name T860
Test name
Test status
Simulation time 171588723 ps
CPU time 0.83 seconds
Started Jul 12 05:29:41 PM PDT 24
Finished Jul 12 05:29:43 PM PDT 24
Peak memory 206812 kb
Host smart-3ec55714-22b4-4823-858e-d706f5ef8291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16692
18602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1669218602
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3004491325
Short name T1229
Test name
Test status
Simulation time 139645910 ps
CPU time 0.77 seconds
Started Jul 12 05:29:45 PM PDT 24
Finished Jul 12 05:29:48 PM PDT 24
Peak memory 206788 kb
Host smart-0d662f39-36b2-4cc7-99c4-eba9f0dd3fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30044
91325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3004491325
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.938562
Short name T1562
Test name
Test status
Simulation time 229851665 ps
CPU time 0.97 seconds
Started Jul 12 05:29:30 PM PDT 24
Finished Jul 12 05:29:32 PM PDT 24
Peak memory 206704 kb
Host smart-a2ee8229-80e8-4557-a123-67911234248a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93856
2 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.938562
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.1881926588
Short name T1367
Test name
Test status
Simulation time 11938855990 ps
CPU time 39.17 seconds
Started Jul 12 05:29:30 PM PDT 24
Finished Jul 12 05:30:11 PM PDT 24
Peak memory 207064 kb
Host smart-17dc1690-e274-41eb-8a69-35fe53ef6d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18819
26588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.1881926588
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3101677508
Short name T1755
Test name
Test status
Simulation time 158679400 ps
CPU time 0.76 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:29:39 PM PDT 24
Peak memory 206744 kb
Host smart-3305f825-2e7e-48ba-9774-513f72a7ced3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31016
77508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3101677508
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.184674826
Short name T1366
Test name
Test status
Simulation time 23302616078 ps
CPU time 22.96 seconds
Started Jul 12 05:29:30 PM PDT 24
Finished Jul 12 05:29:54 PM PDT 24
Peak memory 206816 kb
Host smart-4bc2f6b8-1e93-4603-aac6-67c088ee0bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18467
4826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.184674826
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2506334752
Short name T1487
Test name
Test status
Simulation time 3313762102 ps
CPU time 4.22 seconds
Started Jul 12 05:29:24 PM PDT 24
Finished Jul 12 05:29:31 PM PDT 24
Peak memory 206856 kb
Host smart-c8b4e010-f71f-41c6-b606-1862f5650c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
34752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2506334752
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.3982240005
Short name T698
Test name
Test status
Simulation time 7539065239 ps
CPU time 54.51 seconds
Started Jul 12 05:29:32 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 207084 kb
Host smart-afc94e25-6411-45b9-8997-00a31280d99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39822
40005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.3982240005
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.4255120663
Short name T2641
Test name
Test status
Simulation time 6420928922 ps
CPU time 172.47 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:32:31 PM PDT 24
Peak memory 206948 kb
Host smart-5b3dda09-8e0d-40d9-930c-57de228a80c9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4255120663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.4255120663
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3083513211
Short name T2064
Test name
Test status
Simulation time 273014509 ps
CPU time 0.89 seconds
Started Jul 12 05:29:36 PM PDT 24
Finished Jul 12 05:29:38 PM PDT 24
Peak memory 206672 kb
Host smart-12473059-0ab6-4685-af40-5a5502aa715d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3083513211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3083513211
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2672911752
Short name T1430
Test name
Test status
Simulation time 191064119 ps
CPU time 0.84 seconds
Started Jul 12 05:29:28 PM PDT 24
Finished Jul 12 05:29:31 PM PDT 24
Peak memory 206808 kb
Host smart-0d1153d1-9c1e-4f39-a98a-e9633db47df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729
11752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2672911752
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3093442484
Short name T515
Test name
Test status
Simulation time 5054931830 ps
CPU time 133.88 seconds
Started Jul 12 05:29:35 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 207048 kb
Host smart-f07a386b-3652-43c3-8d99-26fd18609735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
42484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3093442484
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.3193408921
Short name T1336
Test name
Test status
Simulation time 3536300635 ps
CPU time 32.57 seconds
Started Jul 12 05:29:43 PM PDT 24
Finished Jul 12 05:30:18 PM PDT 24
Peak memory 206672 kb
Host smart-dcb28318-bccd-4ad7-b143-657b732effb5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3193408921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.3193408921
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.2819003591
Short name T2584
Test name
Test status
Simulation time 169457540 ps
CPU time 0.76 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 206792 kb
Host smart-29f2fdbf-5490-4cde-9c83-75f561bc6d5b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2819003591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.2819003591
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2421655805
Short name T2010
Test name
Test status
Simulation time 140537458 ps
CPU time 0.75 seconds
Started Jul 12 05:29:27 PM PDT 24
Finished Jul 12 05:29:30 PM PDT 24
Peak memory 206640 kb
Host smart-fefcddf7-7a2f-4946-bdae-cf6727c38eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
55805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2421655805
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3666373996
Short name T2723
Test name
Test status
Simulation time 188982509 ps
CPU time 0.85 seconds
Started Jul 12 05:29:32 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 206808 kb
Host smart-4b0d93f7-1eef-40b6-aea4-a1019234b9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36663
73996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3666373996
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.1127136960
Short name T2280
Test name
Test status
Simulation time 183836441 ps
CPU time 0.86 seconds
Started Jul 12 05:29:52 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 206788 kb
Host smart-6e836723-7a6f-4342-951b-ce01520f1be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11271
36960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.1127136960
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3175098305
Short name T354
Test name
Test status
Simulation time 167329166 ps
CPU time 0.8 seconds
Started Jul 12 05:29:44 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 206788 kb
Host smart-cc1223eb-07be-4b6f-9bc3-551455d14815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31750
98305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3175098305
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2875656612
Short name T2519
Test name
Test status
Simulation time 160442179 ps
CPU time 0.83 seconds
Started Jul 12 05:29:42 PM PDT 24
Finished Jul 12 05:29:45 PM PDT 24
Peak memory 206704 kb
Host smart-1dbc25b8-86fc-4951-8524-788aaf2ef141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28756
56612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2875656612
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.144408646
Short name T2453
Test name
Test status
Simulation time 147363844 ps
CPU time 0.77 seconds
Started Jul 12 05:29:43 PM PDT 24
Finished Jul 12 05:29:46 PM PDT 24
Peak memory 206812 kb
Host smart-adc86313-dde6-4203-ab25-14184ba0f211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
8646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.144408646
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.3781059882
Short name T1884
Test name
Test status
Simulation time 253107948 ps
CPU time 1 seconds
Started Jul 12 05:29:32 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 206816 kb
Host smart-b0499819-0c6c-4e24-9427-884bebd8c284
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3781059882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.3781059882
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1205207361
Short name T1721
Test name
Test status
Simulation time 164702518 ps
CPU time 0.84 seconds
Started Jul 12 05:29:36 PM PDT 24
Finished Jul 12 05:29:37 PM PDT 24
Peak memory 206808 kb
Host smart-f7271fe2-89ee-41cb-97dd-d6a155f2d3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12052
07361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1205207361
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1619186247
Short name T2219
Test name
Test status
Simulation time 37149196 ps
CPU time 0.7 seconds
Started Jul 12 05:29:35 PM PDT 24
Finished Jul 12 05:29:37 PM PDT 24
Peak memory 206816 kb
Host smart-a9e0e68b-3a6a-4738-8fca-0d50081aa366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16191
86247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1619186247
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3730942397
Short name T1686
Test name
Test status
Simulation time 7575951222 ps
CPU time 17.34 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:30:08 PM PDT 24
Peak memory 207116 kb
Host smart-d66c71cb-964b-4e75-95fc-06f8b4efcaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37309
42397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3730942397
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3128504613
Short name T2683
Test name
Test status
Simulation time 212393984 ps
CPU time 0.89 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:29:39 PM PDT 24
Peak memory 206716 kb
Host smart-6999fd53-26ec-4cd0-bb92-77445c23cdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31285
04613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3128504613
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.4096306873
Short name T1708
Test name
Test status
Simulation time 177224266 ps
CPU time 0.87 seconds
Started Jul 12 05:29:30 PM PDT 24
Finished Jul 12 05:29:32 PM PDT 24
Peak memory 206820 kb
Host smart-22da0c2d-8871-4206-a00a-9c94bfed80ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40963
06873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.4096306873
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3687985421
Short name T1958
Test name
Test status
Simulation time 198761742 ps
CPU time 0.8 seconds
Started Jul 12 05:29:43 PM PDT 24
Finished Jul 12 05:29:46 PM PDT 24
Peak memory 206816 kb
Host smart-2f4c7f72-fb13-4d19-b608-091fd153781e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36879
85421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3687985421
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2216324207
Short name T2099
Test name
Test status
Simulation time 169071884 ps
CPU time 0.88 seconds
Started Jul 12 05:29:39 PM PDT 24
Finished Jul 12 05:29:41 PM PDT 24
Peak memory 206720 kb
Host smart-6f6adc40-c150-463d-930f-21f793c3dcbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22163
24207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2216324207
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2974133542
Short name T1393
Test name
Test status
Simulation time 187769928 ps
CPU time 0.83 seconds
Started Jul 12 05:29:36 PM PDT 24
Finished Jul 12 05:29:38 PM PDT 24
Peak memory 206796 kb
Host smart-90285c51-8169-44d0-908e-5ca0ad8b097c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29741
33542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2974133542
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2847797172
Short name T913
Test name
Test status
Simulation time 161344778 ps
CPU time 0.78 seconds
Started Jul 12 05:29:39 PM PDT 24
Finished Jul 12 05:29:41 PM PDT 24
Peak memory 206796 kb
Host smart-cb1e9b0a-37e9-4231-a19d-ad56d8972220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28477
97172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2847797172
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1108397830
Short name T1787
Test name
Test status
Simulation time 157842287 ps
CPU time 0.82 seconds
Started Jul 12 05:29:47 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 206716 kb
Host smart-b19916bd-5951-4f0d-ae53-cbc67f68bbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11083
97830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1108397830
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1243091275
Short name T1247
Test name
Test status
Simulation time 219458896 ps
CPU time 0.97 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:29:39 PM PDT 24
Peak memory 206804 kb
Host smart-cab15df0-880f-4f9f-9825-8b76995edf53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12430
91275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1243091275
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2958318217
Short name T2729
Test name
Test status
Simulation time 4030298567 ps
CPU time 107.03 seconds
Started Jul 12 05:29:42 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 207000 kb
Host smart-ef515606-e412-46d5-ba05-026a17d8a1ff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2958318217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2958318217
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1882475501
Short name T1001
Test name
Test status
Simulation time 158724402 ps
CPU time 0.84 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 206816 kb
Host smart-97075a4f-ee0e-40b3-a961-6addd6fa8631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18824
75501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1882475501
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.4078267965
Short name T2410
Test name
Test status
Simulation time 267255785 ps
CPU time 0.93 seconds
Started Jul 12 05:29:36 PM PDT 24
Finished Jul 12 05:29:38 PM PDT 24
Peak memory 206816 kb
Host smart-d0254ba8-29df-4635-8a77-361eabbe9d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40782
67965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.4078267965
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.144586816
Short name T602
Test name
Test status
Simulation time 696557676 ps
CPU time 1.7 seconds
Started Jul 12 05:29:40 PM PDT 24
Finished Jul 12 05:29:43 PM PDT 24
Peak memory 207012 kb
Host smart-1d8fbdb3-72e0-4e2f-9ced-03462abbce88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14458
6816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.144586816
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3866295616
Short name T1928
Test name
Test status
Simulation time 5140551530 ps
CPU time 49.31 seconds
Started Jul 12 05:29:35 PM PDT 24
Finished Jul 12 05:30:25 PM PDT 24
Peak memory 207080 kb
Host smart-6d68394e-484d-44ef-86a7-4e961b2af559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38662
95616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3866295616
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1358982677
Short name T2441
Test name
Test status
Simulation time 44858408 ps
CPU time 0.67 seconds
Started Jul 12 05:29:40 PM PDT 24
Finished Jul 12 05:29:42 PM PDT 24
Peak memory 206860 kb
Host smart-ebe6f750-c738-41d6-96b8-77d5034413b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1358982677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1358982677
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.823940232
Short name T480
Test name
Test status
Simulation time 3726523789 ps
CPU time 4.65 seconds
Started Jul 12 05:29:32 PM PDT 24
Finished Jul 12 05:29:37 PM PDT 24
Peak memory 206956 kb
Host smart-69bacab0-3410-4868-86da-8483a3399475
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=823940232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.823940232
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2473898074
Short name T1278
Test name
Test status
Simulation time 13435947660 ps
CPU time 12.73 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:29:50 PM PDT 24
Peak memory 206876 kb
Host smart-a94231e4-f8f6-47b1-a7fa-8b7d7452b86e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2473898074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2473898074
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.820617702
Short name T1345
Test name
Test status
Simulation time 23362398661 ps
CPU time 21.97 seconds
Started Jul 12 05:29:38 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 207008 kb
Host smart-0afbb645-05d0-4e76-8db9-a431f080e3a3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=820617702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.820617702
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.486397850
Short name T633
Test name
Test status
Simulation time 238636146 ps
CPU time 0.84 seconds
Started Jul 12 05:29:32 PM PDT 24
Finished Jul 12 05:29:34 PM PDT 24
Peak memory 206684 kb
Host smart-cd9232da-726e-4e78-88df-132110203da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48639
7850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.486397850
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1199196029
Short name T839
Test name
Test status
Simulation time 163949846 ps
CPU time 0.81 seconds
Started Jul 12 05:29:44 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 206808 kb
Host smart-744ba9ce-6cce-420b-a520-b1f365ccd628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11991
96029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1199196029
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.13480441
Short name T1069
Test name
Test status
Simulation time 184543542 ps
CPU time 0.87 seconds
Started Jul 12 05:29:35 PM PDT 24
Finished Jul 12 05:29:37 PM PDT 24
Peak memory 206824 kb
Host smart-4ed7007b-6f1e-41c9-8afb-4756fa71c8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13480
441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.13480441
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2125278699
Short name T104
Test name
Test status
Simulation time 1170598469 ps
CPU time 2.55 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:29:41 PM PDT 24
Peak memory 207020 kb
Host smart-ddd47352-2e4d-4b39-99f1-4dc1477bc1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21252
78699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2125278699
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.1016681156
Short name T1308
Test name
Test status
Simulation time 22121814183 ps
CPU time 38.97 seconds
Started Jul 12 05:29:47 PM PDT 24
Finished Jul 12 05:30:28 PM PDT 24
Peak memory 207088 kb
Host smart-545da5fa-eae0-4e02-b199-379a58ca5531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166
81156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1016681156
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3895993495
Short name T1187
Test name
Test status
Simulation time 418929251 ps
CPU time 1.32 seconds
Started Jul 12 05:29:39 PM PDT 24
Finished Jul 12 05:29:41 PM PDT 24
Peak memory 206684 kb
Host smart-4059feb4-44dc-4b48-9d9c-27fcad05df5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38959
93495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3895993495
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.4217969219
Short name T2707
Test name
Test status
Simulation time 145891878 ps
CPU time 0.78 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 206792 kb
Host smart-cf0d0a59-55a9-4fcd-b5ce-5051636d8c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42179
69219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.4217969219
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3736930714
Short name T1465
Test name
Test status
Simulation time 94012979 ps
CPU time 0.69 seconds
Started Jul 12 05:29:33 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 206756 kb
Host smart-6cf6e1e6-cd0f-4835-891b-a1beb3db9fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37369
30714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3736930714
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1384644932
Short name T1360
Test name
Test status
Simulation time 861557809 ps
CPU time 2 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:29:54 PM PDT 24
Peak memory 207016 kb
Host smart-a499f8d3-4d9d-4c24-84b8-33194a11d37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
44932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1384644932
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1320839758
Short name T2556
Test name
Test status
Simulation time 308615434 ps
CPU time 1.81 seconds
Started Jul 12 05:29:34 PM PDT 24
Finished Jul 12 05:29:36 PM PDT 24
Peak memory 207008 kb
Host smart-afe4d149-2ef4-4a27-9fa4-a3d40b5aa1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13208
39758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1320839758
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2845011221
Short name T2549
Test name
Test status
Simulation time 182490900 ps
CPU time 0.9 seconds
Started Jul 12 05:29:33 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 206792 kb
Host smart-aadbd88e-5d10-4a02-9699-7cdc0b062eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28450
11221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2845011221
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2056934576
Short name T1705
Test name
Test status
Simulation time 143631597 ps
CPU time 0.75 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:29:53 PM PDT 24
Peak memory 206800 kb
Host smart-4360d4f9-ccb1-4a12-a06e-07856a65454b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20569
34576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2056934576
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2166227961
Short name T1717
Test name
Test status
Simulation time 192270904 ps
CPU time 0.83 seconds
Started Jul 12 05:29:33 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 206808 kb
Host smart-ca4e6405-8811-4dc6-9c0c-7e6b26b0468e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
27961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2166227961
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3963304402
Short name T2541
Test name
Test status
Simulation time 226641009 ps
CPU time 0.96 seconds
Started Jul 12 05:29:45 PM PDT 24
Finished Jul 12 05:29:48 PM PDT 24
Peak memory 207000 kb
Host smart-aee3ccfe-64f2-4825-85c8-f24288cc09b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
04402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3963304402
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.666236126
Short name T2001
Test name
Test status
Simulation time 23273937932 ps
CPU time 22.9 seconds
Started Jul 12 05:29:35 PM PDT 24
Finished Jul 12 05:29:59 PM PDT 24
Peak memory 206872 kb
Host smart-d566b901-2fb5-45a0-b17a-6763be9d3326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66623
6126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.666236126
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2101138120
Short name T2684
Test name
Test status
Simulation time 3301415986 ps
CPU time 4.15 seconds
Started Jul 12 05:29:42 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 206892 kb
Host smart-f9c0909b-8eb8-4b26-98d1-bc11ace52feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21011
38120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2101138120
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1533598721
Short name T2087
Test name
Test status
Simulation time 7806481038 ps
CPU time 70.73 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:30:49 PM PDT 24
Peak memory 207104 kb
Host smart-fcadb6f3-24d3-4e47-9445-c1514f2063d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15335
98721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1533598721
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.4048110718
Short name T523
Test name
Test status
Simulation time 3522268552 ps
CPU time 25.2 seconds
Started Jul 12 05:29:37 PM PDT 24
Finished Jul 12 05:30:03 PM PDT 24
Peak memory 207000 kb
Host smart-3de03599-4437-491e-8e89-9ea89f400a98
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4048110718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.4048110718
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.463287041
Short name T2620
Test name
Test status
Simulation time 265567951 ps
CPU time 0.97 seconds
Started Jul 12 05:29:41 PM PDT 24
Finished Jul 12 05:29:43 PM PDT 24
Peak memory 206816 kb
Host smart-872a039e-89d7-4384-90f1-92057324d690
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=463287041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.463287041
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1485476094
Short name T313
Test name
Test status
Simulation time 192718381 ps
CPU time 0.85 seconds
Started Jul 12 05:29:44 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 206692 kb
Host smart-f065bc28-b3dd-4878-b36a-1cdd80a5fa46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14854
76094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1485476094
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2945930880
Short name T805
Test name
Test status
Simulation time 4002815465 ps
CPU time 37.31 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:38 PM PDT 24
Peak memory 207048 kb
Host smart-65cf79f2-aa8f-4879-85c7-94cd9044e68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29459
30880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2945930880
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1856396720
Short name T1473
Test name
Test status
Simulation time 5773504749 ps
CPU time 41.94 seconds
Started Jul 12 05:29:38 PM PDT 24
Finished Jul 12 05:30:21 PM PDT 24
Peak memory 206968 kb
Host smart-36d11050-e34d-4959-8a1f-2ce079a0e4df
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1856396720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1856396720
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.137414622
Short name T2717
Test name
Test status
Simulation time 193246219 ps
CPU time 0.8 seconds
Started Jul 12 05:29:52 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 206716 kb
Host smart-8ec80b64-5e24-46d0-8fbf-0311bc67da86
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=137414622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.137414622
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2550627782
Short name T1325
Test name
Test status
Simulation time 154065516 ps
CPU time 0.78 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 206836 kb
Host smart-aab3473c-c861-4b9d-978f-299b3d404734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25506
27782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2550627782
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1149786725
Short name T2523
Test name
Test status
Simulation time 239461776 ps
CPU time 0.9 seconds
Started Jul 12 05:29:40 PM PDT 24
Finished Jul 12 05:29:43 PM PDT 24
Peak memory 206692 kb
Host smart-4a8c5374-e00c-426c-82bf-03a83806e413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11497
86725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1149786725
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3123927474
Short name T2262
Test name
Test status
Simulation time 198072209 ps
CPU time 0.82 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 206816 kb
Host smart-651c32f1-80dc-44bc-84c3-836b25e80307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31239
27474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3123927474
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2622092981
Short name T2151
Test name
Test status
Simulation time 171211883 ps
CPU time 0.8 seconds
Started Jul 12 05:29:40 PM PDT 24
Finished Jul 12 05:29:42 PM PDT 24
Peak memory 206692 kb
Host smart-53554f18-fb99-4a2b-b196-44efe4c8cb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
92981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2622092981
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.135194357
Short name T2061
Test name
Test status
Simulation time 219166156 ps
CPU time 0.88 seconds
Started Jul 12 05:29:41 PM PDT 24
Finished Jul 12 05:29:43 PM PDT 24
Peak memory 206796 kb
Host smart-8965dd64-b566-4560-9f07-8b4f7c77edab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
4357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.135194357
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1204821970
Short name T877
Test name
Test status
Simulation time 163175567 ps
CPU time 0.82 seconds
Started Jul 12 05:29:42 PM PDT 24
Finished Jul 12 05:29:45 PM PDT 24
Peak memory 206800 kb
Host smart-dcf03d17-69e1-4efc-a667-f5d69ae79cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12048
21970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1204821970
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.4107289066
Short name T1099
Test name
Test status
Simulation time 215715783 ps
CPU time 0.91 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 207008 kb
Host smart-6f90f486-1c51-4552-bbe2-2c9d6eab9ffc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4107289066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.4107289066
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3318558453
Short name T1032
Test name
Test status
Simulation time 149507164 ps
CPU time 0.78 seconds
Started Jul 12 05:29:39 PM PDT 24
Finished Jul 12 05:29:41 PM PDT 24
Peak memory 206816 kb
Host smart-9187b99f-93a6-4c04-8589-5a1cab6ffadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33185
58453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3318558453
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2526105271
Short name T2679
Test name
Test status
Simulation time 90455753 ps
CPU time 0.69 seconds
Started Jul 12 05:29:52 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 206832 kb
Host smart-116b55be-9593-44f9-88cd-a0c2ed5a10d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25261
05271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2526105271
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3706388441
Short name T2382
Test name
Test status
Simulation time 15994299487 ps
CPU time 36.81 seconds
Started Jul 12 05:29:42 PM PDT 24
Finished Jul 12 05:30:21 PM PDT 24
Peak memory 206996 kb
Host smart-4a16e51c-0f79-4b6b-9956-a0130c85e33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37063
88441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3706388441
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3109360701
Short name T2442
Test name
Test status
Simulation time 185680895 ps
CPU time 0.87 seconds
Started Jul 12 05:29:40 PM PDT 24
Finished Jul 12 05:29:42 PM PDT 24
Peak memory 206820 kb
Host smart-4c81aa6a-5686-49d1-b4d1-ef12376780ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31093
60701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3109360701
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1955841259
Short name T1719
Test name
Test status
Simulation time 190828860 ps
CPU time 0.82 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 206816 kb
Host smart-2d4e2be2-cf6a-4d13-83eb-8118ce1862d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19558
41259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1955841259
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.488912100
Short name T2724
Test name
Test status
Simulation time 213300850 ps
CPU time 0.94 seconds
Started Jul 12 05:29:40 PM PDT 24
Finished Jul 12 05:29:43 PM PDT 24
Peak memory 206796 kb
Host smart-4e3532e3-e9f6-47b8-ac27-64c5d2bfa799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48891
2100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.488912100
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.292656582
Short name T363
Test name
Test status
Simulation time 175661818 ps
CPU time 0.86 seconds
Started Jul 12 05:29:40 PM PDT 24
Finished Jul 12 05:29:42 PM PDT 24
Peak memory 206636 kb
Host smart-d82f4e6c-6a60-4c8f-bcfb-873e177c6949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29265
6582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.292656582
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3142412871
Short name T824
Test name
Test status
Simulation time 143336126 ps
CPU time 0.8 seconds
Started Jul 12 05:29:54 PM PDT 24
Finished Jul 12 05:29:58 PM PDT 24
Peak memory 206672 kb
Host smart-3ef67c38-1911-4125-b74d-52b0ac414f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31424
12871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3142412871
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2381572451
Short name T346
Test name
Test status
Simulation time 163857490 ps
CPU time 0.76 seconds
Started Jul 12 05:29:56 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 206812 kb
Host smart-7b7ae54a-19d9-40aa-ac55-fe176eb94086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23815
72451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2381572451
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2459516164
Short name T911
Test name
Test status
Simulation time 162345001 ps
CPU time 0.84 seconds
Started Jul 12 05:29:45 PM PDT 24
Finished Jul 12 05:29:47 PM PDT 24
Peak memory 206692 kb
Host smart-300715b0-3f77-4d9d-a891-a99ff8c4051e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24595
16164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2459516164
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3284896942
Short name T2533
Test name
Test status
Simulation time 253064463 ps
CPU time 0.97 seconds
Started Jul 12 05:29:40 PM PDT 24
Finished Jul 12 05:29:42 PM PDT 24
Peak memory 206816 kb
Host smart-d0e4aa4a-ccd1-4cb1-b004-28486b39ec03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848
96942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3284896942
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.842405859
Short name T1417
Test name
Test status
Simulation time 4561608122 ps
CPU time 120.32 seconds
Started Jul 12 05:29:42 PM PDT 24
Finished Jul 12 05:31:44 PM PDT 24
Peak memory 207060 kb
Host smart-5ebc2258-2f2a-46c1-823f-f4fe13f56e49
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=842405859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.842405859
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2884396876
Short name T2324
Test name
Test status
Simulation time 152267376 ps
CPU time 0.84 seconds
Started Jul 12 05:29:47 PM PDT 24
Finished Jul 12 05:29:50 PM PDT 24
Peak memory 206824 kb
Host smart-c1d91061-9f09-4783-b6fb-7392508d0784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28843
96876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2884396876
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.343899577
Short name T947
Test name
Test status
Simulation time 192505598 ps
CPU time 0.84 seconds
Started Jul 12 05:29:41 PM PDT 24
Finished Jul 12 05:29:44 PM PDT 24
Peak memory 206808 kb
Host smart-64e9ff5a-7c27-4df9-9567-6c3ac2ce3b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34389
9577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.343899577
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3672318280
Short name T1218
Test name
Test status
Simulation time 809921509 ps
CPU time 1.79 seconds
Started Jul 12 05:29:46 PM PDT 24
Finished Jul 12 05:29:50 PM PDT 24
Peak memory 206964 kb
Host smart-f634138a-554d-4832-94e9-8fd5649d9db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36723
18280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3672318280
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.19921335
Short name T451
Test name
Test status
Simulation time 7575662143 ps
CPU time 71.34 seconds
Started Jul 12 05:29:47 PM PDT 24
Finished Jul 12 05:31:00 PM PDT 24
Peak memory 207096 kb
Host smart-a94c540f-b171-45e2-9824-0fa0e39758ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19921
335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.19921335
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.513894889
Short name T1283
Test name
Test status
Simulation time 42459591 ps
CPU time 0.73 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:29:59 PM PDT 24
Peak memory 206672 kb
Host smart-41042146-8c5d-45dd-9843-e2160d020c86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=513894889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.513894889
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2249742516
Short name T572
Test name
Test status
Simulation time 4340845854 ps
CPU time 5.07 seconds
Started Jul 12 05:29:42 PM PDT 24
Finished Jul 12 05:29:48 PM PDT 24
Peak memory 207016 kb
Host smart-2961e2c1-cf2a-4e36-8e3e-ecde41e4c9b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2249742516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2249742516
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.4159082130
Short name T977
Test name
Test status
Simulation time 13367736494 ps
CPU time 13.22 seconds
Started Jul 12 05:29:45 PM PDT 24
Finished Jul 12 05:30:00 PM PDT 24
Peak memory 207108 kb
Host smart-36cea829-89e4-4a4f-8c82-725f72f5bac6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4159082130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.4159082130
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.4001780056
Short name T2337
Test name
Test status
Simulation time 23335953688 ps
CPU time 23.75 seconds
Started Jul 12 05:29:56 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206888 kb
Host smart-076159e1-8c10-49b1-a454-ad500f4d9c06
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4001780056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.4001780056
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.927375816
Short name T2648
Test name
Test status
Simulation time 198001172 ps
CPU time 0.91 seconds
Started Jul 12 05:29:41 PM PDT 24
Finished Jul 12 05:29:44 PM PDT 24
Peak memory 206808 kb
Host smart-44bcfc79-72e3-4155-a643-792f085e83a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92737
5816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.927375816
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.927067997
Short name T2507
Test name
Test status
Simulation time 158139090 ps
CPU time 0.85 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 206820 kb
Host smart-92c83c97-8b59-4fc5-931c-06c2d1178c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92706
7997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.927067997
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3927930045
Short name T1968
Test name
Test status
Simulation time 233876837 ps
CPU time 0.93 seconds
Started Jul 12 05:29:47 PM PDT 24
Finished Jul 12 05:29:50 PM PDT 24
Peak memory 206720 kb
Host smart-6f54aef7-7a87-4a8f-bb31-42c1123e8fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39279
30045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3927930045
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.648298050
Short name T1737
Test name
Test status
Simulation time 672309025 ps
CPU time 1.67 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 206824 kb
Host smart-b11da8a9-36de-49da-ab3f-726c6e98dbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64829
8050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.648298050
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.285293206
Short name T2699
Test name
Test status
Simulation time 481336348 ps
CPU time 1.43 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:02 PM PDT 24
Peak memory 206696 kb
Host smart-0a85e67e-0195-46dd-bd8b-7f21bbfa6b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28529
3206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.285293206
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3791937161
Short name T1581
Test name
Test status
Simulation time 155339052 ps
CPU time 0.79 seconds
Started Jul 12 05:30:01 PM PDT 24
Finished Jul 12 05:30:05 PM PDT 24
Peak memory 206808 kb
Host smart-1f37453a-d08b-4a08-8a98-7bedf57a62a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37919
37161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3791937161
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3869393192
Short name T1376
Test name
Test status
Simulation time 43324915 ps
CPU time 0.71 seconds
Started Jul 12 05:29:53 PM PDT 24
Finished Jul 12 05:29:56 PM PDT 24
Peak memory 206688 kb
Host smart-04bbf0c0-85aa-4aac-a1f0-3da847050856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38693
93192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3869393192
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2939243584
Short name T1156
Test name
Test status
Simulation time 886764615 ps
CPU time 2.4 seconds
Started Jul 12 05:29:52 PM PDT 24
Finished Jul 12 05:29:56 PM PDT 24
Peak memory 207008 kb
Host smart-49a8f999-4ca3-45e5-af2e-b312c2ea222d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29392
43584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2939243584
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.823989302
Short name T364
Test name
Test status
Simulation time 289261618 ps
CPU time 1.63 seconds
Started Jul 12 05:29:54 PM PDT 24
Finished Jul 12 05:29:58 PM PDT 24
Peak memory 206828 kb
Host smart-817901e4-9a2d-4abc-a1db-186a0b150a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82398
9302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.823989302
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2752541188
Short name T1716
Test name
Test status
Simulation time 190804998 ps
CPU time 0.79 seconds
Started Jul 12 05:29:54 PM PDT 24
Finished Jul 12 05:29:58 PM PDT 24
Peak memory 206820 kb
Host smart-20d7bb24-e5a2-45cf-8b66-c4af7bbacfd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
41188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2752541188
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.720164518
Short name T2496
Test name
Test status
Simulation time 153969169 ps
CPU time 0.79 seconds
Started Jul 12 05:30:03 PM PDT 24
Finished Jul 12 05:30:07 PM PDT 24
Peak memory 206804 kb
Host smart-f83ee99d-e1d0-4a09-9c52-1df6de73dbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72016
4518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.720164518
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3898903211
Short name T921
Test name
Test status
Simulation time 244420601 ps
CPU time 0.94 seconds
Started Jul 12 05:29:46 PM PDT 24
Finished Jul 12 05:29:49 PM PDT 24
Peak memory 206812 kb
Host smart-009c29df-8062-4931-97b0-c3019c62ccf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38989
03211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3898903211
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.3020742638
Short name T2357
Test name
Test status
Simulation time 5679839191 ps
CPU time 40.82 seconds
Started Jul 12 05:29:56 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206860 kb
Host smart-2e63ae5b-4e38-42aa-8111-e97afb782db3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3020742638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.3020742638
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1682466794
Short name T2404
Test name
Test status
Simulation time 9082698781 ps
CPU time 79.52 seconds
Started Jul 12 05:30:02 PM PDT 24
Finished Jul 12 05:31:25 PM PDT 24
Peak memory 207076 kb
Host smart-cbcc22e3-6aba-4343-9d5a-890b7fec6726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16824
66794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1682466794
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3724750993
Short name T2432
Test name
Test status
Simulation time 227176922 ps
CPU time 0.9 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 206768 kb
Host smart-58e3c0d6-32ed-4e67-8ba5-0da9a3340080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37247
50993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3724750993
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3898224150
Short name T1598
Test name
Test status
Simulation time 23314529750 ps
CPU time 27 seconds
Started Jul 12 05:29:59 PM PDT 24
Finished Jul 12 05:30:30 PM PDT 24
Peak memory 206784 kb
Host smart-cec9f354-3745-4459-b96d-3a28284ca1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38982
24150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3898224150
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2654910883
Short name T1319
Test name
Test status
Simulation time 3364306750 ps
CPU time 3.97 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 206880 kb
Host smart-dd497897-f090-4882-ab19-6f24550eaab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26549
10883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2654910883
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.3754669613
Short name T1003
Test name
Test status
Simulation time 8022997696 ps
CPU time 57.72 seconds
Started Jul 12 05:29:50 PM PDT 24
Finished Jul 12 05:30:50 PM PDT 24
Peak memory 206968 kb
Host smart-418f9bd8-152d-483a-84c3-e57ef9aa20f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37546
69613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3754669613
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.999603079
Short name T2736
Test name
Test status
Simulation time 5629743904 ps
CPU time 157.24 seconds
Started Jul 12 05:29:51 PM PDT 24
Finished Jul 12 05:32:31 PM PDT 24
Peak memory 206892 kb
Host smart-e5f1e168-8d15-4483-a233-c1daf2e41a26
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=999603079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.999603079
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.4249403787
Short name T418
Test name
Test status
Simulation time 238553286 ps
CPU time 0.95 seconds
Started Jul 12 05:29:50 PM PDT 24
Finished Jul 12 05:29:54 PM PDT 24
Peak memory 206804 kb
Host smart-227c85fb-7afe-4e62-822d-cffaed47b6ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4249403787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.4249403787
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1507951046
Short name T1309
Test name
Test status
Simulation time 219932862 ps
CPU time 0.95 seconds
Started Jul 12 05:29:59 PM PDT 24
Finished Jul 12 05:30:03 PM PDT 24
Peak memory 207036 kb
Host smart-3aa581a6-fd95-44f5-8c16-d07e038580b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15079
51046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1507951046
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3279825439
Short name T1966
Test name
Test status
Simulation time 3863230162 ps
CPU time 29.7 seconds
Started Jul 12 05:30:06 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 207048 kb
Host smart-d4d51a6a-8733-46b9-9557-276b4ef65428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32798
25439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3279825439
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1947185611
Short name T2188
Test name
Test status
Simulation time 4328327207 ps
CPU time 113.74 seconds
Started Jul 12 05:29:53 PM PDT 24
Finished Jul 12 05:31:50 PM PDT 24
Peak memory 206984 kb
Host smart-12d43871-d185-4d10-ac0c-47332cf31329
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1947185611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1947185611
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2833555762
Short name T2175
Test name
Test status
Simulation time 188894571 ps
CPU time 0.84 seconds
Started Jul 12 05:29:52 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 206936 kb
Host smart-49394b33-c903-493c-a94d-34e40849397a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2833555762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2833555762
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2090335670
Short name T1583
Test name
Test status
Simulation time 144840746 ps
CPU time 0.81 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 206680 kb
Host smart-dfc6e4c3-5368-4cb2-831f-bc2384c22051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903
35670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2090335670
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3460263027
Short name T110
Test name
Test status
Simulation time 206443390 ps
CPU time 0.82 seconds
Started Jul 12 05:30:00 PM PDT 24
Finished Jul 12 05:30:04 PM PDT 24
Peak memory 206832 kb
Host smart-1544d491-ede4-4006-b8cc-cacefaa75768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34602
63027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3460263027
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.801179007
Short name T935
Test name
Test status
Simulation time 200111832 ps
CPU time 0.87 seconds
Started Jul 12 05:29:52 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 206696 kb
Host smart-8746598d-f637-4efe-bb27-df1902a870a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80117
9007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.801179007
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1399146027
Short name T334
Test name
Test status
Simulation time 153122597 ps
CPU time 0.75 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206808 kb
Host smart-ac998800-f526-4515-ba08-a34b48669ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13991
46027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1399146027
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3542637937
Short name T873
Test name
Test status
Simulation time 178527937 ps
CPU time 0.83 seconds
Started Jul 12 05:29:51 PM PDT 24
Finished Jul 12 05:29:54 PM PDT 24
Peak memory 206812 kb
Host smart-28c3378d-b748-49ee-b729-d6345bf1d38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35426
37937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3542637937
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1994594711
Short name T677
Test name
Test status
Simulation time 150011195 ps
CPU time 0.77 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:29:59 PM PDT 24
Peak memory 206796 kb
Host smart-e6692241-0510-4a39-8824-cfd8a5450bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19945
94711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1994594711
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1758026593
Short name T1668
Test name
Test status
Simulation time 245649833 ps
CPU time 1.02 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:29:53 PM PDT 24
Peak memory 206820 kb
Host smart-a77ac1d6-cfeb-40a8-94f9-9c2c06da73c4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1758026593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1758026593
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1821342639
Short name T967
Test name
Test status
Simulation time 143713104 ps
CPU time 0.78 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:29:53 PM PDT 24
Peak memory 206820 kb
Host smart-d1d7138f-7093-47fe-94cb-0e4ab5963aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18213
42639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1821342639
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1327029056
Short name T797
Test name
Test status
Simulation time 42098811 ps
CPU time 0.68 seconds
Started Jul 12 05:29:53 PM PDT 24
Finished Jul 12 05:29:56 PM PDT 24
Peak memory 206828 kb
Host smart-5f4cb4c3-9b21-41ca-89b3-e1ed70670e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13270
29056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1327029056
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1510748674
Short name T2452
Test name
Test status
Simulation time 9793857382 ps
CPU time 21.48 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:23 PM PDT 24
Peak memory 207100 kb
Host smart-98bbec75-9712-4871-b6d6-ba82e50d5f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15107
48674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1510748674
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2730808718
Short name T1115
Test name
Test status
Simulation time 173563526 ps
CPU time 0.85 seconds
Started Jul 12 05:29:52 PM PDT 24
Finished Jul 12 05:29:55 PM PDT 24
Peak memory 206820 kb
Host smart-41d6e18c-97e7-4d90-bdc2-0046d715042f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27308
08718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2730808718
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.386732665
Short name T1463
Test name
Test status
Simulation time 200098579 ps
CPU time 0.85 seconds
Started Jul 12 05:29:54 PM PDT 24
Finished Jul 12 05:29:58 PM PDT 24
Peak memory 206808 kb
Host smart-f42d59a0-04b0-4e25-9bfd-93b3009e3d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38673
2665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.386732665
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.150155985
Short name T341
Test name
Test status
Simulation time 232392203 ps
CPU time 0.92 seconds
Started Jul 12 05:29:52 PM PDT 24
Finished Jul 12 05:29:56 PM PDT 24
Peak memory 206908 kb
Host smart-119c521b-b1f1-48e8-97e9-3d32de637038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15015
5985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.150155985
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2959022378
Short name T2640
Test name
Test status
Simulation time 159920325 ps
CPU time 0.84 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:29:53 PM PDT 24
Peak memory 206824 kb
Host smart-a05b43f4-3305-4bf6-8ac9-3318302861fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29590
22378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2959022378
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1339426638
Short name T576
Test name
Test status
Simulation time 243485186 ps
CPU time 0.86 seconds
Started Jul 12 05:29:53 PM PDT 24
Finished Jul 12 05:29:56 PM PDT 24
Peak memory 206816 kb
Host smart-511c2de5-5ad4-4cea-b2f2-27fb8210b559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
26638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1339426638
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.4046592640
Short name T1416
Test name
Test status
Simulation time 162037701 ps
CPU time 0.79 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:29:59 PM PDT 24
Peak memory 206812 kb
Host smart-1591244a-d3c7-414a-b9e7-1a1f11a66fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40465
92640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.4046592640
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3260555840
Short name T682
Test name
Test status
Simulation time 149887406 ps
CPU time 0.83 seconds
Started Jul 12 05:30:00 PM PDT 24
Finished Jul 12 05:30:04 PM PDT 24
Peak memory 206812 kb
Host smart-c35417c7-75a4-4ae4-96ef-64bbcdee73c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32605
55840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3260555840
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.444252024
Short name T2150
Test name
Test status
Simulation time 241663608 ps
CPU time 0.93 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 206808 kb
Host smart-71d220b1-14bc-4712-962e-4ac01fe89ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44425
2024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.444252024
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.514020494
Short name T1813
Test name
Test status
Simulation time 3693354069 ps
CPU time 97.89 seconds
Started Jul 12 05:30:12 PM PDT 24
Finished Jul 12 05:31:57 PM PDT 24
Peak memory 207052 kb
Host smart-4175320a-1e28-4156-bacd-684b1d344bd3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=514020494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.514020494
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1150067385
Short name T1864
Test name
Test status
Simulation time 184094332 ps
CPU time 0.8 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:25 PM PDT 24
Peak memory 206812 kb
Host smart-cfb67e00-0d5d-4874-874a-61595652f91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11500
67385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1150067385
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1964194520
Short name T1897
Test name
Test status
Simulation time 165562544 ps
CPU time 0.8 seconds
Started Jul 12 05:29:47 PM PDT 24
Finished Jul 12 05:29:51 PM PDT 24
Peak memory 206768 kb
Host smart-eef78dfa-9411-4620-86c7-a8596ebff902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19641
94520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1964194520
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1191752069
Short name T816
Test name
Test status
Simulation time 566764309 ps
CPU time 1.35 seconds
Started Jul 12 05:29:48 PM PDT 24
Finished Jul 12 05:29:52 PM PDT 24
Peak memory 206812 kb
Host smart-34da25ba-91eb-4446-a4dc-d461175dfd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11917
52069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1191752069
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3323014126
Short name T1350
Test name
Test status
Simulation time 7234908305 ps
CPU time 51.2 seconds
Started Jul 12 05:29:51 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 206904 kb
Host smart-7c1830bb-222d-4453-b7bd-5f3e43e90796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33230
14126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3323014126
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.2757239597
Short name T808
Test name
Test status
Simulation time 201135192 ps
CPU time 0.79 seconds
Started Jul 12 05:29:49 PM PDT 24
Finished Jul 12 05:29:53 PM PDT 24
Peak memory 206812 kb
Host smart-59b4a132-da96-4926-85af-af4ea972c74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27572
39597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_host_handshake.2757239597
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2261734072
Short name T2002
Test name
Test status
Simulation time 37467717 ps
CPU time 0.69 seconds
Started Jul 12 05:30:02 PM PDT 24
Finished Jul 12 05:30:06 PM PDT 24
Peak memory 206860 kb
Host smart-fce9c65d-d001-48e0-898b-81cd13091700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2261734072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2261734072
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2965912074
Short name T917
Test name
Test status
Simulation time 3770827418 ps
CPU time 5.25 seconds
Started Jul 12 05:29:54 PM PDT 24
Finished Jul 12 05:30:02 PM PDT 24
Peak memory 206700 kb
Host smart-15ce8fc8-0f81-40fd-be62-ab9f7461105a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2965912074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2965912074
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2534217410
Short name T9
Test name
Test status
Simulation time 13326293959 ps
CPU time 14.3 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:30:12 PM PDT 24
Peak memory 206840 kb
Host smart-da93009a-f15a-49c7-9252-8e710da4367b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2534217410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2534217410
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.4026870428
Short name T214
Test name
Test status
Simulation time 23400107912 ps
CPU time 26.63 seconds
Started Jul 12 05:29:54 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 207084 kb
Host smart-5634a3fb-5410-4599-8afb-be586ad52b08
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4026870428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.4026870428
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2972623681
Short name T573
Test name
Test status
Simulation time 155616541 ps
CPU time 0.78 seconds
Started Jul 12 05:29:50 PM PDT 24
Finished Jul 12 05:29:54 PM PDT 24
Peak memory 206692 kb
Host smart-f967385e-4d56-4181-a493-a46a2af93195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29726
23681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2972623681
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.1344814503
Short name T2152
Test name
Test status
Simulation time 144196819 ps
CPU time 0.78 seconds
Started Jul 12 05:29:50 PM PDT 24
Finished Jul 12 05:29:54 PM PDT 24
Peak memory 206720 kb
Host smart-78ba452d-83f4-42e5-a93c-b73731987d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13448
14503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.1344814503
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.3325108396
Short name T1033
Test name
Test status
Simulation time 164556556 ps
CPU time 0.83 seconds
Started Jul 12 05:29:58 PM PDT 24
Finished Jul 12 05:30:02 PM PDT 24
Peak memory 206836 kb
Host smart-473033de-8626-4179-bf55-9f16552a8188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33251
08396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.3325108396
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_device_address.177921983
Short name T987
Test name
Test status
Simulation time 13508279797 ps
CPU time 23.05 seconds
Started Jul 12 05:29:53 PM PDT 24
Finished Jul 12 05:30:19 PM PDT 24
Peak memory 206928 kb
Host smart-683230e2-8b00-40bc-9fc7-8c4fdab728d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17792
1983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.177921983
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3423259653
Short name T1113
Test name
Test status
Simulation time 414350198 ps
CPU time 1.21 seconds
Started Jul 12 05:30:08 PM PDT 24
Finished Jul 12 05:30:13 PM PDT 24
Peak memory 206824 kb
Host smart-ca61965b-ac4c-424f-be32-7d830c8ba6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34232
59653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3423259653
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2322297907
Short name T964
Test name
Test status
Simulation time 155022042 ps
CPU time 0.78 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:30:04 PM PDT 24
Peak memory 206792 kb
Host smart-34416448-df49-4444-bde7-2a49827f965c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23222
97907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2322297907
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.4017598874
Short name T2654
Test name
Test status
Simulation time 35156840 ps
CPU time 0.66 seconds
Started Jul 12 05:30:13 PM PDT 24
Finished Jul 12 05:30:21 PM PDT 24
Peak memory 206812 kb
Host smart-6305ed89-328e-4de7-bc01-2de249376b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175
98874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.4017598874
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2108009838
Short name T803
Test name
Test status
Simulation time 836141471 ps
CPU time 1.96 seconds
Started Jul 12 05:29:56 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 206864 kb
Host smart-44fe4083-33cc-4cb4-adac-47d4be97b737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21080
09838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2108009838
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.866666890
Short name T2503
Test name
Test status
Simulation time 159545483 ps
CPU time 1.32 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:30:00 PM PDT 24
Peak memory 206952 kb
Host smart-05bc7f98-2e80-438b-b8e3-629a375ba85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86666
6890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.866666890
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.4018488685
Short name T338
Test name
Test status
Simulation time 218339465 ps
CPU time 0.95 seconds
Started Jul 12 05:30:03 PM PDT 24
Finished Jul 12 05:30:07 PM PDT 24
Peak memory 206836 kb
Host smart-c547a544-7aa9-4074-ba37-443245764d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40184
88685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.4018488685
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.972626527
Short name T385
Test name
Test status
Simulation time 150453693 ps
CPU time 0.81 seconds
Started Jul 12 05:30:12 PM PDT 24
Finished Jul 12 05:30:20 PM PDT 24
Peak memory 206804 kb
Host smart-f74bf254-bf09-4f2c-9704-05a93b3ef8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97262
6527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.972626527
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.4138734602
Short name T2727
Test name
Test status
Simulation time 203037218 ps
CPU time 0.88 seconds
Started Jul 12 05:30:00 PM PDT 24
Finished Jul 12 05:30:04 PM PDT 24
Peak memory 206696 kb
Host smart-ae1607c0-9787-4f26-9313-cd26132f4d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41387
34602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.4138734602
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.1352294599
Short name T1819
Test name
Test status
Simulation time 6840709938 ps
CPU time 70.16 seconds
Started Jul 12 05:30:13 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 207008 kb
Host smart-701f5342-10ba-42dc-a3d6-511f4d50c9c4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1352294599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1352294599
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.3139860440
Short name T1539
Test name
Test status
Simulation time 10652598967 ps
CPU time 31.94 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:30:48 PM PDT 24
Peak memory 207084 kb
Host smart-f2ec105d-ab58-4098-b811-f6c2c0eefae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31398
60440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.3139860440
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1721858148
Short name T733
Test name
Test status
Simulation time 287653925 ps
CPU time 0.96 seconds
Started Jul 12 05:30:31 PM PDT 24
Finished Jul 12 05:30:38 PM PDT 24
Peak memory 206808 kb
Host smart-5213a239-6088-47e0-b63d-4e84cd77afef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17218
58148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1721858148
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.706022481
Short name T1724
Test name
Test status
Simulation time 23355703191 ps
CPU time 21.1 seconds
Started Jul 12 05:30:10 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206876 kb
Host smart-b9c75b02-ede5-4577-9db5-1f6220fbe910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70602
2481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.706022481
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2169132598
Short name T2072
Test name
Test status
Simulation time 3333120744 ps
CPU time 4.02 seconds
Started Jul 12 05:30:08 PM PDT 24
Finished Jul 12 05:30:16 PM PDT 24
Peak memory 206888 kb
Host smart-de460259-467e-46ad-8d2d-c4d4582656d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21691
32598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2169132598
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1991296953
Short name T404
Test name
Test status
Simulation time 10213052864 ps
CPU time 101.66 seconds
Started Jul 12 05:29:53 PM PDT 24
Finished Jul 12 05:31:37 PM PDT 24
Peak memory 207036 kb
Host smart-760d5fc0-2bc5-4f43-baf5-298aa1b2be24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19912
96953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1991296953
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2734091246
Short name T1890
Test name
Test status
Simulation time 5660386459 ps
CPU time 159.31 seconds
Started Jul 12 05:30:08 PM PDT 24
Finished Jul 12 05:32:49 PM PDT 24
Peak memory 207228 kb
Host smart-799e7154-f614-4c86-b2b2-09c4126e9128
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2734091246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2734091246
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1911747900
Short name T881
Test name
Test status
Simulation time 259778169 ps
CPU time 0.94 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:02 PM PDT 24
Peak memory 206692 kb
Host smart-d8070cb9-62f4-4527-bd4b-6c3e88a1ec90
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1911747900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1911747900
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2006871158
Short name T1679
Test name
Test status
Simulation time 217033889 ps
CPU time 1.01 seconds
Started Jul 12 05:30:07 PM PDT 24
Finished Jul 12 05:30:10 PM PDT 24
Peak memory 206820 kb
Host smart-40b0ccf5-67b1-4ad3-bd7f-2502ceaeac96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
71158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2006871158
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1192311869
Short name T685
Test name
Test status
Simulation time 3707355728 ps
CPU time 98.93 seconds
Started Jul 12 05:30:07 PM PDT 24
Finished Jul 12 05:31:48 PM PDT 24
Peak memory 207064 kb
Host smart-c56815e7-54bd-4af1-ab52-94ad9f621f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11923
11869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1192311869
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1043311426
Short name T1648
Test name
Test status
Simulation time 3346214636 ps
CPU time 91.9 seconds
Started Jul 12 05:30:00 PM PDT 24
Finished Jul 12 05:31:35 PM PDT 24
Peak memory 207028 kb
Host smart-b81ed0ce-abaa-4e92-994e-e8a304f91e78
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1043311426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1043311426
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.721078925
Short name T458
Test name
Test status
Simulation time 205194567 ps
CPU time 0.97 seconds
Started Jul 12 05:29:56 PM PDT 24
Finished Jul 12 05:30:00 PM PDT 24
Peak memory 206796 kb
Host smart-c2deecfd-0890-42e3-b7fc-907cb019dbb7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=721078925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.721078925
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2425260310
Short name T1626
Test name
Test status
Simulation time 147939570 ps
CPU time 0.84 seconds
Started Jul 12 05:30:04 PM PDT 24
Finished Jul 12 05:30:07 PM PDT 24
Peak memory 206536 kb
Host smart-bcf7f5da-ec06-4d54-982b-44509f94a4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24252
60310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2425260310
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2304784043
Short name T1589
Test name
Test status
Simulation time 184651449 ps
CPU time 0.89 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 206808 kb
Host smart-7d286465-836a-4eb6-b548-2d921fae99b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23047
84043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2304784043
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3174206382
Short name T1766
Test name
Test status
Simulation time 198337634 ps
CPU time 0.83 seconds
Started Jul 12 05:29:54 PM PDT 24
Finished Jul 12 05:29:58 PM PDT 24
Peak memory 206768 kb
Host smart-1764d94b-f271-456b-bce4-ee0ac119d098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31742
06382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3174206382
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1648633748
Short name T2537
Test name
Test status
Simulation time 245718234 ps
CPU time 0.92 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:29:59 PM PDT 24
Peak memory 206820 kb
Host smart-44d52abf-fa5e-49c9-b909-67d7a0ca642a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16486
33748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1648633748
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2593068843
Short name T1111
Test name
Test status
Simulation time 150514701 ps
CPU time 0.77 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:29:59 PM PDT 24
Peak memory 206820 kb
Host smart-278ba9ef-028f-4b8b-8d03-c63ff6708823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25930
68843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2593068843
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.825598969
Short name T367
Test name
Test status
Simulation time 205616195 ps
CPU time 0.87 seconds
Started Jul 12 05:29:55 PM PDT 24
Finished Jul 12 05:30:00 PM PDT 24
Peak memory 206720 kb
Host smart-4d357339-d937-41c9-8e00-1dee6be45857
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=825598969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.825598969
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.634684436
Short name T188
Test name
Test status
Simulation time 164650457 ps
CPU time 0.79 seconds
Started Jul 12 05:29:56 PM PDT 24
Finished Jul 12 05:30:00 PM PDT 24
Peak memory 206796 kb
Host smart-9b1a75d2-859d-4aa5-9287-6fb2e67c4b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63468
4436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.634684436
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2954357862
Short name T1869
Test name
Test status
Simulation time 53348928 ps
CPU time 0.67 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:01 PM PDT 24
Peak memory 206816 kb
Host smart-05a1249a-cc1a-4ab9-9051-14071113bd98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29543
57862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2954357862
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.285386482
Short name T1845
Test name
Test status
Simulation time 21157518080 ps
CPU time 47.49 seconds
Started Jul 12 05:29:57 PM PDT 24
Finished Jul 12 05:30:48 PM PDT 24
Peak memory 207164 kb
Host smart-9e6e34ed-5f42-44fc-b6b0-508ac685b25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28538
6482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.285386482
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2467730168
Short name T2109
Test name
Test status
Simulation time 180059846 ps
CPU time 0.84 seconds
Started Jul 12 05:29:58 PM PDT 24
Finished Jul 12 05:30:02 PM PDT 24
Peak memory 206820 kb
Host smart-ba1e76a2-7046-48fe-9540-a443eed0f184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
30168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2467730168
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.64945584
Short name T2577
Test name
Test status
Simulation time 191904155 ps
CPU time 0.82 seconds
Started Jul 12 05:30:13 PM PDT 24
Finished Jul 12 05:30:22 PM PDT 24
Peak memory 206816 kb
Host smart-74e67915-35d6-45d2-a9cf-cbf66548798c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64945
584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.64945584
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.2091948974
Short name T329
Test name
Test status
Simulation time 272147727 ps
CPU time 0.96 seconds
Started Jul 12 05:29:58 PM PDT 24
Finished Jul 12 05:30:03 PM PDT 24
Peak memory 206836 kb
Host smart-4dd2658a-08dc-4605-810d-e0e3e25c38b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20919
48974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.2091948974
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.377582809
Short name T1595
Test name
Test status
Simulation time 194349826 ps
CPU time 0.86 seconds
Started Jul 12 05:29:59 PM PDT 24
Finished Jul 12 05:30:03 PM PDT 24
Peak memory 206808 kb
Host smart-d4db72b3-2cb4-454c-aec3-0716206b2ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37758
2809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.377582809
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1039098138
Short name T42
Test name
Test status
Simulation time 145761911 ps
CPU time 0.78 seconds
Started Jul 12 05:30:10 PM PDT 24
Finished Jul 12 05:30:16 PM PDT 24
Peak memory 206808 kb
Host smart-71c74e3d-305e-4b99-aceb-e486eff7657d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10390
98138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1039098138
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.497157845
Short name T1127
Test name
Test status
Simulation time 193598619 ps
CPU time 0.86 seconds
Started Jul 12 05:30:10 PM PDT 24
Finished Jul 12 05:30:16 PM PDT 24
Peak memory 206808 kb
Host smart-059ebae2-d12f-483d-aed8-9ccfae85b68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49715
7845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.497157845
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1971665700
Short name T2034
Test name
Test status
Simulation time 163551546 ps
CPU time 0.78 seconds
Started Jul 12 05:30:10 PM PDT 24
Finished Jul 12 05:30:15 PM PDT 24
Peak memory 206812 kb
Host smart-83f5d9af-fb8a-4a71-bd93-44cf85acc828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19716
65700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1971665700
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.4076200333
Short name T1904
Test name
Test status
Simulation time 208602055 ps
CPU time 0.92 seconds
Started Jul 12 05:30:07 PM PDT 24
Finished Jul 12 05:30:10 PM PDT 24
Peak memory 206812 kb
Host smart-12037c0d-25c2-48a2-93e0-effa661261b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40762
00333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.4076200333
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2088086691
Short name T1586
Test name
Test status
Simulation time 5680368089 ps
CPU time 162.57 seconds
Started Jul 12 05:30:05 PM PDT 24
Finished Jul 12 05:32:49 PM PDT 24
Peak memory 206988 kb
Host smart-6e90d413-a3aa-4d76-81e3-03a9b4de3942
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2088086691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2088086691
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.560834297
Short name T2473
Test name
Test status
Simulation time 169926327 ps
CPU time 0.84 seconds
Started Jul 12 05:30:04 PM PDT 24
Finished Jul 12 05:30:07 PM PDT 24
Peak memory 206560 kb
Host smart-05a6abaf-de8e-4adc-ba2a-744ef0b639fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56083
4297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.560834297
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2957413860
Short name T2356
Test name
Test status
Simulation time 174578315 ps
CPU time 0.79 seconds
Started Jul 12 05:30:08 PM PDT 24
Finished Jul 12 05:30:12 PM PDT 24
Peak memory 206820 kb
Host smart-f89ecaa7-c626-4912-b9a7-b89c076f9979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29574
13860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2957413860
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2056219557
Short name T2425
Test name
Test status
Simulation time 848139898 ps
CPU time 1.93 seconds
Started Jul 12 05:30:02 PM PDT 24
Finished Jul 12 05:30:08 PM PDT 24
Peak memory 207008 kb
Host smart-5c408243-b30b-4fc9-adc9-0cefe8e59eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20562
19557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2056219557
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1034032240
Short name T1274
Test name
Test status
Simulation time 5974819443 ps
CPU time 56.54 seconds
Started Jul 12 05:29:58 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 207084 kb
Host smart-1fad08b3-ad90-485d-877b-93034f03054d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340
32240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1034032240
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.561237746
Short name T1433
Test name
Test status
Simulation time 68984493 ps
CPU time 0.72 seconds
Started Jul 12 05:30:09 PM PDT 24
Finished Jul 12 05:30:14 PM PDT 24
Peak memory 206672 kb
Host smart-cc22ab10-e08d-4452-8b24-dfb088694c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=561237746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.561237746
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3536425183
Short name T1378
Test name
Test status
Simulation time 4261364193 ps
CPU time 4.72 seconds
Started Jul 12 05:29:56 PM PDT 24
Finished Jul 12 05:30:04 PM PDT 24
Peak memory 207024 kb
Host smart-16eefc61-5d7c-42af-b263-5a205a49b03e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3536425183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3536425183
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2392856774
Short name T649
Test name
Test status
Simulation time 13381577105 ps
CPU time 11.76 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 207056 kb
Host smart-14489717-0f4f-422d-9444-5927e9892f4f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2392856774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2392856774
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.761160663
Short name T2512
Test name
Test status
Simulation time 23442416038 ps
CPU time 24.22 seconds
Started Jul 12 05:30:14 PM PDT 24
Finished Jul 12 05:30:46 PM PDT 24
Peak memory 207084 kb
Host smart-f2e74393-2df8-4ab4-8b8a-0d5ec679d10b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=761160663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.761160663
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.4160026083
Short name T2184
Test name
Test status
Simulation time 221454027 ps
CPU time 0.9 seconds
Started Jul 12 05:30:00 PM PDT 24
Finished Jul 12 05:30:05 PM PDT 24
Peak memory 206716 kb
Host smart-0f43bfe3-e5ae-419b-b235-578740db237d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41600
26083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.4160026083
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.4266242150
Short name T2436
Test name
Test status
Simulation time 148544882 ps
CPU time 0.77 seconds
Started Jul 12 05:30:14 PM PDT 24
Finished Jul 12 05:30:23 PM PDT 24
Peak memory 206828 kb
Host smart-090eacba-0333-4ce3-951f-7cd778749fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42662
42150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.4266242150
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2603883687
Short name T2596
Test name
Test status
Simulation time 507026111 ps
CPU time 1.67 seconds
Started Jul 12 05:30:06 PM PDT 24
Finished Jul 12 05:30:10 PM PDT 24
Peak memory 206824 kb
Host smart-103ba02c-2111-4198-b4b3-735f5f21d32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26038
83687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2603883687
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1340604327
Short name T574
Test name
Test status
Simulation time 374223159 ps
CPU time 1.07 seconds
Started Jul 12 05:30:03 PM PDT 24
Finished Jul 12 05:30:07 PM PDT 24
Peak memory 206812 kb
Host smart-9208fc09-5ccc-4103-973e-9c69dbc640f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406
04327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1340604327
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2139129010
Short name T2468
Test name
Test status
Simulation time 6147772010 ps
CPU time 12.5 seconds
Started Jul 12 05:30:12 PM PDT 24
Finished Jul 12 05:30:32 PM PDT 24
Peak memory 207080 kb
Host smart-32849bb1-223c-468e-81d2-69beccf277e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21391
29010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2139129010
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.930248433
Short name T470
Test name
Test status
Simulation time 315403385 ps
CPU time 1.17 seconds
Started Jul 12 05:30:13 PM PDT 24
Finished Jul 12 05:30:22 PM PDT 24
Peak memory 206808 kb
Host smart-3047cc49-db2c-4e8b-ba9c-e5bd0c5f20f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93024
8433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.930248433
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.418153550
Short name T1191
Test name
Test status
Simulation time 156204040 ps
CPU time 0.76 seconds
Started Jul 12 05:30:09 PM PDT 24
Finished Jul 12 05:30:14 PM PDT 24
Peak memory 206820 kb
Host smart-1e0c54f9-72f5-4e2b-b2bf-fa077d248c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41815
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.418153550
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1656134065
Short name T335
Test name
Test status
Simulation time 55062183 ps
CPU time 0.72 seconds
Started Jul 12 05:30:13 PM PDT 24
Finished Jul 12 05:30:21 PM PDT 24
Peak memory 206828 kb
Host smart-5f17dcb1-8e13-49a7-a504-9b4fe2199c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
34065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1656134065
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2364140001
Short name T2296
Test name
Test status
Simulation time 777473102 ps
CPU time 1.94 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 207008 kb
Host smart-ebe98295-4cd8-4174-95fb-2ef01ceaa39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23641
40001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2364140001
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1009024504
Short name T2320
Test name
Test status
Simulation time 158872465 ps
CPU time 1.12 seconds
Started Jul 12 05:30:09 PM PDT 24
Finished Jul 12 05:30:15 PM PDT 24
Peak memory 207028 kb
Host smart-270873e4-5b4c-449c-a0ec-ecc49ec20c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10090
24504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1009024504
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3585672582
Short name T986
Test name
Test status
Simulation time 158872211 ps
CPU time 0.81 seconds
Started Jul 12 05:30:01 PM PDT 24
Finished Jul 12 05:30:05 PM PDT 24
Peak memory 206712 kb
Host smart-e03ce637-cfe2-424c-90d2-a7ce2bcbac43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856
72582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3585672582
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.288004849
Short name T352
Test name
Test status
Simulation time 201107285 ps
CPU time 0.85 seconds
Started Jul 12 05:29:59 PM PDT 24
Finished Jul 12 05:30:03 PM PDT 24
Peak memory 206804 kb
Host smart-e58a45f3-b572-456b-8a66-edd6c05ad856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28800
4849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.288004849
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1166363117
Short name T2715
Test name
Test status
Simulation time 187338618 ps
CPU time 0.87 seconds
Started Jul 12 05:29:59 PM PDT 24
Finished Jul 12 05:30:03 PM PDT 24
Peak memory 206760 kb
Host smart-61d18055-86c0-49b0-a86f-0675fd458f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11663
63117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1166363117
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.172486818
Short name T497
Test name
Test status
Simulation time 7738760108 ps
CPU time 23.2 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:46 PM PDT 24
Peak memory 207036 kb
Host smart-7e95b8ce-9b0f-4fe5-ac33-7a3a3726fa2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
6818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.172486818
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3905846070
Short name T831
Test name
Test status
Simulation time 291423729 ps
CPU time 1 seconds
Started Jul 12 05:29:59 PM PDT 24
Finished Jul 12 05:30:03 PM PDT 24
Peak memory 206688 kb
Host smart-195c124d-f019-49d5-81ff-bc3d00df0e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058
46070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3905846070
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.894970168
Short name T2354
Test name
Test status
Simulation time 23344185475 ps
CPU time 27.2 seconds
Started Jul 12 05:30:08 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206880 kb
Host smart-aae2fac2-3372-470c-8f19-27066a61a52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89497
0168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.894970168
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.383629886
Short name T623
Test name
Test status
Simulation time 3332446210 ps
CPU time 4.41 seconds
Started Jul 12 05:30:02 PM PDT 24
Finished Jul 12 05:30:09 PM PDT 24
Peak memory 206884 kb
Host smart-0253928f-ebc4-4732-a45e-eaf47672b9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38362
9886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.383629886
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.535338422
Short name T1258
Test name
Test status
Simulation time 10150010679 ps
CPU time 78.5 seconds
Started Jul 12 05:30:03 PM PDT 24
Finished Jul 12 05:31:24 PM PDT 24
Peak memory 206996 kb
Host smart-37337a32-479f-4f0d-946e-f5d887bcb8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53533
8422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.535338422
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1765356813
Short name T1106
Test name
Test status
Simulation time 4601261243 ps
CPU time 42.97 seconds
Started Jul 12 05:30:02 PM PDT 24
Finished Jul 12 05:30:48 PM PDT 24
Peak memory 207068 kb
Host smart-a3fb2c2b-cae1-4173-bd30-f6e227c2e59d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1765356813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1765356813
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.209658150
Short name T1219
Test name
Test status
Simulation time 283266180 ps
CPU time 0.94 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:26 PM PDT 24
Peak memory 206792 kb
Host smart-3ea81988-9d3d-4298-8c4d-c671a2bec218
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=209658150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.209658150
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.824360881
Short name T1712
Test name
Test status
Simulation time 183177682 ps
CPU time 0.83 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206824 kb
Host smart-07fd7c30-5391-4d25-876f-26ed7e102966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82436
0881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.824360881
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.860304967
Short name T719
Test name
Test status
Simulation time 5231858363 ps
CPU time 145.29 seconds
Started Jul 12 05:30:05 PM PDT 24
Finished Jul 12 05:32:32 PM PDT 24
Peak memory 206932 kb
Host smart-732b7ed7-df1f-448d-ba1a-170d4e23f444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86030
4967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.860304967
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.226561871
Short name T1585
Test name
Test status
Simulation time 5750123289 ps
CPU time 149.78 seconds
Started Jul 12 05:30:08 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 206872 kb
Host smart-8a19408b-7501-42b9-a483-b2f48a398e34
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=226561871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.226561871
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3811614891
Short name T1678
Test name
Test status
Simulation time 151695759 ps
CPU time 0.79 seconds
Started Jul 12 05:30:08 PM PDT 24
Finished Jul 12 05:30:12 PM PDT 24
Peak memory 206820 kb
Host smart-353b3f7f-c9f3-49a5-8ff7-8d9f82aaf8e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3811614891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3811614891
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2551361694
Short name T1775
Test name
Test status
Simulation time 144233797 ps
CPU time 0.82 seconds
Started Jul 12 05:30:03 PM PDT 24
Finished Jul 12 05:30:06 PM PDT 24
Peak memory 206804 kb
Host smart-56a12f4d-c5d9-4c01-8b18-a6a695f7c010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25513
61694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2551361694
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.108787799
Short name T2074
Test name
Test status
Simulation time 195319134 ps
CPU time 0.87 seconds
Started Jul 12 05:30:07 PM PDT 24
Finished Jul 12 05:30:10 PM PDT 24
Peak memory 206664 kb
Host smart-770a2eae-8762-4221-a612-dd5099799407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10878
7799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.108787799
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.340135999
Short name T2674
Test name
Test status
Simulation time 193219437 ps
CPU time 0.91 seconds
Started Jul 12 05:30:01 PM PDT 24
Finished Jul 12 05:30:05 PM PDT 24
Peak memory 206828 kb
Host smart-c03122c2-334f-4fe8-875d-3f7468e98824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34013
5999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.340135999
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.4278111493
Short name T661
Test name
Test status
Simulation time 185089501 ps
CPU time 0.85 seconds
Started Jul 12 05:30:07 PM PDT 24
Finished Jul 12 05:30:11 PM PDT 24
Peak memory 206768 kb
Host smart-0bd7f521-9793-42fb-af77-8190719a4817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42781
11493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.4278111493
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2611695164
Short name T1341
Test name
Test status
Simulation time 226395642 ps
CPU time 0.87 seconds
Started Jul 12 05:30:07 PM PDT 24
Finished Jul 12 05:30:11 PM PDT 24
Peak memory 206740 kb
Host smart-817b3165-95a9-4442-9b2c-e76138b05db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
95164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2611695164
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3167743623
Short name T766
Test name
Test status
Simulation time 152758291 ps
CPU time 0.8 seconds
Started Jul 12 05:30:06 PM PDT 24
Finished Jul 12 05:30:09 PM PDT 24
Peak memory 206816 kb
Host smart-2c3540e2-e89c-4961-95b8-bdf5a11f66a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31677
43623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3167743623
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3890536712
Short name T1227
Test name
Test status
Simulation time 239772923 ps
CPU time 0.96 seconds
Started Jul 12 05:30:07 PM PDT 24
Finished Jul 12 05:30:11 PM PDT 24
Peak memory 206720 kb
Host smart-d8f459be-5eb6-4b31-a657-866a5bb02439
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3890536712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3890536712
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.655819318
Short name T513
Test name
Test status
Simulation time 189063219 ps
CPU time 0.89 seconds
Started Jul 12 05:30:13 PM PDT 24
Finished Jul 12 05:30:21 PM PDT 24
Peak memory 206816 kb
Host smart-f91bd527-48f8-44ce-a309-00793f7946d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65581
9318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.655819318
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.885595457
Short name T1492
Test name
Test status
Simulation time 65263339 ps
CPU time 0.73 seconds
Started Jul 12 05:30:18 PM PDT 24
Finished Jul 12 05:30:28 PM PDT 24
Peak memory 206816 kb
Host smart-0a79d739-ad63-4a22-8bfc-7fcc029591ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88559
5457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.885595457
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2968864209
Short name T253
Test name
Test status
Simulation time 18894290642 ps
CPU time 40.36 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:31:05 PM PDT 24
Peak memory 207044 kb
Host smart-a8beb6de-d871-4744-b71f-887e3d1dc69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29688
64209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2968864209
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3764288454
Short name T2515
Test name
Test status
Simulation time 196729335 ps
CPU time 0.89 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206820 kb
Host smart-eaa24d2b-6b8d-4506-bc2d-932848faf71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37642
88454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3764288454
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1140634341
Short name T1142
Test name
Test status
Simulation time 232861107 ps
CPU time 0.92 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:26 PM PDT 24
Peak memory 206804 kb
Host smart-0be1c2ef-b451-4fdd-951d-fd9073e2e64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11406
34341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1140634341
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3931227376
Short name T526
Test name
Test status
Simulation time 201526986 ps
CPU time 0.89 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 206832 kb
Host smart-3c20e2ae-eba6-43b6-9d32-ee414d203476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39312
27376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3931227376
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2944291760
Short name T1104
Test name
Test status
Simulation time 159794401 ps
CPU time 0.82 seconds
Started Jul 12 05:30:14 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206824 kb
Host smart-b5a5873f-3f53-4d88-ae89-5f022fd12bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
91760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2944291760
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.320600004
Short name T1482
Test name
Test status
Simulation time 166816667 ps
CPU time 0.87 seconds
Started Jul 12 05:30:14 PM PDT 24
Finished Jul 12 05:30:23 PM PDT 24
Peak memory 206804 kb
Host smart-ca05c4a7-b60d-46ee-abe4-0e72a51ee136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32060
0004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.320600004
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3106845651
Short name T2505
Test name
Test status
Simulation time 161708993 ps
CPU time 0.78 seconds
Started Jul 12 05:30:09 PM PDT 24
Finished Jul 12 05:30:14 PM PDT 24
Peak memory 206788 kb
Host smart-44852a45-192e-4cc1-8578-5fdfe8db727e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
45651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3106845651
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3192880252
Short name T444
Test name
Test status
Simulation time 168909220 ps
CPU time 0.8 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206808 kb
Host smart-5e5a87cc-29d4-4879-a3b3-95179e263750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31928
80252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3192880252
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1328317734
Short name T1784
Test name
Test status
Simulation time 248207927 ps
CPU time 0.98 seconds
Started Jul 12 05:30:09 PM PDT 24
Finished Jul 12 05:30:14 PM PDT 24
Peak memory 206812 kb
Host smart-083f76dd-fe18-4479-b668-0a549f5610fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13283
17734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1328317734
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.2130213322
Short name T144
Test name
Test status
Simulation time 3248165424 ps
CPU time 30.75 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206928 kb
Host smart-3fad3590-2623-406c-a0c4-16eb4cbd86b3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2130213322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.2130213322
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3791820018
Short name T2614
Test name
Test status
Simulation time 183971755 ps
CPU time 0.91 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 206796 kb
Host smart-7337ba7d-6456-48e9-b68f-edc83e943566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37918
20018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3791820018
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.976065505
Short name T2372
Test name
Test status
Simulation time 152348895 ps
CPU time 0.8 seconds
Started Jul 12 05:30:12 PM PDT 24
Finished Jul 12 05:30:20 PM PDT 24
Peak memory 206816 kb
Host smart-9e49cb62-cc9e-45f2-8126-2934fe45db33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97606
5505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.976065505
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1205982864
Short name T1917
Test name
Test status
Simulation time 822272979 ps
CPU time 1.97 seconds
Started Jul 12 05:30:12 PM PDT 24
Finished Jul 12 05:30:21 PM PDT 24
Peak memory 206976 kb
Host smart-99bfbc39-54c3-4a6e-a203-e6db1ec5a23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059
82864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1205982864
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2580905840
Short name T1259
Test name
Test status
Simulation time 6663280024 ps
CPU time 190.16 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:33:34 PM PDT 24
Peak memory 206996 kb
Host smart-984710a8-4f41-4e7c-ab39-d8ba8a5cb02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25809
05840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2580905840
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.4233448655
Short name T1980
Test name
Test status
Simulation time 41752636 ps
CPU time 0.72 seconds
Started Jul 12 05:30:20 PM PDT 24
Finished Jul 12 05:30:30 PM PDT 24
Peak memory 206712 kb
Host smart-f107402d-2d9e-44cb-9596-b0ca03fb432a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4233448655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.4233448655
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3105124672
Short name T1946
Test name
Test status
Simulation time 4149203695 ps
CPU time 5.79 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:30:22 PM PDT 24
Peak memory 206784 kb
Host smart-9d435e09-14dd-4a85-a806-97b8d4cd6885
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3105124672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.3105124672
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.510671979
Short name T2466
Test name
Test status
Simulation time 13366447175 ps
CPU time 13.18 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 206856 kb
Host smart-82185f51-f198-4393-88af-529e74c0847b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=510671979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.510671979
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.926650042
Short name T2649
Test name
Test status
Simulation time 23348623183 ps
CPU time 23.51 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:48 PM PDT 24
Peak memory 206768 kb
Host smart-97ef7a95-5e8e-468c-a9aa-60291c154e48
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=926650042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.926650042
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2168351451
Short name T1891
Test name
Test status
Simulation time 199216535 ps
CPU time 0.81 seconds
Started Jul 12 05:30:12 PM PDT 24
Finished Jul 12 05:30:18 PM PDT 24
Peak memory 206828 kb
Host smart-15698d67-b453-4e08-876e-f36a953791cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21683
51451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2168351451
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3123764176
Short name T1535
Test name
Test status
Simulation time 178458402 ps
CPU time 0.77 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206808 kb
Host smart-ee84b8a1-489b-4913-a5dc-acd7fbdc7e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31237
64176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3123764176
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2863563645
Short name T1544
Test name
Test status
Simulation time 568210812 ps
CPU time 1.6 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 206860 kb
Host smart-ba26f998-6a4c-4e7a-a438-377a2246221e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28635
63645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2863563645
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2594843119
Short name T2524
Test name
Test status
Simulation time 1131362080 ps
CPU time 2.72 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 207008 kb
Host smart-379f6faa-4756-45a5-8637-337afb7bbfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25948
43119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2594843119
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.834937129
Short name T2664
Test name
Test status
Simulation time 9156542237 ps
CPU time 17.64 seconds
Started Jul 12 05:30:18 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 206924 kb
Host smart-6a1c1eb3-d216-45a5-9679-bacd8a7dbab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83493
7129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.834937129
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2361774924
Short name T1577
Test name
Test status
Simulation time 351712130 ps
CPU time 1.19 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:30:17 PM PDT 24
Peak memory 206700 kb
Host smart-7b9b15c5-c207-447c-9e21-f2aba1a69af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23617
74924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2361774924
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3385807291
Short name T26
Test name
Test status
Simulation time 150680596 ps
CPU time 0.81 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206660 kb
Host smart-981bdccb-a816-4d81-93d0-19b309327804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33858
07291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3385807291
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1192488961
Short name T1739
Test name
Test status
Simulation time 45333748 ps
CPU time 0.66 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206976 kb
Host smart-9bec94ac-e189-440d-8d4f-1e8e80313142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
88961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1192488961
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1759313058
Short name T2289
Test name
Test status
Simulation time 944710949 ps
CPU time 2.26 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 207040 kb
Host smart-f33f8d2f-2ee5-4c7e-aa90-112fd6df4c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17593
13058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1759313058
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2410708606
Short name T691
Test name
Test status
Simulation time 199515854 ps
CPU time 1.25 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:26 PM PDT 24
Peak memory 206792 kb
Host smart-c7ab426f-df8f-48ed-91d0-4bfb5d8b9b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
08606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2410708606
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3699714193
Short name T2458
Test name
Test status
Simulation time 201496992 ps
CPU time 0.85 seconds
Started Jul 12 05:30:10 PM PDT 24
Finished Jul 12 05:30:16 PM PDT 24
Peak memory 206672 kb
Host smart-03518536-4e7b-4da0-8e89-38f3c40e182b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36997
14193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3699714193
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1393116250
Short name T1178
Test name
Test status
Simulation time 142343361 ps
CPU time 0.81 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:30:17 PM PDT 24
Peak memory 206804 kb
Host smart-8d96df21-0415-4da1-a21b-52fb21e9465a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13931
16250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1393116250
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3431727577
Short name T846
Test name
Test status
Simulation time 219534454 ps
CPU time 0.91 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:30:28 PM PDT 24
Peak memory 206712 kb
Host smart-81dff8b4-11a0-44d1-b2dd-e1ec0d9eaf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34317
27577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3431727577
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3785536216
Short name T1131
Test name
Test status
Simulation time 179953471 ps
CPU time 0.83 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 206712 kb
Host smart-1df74ab6-9dfc-423c-81ee-4e48e7b2b6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37855
36216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3785536216
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1261661631
Short name T1408
Test name
Test status
Simulation time 23354044671 ps
CPU time 24.02 seconds
Started Jul 12 05:30:09 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206888 kb
Host smart-dedc709e-790c-4963-8425-7307cbc71a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12616
61631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1261661631
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1286281126
Short name T1346
Test name
Test status
Simulation time 3312854509 ps
CPU time 4.33 seconds
Started Jul 12 05:30:10 PM PDT 24
Finished Jul 12 05:30:20 PM PDT 24
Peak memory 206760 kb
Host smart-96fdbf1f-0237-46c7-8827-e66cca003307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12862
81126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1286281126
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.1008206731
Short name T1689
Test name
Test status
Simulation time 8957650555 ps
CPU time 250.81 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:34:38 PM PDT 24
Peak memory 207112 kb
Host smart-876f1de3-cae1-4a96-80a2-2bfa21b522d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10082
06731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.1008206731
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1650282449
Short name T1040
Test name
Test status
Simulation time 4509770485 ps
CPU time 123.22 seconds
Started Jul 12 05:30:09 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 206940 kb
Host smart-58502b82-c510-413a-85e8-845abe8a998c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1650282449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1650282449
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1956931383
Short name T1093
Test name
Test status
Simulation time 254648557 ps
CPU time 0.92 seconds
Started Jul 12 05:30:07 PM PDT 24
Finished Jul 12 05:30:10 PM PDT 24
Peak memory 206808 kb
Host smart-8c72f35a-d6a2-4a8f-9298-6061805d618e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1956931383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1956931383
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2064795158
Short name T673
Test name
Test status
Simulation time 189383313 ps
CPU time 0.87 seconds
Started Jul 12 05:30:12 PM PDT 24
Finished Jul 12 05:30:20 PM PDT 24
Peak memory 206836 kb
Host smart-7418d1f7-91b8-4cc6-ac48-1725cac6e3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20647
95158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2064795158
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.1226938849
Short name T1212
Test name
Test status
Simulation time 6085932185 ps
CPU time 56.29 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:31:12 PM PDT 24
Peak memory 207068 kb
Host smart-ed126020-46a7-44e2-8370-54c6e40fbc93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12269
38849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.1226938849
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2715624815
Short name T976
Test name
Test status
Simulation time 5540865808 ps
CPU time 154.86 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:32:53 PM PDT 24
Peak memory 207072 kb
Host smart-7128e48a-8dcc-40a4-bc5e-6afd89fc3e1a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2715624815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2715624815
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2627492085
Short name T1870
Test name
Test status
Simulation time 151704511 ps
CPU time 0.8 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:26 PM PDT 24
Peak memory 206700 kb
Host smart-6c7b7569-70cf-4985-9a16-00af3ca072ba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2627492085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2627492085
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1707566188
Short name T2422
Test name
Test status
Simulation time 174377481 ps
CPU time 0.84 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 206696 kb
Host smart-47113b75-bf81-42b2-9a47-d4d5a210b75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
66188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1707566188
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.4101047777
Short name T116
Test name
Test status
Simulation time 219145101 ps
CPU time 0.86 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:26 PM PDT 24
Peak memory 206832 kb
Host smart-5269b91f-e89d-44d6-867e-45ba73ca06b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41010
47777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.4101047777
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2628988227
Short name T416
Test name
Test status
Simulation time 226463021 ps
CPU time 0.95 seconds
Started Jul 12 05:30:18 PM PDT 24
Finished Jul 12 05:30:29 PM PDT 24
Peak memory 206816 kb
Host smart-69c221f9-bb30-4cfa-a586-a83810d74788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26289
88227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2628988227
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1858487581
Short name T1881
Test name
Test status
Simulation time 181096854 ps
CPU time 0.83 seconds
Started Jul 12 05:30:12 PM PDT 24
Finished Jul 12 05:30:20 PM PDT 24
Peak memory 206668 kb
Host smart-67c076e5-60bb-4d1f-bc45-da6ad1b95f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18584
87581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1858487581
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1799264756
Short name T1675
Test name
Test status
Simulation time 170069727 ps
CPU time 0.81 seconds
Started Jul 12 05:30:11 PM PDT 24
Finished Jul 12 05:30:17 PM PDT 24
Peak memory 206672 kb
Host smart-9000bdc7-0bbf-4d1e-bf30-730d95265671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17992
64756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1799264756
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.821513450
Short name T2163
Test name
Test status
Simulation time 145351333 ps
CPU time 0.77 seconds
Started Jul 12 05:30:10 PM PDT 24
Finished Jul 12 05:30:16 PM PDT 24
Peak memory 206776 kb
Host smart-c0eb989e-aeef-4c8e-b1eb-fca0619753f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82151
3450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.821513450
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.150695912
Short name T2
Test name
Test status
Simulation time 192569496 ps
CPU time 0.87 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:30:28 PM PDT 24
Peak memory 206820 kb
Host smart-0be8b0d2-c52e-4ac0-a6e5-c279e8e2dd0a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=150695912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.150695912
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.28416336
Short name T426
Test name
Test status
Simulation time 144772476 ps
CPU time 0.74 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206796 kb
Host smart-d5ac8411-17af-4c91-9047-a3a6d6ee4df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28416
336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.28416336
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2286391555
Short name T756
Test name
Test status
Simulation time 31540133 ps
CPU time 0.65 seconds
Started Jul 12 05:30:29 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206808 kb
Host smart-f01599a9-5f79-4f7a-8a52-6dcad4198bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22863
91555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2286391555
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3784099333
Short name T1915
Test name
Test status
Simulation time 9790402484 ps
CPU time 22.58 seconds
Started Jul 12 05:30:23 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 207052 kb
Host smart-c454cde9-8c4e-40c9-bf91-18c9671d6d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37840
99333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3784099333
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.597057182
Short name T290
Test name
Test status
Simulation time 181209529 ps
CPU time 0.9 seconds
Started Jul 12 05:30:18 PM PDT 24
Finished Jul 12 05:30:29 PM PDT 24
Peak memory 206836 kb
Host smart-11f1882b-bd6b-4575-8d9f-a48ef61e8679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59705
7182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.597057182
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2404345584
Short name T442
Test name
Test status
Simulation time 168701645 ps
CPU time 0.81 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 206800 kb
Host smart-4cc0c899-68bb-46d4-a4d5-69aa4fd65925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043
45584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2404345584
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2604223457
Short name T2568
Test name
Test status
Simulation time 288869540 ps
CPU time 0.92 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 206804 kb
Host smart-ea0b2858-c734-49a0-bcd1-af9580ba33d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26042
23457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2604223457
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2169317548
Short name T476
Test name
Test status
Simulation time 187205778 ps
CPU time 0.84 seconds
Started Jul 12 05:30:24 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 206840 kb
Host smart-03f4031f-1e3f-4ad6-b017-e56b9c5d6622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
17548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2169317548
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.65644386
Short name T800
Test name
Test status
Simulation time 162949511 ps
CPU time 0.77 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206816 kb
Host smart-2f1c37f1-ef00-479c-a09f-d4a2706a13cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65644
386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.65644386
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3954989992
Short name T908
Test name
Test status
Simulation time 155766571 ps
CPU time 0.79 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:26 PM PDT 24
Peak memory 206812 kb
Host smart-941c6f7d-8a86-4361-ae0b-9187f193c516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39549
89992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3954989992
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1558940141
Short name T2117
Test name
Test status
Simulation time 151853026 ps
CPU time 0.79 seconds
Started Jul 12 05:30:18 PM PDT 24
Finished Jul 12 05:30:29 PM PDT 24
Peak memory 206812 kb
Host smart-098074ad-99ae-4c49-8f3c-2c7271d67e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15589
40141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1558940141
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3294216983
Short name T440
Test name
Test status
Simulation time 247650915 ps
CPU time 0.96 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:30:28 PM PDT 24
Peak memory 206716 kb
Host smart-6f937825-2531-4aed-b9bc-adb85c3c8d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32942
16983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3294216983
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3067244010
Short name T486
Test name
Test status
Simulation time 3308277158 ps
CPU time 28.84 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 206896 kb
Host smart-f3713ac4-d3b3-49c7-8196-f0793398d37a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3067244010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3067244010
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3101241816
Short name T2333
Test name
Test status
Simulation time 184114372 ps
CPU time 0.79 seconds
Started Jul 12 05:30:19 PM PDT 24
Finished Jul 12 05:30:29 PM PDT 24
Peak memory 206704 kb
Host smart-9c10a729-c165-4edf-ace3-d9c3164682b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31012
41816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3101241816
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1753496170
Short name T386
Test name
Test status
Simulation time 166174421 ps
CPU time 0.81 seconds
Started Jul 12 05:30:19 PM PDT 24
Finished Jul 12 05:30:29 PM PDT 24
Peak memory 206804 kb
Host smart-47f46b3e-bc6f-40d0-aa65-68a1155d32e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17534
96170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1753496170
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3735832997
Short name T771
Test name
Test status
Simulation time 571350307 ps
CPU time 1.62 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:30:29 PM PDT 24
Peak memory 206820 kb
Host smart-e658aafd-59f7-41f0-9250-4b9644ae7727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37358
32997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3735832997
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2291844757
Short name T945
Test name
Test status
Simulation time 7998560977 ps
CPU time 78.6 seconds
Started Jul 12 05:30:22 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 206956 kb
Host smart-a57dd649-e4b3-420a-b0e3-2ac6a1363070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22918
44757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2291844757
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.3816981484
Short name T1838
Test name
Test status
Simulation time 49399957 ps
CPU time 0.71 seconds
Started Jul 12 05:30:30 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206844 kb
Host smart-bb9e8221-b862-47cf-abc5-57fea0d0b91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3816981484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.3816981484
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3262465558
Short name T1925
Test name
Test status
Simulation time 13326522467 ps
CPU time 13.01 seconds
Started Jul 12 05:30:18 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206864 kb
Host smart-1a026932-0f3e-4dc2-afb9-3c410296991b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3262465558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3262465558
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1596923846
Short name T445
Test name
Test status
Simulation time 23306865131 ps
CPU time 25.16 seconds
Started Jul 12 05:30:19 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 207028 kb
Host smart-7f4721ab-3d27-40cd-bbb5-294dd4cd55ef
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1596923846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.1596923846
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1110886452
Short name T478
Test name
Test status
Simulation time 158474790 ps
CPU time 0.87 seconds
Started Jul 12 05:30:23 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 206808 kb
Host smart-e70d8eeb-5fea-4956-9aba-ed64c87cb4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11108
86452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1110886452
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.4279374089
Short name T864
Test name
Test status
Simulation time 148113127 ps
CPU time 0.76 seconds
Started Jul 12 05:30:30 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206804 kb
Host smart-a9832ae1-25f4-4278-bc74-092d3a6a394d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42793
74089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.4279374089
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.245944865
Short name T1799
Test name
Test status
Simulation time 382389706 ps
CPU time 1.2 seconds
Started Jul 12 05:30:16 PM PDT 24
Finished Jul 12 05:30:27 PM PDT 24
Peak memory 206768 kb
Host smart-8ee019bd-0adf-4223-8cb4-4de70205d1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24594
4865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.245944865
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3149731792
Short name T398
Test name
Test status
Simulation time 730553908 ps
CPU time 1.81 seconds
Started Jul 12 05:30:19 PM PDT 24
Finished Jul 12 05:30:30 PM PDT 24
Peak memory 206860 kb
Host smart-7dc1e14b-ba58-4c75-b503-4e4c0cd6f854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31497
31792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3149731792
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1582489029
Short name T92
Test name
Test status
Simulation time 16485766061 ps
CPU time 30.74 seconds
Started Jul 12 05:30:20 PM PDT 24
Finished Jul 12 05:31:00 PM PDT 24
Peak memory 207036 kb
Host smart-ae5558d4-0bd0-41a6-ac14-c6f5ee64a6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15824
89029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1582489029
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.2926425907
Short name T2573
Test name
Test status
Simulation time 302498215 ps
CPU time 1.1 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206684 kb
Host smart-596e03bc-5a35-4606-b806-5515e2fd8c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29264
25907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.2926425907
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.239344323
Short name T2330
Test name
Test status
Simulation time 157936694 ps
CPU time 0.79 seconds
Started Jul 12 05:30:20 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 206820 kb
Host smart-96ede73c-f6f1-45b6-852f-b7d6e54688d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23934
4323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.239344323
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1039586219
Short name T1182
Test name
Test status
Simulation time 60383679 ps
CPU time 0.71 seconds
Started Jul 12 05:30:19 PM PDT 24
Finished Jul 12 05:30:30 PM PDT 24
Peak memory 206712 kb
Host smart-6a88a087-05db-4407-9c90-5dfb5a4d7092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10395
86219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1039586219
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.132015488
Short name T1815
Test name
Test status
Simulation time 943170599 ps
CPU time 2.14 seconds
Started Jul 12 05:30:23 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 206868 kb
Host smart-b23989bd-2ea8-4e2f-8e51-4979e41724ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13201
5488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.132015488
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2787789792
Short name T553
Test name
Test status
Simulation time 280298692 ps
CPU time 1.73 seconds
Started Jul 12 05:30:20 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 206976 kb
Host smart-2d91d9a7-566d-4759-9d29-8ef6375b52d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
89792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2787789792
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2013108202
Short name T678
Test name
Test status
Simulation time 257727228 ps
CPU time 0.95 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:25 PM PDT 24
Peak memory 206768 kb
Host smart-6b376363-9152-4f89-849b-2eb25d4aa48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131
08202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2013108202
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3743674033
Short name T483
Test name
Test status
Simulation time 149605211 ps
CPU time 0.77 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206820 kb
Host smart-a7d6b623-b253-4957-aa84-172def191e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37436
74033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3743674033
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.745233489
Short name T1580
Test name
Test status
Simulation time 218268936 ps
CPU time 0.87 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:30:28 PM PDT 24
Peak memory 206816 kb
Host smart-16b47962-6246-41db-a920-3f1d82244fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74523
3489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.745233489
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.3130963717
Short name T841
Test name
Test status
Simulation time 9763621555 ps
CPU time 264.35 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:34:48 PM PDT 24
Peak memory 206820 kb
Host smart-75aa169d-3d96-43fc-abbc-eff8dffcc704
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3130963717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3130963717
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3269474839
Short name T34
Test name
Test status
Simulation time 208638080 ps
CPU time 0.89 seconds
Started Jul 12 05:30:36 PM PDT 24
Finished Jul 12 05:30:43 PM PDT 24
Peak memory 206784 kb
Host smart-5e357b38-d0c1-4f5b-ab4f-811e30e281a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32694
74839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3269474839
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3634083163
Short name T1110
Test name
Test status
Simulation time 23321509353 ps
CPU time 30.3 seconds
Started Jul 12 05:30:19 PM PDT 24
Finished Jul 12 05:30:59 PM PDT 24
Peak memory 206760 kb
Host smart-2db658a7-ec9e-47ab-8c45-013b733454f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36340
83163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3634083163
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1806351749
Short name T2305
Test name
Test status
Simulation time 3309246995 ps
CPU time 3.51 seconds
Started Jul 12 05:30:21 PM PDT 24
Finished Jul 12 05:30:34 PM PDT 24
Peak memory 206876 kb
Host smart-94fdb871-d3a9-4a47-ba87-2b6e401bcefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18063
51749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1806351749
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.418462051
Short name T2630
Test name
Test status
Simulation time 7122277502 ps
CPU time 193.79 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:33:41 PM PDT 24
Peak memory 206980 kb
Host smart-0c11a5fb-5a00-42cd-b180-9d274fbc8da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41846
2051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.418462051
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2514608078
Short name T717
Test name
Test status
Simulation time 3159064885 ps
CPU time 83.09 seconds
Started Jul 12 05:30:19 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206908 kb
Host smart-e54ec3fb-e7de-4fe6-8608-3ca1b6aec822
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2514608078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2514608078
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.2459647258
Short name T1752
Test name
Test status
Simulation time 255587219 ps
CPU time 0.89 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 206808 kb
Host smart-c9486049-4469-4a29-bf05-09b1acc23ef8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2459647258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.2459647258
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3021059188
Short name T2140
Test name
Test status
Simulation time 191717343 ps
CPU time 0.86 seconds
Started Jul 12 05:30:20 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 206680 kb
Host smart-d61abc1e-bf3b-4604-a99e-c0af94e3ce31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30210
59188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3021059188
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3519136623
Short name T898
Test name
Test status
Simulation time 6079772007 ps
CPU time 169.74 seconds
Started Jul 12 05:30:17 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 207032 kb
Host smart-7d22d82f-5938-4578-ae62-b3f347d44716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191
36623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3519136623
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1501789140
Short name T2196
Test name
Test status
Simulation time 2904225134 ps
CPU time 80.73 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:32:00 PM PDT 24
Peak memory 207064 kb
Host smart-714ca99a-ad6d-4bc8-99d6-ecc0c8a58a15
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1501789140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1501789140
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.376541598
Short name T1268
Test name
Test status
Simulation time 173499429 ps
CPU time 0.83 seconds
Started Jul 12 05:30:15 PM PDT 24
Finished Jul 12 05:30:25 PM PDT 24
Peak memory 206792 kb
Host smart-a2cf0625-c034-43b6-ae2d-ae2dce9f75c4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=376541598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.376541598
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.4004933719
Short name T2511
Test name
Test status
Simulation time 141963052 ps
CPU time 0.79 seconds
Started Jul 12 05:30:30 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206700 kb
Host smart-9c3d7238-8ec9-4ed9-8b30-a7618ac4f34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40049
33719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.4004933719
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1853748682
Short name T1153
Test name
Test status
Simulation time 234498333 ps
CPU time 0.88 seconds
Started Jul 12 05:30:21 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 206760 kb
Host smart-adfccc38-39b4-429b-965f-951f0187afe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18537
48682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1853748682
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3535191382
Short name T548
Test name
Test status
Simulation time 164554906 ps
CPU time 0.83 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206828 kb
Host smart-7d5e2ec3-ab95-493d-a660-f37dec2aef84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35351
91382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3535191382
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2298382114
Short name T551
Test name
Test status
Simulation time 176774116 ps
CPU time 0.8 seconds
Started Jul 12 05:30:31 PM PDT 24
Finished Jul 12 05:30:38 PM PDT 24
Peak memory 206784 kb
Host smart-6d97d268-f2f4-4aee-95eb-97527993e29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22983
82114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2298382114
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.4272391294
Short name T2159
Test name
Test status
Simulation time 165926345 ps
CPU time 0.79 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206756 kb
Host smart-f9e5b145-7e81-46ff-91e3-9cb3ccbf8a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723
91294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.4272391294
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2584163882
Short name T1988
Test name
Test status
Simulation time 193036122 ps
CPU time 0.77 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206684 kb
Host smart-90fe152e-db3f-4adf-8876-0cb77519132f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25841
63882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2584163882
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.696458872
Short name T1172
Test name
Test status
Simulation time 213648291 ps
CPU time 0.95 seconds
Started Jul 12 05:30:25 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 206820 kb
Host smart-e5d350fd-e6e6-4d0c-b003-1e4c9ebcef30
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=696458872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.696458872
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3395540040
Short name T648
Test name
Test status
Simulation time 145210893 ps
CPU time 0.77 seconds
Started Jul 12 05:30:26 PM PDT 24
Finished Jul 12 05:30:34 PM PDT 24
Peak memory 206816 kb
Host smart-2685b0e9-8892-4614-b685-830cf99d6102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
40040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3395540040
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1420120525
Short name T2104
Test name
Test status
Simulation time 51899871 ps
CPU time 0.67 seconds
Started Jul 12 05:30:31 PM PDT 24
Finished Jul 12 05:30:38 PM PDT 24
Peak memory 206820 kb
Host smart-80f6637a-8ec1-471a-b2a1-735dbc74eeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14201
20525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1420120525
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2051553794
Short name T1331
Test name
Test status
Simulation time 13230853296 ps
CPU time 31.32 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:31:09 PM PDT 24
Peak memory 207112 kb
Host smart-4bce010c-3f25-4954-9bb5-74b04d4d3c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20515
53794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2051553794
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3736445042
Short name T634
Test name
Test status
Simulation time 172518054 ps
CPU time 0.85 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 206756 kb
Host smart-cb6d1498-35ba-4bec-9e84-3d5a6b8371c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37364
45042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3736445042
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1431195086
Short name T996
Test name
Test status
Simulation time 234454194 ps
CPU time 0.87 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206980 kb
Host smart-3f74a3ec-fa03-47f0-97ba-8cb5e930e9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14311
95086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1431195086
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2834554966
Short name T2748
Test name
Test status
Simulation time 172668934 ps
CPU time 0.87 seconds
Started Jul 12 05:30:30 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206816 kb
Host smart-07596afd-7b5c-45a4-af91-8de7aa1abdc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28345
54966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2834554966
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.923289143
Short name T1530
Test name
Test status
Simulation time 156001319 ps
CPU time 0.82 seconds
Started Jul 12 05:30:36 PM PDT 24
Finished Jul 12 05:30:43 PM PDT 24
Peak memory 206792 kb
Host smart-1ed076b1-4a42-4ee1-a027-1f94c7a2b4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92328
9143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.923289143
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.4077778119
Short name T1021
Test name
Test status
Simulation time 166876676 ps
CPU time 0.8 seconds
Started Jul 12 05:30:23 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 206792 kb
Host smart-16a11da9-9794-4f8f-aa55-3158035f4f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40777
78119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.4077778119
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.106901399
Short name T1190
Test name
Test status
Simulation time 158583312 ps
CPU time 0.8 seconds
Started Jul 12 05:30:30 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206812 kb
Host smart-a6a571d8-3a1b-4d9e-a598-42a7b4555bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690
1399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.106901399
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4222054711
Short name T1060
Test name
Test status
Simulation time 261298626 ps
CPU time 1 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206692 kb
Host smart-e3c06f22-339f-4f30-ac4f-69706fdda3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42220
54711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4222054711
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2688496481
Short name T343
Test name
Test status
Simulation time 5003521312 ps
CPU time 134.89 seconds
Started Jul 12 05:30:31 PM PDT 24
Finished Jul 12 05:32:52 PM PDT 24
Peak memory 207032 kb
Host smart-a39eacde-99a9-4a3c-90b8-3e8c9db4e735
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2688496481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2688496481
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.372623987
Short name T712
Test name
Test status
Simulation time 166810182 ps
CPU time 0.81 seconds
Started Jul 12 05:30:25 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 206812 kb
Host smart-8da1f4f6-b2ed-4c7d-a960-43671e5a4d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37262
3987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.372623987
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1739959467
Short name T1984
Test name
Test status
Simulation time 188533359 ps
CPU time 0.83 seconds
Started Jul 12 05:30:23 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 206808 kb
Host smart-63cda06f-e20b-4734-9bdb-ff4755a56f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17399
59467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1739959467
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3897576717
Short name T2120
Test name
Test status
Simulation time 1395960095 ps
CPU time 2.95 seconds
Started Jul 12 05:30:25 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206972 kb
Host smart-d30ff0dd-04f1-43b4-997c-8725c23fcb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38975
76717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3897576717
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2776145777
Short name T1681
Test name
Test status
Simulation time 5489512584 ps
CPU time 52.99 seconds
Started Jul 12 05:30:28 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 207084 kb
Host smart-f732c187-340d-44c9-a46c-5a799d210e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27761
45777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2776145777
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3985020993
Short name T434
Test name
Test status
Simulation time 34097007 ps
CPU time 0.69 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 206852 kb
Host smart-09dee568-2f1d-4fde-9a1f-50e4ff96caf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3985020993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3985020993
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.743482245
Short name T2706
Test name
Test status
Simulation time 3824622260 ps
CPU time 4.46 seconds
Started Jul 12 05:30:29 PM PDT 24
Finished Jul 12 05:30:40 PM PDT 24
Peak memory 206812 kb
Host smart-09010092-084a-49df-8133-1dcb333a6e0b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=743482245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.743482245
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.483036097
Short name T2178
Test name
Test status
Simulation time 13408124695 ps
CPU time 12.34 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:47 PM PDT 24
Peak memory 207064 kb
Host smart-b4cf0474-b7f8-4d66-bd99-2dc2d1246656
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=483036097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.483036097
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1889409120
Short name T883
Test name
Test status
Simulation time 23367319370 ps
CPU time 23.74 seconds
Started Jul 12 05:30:31 PM PDT 24
Finished Jul 12 05:31:01 PM PDT 24
Peak memory 207024 kb
Host smart-b1613db8-b788-4957-911f-ed30887b8413
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1889409120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1889409120
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3834325530
Short name T2637
Test name
Test status
Simulation time 185564455 ps
CPU time 0.83 seconds
Started Jul 12 05:30:28 PM PDT 24
Finished Jul 12 05:30:36 PM PDT 24
Peak memory 206800 kb
Host smart-a73a8ed4-16ff-4cdc-a29c-4bccb20f6272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38343
25530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3834325530
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.4211131534
Short name T1720
Test name
Test status
Simulation time 147720818 ps
CPU time 0.78 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206812 kb
Host smart-deeded54-e4a3-4f0b-a02f-13a752d3a0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42111
31534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.4211131534
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1232481183
Short name T1027
Test name
Test status
Simulation time 477571023 ps
CPU time 1.61 seconds
Started Jul 12 05:30:29 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206916 kb
Host smart-ba4f50d8-09ad-4134-9cc2-d4158e83e47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12324
81183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1232481183
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.757678287
Short name T2264
Test name
Test status
Simulation time 364407536 ps
CPU time 1.06 seconds
Started Jul 12 05:30:23 PM PDT 24
Finished Jul 12 05:30:33 PM PDT 24
Peak memory 206792 kb
Host smart-02fe00b1-5412-49fc-b673-1144392100fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75767
8287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.757678287
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2667172245
Short name T2058
Test name
Test status
Simulation time 10221746647 ps
CPU time 17.87 seconds
Started Jul 12 05:30:29 PM PDT 24
Finished Jul 12 05:30:53 PM PDT 24
Peak memory 207028 kb
Host smart-0b637194-f542-4097-890e-e377edf3ca07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26671
72245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2667172245
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.2658519859
Short name T857
Test name
Test status
Simulation time 396719098 ps
CPU time 1.32 seconds
Started Jul 12 05:30:30 PM PDT 24
Finished Jul 12 05:30:37 PM PDT 24
Peak memory 206824 kb
Host smart-eeff377c-f4ad-4b79-8525-b0256c7267f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26585
19859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.2658519859
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.816519833
Short name T2412
Test name
Test status
Simulation time 138734853 ps
CPU time 0.78 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206660 kb
Host smart-a313c35a-3212-49f3-8d83-f0553882905e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81651
9833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.816519833
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1623737130
Short name T1934
Test name
Test status
Simulation time 30051332 ps
CPU time 0.64 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:40 PM PDT 24
Peak memory 206752 kb
Host smart-fce7a9ba-86c7-4835-ae40-8b64a7fc0a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16237
37130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1623737130
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.338914441
Short name T1090
Test name
Test status
Simulation time 671104920 ps
CPU time 1.86 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 206956 kb
Host smart-fa48d338-9c8e-43e6-98d3-dc43cff7ccb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33891
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.338914441
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3551918209
Short name T2339
Test name
Test status
Simulation time 305087898 ps
CPU time 1.75 seconds
Started Jul 12 05:30:22 PM PDT 24
Finished Jul 12 05:30:32 PM PDT 24
Peak memory 207004 kb
Host smart-32efec93-b9e5-4c9c-b151-e30536c6bb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
18209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3551918209
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2635766704
Short name T361
Test name
Test status
Simulation time 143469313 ps
CPU time 0.81 seconds
Started Jul 12 05:30:27 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 206812 kb
Host smart-548a1676-0e5d-4fbb-b346-a77d6fe94dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
66704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2635766704
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1468644323
Short name T2215
Test name
Test status
Simulation time 207652173 ps
CPU time 0.87 seconds
Started Jul 12 05:30:36 PM PDT 24
Finished Jul 12 05:30:43 PM PDT 24
Peak memory 206776 kb
Host smart-21f7972e-743a-4644-8ecd-0cf3e443b586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14686
44323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1468644323
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.1796343763
Short name T2668
Test name
Test status
Simulation time 7591232118 ps
CPU time 72.39 seconds
Started Jul 12 05:30:25 PM PDT 24
Finished Jul 12 05:31:45 PM PDT 24
Peak memory 206856 kb
Host smart-896204e4-d800-40db-a6e8-f170e52f5049
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1796343763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.1796343763
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.3913458718
Short name T1832
Test name
Test status
Simulation time 4294279838 ps
CPU time 14.55 seconds
Started Jul 12 05:30:26 PM PDT 24
Finished Jul 12 05:30:48 PM PDT 24
Peak memory 206876 kb
Host smart-caf03588-b437-4e18-bb77-fc62d8453055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39134
58718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.3913458718
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2162686429
Short name T54
Test name
Test status
Simulation time 229435106 ps
CPU time 0.85 seconds
Started Jul 12 05:30:29 PM PDT 24
Finished Jul 12 05:30:36 PM PDT 24
Peak memory 206768 kb
Host smart-a12a4a90-c0ca-4210-8ddf-717dc02ef11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21626
86429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2162686429
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.434121906
Short name T1791
Test name
Test status
Simulation time 23297140029 ps
CPU time 21.86 seconds
Started Jul 12 05:30:25 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 206856 kb
Host smart-88a38a51-6683-48bf-9abe-d37bfbf24bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43412
1906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.434121906
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.3249310131
Short name T2257
Test name
Test status
Simulation time 3331508696 ps
CPU time 3.94 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206876 kb
Host smart-5ed3fc8c-cbf5-4cff-8338-c559d9fbebb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32493
10131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.3249310131
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3350322601
Short name T1506
Test name
Test status
Simulation time 11411765809 ps
CPU time 315.91 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 207108 kb
Host smart-4765ceb1-db8d-47d7-afc2-9dee34d634f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33503
22601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3350322601
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3809601673
Short name T2407
Test name
Test status
Simulation time 4518896612 ps
CPU time 41.04 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 207040 kb
Host smart-451b96ad-647d-4c37-a49a-b065b7e1ccdc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3809601673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3809601673
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.4138126819
Short name T835
Test name
Test status
Simulation time 246566733 ps
CPU time 0.92 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206820 kb
Host smart-b2c4d8a9-d3a3-4e20-8d25-27373842b427
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4138126819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.4138126819
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3924268973
Short name T321
Test name
Test status
Simulation time 196306931 ps
CPU time 0.92 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206716 kb
Host smart-addec25d-2f38-4fb9-bf90-ed14f8b43067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242
68973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3924268973
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3709892248
Short name T1034
Test name
Test status
Simulation time 3318148259 ps
CPU time 28.8 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:31:09 PM PDT 24
Peak memory 207024 kb
Host smart-821740ad-2641-4f6a-97d4-847ae70b84c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37098
92248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3709892248
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1808461292
Short name T1271
Test name
Test status
Simulation time 3901519867 ps
CPU time 104.04 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:32:41 PM PDT 24
Peak memory 207036 kb
Host smart-fe4c7741-0ba9-4310-88a1-c65c7e186443
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1808461292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1808461292
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2451939297
Short name T671
Test name
Test status
Simulation time 162222153 ps
CPU time 0.78 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206816 kb
Host smart-78100920-8a2e-4d7b-b7ab-b23520a6a67b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2451939297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2451939297
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1600103722
Short name T568
Test name
Test status
Simulation time 149801676 ps
CPU time 0.77 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 206716 kb
Host smart-d7131460-a0ce-4288-a54a-e8e9ecaf892e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16001
03722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1600103722
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.685088837
Short name T2697
Test name
Test status
Simulation time 179213999 ps
CPU time 0.89 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 206716 kb
Host smart-622fa473-aa47-4144-8a64-0f9b89378601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68508
8837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.685088837
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3047113920
Short name T1620
Test name
Test status
Simulation time 199343698 ps
CPU time 0.88 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206816 kb
Host smart-08296464-0b29-46fc-9a6e-11f58d63d59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30471
13920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3047113920
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1654622257
Short name T2692
Test name
Test status
Simulation time 177613944 ps
CPU time 0.81 seconds
Started Jul 12 05:30:39 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206924 kb
Host smart-b0dff9e3-2f81-4f1a-b4fa-97e7b9b60a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16546
22257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1654622257
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3265872586
Short name T2439
Test name
Test status
Simulation time 149051164 ps
CPU time 0.78 seconds
Started Jul 12 05:30:37 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206772 kb
Host smart-b5514b5a-d659-41f5-aadd-aa1fef843c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32658
72586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3265872586
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3946539071
Short name T2603
Test name
Test status
Simulation time 143948026 ps
CPU time 0.82 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:30:40 PM PDT 24
Peak memory 206676 kb
Host smart-c23b78bc-ac69-42ab-b665-4528a228d650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39465
39071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3946539071
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.12897301
Short name T1529
Test name
Test status
Simulation time 288423652 ps
CPU time 1.01 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:43 PM PDT 24
Peak memory 206808 kb
Host smart-94416685-2357-4291-ac68-c1b3b95e2c86
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=12897301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.12897301
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.4222182759
Short name T567
Test name
Test status
Simulation time 152295132 ps
CPU time 0.78 seconds
Started Jul 12 05:30:39 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206928 kb
Host smart-af3fbbd5-0502-473c-a114-1726e9f7b232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42221
82759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.4222182759
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3044932440
Short name T2536
Test name
Test status
Simulation time 31059688 ps
CPU time 0.67 seconds
Started Jul 12 05:30:40 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 206812 kb
Host smart-9ec1f222-c78b-4a71-9069-b3c0c0ae0bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30449
32440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3044932440
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2958020205
Short name T1165
Test name
Test status
Simulation time 16641427318 ps
CPU time 37.7 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:31:17 PM PDT 24
Peak memory 206940 kb
Host smart-20475809-ba10-4e28-9c45-8ea8142a6626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580
20205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2958020205
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1174183494
Short name T663
Test name
Test status
Simulation time 144397784 ps
CPU time 0.81 seconds
Started Jul 12 05:30:37 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206820 kb
Host smart-0f548683-4d9b-4e7f-a718-b21c66359fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11741
83494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1174183494
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2257730796
Short name T562
Test name
Test status
Simulation time 197499312 ps
CPU time 0.87 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206676 kb
Host smart-2ab3076c-8cee-42d6-8840-5650b1de0aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22577
30796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2257730796
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1982974024
Short name T2077
Test name
Test status
Simulation time 188474890 ps
CPU time 0.81 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206716 kb
Host smart-5a728c04-d251-4e17-a792-cb65e31de720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19829
74024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1982974024
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.908091309
Short name T751
Test name
Test status
Simulation time 173774745 ps
CPU time 0.84 seconds
Started Jul 12 05:30:41 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 206836 kb
Host smart-084e8b46-f2fc-4762-9773-08c564cc97fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90809
1309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.908091309
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.4275264458
Short name T1483
Test name
Test status
Simulation time 139184727 ps
CPU time 0.76 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:30:40 PM PDT 24
Peak memory 206792 kb
Host smart-80d12646-1de9-4772-9083-992144fe793b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42752
64458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.4275264458
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.4139889102
Short name T1762
Test name
Test status
Simulation time 149914636 ps
CPU time 0.8 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 206828 kb
Host smart-191d88fe-fadc-4412-ad49-7a72586d6e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41398
89102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.4139889102
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.240534356
Short name T1072
Test name
Test status
Simulation time 189484215 ps
CPU time 0.81 seconds
Started Jul 12 05:30:36 PM PDT 24
Finished Jul 12 05:30:43 PM PDT 24
Peak memory 206688 kb
Host smart-bbd87fcb-146c-4e69-9878-01b4bf6e56f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24053
4356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.240534356
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1954844411
Short name T1496
Test name
Test status
Simulation time 220042130 ps
CPU time 0.97 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 206804 kb
Host smart-bfc249b2-a555-43b1-aa29-715b5a576208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
44411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1954844411
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.1518424645
Short name T2564
Test name
Test status
Simulation time 3297683124 ps
CPU time 30.5 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:31:11 PM PDT 24
Peak memory 207056 kb
Host smart-cb7681f4-77c1-4340-ae5f-efa280220eba
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1518424645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.1518424645
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2872684955
Short name T2619
Test name
Test status
Simulation time 160818165 ps
CPU time 0.78 seconds
Started Jul 12 05:30:38 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206824 kb
Host smart-75bf0b6b-6695-4f45-8bb0-123dbf3cc9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28726
84955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2872684955
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1018082105
Short name T384
Test name
Test status
Simulation time 146627030 ps
CPU time 0.82 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206760 kb
Host smart-b03cfb2a-e79d-405f-b2be-1f405b28f5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
82105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1018082105
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3331966170
Short name T612
Test name
Test status
Simulation time 376102445 ps
CPU time 1.12 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:30:41 PM PDT 24
Peak memory 206820 kb
Host smart-4e81c630-cf33-462f-a105-abac2e0b091e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33319
66170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3331966170
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.3741219089
Short name T2634
Test name
Test status
Simulation time 6389366415 ps
CPU time 180.76 seconds
Started Jul 12 05:30:38 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 206976 kb
Host smart-75eb0314-549b-4e34-8267-3e3c2b6695ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37412
19089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.3741219089
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.909455262
Short name T1101
Test name
Test status
Simulation time 51470302 ps
CPU time 0.74 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206828 kb
Host smart-bb3b382a-8d82-45e0-809c-86a05057379c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=909455262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.909455262
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1608581635
Short name T1646
Test name
Test status
Simulation time 4043997031 ps
CPU time 5 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:47 PM PDT 24
Peak memory 207084 kb
Host smart-489e4872-fc45-4be7-9c27-cd588e05cbc6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1608581635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1608581635
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2529741027
Short name T2228
Test name
Test status
Simulation time 13383000029 ps
CPU time 13.1 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:30:53 PM PDT 24
Peak memory 206768 kb
Host smart-96664392-b258-4e0d-9684-6b9a5cdc9f1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2529741027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2529741027
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.1686309352
Short name T1403
Test name
Test status
Simulation time 23291789803 ps
CPU time 25.45 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 207020 kb
Host smart-30da7bdb-67e4-456d-9f6d-0d69ca5fafad
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1686309352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.1686309352
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2584560179
Short name T1773
Test name
Test status
Simulation time 148951375 ps
CPU time 0.83 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206800 kb
Host smart-d87992dc-a3b0-480a-a010-c855820c6ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25845
60179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2584560179
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.4195639853
Short name T1082
Test name
Test status
Simulation time 136984341 ps
CPU time 0.76 seconds
Started Jul 12 05:30:36 PM PDT 24
Finished Jul 12 05:30:43 PM PDT 24
Peak memory 206828 kb
Host smart-b766bc91-a5a4-4bd9-8155-fdee65d3de7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41956
39853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.4195639853
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3628894866
Short name T2694
Test name
Test status
Simulation time 325724426 ps
CPU time 1.18 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:40 PM PDT 24
Peak memory 206720 kb
Host smart-afad65cc-bb53-402f-9a58-7d9b4f3691ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36288
94866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3628894866
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.398967662
Short name T473
Test name
Test status
Simulation time 1193165517 ps
CPU time 2.52 seconds
Started Jul 12 05:30:36 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 206864 kb
Host smart-3dec41e6-0b65-48d3-926b-387a06dd0b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39896
7662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.398967662
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.4002206535
Short name T176
Test name
Test status
Simulation time 21532298001 ps
CPU time 39.99 seconds
Started Jul 12 05:30:34 PM PDT 24
Finished Jul 12 05:31:20 PM PDT 24
Peak memory 207016 kb
Host smart-5e0bb2bf-df38-4cb5-a207-4087a53b090f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40022
06535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.4002206535
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.77366121
Short name T545
Test name
Test status
Simulation time 410185098 ps
CPU time 1.31 seconds
Started Jul 12 05:30:33 PM PDT 24
Finished Jul 12 05:30:42 PM PDT 24
Peak memory 207016 kb
Host smart-a455baa2-f33f-453d-ad76-3f7336339207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77366
121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.77366121
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.638102894
Short name T1173
Test name
Test status
Simulation time 142449807 ps
CPU time 0.74 seconds
Started Jul 12 05:30:36 PM PDT 24
Finished Jul 12 05:30:43 PM PDT 24
Peak memory 206692 kb
Host smart-300157b0-ddb7-46db-ac3c-dc4f8b81fdd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63810
2894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.638102894
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2622907798
Short name T221
Test name
Test status
Simulation time 34392481 ps
CPU time 0.64 seconds
Started Jul 12 05:30:55 PM PDT 24
Finished Jul 12 05:30:59 PM PDT 24
Peak memory 206788 kb
Host smart-cb96d1d3-5c3a-409d-a103-e94c0792105e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26229
07798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2622907798
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.222440595
Short name T2346
Test name
Test status
Simulation time 851757674 ps
CPU time 1.95 seconds
Started Jul 12 05:30:35 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206968 kb
Host smart-21c19990-e0da-4ba4-93ea-167f3205a6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22244
0595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.222440595
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1975593308
Short name T1363
Test name
Test status
Simulation time 240227865 ps
CPU time 1.49 seconds
Started Jul 12 05:30:39 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 207000 kb
Host smart-3b418fa3-2f20-4499-9592-5b64a8d27b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
93308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1975593308
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1410042068
Short name T2384
Test name
Test status
Simulation time 238458859 ps
CPU time 0.94 seconds
Started Jul 12 05:30:48 PM PDT 24
Finished Jul 12 05:30:51 PM PDT 24
Peak memory 206828 kb
Host smart-7d2d989b-486d-49cd-9f2f-0f8586bcac70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14100
42068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1410042068
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1699898700
Short name T538
Test name
Test status
Simulation time 182710526 ps
CPU time 0.82 seconds
Started Jul 12 05:30:39 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206872 kb
Host smart-801eec4b-d378-485a-834c-94f01384496d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998
98700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1699898700
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1110275460
Short name T1428
Test name
Test status
Simulation time 202756540 ps
CPU time 0.88 seconds
Started Jul 12 05:30:32 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 206804 kb
Host smart-f6c2b362-57a7-4ffa-9189-86e098cebf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11102
75460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1110275460
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3640439131
Short name T2433
Test name
Test status
Simulation time 8480682255 ps
CPU time 79.8 seconds
Started Jul 12 05:30:56 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 206900 kb
Host smart-95657c00-a07d-483d-8f03-826c2b08a965
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3640439131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3640439131
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.3523837162
Short name T509
Test name
Test status
Simulation time 8314497637 ps
CPU time 32.31 seconds
Started Jul 12 05:30:53 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 207076 kb
Host smart-0baec4ed-e7a7-4d50-bcc9-e016a083150b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35238
37162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.3523837162
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2970452209
Short name T388
Test name
Test status
Simulation time 191132280 ps
CPU time 0.87 seconds
Started Jul 12 05:30:43 PM PDT 24
Finished Jul 12 05:30:47 PM PDT 24
Peak memory 206768 kb
Host smart-ccf932f1-a84b-4abb-8ace-2773533a5be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29704
52209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2970452209
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2861795934
Short name T637
Test name
Test status
Simulation time 23263425971 ps
CPU time 23.05 seconds
Started Jul 12 05:30:44 PM PDT 24
Finished Jul 12 05:31:09 PM PDT 24
Peak memory 206864 kb
Host smart-cee9535e-b737-4d8c-ad51-9d800abe1c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28617
95934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2861795934
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3135784937
Short name T1200
Test name
Test status
Simulation time 3341335033 ps
CPU time 3.95 seconds
Started Jul 12 05:30:42 PM PDT 24
Finished Jul 12 05:30:49 PM PDT 24
Peak memory 206780 kb
Host smart-d8a10188-5cdd-4dea-914d-d9b1c3f7b01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
84937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3135784937
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.3564892252
Short name T1318
Test name
Test status
Simulation time 7883636549 ps
CPU time 222.92 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:34:37 PM PDT 24
Peak memory 207132 kb
Host smart-d44182b2-6789-493c-966d-f387ad7b9257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35648
92252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.3564892252
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3387633598
Short name T1161
Test name
Test status
Simulation time 3682026530 ps
CPU time 32.67 seconds
Started Jul 12 05:30:58 PM PDT 24
Finished Jul 12 05:31:34 PM PDT 24
Peak memory 207060 kb
Host smart-21816085-57cf-4bf4-98b1-ad8d4a518fed
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3387633598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3387633598
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1112747775
Short name T865
Test name
Test status
Simulation time 306564711 ps
CPU time 0.99 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 206720 kb
Host smart-4d346ab5-c077-4921-b985-69c014ad8159
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1112747775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1112747775
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.65462124
Short name T360
Test name
Test status
Simulation time 194722621 ps
CPU time 0.88 seconds
Started Jul 12 05:30:49 PM PDT 24
Finished Jul 12 05:30:51 PM PDT 24
Peak memory 206816 kb
Host smart-dbe205db-4f3e-45de-9d26-d6fffb50f780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65462
124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.65462124
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2267040730
Short name T1649
Test name
Test status
Simulation time 3623225841 ps
CPU time 98.79 seconds
Started Jul 12 05:30:53 PM PDT 24
Finished Jul 12 05:32:35 PM PDT 24
Peak memory 207032 kb
Host smart-f21bad2c-b19a-41d0-a6c9-ec93493c4115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22670
40730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2267040730
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2346762821
Short name T154
Test name
Test status
Simulation time 6127780984 ps
CPU time 57.51 seconds
Started Jul 12 05:30:40 PM PDT 24
Finished Jul 12 05:31:42 PM PDT 24
Peak memory 207008 kb
Host smart-6280f290-d33a-4065-80a9-d481d3425ef8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2346762821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2346762821
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1361085562
Short name T1911
Test name
Test status
Simulation time 162731772 ps
CPU time 0.79 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206808 kb
Host smart-5879b64e-de32-440c-9945-27593a092816
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1361085562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1361085562
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.353963108
Short name T2076
Test name
Test status
Simulation time 167369437 ps
CPU time 0.8 seconds
Started Jul 12 05:30:49 PM PDT 24
Finished Jul 12 05:30:51 PM PDT 24
Peak memory 206824 kb
Host smart-d3750ce8-974e-4a17-8a5d-b7f247c3a8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35396
3108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.353963108
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1515616206
Short name T129
Test name
Test status
Simulation time 211978322 ps
CPU time 0.86 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206676 kb
Host smart-3f86d930-3e0f-4ad1-8e50-9fad75149bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15156
16206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1515616206
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3907287154
Short name T1304
Test name
Test status
Simulation time 174422552 ps
CPU time 0.82 seconds
Started Jul 12 05:30:47 PM PDT 24
Finished Jul 12 05:30:49 PM PDT 24
Peak memory 206812 kb
Host smart-26a28db9-a9e4-4312-a93a-d129a6e9a25d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
87154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3907287154
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2151711725
Short name T441
Test name
Test status
Simulation time 161348727 ps
CPU time 0.78 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206696 kb
Host smart-4f456660-e15c-43e7-a778-fca84485915a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21517
11725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2151711725
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1661236084
Short name T1932
Test name
Test status
Simulation time 211200984 ps
CPU time 0.85 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 206812 kb
Host smart-757c68da-3a14-4d1e-850c-52860b39590e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16612
36084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1661236084
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2138077464
Short name T173
Test name
Test status
Simulation time 148254284 ps
CPU time 0.77 seconds
Started Jul 12 05:30:39 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 206820 kb
Host smart-a8ff9e13-d0fc-4016-a643-a36b247cacf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21380
77464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2138077464
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3775141414
Short name T2121
Test name
Test status
Simulation time 244329555 ps
CPU time 0.98 seconds
Started Jul 12 05:30:49 PM PDT 24
Finished Jul 12 05:30:51 PM PDT 24
Peak memory 206820 kb
Host smart-4def4ba8-325e-41b3-8192-a0fab9e6f302
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3775141414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3775141414
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3252719732
Short name T966
Test name
Test status
Simulation time 143998966 ps
CPU time 0.76 seconds
Started Jul 12 05:30:38 PM PDT 24
Finished Jul 12 05:30:44 PM PDT 24
Peak memory 206696 kb
Host smart-74dfd2ee-cd15-4d36-a468-5fdbaf244f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32527
19732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3252719732
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1729008227
Short name T2483
Test name
Test status
Simulation time 45788582 ps
CPU time 0.67 seconds
Started Jul 12 05:30:49 PM PDT 24
Finished Jul 12 05:30:51 PM PDT 24
Peak memory 206708 kb
Host smart-e78b9fc5-551e-4ab2-a03c-dfb883628980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17290
08227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1729008227
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4018582290
Short name T1489
Test name
Test status
Simulation time 9216696587 ps
CPU time 23.3 seconds
Started Jul 12 05:30:47 PM PDT 24
Finished Jul 12 05:31:11 PM PDT 24
Peak memory 207096 kb
Host smart-57abc8c6-3880-40c1-9115-e9f52b83af48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40185
82290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4018582290
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.587028527
Short name T1621
Test name
Test status
Simulation time 173661727 ps
CPU time 0.82 seconds
Started Jul 12 05:30:55 PM PDT 24
Finished Jul 12 05:30:59 PM PDT 24
Peak memory 206636 kb
Host smart-19424269-ad3b-4743-95d4-c285a814cb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58702
8527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.587028527
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3992545170
Short name T1744
Test name
Test status
Simulation time 186332465 ps
CPU time 0.83 seconds
Started Jul 12 05:30:50 PM PDT 24
Finished Jul 12 05:30:53 PM PDT 24
Peak memory 206808 kb
Host smart-6c269ebd-b229-4803-a86f-93317b5d3f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39925
45170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3992545170
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2402274275
Short name T927
Test name
Test status
Simulation time 213097196 ps
CPU time 0.89 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206812 kb
Host smart-777ffe81-c62c-4bd2-b295-ea2ac01cd9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24022
74275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2402274275
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1426367631
Short name T1879
Test name
Test status
Simulation time 188202451 ps
CPU time 0.83 seconds
Started Jul 12 05:30:46 PM PDT 24
Finished Jul 12 05:30:48 PM PDT 24
Peak memory 206800 kb
Host smart-0edf64aa-3c09-488e-9268-a0385cca6956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14263
67631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1426367631
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.571947388
Short name T421
Test name
Test status
Simulation time 161808868 ps
CPU time 0.74 seconds
Started Jul 12 05:30:47 PM PDT 24
Finished Jul 12 05:30:49 PM PDT 24
Peak memory 206704 kb
Host smart-b01e8049-e83c-4e2b-900a-3e8d32f047b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57194
7388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.571947388
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2081277926
Short name T655
Test name
Test status
Simulation time 153519156 ps
CPU time 0.81 seconds
Started Jul 12 05:30:50 PM PDT 24
Finished Jul 12 05:30:52 PM PDT 24
Peak memory 206804 kb
Host smart-e3108369-659d-487c-92d1-72fe0e3e6979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20812
77926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2081277926
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2273604211
Short name T2162
Test name
Test status
Simulation time 151892366 ps
CPU time 0.82 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 207000 kb
Host smart-79edad99-62bc-41ca-8579-fca07c40b183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22736
04211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2273604211
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1099185705
Short name T2300
Test name
Test status
Simulation time 220032187 ps
CPU time 0.96 seconds
Started Jul 12 05:30:47 PM PDT 24
Finished Jul 12 05:30:48 PM PDT 24
Peak memory 206768 kb
Host smart-47b64ae1-767a-43f8-bd13-a0ec95460baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10991
85705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1099185705
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.619308822
Short name T1475
Test name
Test status
Simulation time 5230821054 ps
CPU time 136.08 seconds
Started Jul 12 05:30:48 PM PDT 24
Finished Jul 12 05:33:05 PM PDT 24
Peak memory 207044 kb
Host smart-4948f896-0b37-451a-99fa-6ebfe950a77b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=619308822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.619308822
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.4146253299
Short name T333
Test name
Test status
Simulation time 192187138 ps
CPU time 0.9 seconds
Started Jul 12 05:30:50 PM PDT 24
Finished Jul 12 05:30:53 PM PDT 24
Peak memory 206700 kb
Host smart-9df2dd92-9d3b-4653-8118-9107b9987599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41462
53299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.4146253299
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1590787514
Short name T1054
Test name
Test status
Simulation time 167404888 ps
CPU time 0.79 seconds
Started Jul 12 05:30:48 PM PDT 24
Finished Jul 12 05:30:50 PM PDT 24
Peak memory 206804 kb
Host smart-db5c1566-a35d-4f0f-aa93-4b05338eea49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15907
87514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1590787514
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.643322216
Short name T1121
Test name
Test status
Simulation time 263326213 ps
CPU time 1.01 seconds
Started Jul 12 05:30:47 PM PDT 24
Finished Jul 12 05:30:50 PM PDT 24
Peak memory 206804 kb
Host smart-ea9e7a1d-45f1-4d6a-ae9e-eb2cb7776abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64332
2216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.643322216
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.213495549
Short name T82
Test name
Test status
Simulation time 3581167379 ps
CPU time 98.15 seconds
Started Jul 12 05:30:57 PM PDT 24
Finished Jul 12 05:32:39 PM PDT 24
Peak memory 206960 kb
Host smart-5c50cdd0-9010-4ceb-8b18-cab583ccb723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21349
5549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.213495549
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3849020663
Short name T2721
Test name
Test status
Simulation time 66640818 ps
CPU time 0.75 seconds
Started Jul 12 05:30:53 PM PDT 24
Finished Jul 12 05:30:56 PM PDT 24
Peak memory 206868 kb
Host smart-60410ace-b0b8-41db-9c16-8276089c1ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3849020663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3849020663
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.3887143893
Short name T1601
Test name
Test status
Simulation time 4019165071 ps
CPU time 4.84 seconds
Started Jul 12 05:30:48 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 207044 kb
Host smart-a0c87a89-8027-47c4-861b-e45123462f60
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3887143893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.3887143893
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2392674975
Short name T832
Test name
Test status
Simulation time 13452398679 ps
CPU time 13.08 seconds
Started Jul 12 05:30:48 PM PDT 24
Finished Jul 12 05:31:02 PM PDT 24
Peak memory 207032 kb
Host smart-cd06b2e5-1ba9-4199-9fa7-15a3559cb460
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2392674975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2392674975
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.903522807
Short name T2350
Test name
Test status
Simulation time 23369538497 ps
CPU time 21.47 seconds
Started Jul 12 05:30:43 PM PDT 24
Finished Jul 12 05:31:07 PM PDT 24
Peak memory 207084 kb
Host smart-db71f536-5624-4adf-918a-65314fcb7dde
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=903522807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.903522807
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.361920287
Short name T1438
Test name
Test status
Simulation time 154388313 ps
CPU time 0.8 seconds
Started Jul 12 05:30:42 PM PDT 24
Finished Jul 12 05:30:46 PM PDT 24
Peak memory 206692 kb
Host smart-438db233-ca71-483f-a1a5-b4d22c45a8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36192
0287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.361920287
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.309645737
Short name T614
Test name
Test status
Simulation time 148872481 ps
CPU time 0.79 seconds
Started Jul 12 05:30:40 PM PDT 24
Finished Jul 12 05:30:45 PM PDT 24
Peak memory 206816 kb
Host smart-c1885dc8-1f32-4249-b189-f24945201992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30964
5737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.309645737
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3734775512
Short name T1747
Test name
Test status
Simulation time 467980080 ps
CPU time 1.5 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:30:56 PM PDT 24
Peak memory 206812 kb
Host smart-56e1b21c-f0ea-462b-9c9e-b076b3dcfa74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37347
75512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3734775512
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.674047567
Short name T2542
Test name
Test status
Simulation time 797678477 ps
CPU time 1.89 seconds
Started Jul 12 05:30:50 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206836 kb
Host smart-af57668c-fdd1-4cb6-8fd6-f88c480b6b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67404
7567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.674047567
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.2639134069
Short name T2673
Test name
Test status
Simulation time 5984419925 ps
CPU time 11.52 seconds
Started Jul 12 05:30:53 PM PDT 24
Finished Jul 12 05:31:08 PM PDT 24
Peak memory 207188 kb
Host smart-5ee79a79-7787-4d02-af08-128656c82486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26391
34069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2639134069
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.3762435322
Short name T1349
Test name
Test status
Simulation time 437573601 ps
CPU time 1.39 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206812 kb
Host smart-8296238f-d06d-4dd2-8173-2ae6743f06e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37624
35322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.3762435322
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2011978689
Short name T679
Test name
Test status
Simulation time 169550360 ps
CPU time 0.76 seconds
Started Jul 12 05:30:47 PM PDT 24
Finished Jul 12 05:30:48 PM PDT 24
Peak memory 206720 kb
Host smart-ca55afc9-b9a4-4e2a-8cbd-64e8c22189c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20119
78689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2011978689
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.453484897
Short name T2327
Test name
Test status
Simulation time 49254681 ps
CPU time 0.69 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:30:56 PM PDT 24
Peak memory 206804 kb
Host smart-44dd7712-ea43-4e9f-a380-4a316214fbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45348
4897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.453484897
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3488010365
Short name T2250
Test name
Test status
Simulation time 752239282 ps
CPU time 1.88 seconds
Started Jul 12 05:30:48 PM PDT 24
Finished Jul 12 05:30:57 PM PDT 24
Peak memory 206848 kb
Host smart-d543c376-01c1-401d-99cc-80cb24fcde4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34880
10365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3488010365
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3067371501
Short name T692
Test name
Test status
Simulation time 288936849 ps
CPU time 1.7 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 207024 kb
Host smart-073f07e1-2cbb-4ce2-8624-cc327353dec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30673
71501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3067371501
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2955667340
Short name T2127
Test name
Test status
Simulation time 210732561 ps
CPU time 0.88 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 206828 kb
Host smart-c4a11dd0-64c6-496f-8ea6-da47d367b6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556
67340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2955667340
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.881570914
Short name T1778
Test name
Test status
Simulation time 237617537 ps
CPU time 0.83 seconds
Started Jul 12 05:30:55 PM PDT 24
Finished Jul 12 05:30:59 PM PDT 24
Peak memory 206628 kb
Host smart-5d4ad5d2-72a9-4820-b22d-4fc0d3422547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88157
0914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.881570914
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.938392875
Short name T2728
Test name
Test status
Simulation time 192708456 ps
CPU time 0.95 seconds
Started Jul 12 05:30:47 PM PDT 24
Finished Jul 12 05:30:49 PM PDT 24
Peak memory 206696 kb
Host smart-197b020b-6621-45f8-9227-63e0b9d5d2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93839
2875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.938392875
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.273073557
Short name T2678
Test name
Test status
Simulation time 8656245120 ps
CPU time 227.59 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:34:42 PM PDT 24
Peak memory 207028 kb
Host smart-faaae545-866a-401d-84f0-93478af7d8e0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=273073557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.273073557
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.2692195210
Short name T732
Test name
Test status
Simulation time 3986824492 ps
CPU time 11.86 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:31:05 PM PDT 24
Peak memory 207016 kb
Host smart-f66d1a7f-d77d-4093-97d1-2cf0f7109ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26921
95210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.2692195210
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.142239288
Short name T2006
Test name
Test status
Simulation time 248378695 ps
CPU time 0.9 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206808 kb
Host smart-347e46da-42fc-4798-8373-02658a84aab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14223
9288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.142239288
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1346127740
Short name T1844
Test name
Test status
Simulation time 23256400442 ps
CPU time 21.71 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:31:19 PM PDT 24
Peak memory 206872 kb
Host smart-24af6a5f-bd4d-425a-8b7d-a869cf7ea0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13461
27740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1346127740
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3655209494
Short name T2044
Test name
Test status
Simulation time 3336171637 ps
CPU time 3.63 seconds
Started Jul 12 05:30:46 PM PDT 24
Finished Jul 12 05:30:50 PM PDT 24
Peak memory 206860 kb
Host smart-c3e1327e-e4f7-4046-af96-daf0597d7c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36552
09494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3655209494
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.894745423
Short name T1355
Test name
Test status
Simulation time 10022778428 ps
CPU time 71.84 seconds
Started Jul 12 05:30:49 PM PDT 24
Finished Jul 12 05:32:02 PM PDT 24
Peak memory 207084 kb
Host smart-20e9a620-7b5e-426b-b273-1798af17bb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89474
5423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.894745423
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2468127090
Short name T1472
Test name
Test status
Simulation time 4159681937 ps
CPU time 38.56 seconds
Started Jul 12 05:30:56 PM PDT 24
Finished Jul 12 05:31:39 PM PDT 24
Peak memory 206832 kb
Host smart-896e86d0-f39d-498d-9eff-32e7d2577640
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2468127090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2468127090
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1606798620
Short name T277
Test name
Test status
Simulation time 317642331 ps
CPU time 1.08 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 206808 kb
Host smart-71b46687-0146-41db-a28f-4686ed911214
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1606798620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1606798620
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3286966969
Short name T1661
Test name
Test status
Simulation time 256803178 ps
CPU time 1 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206812 kb
Host smart-28682004-da7a-4845-90a4-97b1af4def24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32869
66969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3286966969
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2176311949
Short name T1125
Test name
Test status
Simulation time 5079184431 ps
CPU time 47.49 seconds
Started Jul 12 05:31:03 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 207104 kb
Host smart-6725a8b2-6a76-4b2d-9ce3-d491e53d0e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21763
11949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2176311949
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2766128215
Short name T36
Test name
Test status
Simulation time 7090832498 ps
CPU time 190.25 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:34:03 PM PDT 24
Peak memory 206944 kb
Host smart-b361386e-dfda-4915-8594-9211857abbd1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2766128215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2766128215
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.3921758534
Short name T875
Test name
Test status
Simulation time 163164636 ps
CPU time 0.86 seconds
Started Jul 12 05:31:02 PM PDT 24
Finished Jul 12 05:31:05 PM PDT 24
Peak memory 206808 kb
Host smart-c815262a-b498-474c-8e26-00b3cced1511
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3921758534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.3921758534
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1422201315
Short name T1654
Test name
Test status
Simulation time 175768632 ps
CPU time 0.8 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206804 kb
Host smart-0c9fa10b-0e1d-4b77-b48e-a3159d945c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14222
01315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1422201315
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3579139237
Short name T140
Test name
Test status
Simulation time 268153580 ps
CPU time 0.96 seconds
Started Jul 12 05:30:57 PM PDT 24
Finished Jul 12 05:31:01 PM PDT 24
Peak memory 206712 kb
Host smart-762da245-70dc-42df-b294-3f1c0675fec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35791
39237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3579139237
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1012387787
Short name T2021
Test name
Test status
Simulation time 143741792 ps
CPU time 0.8 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206800 kb
Host smart-256fedd3-f478-4bb6-adf5-84551cd5c77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10123
87787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1012387787
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.712749422
Short name T2148
Test name
Test status
Simulation time 184975823 ps
CPU time 0.86 seconds
Started Jul 12 05:30:53 PM PDT 24
Finished Jul 12 05:30:56 PM PDT 24
Peak memory 206760 kb
Host smart-efcaee5f-ad03-4f08-87c6-da0edccf25ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71274
9422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.712749422
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.961612191
Short name T867
Test name
Test status
Simulation time 185196512 ps
CPU time 0.81 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 206808 kb
Host smart-bcc4f750-7852-4453-b1e2-75fdadab024a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96161
2191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.961612191
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2234694167
Short name T1137
Test name
Test status
Simulation time 166419697 ps
CPU time 0.83 seconds
Started Jul 12 05:30:57 PM PDT 24
Finished Jul 12 05:31:01 PM PDT 24
Peak memory 206836 kb
Host smart-0a3d3302-cc28-4320-80ea-ab7c801d6f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22346
94167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2234694167
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2717929832
Short name T1916
Test name
Test status
Simulation time 230324366 ps
CPU time 0.93 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206692 kb
Host smart-45a9ea42-5c3c-469e-9a18-12f72c7529cb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2717929832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2717929832
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.830147516
Short name T1942
Test name
Test status
Simulation time 161831078 ps
CPU time 0.79 seconds
Started Jul 12 05:30:56 PM PDT 24
Finished Jul 12 05:31:01 PM PDT 24
Peak memory 206820 kb
Host smart-52f42fa9-d89a-48cb-88f3-2240005ab92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83014
7516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.830147516
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.4224164886
Short name T636
Test name
Test status
Simulation time 35152047 ps
CPU time 0.67 seconds
Started Jul 12 05:30:56 PM PDT 24
Finished Jul 12 05:31:00 PM PDT 24
Peak memory 206804 kb
Host smart-7ef4b81c-d2b5-418b-bb09-6cc1f4bedf95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42241
64886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.4224164886
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1369320816
Short name T2485
Test name
Test status
Simulation time 19291313519 ps
CPU time 40 seconds
Started Jul 12 05:30:53 PM PDT 24
Finished Jul 12 05:31:35 PM PDT 24
Peak memory 207108 kb
Host smart-94d4a5e1-818c-4f8a-8fb5-6aef8127c5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13693
20816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1369320816
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.647231693
Short name T2457
Test name
Test status
Simulation time 156040047 ps
CPU time 0.81 seconds
Started Jul 12 05:30:56 PM PDT 24
Finished Jul 12 05:31:00 PM PDT 24
Peak memory 206816 kb
Host smart-d267ea68-5505-4be3-9a17-c2d937925443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64723
1693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.647231693
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3051041090
Short name T1400
Test name
Test status
Simulation time 204222036 ps
CPU time 0.9 seconds
Started Jul 12 05:30:55 PM PDT 24
Finished Jul 12 05:30:59 PM PDT 24
Peak memory 206808 kb
Host smart-87134e48-97c5-43e9-b00b-8dbd669f7d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30510
41090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3051041090
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2430347406
Short name T1107
Test name
Test status
Simulation time 173253207 ps
CPU time 0.81 seconds
Started Jul 12 05:30:53 PM PDT 24
Finished Jul 12 05:30:57 PM PDT 24
Peak memory 206840 kb
Host smart-d457a6f2-ab5f-47d5-a249-03c08cf354b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303
47406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2430347406
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1557266562
Short name T736
Test name
Test status
Simulation time 144164116 ps
CPU time 0.79 seconds
Started Jul 12 05:30:59 PM PDT 24
Finished Jul 12 05:31:02 PM PDT 24
Peak memory 206824 kb
Host smart-54e6cb70-0532-4f9f-86ee-3bb3ed4a20d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
66562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1557266562
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.284402882
Short name T1150
Test name
Test status
Simulation time 141957548 ps
CPU time 0.77 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:57 PM PDT 24
Peak memory 206816 kb
Host smart-a1e06f23-08b6-4eee-9b9f-4a9209a900c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
2882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.284402882
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1897873210
Short name T1607
Test name
Test status
Simulation time 146456666 ps
CPU time 0.83 seconds
Started Jul 12 05:30:56 PM PDT 24
Finished Jul 12 05:31:01 PM PDT 24
Peak memory 206712 kb
Host smart-012912d6-0d1a-41a6-b9ac-6311f6f84b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18978
73210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1897873210
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2265754019
Short name T1177
Test name
Test status
Simulation time 166742837 ps
CPU time 0.83 seconds
Started Jul 12 05:30:57 PM PDT 24
Finished Jul 12 05:31:02 PM PDT 24
Peak memory 206808 kb
Host smart-8083914c-5547-4a4d-af61-cc1d911e1243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22657
54019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2265754019
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1186804474
Short name T999
Test name
Test status
Simulation time 225396370 ps
CPU time 0.96 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206716 kb
Host smart-ceac64a9-4ec4-46b5-a1b9-faa3ba2413af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11868
04474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1186804474
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.606796793
Short name T1266
Test name
Test status
Simulation time 3705912544 ps
CPU time 25.32 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 207016 kb
Host smart-d9d509f7-ed09-4634-8c51-7992a1cec428
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=606796793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.606796793
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1813029376
Short name T564
Test name
Test status
Simulation time 166292894 ps
CPU time 0.81 seconds
Started Jul 12 05:30:49 PM PDT 24
Finished Jul 12 05:30:51 PM PDT 24
Peak memory 206816 kb
Host smart-4da70599-ef56-4836-b84d-51a9905de9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130
29376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1813029376
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2011880025
Short name T2180
Test name
Test status
Simulation time 198659383 ps
CPU time 0.94 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206828 kb
Host smart-d7bc60a4-03f0-453d-ad81-f92df285558a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20118
80025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2011880025
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1138222064
Short name T1998
Test name
Test status
Simulation time 590724933 ps
CPU time 1.38 seconds
Started Jul 12 05:30:49 PM PDT 24
Finished Jul 12 05:30:52 PM PDT 24
Peak memory 206720 kb
Host smart-00058695-384f-4975-b9a5-d9c3437e2e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11382
22064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1138222064
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3637098609
Short name T1396
Test name
Test status
Simulation time 7687807197 ps
CPU time 217.34 seconds
Started Jul 12 05:30:57 PM PDT 24
Finished Jul 12 05:34:38 PM PDT 24
Peak memory 207028 kb
Host smart-5ef35a82-4923-4941-a312-5bb391d3343b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36370
98609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3637098609
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.434970594
Short name T2520
Test name
Test status
Simulation time 31456367 ps
CPU time 0.69 seconds
Started Jul 12 05:26:42 PM PDT 24
Finished Jul 12 05:26:45 PM PDT 24
Peak memory 206852 kb
Host smart-946b9331-e42b-4134-a531-8776fb0d6da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=434970594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.434970594
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2481292274
Short name T2681
Test name
Test status
Simulation time 3658166842 ps
CPU time 4.55 seconds
Started Jul 12 05:26:40 PM PDT 24
Finished Jul 12 05:26:47 PM PDT 24
Peak memory 206700 kb
Host smart-2b96266c-aaa6-4717-88f1-6b19e8d6ea0b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2481292274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.2481292274
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.4083912129
Short name T1722
Test name
Test status
Simulation time 13415631745 ps
CPU time 13.37 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:27:05 PM PDT 24
Peak memory 206816 kb
Host smart-9782aba3-1bdb-4462-9784-ad1581103971
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4083912129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.4083912129
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2510723425
Short name T1324
Test name
Test status
Simulation time 23434069670 ps
CPU time 22.57 seconds
Started Jul 12 05:26:37 PM PDT 24
Finished Jul 12 05:27:01 PM PDT 24
Peak memory 206788 kb
Host smart-361c3ad5-0be3-45ff-a22c-31104a35d7b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2510723425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.2510723425
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.70960224
Short name T1948
Test name
Test status
Simulation time 208492967 ps
CPU time 0.89 seconds
Started Jul 12 05:26:39 PM PDT 24
Finished Jul 12 05:26:43 PM PDT 24
Peak memory 206804 kb
Host smart-8964b1e5-a0af-4e6f-adf0-fcbd50a578d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70960
224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.70960224
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3495297282
Short name T52
Test name
Test status
Simulation time 159222045 ps
CPU time 0.79 seconds
Started Jul 12 05:26:38 PM PDT 24
Finished Jul 12 05:26:42 PM PDT 24
Peak memory 206812 kb
Host smart-f48d8f5a-af2e-47e1-bdf1-9ea24853ae3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34952
97282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3495297282
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.1515450299
Short name T83
Test name
Test status
Simulation time 151194622 ps
CPU time 0.79 seconds
Started Jul 12 05:26:35 PM PDT 24
Finished Jul 12 05:26:37 PM PDT 24
Peak memory 206816 kb
Host smart-c07d586e-c0e6-4e9e-aef0-0faf2308cafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15154
50299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.1515450299
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2271377595
Short name T1012
Test name
Test status
Simulation time 177377192 ps
CPU time 0.84 seconds
Started Jul 12 05:26:34 PM PDT 24
Finished Jul 12 05:26:36 PM PDT 24
Peak memory 206816 kb
Host smart-8c161cb5-4940-48a1-8e61-7a38c5bd0edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713
77595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2271377595
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.2104658234
Short name T1359
Test name
Test status
Simulation time 387157668 ps
CPU time 1.22 seconds
Started Jul 12 05:26:37 PM PDT 24
Finished Jul 12 05:26:41 PM PDT 24
Peak memory 206760 kb
Host smart-44d758b1-abbf-4af3-82c7-e8dd705a5df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21046
58234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2104658234
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2081467506
Short name T1758
Test name
Test status
Simulation time 1173610977 ps
CPU time 2.46 seconds
Started Jul 12 05:26:36 PM PDT 24
Finished Jul 12 05:26:40 PM PDT 24
Peak memory 207052 kb
Host smart-77f642f9-ef94-484b-a352-582a3f72298e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20814
67506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2081467506
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.721669412
Short name T91
Test name
Test status
Simulation time 6993645523 ps
CPU time 12.82 seconds
Started Jul 12 05:26:35 PM PDT 24
Finished Jul 12 05:26:48 PM PDT 24
Peak memory 206932 kb
Host smart-7c069cdb-fdee-4576-8287-ec183b00087f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72166
9412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.721669412
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.1994967986
Short name T546
Test name
Test status
Simulation time 418565766 ps
CPU time 1.28 seconds
Started Jul 12 05:26:50 PM PDT 24
Finished Jul 12 05:26:52 PM PDT 24
Peak memory 206816 kb
Host smart-8d9dd382-9069-4269-ac35-a41c77271863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19949
67986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.1994967986
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2344490450
Short name T1749
Test name
Test status
Simulation time 145932631 ps
CPU time 0.75 seconds
Started Jul 12 05:26:50 PM PDT 24
Finished Jul 12 05:26:52 PM PDT 24
Peak memory 206816 kb
Host smart-220c70db-1871-46d9-84b4-9548a4865948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
90450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2344490450
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1225181565
Short name T1733
Test name
Test status
Simulation time 38393353 ps
CPU time 0.66 seconds
Started Jul 12 05:26:37 PM PDT 24
Finished Jul 12 05:26:40 PM PDT 24
Peak memory 206784 kb
Host smart-bf137e87-2041-45d9-9b74-58b5b2cc7a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
81565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1225181565
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1184398667
Short name T1321
Test name
Test status
Simulation time 921322460 ps
CPU time 2.18 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:54 PM PDT 24
Peak memory 206956 kb
Host smart-775b1f31-abf6-4de5-ab0b-14aec3f5ebf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11843
98667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1184398667
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3914640948
Short name T1083
Test name
Test status
Simulation time 180205852 ps
CPU time 1.44 seconds
Started Jul 12 05:26:37 PM PDT 24
Finished Jul 12 05:26:41 PM PDT 24
Peak memory 207008 kb
Host smart-f99e3d40-8713-4c8b-9056-da06e173e283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39146
40948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3914640948
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.1947784531
Short name T870
Test name
Test status
Simulation time 91170138790 ps
CPU time 122.45 seconds
Started Jul 12 05:26:37 PM PDT 24
Finished Jul 12 05:28:42 PM PDT 24
Peak memory 206936 kb
Host smart-3455d523-6250-4efe-9278-48c33a14c294
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1947784531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.1947784531
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3771582872
Short name T2273
Test name
Test status
Simulation time 104144004161 ps
CPU time 144.11 seconds
Started Jul 12 05:26:40 PM PDT 24
Finished Jul 12 05:29:07 PM PDT 24
Peak memory 206432 kb
Host smart-96a1f232-97b2-4c48-9475-24acde7d9d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771582872 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3771582872
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.4237245106
Short name T465
Test name
Test status
Simulation time 89112399414 ps
CPU time 104.76 seconds
Started Jul 12 05:26:40 PM PDT 24
Finished Jul 12 05:28:27 PM PDT 24
Peak memory 206900 kb
Host smart-c5bc880d-cd67-4020-bff5-329fa93a1828
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4237245106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.4237245106
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.623788526
Short name T1039
Test name
Test status
Simulation time 119869796921 ps
CPU time 190.12 seconds
Started Jul 12 05:26:37 PM PDT 24
Finished Jul 12 05:29:49 PM PDT 24
Peak memory 206968 kb
Host smart-a007c865-2cb9-4aa2-91c3-43e2c9b61d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623788526 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.623788526
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.1981671833
Short name T2235
Test name
Test status
Simulation time 121122266860 ps
CPU time 163.77 seconds
Started Jul 12 05:26:37 PM PDT 24
Finished Jul 12 05:29:24 PM PDT 24
Peak memory 206956 kb
Host smart-e8c32635-06fe-4ec3-b34f-491735354530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19816
71833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.1981671833
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1797408477
Short name T894
Test name
Test status
Simulation time 247160262 ps
CPU time 0.91 seconds
Started Jul 12 05:26:40 PM PDT 24
Finished Jul 12 05:26:43 PM PDT 24
Peak memory 206180 kb
Host smart-1db25ead-768b-4afb-a590-b7b38a551d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17974
08477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1797408477
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2001868264
Short name T2189
Test name
Test status
Simulation time 142251978 ps
CPU time 0.75 seconds
Started Jul 12 05:26:38 PM PDT 24
Finished Jul 12 05:26:41 PM PDT 24
Peak memory 206804 kb
Host smart-e29459cd-273b-4253-9d02-5e4d9eacc0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20018
68264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2001868264
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.434333861
Short name T1817
Test name
Test status
Simulation time 240485517 ps
CPU time 0.93 seconds
Started Jul 12 05:26:38 PM PDT 24
Finished Jul 12 05:26:41 PM PDT 24
Peak memory 206696 kb
Host smart-346d9780-fe67-4019-942a-a09cc93b2402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43433
3861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.434333861
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3687570965
Short name T234
Test name
Test status
Simulation time 10849917020 ps
CPU time 300.94 seconds
Started Jul 12 05:26:38 PM PDT 24
Finished Jul 12 05:31:41 PM PDT 24
Peak memory 207032 kb
Host smart-5843a5a1-b54b-43ef-97de-5911b827cf4f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3687570965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3687570965
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2305547943
Short name T225
Test name
Test status
Simulation time 4242698193 ps
CPU time 13.03 seconds
Started Jul 12 05:26:41 PM PDT 24
Finished Jul 12 05:26:56 PM PDT 24
Peak memory 206868 kb
Host smart-f9361efa-6c31-46cb-824e-6d72c5e57a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23055
47943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2305547943
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3262994456
Short name T2379
Test name
Test status
Simulation time 184166185 ps
CPU time 0.82 seconds
Started Jul 12 05:26:40 PM PDT 24
Finished Jul 12 05:26:43 PM PDT 24
Peak memory 206804 kb
Host smart-f894bc82-58cf-4938-8e43-41c18aa32b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32629
94456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3262994456
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1953373976
Short name T244
Test name
Test status
Simulation time 23316307921 ps
CPU time 25.06 seconds
Started Jul 12 05:26:40 PM PDT 24
Finished Jul 12 05:27:07 PM PDT 24
Peak memory 206868 kb
Host smart-7fc54a51-7295-479a-a763-8f77d0835155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533
73976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1953373976
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2355689781
Short name T1301
Test name
Test status
Simulation time 3307904617 ps
CPU time 3.98 seconds
Started Jul 12 05:26:40 PM PDT 24
Finished Jul 12 05:26:46 PM PDT 24
Peak memory 206900 kb
Host smart-6548f092-8007-4f1a-b652-c732a4c35ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23556
89781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2355689781
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1975904143
Short name T1912
Test name
Test status
Simulation time 8757567995 ps
CPU time 229.02 seconds
Started Jul 12 05:26:40 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 207080 kb
Host smart-fe12ef40-f2d3-4657-826f-12fa5ded9828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19759
04143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1975904143
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2830819394
Short name T1885
Test name
Test status
Simulation time 4337729254 ps
CPU time 31.91 seconds
Started Jul 12 05:26:39 PM PDT 24
Finished Jul 12 05:27:13 PM PDT 24
Peak memory 207024 kb
Host smart-4c791532-a9eb-4d2e-aa60-5874d2111c15
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2830819394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2830819394
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3134871703
Short name T2229
Test name
Test status
Simulation time 240928938 ps
CPU time 0.96 seconds
Started Jul 12 05:26:47 PM PDT 24
Finished Jul 12 05:26:50 PM PDT 24
Peak memory 206820 kb
Host smart-9ab8ac82-a84b-459f-a17d-057e631bfe77
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3134871703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3134871703
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1833229946
Short name T2691
Test name
Test status
Simulation time 231035945 ps
CPU time 0.92 seconds
Started Jul 12 05:26:44 PM PDT 24
Finished Jul 12 05:26:47 PM PDT 24
Peak memory 206696 kb
Host smart-f3ea9cdc-66b6-490f-8cb2-16c8c8da9465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
29946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1833229946
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1263708379
Short name T2504
Test name
Test status
Simulation time 5857968136 ps
CPU time 40.63 seconds
Started Jul 12 05:26:54 PM PDT 24
Finished Jul 12 05:27:36 PM PDT 24
Peak memory 207088 kb
Host smart-f9e4a7f4-3a9a-4397-8e2d-16d69312b426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12637
08379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1263708379
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3906012094
Short name T2380
Test name
Test status
Simulation time 6356069029 ps
CPU time 171.24 seconds
Started Jul 12 05:26:52 PM PDT 24
Finished Jul 12 05:29:45 PM PDT 24
Peak memory 206952 kb
Host smart-e2dd4bd7-faee-4d96-bc6e-fee6cc337cf5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3906012094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3906012094
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2446160256
Short name T2659
Test name
Test status
Simulation time 167880697 ps
CPU time 0.83 seconds
Started Jul 12 05:26:42 PM PDT 24
Finished Jul 12 05:26:45 PM PDT 24
Peak memory 206772 kb
Host smart-ff019ed0-e377-42d5-9d64-a1a313be301d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2446160256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2446160256
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.518818247
Short name T1068
Test name
Test status
Simulation time 172991554 ps
CPU time 0.84 seconds
Started Jul 12 05:26:43 PM PDT 24
Finished Jul 12 05:26:46 PM PDT 24
Peak memory 206776 kb
Host smart-d2e02f5d-d091-4a32-862b-8070c282ccb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51881
8247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.518818247
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.238213991
Short name T2462
Test name
Test status
Simulation time 199550868 ps
CPU time 0.89 seconds
Started Jul 12 05:26:46 PM PDT 24
Finished Jul 12 05:26:49 PM PDT 24
Peak memory 206688 kb
Host smart-19de0db2-eef6-406a-abe6-f157a55b7c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821
3991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.238213991
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3126975474
Short name T425
Test name
Test status
Simulation time 181801131 ps
CPU time 0.88 seconds
Started Jul 12 05:26:42 PM PDT 24
Finished Jul 12 05:26:45 PM PDT 24
Peak memory 206668 kb
Host smart-bfd3a22e-f8b5-4d04-9d2c-5def8dd64b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31269
75474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3126975474
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3288201211
Short name T1206
Test name
Test status
Simulation time 153804545 ps
CPU time 0.8 seconds
Started Jul 12 05:26:46 PM PDT 24
Finished Jul 12 05:26:49 PM PDT 24
Peak memory 206816 kb
Host smart-b53b6229-ab17-488e-b20a-ff6134a97882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32882
01211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3288201211
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3856911468
Short name T2591
Test name
Test status
Simulation time 168427143 ps
CPU time 0.79 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:26:48 PM PDT 24
Peak memory 206816 kb
Host smart-19420721-559c-4ac6-9fe4-87b76316eb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38569
11468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3856911468
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.456268568
Short name T179
Test name
Test status
Simulation time 212321494 ps
CPU time 0.81 seconds
Started Jul 12 05:26:47 PM PDT 24
Finished Jul 12 05:26:50 PM PDT 24
Peak memory 206692 kb
Host smart-17316eef-cb25-4160-afa2-0597e183aa68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45626
8568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.456268568
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3591946279
Short name T1480
Test name
Test status
Simulation time 177530220 ps
CPU time 0.85 seconds
Started Jul 12 05:26:44 PM PDT 24
Finished Jul 12 05:26:47 PM PDT 24
Peak memory 206704 kb
Host smart-4b82637a-4a48-40f3-aaa6-62a56fac3539
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3591946279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3591946279
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2158201389
Short name T197
Test name
Test status
Simulation time 239682757 ps
CPU time 0.96 seconds
Started Jul 12 05:26:48 PM PDT 24
Finished Jul 12 05:26:50 PM PDT 24
Peak memory 206824 kb
Host smart-abe16f03-d34e-4bc4-9649-f2c361b47489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21582
01389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2158201389
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3122541069
Short name T711
Test name
Test status
Simulation time 143595574 ps
CPU time 0.79 seconds
Started Jul 12 05:26:41 PM PDT 24
Finished Jul 12 05:26:44 PM PDT 24
Peak memory 206920 kb
Host smart-c545f5d1-7093-40ea-a1b6-0a193a0ac873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31225
41069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3122541069
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1094912219
Short name T1109
Test name
Test status
Simulation time 37347693 ps
CPU time 0.66 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:26:48 PM PDT 24
Peak memory 206828 kb
Host smart-f6e7f4eb-f0e3-471d-9525-6474abd06016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10949
12219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1094912219
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.992014925
Short name T989
Test name
Test status
Simulation time 6771560088 ps
CPU time 17.51 seconds
Started Jul 12 05:26:48 PM PDT 24
Finished Jul 12 05:27:07 PM PDT 24
Peak memory 207064 kb
Host smart-8c95c7fb-8cb1-485e-9ffe-6a9a44b2d432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99201
4925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.992014925
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1351561981
Short name T1827
Test name
Test status
Simulation time 190767945 ps
CPU time 0.84 seconds
Started Jul 12 05:31:52 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 206768 kb
Host smart-c2b527dc-d22f-4f28-a03c-01a4929005c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13515
61981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1351561981
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1847309675
Short name T2745
Test name
Test status
Simulation time 181938470 ps
CPU time 0.84 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:26:48 PM PDT 24
Peak memory 206820 kb
Host smart-2b5b9715-a52e-4216-81fc-28ba0897a7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18473
09675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1847309675
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.4270888475
Short name T2671
Test name
Test status
Simulation time 10507295933 ps
CPU time 88.98 seconds
Started Jul 12 05:26:42 PM PDT 24
Finished Jul 12 05:28:13 PM PDT 24
Peak memory 206876 kb
Host smart-587602e8-1d31-456f-aaba-6336e0077f16
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4270888475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.4270888475
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2237771818
Short name T690
Test name
Test status
Simulation time 8898019890 ps
CPU time 245.52 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206948 kb
Host smart-4ead8fc0-a68b-420e-b62f-aa1a3e2d3ca8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2237771818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2237771818
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.175192534
Short name T951
Test name
Test status
Simulation time 14782889304 ps
CPU time 99.75 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:28:27 PM PDT 24
Peak memory 207056 kb
Host smart-c6edc3bb-1ef1-4453-8e2b-b06dea22eef1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=175192534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.175192534
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2719685877
Short name T2586
Test name
Test status
Simulation time 198946738 ps
CPU time 0.87 seconds
Started Jul 12 05:26:44 PM PDT 24
Finished Jul 12 05:26:47 PM PDT 24
Peak memory 206820 kb
Host smart-75cf0a4f-3d9d-4aa2-b829-7e5a595d6561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27196
85877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2719685877
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.86827554
Short name T452
Test name
Test status
Simulation time 174113380 ps
CPU time 0.89 seconds
Started Jul 12 05:26:42 PM PDT 24
Finished Jul 12 05:26:45 PM PDT 24
Peak memory 206816 kb
Host smart-91078331-fb5b-41ba-940d-211176fbc849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86827
554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.86827554
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3078262372
Short name T1126
Test name
Test status
Simulation time 177533227 ps
CPU time 0.85 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:26:49 PM PDT 24
Peak memory 206808 kb
Host smart-32157958-14a4-4372-b1bb-5c4c164e086b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30782
62372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3078262372
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.455984780
Short name T69
Test name
Test status
Simulation time 213985277 ps
CPU time 0.92 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:26:48 PM PDT 24
Peak memory 206816 kb
Host smart-93db1381-fbfa-406f-b513-2ff1a23ac68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45598
4780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.455984780
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2309735512
Short name T192
Test name
Test status
Simulation time 408299028 ps
CPU time 1.29 seconds
Started Jul 12 05:26:47 PM PDT 24
Finished Jul 12 05:26:50 PM PDT 24
Peak memory 225528 kb
Host smart-1d53903a-00bd-48e8-8c33-7de2547b7002
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2309735512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2309735512
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.2726837622
Short name T47
Test name
Test status
Simulation time 385284037 ps
CPU time 1.17 seconds
Started Jul 12 05:26:44 PM PDT 24
Finished Jul 12 05:26:47 PM PDT 24
Peak memory 206820 kb
Host smart-0c8b547a-b159-44a9-8b05-79d0a43b886d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268
37622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.2726837622
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2904107104
Short name T1871
Test name
Test status
Simulation time 202720019 ps
CPU time 0.89 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:26:49 PM PDT 24
Peak memory 206800 kb
Host smart-7f2cff56-018d-4e65-92b3-a185b75adf93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29041
07104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2904107104
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2188029952
Short name T2123
Test name
Test status
Simulation time 153490110 ps
CPU time 0.73 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:53 PM PDT 24
Peak memory 206676 kb
Host smart-c25d2c86-882b-4059-8f77-963bed73281f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21880
29952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2188029952
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.292219986
Short name T843
Test name
Test status
Simulation time 150757787 ps
CPU time 0.76 seconds
Started Jul 12 05:26:46 PM PDT 24
Finished Jul 12 05:26:49 PM PDT 24
Peak memory 206796 kb
Host smart-fd901ded-e38c-488f-8592-66086c6c1226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29221
9986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.292219986
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2609828799
Short name T2527
Test name
Test status
Simulation time 236771322 ps
CPU time 0.94 seconds
Started Jul 12 05:26:41 PM PDT 24
Finished Jul 12 05:26:44 PM PDT 24
Peak memory 206712 kb
Host smart-18fa8980-75ee-41d1-848e-87fe601e89b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
28799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2609828799
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.1416062317
Short name T1979
Test name
Test status
Simulation time 5781926182 ps
CPU time 41.68 seconds
Started Jul 12 05:26:43 PM PDT 24
Finished Jul 12 05:27:27 PM PDT 24
Peak memory 207080 kb
Host smart-40a8c3ee-4ebb-4169-8b6c-57da1cf1b39f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1416062317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.1416062317
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1920408631
Short name T2535
Test name
Test status
Simulation time 162026715 ps
CPU time 0.79 seconds
Started Jul 12 05:26:48 PM PDT 24
Finished Jul 12 05:26:50 PM PDT 24
Peak memory 206832 kb
Host smart-a7521cba-5dcd-466c-98bb-bf5d1d8f6b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19204
08631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1920408631
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.4027484429
Short name T2450
Test name
Test status
Simulation time 157700224 ps
CPU time 0.78 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:53 PM PDT 24
Peak memory 206768 kb
Host smart-d698e33b-2d85-41c0-9bc0-461a20b17fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40274
84429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.4027484429
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3388884703
Short name T1316
Test name
Test status
Simulation time 1252127053 ps
CPU time 2.67 seconds
Started Jul 12 05:26:52 PM PDT 24
Finished Jul 12 05:26:56 PM PDT 24
Peak memory 206820 kb
Host smart-feaa3be0-a7c0-4a5a-b5b2-093dfab89539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33888
84703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3388884703
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.136950849
Short name T1725
Test name
Test status
Simulation time 4898773180 ps
CPU time 44.21 seconds
Started Jul 12 05:26:43 PM PDT 24
Finished Jul 12 05:27:29 PM PDT 24
Peak memory 206956 kb
Host smart-7232892d-6f0e-4432-b8a7-c436f798d793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13695
0849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.136950849
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.37315448
Short name T1000
Test name
Test status
Simulation time 47456862 ps
CPU time 0.7 seconds
Started Jul 12 05:31:03 PM PDT 24
Finished Jul 12 05:31:06 PM PDT 24
Peak memory 206804 kb
Host smart-7cceb5be-755a-479c-bf37-497608e2addc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=37315448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.37315448
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2826121967
Short name T1128
Test name
Test status
Simulation time 3668678776 ps
CPU time 4.61 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206860 kb
Host smart-7a445c14-37cd-4012-9f80-5416951f5661
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2826121967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2826121967
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.4156660134
Short name T731
Test name
Test status
Simulation time 13378584190 ps
CPU time 13.86 seconds
Started Jul 12 05:30:53 PM PDT 24
Finished Jul 12 05:31:10 PM PDT 24
Peak memory 206892 kb
Host smart-7a1b25cb-ed32-4323-8966-940b2cb4aef5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4156660134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.4156660134
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2926760627
Short name T415
Test name
Test status
Simulation time 23338179958 ps
CPU time 26.87 seconds
Started Jul 12 05:30:48 PM PDT 24
Finished Jul 12 05:31:17 PM PDT 24
Peak memory 207072 kb
Host smart-b71a1347-6a64-445d-b1f1-ae944e07b650
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2926760627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.2926760627
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.4090836319
Short name T747
Test name
Test status
Simulation time 159121466 ps
CPU time 0.78 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:30:54 PM PDT 24
Peak memory 206700 kb
Host smart-f65b1b1e-49e3-4057-ab35-07ae077b08a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40908
36319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.4090836319
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1648046981
Short name T1306
Test name
Test status
Simulation time 193994842 ps
CPU time 0.81 seconds
Started Jul 12 05:31:11 PM PDT 24
Finished Jul 12 05:31:14 PM PDT 24
Peak memory 206716 kb
Host smart-3963ee70-213d-4280-8673-338d16ed6f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16480
46981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1648046981
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1906754730
Short name T2329
Test name
Test status
Simulation time 367105127 ps
CPU time 1.28 seconds
Started Jul 12 05:30:48 PM PDT 24
Finished Jul 12 05:30:51 PM PDT 24
Peak memory 206812 kb
Host smart-2e6d557c-fafb-4532-895a-c19d2e8f397d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19067
54730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1906754730
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.556465778
Short name T1230
Test name
Test status
Simulation time 878324879 ps
CPU time 2.39 seconds
Started Jul 12 05:30:56 PM PDT 24
Finished Jul 12 05:31:02 PM PDT 24
Peak memory 207032 kb
Host smart-443c4fed-2765-47d7-b639-a604fe24ee45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55646
5778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.556465778
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.475650493
Short name T924
Test name
Test status
Simulation time 6692431616 ps
CPU time 13.03 seconds
Started Jul 12 05:31:00 PM PDT 24
Finished Jul 12 05:31:15 PM PDT 24
Peak memory 207088 kb
Host smart-d8cd9333-6ed0-4416-b913-457b43ffcada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47565
0493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.475650493
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1261958682
Short name T1120
Test name
Test status
Simulation time 467645455 ps
CPU time 1.38 seconds
Started Jul 12 05:31:01 PM PDT 24
Finished Jul 12 05:31:05 PM PDT 24
Peak memory 206816 kb
Host smart-cefbe43c-a1b3-45c4-bd53-396f57778cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12619
58682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1261958682
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3737368411
Short name T2531
Test name
Test status
Simulation time 164109149 ps
CPU time 0.77 seconds
Started Jul 12 05:30:54 PM PDT 24
Finished Jul 12 05:30:58 PM PDT 24
Peak memory 206812 kb
Host smart-96f8c2df-ecec-425d-be0e-cde9662a2dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37373
68411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3737368411
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2586929984
Short name T2359
Test name
Test status
Simulation time 42010244 ps
CPU time 0.65 seconds
Started Jul 12 05:30:52 PM PDT 24
Finished Jul 12 05:30:55 PM PDT 24
Peak memory 206804 kb
Host smart-96fd24aa-8722-46b9-8826-66dc3b3de9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
29984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2586929984
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3076861916
Short name T2451
Test name
Test status
Simulation time 845524297 ps
CPU time 2.24 seconds
Started Jul 12 05:30:55 PM PDT 24
Finished Jul 12 05:31:00 PM PDT 24
Peak memory 207040 kb
Host smart-87b4c00d-9816-4e7b-a378-d8cc2cd92ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30768
61916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3076861916
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1056711044
Short name T17
Test name
Test status
Simulation time 172468049 ps
CPU time 1.65 seconds
Started Jul 12 05:31:56 PM PDT 24
Finished Jul 12 05:32:01 PM PDT 24
Peak memory 206944 kb
Host smart-39b7892d-aa29-4a5a-a4a8-8c1bf24433cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
11044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1056711044
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.4067329957
Short name T2177
Test name
Test status
Simulation time 170236233 ps
CPU time 0.81 seconds
Started Jul 12 05:30:59 PM PDT 24
Finished Jul 12 05:31:02 PM PDT 24
Peak memory 206672 kb
Host smart-60d39a8c-746e-496e-aca6-d7a0d60f39c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40673
29957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.4067329957
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.285397071
Short name T2288
Test name
Test status
Simulation time 136457183 ps
CPU time 0.73 seconds
Started Jul 12 05:31:03 PM PDT 24
Finished Jul 12 05:31:05 PM PDT 24
Peak memory 206812 kb
Host smart-b507c71a-d51a-4943-9e6e-52f187a99350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
7071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.285397071
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2294897149
Short name T2128
Test name
Test status
Simulation time 163919382 ps
CPU time 0.96 seconds
Started Jul 12 05:31:03 PM PDT 24
Finished Jul 12 05:31:06 PM PDT 24
Peak memory 206792 kb
Host smart-64445983-e371-48b5-a6eb-66db77c523a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22948
97149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2294897149
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.286596216
Short name T1894
Test name
Test status
Simulation time 6781391274 ps
CPU time 48.41 seconds
Started Jul 12 05:30:51 PM PDT 24
Finished Jul 12 05:31:41 PM PDT 24
Peak memory 207068 kb
Host smart-aabe89d1-abe3-4d74-aee9-c04c800a86aa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=286596216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.286596216
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1710452176
Short name T1058
Test name
Test status
Simulation time 256470236 ps
CPU time 0.92 seconds
Started Jul 12 05:31:00 PM PDT 24
Finished Jul 12 05:31:03 PM PDT 24
Peak memory 206760 kb
Host smart-0695f532-2999-4475-b4f3-6a8fda37755f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17104
52176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1710452176
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.651452772
Short name T930
Test name
Test status
Simulation time 23337417408 ps
CPU time 21.94 seconds
Started Jul 12 05:31:02 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 206876 kb
Host smart-dddc7485-e48f-4ba1-a6fe-b4b71f2d556b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65145
2772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.651452772
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3702630700
Short name T556
Test name
Test status
Simulation time 3323434796 ps
CPU time 3.87 seconds
Started Jul 12 05:31:01 PM PDT 24
Finished Jul 12 05:31:07 PM PDT 24
Peak memory 206700 kb
Host smart-e5158314-c881-4202-8702-0141a6e762aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37026
30700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3702630700
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1321917810
Short name T2484
Test name
Test status
Simulation time 10787048885 ps
CPU time 94.86 seconds
Started Jul 12 05:31:04 PM PDT 24
Finished Jul 12 05:32:41 PM PDT 24
Peak memory 207084 kb
Host smart-d13c4447-15ea-4000-a942-76f18777f782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13219
17810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1321917810
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1307689522
Short name T1166
Test name
Test status
Simulation time 3645172473 ps
CPU time 24.98 seconds
Started Jul 12 05:30:59 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 207080 kb
Host smart-4479a2f0-5832-48c1-aebc-5a1c5c32f05e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1307689522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1307689522
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2780548192
Short name T2132
Test name
Test status
Simulation time 324883867 ps
CPU time 0.97 seconds
Started Jul 12 05:31:05 PM PDT 24
Finished Jul 12 05:31:07 PM PDT 24
Peak memory 206816 kb
Host smart-68a985bc-cedf-47b4-97f3-af2c2899068e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2780548192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2780548192
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3383976876
Short name T919
Test name
Test status
Simulation time 207245298 ps
CPU time 0.87 seconds
Started Jul 12 05:31:00 PM PDT 24
Finished Jul 12 05:31:03 PM PDT 24
Peak memory 206820 kb
Host smart-a92a6115-0a6a-44bc-9993-b2ea838a2484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33839
76876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3383976876
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.4248762603
Short name T1479
Test name
Test status
Simulation time 4189113709 ps
CPU time 110.88 seconds
Started Jul 12 05:31:01 PM PDT 24
Finished Jul 12 05:32:54 PM PDT 24
Peak memory 206880 kb
Host smart-900a6b1f-d5c7-4511-9f76-7d8dfcd7974c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
62603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.4248762603
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1078281370
Short name T790
Test name
Test status
Simulation time 5372012233 ps
CPU time 51.9 seconds
Started Jul 12 05:31:02 PM PDT 24
Finished Jul 12 05:31:56 PM PDT 24
Peak memory 206992 kb
Host smart-9bd58808-1ec9-4e78-9174-a8458272fe6a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1078281370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1078281370
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3442216689
Short name T554
Test name
Test status
Simulation time 196260882 ps
CPU time 0.83 seconds
Started Jul 12 05:30:55 PM PDT 24
Finished Jul 12 05:30:59 PM PDT 24
Peak memory 206812 kb
Host smart-e1a7ed3b-861a-425e-92cf-82a015a1131c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3442216689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3442216689
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1895367021
Short name T998
Test name
Test status
Simulation time 148533182 ps
CPU time 0.8 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 206816 kb
Host smart-fc35306f-808b-477b-baa8-ad1d6d6f3390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18953
67021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1895367021
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1381820265
Short name T122
Test name
Test status
Simulation time 196168966 ps
CPU time 0.84 seconds
Started Jul 12 05:31:04 PM PDT 24
Finished Jul 12 05:31:06 PM PDT 24
Peak memory 206816 kb
Host smart-4e923086-5712-4b16-a190-e998b4bbc38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13818
20265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1381820265
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1242071288
Short name T1427
Test name
Test status
Simulation time 176414017 ps
CPU time 0.89 seconds
Started Jul 12 05:31:00 PM PDT 24
Finished Jul 12 05:31:03 PM PDT 24
Peak memory 206812 kb
Host smart-1836a105-144d-495b-bace-8f5ed61110a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12420
71288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1242071288
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2077438232
Short name T1634
Test name
Test status
Simulation time 168848651 ps
CPU time 0.87 seconds
Started Jul 12 05:30:56 PM PDT 24
Finished Jul 12 05:31:01 PM PDT 24
Peak memory 206804 kb
Host smart-e0147e0b-ac63-4eed-8c7f-b2cd6753c184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20774
38232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2077438232
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2564124198
Short name T1295
Test name
Test status
Simulation time 168274717 ps
CPU time 0.79 seconds
Started Jul 12 05:31:06 PM PDT 24
Finished Jul 12 05:31:08 PM PDT 24
Peak memory 206820 kb
Host smart-e302a430-6fac-4721-9856-f1d1c69093a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25641
24198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2564124198
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3039634825
Short name T769
Test name
Test status
Simulation time 207831777 ps
CPU time 0.84 seconds
Started Jul 12 05:31:07 PM PDT 24
Finished Jul 12 05:31:09 PM PDT 24
Peak memory 206816 kb
Host smart-8410e4f5-02f4-459a-a6a6-715b2072fc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30396
34825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3039634825
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.2707459493
Short name T1977
Test name
Test status
Simulation time 205779590 ps
CPU time 0.94 seconds
Started Jul 12 05:31:09 PM PDT 24
Finished Jul 12 05:31:11 PM PDT 24
Peak memory 206828 kb
Host smart-f77d0e17-3693-46e5-8a10-9968fc39f2e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2707459493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.2707459493
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2457865543
Short name T1643
Test name
Test status
Simulation time 141715704 ps
CPU time 0.8 seconds
Started Jul 12 05:31:02 PM PDT 24
Finished Jul 12 05:31:05 PM PDT 24
Peak memory 206812 kb
Host smart-27734b87-beed-4f39-82ae-13bf17ceb4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24578
65543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2457865543
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3770850226
Short name T2306
Test name
Test status
Simulation time 42781477 ps
CPU time 0.66 seconds
Started Jul 12 05:31:02 PM PDT 24
Finished Jul 12 05:31:05 PM PDT 24
Peak memory 206812 kb
Host smart-3cb54dd4-be94-4e9f-88da-0c1f59c63bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37708
50226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3770850226
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3764026493
Short name T1223
Test name
Test status
Simulation time 6916670103 ps
CPU time 15.76 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:27 PM PDT 24
Peak memory 207064 kb
Host smart-95cdabe5-532d-4d8c-8a44-96724c57099a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37640
26493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3764026493
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2089460732
Short name T2146
Test name
Test status
Simulation time 188713554 ps
CPU time 0.94 seconds
Started Jul 12 05:31:07 PM PDT 24
Finished Jul 12 05:31:10 PM PDT 24
Peak memory 206812 kb
Host smart-a3a7a5ee-fa8a-44a6-934e-5886069d3ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20894
60732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2089460732
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3520973043
Short name T2367
Test name
Test status
Simulation time 232121715 ps
CPU time 0.94 seconds
Started Jul 12 05:31:00 PM PDT 24
Finished Jul 12 05:31:03 PM PDT 24
Peak memory 206692 kb
Host smart-eb8ae301-9742-45a3-8ff2-19a438484960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35209
73043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3520973043
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.732942657
Short name T1829
Test name
Test status
Simulation time 157566422 ps
CPU time 0.78 seconds
Started Jul 12 05:31:00 PM PDT 24
Finished Jul 12 05:31:03 PM PDT 24
Peak memory 206672 kb
Host smart-4602f218-88d1-4c32-934c-77d52f0e9384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73294
2657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.732942657
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2589267671
Short name T2455
Test name
Test status
Simulation time 168002996 ps
CPU time 0.82 seconds
Started Jul 12 05:31:08 PM PDT 24
Finished Jul 12 05:31:10 PM PDT 24
Peak memory 206808 kb
Host smart-83650c65-79ea-4984-bd45-ed6210fc8405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25892
67671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2589267671
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3555440281
Short name T1999
Test name
Test status
Simulation time 144206632 ps
CPU time 0.77 seconds
Started Jul 12 05:31:06 PM PDT 24
Finished Jul 12 05:31:07 PM PDT 24
Peak memory 206812 kb
Host smart-c78a0476-fd50-4d8a-9e39-56f0a5d787be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35554
40281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3555440281
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1716954987
Short name T151
Test name
Test status
Simulation time 163985564 ps
CPU time 0.82 seconds
Started Jul 12 05:31:02 PM PDT 24
Finished Jul 12 05:31:05 PM PDT 24
Peak memory 206716 kb
Host smart-ad91be90-517b-40ee-9da2-f4c8fcba996f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169
54987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1716954987
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2335519027
Short name T2124
Test name
Test status
Simulation time 176691900 ps
CPU time 0.88 seconds
Started Jul 12 05:30:59 PM PDT 24
Finished Jul 12 05:31:02 PM PDT 24
Peak memory 206772 kb
Host smart-d09b52ab-25be-4f62-9320-23239a9b22d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23355
19027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2335519027
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1929419756
Short name T1169
Test name
Test status
Simulation time 303162516 ps
CPU time 1 seconds
Started Jul 12 05:31:01 PM PDT 24
Finished Jul 12 05:31:04 PM PDT 24
Peak memory 206632 kb
Host smart-9c91d937-687c-46d8-9504-b998aa074469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19294
19756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1929419756
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.755050081
Short name T424
Test name
Test status
Simulation time 4092834064 ps
CPU time 29.08 seconds
Started Jul 12 05:31:02 PM PDT 24
Finished Jul 12 05:31:33 PM PDT 24
Peak memory 206992 kb
Host smart-e5d4dc9a-da3f-48d9-91ce-e3ad104a9833
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=755050081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.755050081
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3590530775
Short name T1944
Test name
Test status
Simulation time 147820064 ps
CPU time 0.8 seconds
Started Jul 12 05:31:00 PM PDT 24
Finished Jul 12 05:31:03 PM PDT 24
Peak memory 206684 kb
Host smart-1554f6c1-1c82-4f49-b69b-862f7aee699f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
30775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3590530775
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.681346559
Short name T1861
Test name
Test status
Simulation time 205994953 ps
CPU time 0.9 seconds
Started Jul 12 05:31:07 PM PDT 24
Finished Jul 12 05:31:09 PM PDT 24
Peak memory 206668 kb
Host smart-110f5ef7-a122-4aa4-9f98-168bfb850721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68134
6559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.681346559
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3890586098
Short name T2111
Test name
Test status
Simulation time 771180032 ps
CPU time 1.86 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 206984 kb
Host smart-d66fd3af-0d7c-4bf6-b95f-ffcfc9bde276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38905
86098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3890586098
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2595341261
Short name T2176
Test name
Test status
Simulation time 3048209525 ps
CPU time 83.22 seconds
Started Jul 12 05:31:09 PM PDT 24
Finished Jul 12 05:32:34 PM PDT 24
Peak memory 207008 kb
Host smart-638fa36c-4c54-4bcc-86e8-bef57e85a78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25953
41261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2595341261
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2167114848
Short name T853
Test name
Test status
Simulation time 38839888 ps
CPU time 0.69 seconds
Started Jul 12 05:31:11 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 206844 kb
Host smart-02ac8225-b4b3-440c-812f-965735404e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2167114848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2167114848
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2129465610
Short name T1449
Test name
Test status
Simulation time 3934115647 ps
CPU time 5.52 seconds
Started Jul 12 05:31:09 PM PDT 24
Finished Jul 12 05:31:16 PM PDT 24
Peak memory 207016 kb
Host smart-100c0918-cee6-429a-aa88-1deea0d9a1ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2129465610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2129465610
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2271733783
Short name T600
Test name
Test status
Simulation time 13331974948 ps
CPU time 11.96 seconds
Started Jul 12 05:31:13 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 207028 kb
Host smart-815cb028-a5ba-4082-b652-f4aef73c12c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2271733783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2271733783
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3019911489
Short name T2693
Test name
Test status
Simulation time 23418134338 ps
CPU time 24.14 seconds
Started Jul 12 05:31:08 PM PDT 24
Finished Jul 12 05:31:33 PM PDT 24
Peak memory 207084 kb
Host smart-cfea32b9-057e-4a06-9ab0-39cabb72481f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3019911489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.3019911489
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.901957222
Short name T2617
Test name
Test status
Simulation time 153372552 ps
CPU time 0.85 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:12 PM PDT 24
Peak memory 206816 kb
Host smart-b6e63f6f-2719-46dd-b666-ba3b583143fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90195
7222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.901957222
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.235691492
Short name T401
Test name
Test status
Simulation time 140077672 ps
CPU time 0.77 seconds
Started Jul 12 05:31:11 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 206808 kb
Host smart-7d406f68-148d-4b05-be69-459968d31fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23569
1492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.235691492
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2985122464
Short name T1323
Test name
Test status
Simulation time 598171992 ps
CPU time 1.85 seconds
Started Jul 12 05:31:08 PM PDT 24
Finished Jul 12 05:31:11 PM PDT 24
Peak memory 206836 kb
Host smart-5b11f68f-868e-4fb0-82ec-a39e160e82bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29851
22464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2985122464
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.332537407
Short name T969
Test name
Test status
Simulation time 733601302 ps
CPU time 1.85 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 207236 kb
Host smart-d553dfdb-c935-490a-9188-e7a8e67fcd30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33253
7407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.332537407
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3902499890
Short name T2158
Test name
Test status
Simulation time 20717039470 ps
CPU time 41.37 seconds
Started Jul 12 05:31:09 PM PDT 24
Finished Jul 12 05:31:51 PM PDT 24
Peak memory 207080 kb
Host smart-fb19c236-d705-43ac-b381-9a592a9857d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39024
99890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3902499890
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.954213868
Short name T2347
Test name
Test status
Simulation time 497846125 ps
CPU time 1.41 seconds
Started Jul 12 05:31:07 PM PDT 24
Finished Jul 12 05:31:10 PM PDT 24
Peak memory 206724 kb
Host smart-ae08ef45-f733-4513-8966-b7e47e180c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95421
3868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.954213868
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3471299537
Short name T1769
Test name
Test status
Simulation time 150944793 ps
CPU time 0.84 seconds
Started Jul 12 05:31:04 PM PDT 24
Finished Jul 12 05:31:07 PM PDT 24
Peak memory 206720 kb
Host smart-2b723172-84d9-4872-abd6-c7f4f4b91b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34712
99537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3471299537
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2662692516
Short name T1022
Test name
Test status
Simulation time 47749435 ps
CPU time 0.68 seconds
Started Jul 12 05:31:15 PM PDT 24
Finished Jul 12 05:31:17 PM PDT 24
Peak memory 206804 kb
Host smart-0765daf3-399b-40fe-b4dc-6aa43faea331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26626
92516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2662692516
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3605810396
Short name T2608
Test name
Test status
Simulation time 871148558 ps
CPU time 2.12 seconds
Started Jul 12 05:31:05 PM PDT 24
Finished Jul 12 05:31:08 PM PDT 24
Peak memory 206968 kb
Host smart-8d7c20b5-432e-4471-b5ed-e51c36c8edaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36058
10396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3605810396
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.282379334
Short name T372
Test name
Test status
Simulation time 254962345 ps
CPU time 1.35 seconds
Started Jul 12 05:39:24 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 206984 kb
Host smart-180e63d1-dc8b-4f37-aa3e-7b7f756e0a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237
9334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.282379334
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1891204796
Short name T1474
Test name
Test status
Simulation time 185175789 ps
CPU time 0.85 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 206524 kb
Host smart-0d11d944-26c3-4072-bfb3-7e9a33b6cc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18912
04796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1891204796
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.162204003
Short name T584
Test name
Test status
Simulation time 141102989 ps
CPU time 0.82 seconds
Started Jul 12 05:31:06 PM PDT 24
Finished Jul 12 05:31:08 PM PDT 24
Peak memory 206824 kb
Host smart-1512a5e4-b5fc-4df7-83d6-9cb248e4d68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16220
4003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.162204003
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3843799864
Short name T1798
Test name
Test status
Simulation time 250430461 ps
CPU time 1.01 seconds
Started Jul 12 05:31:03 PM PDT 24
Finished Jul 12 05:31:06 PM PDT 24
Peak memory 206692 kb
Host smart-77866ee1-e32f-41ec-a20a-26b7ced3a795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38437
99864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3843799864
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.112937128
Short name T1554
Test name
Test status
Simulation time 8327343066 ps
CPU time 78.57 seconds
Started Jul 12 05:31:05 PM PDT 24
Finished Jul 12 05:32:25 PM PDT 24
Peak memory 207032 kb
Host smart-c6b9a0e4-6025-4890-b252-41d23d83e573
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=112937128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.112937128
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.529518407
Short name T2557
Test name
Test status
Simulation time 5335534605 ps
CPU time 44.82 seconds
Started Jul 12 05:31:09 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 207064 kb
Host smart-86dbc130-f402-475b-96f8-f3e9cb012075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52951
8407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.529518407
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1917107069
Short name T2335
Test name
Test status
Simulation time 243867015 ps
CPU time 0.92 seconds
Started Jul 12 05:31:09 PM PDT 24
Finished Jul 12 05:31:11 PM PDT 24
Peak memory 206696 kb
Host smart-cbe3d777-16e7-4a09-8644-08139e432d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19171
07069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1917107069
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.861496235
Short name T2256
Test name
Test status
Simulation time 23342397373 ps
CPU time 23.74 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 206864 kb
Host smart-91b58cd2-a549-4964-9a34-65c622874b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86149
6235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.861496235
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3538571508
Short name T2476
Test name
Test status
Simulation time 3348242929 ps
CPU time 3.77 seconds
Started Jul 12 05:31:07 PM PDT 24
Finished Jul 12 05:31:12 PM PDT 24
Peak memory 206784 kb
Host smart-b72deb54-8f05-4f10-91b6-baebdffcb6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35385
71508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3538571508
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1356338476
Short name T1279
Test name
Test status
Simulation time 7635941031 ps
CPU time 211.73 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:34:43 PM PDT 24
Peak memory 207100 kb
Host smart-dbc2c014-5d2b-4f1d-88e7-dc07f4e3da63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13563
38476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1356338476
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.624018778
Short name T1305
Test name
Test status
Simulation time 3364662121 ps
CPU time 30.58 seconds
Started Jul 12 05:31:07 PM PDT 24
Finished Jul 12 05:31:39 PM PDT 24
Peak memory 207016 kb
Host smart-24695422-9ede-4dec-805f-a462f3a01380
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=624018778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.624018778
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3745494420
Short name T778
Test name
Test status
Simulation time 245173086 ps
CPU time 0.88 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:14 PM PDT 24
Peak memory 206788 kb
Host smart-ed17b3a7-aa0f-4596-9493-2d2e1bcc4682
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3745494420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3745494420
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1761252903
Short name T1347
Test name
Test status
Simulation time 182582173 ps
CPU time 0.84 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:15 PM PDT 24
Peak memory 206804 kb
Host smart-127f38ca-e983-4f79-920b-4526f4ce6299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17612
52903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1761252903
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.114350050
Short name T2253
Test name
Test status
Simulation time 5260602758 ps
CPU time 37.71 seconds
Started Jul 12 05:31:06 PM PDT 24
Finished Jul 12 05:31:45 PM PDT 24
Peak memory 207080 kb
Host smart-9634eddc-f490-44a3-8177-c4d3a6714a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11435
0050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.114350050
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2183186351
Short name T489
Test name
Test status
Simulation time 6059698693 ps
CPU time 43.33 seconds
Started Jul 12 05:31:06 PM PDT 24
Finished Jul 12 05:31:51 PM PDT 24
Peak memory 207064 kb
Host smart-ad1104bc-6012-476f-ae88-e49d1e3ee663
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2183186351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2183186351
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1257938280
Short name T2579
Test name
Test status
Simulation time 152487323 ps
CPU time 0.76 seconds
Started Jul 12 05:31:05 PM PDT 24
Finished Jul 12 05:31:07 PM PDT 24
Peak memory 206704 kb
Host smart-080c09c3-c664-4306-b6d1-af3464c19905
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1257938280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1257938280
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4174518105
Short name T1900
Test name
Test status
Simulation time 206713208 ps
CPU time 0.88 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:12 PM PDT 24
Peak memory 206828 kb
Host smart-c97af7bd-4bd8-418f-8d8a-ee786bc45e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41745
18105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4174518105
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3725536971
Short name T2211
Test name
Test status
Simulation time 171337615 ps
CPU time 0.84 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:12 PM PDT 24
Peak memory 207020 kb
Host smart-e0df980a-fb57-4969-96e6-12821dad1316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37255
36971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3725536971
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2465363931
Short name T1927
Test name
Test status
Simulation time 166627423 ps
CPU time 0.77 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:14 PM PDT 24
Peak memory 206788 kb
Host smart-98496238-9d8c-4984-990d-ac3fa0299d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24653
63931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2465363931
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2617207099
Short name T1326
Test name
Test status
Simulation time 226888905 ps
CPU time 0.84 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 206832 kb
Host smart-995ccf6f-08e7-451a-aa9e-dcd744992be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26172
07099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2617207099
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.249694897
Short name T1930
Test name
Test status
Simulation time 202933314 ps
CPU time 0.87 seconds
Started Jul 12 05:31:09 PM PDT 24
Finished Jul 12 05:31:11 PM PDT 24
Peak memory 206680 kb
Host smart-3e17a0e1-7d64-4421-9765-35b2eff47315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24969
4897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.249694897
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1632043422
Short name T162
Test name
Test status
Simulation time 162027978 ps
CPU time 0.8 seconds
Started Jul 12 05:31:07 PM PDT 24
Finished Jul 12 05:31:09 PM PDT 24
Peak memory 206824 kb
Host smart-74947482-c11b-4905-aa8f-abb55f7e0475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320
43422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1632043422
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.961437541
Short name T1914
Test name
Test status
Simulation time 210350537 ps
CPU time 0.9 seconds
Started Jul 12 05:31:06 PM PDT 24
Finished Jul 12 05:31:08 PM PDT 24
Peak memory 206796 kb
Host smart-2faf7a58-3869-4df9-b3bc-7c5a80bcbcaa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=961437541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.961437541
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3754262277
Short name T2401
Test name
Test status
Simulation time 144928902 ps
CPU time 0.74 seconds
Started Jul 12 05:31:13 PM PDT 24
Finished Jul 12 05:31:15 PM PDT 24
Peak memory 206808 kb
Host smart-820603ad-472e-4605-bf80-6a219e8dfa61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37542
62277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3754262277
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2301438827
Short name T2471
Test name
Test status
Simulation time 37979604 ps
CPU time 0.66 seconds
Started Jul 12 05:31:09 PM PDT 24
Finished Jul 12 05:31:11 PM PDT 24
Peak memory 206808 kb
Host smart-38cdf846-a3b3-4c65-9ec7-bcb96e54c46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23014
38827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2301438827
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.415449350
Short name T1468
Test name
Test status
Simulation time 22417793673 ps
CPU time 59.83 seconds
Started Jul 12 05:31:07 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 207052 kb
Host smart-f41de18c-d2da-4e7e-83a5-2c1b614a9dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41544
9350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.415449350
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2253446013
Short name T907
Test name
Test status
Simulation time 176039831 ps
CPU time 0.83 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 206300 kb
Host smart-0a9e94b9-d05b-4936-9301-e1d8b909fad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22534
46013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2253446013
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.986871408
Short name T2101
Test name
Test status
Simulation time 200964127 ps
CPU time 0.87 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 206368 kb
Host smart-b918ba13-92a7-4cbd-b328-5c672f403245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98687
1408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.986871408
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1329759270
Short name T2194
Test name
Test status
Simulation time 176888510 ps
CPU time 0.81 seconds
Started Jul 12 05:31:11 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 206824 kb
Host smart-8c94ec0f-b032-47cd-94b7-1ed361c9fd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13297
59270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1329759270
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1892914497
Short name T1519
Test name
Test status
Simulation time 203175599 ps
CPU time 0.88 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 206408 kb
Host smart-30571a11-29f1-4a29-bf61-6e5cf2a66f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18929
14497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1892914497
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.685210827
Short name T2050
Test name
Test status
Simulation time 167888243 ps
CPU time 0.86 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:15 PM PDT 24
Peak memory 206716 kb
Host smart-461f83a3-d3eb-4365-9fb3-bfbad23dddf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68521
0827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.685210827
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1729085911
Short name T1050
Test name
Test status
Simulation time 153458839 ps
CPU time 0.76 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:27 PM PDT 24
Peak memory 206676 kb
Host smart-fbe51209-e7d0-4ea9-ae6f-b0f19f51244b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17290
85911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1729085911
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2724523781
Short name T2328
Test name
Test status
Simulation time 219808268 ps
CPU time 0.81 seconds
Started Jul 12 05:31:13 PM PDT 24
Finished Jul 12 05:31:15 PM PDT 24
Peak memory 206820 kb
Host smart-aa834310-2e39-4749-9467-955545f78e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27245
23781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2724523781
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.4067444443
Short name T1203
Test name
Test status
Simulation time 195312644 ps
CPU time 0.89 seconds
Started Jul 12 05:31:16 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 206768 kb
Host smart-613e8d75-3841-46bb-a923-72214b69d77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40674
44443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.4067444443
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3510588780
Short name T773
Test name
Test status
Simulation time 4702293764 ps
CPU time 132.29 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 207000 kb
Host smart-4bc84da7-fd99-4755-a2ea-eb5f3cdb8766
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3510588780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3510588780
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.249388626
Short name T527
Test name
Test status
Simulation time 179645413 ps
CPU time 0.78 seconds
Started Jul 12 05:31:25 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 206716 kb
Host smart-e47ae1ea-c36a-40b8-b473-9cf9d687fdfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24938
8626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.249388626
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3005022917
Short name T856
Test name
Test status
Simulation time 153864459 ps
CPU time 0.8 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:14 PM PDT 24
Peak memory 206760 kb
Host smart-90e07916-5ac3-4f6a-9f3c-b64aba55092d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30050
22917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3005022917
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.969732077
Short name T1447
Test name
Test status
Simulation time 1372131075 ps
CPU time 2.7 seconds
Started Jul 12 05:31:11 PM PDT 24
Finished Jul 12 05:31:15 PM PDT 24
Peak memory 206984 kb
Host smart-0ac75caf-3457-442c-a099-75c80328a2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96973
2077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.969732077
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2968867516
Short name T2469
Test name
Test status
Simulation time 5305863513 ps
CPU time 38.51 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 207060 kb
Host smart-cfdad6ad-33a1-4dbb-a6ed-8fb90c9346c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29688
67516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2968867516
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.4131753442
Short name T184
Test name
Test status
Simulation time 45890976 ps
CPU time 0.68 seconds
Started Jul 12 05:31:19 PM PDT 24
Finished Jul 12 05:31:20 PM PDT 24
Peak memory 206804 kb
Host smart-fe85239c-4b4a-4d7f-96e6-21d18ded251b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4131753442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.4131753442
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2963679135
Short name T474
Test name
Test status
Simulation time 4172076255 ps
CPU time 4.91 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:31:32 PM PDT 24
Peak memory 207084 kb
Host smart-63788b2f-5ea1-414c-9d4f-61a436f34344
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2963679135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2963679135
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3766589668
Short name T1751
Test name
Test status
Simulation time 13373188989 ps
CPU time 13.13 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:38 PM PDT 24
Peak memory 206880 kb
Host smart-235cc0a1-0f6d-4021-b400-ea1780db8af9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3766589668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3766589668
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1848973671
Short name T2572
Test name
Test status
Simulation time 23352889570 ps
CPU time 21.78 seconds
Started Jul 12 05:31:15 PM PDT 24
Finished Jul 12 05:31:39 PM PDT 24
Peak memory 207088 kb
Host smart-72e3c716-6df9-40bb-bff0-bc73eafc1682
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1848973671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.1848973671
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.925040082
Short name T481
Test name
Test status
Simulation time 150084782 ps
CPU time 0.77 seconds
Started Jul 12 05:31:19 PM PDT 24
Finished Jul 12 05:31:20 PM PDT 24
Peak memory 206812 kb
Host smart-c9462cce-a090-495a-84ee-2df44d2d5628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92504
0082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.925040082
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1409296505
Short name T366
Test name
Test status
Simulation time 221234404 ps
CPU time 0.81 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:15 PM PDT 24
Peak memory 206672 kb
Host smart-f810269b-a3db-46b3-8a1f-bdc9e23c7337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14092
96505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1409296505
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1880453512
Short name T2141
Test name
Test status
Simulation time 258765932 ps
CPU time 1.03 seconds
Started Jul 12 05:31:15 PM PDT 24
Finished Jul 12 05:31:17 PM PDT 24
Peak memory 206924 kb
Host smart-f34e3d52-bc09-4e27-8b96-1edc24af414f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18804
53512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1880453512
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1768029052
Short name T1248
Test name
Test status
Simulation time 466760254 ps
CPU time 1.33 seconds
Started Jul 12 05:31:15 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 206808 kb
Host smart-e4c01a84-d8f8-4b31-a056-80dfc2b78a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17680
29052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1768029052
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.680345663
Short name T1055
Test name
Test status
Simulation time 8742221758 ps
CPU time 16.22 seconds
Started Jul 12 05:31:10 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 207056 kb
Host smart-e032085b-f5b9-48e1-a766-a8679c037974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68034
5663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.680345663
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3522547089
Short name T814
Test name
Test status
Simulation time 331042184 ps
CPU time 1.22 seconds
Started Jul 12 05:31:13 PM PDT 24
Finished Jul 12 05:31:16 PM PDT 24
Peak memory 206820 kb
Host smart-c3a3ae91-67a2-4b8e-b4fa-119e3b7d5cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35225
47089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3522547089
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2350321005
Short name T2041
Test name
Test status
Simulation time 151640260 ps
CPU time 0.75 seconds
Started Jul 12 05:31:33 PM PDT 24
Finished Jul 12 05:31:35 PM PDT 24
Peak memory 206812 kb
Host smart-0d2fa9bc-533c-4377-a338-9c0181626554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23503
21005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2350321005
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.819599504
Short name T1561
Test name
Test status
Simulation time 55011341 ps
CPU time 0.66 seconds
Started Jul 12 05:31:16 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 206808 kb
Host smart-0b37dfd8-e2cb-4795-ac59-fa1466b004cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81959
9504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.819599504
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.732073873
Short name T763
Test name
Test status
Simulation time 1067428038 ps
CPU time 2.37 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 207008 kb
Host smart-7dc0919c-d68c-414e-8d7d-3a8f6d646333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73207
3873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.732073873
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2560321255
Short name T1037
Test name
Test status
Simulation time 215384249 ps
CPU time 1.51 seconds
Started Jul 12 05:31:29 PM PDT 24
Finished Jul 12 05:31:33 PM PDT 24
Peak memory 207028 kb
Host smart-d6030d62-1e0b-4a60-b6e0-08841ffd0b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25603
21255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2560321255
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2021013094
Short name T2165
Test name
Test status
Simulation time 210420528 ps
CPU time 0.85 seconds
Started Jul 12 05:31:17 PM PDT 24
Finished Jul 12 05:31:19 PM PDT 24
Peak memory 206828 kb
Host smart-7446e3c1-68eb-48af-bfd9-6b8a62fb76b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20210
13094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2021013094
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3880643932
Short name T978
Test name
Test status
Simulation time 180609110 ps
CPU time 0.8 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:25 PM PDT 24
Peak memory 206816 kb
Host smart-9dc8139d-0c17-47dc-b28b-87422542f937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806
43932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3880643932
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3639291465
Short name T587
Test name
Test status
Simulation time 162383388 ps
CPU time 0.8 seconds
Started Jul 12 05:31:15 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 206804 kb
Host smart-4de4d859-6a28-4981-a569-dcacca260f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36392
91465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3639291465
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.2277076734
Short name T1571
Test name
Test status
Simulation time 4091706913 ps
CPU time 33.48 seconds
Started Jul 12 05:31:16 PM PDT 24
Finished Jul 12 05:31:51 PM PDT 24
Peak memory 206980 kb
Host smart-25aafb57-cfa4-48da-a791-4c9de1e38841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22770
76734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2277076734
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2661537981
Short name T1249
Test name
Test status
Simulation time 209079640 ps
CPU time 0.88 seconds
Started Jul 12 05:31:27 PM PDT 24
Finished Jul 12 05:31:31 PM PDT 24
Peak memory 206828 kb
Host smart-eb15715e-c985-45cc-89ee-7118a3963d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26615
37981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2661537981
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2861815192
Short name T990
Test name
Test status
Simulation time 23338092917 ps
CPU time 22.28 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:36 PM PDT 24
Peak memory 206856 kb
Host smart-d183c2bb-3edd-47a3-8a4b-1004eeac7ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
15192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2861815192
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3165381499
Short name T785
Test name
Test status
Simulation time 3300220610 ps
CPU time 3.73 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:31:31 PM PDT 24
Peak memory 206884 kb
Host smart-70aca590-4a1e-4c4d-8564-d8d3def95231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
81499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3165381499
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1627495117
Short name T1122
Test name
Test status
Simulation time 11411585983 ps
CPU time 318.11 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 207080 kb
Host smart-182571d9-b7f1-4b42-8e50-f131558f668c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
95117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1627495117
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.4216079827
Short name T2390
Test name
Test status
Simulation time 4717239950 ps
CPU time 32.73 seconds
Started Jul 12 05:31:15 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 207004 kb
Host smart-67017423-27c6-48ee-9c8c-965c61b7ed99
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4216079827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.4216079827
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1722433713
Short name T276
Test name
Test status
Simulation time 289985706 ps
CPU time 0.97 seconds
Started Jul 12 05:31:15 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 206812 kb
Host smart-af60ba1a-49aa-4522-84fe-82df8ac1712b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1722433713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1722433713
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.654352562
Short name T2043
Test name
Test status
Simulation time 190167946 ps
CPU time 0.8 seconds
Started Jul 12 05:31:14 PM PDT 24
Finished Jul 12 05:31:16 PM PDT 24
Peak memory 206816 kb
Host smart-14554946-3049-40e3-936d-b09d96a421b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65435
2562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.654352562
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1209571735
Short name T932
Test name
Test status
Simulation time 3982046086 ps
CPU time 103.51 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206840 kb
Host smart-8f7c54e0-e687-49dc-992a-45c0241bcb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12095
71735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1209571735
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.344101958
Short name T791
Test name
Test status
Simulation time 5001586073 ps
CPU time 35.27 seconds
Started Jul 12 05:31:39 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 207032 kb
Host smart-139a63df-fb15-44e8-a885-94e566f3013a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=344101958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.344101958
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3516186830
Short name T1610
Test name
Test status
Simulation time 168869645 ps
CPU time 0.83 seconds
Started Jul 12 05:31:14 PM PDT 24
Finished Jul 12 05:31:16 PM PDT 24
Peak memory 206772 kb
Host smart-86c7ee4d-ca57-4b25-85da-14cb40084aa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3516186830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3516186830
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.292992426
Short name T1098
Test name
Test status
Simulation time 174211047 ps
CPU time 0.81 seconds
Started Jul 12 05:31:12 PM PDT 24
Finished Jul 12 05:31:15 PM PDT 24
Peak memory 206804 kb
Host smart-5da53876-f410-4b50-aacb-63a80c22b845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29299
2426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.292992426
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.692022056
Short name T1049
Test name
Test status
Simulation time 211196282 ps
CPU time 0.86 seconds
Started Jul 12 05:31:11 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 206696 kb
Host smart-cba53be8-ecb7-4f01-82f2-3576285472b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69202
2056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.692022056
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3578982639
Short name T1437
Test name
Test status
Simulation time 191326007 ps
CPU time 0.93 seconds
Started Jul 12 05:31:15 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 206832 kb
Host smart-983c945e-e021-4f15-a359-a75306b3ef5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35789
82639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3578982639
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1682160788
Short name T2374
Test name
Test status
Simulation time 155832821 ps
CPU time 0.78 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 206712 kb
Host smart-5d734361-f666-4e21-87a3-47fc4b800ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
60788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1682160788
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2214325469
Short name T242
Test name
Test status
Simulation time 165496221 ps
CPU time 0.79 seconds
Started Jul 12 05:31:16 PM PDT 24
Finished Jul 12 05:31:18 PM PDT 24
Peak memory 206812 kb
Host smart-3708d4ee-24f0-4b35-956d-9833c3ae5fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22143
25469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2214325469
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.157833276
Short name T1527
Test name
Test status
Simulation time 154040918 ps
CPU time 0.84 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 206824 kb
Host smart-cad16d68-b0d4-4062-b344-da4efd385134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15783
3276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.157833276
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3282028772
Short name T884
Test name
Test status
Simulation time 223206242 ps
CPU time 0.91 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:25 PM PDT 24
Peak memory 206812 kb
Host smart-cb74b140-afce-475c-858e-c30f5c3a661f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3282028772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3282028772
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3881716215
Short name T660
Test name
Test status
Simulation time 148390627 ps
CPU time 0.77 seconds
Started Jul 12 05:31:11 PM PDT 24
Finished Jul 12 05:31:13 PM PDT 24
Peak memory 206792 kb
Host smart-999670e6-4b4c-450f-bb9f-030c1e0ed3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38817
16215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3881716215
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.601868297
Short name T2371
Test name
Test status
Simulation time 43991288 ps
CPU time 0.68 seconds
Started Jul 12 05:31:16 PM PDT 24
Finished Jul 12 05:31:24 PM PDT 24
Peak memory 206768 kb
Host smart-183214ed-de71-426f-a435-74eb311e533f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60186
8297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.601868297
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.313892754
Short name T280
Test name
Test status
Simulation time 14186162347 ps
CPU time 34.23 seconds
Started Jul 12 05:31:26 PM PDT 24
Finished Jul 12 05:32:04 PM PDT 24
Peak memory 207132 kb
Host smart-06e92d5c-6de4-4459-bc9d-4fdd5f4649e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31389
2754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.313892754
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.609568646
Short name T1807
Test name
Test status
Simulation time 167426235 ps
CPU time 0.78 seconds
Started Jul 12 05:31:16 PM PDT 24
Finished Jul 12 05:31:24 PM PDT 24
Peak memory 206812 kb
Host smart-0f220ea1-5e4e-4d54-a326-922d938cba42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60956
8646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.609568646
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1312829096
Short name T2254
Test name
Test status
Simulation time 215656767 ps
CPU time 0.94 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:29 PM PDT 24
Peak memory 206828 kb
Host smart-c65146dc-dc3a-4c29-85d4-2bfc14733807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13128
29096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1312829096
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1389724566
Short name T1699
Test name
Test status
Simulation time 252744823 ps
CPU time 0.97 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 206676 kb
Host smart-b1d586d7-236e-454f-a833-b2cb49533a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13897
24566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1389724566
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2611690104
Short name T929
Test name
Test status
Simulation time 170651757 ps
CPU time 0.85 seconds
Started Jul 12 05:31:14 PM PDT 24
Finished Jul 12 05:31:16 PM PDT 24
Peak memory 206816 kb
Host smart-13f93828-5b29-4205-80be-148a6a9212e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
90104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2611690104
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.771393231
Short name T1641
Test name
Test status
Simulation time 154827146 ps
CPU time 0.8 seconds
Started Jul 12 05:31:25 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 206808 kb
Host smart-b4b5add4-6bfa-4e44-938b-cb44d63efcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77139
3231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.771393231
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3366848808
Short name T1281
Test name
Test status
Simulation time 147111903 ps
CPU time 0.74 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 206768 kb
Host smart-9e8bb926-b486-46b3-a2e9-34f36202706f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33668
48808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3366848808
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1513431475
Short name T2139
Test name
Test status
Simulation time 152136201 ps
CPU time 0.82 seconds
Started Jul 12 05:31:25 PM PDT 24
Finished Jul 12 05:31:29 PM PDT 24
Peak memory 206756 kb
Host smart-971fac33-461d-4890-8772-4aaae9ccedf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
31475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1513431475
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2610839255
Short name T1269
Test name
Test status
Simulation time 263323213 ps
CPU time 0.96 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:23 PM PDT 24
Peak memory 206712 kb
Host smart-3541fc1c-acc0-45bb-b170-6b5bb367e68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26108
39255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2610839255
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.4257659938
Short name T810
Test name
Test status
Simulation time 6096280332 ps
CPU time 170.99 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:34:14 PM PDT 24
Peak memory 206900 kb
Host smart-98902cf3-6486-49a1-81c4-1ba45a238fcc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4257659938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.4257659938
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3270946314
Short name T1591
Test name
Test status
Simulation time 174887124 ps
CPU time 0.81 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 206832 kb
Host smart-9834c8b3-887e-4f04-8106-1966ccb26a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32709
46314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3270946314
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1056195576
Short name T1038
Test name
Test status
Simulation time 182853803 ps
CPU time 0.8 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:25 PM PDT 24
Peak memory 206816 kb
Host smart-409e59cb-2e85-428b-87a0-6094ff3a6219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
95576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1056195576
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1341573560
Short name T375
Test name
Test status
Simulation time 968540089 ps
CPU time 2.1 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:23 PM PDT 24
Peak memory 206872 kb
Host smart-fd51a51b-9cdd-4c78-89d3-000774af5a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13415
73560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1341573560
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.670532318
Short name T2420
Test name
Test status
Simulation time 3139998904 ps
CPU time 27.87 seconds
Started Jul 12 05:31:25 PM PDT 24
Finished Jul 12 05:31:57 PM PDT 24
Peak memory 207016 kb
Host smart-bb33bcff-8c8b-4f97-8272-3c3b1c981e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67053
2318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.670532318
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3951712591
Short name T2134
Test name
Test status
Simulation time 104387929 ps
CPU time 0.72 seconds
Started Jul 12 05:32:06 PM PDT 24
Finished Jul 12 05:32:12 PM PDT 24
Peak memory 206728 kb
Host smart-7905ed61-7217-4010-886b-5eb59ec72427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3951712591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3951712591
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1753020354
Short name T1935
Test name
Test status
Simulation time 4190866300 ps
CPU time 4.73 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:25 PM PDT 24
Peak memory 206876 kb
Host smart-8403a891-ff68-4230-a3a7-e5cf4ae71aa1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1753020354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1753020354
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2256471292
Short name T216
Test name
Test status
Simulation time 13325488835 ps
CPU time 12.45 seconds
Started Jul 12 05:31:39 PM PDT 24
Finished Jul 12 05:31:53 PM PDT 24
Peak memory 207092 kb
Host smart-24c21b67-47d4-4203-ba0e-93db7328a7e2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2256471292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2256471292
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3289355767
Short name T2059
Test name
Test status
Simulation time 23321746703 ps
CPU time 30.13 seconds
Started Jul 12 05:31:31 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206904 kb
Host smart-b7e7f4ec-5bbb-441c-b073-8deb0248f415
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3289355767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.3289355767
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.694229499
Short name T809
Test name
Test status
Simulation time 166668439 ps
CPU time 0.83 seconds
Started Jul 12 05:31:26 PM PDT 24
Finished Jul 12 05:31:31 PM PDT 24
Peak memory 206804 kb
Host smart-3b4f4ee2-baa4-4389-8e67-13478b1bbf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69422
9499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.694229499
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2177750141
Short name T557
Test name
Test status
Simulation time 172327584 ps
CPU time 0.81 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 206700 kb
Host smart-d4f13bc9-861e-4941-b042-24cc077c0c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
50141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2177750141
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3883855035
Short name T707
Test name
Test status
Simulation time 556089157 ps
CPU time 1.51 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 207020 kb
Host smart-e972c3e7-c6fa-4cb7-87f7-09d6158ed7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38838
55035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3883855035
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.380059957
Short name T2685
Test name
Test status
Simulation time 565616955 ps
CPU time 1.43 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 206804 kb
Host smart-4834cc35-e800-48d0-94bd-8b7a88b2f266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38005
9957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.380059957
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.3176214287
Short name T1745
Test name
Test status
Simulation time 21681463337 ps
CPU time 38.08 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:32:02 PM PDT 24
Peak memory 207084 kb
Host smart-d27a9c8e-a49e-452a-966e-2f99747b8bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31762
14287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3176214287
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3225509351
Short name T2365
Test name
Test status
Simulation time 494289744 ps
CPU time 1.35 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:31:29 PM PDT 24
Peak memory 206824 kb
Host smart-d96fe5d0-755d-427d-aa1a-594d09ae798f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32255
09351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3225509351
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.1575235920
Short name T854
Test name
Test status
Simulation time 148693014 ps
CPU time 0.8 seconds
Started Jul 12 05:31:33 PM PDT 24
Finished Jul 12 05:31:35 PM PDT 24
Peak memory 206692 kb
Host smart-d70ab517-616f-4705-989f-55ff3be848c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752
35920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1575235920
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.447547623
Short name T207
Test name
Test status
Simulation time 74942024 ps
CPU time 0.69 seconds
Started Jul 12 05:31:19 PM PDT 24
Finished Jul 12 05:31:21 PM PDT 24
Peak memory 206688 kb
Host smart-2aa25ddd-a1ae-4281-9a41-973789842b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44754
7623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.447547623
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.163926792
Short name T79
Test name
Test status
Simulation time 823784778 ps
CPU time 1.93 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 206952 kb
Host smart-02a0c137-7b19-4220-b2df-bb709718ccb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16392
6792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.163926792
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2318717414
Short name T1566
Test name
Test status
Simulation time 349240577 ps
CPU time 2.29 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 207004 kb
Host smart-424778ca-5def-4b40-a1cc-8f0aad863742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23187
17414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2318717414
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3551168874
Short name T1454
Test name
Test status
Simulation time 210013753 ps
CPU time 0.85 seconds
Started Jul 12 05:36:50 PM PDT 24
Finished Jul 12 05:36:53 PM PDT 24
Peak memory 206808 kb
Host smart-eee48b43-ea0a-418c-bdfb-634a805c6281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
68874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3551168874
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3828012994
Short name T1918
Test name
Test status
Simulation time 145200089 ps
CPU time 0.81 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:24 PM PDT 24
Peak memory 206712 kb
Host smart-10b0d017-4e5b-48cf-b0e7-09e6cec8a0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38280
12994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3828012994
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1514138249
Short name T659
Test name
Test status
Simulation time 229624120 ps
CPU time 0.98 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 206696 kb
Host smart-bbcff3b5-f2c3-44f1-99ef-bb5ba27cd1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15141
38249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1514138249
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.53799308
Short name T2743
Test name
Test status
Simulation time 206314085 ps
CPU time 0.86 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:29 PM PDT 24
Peak memory 206820 kb
Host smart-0db33274-3035-4df5-872d-83c0f3c32a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53799
308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.53799308
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2209288161
Short name T1983
Test name
Test status
Simulation time 23303552297 ps
CPU time 21.67 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 206856 kb
Host smart-089b0c5d-4fde-4e59-942f-4f3677b7afc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22092
88161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2209288161
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3801431395
Short name T2269
Test name
Test status
Simulation time 3295097780 ps
CPU time 4.08 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:31:31 PM PDT 24
Peak memory 206864 kb
Host smart-791d8b06-1262-4901-8f86-c6ba3f557c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38014
31395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3801431395
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1155364480
Short name T1602
Test name
Test status
Simulation time 10289733585 ps
CPU time 292.06 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:36:17 PM PDT 24
Peak memory 207252 kb
Host smart-ef79835b-6510-4f32-8f5c-b153bf6c21f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11553
64480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1155364480
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.469080252
Short name T1217
Test name
Test status
Simulation time 5038896100 ps
CPU time 141.07 seconds
Started Jul 12 05:31:31 PM PDT 24
Finished Jul 12 05:33:54 PM PDT 24
Peak memory 206996 kb
Host smart-86939dca-90ce-4971-8e44-94d78f4940f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=469080252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.469080252
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1846015963
Short name T1743
Test name
Test status
Simulation time 257150910 ps
CPU time 0.88 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:27 PM PDT 24
Peak memory 206800 kb
Host smart-95f2b422-f826-45f8-af1a-fc03a680f161
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1846015963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1846015963
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.427204509
Short name T1186
Test name
Test status
Simulation time 197753784 ps
CPU time 0.86 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:29 PM PDT 24
Peak memory 206824 kb
Host smart-71c2e1d5-ceb8-4429-abf0-987d977c6883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42720
4509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.427204509
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.3081298542
Short name T2444
Test name
Test status
Simulation time 5237995344 ps
CPU time 48.47 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:32:12 PM PDT 24
Peak memory 207024 kb
Host smart-10e8fe39-d0ce-4969-bcf3-4ab09c3717b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30812
98542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.3081298542
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3501815984
Short name T997
Test name
Test status
Simulation time 6391182827 ps
CPU time 174.91 seconds
Started Jul 12 05:31:25 PM PDT 24
Finished Jul 12 05:34:24 PM PDT 24
Peak memory 206936 kb
Host smart-593b22fb-3930-44d6-8659-9ded86ebaef8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3501815984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3501815984
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.597683085
Short name T2622
Test name
Test status
Simulation time 154873317 ps
CPU time 0.8 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 206796 kb
Host smart-b2540a3d-a763-4feb-b87d-fe241dd948ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=597683085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.597683085
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.402602119
Short name T1254
Test name
Test status
Simulation time 160279909 ps
CPU time 0.78 seconds
Started Jul 12 05:31:30 PM PDT 24
Finished Jul 12 05:31:33 PM PDT 24
Peak memory 206824 kb
Host smart-891abf6f-1a43-46e0-a7f1-2fc84c698179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40260
2119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.402602119
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.4208868702
Short name T124
Test name
Test status
Simulation time 206321415 ps
CPU time 0.84 seconds
Started Jul 12 05:31:27 PM PDT 24
Finished Jul 12 05:31:31 PM PDT 24
Peak memory 206824 kb
Host smart-2d2b8922-dbf1-4b58-b342-1fa2cc083efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42088
68702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.4208868702
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2155782112
Short name T942
Test name
Test status
Simulation time 191032174 ps
CPU time 0.91 seconds
Started Jul 12 05:31:37 PM PDT 24
Finished Jul 12 05:31:40 PM PDT 24
Peak memory 206768 kb
Host smart-83994831-ecb4-4c6b-89a7-a8f6b16bf60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21557
82112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2155782112
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.4192338459
Short name T320
Test name
Test status
Simulation time 235273476 ps
CPU time 0.87 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206816 kb
Host smart-c122881f-65b4-4a03-9b16-188f6862edd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41923
38459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.4192338459
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2991768987
Short name T1236
Test name
Test status
Simulation time 171204601 ps
CPU time 0.76 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 206804 kb
Host smart-0030170f-9d0d-4b86-8b31-1c262b4bd188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29917
68987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2991768987
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3730143438
Short name T1517
Test name
Test status
Simulation time 154576780 ps
CPU time 0.8 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:26 PM PDT 24
Peak memory 206704 kb
Host smart-89d3c807-ffc7-4c69-a47d-2d07dd19244b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37301
43438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3730143438
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.374777878
Short name T1659
Test name
Test status
Simulation time 236147322 ps
CPU time 0.97 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:32 PM PDT 24
Peak memory 206776 kb
Host smart-1c64cc7c-f028-49c9-8a94-84d7e9f39ede
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=374777878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.374777878
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3651915643
Short name T1070
Test name
Test status
Simulation time 151490761 ps
CPU time 0.79 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 206768 kb
Host smart-5084f03d-5e10-4e7c-98fd-2414fef1d0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36519
15643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3651915643
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1521012365
Short name T591
Test name
Test status
Simulation time 32189352 ps
CPU time 0.64 seconds
Started Jul 12 05:31:22 PM PDT 24
Finished Jul 12 05:31:27 PM PDT 24
Peak memory 206688 kb
Host smart-e27d10f9-5906-4e93-8cc0-09584ac5917a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
12365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1521012365
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.224060825
Short name T1439
Test name
Test status
Simulation time 7942959344 ps
CPU time 17.02 seconds
Started Jul 12 05:31:28 PM PDT 24
Finished Jul 12 05:31:48 PM PDT 24
Peak memory 207072 kb
Host smart-7c6cd246-7bb0-4815-af71-745d7e7e7876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22406
0825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.224060825
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1038436147
Short name T1674
Test name
Test status
Simulation time 182490225 ps
CPU time 0.83 seconds
Started Jul 12 05:31:27 PM PDT 24
Finished Jul 12 05:31:31 PM PDT 24
Peak memory 206820 kb
Host smart-2555384f-1f29-44f5-9d94-8331ef134fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10384
36147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1038436147
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.26344035
Short name T1340
Test name
Test status
Simulation time 185633177 ps
CPU time 0.82 seconds
Started Jul 12 05:31:20 PM PDT 24
Finished Jul 12 05:31:22 PM PDT 24
Peak memory 206816 kb
Host smart-788a442b-5cd0-476f-90e0-012e86a8db8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26344
035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.26344035
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.482685516
Short name T1896
Test name
Test status
Simulation time 181461445 ps
CPU time 0.8 seconds
Started Jul 12 05:31:44 PM PDT 24
Finished Jul 12 05:31:46 PM PDT 24
Peak memory 206820 kb
Host smart-9b52a6e0-37ce-4980-b86d-80d08aac1337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48268
5516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.482685516
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3577585825
Short name T1823
Test name
Test status
Simulation time 193705493 ps
CPU time 0.85 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:28 PM PDT 24
Peak memory 206820 kb
Host smart-003bb3f3-af34-4a1a-abf6-8a34dd34d65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35775
85825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3577585825
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1650081849
Short name T1063
Test name
Test status
Simulation time 220242425 ps
CPU time 0.82 seconds
Started Jul 12 05:31:25 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 206800 kb
Host smart-c355fb0b-b432-4631-b12a-52224507d142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16500
81849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1650081849
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.946758107
Short name T885
Test name
Test status
Simulation time 152227852 ps
CPU time 0.79 seconds
Started Jul 12 05:31:26 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 206820 kb
Host smart-f5bee5b5-639c-4ec3-8952-0980f19ee641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94675
8107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.946758107
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1123032353
Short name T1143
Test name
Test status
Simulation time 161491210 ps
CPU time 0.77 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:29 PM PDT 24
Peak memory 206816 kb
Host smart-019ed37d-e713-4bd8-af34-4e8f7ce7928c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11230
32353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1123032353
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2795582507
Short name T1046
Test name
Test status
Simulation time 230820807 ps
CPU time 0.91 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:25 PM PDT 24
Peak memory 206716 kb
Host smart-b60e6dc4-ff7f-41fd-a247-8f3dd0c8e19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
82507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2795582507
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.152343815
Short name T377
Test name
Test status
Simulation time 6985016807 ps
CPU time 185.56 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:34:32 PM PDT 24
Peak memory 206988 kb
Host smart-979e8586-4e18-4d15-8eb2-ad4bc6a25754
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=152343815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.152343815
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3116331641
Short name T2448
Test name
Test status
Simulation time 214671637 ps
CPU time 0.85 seconds
Started Jul 12 05:31:21 PM PDT 24
Finished Jul 12 05:31:25 PM PDT 24
Peak memory 206808 kb
Host smart-17a8d57a-24e8-4a15-857d-3e7f56570a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31163
31641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3116331641
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.302180880
Short name T2403
Test name
Test status
Simulation time 179623341 ps
CPU time 0.8 seconds
Started Jul 12 05:31:33 PM PDT 24
Finished Jul 12 05:31:35 PM PDT 24
Peak memory 206828 kb
Host smart-20a1caa4-6db3-492d-96db-d2fdbf4a92b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30218
0880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.302180880
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.451805792
Short name T2419
Test name
Test status
Simulation time 401553997 ps
CPU time 1.23 seconds
Started Jul 12 05:31:53 PM PDT 24
Finished Jul 12 05:31:56 PM PDT 24
Peak memory 206688 kb
Host smart-b4314738-d8ee-4df2-9333-ba41f92e711c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45180
5792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.451805792
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3733471156
Short name T1961
Test name
Test status
Simulation time 5028193464 ps
CPU time 37.85 seconds
Started Jul 12 05:31:25 PM PDT 24
Finished Jul 12 05:32:07 PM PDT 24
Peak memory 206960 kb
Host smart-aa74ac5b-10c7-40c1-afde-514cef8f7894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37334
71156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3733471156
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2009281607
Short name T484
Test name
Test status
Simulation time 42328928 ps
CPU time 0.66 seconds
Started Jul 12 05:31:37 PM PDT 24
Finished Jul 12 05:31:38 PM PDT 24
Peak memory 206744 kb
Host smart-207f03f2-66cb-4b50-838e-ca116f97b9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2009281607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2009281607
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2566947880
Short name T759
Test name
Test status
Simulation time 3431159339 ps
CPU time 4.18 seconds
Started Jul 12 05:31:31 PM PDT 24
Finished Jul 12 05:31:37 PM PDT 24
Peak memory 206892 kb
Host smart-a631bdfd-37d7-4b7a-9103-13b80afb091c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2566947880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.2566947880
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3247949851
Short name T1567
Test name
Test status
Simulation time 13301593225 ps
CPU time 11.9 seconds
Started Jul 12 05:31:46 PM PDT 24
Finished Jul 12 05:32:00 PM PDT 24
Peak memory 207032 kb
Host smart-ec126e1b-5f96-461d-bd80-d43d3139ce98
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3247949851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3247949851
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1211863832
Short name T1091
Test name
Test status
Simulation time 23364607302 ps
CPU time 23.65 seconds
Started Jul 12 05:31:53 PM PDT 24
Finished Jul 12 05:32:18 PM PDT 24
Peak memory 206756 kb
Host smart-426ed609-a275-4c37-8176-530c80eba348
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1211863832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.1211863832
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.301330379
Short name T937
Test name
Test status
Simulation time 195093854 ps
CPU time 0.87 seconds
Started Jul 12 05:31:54 PM PDT 24
Finished Jul 12 05:31:57 PM PDT 24
Peak memory 206680 kb
Host smart-8455373d-e4e2-479d-9e72-85b8fe78a59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30133
0379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.301330379
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2710964321
Short name T1684
Test name
Test status
Simulation time 144830130 ps
CPU time 0.82 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 206820 kb
Host smart-2d65d071-d4d7-4eb5-b021-de7b7761f4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27109
64321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2710964321
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2313056072
Short name T33
Test name
Test status
Simulation time 526632665 ps
CPU time 1.71 seconds
Started Jul 12 05:31:26 PM PDT 24
Finished Jul 12 05:31:31 PM PDT 24
Peak memory 207024 kb
Host smart-4b9fa859-38a8-4c17-bc67-d5d4338a3b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23130
56072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2313056072
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1369305113
Short name T1547
Test name
Test status
Simulation time 924344547 ps
CPU time 2.22 seconds
Started Jul 12 05:31:24 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 207008 kb
Host smart-06a58ae9-9c57-40e5-8a73-98fe6489b897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13693
05113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1369305113
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1750077877
Short name T1804
Test name
Test status
Simulation time 11108574999 ps
CPU time 21.81 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 207084 kb
Host smart-45ead68a-8d9d-4074-adb9-76bc46f8f23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17500
77877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1750077877
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.43166600
Short name T1920
Test name
Test status
Simulation time 447669295 ps
CPU time 1.34 seconds
Started Jul 12 05:31:23 PM PDT 24
Finished Jul 12 05:31:29 PM PDT 24
Peak memory 206820 kb
Host smart-7eb35036-a701-4770-9a86-8c87ebe6044d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43166
600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.43166600
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3843456630
Short name T1077
Test name
Test status
Simulation time 187029752 ps
CPU time 0.81 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 206920 kb
Host smart-2c63fcab-01b4-4779-8756-e6b5fb93be37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38434
56630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3843456630
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.601786964
Short name T2236
Test name
Test status
Simulation time 34826358 ps
CPU time 0.67 seconds
Started Jul 12 05:31:25 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 206804 kb
Host smart-ae268b16-248d-4f6a-8faa-e3feaa2db7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60178
6964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.601786964
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3199559367
Short name T639
Test name
Test status
Simulation time 807761002 ps
CPU time 2.01 seconds
Started Jul 12 05:31:37 PM PDT 24
Finished Jul 12 05:31:41 PM PDT 24
Peak memory 206984 kb
Host smart-18a648f7-478f-48dd-8eee-072669106e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31995
59367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3199559367
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1292421274
Short name T1307
Test name
Test status
Simulation time 148389034 ps
CPU time 1.27 seconds
Started Jul 12 05:31:41 PM PDT 24
Finished Jul 12 05:31:43 PM PDT 24
Peak memory 206980 kb
Host smart-87648df2-e615-431d-860d-ca87cd1895d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12924
21274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1292421274
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1264436997
Short name T1854
Test name
Test status
Simulation time 213562665 ps
CPU time 0.84 seconds
Started Jul 12 05:31:34 PM PDT 24
Finished Jul 12 05:31:36 PM PDT 24
Peak memory 206816 kb
Host smart-f3bb4e4b-eec9-4a5a-82ec-0bd9e1406be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12644
36997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1264436997
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2191174969
Short name T1873
Test name
Test status
Simulation time 143966029 ps
CPU time 0.78 seconds
Started Jul 12 05:31:37 PM PDT 24
Finished Jul 12 05:31:40 PM PDT 24
Peak memory 206872 kb
Host smart-787c466f-b903-49e1-8251-39d863f7b969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21911
74969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2191174969
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.730988364
Short name T2056
Test name
Test status
Simulation time 232793377 ps
CPU time 0.97 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:33:09 PM PDT 24
Peak memory 206804 kb
Host smart-cabe2846-a90a-461c-a1dc-9bd950c66c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73098
8364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.730988364
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2859187879
Short name T606
Test name
Test status
Simulation time 6233738546 ps
CPU time 177.79 seconds
Started Jul 12 05:31:33 PM PDT 24
Finished Jul 12 05:34:32 PM PDT 24
Peak memory 207164 kb
Host smart-aed2cb4f-fad6-475f-91ad-39102daa4fce
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2859187879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2859187879
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.393657374
Short name T1709
Test name
Test status
Simulation time 5750571614 ps
CPU time 52.04 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 207084 kb
Host smart-cf48b287-bfd1-48f4-84be-f5e3854283f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39365
7374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.393657374
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2982691536
Short name T1398
Test name
Test status
Simulation time 211901248 ps
CPU time 0.86 seconds
Started Jul 12 05:31:34 PM PDT 24
Finished Jul 12 05:31:36 PM PDT 24
Peak memory 206712 kb
Host smart-96e048e1-066f-403d-8119-1a371b38c97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29826
91536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2982691536
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1861806097
Short name T2642
Test name
Test status
Simulation time 23373980804 ps
CPU time 22.99 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 206852 kb
Host smart-bbc5202a-f249-40ee-bef8-866ccbe3ba00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18618
06097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1861806097
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2918038519
Short name T1859
Test name
Test status
Simulation time 3298672776 ps
CPU time 4.15 seconds
Started Jul 12 05:31:41 PM PDT 24
Finished Jul 12 05:31:46 PM PDT 24
Peak memory 206700 kb
Host smart-d84e0c48-b265-4f68-97d2-11049be9b11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29180
38519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2918038519
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3653349995
Short name T657
Test name
Test status
Simulation time 7637386058 ps
CPU time 198.1 seconds
Started Jul 12 05:31:37 PM PDT 24
Finished Jul 12 05:34:56 PM PDT 24
Peak memory 206988 kb
Host smart-34deb8a9-d7ee-4996-a186-a05687ba1667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36533
49995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3653349995
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.670280529
Short name T153
Test name
Test status
Simulation time 4045116631 ps
CPU time 29.36 seconds
Started Jul 12 05:31:45 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 207060 kb
Host smart-f25244ec-d076-49b6-829d-d702e9844232
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=670280529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.670280529
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.3229024779
Short name T1499
Test name
Test status
Simulation time 240456149 ps
CPU time 0.94 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:06 PM PDT 24
Peak memory 206820 kb
Host smart-36d1af67-e1ad-4104-a8e9-ea2a6a3e6266
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3229024779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.3229024779
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.953454692
Short name T76
Test name
Test status
Simulation time 203682545 ps
CPU time 0.95 seconds
Started Jul 12 05:31:46 PM PDT 24
Finished Jul 12 05:31:48 PM PDT 24
Peak memory 206824 kb
Host smart-31ceef7a-0e7e-4e4c-b92c-0e8939c1459e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95345
4692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.953454692
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3945071174
Short name T494
Test name
Test status
Simulation time 5847916996 ps
CPU time 55.04 seconds
Started Jul 12 05:31:40 PM PDT 24
Finished Jul 12 05:32:36 PM PDT 24
Peak memory 207104 kb
Host smart-169b2c8e-b0b1-486b-bab6-758757680b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39450
71174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3945071174
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.719077740
Short name T1016
Test name
Test status
Simulation time 3987596165 ps
CPU time 109.45 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:33:39 PM PDT 24
Peak memory 206972 kb
Host smart-04e56772-e42c-4147-ac14-78bcaf955ee9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=719077740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.719077740
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1481455690
Short name T666
Test name
Test status
Simulation time 147683090 ps
CPU time 0.83 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 206692 kb
Host smart-83660a99-f3ef-4ad4-ace4-db6d16aa0991
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1481455690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1481455690
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3833845176
Short name T1906
Test name
Test status
Simulation time 162150774 ps
CPU time 0.78 seconds
Started Jul 12 05:31:32 PM PDT 24
Finished Jul 12 05:31:34 PM PDT 24
Peak memory 206828 kb
Host smart-a2c112ff-f3bb-40fc-88e9-95e12a014875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38338
45176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3833845176
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3426694380
Short name T136
Test name
Test status
Simulation time 232928753 ps
CPU time 0.88 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:05 PM PDT 24
Peak memory 207028 kb
Host smart-089656f9-d7ad-4e47-bfb7-1efba0656dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34266
94380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3426694380
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1125042326
Short name T799
Test name
Test status
Simulation time 160510921 ps
CPU time 0.83 seconds
Started Jul 12 05:31:53 PM PDT 24
Finished Jul 12 05:31:56 PM PDT 24
Peak memory 206684 kb
Host smart-9a5dc7e1-d714-4ab5-9317-1b2f31fc9d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11250
42326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1125042326
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3284462757
Short name T2394
Test name
Test status
Simulation time 173550262 ps
CPU time 0.81 seconds
Started Jul 12 05:31:57 PM PDT 24
Finished Jul 12 05:32:02 PM PDT 24
Peak memory 206976 kb
Host smart-0023ae57-6c49-4d84-8d74-542ac318ea58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32844
62757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3284462757
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2896974487
Short name T1887
Test name
Test status
Simulation time 165686846 ps
CPU time 0.79 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:31:58 PM PDT 24
Peak memory 206800 kb
Host smart-a6e50667-4254-41fd-b1d9-9eaaf80b6f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28969
74487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2896974487
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.4186749019
Short name T2726
Test name
Test status
Simulation time 180962300 ps
CPU time 0.9 seconds
Started Jul 12 05:31:43 PM PDT 24
Finished Jul 12 05:31:45 PM PDT 24
Peak memory 206792 kb
Host smart-946e10df-5dfa-44ce-82ff-92c51570dbfb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4186749019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.4186749019
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1379138681
Short name T1824
Test name
Test status
Simulation time 140057613 ps
CPU time 0.81 seconds
Started Jul 12 05:31:42 PM PDT 24
Finished Jul 12 05:31:44 PM PDT 24
Peak memory 206816 kb
Host smart-4bcf9df3-ff0b-4809-8403-a6e972031a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13791
38681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1379138681
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3741533236
Short name T2456
Test name
Test status
Simulation time 60279307 ps
CPU time 0.69 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:31:59 PM PDT 24
Peak memory 206972 kb
Host smart-45499b18-6d5a-49eb-8ec0-5c3894c7f246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37415
33236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3741533236
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2409661105
Short name T830
Test name
Test status
Simulation time 11556964910 ps
CPU time 25.67 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 207216 kb
Host smart-16521628-5b6e-4b73-a528-2c456d54ac94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
61105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2409661105
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1705469216
Short name T2696
Test name
Test status
Simulation time 194296289 ps
CPU time 0.83 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:31:51 PM PDT 24
Peak memory 206816 kb
Host smart-d2194b82-6e50-4140-8ef6-245b4ba8e8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17054
69216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1705469216
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2681481017
Short name T1291
Test name
Test status
Simulation time 187477071 ps
CPU time 0.8 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206804 kb
Host smart-3a6b030e-cc16-429d-b519-6567ebd75796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26814
81017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2681481017
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2494792959
Short name T1139
Test name
Test status
Simulation time 239199570 ps
CPU time 0.91 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206816 kb
Host smart-cce17dc3-8ab9-4929-b131-4980b91ccd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24947
92959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2494792959
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2586303710
Short name T498
Test name
Test status
Simulation time 173525517 ps
CPU time 0.86 seconds
Started Jul 12 05:31:45 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 206840 kb
Host smart-325b9a7d-7de1-4120-be43-8218d9f8306b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25863
03710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2586303710
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3542019814
Short name T67
Test name
Test status
Simulation time 166451652 ps
CPU time 0.79 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 206976 kb
Host smart-e4d662e1-2647-41b9-a035-c4f8e3bf5d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35420
19814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3542019814
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1757747104
Short name T471
Test name
Test status
Simulation time 160798206 ps
CPU time 0.78 seconds
Started Jul 12 05:31:57 PM PDT 24
Finished Jul 12 05:32:02 PM PDT 24
Peak memory 206972 kb
Host smart-4f766aee-c560-4eac-beb2-f3102ea3674f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17577
47104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1757747104
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3710588463
Short name T1056
Test name
Test status
Simulation time 219587572 ps
CPU time 0.82 seconds
Started Jul 12 05:31:46 PM PDT 24
Finished Jul 12 05:31:48 PM PDT 24
Peak memory 206812 kb
Host smart-e7607216-26c6-4b00-b094-c3b293080344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37105
88463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3710588463
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3721656686
Short name T2336
Test name
Test status
Simulation time 241688897 ps
CPU time 0.94 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206768 kb
Host smart-f95d335f-b92b-41a9-b135-0fc0b0f807db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37216
56686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3721656686
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.4216945650
Short name T2548
Test name
Test status
Simulation time 4805227588 ps
CPU time 125.16 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:33:56 PM PDT 24
Peak memory 206972 kb
Host smart-7cb5d425-7b67-4648-8ffd-d5998901175d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4216945650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.4216945650
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1998196345
Short name T813
Test name
Test status
Simulation time 188139762 ps
CPU time 0.86 seconds
Started Jul 12 05:31:32 PM PDT 24
Finished Jul 12 05:31:34 PM PDT 24
Peak memory 207032 kb
Host smart-76e745da-f481-4508-9aa0-350f7d97dd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981
96345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1998196345
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3260306323
Short name T955
Test name
Test status
Simulation time 157085106 ps
CPU time 0.86 seconds
Started Jul 12 05:31:45 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 206712 kb
Host smart-4296a4f5-d0d7-47b1-a054-c6688554482b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32603
06323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3260306323
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1876757050
Short name T1617
Test name
Test status
Simulation time 670795487 ps
CPU time 1.54 seconds
Started Jul 12 05:31:44 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 207016 kb
Host smart-153964b9-893d-4927-be01-a19fed33d79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18767
57050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1876757050
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.548097035
Short name T605
Test name
Test status
Simulation time 7555139100 ps
CPU time 210.63 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:35:20 PM PDT 24
Peak memory 206976 kb
Host smart-c8661d39-6819-47fc-aeae-c304e5d2d409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54809
7035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.548097035
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2310361115
Short name T1992
Test name
Test status
Simulation time 72872067 ps
CPU time 0.69 seconds
Started Jul 12 05:31:40 PM PDT 24
Finished Jul 12 05:31:42 PM PDT 24
Peak memory 206760 kb
Host smart-bf551f79-d643-4a4e-a996-c34d9bcfd80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2310361115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2310361115
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3559133906
Short name T2341
Test name
Test status
Simulation time 3979271276 ps
CPU time 4.76 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:56 PM PDT 24
Peak memory 206752 kb
Host smart-14aee271-3afd-49d6-884b-37688d46b51e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3559133906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.3559133906
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3903945545
Short name T2676
Test name
Test status
Simulation time 13342979614 ps
CPU time 11.82 seconds
Started Jul 12 05:31:57 PM PDT 24
Finished Jul 12 05:32:12 PM PDT 24
Peak memory 207232 kb
Host smart-962a21db-c5a3-4739-aaa6-edfa0b8a1b3e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3903945545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3903945545
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3182933786
Short name T1440
Test name
Test status
Simulation time 23381543188 ps
CPU time 24.3 seconds
Started Jul 12 05:31:36 PM PDT 24
Finished Jul 12 05:32:01 PM PDT 24
Peak memory 206748 kb
Host smart-11709f00-65d5-41c6-a87f-ffbb0cc969e2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3182933786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3182933786
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.4258905842
Short name T2486
Test name
Test status
Simulation time 188412737 ps
CPU time 0.81 seconds
Started Jul 12 05:31:45 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 206804 kb
Host smart-b37399e9-ee20-4528-a58c-946d1949ffae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42589
05842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.4258905842
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3514719867
Short name T1656
Test name
Test status
Simulation time 148611094 ps
CPU time 0.79 seconds
Started Jul 12 05:31:27 PM PDT 24
Finished Jul 12 05:31:30 PM PDT 24
Peak memory 206820 kb
Host smart-32d042f6-1603-4ba9-92ae-193cf1377cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35147
19867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3514719867
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1100874462
Short name T422
Test name
Test status
Simulation time 391846853 ps
CPU time 1.28 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206924 kb
Host smart-4818471b-81a9-4244-a52c-3ad1d772f719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11008
74462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1100874462
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.704051777
Short name T780
Test name
Test status
Simulation time 1091905429 ps
CPU time 2.48 seconds
Started Jul 12 05:31:39 PM PDT 24
Finished Jul 12 05:31:44 PM PDT 24
Peak memory 207024 kb
Host smart-f98ba042-3d87-4328-8c73-77aefb52a75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70405
1777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.704051777
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.827975754
Short name T1147
Test name
Test status
Simulation time 10128300199 ps
CPU time 20.1 seconds
Started Jul 12 05:31:36 PM PDT 24
Finished Jul 12 05:31:57 PM PDT 24
Peak memory 207092 kb
Host smart-6f94328e-80f4-4130-ac75-a74911072077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82797
5754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.827975754
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.4038335582
Short name T2546
Test name
Test status
Simulation time 451332653 ps
CPU time 1.38 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:31:50 PM PDT 24
Peak memory 206700 kb
Host smart-18475e94-4fa9-442c-9e02-54294bb52188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40383
35582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.4038335582
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.304682405
Short name T2274
Test name
Test status
Simulation time 149738773 ps
CPU time 0.8 seconds
Started Jul 12 05:31:27 PM PDT 24
Finished Jul 12 05:31:31 PM PDT 24
Peak memory 206756 kb
Host smart-ffc3edb4-62c0-41ee-983f-2a352a1896c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30468
2405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.304682405
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1744674761
Short name T1188
Test name
Test status
Simulation time 55359649 ps
CPU time 0.72 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:31:58 PM PDT 24
Peak memory 206684 kb
Host smart-faa20929-eb4c-46d2-b17d-6a6d1bd51d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17446
74761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1744674761
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1677243493
Short name T2307
Test name
Test status
Simulation time 823364463 ps
CPU time 2.21 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:31:54 PM PDT 24
Peak memory 206960 kb
Host smart-c0d9f41c-b59e-41d9-9de5-b377b783af5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16772
43493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1677243493
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3205091960
Short name T2292
Test name
Test status
Simulation time 165757982 ps
CPU time 1.65 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:31:50 PM PDT 24
Peak memory 206948 kb
Host smart-f3b99f6c-3e4b-4228-9f22-0a8e177f588e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32050
91960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3205091960
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1498273455
Short name T1888
Test name
Test status
Simulation time 164543238 ps
CPU time 0.82 seconds
Started Jul 12 05:31:32 PM PDT 24
Finished Jul 12 05:31:34 PM PDT 24
Peak memory 206668 kb
Host smart-01374849-5aaa-4ab1-8d67-c0982efea0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14982
73455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1498273455
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3443365121
Short name T446
Test name
Test status
Simulation time 144031389 ps
CPU time 0.81 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:31:53 PM PDT 24
Peak memory 206972 kb
Host smart-50fcc413-bd74-4778-8634-8f80e85bd4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34433
65121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3443365121
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.827496341
Short name T855
Test name
Test status
Simulation time 167922591 ps
CPU time 0.82 seconds
Started Jul 12 05:31:40 PM PDT 24
Finished Jul 12 05:31:43 PM PDT 24
Peak memory 206808 kb
Host smart-3e27fde5-ab0c-45a0-bcad-6f42c8b62063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82749
6341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.827496341
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3994715160
Short name T1951
Test name
Test status
Simulation time 5648739073 ps
CPU time 40.04 seconds
Started Jul 12 05:31:35 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 206920 kb
Host smart-ddd8ae1d-4661-4e2f-98f1-823ad64a0d74
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3994715160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3994715160
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.3280640695
Short name T725
Test name
Test status
Simulation time 13573867704 ps
CPU time 116.32 seconds
Started Jul 12 05:31:46 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 207044 kb
Host smart-9678116f-2def-4716-ba60-9ac534d03c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32806
40695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.3280640695
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3669768753
Short name T1310
Test name
Test status
Simulation time 200231952 ps
CPU time 0.87 seconds
Started Jul 12 05:31:51 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 206832 kb
Host smart-92803a2f-df64-470d-b5fa-c689a6704c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36697
68753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3669768753
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.160436534
Short name T1698
Test name
Test status
Simulation time 23326237390 ps
CPU time 23.84 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:32:13 PM PDT 24
Peak memory 206824 kb
Host smart-d1ccda8f-629d-4969-be60-b6e76d7b41f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16043
6534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.160436534
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.667044127
Short name T2698
Test name
Test status
Simulation time 3325707376 ps
CPU time 3.75 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:06 PM PDT 24
Peak memory 206880 kb
Host smart-6e094329-f08d-477b-b0c6-e08967918560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66704
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.667044127
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.600024419
Short name T2686
Test name
Test status
Simulation time 7546523010 ps
CPU time 66.29 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:32:58 PM PDT 24
Peak memory 207084 kb
Host smart-7fb16e7e-de9b-472f-82fb-5695f3ff96f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60002
4419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.600024419
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2131876282
Short name T1671
Test name
Test status
Simulation time 4971181714 ps
CPU time 36.75 seconds
Started Jul 12 05:31:52 PM PDT 24
Finished Jul 12 05:32:31 PM PDT 24
Peak memory 206888 kb
Host smart-c29a5ac1-ecfa-4b1c-8357-4950a699d1de
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2131876282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2131876282
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3594102054
Short name T2213
Test name
Test status
Simulation time 275309543 ps
CPU time 0.96 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206820 kb
Host smart-70ce6dd5-0cf7-4bde-b39d-bfd8ee12e6fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3594102054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3594102054
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2813502329
Short name T2593
Test name
Test status
Simulation time 191641706 ps
CPU time 0.89 seconds
Started Jul 12 05:31:52 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 206828 kb
Host smart-536bc80c-1889-4bb3-8cb9-efcd1d3d99a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28135
02329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2813502329
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.1502388776
Short name T359
Test name
Test status
Simulation time 4104334647 ps
CPU time 37.34 seconds
Started Jul 12 05:31:43 PM PDT 24
Finished Jul 12 05:32:22 PM PDT 24
Peak memory 207096 kb
Host smart-c1f0b4b7-42f7-42ea-a991-6a584f9ef4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15023
88776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.1502388776
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2269265541
Short name T1498
Test name
Test status
Simulation time 4608860806 ps
CPU time 127.26 seconds
Started Jul 12 05:31:42 PM PDT 24
Finished Jul 12 05:33:51 PM PDT 24
Peak memory 207004 kb
Host smart-eccae12a-b65a-4693-81b8-e9d38e00998f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2269265541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2269265541
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3404479704
Short name T1663
Test name
Test status
Simulation time 180991775 ps
CPU time 0.77 seconds
Started Jul 12 05:31:45 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 206828 kb
Host smart-2ac718af-5045-4b33-b29a-335a8ed141ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3404479704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3404479704
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3757750614
Short name T1592
Test name
Test status
Simulation time 143298989 ps
CPU time 0.74 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:31:50 PM PDT 24
Peak memory 206812 kb
Host smart-f5c9f48c-eebb-43e6-9dc8-d786aadb6af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577
50614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3757750614
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2483343974
Short name T2195
Test name
Test status
Simulation time 234920192 ps
CPU time 0.88 seconds
Started Jul 12 05:31:46 PM PDT 24
Finished Jul 12 05:31:49 PM PDT 24
Peak memory 206792 kb
Host smart-52f94775-b728-462a-884f-81d5429d48e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24833
43974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2483343974
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1411725026
Short name T912
Test name
Test status
Simulation time 172131786 ps
CPU time 0.85 seconds
Started Jul 12 05:31:52 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 206804 kb
Host smart-eb13f398-bbc7-4b77-a09c-621c1f7b6d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14117
25026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1411725026
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1570498446
Short name T1329
Test name
Test status
Simulation time 215612130 ps
CPU time 0.88 seconds
Started Jul 12 05:31:51 PM PDT 24
Finished Jul 12 05:31:54 PM PDT 24
Peak memory 206812 kb
Host smart-cb8a2f16-baa7-404c-b064-681421162e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
98446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1570498446
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.282856733
Short name T1390
Test name
Test status
Simulation time 146524949 ps
CPU time 0.76 seconds
Started Jul 12 05:31:53 PM PDT 24
Finished Jul 12 05:31:57 PM PDT 24
Peak memory 206716 kb
Host smart-54bcfac7-cabb-4153-bf55-ddd7e2184d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
6733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.282856733
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2678639453
Short name T1971
Test name
Test status
Simulation time 172169231 ps
CPU time 0.79 seconds
Started Jul 12 05:31:56 PM PDT 24
Finished Jul 12 05:32:00 PM PDT 24
Peak memory 206724 kb
Host smart-6e9296a8-6d7a-4bba-868e-456cbac21ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26786
39453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2678639453
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.594478501
Short name T1767
Test name
Test status
Simulation time 247729770 ps
CPU time 1 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:31:54 PM PDT 24
Peak memory 206800 kb
Host smart-444d388a-4d28-40bd-b8df-80bf7aa6a57a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=594478501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.594478501
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3916719646
Short name T2293
Test name
Test status
Simulation time 183790602 ps
CPU time 0.76 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206692 kb
Host smart-6499f06c-1f0f-4da1-ac45-0d87612c7f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39167
19646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3916719646
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3392213045
Short name T2725
Test name
Test status
Simulation time 43669262 ps
CPU time 0.65 seconds
Started Jul 12 05:31:46 PM PDT 24
Finished Jul 12 05:31:48 PM PDT 24
Peak memory 206812 kb
Host smart-3ddd3ace-9144-4a10-8846-32252830c9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33922
13045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3392213045
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2565348650
Short name T279
Test name
Test status
Simulation time 7088984476 ps
CPU time 16.8 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:32:06 PM PDT 24
Peak memory 215268 kb
Host smart-f59744f9-d0bc-4a52-b5d0-9f085a585551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25653
48650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2565348650
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.746810977
Short name T2086
Test name
Test status
Simulation time 212390387 ps
CPU time 0.85 seconds
Started Jul 12 05:31:45 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 206820 kb
Host smart-59ae8461-67cd-43c7-bba4-f60fa77d810a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74681
0977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.746810977
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.940977211
Short name T748
Test name
Test status
Simulation time 166744695 ps
CPU time 0.82 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:52 PM PDT 24
Peak memory 206828 kb
Host smart-68c740a2-90b3-4540-b7ad-6f11d664af7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94097
7211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.940977211
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2378755032
Short name T423
Test name
Test status
Simulation time 251364948 ps
CPU time 0.87 seconds
Started Jul 12 05:31:41 PM PDT 24
Finished Jul 12 05:31:44 PM PDT 24
Peak memory 206684 kb
Host smart-b9c9ca9a-9282-4f4f-932b-caedf80782aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
55032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2378755032
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2405872786
Short name T1302
Test name
Test status
Simulation time 179323317 ps
CPU time 0.87 seconds
Started Jul 12 05:31:45 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 206640 kb
Host smart-99405b79-c7f0-426d-8192-faf484a7275b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24058
72786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2405872786
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.328165857
Short name T910
Test name
Test status
Simulation time 139736103 ps
CPU time 0.77 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:31:51 PM PDT 24
Peak memory 206808 kb
Host smart-801e737b-ca19-4ce9-b8a8-eeacb7867f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32816
5857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.328165857
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3652781988
Short name T1413
Test name
Test status
Simulation time 187441848 ps
CPU time 0.8 seconds
Started Jul 12 05:31:35 PM PDT 24
Finished Jul 12 05:31:37 PM PDT 24
Peak memory 206804 kb
Host smart-69ab7036-e438-4b43-b915-03abfbe6f1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36527
81988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3652781988
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.464454261
Short name T892
Test name
Test status
Simulation time 172852269 ps
CPU time 0.84 seconds
Started Jul 12 05:31:40 PM PDT 24
Finished Jul 12 05:31:42 PM PDT 24
Peak memory 206812 kb
Host smart-01528bf8-baa8-4e9b-8f0f-4c4c242ba9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46445
4261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.464454261
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2749230407
Short name T2338
Test name
Test status
Simulation time 307532508 ps
CPU time 1.04 seconds
Started Jul 12 05:31:37 PM PDT 24
Finished Jul 12 05:31:39 PM PDT 24
Peak memory 206700 kb
Host smart-cf2e1787-9cf8-4fd2-b578-495437cab5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27492
30407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2749230407
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.552340497
Short name T1140
Test name
Test status
Simulation time 4187982424 ps
CPU time 109.23 seconds
Started Jul 12 05:31:52 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 206908 kb
Host smart-5cd58e1a-288a-4841-bed5-5c468ade0d94
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=552340497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.552340497
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1308396510
Short name T2204
Test name
Test status
Simulation time 170128757 ps
CPU time 0.79 seconds
Started Jul 12 05:31:43 PM PDT 24
Finished Jul 12 05:31:45 PM PDT 24
Peak memory 206812 kb
Host smart-7f7d01b1-dc87-40e1-bf41-ddfe0ac8ba2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13083
96510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1308396510
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.4068975944
Short name T628
Test name
Test status
Simulation time 167302411 ps
CPU time 0.81 seconds
Started Jul 12 05:31:45 PM PDT 24
Finished Jul 12 05:31:47 PM PDT 24
Peak memory 206812 kb
Host smart-dc497e6b-c994-43a1-a640-c0427d2e9e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40689
75944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.4068975944
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2813492479
Short name T1087
Test name
Test status
Simulation time 330788495 ps
CPU time 1.12 seconds
Started Jul 12 05:31:42 PM PDT 24
Finished Jul 12 05:31:45 PM PDT 24
Peak memory 206816 kb
Host smart-ceef142c-f487-4b29-9f8b-1fc31db55407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28134
92479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2813492479
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.179808753
Short name T396
Test name
Test status
Simulation time 6372866393 ps
CPU time 179.47 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:34:50 PM PDT 24
Peak memory 206916 kb
Host smart-22da1267-cc7b-49f7-bd6f-a603d3148ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17980
8753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.179808753
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.3186587229
Short name T1526
Test name
Test status
Simulation time 74635315 ps
CPU time 0.71 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:31:58 PM PDT 24
Peak memory 206756 kb
Host smart-a54b14d1-b92f-40f0-8a4b-25e13a965716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3186587229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3186587229
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2394315900
Short name T1835
Test name
Test status
Simulation time 3446150400 ps
CPU time 4.56 seconds
Started Jul 12 05:31:51 PM PDT 24
Finished Jul 12 05:31:58 PM PDT 24
Peak memory 206740 kb
Host smart-a887961d-a83c-4b70-967a-3ffe83171368
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2394315900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2394315900
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.517071322
Short name T185
Test name
Test status
Simulation time 13414559110 ps
CPU time 12.29 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:32:04 PM PDT 24
Peak memory 206852 kb
Host smart-48df29a4-a516-4d9e-a97c-ac79f627e2e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=517071322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.517071322
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3224365517
Short name T586
Test name
Test status
Simulation time 23382236824 ps
CPU time 24.47 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:27 PM PDT 24
Peak memory 207080 kb
Host smart-e77a59dd-40be-416d-a2e8-bb9285fd5448
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3224365517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3224365517
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.487540065
Short name T706
Test name
Test status
Simulation time 152005840 ps
CPU time 0.81 seconds
Started Jul 12 05:31:52 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 206812 kb
Host smart-cb088568-20d5-48ae-b58f-d5e95f8269fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48754
0065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.487540065
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3589092981
Short name T871
Test name
Test status
Simulation time 161024553 ps
CPU time 0.78 seconds
Started Jul 12 05:31:56 PM PDT 24
Finished Jul 12 05:32:00 PM PDT 24
Peak memory 206720 kb
Host smart-c658f8ee-8420-4df4-9701-71ff91a57e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35890
92981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3589092981
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2730468874
Short name T848
Test name
Test status
Simulation time 471893697 ps
CPU time 1.51 seconds
Started Jul 12 05:31:51 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 206808 kb
Host smart-071e84b9-7ff6-4c83-8f5e-ac9072a36998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
68874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2730468874
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.4089622642
Short name T613
Test name
Test status
Simulation time 619897413 ps
CPU time 1.72 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:31:51 PM PDT 24
Peak memory 206896 kb
Host smart-096f1e51-68bf-4228-b78a-6f9b12646245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896
22642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.4089622642
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1098857638
Short name T1546
Test name
Test status
Simulation time 16527876103 ps
CPU time 31.48 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:32:29 PM PDT 24
Peak memory 206984 kb
Host smart-50c2cade-1880-4e09-81f7-f77ca609ee9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
57638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1098857638
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3870791460
Short name T339
Test name
Test status
Simulation time 452717332 ps
CPU time 1.51 seconds
Started Jul 12 05:31:41 PM PDT 24
Finished Jul 12 05:31:44 PM PDT 24
Peak memory 206796 kb
Host smart-88fb1858-e21b-4251-9cbe-7029acc92321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38707
91460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3870791460
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3380147453
Short name T2145
Test name
Test status
Simulation time 142919148 ps
CPU time 0.75 seconds
Started Jul 12 05:31:54 PM PDT 24
Finished Jul 12 05:31:58 PM PDT 24
Peak memory 206816 kb
Host smart-2ce63dfc-be8b-4a43-8863-e84ddd875668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33801
47453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3380147453
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3560350887
Short name T1226
Test name
Test status
Simulation time 43214030 ps
CPU time 0.66 seconds
Started Jul 12 05:31:41 PM PDT 24
Finished Jul 12 05:31:43 PM PDT 24
Peak memory 206788 kb
Host smart-a7cc06ff-fd00-4ee5-88c5-8a43251209de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35603
50887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3560350887
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2876494344
Short name T2078
Test name
Test status
Simulation time 951268080 ps
CPU time 1.99 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:31:54 PM PDT 24
Peak memory 207016 kb
Host smart-812a93f0-8d6a-4132-ba78-ebcadb6feaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28764
94344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2876494344
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2254980750
Short name T793
Test name
Test status
Simulation time 330863017 ps
CPU time 1.99 seconds
Started Jul 12 05:31:49 PM PDT 24
Finished Jul 12 05:31:53 PM PDT 24
Peak memory 206920 kb
Host smart-572e7193-2ba1-4ccd-84f8-5ae864852faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22549
80750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2254980750
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1471788739
Short name T1146
Test name
Test status
Simulation time 212404496 ps
CPU time 0.94 seconds
Started Jul 12 05:31:51 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 206812 kb
Host smart-789709ef-514a-4a1c-820d-7d108c280134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14717
88739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1471788739
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1401997960
Short name T1972
Test name
Test status
Simulation time 138825494 ps
CPU time 0.75 seconds
Started Jul 12 05:31:36 PM PDT 24
Finished Jul 12 05:31:38 PM PDT 24
Peak memory 206800 kb
Host smart-28b3aa14-1f2e-43e9-9811-cfff794be04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14019
97960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1401997960
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1695990526
Short name T1509
Test name
Test status
Simulation time 207137211 ps
CPU time 0.89 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:31:50 PM PDT 24
Peak memory 206800 kb
Host smart-4ad524e8-43f8-4b81-b989-5152c0e61a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16959
90526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1695990526
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2211147836
Short name T2427
Test name
Test status
Simulation time 9300193916 ps
CPU time 31.01 seconds
Started Jul 12 05:31:39 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 207020 kb
Host smart-3728083a-51ec-4763-a178-5aad48385b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
47836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2211147836
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2415403678
Short name T2645
Test name
Test status
Simulation time 192818138 ps
CPU time 0.93 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:31:51 PM PDT 24
Peak memory 207000 kb
Host smart-cb108843-34b9-4ddf-89de-51adea3acde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24154
03678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2415403678
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.618630776
Short name T186
Test name
Test status
Simulation time 23408552508 ps
CPU time 22.35 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206880 kb
Host smart-54138e3c-82f9-4d3c-a139-e006a2c7e717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61863
0776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.618630776
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2479589385
Short name T2351
Test name
Test status
Simulation time 3277768481 ps
CPU time 3.55 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206744 kb
Host smart-c26d9406-76af-43f8-be98-70d7688322f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
89385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2479589385
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.1905724529
Short name T1469
Test name
Test status
Simulation time 8150102599 ps
CPU time 79.61 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:33:26 PM PDT 24
Peak memory 207252 kb
Host smart-e25c16ae-21d4-4bce-bb88-84dcc80b933f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19057
24529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1905724529
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.52727348
Short name T1061
Test name
Test status
Simulation time 4958260208 ps
CPU time 137.97 seconds
Started Jul 12 05:31:54 PM PDT 24
Finished Jul 12 05:34:15 PM PDT 24
Peak memory 207024 kb
Host smart-ca675ab6-a435-4c5d-9409-42008aa12ab9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=52727348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.52727348
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3469384855
Short name T2030
Test name
Test status
Simulation time 242024693 ps
CPU time 0.92 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:05 PM PDT 24
Peak memory 206820 kb
Host smart-86dec7c7-4020-4f5e-8950-6f7e63566507
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3469384855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3469384855
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1695376148
Short name T2220
Test name
Test status
Simulation time 192090498 ps
CPU time 0.87 seconds
Started Jul 12 05:31:54 PM PDT 24
Finished Jul 12 05:31:58 PM PDT 24
Peak memory 206772 kb
Host smart-e9d423ba-a1f8-443d-9c77-c3e940ebe185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16953
76148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1695376148
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.3335093824
Short name T2348
Test name
Test status
Simulation time 7773715682 ps
CPU time 55.4 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:59 PM PDT 24
Peak memory 207104 kb
Host smart-5c4e1d27-f6f2-4a45-ad5c-501cae9ddf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33350
93824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.3335093824
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1039018411
Short name T1638
Test name
Test status
Simulation time 4080350502 ps
CPU time 112.53 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:34:00 PM PDT 24
Peak memory 207148 kb
Host smart-75861313-1b56-421b-9e5e-598030d28461
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1039018411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1039018411
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2180560590
Short name T2737
Test name
Test status
Simulation time 204526286 ps
CPU time 0.82 seconds
Started Jul 12 05:31:47 PM PDT 24
Finished Jul 12 05:31:50 PM PDT 24
Peak memory 206824 kb
Host smart-10fbbc11-a6fa-47ee-92cb-913e0c897fc3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2180560590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2180560590
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1017581737
Short name T1694
Test name
Test status
Simulation time 160224971 ps
CPU time 0.87 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206820 kb
Host smart-90f17536-eec4-445d-98df-7dfa0a775037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10175
81737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1017581737
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3517678281
Short name T137
Test name
Test status
Simulation time 209287689 ps
CPU time 0.91 seconds
Started Jul 12 05:34:42 PM PDT 24
Finished Jul 12 05:34:44 PM PDT 24
Peak memory 206804 kb
Host smart-9c841f04-d6d4-49c5-8400-f79327e54905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35176
78281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3517678281
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1223078795
Short name T1680
Test name
Test status
Simulation time 144175079 ps
CPU time 0.82 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206792 kb
Host smart-1a5fc2c6-d051-410e-bf2b-200e40e5263d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12230
78795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1223078795
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1795420920
Short name T896
Test name
Test status
Simulation time 222047630 ps
CPU time 0.91 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:31:59 PM PDT 24
Peak memory 206808 kb
Host smart-1b928321-3a48-48ef-8984-daf2df4fc2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
20920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1795420920
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.346868974
Short name T2582
Test name
Test status
Simulation time 182432474 ps
CPU time 0.85 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206792 kb
Host smart-6880a380-aab9-47a6-92b7-ab5163a51698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34686
8974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.346868974
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1204309860
Short name T1794
Test name
Test status
Simulation time 156643206 ps
CPU time 0.8 seconds
Started Jul 12 05:31:54 PM PDT 24
Finished Jul 12 05:31:57 PM PDT 24
Peak memory 206760 kb
Host smart-5f9e10ab-7c94-4499-93f2-ff0dda5a14a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12043
09860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1204309860
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1751248274
Short name T647
Test name
Test status
Simulation time 247164740 ps
CPU time 0.96 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:05 PM PDT 24
Peak memory 206836 kb
Host smart-688a6c0e-c6d5-4310-a866-0779f0422ab1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1751248274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1751248274
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1145303222
Short name T419
Test name
Test status
Simulation time 150243785 ps
CPU time 0.78 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:31:59 PM PDT 24
Peak memory 206800 kb
Host smart-96a2d4d0-5edc-49af-8f5c-879ac8a6847f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11453
03222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1145303222
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.821841123
Short name T2232
Test name
Test status
Simulation time 79454944 ps
CPU time 0.69 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:05 PM PDT 24
Peak memory 206716 kb
Host smart-e76c8b5a-182a-444f-a098-2861d36bf6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82184
1123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.821841123
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3693329109
Short name T1534
Test name
Test status
Simulation time 7258139863 ps
CPU time 14.79 seconds
Started Jul 12 05:31:56 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 207048 kb
Host smart-96fccc74-92ad-487e-98bd-98373dffb2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36933
29109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3693329109
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.4169024903
Short name T852
Test name
Test status
Simulation time 166592509 ps
CPU time 0.83 seconds
Started Jul 12 05:31:53 PM PDT 24
Finished Jul 12 05:31:56 PM PDT 24
Peak memory 206812 kb
Host smart-fdbadfc7-94fd-40ca-89d1-1731f330eaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41690
24903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.4169024903
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.614805613
Short name T2460
Test name
Test status
Simulation time 229547137 ps
CPU time 0.88 seconds
Started Jul 12 05:31:48 PM PDT 24
Finished Jul 12 05:31:51 PM PDT 24
Peak memory 206700 kb
Host smart-bc3fcd50-bece-49aa-aab4-f96715f0b3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61480
5613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.614805613
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.4135899781
Short name T2731
Test name
Test status
Simulation time 253751391 ps
CPU time 0.98 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206796 kb
Host smart-03d64b6b-0b9a-45d7-83dd-f09f49d30476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
99781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.4135899781
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.166743645
Short name T1858
Test name
Test status
Simulation time 178503905 ps
CPU time 0.83 seconds
Started Jul 12 05:31:52 PM PDT 24
Finished Jul 12 05:31:55 PM PDT 24
Peak memory 206696 kb
Host smart-05e1cbde-2f88-4c84-ae05-e41500da30e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16674
3645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.166743645
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.564846956
Short name T900
Test name
Test status
Simulation time 178021017 ps
CPU time 0.85 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206812 kb
Host smart-5f13df01-1ab0-48e8-90af-68bb0723a661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56484
6956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.564846956
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3456352964
Short name T1265
Test name
Test status
Simulation time 151141545 ps
CPU time 0.84 seconds
Started Jul 12 05:31:50 PM PDT 24
Finished Jul 12 05:31:54 PM PDT 24
Peak memory 206716 kb
Host smart-c10de5fd-aa53-48f4-9004-cb6f9409e3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34563
52964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3456352964
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2013862838
Short name T2499
Test name
Test status
Simulation time 154142244 ps
CPU time 0.76 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:06 PM PDT 24
Peak memory 206716 kb
Host smart-d6700fa6-1c65-4272-ad37-634e12bc3454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20138
62838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2013862838
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.4286475921
Short name T1846
Test name
Test status
Simulation time 229528832 ps
CPU time 0.95 seconds
Started Jul 12 05:31:53 PM PDT 24
Finished Jul 12 05:31:56 PM PDT 24
Peak memory 206692 kb
Host smart-9372cfda-20e4-4ddf-8b58-5b3ce9cd4944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
75921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.4286475921
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3357372323
Short name T1828
Test name
Test status
Simulation time 5281784537 ps
CPU time 144 seconds
Started Jul 12 05:31:53 PM PDT 24
Finished Jul 12 05:34:19 PM PDT 24
Peak memory 206852 kb
Host smart-9761ff51-ab22-45d1-802c-a5f2b0b65547
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3357372323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3357372323
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3637744846
Short name T2639
Test name
Test status
Simulation time 162287477 ps
CPU time 0.79 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:07 PM PDT 24
Peak memory 206696 kb
Host smart-606702dd-da1a-4ea8-bd4b-e8fdf9eb1d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36377
44846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3637744846
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3810870864
Short name T532
Test name
Test status
Simulation time 181501317 ps
CPU time 0.84 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206804 kb
Host smart-81e121c6-dfd3-4575-b747-9e3b4ded2f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38108
70864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3810870864
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.1052033503
Short name T245
Test name
Test status
Simulation time 1369594035 ps
CPU time 2.76 seconds
Started Jul 12 05:31:56 PM PDT 24
Finished Jul 12 05:32:01 PM PDT 24
Peak memory 207012 kb
Host smart-0c770a9f-d434-4dde-8961-801fafd88b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
33503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.1052033503
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.707027100
Short name T1652
Test name
Test status
Simulation time 7582311477 ps
CPU time 68.32 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 207016 kb
Host smart-d4920201-7b1b-4708-a61c-9b043b602884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70702
7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.707027100
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2699851156
Short name T1662
Test name
Test status
Simulation time 72233378 ps
CPU time 0.71 seconds
Started Jul 12 05:32:12 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 206848 kb
Host smart-23f00148-a8fe-4969-82d4-ba25726d47b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2699851156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2699851156
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.644984240
Short name T1377
Test name
Test status
Simulation time 4257618701 ps
CPU time 6.41 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:10 PM PDT 24
Peak memory 207040 kb
Host smart-a11f7d40-f8b9-46db-89ed-0e81569035c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=644984240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.644984240
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1183923086
Short name T1970
Test name
Test status
Simulation time 13384317879 ps
CPU time 13.85 seconds
Started Jul 12 05:31:51 PM PDT 24
Finished Jul 12 05:32:07 PM PDT 24
Peak memory 206892 kb
Host smart-07adcc65-d0f7-4874-a516-35ea5186226f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1183923086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1183923086
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3887578034
Short name T448
Test name
Test status
Simulation time 23384123918 ps
CPU time 23.72 seconds
Started Jul 12 05:31:58 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 207032 kb
Host smart-e12c7502-b97d-4ea4-896a-b4c3193446f9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3887578034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3887578034
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1486776276
Short name T789
Test name
Test status
Simulation time 153234080 ps
CPU time 0.85 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206712 kb
Host smart-e0beb931-93da-4391-ae01-4f6d518aa3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867
76276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1486776276
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.4267499679
Short name T2313
Test name
Test status
Simulation time 172279760 ps
CPU time 0.79 seconds
Started Jul 12 05:32:07 PM PDT 24
Finished Jul 12 05:32:13 PM PDT 24
Peak memory 206820 kb
Host smart-c7e2d3f0-fbf4-4a71-8c5f-03be07aba411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42674
99679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.4267499679
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2177472961
Short name T510
Test name
Test status
Simulation time 455537785 ps
CPU time 1.36 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:10 PM PDT 24
Peak memory 206808 kb
Host smart-f3fd7e96-d4e2-4926-8b6e-1cdb11ccb817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21774
72961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2177472961
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.602997997
Short name T1910
Test name
Test status
Simulation time 613771480 ps
CPU time 1.66 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:05 PM PDT 24
Peak memory 206840 kb
Host smart-5efc798d-5c08-49df-b918-f9ba1c20113d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60299
7997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.602997997
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3922900754
Short name T164
Test name
Test status
Simulation time 10254565425 ps
CPU time 21.8 seconds
Started Jul 12 05:31:54 PM PDT 24
Finished Jul 12 05:32:18 PM PDT 24
Peak memory 206880 kb
Host smart-8267a195-d7eb-4409-b579-05fb5b896b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39229
00754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3922900754
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3857122008
Short name T1257
Test name
Test status
Simulation time 443552994 ps
CPU time 1.39 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206836 kb
Host smart-c0b582dd-d6fa-4a5f-8e23-c1a98c69272b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38571
22008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3857122008
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.4124420022
Short name T1490
Test name
Test status
Simulation time 190578591 ps
CPU time 0.88 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:06 PM PDT 24
Peak memory 206700 kb
Host smart-ab3bcffa-3481-4400-83e1-ffde7e4a6264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41244
20022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.4124420022
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2576436446
Short name T420
Test name
Test status
Simulation time 36016619 ps
CPU time 0.66 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206708 kb
Host smart-969ae3df-f28e-4dec-9d97-ad07bdacaf2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25764
36446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2576436446
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.528329425
Short name T1124
Test name
Test status
Simulation time 1005025723 ps
CPU time 2.52 seconds
Started Jul 12 05:31:58 PM PDT 24
Finished Jul 12 05:32:04 PM PDT 24
Peak memory 207028 kb
Host smart-1c81d403-d7a4-46d7-8159-647f05a4e11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52832
9425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.528329425
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.119747732
Short name T378
Test name
Test status
Simulation time 337462113 ps
CPU time 1.65 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 207004 kb
Host smart-cf3a5b90-e8af-4697-9b9f-476b0fd08a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11974
7732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.119747732
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2290253247
Short name T954
Test name
Test status
Simulation time 222488548 ps
CPU time 0.89 seconds
Started Jul 12 05:31:56 PM PDT 24
Finished Jul 12 05:32:00 PM PDT 24
Peak memory 206808 kb
Host smart-bb3da955-a0c0-4437-bda1-2b999d239397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22902
53247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2290253247
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4214011204
Short name T632
Test name
Test status
Simulation time 159111866 ps
CPU time 0.79 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206784 kb
Host smart-4523d706-6653-4774-94eb-a370e0937aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42140
11204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4214011204
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.4030119111
Short name T247
Test name
Test status
Simulation time 177624714 ps
CPU time 0.86 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206828 kb
Host smart-b5118bb7-c7df-4286-b9be-0c88ff66160b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40301
19111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.4030119111
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.2555030841
Short name T506
Test name
Test status
Simulation time 5490358861 ps
CPU time 145.84 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:34:33 PM PDT 24
Peak memory 206992 kb
Host smart-4a5e8c62-3481-4a61-bf17-a8664e81a8c4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2555030841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2555030841
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.469989717
Short name T250
Test name
Test status
Simulation time 13098919689 ps
CPU time 42.35 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:49 PM PDT 24
Peak memory 207028 kb
Host smart-4209f701-5802-45d9-98e3-3c85819991df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46998
9717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.469989717
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.2308788106
Short name T579
Test name
Test status
Simulation time 243905744 ps
CPU time 0.96 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206688 kb
Host smart-cc56736a-d142-4d4e-942b-49e0eb32592a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23087
88106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2308788106
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.3207321140
Short name T2703
Test name
Test status
Simulation time 23345816106 ps
CPU time 23.04 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 206856 kb
Host smart-88b46f91-e470-4ebf-930c-3c81ab7129c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
21140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3207321140
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2527669970
Short name T1425
Test name
Test status
Simulation time 3334839953 ps
CPU time 3.76 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:10 PM PDT 24
Peak memory 206880 kb
Host smart-db03b538-2022-4b32-a986-1beb1a5af0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
69970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2527669970
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.4131503251
Short name T1893
Test name
Test status
Simulation time 7384093531 ps
CPU time 71.46 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 207104 kb
Host smart-cb251d4b-0412-45d7-aed1-794f66ac8af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
03251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.4131503251
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3256737859
Short name T522
Test name
Test status
Simulation time 5123428206 ps
CPU time 49.37 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:53 PM PDT 24
Peak memory 207284 kb
Host smart-f142f65d-481a-48bd-a92e-c214b3bf829e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3256737859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3256737859
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.405115999
Short name T555
Test name
Test status
Simulation time 241977201 ps
CPU time 0.96 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206764 kb
Host smart-7bdf9052-f2a3-4db6-b74e-7b92f73d0650
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=405115999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.405115999
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2832353545
Short name T2605
Test name
Test status
Simulation time 209761235 ps
CPU time 0.91 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206716 kb
Host smart-41062242-00d7-49ab-a281-2c951f9181d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28323
53545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2832353545
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.796539419
Short name T578
Test name
Test status
Simulation time 3598656418 ps
CPU time 97.85 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:33:47 PM PDT 24
Peak memory 207032 kb
Host smart-254afd54-c1c4-4e00-a302-bc5fee6f51b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79653
9419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.796539419
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2327785471
Short name T547
Test name
Test status
Simulation time 5576902754 ps
CPU time 38.57 seconds
Started Jul 12 05:32:00 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 207000 kb
Host smart-58a2685a-18eb-456f-881f-92e2d2f5013d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2327785471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2327785471
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.4117726570
Short name T1831
Test name
Test status
Simulation time 166180315 ps
CPU time 0.79 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 206812 kb
Host smart-aa572819-5caa-40eb-9e14-39a339599c88
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4117726570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.4117726570
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1792096410
Short name T2625
Test name
Test status
Simulation time 143011056 ps
CPU time 0.78 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206836 kb
Host smart-cc1aafa4-92f2-43e1-a8ef-cef8da6a1348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17920
96410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1792096410
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1028799943
Short name T1405
Test name
Test status
Simulation time 163844908 ps
CPU time 0.84 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206816 kb
Host smart-49cc474f-8ad2-44ea-892a-48266ac0b370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10287
99943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1028799943
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1388914206
Short name T795
Test name
Test status
Simulation time 188459222 ps
CPU time 0.79 seconds
Started Jul 12 05:31:57 PM PDT 24
Finished Jul 12 05:32:01 PM PDT 24
Peak memory 206812 kb
Host smart-9abbea72-6710-406c-a913-3d2573a4128d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13889
14206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1388914206
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.693473145
Short name T1664
Test name
Test status
Simulation time 234770226 ps
CPU time 0.88 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206816 kb
Host smart-79130930-ba46-4289-ac63-1cc1667d94a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69347
3145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.693473145
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2255827422
Short name T2311
Test name
Test status
Simulation time 171531300 ps
CPU time 0.78 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:07 PM PDT 24
Peak memory 206808 kb
Host smart-b7c8c5fb-cfd9-4b1e-b5ff-b9c7b0b43106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22558
27422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2255827422
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.3330872251
Short name T1395
Test name
Test status
Simulation time 246503413 ps
CPU time 0.94 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206808 kb
Host smart-6eff65d5-dae6-4329-8a93-6fb2f0610198
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3330872251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.3330872251
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2218971142
Short name T1952
Test name
Test status
Simulation time 191620489 ps
CPU time 0.8 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:04 PM PDT 24
Peak memory 206632 kb
Host smart-7c3eaf90-b2b7-40e6-843b-bea7c0c4f715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22189
71142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2218971142
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.97292608
Short name T2518
Test name
Test status
Simulation time 56217528 ps
CPU time 0.65 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 206712 kb
Host smart-38fa3dde-8ce4-4ad0-885d-f87a0de864e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97292
608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.97292608
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1309901397
Short name T1513
Test name
Test status
Simulation time 9443101630 ps
CPU time 21.53 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 207108 kb
Host smart-d9943518-5fba-42b7-a291-c45e292fe261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13099
01397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1309901397
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.739013098
Short name T2286
Test name
Test status
Simulation time 165763159 ps
CPU time 0.82 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:31:58 PM PDT 24
Peak memory 206812 kb
Host smart-edf32f76-e7ce-4e1f-8988-151aa301afc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73901
3098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.739013098
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2578340064
Short name T2552
Test name
Test status
Simulation time 262954557 ps
CPU time 0.92 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 206760 kb
Host smart-7879d7ee-5c4a-4331-9f78-3a994d816080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25783
40064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2578340064
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1836154382
Short name T1467
Test name
Test status
Simulation time 190262163 ps
CPU time 0.85 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206824 kb
Host smart-65b94ed3-1301-46a7-9b74-7de38eef748a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18361
54382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1836154382
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2715394583
Short name T1538
Test name
Test status
Simulation time 181059078 ps
CPU time 0.93 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 206812 kb
Host smart-c1ebe4cc-8430-4103-b775-743705e94bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27153
94583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2715394583
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1305045544
Short name T2316
Test name
Test status
Simulation time 139843444 ps
CPU time 0.78 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206672 kb
Host smart-fcbb1f00-cd50-4ef5-99b3-1439c26f9ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13050
45544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1305045544
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3738718742
Short name T1461
Test name
Test status
Simulation time 158248268 ps
CPU time 0.78 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206816 kb
Host smart-83a5ace6-e041-49d7-8f89-a843b111b9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37387
18742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3738718742
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.4144807304
Short name T2440
Test name
Test status
Simulation time 148587820 ps
CPU time 0.77 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206820 kb
Host smart-c4aa0b56-8e84-4d2d-88a9-0e8e3f296a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41448
07304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.4144807304
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3342586062
Short name T1502
Test name
Test status
Simulation time 203576258 ps
CPU time 0.95 seconds
Started Jul 12 05:31:59 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206824 kb
Host smart-0be4a4b5-0169-4b10-8b1b-9f3f85bb199b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33425
86062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3342586062
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3395085426
Short name T1943
Test name
Test status
Simulation time 3921819063 ps
CPU time 38.2 seconds
Started Jul 12 05:32:06 PM PDT 24
Finished Jul 12 05:32:50 PM PDT 24
Peak memory 207000 kb
Host smart-63f8f421-ccae-4131-8909-0316de8dd981
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3395085426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3395085426
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.531950223
Short name T1852
Test name
Test status
Simulation time 238134012 ps
CPU time 0.91 seconds
Started Jul 12 05:31:55 PM PDT 24
Finished Jul 12 05:31:59 PM PDT 24
Peak memory 206800 kb
Host smart-c8043e54-6b4a-4dc8-ab02-22977b2e6dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53195
0223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.531950223
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3649251440
Short name T1031
Test name
Test status
Simulation time 178482501 ps
CPU time 0.8 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 206664 kb
Host smart-fb3919f9-bde2-4d0b-87cc-25dc15e7ee69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36492
51440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3649251440
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.1509125807
Short name T1801
Test name
Test status
Simulation time 1274498716 ps
CPU time 2.88 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206896 kb
Host smart-430bb0bd-e8b4-4140-b8fb-c47d1778651b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15091
25807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1509125807
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.81617378
Short name T2449
Test name
Test status
Simulation time 6353197265 ps
CPU time 172.9 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:35:03 PM PDT 24
Peak memory 207024 kb
Host smart-32263783-3194-4254-a475-3f0255cf7563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81617
378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.81617378
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1156001026
Short name T1286
Test name
Test status
Simulation time 45504346 ps
CPU time 0.69 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206848 kb
Host smart-5a0d4a5b-df97-45be-ae3d-8fb7c4560ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1156001026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1156001026
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1423924930
Short name T1976
Test name
Test status
Simulation time 4046783602 ps
CPU time 4.62 seconds
Started Jul 12 05:32:09 PM PDT 24
Finished Jul 12 05:32:18 PM PDT 24
Peak memory 206904 kb
Host smart-98aea02e-9255-47b5-b075-3003039ec3c1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1423924930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1423924930
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.802941697
Short name T1913
Test name
Test status
Simulation time 13367577129 ps
CPU time 13.7 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 207064 kb
Host smart-90e13341-fa56-4f50-997e-70a053afe837
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=802941697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.802941697
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3839630934
Short name T1086
Test name
Test status
Simulation time 23372307040 ps
CPU time 22.37 seconds
Started Jul 12 05:31:56 PM PDT 24
Finished Jul 12 05:32:22 PM PDT 24
Peak memory 206848 kb
Host smart-9e7b6cf1-f87a-42a5-852f-1c5ff937af44
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3839630934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3839630934
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3830310295
Short name T429
Test name
Test status
Simulation time 205320728 ps
CPU time 0.87 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:07 PM PDT 24
Peak memory 206800 kb
Host smart-96bcef4a-7d2f-4759-9993-1b849ee0cb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38303
10295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3830310295
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3292409871
Short name T2495
Test name
Test status
Simulation time 167944568 ps
CPU time 0.81 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 206720 kb
Host smart-f7d5b82c-f414-4205-a214-43899f6f609b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32924
09871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3292409871
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.3717455295
Short name T1619
Test name
Test status
Simulation time 376916241 ps
CPU time 1.28 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 206632 kb
Host smart-17217da0-4342-41ed-a58f-285e84ad1909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37174
55295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.3717455295
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.4267550126
Short name T1565
Test name
Test status
Simulation time 971658186 ps
CPU time 2.31 seconds
Started Jul 12 05:31:54 PM PDT 24
Finished Jul 12 05:31:59 PM PDT 24
Peak memory 207016 kb
Host smart-b1e7a571-340a-440d-9979-63d825c4e723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42675
50126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.4267550126
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1875560791
Short name T2417
Test name
Test status
Simulation time 13083583986 ps
CPU time 21.79 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:32 PM PDT 24
Peak memory 207084 kb
Host smart-deb029b1-2658-4ee8-b496-bf08867b8e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18755
60791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1875560791
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3661881925
Short name T2711
Test name
Test status
Simulation time 429125897 ps
CPU time 1.35 seconds
Started Jul 12 05:31:58 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206812 kb
Host smart-6861baee-3b5f-46e7-a69b-7a5df5873115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36618
81925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3661881925
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.1764087158
Short name T2477
Test name
Test status
Simulation time 221723964 ps
CPU time 0.84 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206820 kb
Host smart-e9c6540c-9aa8-4001-a9bf-f163456837b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17640
87158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1764087158
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.4196311672
Short name T1392
Test name
Test status
Simulation time 49203038 ps
CPU time 0.66 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:06 PM PDT 24
Peak memory 206820 kb
Host smart-b55c1fa0-0559-482a-a682-d7c610e08486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41963
11672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.4196311672
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2810234524
Short name T654
Test name
Test status
Simulation time 871545268 ps
CPU time 2.14 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206884 kb
Host smart-21abc4fc-1eb8-4f06-ba45-400fa38bc816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28102
34524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2810234524
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1794776648
Short name T1047
Test name
Test status
Simulation time 305326910 ps
CPU time 2.18 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:12 PM PDT 24
Peak memory 206836 kb
Host smart-091ab03b-e191-4df6-8e71-31e9345176f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17947
76648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1794776648
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2881550889
Short name T708
Test name
Test status
Simulation time 171762667 ps
CPU time 0.8 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206808 kb
Host smart-5f5a23ea-12ad-4d8a-914e-e8848eb4c374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28815
50889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2881550889
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1650539991
Short name T1148
Test name
Test status
Simulation time 163231165 ps
CPU time 0.76 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206808 kb
Host smart-f5ceb3f5-37ab-48b2-b507-46d8dd4fa3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16505
39991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1650539991
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1691620474
Short name T1627
Test name
Test status
Simulation time 199313025 ps
CPU time 0.95 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206824 kb
Host smart-bb56c0cd-438a-4999-b355-21f287b63144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16916
20474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1691620474
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.665415114
Short name T788
Test name
Test status
Simulation time 5678876154 ps
CPU time 17.3 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:32:35 PM PDT 24
Peak memory 205928 kb
Host smart-adf61338-7ec1-401f-83e0-21ba6658582f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66541
5114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.665415114
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.197634922
Short name T310
Test name
Test status
Simulation time 221826989 ps
CPU time 0.85 seconds
Started Jul 12 05:32:09 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 206760 kb
Host smart-66b21ded-fb93-4282-a25e-63b75994d8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19763
4922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.197634922
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1630435635
Short name T19
Test name
Test status
Simulation time 23325075959 ps
CPU time 20.93 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:32:38 PM PDT 24
Peak memory 206760 kb
Host smart-d380763e-adc7-46e8-b078-0b3f87febc00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16304
35635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1630435635
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3740032872
Short name T1905
Test name
Test status
Simulation time 3378154005 ps
CPU time 3.55 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 206764 kb
Host smart-aa9c6b83-769d-46b1-80e1-50ce2d658d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37400
32872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3740032872
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2144536302
Short name T2628
Test name
Test status
Simulation time 10253110480 ps
CPU time 271.76 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:36:50 PM PDT 24
Peak memory 207108 kb
Host smart-82216daf-a6b0-4653-a62d-d16f062102f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21445
36302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2144536302
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.961868805
Short name T596
Test name
Test status
Simulation time 6151386837 ps
CPU time 43.19 seconds
Started Jul 12 05:32:06 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 207036 kb
Host smart-883df1b1-1708-4160-af76-6da358b0a4ce
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=961868805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.961868805
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1005493861
Short name T962
Test name
Test status
Simulation time 247353860 ps
CPU time 0.86 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 206808 kb
Host smart-debee815-89a0-4c30-b7a3-5bc7fc0f63cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1005493861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1005493861
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2351326338
Short name T618
Test name
Test status
Simulation time 191318114 ps
CPU time 0.84 seconds
Started Jul 12 05:32:06 PM PDT 24
Finished Jul 12 05:32:12 PM PDT 24
Peak memory 206812 kb
Host smart-3b490312-6fd3-4180-9544-8d91a2d58854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23513
26338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2351326338
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.2988017080
Short name T2650
Test name
Test status
Simulation time 5048158233 ps
CPU time 46.6 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:33:04 PM PDT 24
Peak memory 205652 kb
Host smart-10d9ff89-6eef-4209-90f9-0de13f96444b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29880
17080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.2988017080
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2762181779
Short name T1697
Test name
Test status
Simulation time 5105786054 ps
CPU time 48.76 seconds
Started Jul 12 05:32:01 PM PDT 24
Finished Jul 12 05:32:54 PM PDT 24
Peak memory 207016 kb
Host smart-46698c6a-7b61-4f90-9e9d-36a54b38331e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2762181779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2762181779
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1982421982
Short name T2240
Test name
Test status
Simulation time 187187755 ps
CPU time 0.83 seconds
Started Jul 12 05:32:24 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 206772 kb
Host smart-fdb5536c-c115-4fca-9d61-a125fbe06207
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1982421982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1982421982
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2093776986
Short name T224
Test name
Test status
Simulation time 147991248 ps
CPU time 0.79 seconds
Started Jul 12 05:32:09 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 206816 kb
Host smart-8ed3b5fb-9bc5-4d8a-9fa7-a210f523f761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
76986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2093776986
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3009767670
Short name T133
Test name
Test status
Simulation time 199624617 ps
CPU time 0.85 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206816 kb
Host smart-3fe5bbf5-07d6-4018-82c3-662dd87d1abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30097
67670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3009767670
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.4033993380
Short name T2191
Test name
Test status
Simulation time 157201143 ps
CPU time 0.85 seconds
Started Jul 12 05:32:13 PM PDT 24
Finished Jul 12 05:32:17 PM PDT 24
Peak memory 206804 kb
Host smart-deeb149a-2d6c-4463-b729-5106470dc706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40339
93380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.4033993380
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.4111348488
Short name T1023
Test name
Test status
Simulation time 251713143 ps
CPU time 0.96 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206800 kb
Host smart-4191fd86-9058-4f78-9b31-228a871c6886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
48488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.4111348488
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1729521211
Short name T645
Test name
Test status
Simulation time 164069319 ps
CPU time 0.79 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:32:18 PM PDT 24
Peak memory 206672 kb
Host smart-69868a6a-72ef-499a-bb3d-79bd00c2b058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17295
21211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1729521211
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2149548577
Short name T169
Test name
Test status
Simulation time 152963078 ps
CPU time 0.82 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 206704 kb
Host smart-f47c7d58-c52a-4f05-a300-4a574cf7b6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21495
48577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2149548577
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.1417496991
Short name T1889
Test name
Test status
Simulation time 213328435 ps
CPU time 0.9 seconds
Started Jul 12 05:31:58 PM PDT 24
Finished Jul 12 05:32:02 PM PDT 24
Peak memory 206792 kb
Host smart-45bbf3f7-2c87-4b56-9477-a7c04fb0e6d2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1417496991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.1417496991
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2116773432
Short name T2258
Test name
Test status
Simulation time 166859984 ps
CPU time 0.77 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:10 PM PDT 24
Peak memory 206804 kb
Host smart-106ae902-7633-4464-a63a-331337fa462d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21167
73432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2116773432
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.280524574
Short name T2106
Test name
Test status
Simulation time 43925362 ps
CPU time 0.71 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206804 kb
Host smart-de906b72-2fd7-4ab5-a570-498a5e77edac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28052
4574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.280524574
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.244958476
Short name T251
Test name
Test status
Simulation time 12657326596 ps
CPU time 30.48 seconds
Started Jul 12 05:32:08 PM PDT 24
Finished Jul 12 05:32:43 PM PDT 24
Peak memory 207056 kb
Host smart-3420892d-9294-48ca-a725-bcb5d6e38955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24495
8476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.244958476
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3548801500
Short name T1184
Test name
Test status
Simulation time 212347524 ps
CPU time 0.88 seconds
Started Jul 12 05:32:10 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 206808 kb
Host smart-ff99f11b-3ac0-47a4-a42f-f3b4810a6324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35488
01500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3548801500
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3918059702
Short name T1560
Test name
Test status
Simulation time 271860324 ps
CPU time 0.95 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206980 kb
Host smart-a5a96f67-cd99-4735-b1d0-061ed61ee92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39180
59702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3918059702
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1432988543
Short name T1867
Test name
Test status
Simulation time 225752810 ps
CPU time 0.91 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 207020 kb
Host smart-75c50dad-e9df-4fa7-8721-346d91e5c509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14329
88543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1432988543
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.920733861
Short name T2225
Test name
Test status
Simulation time 175811903 ps
CPU time 0.89 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:21 PM PDT 24
Peak memory 206676 kb
Host smart-a800310a-566f-4910-9a0e-f1922fef1b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92073
3861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.920733861
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.402374611
Short name T1414
Test name
Test status
Simulation time 208079602 ps
CPU time 0.82 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 206676 kb
Host smart-0a56ebb0-5b48-45fd-957c-facf1b33ad75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40237
4611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.402374611
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1235248203
Short name T1670
Test name
Test status
Simulation time 155541732 ps
CPU time 0.83 seconds
Started Jul 12 05:32:06 PM PDT 24
Finished Jul 12 05:32:12 PM PDT 24
Peak memory 206756 kb
Host smart-76be5346-032e-4ef6-b324-f7579f91ce15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12352
48203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1235248203
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4224528980
Short name T1820
Test name
Test status
Simulation time 153221865 ps
CPU time 0.78 seconds
Started Jul 12 05:32:02 PM PDT 24
Finished Jul 12 05:32:08 PM PDT 24
Peak memory 206672 kb
Host smart-7adb7119-7cd5-4249-9935-a679faea6e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42245
28980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4224528980
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.617096984
Short name T569
Test name
Test status
Simulation time 203305529 ps
CPU time 0.91 seconds
Started Jul 12 05:32:13 PM PDT 24
Finished Jul 12 05:32:17 PM PDT 24
Peak memory 206812 kb
Host smart-f74d24a9-5353-427d-87e6-bf34379402ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61709
6984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.617096984
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.687294082
Short name T145
Test name
Test status
Simulation time 4845506755 ps
CPU time 44.37 seconds
Started Jul 12 05:32:04 PM PDT 24
Finished Jul 12 05:32:54 PM PDT 24
Peak memory 206988 kb
Host smart-6d11f657-44c5-4519-ab90-cbeda73a4f6b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=687294082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.687294082
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1078077038
Short name T1052
Test name
Test status
Simulation time 175575936 ps
CPU time 0.82 seconds
Started Jul 12 05:32:07 PM PDT 24
Finished Jul 12 05:32:13 PM PDT 24
Peak memory 206676 kb
Host smart-cf7496d2-309d-4dd1-bc89-d92cc07bf9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10780
77038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1078077038
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3027598534
Short name T570
Test name
Test status
Simulation time 193772304 ps
CPU time 0.89 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206788 kb
Host smart-d8062bdb-cfb6-47e8-95c8-8c7e077aa188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30275
98534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3027598534
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2976423015
Short name T2073
Test name
Test status
Simulation time 402965621 ps
CPU time 1.15 seconds
Started Jul 12 05:32:09 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 206808 kb
Host smart-b5bc097c-4a7c-4c5a-a68e-364c750557ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29764
23015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2976423015
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1400723311
Short name T1292
Test name
Test status
Simulation time 5054034700 ps
CPU time 137.74 seconds
Started Jul 12 05:32:06 PM PDT 24
Finished Jul 12 05:34:29 PM PDT 24
Peak memory 207056 kb
Host smart-bd978a47-53af-4dd0-851f-1e540574cfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14007
23311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1400723311
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.1339440041
Short name T2589
Test name
Test status
Simulation time 161741230 ps
CPU time 0.9 seconds
Started Jul 12 05:31:58 PM PDT 24
Finished Jul 12 05:32:03 PM PDT 24
Peak memory 206820 kb
Host smart-102c55e2-43e9-48ee-a3d2-0647757d2572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
40041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_host_handshake.1339440041
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.3390154660
Short name T1504
Test name
Test status
Simulation time 32768263 ps
CPU time 0.67 seconds
Started Jul 12 05:32:21 PM PDT 24
Finished Jul 12 05:32:24 PM PDT 24
Peak memory 206872 kb
Host smart-125c8912-40bd-431a-9c79-9eb9dcc59d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3390154660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3390154660
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2099325008
Short name T14
Test name
Test status
Simulation time 4439099695 ps
CPU time 4.89 seconds
Started Jul 12 05:32:08 PM PDT 24
Finished Jul 12 05:32:18 PM PDT 24
Peak memory 207080 kb
Host smart-82615334-5680-48b3-8b70-63e87b5a5741
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2099325008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2099325008
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3274317365
Short name T792
Test name
Test status
Simulation time 13289625617 ps
CPU time 11.92 seconds
Started Jul 12 05:32:10 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 206756 kb
Host smart-572b7a79-b66b-4c68-b0fa-8508ce4cfad1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3274317365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3274317365
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1653738129
Short name T215
Test name
Test status
Simulation time 23519707206 ps
CPU time 26.43 seconds
Started Jul 12 05:32:18 PM PDT 24
Finished Jul 12 05:32:48 PM PDT 24
Peak memory 206912 kb
Host smart-ab9647c0-d947-4441-91b2-270a17ef21df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1653738129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1653738129
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.962218938
Short name T1232
Test name
Test status
Simulation time 169815176 ps
CPU time 0.82 seconds
Started Jul 12 05:32:11 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 206824 kb
Host smart-71c63c66-9e68-49c6-a5ec-fc973013f256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96221
8938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.962218938
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2604724544
Short name T1317
Test name
Test status
Simulation time 205991100 ps
CPU time 0.83 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:32:18 PM PDT 24
Peak memory 206716 kb
Host smart-ad4ea97a-2af1-4631-bec2-2f79b26843a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26047
24544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2604724544
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1826173999
Short name T2345
Test name
Test status
Simulation time 483698508 ps
CPU time 1.46 seconds
Started Jul 12 05:32:10 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 207020 kb
Host smart-2e544937-3828-4703-a2ab-2c569cf54cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18261
73999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1826173999
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1683309545
Short name T1806
Test name
Test status
Simulation time 1264735194 ps
CPU time 2.77 seconds
Started Jul 12 05:32:10 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 207020 kb
Host smart-3057e8aa-36e8-47ea-9ac1-3fb00886fe14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16833
09545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1683309545
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3068121483
Short name T1273
Test name
Test status
Simulation time 10291356558 ps
CPU time 19.02 seconds
Started Jul 12 05:32:07 PM PDT 24
Finished Jul 12 05:32:31 PM PDT 24
Peak memory 207084 kb
Host smart-1d4bd17d-b7a0-432d-9592-8c26e1885de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30681
21483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3068121483
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.3623541576
Short name T541
Test name
Test status
Simulation time 465120257 ps
CPU time 1.39 seconds
Started Jul 12 05:32:22 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 206824 kb
Host smart-bd2c76f4-af1b-4eb3-89c0-598108987d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36235
41576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.3623541576
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3442627912
Short name T417
Test name
Test status
Simulation time 194483333 ps
CPU time 0.81 seconds
Started Jul 12 05:32:38 PM PDT 24
Finished Jul 12 05:32:40 PM PDT 24
Peak memory 206672 kb
Host smart-ad63f8e4-f1cb-493f-a997-87e0eb2efde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34426
27912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3442627912
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1654625594
Short name T1353
Test name
Test status
Simulation time 36173853 ps
CPU time 0.64 seconds
Started Jul 12 05:32:20 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 206816 kb
Host smart-8ce66492-84ef-468e-9116-34584b3df7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16546
25594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1654625594
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2019139924
Short name T1035
Test name
Test status
Simulation time 903625915 ps
CPU time 2.3 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 206924 kb
Host smart-0d985a1b-dbf6-4456-a7d6-c914f780a39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20191
39924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2019139924
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1304526919
Short name T81
Test name
Test status
Simulation time 185617594 ps
CPU time 1.73 seconds
Started Jul 12 05:32:11 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 206908 kb
Host smart-5e0c3f57-95f4-404c-b584-d4a3d6b910ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13045
26919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1304526919
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1428865920
Short name T2011
Test name
Test status
Simulation time 165999296 ps
CPU time 0.8 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206792 kb
Host smart-34cfd255-ac13-4db3-add6-7dd1b8680a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14288
65920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1428865920
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3053340099
Short name T2431
Test name
Test status
Simulation time 175881069 ps
CPU time 0.79 seconds
Started Jul 12 05:32:23 PM PDT 24
Finished Jul 12 05:32:25 PM PDT 24
Peak memory 206824 kb
Host smart-4c21a7d5-264c-4bb2-99ea-15d1dbdc1345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30533
40099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3053340099
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3624803451
Short name T2217
Test name
Test status
Simulation time 215053517 ps
CPU time 0.94 seconds
Started Jul 12 05:32:11 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 206804 kb
Host smart-e814e01d-f5cf-48a4-ab94-0aa17670a037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36248
03451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3624803451
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2188966280
Short name T450
Test name
Test status
Simulation time 11981748728 ps
CPU time 104.11 seconds
Started Jul 12 05:32:09 PM PDT 24
Finished Jul 12 05:33:57 PM PDT 24
Peak memory 206896 kb
Host smart-cd12604b-7e36-4c43-8595-e559f7a08d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21889
66280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2188966280
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2697562623
Short name T533
Test name
Test status
Simulation time 163006031 ps
CPU time 0.8 seconds
Started Jul 12 05:32:20 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 206808 kb
Host smart-148fced6-a58e-4a57-9270-f30570b569dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26975
62623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2697562623
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.975461988
Short name T528
Test name
Test status
Simulation time 23323372158 ps
CPU time 23.85 seconds
Started Jul 12 05:32:12 PM PDT 24
Finished Jul 12 05:32:39 PM PDT 24
Peak memory 206868 kb
Host smart-e8097871-09e7-43ef-969d-30c3e9594581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97546
1988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.975461988
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.527285331
Short name T520
Test name
Test status
Simulation time 3360133231 ps
CPU time 3.86 seconds
Started Jul 12 05:32:07 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 206884 kb
Host smart-d1b1f1a6-73cb-4160-8c97-aff069ebaa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52728
5331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.527285331
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2865805717
Short name T1594
Test name
Test status
Simulation time 12161894769 ps
CPU time 86.23 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 207108 kb
Host smart-3b21dc3c-169f-43d3-bf67-1a17e1a02572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28658
05717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2865805717
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.985060505
Short name T4
Test name
Test status
Simulation time 3785522798 ps
CPU time 103.19 seconds
Started Jul 12 05:32:20 PM PDT 24
Finished Jul 12 05:34:06 PM PDT 24
Peak memory 207004 kb
Host smart-864acbea-e525-4fa4-9ee5-e9e7e07ac3a7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=985060505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.985060505
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.1585851972
Short name T878
Test name
Test status
Simulation time 243205634 ps
CPU time 0.9 seconds
Started Jul 12 05:32:11 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 206796 kb
Host smart-1aba7322-67df-4c75-a9b9-64b6efdbf3bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1585851972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.1585851972
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1970837645
Short name T1957
Test name
Test status
Simulation time 190668875 ps
CPU time 0.92 seconds
Started Jul 12 05:32:09 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 206820 kb
Host smart-d4da09a9-eb1a-4568-8423-db14e865a674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19708
37645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1970837645
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.4176080350
Short name T1312
Test name
Test status
Simulation time 3386892467 ps
CPU time 24.57 seconds
Started Jul 12 05:32:10 PM PDT 24
Finished Jul 12 05:32:38 PM PDT 24
Peak memory 207028 kb
Host smart-0556bbb4-09a9-475d-9a3f-e81e1c4553c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41760
80350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.4176080350
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1064672959
Short name T552
Test name
Test status
Simulation time 3346970207 ps
CPU time 24.58 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:33:01 PM PDT 24
Peak memory 207012 kb
Host smart-bbaf1018-a361-40ff-ae95-63237694f45e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1064672959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1064672959
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3038597754
Short name T1043
Test name
Test status
Simulation time 203055772 ps
CPU time 0.83 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:21 PM PDT 24
Peak memory 206808 kb
Host smart-ed0778f1-746c-473d-b222-c290321a6c63
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3038597754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3038597754
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3533104999
Short name T577
Test name
Test status
Simulation time 173577018 ps
CPU time 0.81 seconds
Started Jul 12 05:32:18 PM PDT 24
Finished Jul 12 05:32:22 PM PDT 24
Peak memory 206820 kb
Host smart-6ee51115-33aa-4239-910c-a16fae269bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35331
04999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3533104999
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3177614058
Short name T112
Test name
Test status
Simulation time 193453252 ps
CPU time 0.84 seconds
Started Jul 12 05:32:07 PM PDT 24
Finished Jul 12 05:32:13 PM PDT 24
Peak memory 206768 kb
Host smart-371bc833-ec06-4b19-a07b-3970003bfbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31776
14058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3177614058
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.826702753
Short name T1084
Test name
Test status
Simulation time 155645923 ps
CPU time 0.82 seconds
Started Jul 12 05:32:21 PM PDT 24
Finished Jul 12 05:32:24 PM PDT 24
Peak memory 206816 kb
Host smart-b170dbd4-866d-4719-b5a6-078e7f61767d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82670
2753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.826702753
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.4132099946
Short name T1606
Test name
Test status
Simulation time 179157526 ps
CPU time 0.82 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206812 kb
Host smart-c95b5e56-aec5-40c3-9ab8-cf9742fe71a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41320
99946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.4132099946
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1383388728
Short name T63
Test name
Test status
Simulation time 197489539 ps
CPU time 0.82 seconds
Started Jul 12 05:32:06 PM PDT 24
Finished Jul 12 05:32:12 PM PDT 24
Peak memory 206808 kb
Host smart-56fa6f59-20db-4126-aac3-ca7446e33b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13833
88728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1383388728
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.778455599
Short name T695
Test name
Test status
Simulation time 219958801 ps
CPU time 0.83 seconds
Started Jul 12 05:32:05 PM PDT 24
Finished Jul 12 05:32:11 PM PDT 24
Peak memory 206704 kb
Host smart-cff1d92e-ee4f-4383-8ef3-723dcb704e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77845
5599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.778455599
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.2191273652
Short name T1793
Test name
Test status
Simulation time 207794029 ps
CPU time 0.88 seconds
Started Jul 12 05:32:20 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 206812 kb
Host smart-f5e9d940-941a-4300-8cb7-aab07fcfb081
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2191273652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.2191273652
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2002278411
Short name T466
Test name
Test status
Simulation time 156816424 ps
CPU time 0.78 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206820 kb
Host smart-4fea0bc9-4d75-42a4-a8a1-1ef2fa2af028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20022
78411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2002278411
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.6117224
Short name T1448
Test name
Test status
Simulation time 44974877 ps
CPU time 0.64 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:21 PM PDT 24
Peak memory 206812 kb
Host smart-e8d63860-2369-4df6-bde1-804b4f94031c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61172
24 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.6117224
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2555274516
Short name T237
Test name
Test status
Simulation time 7444861976 ps
CPU time 16.44 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:32:34 PM PDT 24
Peak memory 206968 kb
Host smart-218c5900-199d-4943-80db-dd7d692bea06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25552
74516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2555274516
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1457134330
Short name T2157
Test name
Test status
Simulation time 155153630 ps
CPU time 0.8 seconds
Started Jul 12 05:32:33 PM PDT 24
Finished Jul 12 05:32:34 PM PDT 24
Peak memory 206812 kb
Host smart-deacc323-1f41-4933-984b-4e7771f9c531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14571
34330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1457134330
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1951100701
Short name T1424
Test name
Test status
Simulation time 167123171 ps
CPU time 0.8 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206808 kb
Host smart-a8595926-5588-4e29-b364-d4bc79b3104a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19511
00701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1951100701
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.2282524945
Short name T1753
Test name
Test status
Simulation time 189569114 ps
CPU time 0.81 seconds
Started Jul 12 05:32:03 PM PDT 24
Finished Jul 12 05:32:09 PM PDT 24
Peak memory 206928 kb
Host smart-e0f3e63c-5cf4-48d1-ba40-47a8e6f7a146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22825
24945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.2282524945
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2508422291
Short name T1505
Test name
Test status
Simulation time 160238916 ps
CPU time 0.79 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206808 kb
Host smart-5b59c41c-7a3d-406e-b070-09bfe4c5c119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
22291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2508422291
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.412017193
Short name T342
Test name
Test status
Simulation time 184952542 ps
CPU time 0.78 seconds
Started Jul 12 05:32:12 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 206816 kb
Host smart-2c3a34a7-53b9-48d1-8401-6bbaf67d7317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41201
7193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.412017193
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2842712216
Short name T2383
Test name
Test status
Simulation time 183215248 ps
CPU time 0.8 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:21 PM PDT 24
Peak memory 206708 kb
Host smart-39d7844f-dadb-4d3a-821f-1841d08cc14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
12216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2842712216
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.933964836
Short name T356
Test name
Test status
Simulation time 153856257 ps
CPU time 0.82 seconds
Started Jul 12 05:32:06 PM PDT 24
Finished Jul 12 05:32:12 PM PDT 24
Peak memory 206808 kb
Host smart-8200de55-5ee3-4c9b-8734-becafac89ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93396
4836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.933964836
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1186703501
Short name T740
Test name
Test status
Simulation time 248162860 ps
CPU time 0.91 seconds
Started Jul 12 05:32:09 PM PDT 24
Finished Jul 12 05:32:14 PM PDT 24
Peak memory 206808 kb
Host smart-473b0b8a-2711-44bd-b1e3-74bba83fbdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11867
03501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1186703501
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.628313915
Short name T371
Test name
Test status
Simulation time 6588018471 ps
CPU time 179.34 seconds
Started Jul 12 05:32:08 PM PDT 24
Finished Jul 12 05:35:12 PM PDT 24
Peak memory 207012 kb
Host smart-0fd769d2-90f0-4ec8-8f77-3ac51bb54474
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=628313915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.628313915
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1207391273
Short name T2598
Test name
Test status
Simulation time 188474061 ps
CPU time 0.81 seconds
Started Jul 12 05:32:11 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 206720 kb
Host smart-344fc2c4-30c5-4334-9c9c-7a0730e1eec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
91273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1207391273
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.144318135
Short name T2167
Test name
Test status
Simulation time 246316994 ps
CPU time 0.92 seconds
Started Jul 12 05:32:43 PM PDT 24
Finished Jul 12 05:32:45 PM PDT 24
Peak memory 206808 kb
Host smart-0343382e-1fae-4c64-a901-0cd8b90d5ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14431
8135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.144318135
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3417356039
Short name T1907
Test name
Test status
Simulation time 1381064813 ps
CPU time 2.86 seconds
Started Jul 12 05:32:09 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 206996 kb
Host smart-ca0c7362-46b4-41fa-a90c-8a894e353c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
56039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3417356039
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.315269699
Short name T2199
Test name
Test status
Simulation time 6522948216 ps
CPU time 167.18 seconds
Started Jul 12 05:32:10 PM PDT 24
Finished Jul 12 05:35:01 PM PDT 24
Peak memory 207000 kb
Host smart-bc427ce6-49c6-4233-8403-cfe49b48e1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31526
9699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.315269699
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3271535975
Short name T702
Test name
Test status
Simulation time 78558011 ps
CPU time 0.71 seconds
Started Jul 12 05:26:55 PM PDT 24
Finished Jul 12 05:26:57 PM PDT 24
Peak memory 206752 kb
Host smart-1f858bb5-79b2-47d0-aab8-336ae1d0f297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3271535975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3271535975
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.832567932
Short name T2342
Test name
Test status
Simulation time 3592747171 ps
CPU time 4.35 seconds
Started Jul 12 05:26:41 PM PDT 24
Finished Jul 12 05:26:48 PM PDT 24
Peak memory 206888 kb
Host smart-33edcffb-da3c-4810-95c5-0590c5c30982
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=832567932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.832567932
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.216200417
Short name T1780
Test name
Test status
Simulation time 13364568604 ps
CPU time 14.13 seconds
Started Jul 12 05:26:46 PM PDT 24
Finished Jul 12 05:27:03 PM PDT 24
Peak memory 206840 kb
Host smart-cf9d947e-7549-4fed-8faa-9a48cea00405
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=216200417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.216200417
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1865821944
Short name T1149
Test name
Test status
Simulation time 23343353126 ps
CPU time 28.56 seconds
Started Jul 12 05:26:45 PM PDT 24
Finished Jul 12 05:27:15 PM PDT 24
Peak memory 206888 kb
Host smart-bb30d6ee-2856-46f4-93eb-97052a946906
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1865821944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.1865821944
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3301091602
Short name T2368
Test name
Test status
Simulation time 179638053 ps
CPU time 0.81 seconds
Started Jul 12 05:26:44 PM PDT 24
Finished Jul 12 05:26:47 PM PDT 24
Peak memory 206760 kb
Host smart-be088079-f194-4b8b-9214-dd6891ad8e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33010
91602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3301091602
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.1328021340
Short name T46
Test name
Test status
Simulation time 235439389 ps
CPU time 0.89 seconds
Started Jul 12 05:26:42 PM PDT 24
Finished Jul 12 05:26:45 PM PDT 24
Peak memory 206700 kb
Host smart-4bea861f-e86c-4560-a2ad-2914e74cb7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13280
21340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.1328021340
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.1705505426
Short name T84
Test name
Test status
Simulation time 182795897 ps
CPU time 0.82 seconds
Started Jul 12 05:26:47 PM PDT 24
Finished Jul 12 05:26:50 PM PDT 24
Peak memory 206800 kb
Host smart-e7fc16b9-0f61-409a-8489-dd83141b91e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17055
05426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1705505426
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3490303115
Short name T961
Test name
Test status
Simulation time 206508254 ps
CPU time 0.85 seconds
Started Jul 12 05:26:44 PM PDT 24
Finished Jul 12 05:26:46 PM PDT 24
Peak memory 206724 kb
Host smart-c0211268-b05e-4e48-9193-c740b42a2a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34903
03115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3490303115
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2053454764
Short name T462
Test name
Test status
Simulation time 153721508 ps
CPU time 0.82 seconds
Started Jul 12 05:26:50 PM PDT 24
Finished Jul 12 05:26:52 PM PDT 24
Peak memory 206812 kb
Host smart-c42a66fd-5458-462e-afed-71f06328c0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20534
54764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2053454764
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2446771268
Short name T2067
Test name
Test status
Simulation time 1202641539 ps
CPU time 2.69 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:55 PM PDT 24
Peak memory 206980 kb
Host smart-d5c21056-6fbe-445d-a467-15be9af39459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24467
71268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2446771268
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3173664901
Short name T1081
Test name
Test status
Simulation time 11641621278 ps
CPU time 22.64 seconds
Started Jul 12 05:26:52 PM PDT 24
Finished Jul 12 05:27:16 PM PDT 24
Peak memory 207036 kb
Host smart-e8e8c28b-ddb7-4c36-b923-60982f2108e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31736
64901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3173664901
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.629520307
Short name T430
Test name
Test status
Simulation time 472131703 ps
CPU time 1.42 seconds
Started Jul 12 05:26:53 PM PDT 24
Finished Jul 12 05:26:55 PM PDT 24
Peak memory 206824 kb
Host smart-2f01f108-4e3f-43c5-9f5c-cb4b947c4315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62952
0307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.629520307
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1346017002
Short name T1899
Test name
Test status
Simulation time 139220626 ps
CPU time 0.8 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:53 PM PDT 24
Peak memory 206792 kb
Host smart-ca45c906-ed7a-4864-8e67-999617e8b7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13460
17002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1346017002
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3038134141
Short name T705
Test name
Test status
Simulation time 70555095 ps
CPU time 0.72 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:07 PM PDT 24
Peak memory 206788 kb
Host smart-b78baf11-79dd-4cca-b9e1-6772dbc0bae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30381
34141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3038134141
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.626502663
Short name T2119
Test name
Test status
Simulation time 891651023 ps
CPU time 2.28 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:55 PM PDT 24
Peak memory 206460 kb
Host smart-f8867b58-0b74-4d54-96e1-6f1c7a9ead69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62650
2663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.626502663
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3950708317
Short name T995
Test name
Test status
Simulation time 261191850 ps
CPU time 1.79 seconds
Started Jul 12 05:26:48 PM PDT 24
Finished Jul 12 05:26:51 PM PDT 24
Peak memory 206912 kb
Host smart-446b4b48-5d08-4008-9a3b-9c76d1a626df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39507
08317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3950708317
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.4127882093
Short name T1151
Test name
Test status
Simulation time 83219752415 ps
CPU time 103.14 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 206920 kb
Host smart-24c34bdc-6672-4e37-90ed-54a2e435a175
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4127882093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.4127882093
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2318765979
Short name T1442
Test name
Test status
Simulation time 115428991105 ps
CPU time 168.78 seconds
Started Jul 12 05:27:00 PM PDT 24
Finished Jul 12 05:29:50 PM PDT 24
Peak memory 206884 kb
Host smart-a7659244-8661-4538-83cd-02f4ea28be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318765979 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2318765979
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.2005941892
Short name T1477
Test name
Test status
Simulation time 88101262382 ps
CPU time 110.69 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:28:52 PM PDT 24
Peak memory 206920 kb
Host smart-4661f2e2-3321-445b-9223-96d8057f5ff1
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2005941892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.2005941892
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.387507129
Short name T2003
Test name
Test status
Simulation time 104196309288 ps
CPU time 148.01 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:29:21 PM PDT 24
Peak memory 206476 kb
Host smart-22ee5a5e-5ba2-48a2-a24c-b94344026fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387507129 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.387507129
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.1919414563
Short name T2343
Test name
Test status
Simulation time 114228900183 ps
CPU time 163.92 seconds
Started Jul 12 05:26:50 PM PDT 24
Finished Jul 12 05:29:35 PM PDT 24
Peak memory 207004 kb
Host smart-ffded6cf-1caf-4637-b0a9-f286e0df3a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19194
14563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.1919414563
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3120068947
Short name T697
Test name
Test status
Simulation time 226813215 ps
CPU time 0.89 seconds
Started Jul 12 05:26:53 PM PDT 24
Finished Jul 12 05:26:55 PM PDT 24
Peak memory 206812 kb
Host smart-b0274a16-9fe3-4fe4-83ab-d65f3776a927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200
68947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3120068947
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2674844052
Short name T1811
Test name
Test status
Simulation time 137032431 ps
CPU time 0.78 seconds
Started Jul 12 05:26:50 PM PDT 24
Finished Jul 12 05:26:52 PM PDT 24
Peak memory 206820 kb
Host smart-d84a00ad-3001-4ea6-a905-51ca6faa88c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26748
44052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2674844052
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.836876239
Short name T2424
Test name
Test status
Simulation time 235078552 ps
CPU time 0.96 seconds
Started Jul 12 05:26:50 PM PDT 24
Finished Jul 12 05:26:52 PM PDT 24
Peak memory 206716 kb
Host smart-a2c7a66b-0487-4238-86cd-63630c210715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83687
6239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.836876239
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.1530212273
Short name T2221
Test name
Test status
Simulation time 4640562332 ps
CPU time 40.91 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:27:42 PM PDT 24
Peak memory 206928 kb
Host smart-8113620f-fb5d-486a-9190-953ace18ed56
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1530212273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.1530212273
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3879392662
Short name T643
Test name
Test status
Simulation time 6751114344 ps
CPU time 49.63 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:56 PM PDT 24
Peak memory 206992 kb
Host smart-c9d686f8-9f31-4dac-82d7-1bddc1f37beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38793
92662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3879392662
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3980895661
Short name T1576
Test name
Test status
Simulation time 180119006 ps
CPU time 0.82 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:53 PM PDT 24
Peak memory 206768 kb
Host smart-cd3645d8-2ed5-4ec7-abef-e0caa0df65ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39808
95661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3980895661
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3572343196
Short name T2016
Test name
Test status
Simulation time 23369196659 ps
CPU time 22.85 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:27:16 PM PDT 24
Peak memory 206872 kb
Host smart-27396d10-ade4-457d-8344-c30f35ca3cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35723
43196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3572343196
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3983782211
Short name T2033
Test name
Test status
Simulation time 3291228879 ps
CPU time 3.48 seconds
Started Jul 12 05:26:49 PM PDT 24
Finished Jul 12 05:26:53 PM PDT 24
Peak memory 206876 kb
Host smart-9aa584a8-0dca-43e9-9662-f24388c62752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39837
82211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3983782211
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3492895366
Short name T2479
Test name
Test status
Simulation time 8574493314 ps
CPU time 225.11 seconds
Started Jul 12 05:26:53 PM PDT 24
Finished Jul 12 05:30:39 PM PDT 24
Peak memory 207088 kb
Host smart-953ec407-aa1f-4b6d-9b86-38968dbb8403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34928
95366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3492895366
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2071137304
Short name T1337
Test name
Test status
Simulation time 6171462657 ps
CPU time 55.02 seconds
Started Jul 12 05:26:49 PM PDT 24
Finished Jul 12 05:27:45 PM PDT 24
Peak memory 206868 kb
Host smart-26ecb109-7865-468d-a2f5-37c884d4d864
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2071137304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2071137304
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.112242080
Short name T315
Test name
Test status
Simulation time 272901625 ps
CPU time 0.95 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:53 PM PDT 24
Peak memory 206812 kb
Host smart-3e4497e2-4217-4a0e-a97f-e20974ab8430
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=112242080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.112242080
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1597386216
Short name T1370
Test name
Test status
Simulation time 200696000 ps
CPU time 0.87 seconds
Started Jul 12 05:26:55 PM PDT 24
Finished Jul 12 05:26:57 PM PDT 24
Peak memory 206836 kb
Host smart-565782e0-17da-4c6b-ac0a-2d10f62e2314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15973
86216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1597386216
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2518411241
Short name T2689
Test name
Test status
Simulation time 3353408546 ps
CPU time 91.2 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 207004 kb
Host smart-de364958-017b-40a0-bbc5-660c30b4674a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25184
11241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2518411241
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1586526242
Short name T1860
Test name
Test status
Simulation time 4543070157 ps
CPU time 42.76 seconds
Started Jul 12 05:26:49 PM PDT 24
Finished Jul 12 05:27:33 PM PDT 24
Peak memory 207032 kb
Host smart-5ecd0061-ea90-4768-805a-e1fc4a02e58f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1586526242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1586526242
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1173668076
Short name T2057
Test name
Test status
Simulation time 149943362 ps
CPU time 0.79 seconds
Started Jul 12 05:26:48 PM PDT 24
Finished Jul 12 05:26:50 PM PDT 24
Peak memory 206820 kb
Host smart-94c1e49d-8d9a-4bfd-ab8a-7eb9de62240e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1173668076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1173668076
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3852835071
Short name T1234
Test name
Test status
Simulation time 214307987 ps
CPU time 0.83 seconds
Started Jul 12 05:26:53 PM PDT 24
Finished Jul 12 05:26:55 PM PDT 24
Peak memory 206824 kb
Host smart-447cc9a1-a8a5-4cd0-98a9-8bd6c69d66e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38528
35071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3852835071
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1567238550
Short name T2312
Test name
Test status
Simulation time 210002034 ps
CPU time 0.93 seconds
Started Jul 12 05:26:49 PM PDT 24
Finished Jul 12 05:26:51 PM PDT 24
Peak memory 206820 kb
Host smart-d4fead9e-afcd-4f1c-8b06-72f8d3a3aefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15672
38550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1567238550
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1320962227
Short name T850
Test name
Test status
Simulation time 145495291 ps
CPU time 0.77 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:07 PM PDT 24
Peak memory 206836 kb
Host smart-a8f4adc6-c3ed-470d-a411-308fc0631950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209
62227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1320962227
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2154000348
Short name T391
Test name
Test status
Simulation time 168484046 ps
CPU time 0.83 seconds
Started Jul 12 05:26:55 PM PDT 24
Finished Jul 12 05:26:57 PM PDT 24
Peak memory 206836 kb
Host smart-b8fa7bec-2687-4dca-ab6d-f1972312a491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540
00348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2154000348
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1990819603
Short name T1921
Test name
Test status
Simulation time 174247966 ps
CPU time 0.88 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:07 PM PDT 24
Peak memory 206836 kb
Host smart-ea443d1b-ac88-4067-bb34-c617ab24d16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19908
19603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1990819603
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2682391210
Short name T2576
Test name
Test status
Simulation time 155209600 ps
CPU time 0.83 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:07 PM PDT 24
Peak memory 206772 kb
Host smart-d8a2b390-8d53-445d-8078-eb77b5784b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26823
91210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2682391210
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3690196292
Short name T667
Test name
Test status
Simulation time 207383426 ps
CPU time 0.96 seconds
Started Jul 12 05:26:50 PM PDT 24
Finished Jul 12 05:26:53 PM PDT 24
Peak memory 206820 kb
Host smart-77cc0edc-e0f8-4031-9588-44fb031964af
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3690196292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3690196292
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3450351960
Short name T1512
Test name
Test status
Simulation time 198766283 ps
CPU time 0.85 seconds
Started Jul 12 05:26:51 PM PDT 24
Finished Jul 12 05:26:54 PM PDT 24
Peak memory 206832 kb
Host smart-ad2eed66-6a28-4573-8f0f-caf4fb79701f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34503
51960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3450351960
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2549877659
Short name T2174
Test name
Test status
Simulation time 146662068 ps
CPU time 0.81 seconds
Started Jul 12 05:26:58 PM PDT 24
Finished Jul 12 05:27:01 PM PDT 24
Peak memory 206772 kb
Host smart-47375d81-093b-443a-86f2-d9aad108a461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25498
77659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2549877659
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.256043805
Short name T689
Test name
Test status
Simulation time 40347288 ps
CPU time 0.7 seconds
Started Jul 12 05:26:57 PM PDT 24
Finished Jul 12 05:26:59 PM PDT 24
Peak memory 206808 kb
Host smart-e56a5507-b51e-4c0e-8023-d776afedbb94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25604
3805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.256043805
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3010908771
Short name T248
Test name
Test status
Simulation time 10859288843 ps
CPU time 25.28 seconds
Started Jul 12 05:26:57 PM PDT 24
Finished Jul 12 05:27:25 PM PDT 24
Peak memory 207056 kb
Host smart-2d42a65f-b835-4c32-94c6-c6ebbed7edd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30109
08771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3010908771
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.564611353
Short name T1446
Test name
Test status
Simulation time 183019533 ps
CPU time 0.84 seconds
Started Jul 12 05:26:58 PM PDT 24
Finished Jul 12 05:27:01 PM PDT 24
Peak memory 206792 kb
Host smart-3330b6b2-dbb2-4852-ac89-82670ff676c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56461
1353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.564611353
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3098213842
Short name T753
Test name
Test status
Simulation time 238280331 ps
CPU time 0.91 seconds
Started Jul 12 05:26:57 PM PDT 24
Finished Jul 12 05:27:01 PM PDT 24
Peak memory 206772 kb
Host smart-7727bd00-5300-4a4f-8f08-31eddf05f9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30982
13842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3098213842
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1893610758
Short name T2116
Test name
Test status
Simulation time 10387433066 ps
CPU time 65.23 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:28:06 PM PDT 24
Peak memory 207088 kb
Host smart-c666fb45-68cd-4b31-bbe0-1d43bb028ad3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1893610758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1893610758
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1300632108
Short name T2164
Test name
Test status
Simulation time 12114205702 ps
CPU time 73.24 seconds
Started Jul 12 05:26:56 PM PDT 24
Finished Jul 12 05:28:11 PM PDT 24
Peak memory 206960 kb
Host smart-e07f7ae7-525e-4e52-aa4e-6f00a089c3fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1300632108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1300632108
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.4152002870
Short name T2418
Test name
Test status
Simulation time 17062542911 ps
CPU time 116.54 seconds
Started Jul 12 05:26:56 PM PDT 24
Finished Jul 12 05:28:54 PM PDT 24
Peak memory 207092 kb
Host smart-231d5f97-7162-48db-b179-fc7dc687f82e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4152002870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.4152002870
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.3397732524
Short name T2233
Test name
Test status
Simulation time 211338483 ps
CPU time 0.89 seconds
Started Jul 12 05:26:58 PM PDT 24
Finished Jul 12 05:27:01 PM PDT 24
Peak memory 206824 kb
Host smart-e0a8a013-39b1-483d-9b80-b2159d3b93f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
32524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.3397732524
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.2821181660
Short name T2397
Test name
Test status
Simulation time 156370181 ps
CPU time 0.78 seconds
Started Jul 12 05:26:57 PM PDT 24
Finished Jul 12 05:26:59 PM PDT 24
Peak memory 206820 kb
Host smart-5b9e2af8-dbb5-453b-a4df-245bbe4029b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28211
81660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.2821181660
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.4011868712
Short name T1822
Test name
Test status
Simulation time 141475903 ps
CPU time 0.75 seconds
Started Jul 12 05:26:56 PM PDT 24
Finished Jul 12 05:26:58 PM PDT 24
Peak memory 206828 kb
Host smart-1c261462-0c83-43d7-974a-5375cc2006ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118
68712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.4011868712
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1910239078
Short name T1776
Test name
Test status
Simulation time 184793053 ps
CPU time 0.86 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:27:02 PM PDT 24
Peak memory 206700 kb
Host smart-3234965c-5dd6-4070-b86c-499a7ead0b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19102
39078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1910239078
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.169114
Short name T204
Test name
Test status
Simulation time 674297598 ps
CPU time 1.46 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:27:03 PM PDT 24
Peak memory 224464 kb
Host smart-c45314d4-73cb-4617-9681-3c981203f78c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=169114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.169114
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.3407294319
Short name T2538
Test name
Test status
Simulation time 424202803 ps
CPU time 1.32 seconds
Started Jul 12 05:27:02 PM PDT 24
Finished Jul 12 05:27:04 PM PDT 24
Peak memory 206680 kb
Host smart-3776103b-e89f-4d2a-9265-5001e80e7ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34072
94319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3407294319
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2059192403
Short name T1314
Test name
Test status
Simulation time 310913024 ps
CPU time 1.05 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:27:02 PM PDT 24
Peak memory 206836 kb
Host smart-e5b51fd5-1b9b-40bf-b73f-5dcd908972be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
92403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2059192403
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2273953737
Short name T2529
Test name
Test status
Simulation time 149458212 ps
CPU time 0.78 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:27:01 PM PDT 24
Peak memory 206812 kb
Host smart-4f999bf4-3d1b-4aa2-828c-251ac6c64aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22739
53737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2273953737
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2320533781
Short name T1213
Test name
Test status
Simulation time 167800835 ps
CPU time 0.87 seconds
Started Jul 12 05:26:56 PM PDT 24
Finished Jul 12 05:26:58 PM PDT 24
Peak memory 206816 kb
Host smart-2f9bdb24-677c-451b-8f0e-269c1f4d5724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
33781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2320533781
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2702167111
Short name T672
Test name
Test status
Simulation time 253808598 ps
CPU time 0.98 seconds
Started Jul 12 05:26:59 PM PDT 24
Finished Jul 12 05:27:02 PM PDT 24
Peak memory 206816 kb
Host smart-463c06ec-7fa0-4c56-842a-34a7b170a830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27021
67111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2702167111
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3808629536
Short name T1287
Test name
Test status
Simulation time 6264784622 ps
CPU time 55.57 seconds
Started Jul 12 05:27:00 PM PDT 24
Finished Jul 12 05:27:57 PM PDT 24
Peak memory 207036 kb
Host smart-17a99beb-d53b-4623-9a4b-b1180651991d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3808629536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3808629536
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1875047212
Short name T447
Test name
Test status
Simulation time 192402474 ps
CPU time 0.85 seconds
Started Jul 12 05:26:57 PM PDT 24
Finished Jul 12 05:26:59 PM PDT 24
Peak memory 206704 kb
Host smart-aa362887-148a-4d93-ba73-52e316973cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18750
47212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1875047212
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1818953968
Short name T2446
Test name
Test status
Simulation time 183875563 ps
CPU time 0.84 seconds
Started Jul 12 05:27:00 PM PDT 24
Finished Jul 12 05:27:03 PM PDT 24
Peak memory 206820 kb
Host smart-b0ecbdf1-4c90-47cd-a840-a1b595beb903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18189
53968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1818953968
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2227117488
Short name T2409
Test name
Test status
Simulation time 195504879 ps
CPU time 0.86 seconds
Started Jul 12 05:27:00 PM PDT 24
Finished Jul 12 05:27:03 PM PDT 24
Peak memory 206820 kb
Host smart-0cfdf9cd-3dcc-47e8-a8c3-633958fad34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22271
17488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2227117488
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3195825505
Short name T1628
Test name
Test status
Simulation time 3795208729 ps
CPU time 26.54 seconds
Started Jul 12 05:26:57 PM PDT 24
Finished Jul 12 05:27:26 PM PDT 24
Peak memory 207264 kb
Host smart-900825aa-3da1-45c5-a6ab-df05a32d50cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31958
25505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3195825505
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3963443532
Short name T156
Test name
Test status
Simulation time 12047260657 ps
CPU time 76.68 seconds
Started Jul 12 05:26:56 PM PDT 24
Finished Jul 12 05:28:14 PM PDT 24
Peak memory 207044 kb
Host smart-888aac95-e291-4833-af9b-8682c6db0622
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3963443532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3963443532
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3674224437
Short name T1485
Test name
Test status
Simulation time 35808275 ps
CPU time 0.66 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 206788 kb
Host smart-0e49e99f-19db-46c1-875b-3ee75b87b181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3674224437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3674224437
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.236898808
Short name T2248
Test name
Test status
Simulation time 4099426250 ps
CPU time 4.69 seconds
Started Jul 12 05:32:08 PM PDT 24
Finished Jul 12 05:32:17 PM PDT 24
Peak memory 206848 kb
Host smart-eddd8dd9-415c-415a-9a27-77b65458de61
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=236898808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.236898808
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1199545895
Short name T1164
Test name
Test status
Simulation time 13404932127 ps
CPU time 12.77 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:33 PM PDT 24
Peak memory 206844 kb
Host smart-abfd336a-2d7c-4d19-b6d4-59d471de6bcd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1199545895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1199545895
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.4054011325
Short name T872
Test name
Test status
Simulation time 23403234175 ps
CPU time 25.78 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:46 PM PDT 24
Peak memory 206872 kb
Host smart-3b1ccdef-f3b5-41f0-893d-bf57f4e0dce7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4054011325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.4054011325
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1366679275
Short name T674
Test name
Test status
Simulation time 164960252 ps
CPU time 0.81 seconds
Started Jul 12 05:32:12 PM PDT 24
Finished Jul 12 05:32:16 PM PDT 24
Peak memory 206816 kb
Host smart-ed5636a2-b03d-42e4-97e9-d6e46100b8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13666
79275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1366679275
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.1692831249
Short name T2084
Test name
Test status
Simulation time 142363212 ps
CPU time 0.78 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 206676 kb
Host smart-90667c08-6485-4e2f-8876-40197f44eb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16928
31249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.1692831249
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2052336343
Short name T1975
Test name
Test status
Simulation time 1275154672 ps
CPU time 2.9 seconds
Started Jul 12 05:32:20 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 207016 kb
Host smart-e8b8ff2b-def8-417b-947c-e6e06884c818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20523
36343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2052336343
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1699672187
Short name T175
Test name
Test status
Simulation time 11541682972 ps
CPU time 23.17 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:32:40 PM PDT 24
Peak memory 207004 kb
Host smart-02fa18ba-92e4-44ed-9802-63d0ef4d44de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16996
72187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1699672187
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2240698503
Short name T2710
Test name
Test status
Simulation time 299758775 ps
CPU time 1.03 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:22 PM PDT 24
Peak memory 206840 kb
Host smart-0bfa3410-01c0-4934-ae69-a5ee053485da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22406
98503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2240698503
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_enable.3630064126
Short name T818
Test name
Test status
Simulation time 36588635 ps
CPU time 0.63 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:32:18 PM PDT 24
Peak memory 206696 kb
Host smart-f77dcf2f-5fe1-4f20-a7b2-9e079e07c118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36300
64126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3630064126
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.413305352
Short name T2035
Test name
Test status
Simulation time 863570700 ps
CPU time 2.11 seconds
Started Jul 12 05:32:22 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 207036 kb
Host smart-f87d9e93-8f54-4d62-b237-af30874c4de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41330
5352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.413305352
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.4075161795
Short name T2290
Test name
Test status
Simulation time 329207342 ps
CPU time 2.23 seconds
Started Jul 12 05:32:32 PM PDT 24
Finished Jul 12 05:32:34 PM PDT 24
Peak memory 206856 kb
Host smart-e8f05427-b2bb-4035-907f-3009065284df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
61795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.4075161795
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1987907747
Short name T1313
Test name
Test status
Simulation time 198753573 ps
CPU time 0.83 seconds
Started Jul 12 05:32:11 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 206820 kb
Host smart-639b1eed-b25a-431d-9151-8882ffada164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19879
07747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1987907747
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1346095507
Short name T2385
Test name
Test status
Simulation time 144708028 ps
CPU time 0.81 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 206812 kb
Host smart-72d145f0-ada8-40bf-8293-a6cc0d868936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13460
95507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1346095507
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.547034975
Short name T317
Test name
Test status
Simulation time 202256704 ps
CPU time 0.89 seconds
Started Jul 12 05:32:24 PM PDT 24
Finished Jul 12 05:32:26 PM PDT 24
Peak memory 206816 kb
Host smart-db3812e6-b2ed-4ceb-83b5-b60d664e1f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54703
4975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.547034975
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.1985718440
Short name T98
Test name
Test status
Simulation time 5131028482 ps
CPU time 147.01 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:34:44 PM PDT 24
Peak memory 206992 kb
Host smart-6984fdcd-cd54-4a96-893e-8cd2464a146d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1985718440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.1985718440
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.3271628749
Short name T1351
Test name
Test status
Simulation time 10398101997 ps
CPU time 30.28 seconds
Started Jul 12 05:32:19 PM PDT 24
Finished Jul 12 05:32:52 PM PDT 24
Peak memory 207024 kb
Host smart-7a467e4e-bd78-4308-8c98-12d712cfd109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32716
28749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.3271628749
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.845697131
Short name T820
Test name
Test status
Simulation time 227874784 ps
CPU time 0.9 seconds
Started Jul 12 05:32:16 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 206676 kb
Host smart-21689266-f3d1-4b1f-b6ba-10114eac09a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84569
7131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.845697131
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1427193978
Short name T2744
Test name
Test status
Simulation time 23308485576 ps
CPU time 23.22 seconds
Started Jul 12 05:32:19 PM PDT 24
Finished Jul 12 05:32:45 PM PDT 24
Peak memory 207064 kb
Host smart-b433cb72-1f6a-4773-9d3f-cf48bf91b57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14271
93978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1427193978
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.4079227190
Short name T2246
Test name
Test status
Simulation time 3316057369 ps
CPU time 3.95 seconds
Started Jul 12 05:32:13 PM PDT 24
Finished Jul 12 05:32:20 PM PDT 24
Peak memory 206836 kb
Host smart-f129a460-e570-4d6f-9b86-991bece8cb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40792
27190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.4079227190
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1026268276
Short name T516
Test name
Test status
Simulation time 11143497660 ps
CPU time 103.66 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:34:04 PM PDT 24
Peak memory 207064 kb
Host smart-4d4d23d6-4864-4da4-87c9-c133857026e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10262
68276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1026268276
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3916577514
Short name T943
Test name
Test status
Simulation time 4494663602 ps
CPU time 32.21 seconds
Started Jul 12 05:32:18 PM PDT 24
Finished Jul 12 05:32:54 PM PDT 24
Peak memory 207012 kb
Host smart-b4cfa939-8bfc-4004-b6d9-7876c46ddf36
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3916577514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3916577514
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2299427968
Short name T1176
Test name
Test status
Simulation time 270628267 ps
CPU time 0.97 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 206812 kb
Host smart-1571ea42-60dd-4e64-9a47-b4be917a72a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2299427968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2299427968
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3162756643
Short name T1933
Test name
Test status
Simulation time 207298425 ps
CPU time 0.87 seconds
Started Jul 12 05:32:22 PM PDT 24
Finished Jul 12 05:32:25 PM PDT 24
Peak memory 206808 kb
Host smart-9a9af1ea-4de6-4e2d-8fec-62f5d43cd232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31627
56643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3162756643
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2944829401
Short name T1435
Test name
Test status
Simulation time 5748919464 ps
CPU time 159.67 seconds
Started Jul 12 05:32:21 PM PDT 24
Finished Jul 12 05:35:03 PM PDT 24
Peak memory 207028 kb
Host smart-5108df22-d9a4-445c-be47-a706862fba22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29448
29401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2944829401
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1699255403
Short name T1214
Test name
Test status
Simulation time 7247622621 ps
CPU time 51.1 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 207052 kb
Host smart-775f061f-88d7-4725-81c9-43687185fd04
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1699255403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1699255403
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3185075602
Short name T2081
Test name
Test status
Simulation time 158982921 ps
CPU time 0.83 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:41 PM PDT 24
Peak memory 206812 kb
Host smart-1006eb09-ecfb-4fb1-95d4-22b3b1f5bf06
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3185075602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3185075602
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2484560836
Short name T2138
Test name
Test status
Simulation time 149010423 ps
CPU time 0.78 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 206804 kb
Host smart-71a161e4-0fae-446e-b551-82aa23fce198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24845
60836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2484560836
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.352068647
Short name T115
Test name
Test status
Simulation time 175087257 ps
CPU time 0.81 seconds
Started Jul 12 05:32:34 PM PDT 24
Finished Jul 12 05:32:36 PM PDT 24
Peak memory 206816 kb
Host smart-995ca6ee-bfe6-4290-b0b4-886280cc232d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35206
8647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.352068647
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1148558064
Short name T2182
Test name
Test status
Simulation time 188905965 ps
CPU time 0.85 seconds
Started Jul 12 05:32:21 PM PDT 24
Finished Jul 12 05:32:24 PM PDT 24
Peak memory 206752 kb
Host smart-83c089ab-6f2f-4a4f-a1fe-3260d874645f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11485
58064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1148558064
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1323811905
Short name T2562
Test name
Test status
Simulation time 174984692 ps
CPU time 0.83 seconds
Started Jul 12 05:32:18 PM PDT 24
Finished Jul 12 05:32:22 PM PDT 24
Peak memory 206712 kb
Host smart-9c8e1f31-1189-4b72-8ff5-5e4a4a9bf99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13238
11905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1323811905
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3753673598
Short name T1294
Test name
Test status
Simulation time 183623681 ps
CPU time 0.81 seconds
Started Jul 12 05:32:21 PM PDT 24
Finished Jul 12 05:32:24 PM PDT 24
Peak memory 206828 kb
Host smart-68b61291-92da-43fd-bfec-3ab2351b9d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37536
73598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3753673598
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2579072054
Short name T167
Test name
Test status
Simulation time 201901172 ps
CPU time 0.86 seconds
Started Jul 12 05:32:19 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 206840 kb
Host smart-a4eacfdb-9eab-439d-8639-ed63153f6842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25790
72054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2579072054
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1662873104
Short name T2130
Test name
Test status
Simulation time 297970656 ps
CPU time 1.03 seconds
Started Jul 12 05:32:14 PM PDT 24
Finished Jul 12 05:32:18 PM PDT 24
Peak memory 206724 kb
Host smart-b2d7ffaa-a808-4207-829a-d5bc40f57318
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1662873104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1662873104
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.872701522
Short name T1339
Test name
Test status
Simulation time 145963341 ps
CPU time 0.75 seconds
Started Jul 12 05:32:15 PM PDT 24
Finished Jul 12 05:32:19 PM PDT 24
Peak memory 206804 kb
Host smart-b2d34781-dc84-4abc-856a-6ceb52a73809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87270
1522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.872701522
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.520073247
Short name T2554
Test name
Test status
Simulation time 58953052 ps
CPU time 0.7 seconds
Started Jul 12 05:32:20 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 206684 kb
Host smart-22f0f499-8092-4de7-bc3a-7404dc11a061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52007
3247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.520073247
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3532326437
Short name T86
Test name
Test status
Simulation time 15106234991 ps
CPU time 35.53 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 215248 kb
Host smart-35b60ea0-55a5-4687-9a49-906fbab752ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35323
26437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3532326437
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.800815141
Short name T1362
Test name
Test status
Simulation time 204465173 ps
CPU time 0.89 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:22 PM PDT 24
Peak memory 206792 kb
Host smart-93532a0f-6993-46e0-b8b8-d5794de9a91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80081
5141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.800815141
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.117737599
Short name T1574
Test name
Test status
Simulation time 157146503 ps
CPU time 0.9 seconds
Started Jul 12 05:32:26 PM PDT 24
Finished Jul 12 05:32:27 PM PDT 24
Peak memory 206796 kb
Host smart-c6a20d0c-a125-46a2-92ec-776dbcc30a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11773
7599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.117737599
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.873991587
Short name T1089
Test name
Test status
Simulation time 195824544 ps
CPU time 0.81 seconds
Started Jul 12 05:32:25 PM PDT 24
Finished Jul 12 05:32:27 PM PDT 24
Peak memory 206812 kb
Host smart-8e0105c5-2d5f-4fc3-a61f-fcbc0f939531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87399
1587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.873991587
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.765681277
Short name T993
Test name
Test status
Simulation time 176123876 ps
CPU time 0.84 seconds
Started Jul 12 05:32:17 PM PDT 24
Finished Jul 12 05:32:21 PM PDT 24
Peak memory 206812 kb
Host smart-39167684-d669-4e1a-8ef0-a73ddd927eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76568
1277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.765681277
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.118762300
Short name T2644
Test name
Test status
Simulation time 182035772 ps
CPU time 0.81 seconds
Started Jul 12 05:32:22 PM PDT 24
Finished Jul 12 05:32:25 PM PDT 24
Peak memory 206820 kb
Host smart-2d1dea2d-1b59-4a0d-a0f3-2d296d43be01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11876
2300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.118762300
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2594639300
Short name T726
Test name
Test status
Simulation time 188077028 ps
CPU time 0.84 seconds
Started Jul 12 05:32:19 PM PDT 24
Finished Jul 12 05:32:23 PM PDT 24
Peak memory 206828 kb
Host smart-8a6b038e-4a22-4986-9e1c-0aa9560a085a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25946
39300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2594639300
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2908490048
Short name T1029
Test name
Test status
Simulation time 154525812 ps
CPU time 0.78 seconds
Started Jul 12 05:32:21 PM PDT 24
Finished Jul 12 05:32:24 PM PDT 24
Peak memory 206836 kb
Host smart-33ccb388-e4a8-4257-aed0-bb4486f53d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29084
90048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2908490048
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3189694204
Short name T1160
Test name
Test status
Simulation time 222995535 ps
CPU time 0.95 seconds
Started Jul 12 05:32:11 PM PDT 24
Finished Jul 12 05:32:15 PM PDT 24
Peak memory 206692 kb
Host smart-7f8fa58c-3dee-4270-9885-5d8447a145fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
94204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3189694204
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.866218667
Short name T1637
Test name
Test status
Simulation time 4256850025 ps
CPU time 29.06 seconds
Started Jul 12 05:32:45 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 207084 kb
Host smart-3b9cbc3c-b14f-4244-a38a-14ee1eba7e4d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=866218667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.866218667
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.925359998
Short name T1994
Test name
Test status
Simulation time 167602359 ps
CPU time 0.79 seconds
Started Jul 12 05:32:23 PM PDT 24
Finished Jul 12 05:32:25 PM PDT 24
Peak memory 206756 kb
Host smart-30504a43-ac74-4a5e-906e-432ea5d5a969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92535
9998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.925359998
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1828943824
Short name T344
Test name
Test status
Simulation time 222641186 ps
CPU time 0.86 seconds
Started Jul 12 05:32:34 PM PDT 24
Finished Jul 12 05:32:36 PM PDT 24
Peak memory 206816 kb
Host smart-53f5db39-63f1-49df-8fc2-6dcc8c810628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289
43824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1828943824
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.16371071
Short name T2060
Test name
Test status
Simulation time 500476725 ps
CPU time 1.34 seconds
Started Jul 12 05:32:30 PM PDT 24
Finished Jul 12 05:32:32 PM PDT 24
Peak memory 206836 kb
Host smart-d4f9b298-9c30-452d-b032-c643a679ed24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.16371071
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1540452094
Short name T616
Test name
Test status
Simulation time 4881816341 ps
CPU time 33.6 seconds
Started Jul 12 05:32:41 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 207084 kb
Host smart-1038c37b-dd77-49cb-85b8-7717611f0157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
52094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1540452094
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.309655979
Short name T2635
Test name
Test status
Simulation time 39073409 ps
CPU time 0.67 seconds
Started Jul 12 05:32:34 PM PDT 24
Finished Jul 12 05:32:35 PM PDT 24
Peak memory 206740 kb
Host smart-d0f8a69b-04a4-4597-a1a1-ff3343543443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=309655979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.309655979
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.4197378190
Short name T10
Test name
Test status
Simulation time 4414041306 ps
CPU time 6.24 seconds
Started Jul 12 05:32:34 PM PDT 24
Finished Jul 12 05:32:41 PM PDT 24
Peak memory 206872 kb
Host smart-c39b77b6-91be-4b56-9ed7-9f634bdadb8c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4197378190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.4197378190
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.4220874275
Short name T187
Test name
Test status
Simulation time 13365573024 ps
CPU time 14.44 seconds
Started Jul 12 05:32:36 PM PDT 24
Finished Jul 12 05:32:51 PM PDT 24
Peak memory 206860 kb
Host smart-e046f6e9-1ba1-4fb6-89a9-c1dd24447bb0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4220874275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.4220874275
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.4224428476
Short name T686
Test name
Test status
Simulation time 23355918238 ps
CPU time 23.25 seconds
Started Jul 12 05:32:29 PM PDT 24
Finished Jul 12 05:32:53 PM PDT 24
Peak memory 206888 kb
Host smart-21ea9ee7-1e77-4a92-ab7a-d4ad3285a280
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4224428476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.4224428476
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2561648248
Short name T787
Test name
Test status
Simulation time 185911016 ps
CPU time 0.78 seconds
Started Jul 12 05:32:38 PM PDT 24
Finished Jul 12 05:32:40 PM PDT 24
Peak memory 206768 kb
Host smart-53529b55-ddeb-4f5c-8810-6f524cdbce16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25616
48248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2561648248
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1891704940
Short name T2018
Test name
Test status
Simulation time 192222366 ps
CPU time 0.83 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:32:43 PM PDT 24
Peak memory 206636 kb
Host smart-572acfb3-6113-456d-b11a-72f6d3a55194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18917
04940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1891704940
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3027604669
Short name T696
Test name
Test status
Simulation time 229804235 ps
CPU time 0.95 seconds
Started Jul 12 05:32:47 PM PDT 24
Finished Jul 12 05:32:49 PM PDT 24
Peak memory 206676 kb
Host smart-97ae649c-e2d4-489d-a609-dce4b0d3f3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30276
04669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3027604669
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.319323629
Short name T325
Test name
Test status
Simulation time 567273065 ps
CPU time 1.37 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:41 PM PDT 24
Peak memory 206832 kb
Host smart-c757fbb4-7534-4968-a9e9-054116a12e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31932
3629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.319323629
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1054339699
Short name T1940
Test name
Test status
Simulation time 7842818065 ps
CPU time 15.52 seconds
Started Jul 12 05:32:38 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 207076 kb
Host smart-042c08f0-923f-4912-9e81-d2e787bc0a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543
39699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1054339699
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2723042972
Short name T1185
Test name
Test status
Simulation time 466712389 ps
CPU time 1.49 seconds
Started Jul 12 05:32:21 PM PDT 24
Finished Jul 12 05:32:28 PM PDT 24
Peak memory 206824 kb
Host smart-72d2b47a-6ec5-4117-8b74-9603b2b55056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27230
42972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2723042972
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2037435722
Short name T39
Test name
Test status
Simulation time 147030170 ps
CPU time 0.77 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 206820 kb
Host smart-f8337464-4564-4a21-9721-ed98d604d02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20374
35722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2037435722
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.582073521
Short name T1757
Test name
Test status
Simulation time 51278120 ps
CPU time 0.7 seconds
Started Jul 12 05:32:41 PM PDT 24
Finished Jul 12 05:32:43 PM PDT 24
Peak memory 206752 kb
Host smart-26e41679-9beb-4306-87fc-dbb5454ea69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58207
3521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.582073521
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2907950698
Short name T2135
Test name
Test status
Simulation time 890733343 ps
CPU time 2.23 seconds
Started Jul 12 05:32:44 PM PDT 24
Finished Jul 12 05:32:48 PM PDT 24
Peak memory 206836 kb
Host smart-78e12d83-9288-4466-aef8-738f581fcad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29079
50698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2907950698
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3505498788
Short name T1026
Test name
Test status
Simulation time 179917004 ps
CPU time 1.83 seconds
Started Jul 12 05:32:44 PM PDT 24
Finished Jul 12 05:32:47 PM PDT 24
Peak memory 206812 kb
Host smart-3f3d532b-359a-4fdd-b9a2-68492603feff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
98788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3505498788
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1579162841
Short name T1821
Test name
Test status
Simulation time 186664941 ps
CPU time 0.81 seconds
Started Jul 12 05:32:29 PM PDT 24
Finished Jul 12 05:32:30 PM PDT 24
Peak memory 206808 kb
Host smart-2b86bfc9-197e-480a-b0b6-39d44f183145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15791
62841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1579162841
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3076918414
Short name T397
Test name
Test status
Simulation time 175258118 ps
CPU time 0.82 seconds
Started Jul 12 05:32:34 PM PDT 24
Finished Jul 12 05:32:36 PM PDT 24
Peak memory 206800 kb
Host smart-b6385cb3-2600-4b52-b487-3a697064d29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30769
18414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3076918414
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3491291243
Short name T1216
Test name
Test status
Simulation time 246604838 ps
CPU time 0.99 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:32:37 PM PDT 24
Peak memory 206712 kb
Host smart-30e06497-8882-4440-9ea8-9e0d5b4c579e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34912
91243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3491291243
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2903774909
Short name T236
Test name
Test status
Simulation time 9995863733 ps
CPU time 281.66 seconds
Started Jul 12 05:32:32 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 207008 kb
Host smart-ac07a3af-c72c-441d-b00b-40fe450ed1e2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2903774909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2903774909
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2971750673
Short name T607
Test name
Test status
Simulation time 7671918942 ps
CPU time 66.6 seconds
Started Jul 12 05:32:36 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 207080 kb
Host smart-0f2b1f68-3f0c-4c9a-8a79-2e714a0d9c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29717
50673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2971750673
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2692868319
Short name T983
Test name
Test status
Simulation time 195054630 ps
CPU time 0.85 seconds
Started Jul 12 05:32:33 PM PDT 24
Finished Jul 12 05:32:35 PM PDT 24
Peak memory 206768 kb
Host smart-3c6173bc-9257-4d81-93da-28d670d32309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26928
68319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2692868319
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3004788886
Short name T700
Test name
Test status
Simulation time 23331523325 ps
CPU time 23.4 seconds
Started Jul 12 05:32:20 PM PDT 24
Finished Jul 12 05:32:46 PM PDT 24
Peak memory 206740 kb
Host smart-9beaa27e-cc90-48f8-ab4c-edfb7ad5f4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30047
88886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3004788886
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2865069712
Short name T324
Test name
Test status
Simulation time 3325220602 ps
CPU time 3.54 seconds
Started Jul 12 05:32:41 PM PDT 24
Finished Jul 12 05:32:46 PM PDT 24
Peak memory 206864 kb
Host smart-4453b23a-0c0c-4d68-ac14-c9abbb6296c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28650
69712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2865069712
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.4029970558
Short name T2091
Test name
Test status
Simulation time 7175881765 ps
CPU time 65.13 seconds
Started Jul 12 05:32:26 PM PDT 24
Finished Jul 12 05:33:32 PM PDT 24
Peak memory 207084 kb
Host smart-5c2c1c56-d03c-41ed-84c4-69e4591405f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40299
70558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.4029970558
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.826264159
Short name T1078
Test name
Test status
Simulation time 7692362063 ps
CPU time 216.31 seconds
Started Jul 12 05:32:42 PM PDT 24
Finished Jul 12 05:36:20 PM PDT 24
Peak memory 207012 kb
Host smart-5f9a3d39-af9f-4d35-b538-b8fb0cbfdea6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=826264159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.826264159
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.2065155927
Short name T493
Test name
Test status
Simulation time 266103357 ps
CPU time 0.88 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:32:54 PM PDT 24
Peak memory 206672 kb
Host smart-0f9aeb85-6f6a-4c8e-a4c4-8e0ef28270f2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2065155927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.2065155927
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2315341708
Short name T1723
Test name
Test status
Simulation time 190963587 ps
CPU time 0.87 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 206788 kb
Host smart-da008571-77db-4cad-8988-7075a5fe44d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23153
41708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2315341708
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.145128722
Short name T449
Test name
Test status
Simulation time 5224366195 ps
CPU time 36.98 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 207020 kb
Host smart-9c79b2f7-300d-4734-94b6-c2a2fe0009de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14512
8722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.145128722
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1665830050
Short name T1144
Test name
Test status
Simulation time 3535786583 ps
CPU time 33.2 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:33:09 PM PDT 24
Peak memory 207016 kb
Host smart-58661214-d094-4f46-a6da-698ea43e409c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1665830050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1665830050
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.379344651
Short name T2020
Test name
Test status
Simulation time 182352568 ps
CPU time 0.83 seconds
Started Jul 12 05:32:36 PM PDT 24
Finished Jul 12 05:32:38 PM PDT 24
Peak memory 206764 kb
Host smart-12dadeba-1d7a-4f1b-9219-46b081295a9b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=379344651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.379344651
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3881488901
Short name T1062
Test name
Test status
Simulation time 192749063 ps
CPU time 0.88 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:32:42 PM PDT 24
Peak memory 206688 kb
Host smart-c953c75d-deb0-443c-9146-9caa3df65128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38814
88901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3881488901
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1837013402
Short name T2169
Test name
Test status
Simulation time 190647836 ps
CPU time 0.82 seconds
Started Jul 12 05:32:20 PM PDT 24
Finished Jul 12 05:32:24 PM PDT 24
Peak memory 206804 kb
Host smart-9f0a423d-bd6d-40c6-b7d5-e0d8d4046aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18370
13402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1837013402
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.3046073530
Short name T621
Test name
Test status
Simulation time 150797424 ps
CPU time 0.78 seconds
Started Jul 12 05:32:42 PM PDT 24
Finished Jul 12 05:32:44 PM PDT 24
Peak memory 206764 kb
Host smart-bfdefb31-bc68-4933-8c9a-214b4d3ce2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30460
73530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3046073530
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.362807024
Short name T849
Test name
Test status
Simulation time 144311370 ps
CPU time 0.76 seconds
Started Jul 12 05:32:34 PM PDT 24
Finished Jul 12 05:32:35 PM PDT 24
Peak memory 206816 kb
Host smart-a76c28a1-a83c-4c71-ae0a-2686fcb490e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36280
7024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.362807024
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3610713933
Short name T1443
Test name
Test status
Simulation time 165163980 ps
CPU time 0.79 seconds
Started Jul 12 05:32:43 PM PDT 24
Finished Jul 12 05:32:45 PM PDT 24
Peak memory 206820 kb
Host smart-6dae5d13-3986-415e-8c9e-0cb30a9ee2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36107
13933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3610713933
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.4098053692
Short name T2278
Test name
Test status
Simulation time 152911454 ps
CPU time 0.77 seconds
Started Jul 12 05:32:30 PM PDT 24
Finished Jul 12 05:32:32 PM PDT 24
Peak memory 206704 kb
Host smart-f1758c9a-ea22-4ddd-a6ee-2cd350710fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980
53692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.4098053692
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2630308347
Short name T2019
Test name
Test status
Simulation time 206313208 ps
CPU time 0.89 seconds
Started Jul 12 05:32:29 PM PDT 24
Finished Jul 12 05:32:30 PM PDT 24
Peak memory 206716 kb
Host smart-7bad9e19-e803-47cd-a0b9-99b91d806c85
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2630308347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2630308347
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1495042802
Short name T1004
Test name
Test status
Simulation time 188722229 ps
CPU time 0.86 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:41 PM PDT 24
Peak memory 206796 kb
Host smart-066743c0-6b5d-42ad-b5d9-b18b0d11d89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14950
42802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1495042802
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.879274154
Short name T1785
Test name
Test status
Simulation time 34408142 ps
CPU time 0.66 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:05 PM PDT 24
Peak memory 206788 kb
Host smart-875abacf-033f-422d-af12-4b7374fe2437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87927
4154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.879274154
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3082234326
Short name T1244
Test name
Test status
Simulation time 10398165572 ps
CPU time 23.78 seconds
Started Jul 12 05:32:49 PM PDT 24
Finished Jul 12 05:33:14 PM PDT 24
Peak memory 215252 kb
Host smart-31bec3b7-a313-450c-bdd4-d92abbfc176c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30822
34326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3082234326
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1247165043
Short name T2618
Test name
Test status
Simulation time 155806824 ps
CPU time 0.78 seconds
Started Jul 12 05:36:41 PM PDT 24
Finished Jul 12 05:36:42 PM PDT 24
Peak memory 206804 kb
Host smart-ebfa4d73-a3a7-4367-a3df-955260f25992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12471
65043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1247165043
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3256622767
Short name T593
Test name
Test status
Simulation time 153759582 ps
CPU time 0.79 seconds
Started Jul 12 05:32:46 PM PDT 24
Finished Jul 12 05:32:48 PM PDT 24
Peak memory 206792 kb
Host smart-5a3bee94-3f8f-46c6-ae4e-37c008dca022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566
22767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3256622767
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1087264442
Short name T2508
Test name
Test status
Simulation time 209926089 ps
CPU time 0.86 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:32:59 PM PDT 24
Peak memory 206640 kb
Host smart-db6f2580-f256-47af-b93c-5ced270d8a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10872
64442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1087264442
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1798105809
Short name T2102
Test name
Test status
Simulation time 186996499 ps
CPU time 0.83 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:04 PM PDT 24
Peak memory 206980 kb
Host smart-2e90260c-c9c3-472b-ac49-6a01c129f9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
05809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1798105809
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.406314592
Short name T2714
Test name
Test status
Simulation time 205473566 ps
CPU time 0.84 seconds
Started Jul 12 05:32:41 PM PDT 24
Finished Jul 12 05:32:43 PM PDT 24
Peak memory 206696 kb
Host smart-941edd97-04eb-489e-a85a-6cc0a626744a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40631
4592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.406314592
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3982569259
Short name T2732
Test name
Test status
Simulation time 151916894 ps
CPU time 0.82 seconds
Started Jul 12 05:32:37 PM PDT 24
Finished Jul 12 05:32:38 PM PDT 24
Peak memory 206804 kb
Host smart-d9e7f49f-ba1b-4353-8aad-2d55b689e083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39825
69259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3982569259
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3313773289
Short name T868
Test name
Test status
Simulation time 180543225 ps
CPU time 0.82 seconds
Started Jul 12 05:32:41 PM PDT 24
Finished Jul 12 05:32:43 PM PDT 24
Peak memory 206816 kb
Host smart-3f2a6487-ec90-48db-a040-9161d1b86ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33137
73289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3313773289
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3126765717
Short name T1132
Test name
Test status
Simulation time 201350434 ps
CPU time 0.94 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:56 PM PDT 24
Peak memory 206716 kb
Host smart-89b155c1-f47b-410f-b0d9-3082b6845b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31267
65717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3126765717
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2914845083
Short name T353
Test name
Test status
Simulation time 5350324128 ps
CPU time 39.33 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:33:21 PM PDT 24
Peak memory 207240 kb
Host smart-0a83fc48-5839-4035-a42b-7b2f8fc691c9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2914845083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2914845083
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3701331409
Short name T2112
Test name
Test status
Simulation time 196389042 ps
CPU time 0.87 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:57 PM PDT 24
Peak memory 206816 kb
Host smart-82f519cf-fb0b-4dae-b580-81a5aab168c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37013
31409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3701331409
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.192092037
Short name T627
Test name
Test status
Simulation time 191278889 ps
CPU time 0.82 seconds
Started Jul 12 05:32:44 PM PDT 24
Finished Jul 12 05:32:46 PM PDT 24
Peak memory 206768 kb
Host smart-178465cb-0fb6-439e-91b0-84b5b4e98c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19209
2037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.192092037
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.3675532885
Short name T2063
Test name
Test status
Simulation time 1095034130 ps
CPU time 2.32 seconds
Started Jul 12 05:32:51 PM PDT 24
Finished Jul 12 05:32:54 PM PDT 24
Peak memory 207000 kb
Host smart-87c5b59b-5836-4515-bd62-0fae539b5963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36755
32885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.3675532885
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.957768918
Short name T834
Test name
Test status
Simulation time 5904198262 ps
CPU time 57.25 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:33:34 PM PDT 24
Peak memory 207028 kb
Host smart-a670580f-489b-4a53-b08e-259ef1eed9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95776
8918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.957768918
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3230967086
Short name T559
Test name
Test status
Simulation time 57800437 ps
CPU time 0.7 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:41 PM PDT 24
Peak memory 206860 kb
Host smart-91aa37f4-5284-4ca3-b384-4519204b9ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3230967086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3230967086
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3903856165
Short name T2008
Test name
Test status
Simulation time 4328219300 ps
CPU time 5.77 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:45 PM PDT 24
Peak memory 206760 kb
Host smart-1fe4201d-38b5-41cd-a78b-34606d92a532
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3903856165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3903856165
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1651664212
Short name T1989
Test name
Test status
Simulation time 13338356401 ps
CPU time 14.09 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:33:09 PM PDT 24
Peak memory 206888 kb
Host smart-9b163b6a-4647-41b4-b7bb-440356c5f2e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1651664212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1651664212
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.2213610697
Short name T467
Test name
Test status
Simulation time 23453583762 ps
CPU time 20.93 seconds
Started Jul 12 05:40:07 PM PDT 24
Finished Jul 12 05:40:30 PM PDT 24
Peak memory 207032 kb
Host smart-d55d2533-e44b-4893-af78-d706dabab260
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2213610697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2213610697
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3987649449
Short name T2559
Test name
Test status
Simulation time 188004817 ps
CPU time 0.85 seconds
Started Jul 12 05:32:37 PM PDT 24
Finished Jul 12 05:32:39 PM PDT 24
Peak memory 206816 kb
Host smart-6716cb3a-ca06-4b06-932e-e3e81443287a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39876
49449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3987649449
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2838550126
Short name T1578
Test name
Test status
Simulation time 150935015 ps
CPU time 0.8 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:41 PM PDT 24
Peak memory 206792 kb
Host smart-6a7424b3-e301-4427-9f26-8d55cf50ee54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28385
50126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2838550126
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.4257315309
Short name T2565
Test name
Test status
Simulation time 305185469 ps
CPU time 1.09 seconds
Started Jul 12 05:32:49 PM PDT 24
Finished Jul 12 05:32:52 PM PDT 24
Peak memory 206812 kb
Host smart-699b43a9-e8d3-4af7-98fb-231023b97e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42573
15309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.4257315309
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3871711198
Short name T1036
Test name
Test status
Simulation time 984838795 ps
CPU time 2.32 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:32:43 PM PDT 24
Peak memory 206992 kb
Host smart-ac264a67-f4bc-4536-86d3-566b8018c31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
11198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3871711198
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3942245272
Short name T1959
Test name
Test status
Simulation time 19078762579 ps
CPU time 34.96 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:33:29 PM PDT 24
Peak memory 207084 kb
Host smart-cc42b9b3-585e-4695-965a-c7538e28ec47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
45272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3942245272
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.2147861539
Short name T402
Test name
Test status
Simulation time 432643642 ps
CPU time 1.43 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:32:51 PM PDT 24
Peak memory 206820 kb
Host smart-31e50e94-a9f6-471f-a33b-ed4c966f312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21478
61539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.2147861539
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2368781854
Short name T2237
Test name
Test status
Simulation time 133924246 ps
CPU time 0.74 seconds
Started Jul 12 05:32:42 PM PDT 24
Finished Jul 12 05:32:44 PM PDT 24
Peak memory 206796 kb
Host smart-db451a2e-7a0d-4e5c-a9c6-1c5045e6e90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23687
81854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2368781854
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2090522274
Short name T837
Test name
Test status
Simulation time 53199584 ps
CPU time 0.7 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:32:59 PM PDT 24
Peak memory 206696 kb
Host smart-26ff68a0-2a0b-4062-88ec-5f4630ac443d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20905
22274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2090522274
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2612917086
Short name T718
Test name
Test status
Simulation time 881465209 ps
CPU time 2.15 seconds
Started Jul 12 05:32:46 PM PDT 24
Finished Jul 12 05:32:49 PM PDT 24
Peak memory 206968 kb
Host smart-ec1ee4e5-2dd0-4225-a576-a2b01443ffd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26129
17086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2612917086
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3938534217
Short name T1233
Test name
Test status
Simulation time 190372678 ps
CPU time 2.17 seconds
Started Jul 12 05:32:33 PM PDT 24
Finished Jul 12 05:32:36 PM PDT 24
Peak memory 207028 kb
Host smart-0541a3a5-d4a9-4454-815d-4f38c8f21f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39385
34217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3938534217
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.500625633
Short name T107
Test name
Test status
Simulation time 214907824 ps
CPU time 0.84 seconds
Started Jul 12 05:32:29 PM PDT 24
Finished Jul 12 05:32:30 PM PDT 24
Peak memory 206804 kb
Host smart-30723d59-d06f-4ab2-a527-34205ac1c2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50062
5633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.500625633
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3158882335
Short name T2129
Test name
Test status
Simulation time 146571515 ps
CPU time 0.77 seconds
Started Jul 12 05:32:46 PM PDT 24
Finished Jul 12 05:32:48 PM PDT 24
Peak memory 206812 kb
Host smart-bd1f044a-c1d3-465d-9e77-1eb3afc71ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588
82335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3158882335
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1852680787
Short name T1855
Test name
Test status
Simulation time 290616640 ps
CPU time 1.01 seconds
Started Jul 12 05:32:31 PM PDT 24
Finished Jul 12 05:32:32 PM PDT 24
Peak memory 206828 kb
Host smart-c6b777e4-264c-40cb-9228-b15d049e1844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18526
80787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1852680787
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.231719750
Short name T1129
Test name
Test status
Simulation time 6002739712 ps
CPU time 56.15 seconds
Started Jul 12 05:32:36 PM PDT 24
Finished Jul 12 05:33:33 PM PDT 24
Peak memory 207060 kb
Host smart-26875f6c-0888-4a0c-9a8b-b92a7e56ed9b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=231719750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.231719750
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3668313711
Short name T739
Test name
Test status
Simulation time 219456179 ps
CPU time 0.9 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:32:50 PM PDT 24
Peak memory 206628 kb
Host smart-e7e1756d-9415-4388-93c5-73f98af5dcc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36683
13711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3668313711
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2667615158
Short name T514
Test name
Test status
Simulation time 23343128548 ps
CPU time 25.55 seconds
Started Jul 12 05:32:34 PM PDT 24
Finished Jul 12 05:33:00 PM PDT 24
Peak memory 206728 kb
Host smart-8f2178ab-0b01-411a-8456-c6502f845b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26676
15158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2667615158
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2677048746
Short name T475
Test name
Test status
Simulation time 3336682455 ps
CPU time 4.18 seconds
Started Jul 12 05:32:46 PM PDT 24
Finished Jul 12 05:32:51 PM PDT 24
Peak memory 207084 kb
Host smart-2a1d5ad3-436a-455d-9bf3-3bfebfd9b00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26770
48746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2677048746
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2507258716
Short name T776
Test name
Test status
Simulation time 10861896278 ps
CPU time 77.64 seconds
Started Jul 12 05:32:43 PM PDT 24
Finished Jul 12 05:34:02 PM PDT 24
Peak memory 206968 kb
Host smart-d8bf3a3b-cb56-41bf-ba37-1c5c63595292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25072
58716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2507258716
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3179307604
Short name T524
Test name
Test status
Simulation time 4029432945 ps
CPU time 108.82 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:34:31 PM PDT 24
Peak memory 207044 kb
Host smart-fd92cce0-aa95-4760-beaf-32b8f2144f75
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3179307604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3179307604
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.4229680033
Short name T669
Test name
Test status
Simulation time 242046293 ps
CPU time 0.91 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:40 PM PDT 24
Peak memory 206828 kb
Host smart-6390e8df-2a8c-46c6-a041-fa0f83198d56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4229680033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.4229680033
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1242681479
Short name T1296
Test name
Test status
Simulation time 193039281 ps
CPU time 0.87 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:32:37 PM PDT 24
Peak memory 206836 kb
Host smart-0302f42a-88c0-4ce3-9d7e-6c99d9d02a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12426
81479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1242681479
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2939566054
Short name T2574
Test name
Test status
Simulation time 4168985959 ps
CPU time 111.17 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:34:28 PM PDT 24
Peak memory 206920 kb
Host smart-c9d1b67d-5fa7-4788-842d-b5fa8878f190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29395
66054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2939566054
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3291752575
Short name T2136
Test name
Test status
Simulation time 4549775647 ps
CPU time 41.93 seconds
Started Jul 12 05:32:36 PM PDT 24
Finished Jul 12 05:33:19 PM PDT 24
Peak memory 207024 kb
Host smart-16dff9a8-7c40-4271-a722-e6d82b1e17b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3291752575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3291752575
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3404059746
Short name T2624
Test name
Test status
Simulation time 157212849 ps
CPU time 0.8 seconds
Started Jul 12 05:32:40 PM PDT 24
Finished Jul 12 05:32:43 PM PDT 24
Peak memory 206820 kb
Host smart-76c7d043-c424-4c94-b6f3-d9f4da53890a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3404059746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3404059746
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2185052814
Short name T1333
Test name
Test status
Simulation time 143261278 ps
CPU time 0.76 seconds
Started Jul 12 05:32:42 PM PDT 24
Finished Jul 12 05:32:44 PM PDT 24
Peak memory 206816 kb
Host smart-2269bcd8-3086-4e79-b7a9-f9ea4ccbb1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21850
52814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2185052814
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1810197306
Short name T117
Test name
Test status
Simulation time 188646238 ps
CPU time 0.85 seconds
Started Jul 12 05:32:42 PM PDT 24
Finished Jul 12 05:32:44 PM PDT 24
Peak memory 206812 kb
Host smart-58ea631f-7ba2-4a85-b57a-3cf3a99d3027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18101
97306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1810197306
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.4093789096
Short name T2014
Test name
Test status
Simulation time 159914233 ps
CPU time 0.77 seconds
Started Jul 12 05:32:39 PM PDT 24
Finished Jul 12 05:32:40 PM PDT 24
Peak memory 206820 kb
Host smart-ac0d66b4-10e6-4c00-bead-35125c94879e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
89096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.4093789096
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3384246544
Short name T1990
Test name
Test status
Simulation time 188916621 ps
CPU time 0.83 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206812 kb
Host smart-42d6a0ae-1604-42fd-8261-e2581af7b429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33842
46544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3384246544
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3945163954
Short name T1020
Test name
Test status
Simulation time 199988981 ps
CPU time 0.87 seconds
Started Jul 12 05:32:35 PM PDT 24
Finished Jul 12 05:32:36 PM PDT 24
Peak memory 206672 kb
Host smart-e9b06fb5-c83c-47e9-90ba-9b6335f61baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39451
63954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3945163954
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1672197489
Short name T411
Test name
Test status
Simulation time 172056965 ps
CPU time 0.78 seconds
Started Jul 12 05:32:45 PM PDT 24
Finished Jul 12 05:32:47 PM PDT 24
Peak memory 206720 kb
Host smart-f9cf6cb3-de66-4c6b-8057-89aca78a138f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16721
97489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1672197489
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.474315039
Short name T2279
Test name
Test status
Simulation time 239294335 ps
CPU time 0.94 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:32:50 PM PDT 24
Peak memory 206820 kb
Host smart-2591b9a1-c65d-4c97-a54a-3f98ba398e51
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=474315039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.474315039
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.584926127
Short name T902
Test name
Test status
Simulation time 149144860 ps
CPU time 0.76 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 206764 kb
Host smart-23e1cf4d-1814-4c4f-9ab8-a31332376b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58492
6127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.584926127
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3495582793
Short name T1411
Test name
Test status
Simulation time 31687522 ps
CPU time 0.63 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206804 kb
Host smart-662b7128-9f03-48bf-b916-fa218ab6ae8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34955
82793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3495582793
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.967933994
Short name T1714
Test name
Test status
Simulation time 19590865060 ps
CPU time 43.44 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 207000 kb
Host smart-d7ee1685-ff31-41ec-a401-78c288c357e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96793
3994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.967933994
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1820508441
Short name T2682
Test name
Test status
Simulation time 187926672 ps
CPU time 0.88 seconds
Started Jul 12 05:32:38 PM PDT 24
Finished Jul 12 05:32:39 PM PDT 24
Peak memory 206788 kb
Host smart-b26c336b-6e3a-4303-a10e-0f76a6d3a856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18205
08441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1820508441
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1170258379
Short name T2463
Test name
Test status
Simulation time 248679718 ps
CPU time 0.98 seconds
Started Jul 12 05:32:45 PM PDT 24
Finished Jul 12 05:32:47 PM PDT 24
Peak memory 206692 kb
Host smart-608a0cd3-aa7e-4d11-a129-7ce1b38be0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11702
58379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1170258379
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.4084163339
Short name T2601
Test name
Test status
Simulation time 208868704 ps
CPU time 0.84 seconds
Started Jul 12 05:32:44 PM PDT 24
Finished Jul 12 05:32:46 PM PDT 24
Peak memory 206704 kb
Host smart-bdf2b519-8af7-4bca-b6a2-327ff538444f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40841
63339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.4084163339
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1761767755
Short name T2198
Test name
Test status
Simulation time 171777766 ps
CPU time 0.82 seconds
Started Jul 12 05:33:03 PM PDT 24
Finished Jul 12 05:33:09 PM PDT 24
Peak memory 206820 kb
Host smart-a446ecc6-1c85-40a1-8615-b46fcc696fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17617
67755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1761767755
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3541481162
Short name T2646
Test name
Test status
Simulation time 146894796 ps
CPU time 0.78 seconds
Started Jul 12 05:32:51 PM PDT 24
Finished Jul 12 05:32:52 PM PDT 24
Peak memory 206712 kb
Host smart-b1257360-4970-439c-afb2-39f9171c4b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35414
81162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3541481162
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2624598919
Short name T1079
Test name
Test status
Simulation time 160038724 ps
CPU time 0.75 seconds
Started Jul 12 05:32:43 PM PDT 24
Finished Jul 12 05:32:45 PM PDT 24
Peak memory 206812 kb
Host smart-36f01533-1a61-4d35-b8f2-9fc0eae9ae41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26245
98919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2624598919
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3283423309
Short name T825
Test name
Test status
Simulation time 166396156 ps
CPU time 0.8 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206812 kb
Host smart-a37bcedd-4214-4bf5-90d2-84659bbbac35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
23309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3283423309
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.478946703
Short name T403
Test name
Test status
Simulation time 213525001 ps
CPU time 0.92 seconds
Started Jul 12 05:32:44 PM PDT 24
Finished Jul 12 05:32:46 PM PDT 24
Peak memory 206824 kb
Host smart-e9a9c454-9ca3-45d0-8ec6-c29f9069589a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47894
6703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.478946703
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2153505949
Short name T842
Test name
Test status
Simulation time 4453066643 ps
CPU time 122.7 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:34:53 PM PDT 24
Peak memory 207056 kb
Host smart-6b7458a8-9cca-45d6-8a95-8526b4dd4fc5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2153505949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2153505949
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1914626341
Short name T2268
Test name
Test status
Simulation time 179295815 ps
CPU time 0.78 seconds
Started Jul 12 05:32:49 PM PDT 24
Finished Jul 12 05:32:51 PM PDT 24
Peak memory 206824 kb
Host smart-741dde8b-8d7b-4af6-9f5f-5bac773eb35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19146
26341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1914626341
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1361807296
Short name T575
Test name
Test status
Simulation time 182246481 ps
CPU time 0.85 seconds
Started Jul 12 05:32:46 PM PDT 24
Finished Jul 12 05:32:48 PM PDT 24
Peak memory 206752 kb
Host smart-264204bf-d91a-4ba1-8f40-04a2d05bd4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13618
07296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1361807296
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3923681064
Short name T2633
Test name
Test status
Simulation time 1356260042 ps
CPU time 2.77 seconds
Started Jul 12 05:33:03 PM PDT 24
Finished Jul 12 05:33:11 PM PDT 24
Peak memory 206988 kb
Host smart-8b6f8dde-00e8-4a8a-bfa4-b50078df2340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236
81064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3923681064
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2776488286
Short name T922
Test name
Test status
Simulation time 5430455955 ps
CPU time 47.21 seconds
Started Jul 12 05:32:45 PM PDT 24
Finished Jul 12 05:33:33 PM PDT 24
Peak memory 207080 kb
Host smart-23799960-28c7-4b4b-b441-4c1815fb76e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27764
88286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2776488286
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.4242922391
Short name T1064
Test name
Test status
Simulation time 38934446 ps
CPU time 0.67 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:08 PM PDT 24
Peak memory 206860 kb
Host smart-eb0dd7d2-b7d3-4a8d-9f26-2c6997a39c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4242922391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.4242922391
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.673242164
Short name T906
Test name
Test status
Simulation time 3447577236 ps
CPU time 4.92 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206848 kb
Host smart-dee4079d-b0d7-47fe-ae37-bc4a49f62fc2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=673242164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.673242164
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2982771869
Short name T1174
Test name
Test status
Simulation time 13435371823 ps
CPU time 12.69 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:12 PM PDT 24
Peak memory 206876 kb
Host smart-455ee5c4-acc0-4e13-a8c9-8fda5d4da58b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2982771869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2982771869
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3025793386
Short name T2742
Test name
Test status
Simulation time 23382397698 ps
CPU time 23.68 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:33:20 PM PDT 24
Peak memory 207080 kb
Host smart-2947532b-ac9a-44cf-91f8-3cf243e47c65
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3025793386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3025793386
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.54169745
Short name T495
Test name
Test status
Simulation time 218531092 ps
CPU time 0.89 seconds
Started Jul 12 05:32:50 PM PDT 24
Finished Jul 12 05:32:52 PM PDT 24
Peak memory 206804 kb
Host smart-5778e8bc-1259-4e26-8bb8-b8d0dc80f3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54169
745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.54169745
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.638623891
Short name T1423
Test name
Test status
Simulation time 173910960 ps
CPU time 0.76 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:57 PM PDT 24
Peak memory 206692 kb
Host smart-9ac5fa18-1d1b-4c84-84e0-369a81c389ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63862
3891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.638623891
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.1751545373
Short name T589
Test name
Test status
Simulation time 261271344 ps
CPU time 1.08 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 206720 kb
Host smart-83950b35-5ab1-479b-b35b-322523933d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515
45373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.1751545373
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.4156011330
Short name T934
Test name
Test status
Simulation time 801524282 ps
CPU time 1.95 seconds
Started Jul 12 05:32:44 PM PDT 24
Finished Jul 12 05:32:47 PM PDT 24
Peak memory 206940 kb
Host smart-db7583a0-68a2-44fc-b67c-659befefe914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41560
11330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.4156011330
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3749203768
Short name T99
Test name
Test status
Simulation time 22650275321 ps
CPU time 38.27 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 207036 kb
Host smart-65beb368-1ffa-4a96-b9b4-95ffa3f9c9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37492
03768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3749203768
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.699953280
Short name T1730
Test name
Test status
Simulation time 340512327 ps
CPU time 1.13 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:56 PM PDT 24
Peak memory 207028 kb
Host smart-4931e965-e742-4214-ae70-c948a806de93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69995
3280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.699953280
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3260142228
Short name T1842
Test name
Test status
Simulation time 136077948 ps
CPU time 0.8 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:32:54 PM PDT 24
Peak memory 206800 kb
Host smart-7dd412ee-e9a1-4255-b921-36badc787c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32601
42228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3260142228
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3582728134
Short name T501
Test name
Test status
Simulation time 39795060 ps
CPU time 0.74 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:57 PM PDT 24
Peak memory 206784 kb
Host smart-db0aeb3f-e6be-4592-9d7b-867130066202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35827
28134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3582728134
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1236616759
Short name T1543
Test name
Test status
Simulation time 1084987671 ps
CPU time 2.26 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:32:56 PM PDT 24
Peak memory 206984 kb
Host smart-25ad7ec6-8ec6-4e8b-8114-cf2366ca9e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12366
16759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1236616759
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3214740554
Short name T1383
Test name
Test status
Simulation time 185823813 ps
CPU time 2.05 seconds
Started Jul 12 05:32:50 PM PDT 24
Finished Jul 12 05:32:53 PM PDT 24
Peak memory 207000 kb
Host smart-95d3b392-839f-4fa0-a195-92b215f77bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
40554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3214740554
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2619418529
Short name T2115
Test name
Test status
Simulation time 195281384 ps
CPU time 0.82 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:32:50 PM PDT 24
Peak memory 206816 kb
Host smart-526ab178-a3ea-4ff1-aa45-07666c95b889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26194
18529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2619418529
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3090998803
Short name T1017
Test name
Test status
Simulation time 138613766 ps
CPU time 0.77 seconds
Started Jul 12 05:32:46 PM PDT 24
Finished Jul 12 05:32:48 PM PDT 24
Peak memory 206820 kb
Host smart-bb158a98-ab2d-4ba7-b3c5-6a31052ef3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30909
98803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3090998803
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1076458727
Short name T502
Test name
Test status
Simulation time 207135329 ps
CPU time 0.85 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:57 PM PDT 24
Peak memory 206712 kb
Host smart-dc1bb6bd-7ba0-47af-981b-21542404efe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10764
58727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1076458727
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.2499578760
Short name T1100
Test name
Test status
Simulation time 7858155463 ps
CPU time 53.9 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:53 PM PDT 24
Peak memory 207056 kb
Host smart-f3c9f984-fabb-48a4-8351-6dbe88f12a86
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2499578760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.2499578760
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.1352685830
Short name T1293
Test name
Test status
Simulation time 10777642238 ps
CPU time 90.51 seconds
Started Jul 12 05:32:51 PM PDT 24
Finished Jul 12 05:34:23 PM PDT 24
Peak memory 207020 kb
Host smart-4c47ea81-c37e-4202-be3a-ced17fd7307a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13526
85830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.1352685830
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2963041893
Short name T757
Test name
Test status
Simulation time 203231301 ps
CPU time 0.85 seconds
Started Jul 12 05:32:47 PM PDT 24
Finished Jul 12 05:32:49 PM PDT 24
Peak memory 206808 kb
Host smart-2f0a8a83-cb19-4034-8209-dda1ec8fb6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
41893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2963041893
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1152041507
Short name T1584
Test name
Test status
Simulation time 23306858118 ps
CPU time 22.26 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:33:19 PM PDT 24
Peak memory 206868 kb
Host smart-d6d93d02-7467-4839-b9d0-07dbe359d18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11520
41507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1152041507
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2511146669
Short name T2054
Test name
Test status
Simulation time 3333573183 ps
CPU time 3.72 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:33:00 PM PDT 24
Peak memory 206860 kb
Host smart-9238c318-95a4-4592-b404-161f855ae930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25111
46669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2511146669
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2238407606
Short name T2378
Test name
Test status
Simulation time 11340345966 ps
CPU time 109.08 seconds
Started Jul 12 05:32:56 PM PDT 24
Finished Jul 12 05:34:51 PM PDT 24
Peak memory 206964 kb
Host smart-fa986f52-2742-45fd-9ae1-7ad2d54f0ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22384
07606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2238407606
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2469396731
Short name T631
Test name
Test status
Simulation time 6956798334 ps
CPU time 63.87 seconds
Started Jul 12 05:32:51 PM PDT 24
Finished Jul 12 05:33:56 PM PDT 24
Peak memory 207064 kb
Host smart-33d47136-955a-4e76-9c25-410d03753645
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2469396731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2469396731
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3279171240
Short name T1421
Test name
Test status
Simulation time 241342252 ps
CPU time 0.92 seconds
Started Jul 12 05:32:56 PM PDT 24
Finished Jul 12 05:33:02 PM PDT 24
Peak memory 206816 kb
Host smart-1255b1f8-baf7-4be1-88ab-c5793bbb08af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3279171240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3279171240
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.310261427
Short name T2513
Test name
Test status
Simulation time 205672687 ps
CPU time 0.89 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:32:54 PM PDT 24
Peak memory 206824 kb
Host smart-ca6788f6-0683-4264-be52-652b62f4012e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31026
1427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.310261427
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.1786201979
Short name T2667
Test name
Test status
Simulation time 5183186456 ps
CPU time 145.15 seconds
Started Jul 12 05:32:49 PM PDT 24
Finished Jul 12 05:35:15 PM PDT 24
Peak memory 206960 kb
Host smart-d153990d-4824-4fce-bf19-6760292e4d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17862
01979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.1786201979
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.920867426
Short name T1790
Test name
Test status
Simulation time 5703305777 ps
CPU time 40.08 seconds
Started Jul 12 05:32:50 PM PDT 24
Finished Jul 12 05:33:31 PM PDT 24
Peak memory 207096 kb
Host smart-561dd305-576f-47d0-a8fa-9be37b928ee0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=920867426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.920867426
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2194038129
Short name T622
Test name
Test status
Simulation time 155690928 ps
CPU time 0.81 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 206816 kb
Host smart-5995b370-c3a5-404f-86c3-c00f03d39942
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2194038129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2194038129
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3708939192
Short name T1703
Test name
Test status
Simulation time 184906936 ps
CPU time 0.79 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:00 PM PDT 24
Peak memory 206720 kb
Host smart-b6cfa2a1-c5f9-4924-bb44-6a636d28553a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37089
39192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3708939192
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2597757385
Short name T121
Test name
Test status
Simulation time 167007378 ps
CPU time 0.78 seconds
Started Jul 12 05:32:45 PM PDT 24
Finished Jul 12 05:32:46 PM PDT 24
Peak memory 206812 kb
Host smart-4f032422-f141-4106-9e2a-258e7b09e091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25977
57385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2597757385
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2150434659
Short name T563
Test name
Test status
Simulation time 174185519 ps
CPU time 0.87 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:32:50 PM PDT 24
Peak memory 206692 kb
Host smart-8073309e-869d-4f4d-a099-82c5045834c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21504
34659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2150434659
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.875514822
Short name T543
Test name
Test status
Simulation time 199845711 ps
CPU time 0.78 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:05 PM PDT 24
Peak memory 206684 kb
Host smart-77786616-fd0c-4232-b117-1b27acf4bf7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87551
4822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.875514822
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.154565479
Short name T1865
Test name
Test status
Simulation time 183318382 ps
CPU time 0.81 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:32:58 PM PDT 24
Peak memory 206808 kb
Host smart-57f29186-2a1d-452a-8997-3125b54cb4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15456
5479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.154565479
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.4004063722
Short name T2331
Test name
Test status
Simulation time 212350009 ps
CPU time 0.86 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:57 PM PDT 24
Peak memory 206820 kb
Host smart-e49d3aaa-6b50-44f9-8c20-afa31785cfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40040
63722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.4004063722
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.1585974007
Short name T658
Test name
Test status
Simulation time 258784622 ps
CPU time 0.98 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206820 kb
Host smart-88838b7a-6979-4f08-90d2-7069a6c7eab1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1585974007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.1585974007
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.4049897251
Short name T2661
Test name
Test status
Simulation time 173398149 ps
CPU time 0.75 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:01 PM PDT 24
Peak memory 206716 kb
Host smart-595925d4-5065-47f6-9082-dbe233262c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40498
97251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.4049897251
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2951912624
Short name T1108
Test name
Test status
Simulation time 43577461 ps
CPU time 0.68 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206808 kb
Host smart-6d0820fd-991a-4365-ba10-70fb1d29dcc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29519
12624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2951912624
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.596634880
Short name T249
Test name
Test status
Simulation time 15807595643 ps
CPU time 33.12 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:38 PM PDT 24
Peak memory 206988 kb
Host smart-fafd1b7e-5611-4a83-af43-e53e12922ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59663
4880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.596634880
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2243166406
Short name T1623
Test name
Test status
Simulation time 201920775 ps
CPU time 0.98 seconds
Started Jul 12 05:32:56 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206812 kb
Host smart-39e89b7a-dac7-4763-9b51-01d93c1fe965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22431
66406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2243166406
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2642061389
Short name T1614
Test name
Test status
Simulation time 180137767 ps
CPU time 0.81 seconds
Started Jul 12 05:33:02 PM PDT 24
Finished Jul 12 05:33:09 PM PDT 24
Peak memory 206804 kb
Host smart-d03a1118-ffeb-4f63-9332-277a0a905cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26420
61389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2642061389
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3029855445
Short name T905
Test name
Test status
Simulation time 255239429 ps
CPU time 0.89 seconds
Started Jul 12 05:33:01 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 206796 kb
Host smart-6fa8f5f7-fd96-4a6e-be8f-8bb264c5cd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30298
55445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3029855445
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.28859366
Short name T205
Test name
Test status
Simulation time 182231669 ps
CPU time 0.88 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206812 kb
Host smart-ef8eb558-e287-4b6a-a780-dd5269ea0b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28859
366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.28859366
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2163282145
Short name T1298
Test name
Test status
Simulation time 191303136 ps
CPU time 0.85 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:08 PM PDT 24
Peak memory 206688 kb
Host smart-d95302ac-68dd-4682-a4e3-97f62f45f521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
82145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2163282145
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3139784376
Short name T807
Test name
Test status
Simulation time 161749808 ps
CPU time 0.82 seconds
Started Jul 12 05:32:56 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206792 kb
Host smart-40b3c638-b6cb-425e-9c34-dbbc7b5fea85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31397
84376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3139784376
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.70307028
Short name T1263
Test name
Test status
Simulation time 157760598 ps
CPU time 0.76 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 206800 kb
Host smart-d5228729-1faa-41be-8974-32fa8e369474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70307
028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.70307028
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.3264674367
Short name T641
Test name
Test status
Simulation time 6561618603 ps
CPU time 59.73 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:33:58 PM PDT 24
Peak memory 207056 kb
Host smart-14df012b-2abb-4486-a196-cb66e42b9f96
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3264674367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3264674367
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2757398469
Short name T1066
Test name
Test status
Simulation time 240894239 ps
CPU time 0.84 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:04 PM PDT 24
Peak memory 206980 kb
Host smart-e92684ba-b65f-4625-8388-9db2b74dbd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27573
98469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2757398469
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2340059673
Short name T2013
Test name
Test status
Simulation time 178708573 ps
CPU time 0.8 seconds
Started Jul 12 05:32:56 PM PDT 24
Finished Jul 12 05:33:02 PM PDT 24
Peak memory 206812 kb
Host smart-1e8ec327-a507-4f63-bcbc-53e775b6f4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23400
59673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2340059673
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.449212938
Short name T1235
Test name
Test status
Simulation time 210407326 ps
CPU time 0.88 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:32:58 PM PDT 24
Peak memory 206636 kb
Host smart-c3275de9-46ef-4cbd-9f9f-448f7ebc3fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44921
2938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.449212938
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1043116709
Short name T1750
Test name
Test status
Simulation time 6538906726 ps
CPU time 45.31 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 207072 kb
Host smart-be7225bd-7347-42ee-891c-8218b698f1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10431
16709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1043116709
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3244746960
Short name T2344
Test name
Test status
Simulation time 38759569 ps
CPU time 0.69 seconds
Started Jul 12 05:33:04 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206976 kb
Host smart-00af38f1-e8d2-4b24-b4c5-86069f8f0373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3244746960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3244746960
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2802350310
Short name T1856
Test name
Test status
Simulation time 4438784196 ps
CPU time 5.03 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 207076 kb
Host smart-1c1be5ed-b8d1-4d37-8690-8ea10d7a20f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2802350310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2802350310
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2125005547
Short name T2604
Test name
Test status
Simulation time 13397534941 ps
CPU time 13.16 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:33:11 PM PDT 24
Peak memory 206868 kb
Host smart-364a66c0-c991-4db6-a625-910f9b549166
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2125005547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2125005547
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3307273632
Short name T2210
Test name
Test status
Simulation time 23508789799 ps
CPU time 26.33 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:31 PM PDT 24
Peak memory 206900 kb
Host smart-50102e9b-8be1-435e-bd2f-8f3bc212ad6a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3307273632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3307273632
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.616461303
Short name T2704
Test name
Test status
Simulation time 186599231 ps
CPU time 0.84 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206648 kb
Host smart-d11921a4-d1d2-40c7-a8fe-b151fefb2cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61646
1303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.616461303
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.4287250920
Short name T1673
Test name
Test status
Simulation time 141475861 ps
CPU time 0.82 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:33:00 PM PDT 24
Peak memory 206820 kb
Host smart-adbbceab-b7e9-46a2-b1d7-628bf2e7451f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42872
50920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.4287250920
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2975562709
Short name T2594
Test name
Test status
Simulation time 216825343 ps
CPU time 0.88 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:05 PM PDT 24
Peak memory 206764 kb
Host smart-8f0458bd-d56f-4da1-9a5c-501ae1daa270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29755
62709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2975562709
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1153683936
Short name T991
Test name
Test status
Simulation time 1168326255 ps
CPU time 2.97 seconds
Started Jul 12 05:33:02 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206992 kb
Host smart-7495ff92-4630-4ced-a14d-c8c9ed3b073d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11536
83936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1153683936
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2732101203
Short name T1170
Test name
Test status
Simulation time 20335099698 ps
CPU time 38.49 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 206936 kb
Host smart-8c241f2a-ec29-45ed-a770-75f00af1abf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27321
01203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2732101203
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.4179534650
Short name T1365
Test name
Test status
Simulation time 406226042 ps
CPU time 1.27 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206828 kb
Host smart-9b2af6f0-c823-4022-a5ba-18bb54df32a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41795
34650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.4179534650
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3196208771
Short name T246
Test name
Test status
Simulation time 183711567 ps
CPU time 0.85 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:08 PM PDT 24
Peak memory 206672 kb
Host smart-d62048bc-0697-45dd-9e1b-3cbf7bf5c9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31962
08771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3196208771
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3528916243
Short name T2720
Test name
Test status
Simulation time 43705503 ps
CPU time 0.66 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:56 PM PDT 24
Peak memory 206972 kb
Host smart-e5d86245-d706-4b4c-b4aa-cf434cec7257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35289
16243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3528916243
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2953245850
Short name T2399
Test name
Test status
Simulation time 1011924816 ps
CPU time 2.55 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206952 kb
Host smart-fbfa1ed2-30b7-4666-a49b-a7ccd54248c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29532
45850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2953245850
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3033142805
Short name T537
Test name
Test status
Simulation time 163168528 ps
CPU time 1.56 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:32:51 PM PDT 24
Peak memory 206952 kb
Host smart-10d398ba-6981-4531-85af-b203f7a10014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30331
42805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3033142805
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.393411576
Short name T1508
Test name
Test status
Simulation time 235375799 ps
CPU time 0.9 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:56 PM PDT 24
Peak memory 206676 kb
Host smart-c4fee10a-2751-41ee-9adf-190f93734977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39341
1576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.393411576
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2955406328
Short name T644
Test name
Test status
Simulation time 148214368 ps
CPU time 0.77 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:05 PM PDT 24
Peak memory 206792 kb
Host smart-46cf86cf-5d3a-443f-b0ad-3c320a6c12fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29554
06328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2955406328
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1551532524
Short name T1459
Test name
Test status
Simulation time 206116002 ps
CPU time 0.83 seconds
Started Jul 12 05:33:06 PM PDT 24
Finished Jul 12 05:33:11 PM PDT 24
Peak memory 206676 kb
Host smart-f9199969-b0ae-4735-a40f-3a000f21ed4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15515
32524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1551532524
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.2220900589
Short name T1057
Test name
Test status
Simulation time 11948059283 ps
CPU time 42.06 seconds
Started Jul 12 05:33:05 PM PDT 24
Finished Jul 12 05:33:52 PM PDT 24
Peak memory 207044 kb
Host smart-3f1d8626-c077-4a4c-8e66-1a63b071f66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22209
00589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.2220900589
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1576755835
Short name T646
Test name
Test status
Simulation time 217050033 ps
CPU time 0.93 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206640 kb
Host smart-1c2808a6-c9da-4b53-a0e9-d5cfee31b1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15767
55835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1576755835
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.176883782
Short name T488
Test name
Test status
Simulation time 23297855870 ps
CPU time 25.48 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:31 PM PDT 24
Peak memory 206776 kb
Host smart-780081f6-1c75-406e-8b76-fc995e78069d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17688
3782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.176883782
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3906916490
Short name T362
Test name
Test status
Simulation time 3298083594 ps
CPU time 3.58 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206900 kb
Host smart-1a03846c-6814-4a1a-9d9a-65d7b9373ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39069
16490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3906916490
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3333641045
Short name T1436
Test name
Test status
Simulation time 4862515865 ps
CPU time 33.53 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:38 PM PDT 24
Peak memory 207012 kb
Host smart-695b2bfb-e3e1-42bf-8b43-2b66eed7d787
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3333641045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3333641045
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.4113424724
Short name T1924
Test name
Test status
Simulation time 259631658 ps
CPU time 1.05 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:00 PM PDT 24
Peak memory 206808 kb
Host smart-78efc05c-284b-482f-b1f6-7f2618d72c15
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4113424724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.4113424724
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3040063
Short name T1878
Test name
Test status
Simulation time 192824710 ps
CPU time 0.87 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206812 kb
Host smart-1a773c10-4fe7-4fc8-845a-32e50afe668e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30400
63 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3040063
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.2382620018
Short name T1419
Test name
Test status
Simulation time 5160260185 ps
CPU time 36 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:40 PM PDT 24
Peak memory 207236 kb
Host smart-dfd89788-fc9c-4137-a15f-1e50c3a453ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23826
20018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.2382620018
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.2408035445
Short name T2547
Test name
Test status
Simulation time 3113212926 ps
CPU time 30.38 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:37 PM PDT 24
Peak memory 206912 kb
Host smart-ad1d6892-78a2-4788-b46b-c3e09bb8d7a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2408035445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.2408035445
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2364347784
Short name T2445
Test name
Test status
Simulation time 170859242 ps
CPU time 0.81 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:03 PM PDT 24
Peak memory 206696 kb
Host smart-25fdcc3c-bf84-4067-92af-b1ab19be6225
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2364347784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2364347784
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3003667043
Short name T487
Test name
Test status
Simulation time 146883287 ps
CPU time 0.87 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:05 PM PDT 24
Peak memory 206824 kb
Host smart-f9df7761-1ec6-494f-adbc-ac0727c34397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
67043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3003667043
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.945420279
Short name T1130
Test name
Test status
Simulation time 218060857 ps
CPU time 1 seconds
Started Jul 12 05:32:48 PM PDT 24
Finished Jul 12 05:32:50 PM PDT 24
Peak memory 206816 kb
Host smart-955618e6-f499-4321-a60d-bf57179a463a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94542
0279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.945420279
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2767076656
Short name T1726
Test name
Test status
Simulation time 169232507 ps
CPU time 0.76 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:32:59 PM PDT 24
Peak memory 206808 kb
Host smart-a6c5a300-e81b-4e67-a353-460251d9ca90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27670
76656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2767076656
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3200683151
Short name T460
Test name
Test status
Simulation time 223103565 ps
CPU time 0.91 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206816 kb
Host smart-cd77d078-75dd-47a6-a8bd-8b2da6d89af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32006
83151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3200683151
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3266812596
Short name T2062
Test name
Test status
Simulation time 199772504 ps
CPU time 0.85 seconds
Started Jul 12 05:32:52 PM PDT 24
Finished Jul 12 05:32:55 PM PDT 24
Peak memory 206796 kb
Host smart-fc30ca7d-1fbe-4075-824f-023fc650d2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32668
12596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3266812596
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1219019411
Short name T2592
Test name
Test status
Simulation time 147043888 ps
CPU time 0.77 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:32:59 PM PDT 24
Peak memory 206720 kb
Host smart-807aa469-d16c-421d-9448-4b66053d8e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12190
19411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1219019411
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.169950054
Short name T2370
Test name
Test status
Simulation time 227117772 ps
CPU time 0.98 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206820 kb
Host smart-5cca5fcc-1b37-4c76-9fbf-74430a21bd7e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=169950054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.169950054
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1202046967
Short name T1840
Test name
Test status
Simulation time 149951705 ps
CPU time 0.74 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:15 PM PDT 24
Peak memory 206676 kb
Host smart-32fad87f-bd58-40f6-973b-b76c437411ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12020
46967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1202046967
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2985830523
Short name T1732
Test name
Test status
Simulation time 38606012 ps
CPU time 0.65 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:05 PM PDT 24
Peak memory 206668 kb
Host smart-b54556e8-7a09-403e-87ad-7ab5a7aafe97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29858
30523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2985830523
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.4022220739
Short name T2218
Test name
Test status
Simulation time 12099405279 ps
CPU time 27.04 seconds
Started Jul 12 05:33:18 PM PDT 24
Finished Jul 12 05:33:46 PM PDT 24
Peak memory 207084 kb
Host smart-6ce71270-5e02-4d13-820d-e3b9567e0ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40222
20739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.4022220739
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.430477215
Short name T833
Test name
Test status
Simulation time 194705094 ps
CPU time 0.82 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:32:59 PM PDT 24
Peak memory 206816 kb
Host smart-3942f7d5-98e5-4f9c-93ee-1355bfa85cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43047
7215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.430477215
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.609529712
Short name T1651
Test name
Test status
Simulation time 173564418 ps
CPU time 0.8 seconds
Started Jul 12 05:32:53 PM PDT 24
Finished Jul 12 05:32:58 PM PDT 24
Peak memory 206804 kb
Host smart-8c352d1e-bb01-4a7f-9879-81d65e6cc679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60952
9712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.609529712
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.739292055
Short name T1695
Test name
Test status
Simulation time 230661900 ps
CPU time 0.9 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 206868 kb
Host smart-d40a0bd9-e77d-4d8f-af33-feef2f7704b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73929
2055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.739292055
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.447786762
Short name T1045
Test name
Test status
Simulation time 176262642 ps
CPU time 0.84 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206772 kb
Host smart-d5ed5a54-e4e9-47f5-932f-4bf05c0ea445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44778
6762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.447786762
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.829963696
Short name T590
Test name
Test status
Simulation time 135550076 ps
CPU time 0.8 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:12 PM PDT 24
Peak memory 206700 kb
Host smart-0de66660-aab1-4b35-93fe-b9e00e8210b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82996
3696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.829963696
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.724692036
Short name T1320
Test name
Test status
Simulation time 146455502 ps
CPU time 0.81 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:04 PM PDT 24
Peak memory 206804 kb
Host smart-4e88a673-7cc5-426c-8a88-cbe731596670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72469
2036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.724692036
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3762043851
Short name T1152
Test name
Test status
Simulation time 163397767 ps
CPU time 0.76 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206820 kb
Host smart-ae885655-0d0a-4544-add6-27654d345b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37620
43851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3762043851
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1574578192
Short name T1727
Test name
Test status
Simulation time 223271393 ps
CPU time 0.91 seconds
Started Jul 12 05:33:32 PM PDT 24
Finished Jul 12 05:33:35 PM PDT 24
Peak memory 206696 kb
Host smart-8ac00fef-8ebc-4cf8-99ab-b947b3701730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15745
78192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1574578192
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.694628255
Short name T1908
Test name
Test status
Simulation time 5345738004 ps
CPU time 37.72 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 207088 kb
Host smart-73437b32-d010-4406-802c-2d9c7e4dedb3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=694628255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.694628255
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2170314857
Short name T1141
Test name
Test status
Simulation time 164517870 ps
CPU time 0.75 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206720 kb
Host smart-60b93a4d-3639-4191-9e60-f5e3e209ea79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21703
14857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2170314857
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3653292460
Short name T2454
Test name
Test status
Simulation time 257903932 ps
CPU time 0.88 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:04 PM PDT 24
Peak memory 206816 kb
Host smart-4ceed8e1-538f-455d-8c52-d0b3286ad0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36532
92460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3653292460
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2647390286
Short name T2481
Test name
Test status
Simulation time 942825198 ps
CPU time 2.04 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:33:15 PM PDT 24
Peak memory 207156 kb
Host smart-12ada6d2-58ae-4516-a8e3-e0430a35631c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26473
90286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2647390286
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.4078212365
Short name T1460
Test name
Test status
Simulation time 4606577206 ps
CPU time 31.81 seconds
Started Jul 12 05:33:04 PM PDT 24
Finished Jul 12 05:33:41 PM PDT 24
Peak memory 207084 kb
Host smart-7add9bc0-2c08-4cdf-90e2-6922a62be767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40782
12365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.4078212365
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.2228488279
Short name T1276
Test name
Test status
Simulation time 53386882 ps
CPU time 0.7 seconds
Started Jul 12 05:33:21 PM PDT 24
Finished Jul 12 05:33:23 PM PDT 24
Peak memory 206848 kb
Host smart-fcd99f3b-2b23-4cb1-8e83-9e299b991807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2228488279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2228488279
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.4207733445
Short name T2000
Test name
Test status
Simulation time 4378525079 ps
CPU time 5.35 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206900 kb
Host smart-3b988165-82b5-49af-ba0f-270d1f88d1ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4207733445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.4207733445
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1368876714
Short name T2718
Test name
Test status
Simulation time 13342727885 ps
CPU time 12.48 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206888 kb
Host smart-eccb7ecc-ac07-4721-9a58-1ffef2233a49
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1368876714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1368876714
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.242497732
Short name T1311
Test name
Test status
Simulation time 23350171767 ps
CPU time 30.24 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:41 PM PDT 24
Peak memory 206876 kb
Host smart-bed3f518-a49e-415e-988c-e5a43f7578b2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=242497732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.242497732
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1564904239
Short name T2285
Test name
Test status
Simulation time 168188537 ps
CPU time 0.79 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206820 kb
Host smart-19c22d23-ec36-4457-b4de-5ec38b805f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15649
04239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1564904239
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.286483862
Short name T1097
Test name
Test status
Simulation time 221212749 ps
CPU time 0.88 seconds
Started Jul 12 05:33:01 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 206716 kb
Host smart-d3532819-b4e8-41c8-ac78-9daaed7854ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28648
3862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.286483862
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.1796093216
Short name T890
Test name
Test status
Simulation time 509567346 ps
CPU time 1.54 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206864 kb
Host smart-29b50182-e536-4d4e-be5c-e9bb1b8a2f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17960
93216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.1796093216
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2193456532
Short name T1781
Test name
Test status
Simulation time 695645195 ps
CPU time 1.71 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:14 PM PDT 24
Peak memory 206952 kb
Host smart-01181567-e843-4633-bf25-23d6dfabd1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21934
56532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2193456532
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3412208197
Short name T953
Test name
Test status
Simulation time 18365570971 ps
CPU time 30.47 seconds
Started Jul 12 05:33:22 PM PDT 24
Finished Jul 12 05:33:54 PM PDT 24
Peak memory 207136 kb
Host smart-c89987cf-0c20-411c-90a2-4e30ae03b4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34122
08197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3412208197
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.417978043
Short name T2392
Test name
Test status
Simulation time 477945262 ps
CPU time 1.39 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206768 kb
Host smart-8895a978-cd5e-4f61-802b-d4c574c8e53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41797
8043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.417978043
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.897407084
Short name T2747
Test name
Test status
Simulation time 145759927 ps
CPU time 0.74 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206824 kb
Host smart-75b2c0f1-eafa-4fa2-93cd-f356f4575592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89740
7084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.897407084
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1697576911
Short name T794
Test name
Test status
Simulation time 75629360 ps
CPU time 0.71 seconds
Started Jul 12 05:33:20 PM PDT 24
Finished Jul 12 05:33:21 PM PDT 24
Peak memory 206804 kb
Host smart-409f218f-3220-4a96-ab0c-412627e6d9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
76911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1697576911
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1416423048
Short name T1839
Test name
Test status
Simulation time 852532065 ps
CPU time 2.08 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:01 PM PDT 24
Peak memory 206844 kb
Host smart-9c959fda-328c-4103-b5ea-821164fcb1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14164
23048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1416423048
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.29214206
Short name T222
Test name
Test status
Simulation time 310707413 ps
CPU time 2.25 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:33:01 PM PDT 24
Peak memory 207012 kb
Host smart-30763aa3-1036-4e23-8b9f-1eacea2b4673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29214
206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.29214206
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.829597947
Short name T1260
Test name
Test status
Simulation time 174834144 ps
CPU time 0.79 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206760 kb
Host smart-bcfff1cb-5c9b-461f-9ed6-dbaab073bc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82959
7947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.829597947
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2776052428
Short name T2491
Test name
Test status
Simulation time 143990836 ps
CPU time 0.77 seconds
Started Jul 12 05:33:04 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206808 kb
Host smart-d911bb48-9450-4458-a119-43baa31d9bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27760
52428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2776052428
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.266421627
Short name T2108
Test name
Test status
Simulation time 212034208 ps
CPU time 0.94 seconds
Started Jul 12 05:33:05 PM PDT 24
Finished Jul 12 05:33:11 PM PDT 24
Peak memory 206812 kb
Host smart-cb44021f-b702-49d8-b95b-7a16eef6db22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26642
1627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.266421627
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.765739424
Short name T1495
Test name
Test status
Simulation time 214864369 ps
CPU time 0.87 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 206812 kb
Host smart-9f316fbc-176f-4b5a-b31d-fb0bcead819c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76573
9424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.765739424
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.211787110
Short name T1685
Test name
Test status
Simulation time 23322962449 ps
CPU time 24.14 seconds
Started Jul 12 05:33:01 PM PDT 24
Finished Jul 12 05:33:31 PM PDT 24
Peak memory 206740 kb
Host smart-b2eff75e-7386-4876-ad2d-ed45ee451a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21178
7110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.211787110
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.1614810322
Short name T777
Test name
Test status
Simulation time 3340925192 ps
CPU time 4.31 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:08 PM PDT 24
Peak memory 206764 kb
Host smart-4dc30d9c-3954-4a3d-b9b4-d1b4e4e473ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16148
10322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.1614810322
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1421653202
Short name T337
Test name
Test status
Simulation time 10119859412 ps
CPU time 72.92 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:34:19 PM PDT 24
Peak memory 207080 kb
Host smart-59bc0dbb-8e0b-449e-8fe2-5a89356e98af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14216
53202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1421653202
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1867651142
Short name T2421
Test name
Test status
Simulation time 5034839771 ps
CPU time 43.78 seconds
Started Jul 12 05:32:57 PM PDT 24
Finished Jul 12 05:33:46 PM PDT 24
Peak memory 206832 kb
Host smart-f8cc1c03-08b1-4584-a5fe-f599c06871cd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1867651142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1867651142
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3151915159
Short name T370
Test name
Test status
Simulation time 257606472 ps
CPU time 0.99 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 206672 kb
Host smart-246aed21-9516-4fe1-b505-0206f75e76be
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3151915159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3151915159
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3679156834
Short name T316
Test name
Test status
Simulation time 219116462 ps
CPU time 0.94 seconds
Started Jul 12 05:33:03 PM PDT 24
Finished Jul 12 05:33:09 PM PDT 24
Peak memory 206832 kb
Host smart-1cea0aa7-9449-46c7-a3ea-f267433598e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36791
56834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3679156834
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.1396777229
Short name T2039
Test name
Test status
Simulation time 3288497080 ps
CPU time 29.44 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:34 PM PDT 24
Peak memory 207092 kb
Host smart-b893bf11-e2dc-4e8c-b895-c39d8c3bab60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13967
77229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.1396777229
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3038215784
Short name T1272
Test name
Test status
Simulation time 3035552971 ps
CPU time 21.04 seconds
Started Jul 12 05:32:56 PM PDT 24
Finished Jul 12 05:33:21 PM PDT 24
Peak memory 206892 kb
Host smart-c695db39-ceb1-4520-91d6-27b142fde6b9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3038215784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3038215784
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.2166384204
Short name T1075
Test name
Test status
Simulation time 185173499 ps
CPU time 0.82 seconds
Started Jul 12 05:33:22 PM PDT 24
Finished Jul 12 05:33:24 PM PDT 24
Peak memory 206936 kb
Host smart-fa391072-39d2-4bb7-8ce1-4898a8464ad7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2166384204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2166384204
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2776653358
Short name T1797
Test name
Test status
Simulation time 169196637 ps
CPU time 0.77 seconds
Started Jul 12 05:33:01 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 206636 kb
Host smart-f49d40cc-75b2-4257-832a-2106b013f343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27766
53358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2776653358
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3391540966
Short name T2746
Test name
Test status
Simulation time 230526132 ps
CPU time 0.88 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206804 kb
Host smart-c381bf33-8e00-47b6-aa0e-5aad46ed61f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915
40966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3391540966
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.702570849
Short name T2522
Test name
Test status
Simulation time 181514370 ps
CPU time 0.86 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206692 kb
Host smart-cf33240b-a854-47a3-84b8-424ceb848f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70257
0849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.702570849
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.4262362633
Short name T1041
Test name
Test status
Simulation time 208125888 ps
CPU time 0.81 seconds
Started Jul 12 05:32:56 PM PDT 24
Finished Jul 12 05:33:02 PM PDT 24
Peak memory 206808 kb
Host smart-8f6a9ddc-ce2a-42e7-a1b4-d80c7b7f8de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42623
62633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.4262362633
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1598319085
Short name T2291
Test name
Test status
Simulation time 165830676 ps
CPU time 0.77 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206836 kb
Host smart-2812764f-141b-4389-ac1f-1edb9b3025b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15983
19085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1598319085
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2579068465
Short name T1225
Test name
Test status
Simulation time 152017614 ps
CPU time 0.78 seconds
Started Jul 12 05:33:17 PM PDT 24
Finished Jul 12 05:33:18 PM PDT 24
Peak memory 206924 kb
Host smart-1d3e593f-61c8-4f98-ae92-18a4fdb956fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25790
68465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2579068465
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3537141608
Short name T2389
Test name
Test status
Simulation time 210550259 ps
CPU time 0.94 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:33:14 PM PDT 24
Peak memory 206812 kb
Host smart-d0a43542-b184-4a5c-aa41-532b18aadab5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3537141608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3537141608
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3028850095
Short name T2539
Test name
Test status
Simulation time 138579844 ps
CPU time 0.75 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206808 kb
Host smart-ffe9fec2-b5a0-4ff2-809c-588f73cfa7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30288
50095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3028850095
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2338988118
Short name T1373
Test name
Test status
Simulation time 33956535 ps
CPU time 0.65 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:12 PM PDT 24
Peak memory 206828 kb
Host smart-1fa93a50-cc43-4bd8-b032-84b12c40339b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23389
88118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2338988118
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.272219311
Short name T1939
Test name
Test status
Simulation time 17123628570 ps
CPU time 36.8 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:53 PM PDT 24
Peak memory 207052 kb
Host smart-21fe1af8-e2dd-4d02-b615-162c3cbc900a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27221
9311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.272219311
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2111831550
Short name T292
Test name
Test status
Simulation time 173257556 ps
CPU time 0.88 seconds
Started Jul 12 05:32:55 PM PDT 24
Finished Jul 12 05:33:01 PM PDT 24
Peak memory 206808 kb
Host smart-344fe871-fdfa-4408-9d8e-dd59879bbf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21118
31550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2111831550
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3087332791
Short name T1277
Test name
Test status
Simulation time 224914791 ps
CPU time 0.88 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206800 kb
Host smart-f3eb86e8-861f-4be7-a448-957e8a041cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
32791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3087332791
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.4171106294
Short name T1518
Test name
Test status
Simulation time 166697322 ps
CPU time 0.86 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:14 PM PDT 24
Peak memory 206812 kb
Host smart-3ba7a977-aa2e-4742-b4c8-d9228fa0dc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711
06294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.4171106294
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.1129617849
Short name T676
Test name
Test status
Simulation time 185218660 ps
CPU time 0.86 seconds
Started Jul 12 05:32:59 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 206704 kb
Host smart-fc383b2f-efe3-4e58-b9de-5af32ff05a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296
17849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.1129617849
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.469178455
Short name T88
Test name
Test status
Simulation time 145590207 ps
CPU time 0.81 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 206800 kb
Host smart-f45743d6-567c-49d0-bcb0-55040bf8bddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46917
8455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.469178455
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.4039564908
Short name T2735
Test name
Test status
Simulation time 155030100 ps
CPU time 0.74 seconds
Started Jul 12 05:32:54 PM PDT 24
Finished Jul 12 05:32:58 PM PDT 24
Peak memory 206696 kb
Host smart-176e997a-3eaf-438e-85a9-3cea364f57d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40395
64908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.4039564908
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3831897922
Short name T2090
Test name
Test status
Simulation time 151999007 ps
CPU time 0.79 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206808 kb
Host smart-bfb4f15d-ad85-4535-9a5f-df1b7b3f5876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38318
97922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3831897922
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1742346056
Short name T1335
Test name
Test status
Simulation time 212488829 ps
CPU time 0.9 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206824 kb
Host smart-cfc708bc-34ff-4db8-abfd-5a2afce6dff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17423
46056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1742346056
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.2478289586
Short name T1094
Test name
Test status
Simulation time 6093873554 ps
CPU time 158.7 seconds
Started Jul 12 05:33:10 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 207008 kb
Host smart-25cd68e8-c596-4b93-b6c0-61ee977c9c67
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2478289586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.2478289586
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2533419308
Short name T806
Test name
Test status
Simulation time 223285331 ps
CPU time 0.88 seconds
Started Jul 12 05:33:10 PM PDT 24
Finished Jul 12 05:33:15 PM PDT 24
Peak memory 206832 kb
Host smart-2d7a68b6-dacb-4872-8821-16419e58ce81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
19308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2533419308
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2844235997
Short name T1633
Test name
Test status
Simulation time 173402629 ps
CPU time 0.84 seconds
Started Jul 12 05:33:02 PM PDT 24
Finished Jul 12 05:33:09 PM PDT 24
Peak memory 206976 kb
Host smart-477bfa92-17b3-48f6-9dd8-180df6cb8135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28442
35997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2844235997
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.570592091
Short name T357
Test name
Test status
Simulation time 1090983174 ps
CPU time 2.3 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 207028 kb
Host smart-3fb19ed2-c564-4abf-8df4-660af1542c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57059
2091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.570592091
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3496353413
Short name T1407
Test name
Test status
Simulation time 4742288390 ps
CPU time 33.1 seconds
Started Jul 12 05:33:02 PM PDT 24
Finished Jul 12 05:33:40 PM PDT 24
Peak memory 207084 kb
Host smart-a5b55957-bb42-45fc-96d0-7a176b076582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
53413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3496353413
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.2215339015
Short name T811
Test name
Test status
Simulation time 43615817 ps
CPU time 0.67 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:14 PM PDT 24
Peak memory 206852 kb
Host smart-f3c1bd1f-04a1-4b21-bac7-7bc71e1c9a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2215339015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.2215339015
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.138926636
Short name T550
Test name
Test status
Simulation time 3713716664 ps
CPU time 4.14 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 207012 kb
Host smart-ba896d56-697a-4353-bb72-44425b92559b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=138926636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.138926636
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.633266333
Short name T427
Test name
Test status
Simulation time 13365204741 ps
CPU time 12.83 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206740 kb
Host smart-bc971da4-e7c7-4601-9852-e97e22a2465e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=633266333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.633266333
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.698749959
Short name T457
Test name
Test status
Simulation time 23380878928 ps
CPU time 22.32 seconds
Started Jul 12 05:33:06 PM PDT 24
Finished Jul 12 05:33:33 PM PDT 24
Peak memory 206932 kb
Host smart-ca2a60e3-7ec5-44db-9563-b73cf120b11a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=698749959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.698749959
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1183527580
Short name T783
Test name
Test status
Simulation time 184740821 ps
CPU time 0.85 seconds
Started Jul 12 05:33:03 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206808 kb
Host smart-b7818921-4a35-4263-b269-489d33f28ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11835
27580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1183527580
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3465994005
Short name T1650
Test name
Test status
Simulation time 145447606 ps
CPU time 0.78 seconds
Started Jul 12 05:33:00 PM PDT 24
Finished Jul 12 05:33:07 PM PDT 24
Peak memory 206672 kb
Host smart-14162e13-d7c4-4d93-a01b-65f01a3d9473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34659
94005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3465994005
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3374966987
Short name T2607
Test name
Test status
Simulation time 606306014 ps
CPU time 1.76 seconds
Started Jul 12 05:32:58 PM PDT 24
Finished Jul 12 05:33:06 PM PDT 24
Peak memory 207224 kb
Host smart-eb20a6c5-91a9-4e62-851d-b8d332265dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33749
66987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3374966987
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3904919768
Short name T2340
Test name
Test status
Simulation time 696788556 ps
CPU time 1.8 seconds
Started Jul 12 05:33:03 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 207020 kb
Host smart-c9a3bd3a-ebbc-479f-bb6f-fc5f8bf3d654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39049
19768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3904919768
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3656580906
Short name T958
Test name
Test status
Simulation time 20322604930 ps
CPU time 37.94 seconds
Started Jul 12 05:33:01 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 207076 kb
Host smart-c9bc743b-e7be-46f4-8f21-d369f1d78ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36565
80906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3656580906
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.675671598
Short name T1476
Test name
Test status
Simulation time 498361058 ps
CPU time 1.43 seconds
Started Jul 12 05:33:25 PM PDT 24
Finished Jul 12 05:33:27 PM PDT 24
Peak memory 206828 kb
Host smart-2f01898e-fee9-49b1-8e90-d0d2778ee245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67567
1598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.675671598
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3611180403
Short name T982
Test name
Test status
Simulation time 138820236 ps
CPU time 0.77 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:15 PM PDT 24
Peak memory 206812 kb
Host smart-a49f5405-6b84-4a5f-876b-e9e819be21eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36111
80403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3611180403
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3341829745
Short name T827
Test name
Test status
Simulation time 33624834 ps
CPU time 0.7 seconds
Started Jul 12 05:33:13 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206796 kb
Host smart-c4496caa-a25b-4417-a609-b64ec300b06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33418
29745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3341829745
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.204678595
Short name T2245
Test name
Test status
Simulation time 934664527 ps
CPU time 2 seconds
Started Jul 12 05:33:11 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206968 kb
Host smart-5f7f97d7-8cc9-4b20-a351-bba7d61ee5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467
8595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.204678595
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1735955586
Short name T2490
Test name
Test status
Simulation time 384250957 ps
CPU time 2.31 seconds
Started Jul 12 05:33:12 PM PDT 24
Finished Jul 12 05:33:19 PM PDT 24
Peak memory 207020 kb
Host smart-c56496d7-7ea2-4b06-a276-1ec7ed9581d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17359
55586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1735955586
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1024959578
Short name T1808
Test name
Test status
Simulation time 206644855 ps
CPU time 0.86 seconds
Started Jul 12 05:33:19 PM PDT 24
Finished Jul 12 05:33:21 PM PDT 24
Peak memory 206792 kb
Host smart-1e605899-c96c-4efa-98fa-6c24281e874c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10249
59578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1024959578
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3564241013
Short name T2065
Test name
Test status
Simulation time 166299755 ps
CPU time 0.75 seconds
Started Jul 12 05:33:17 PM PDT 24
Finished Jul 12 05:33:19 PM PDT 24
Peak memory 206712 kb
Host smart-ead1350f-2364-4feb-abfa-f43e959e6f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35642
41013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3564241013
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.596559786
Short name T2097
Test name
Test status
Simulation time 184190859 ps
CPU time 0.83 seconds
Started Jul 12 05:33:02 PM PDT 24
Finished Jul 12 05:33:08 PM PDT 24
Peak memory 206816 kb
Host smart-99be151f-0081-4333-bd87-d40a74de76e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59655
9786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.596559786
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.799666864
Short name T2083
Test name
Test status
Simulation time 4435798611 ps
CPU time 14.05 seconds
Started Jul 12 05:33:29 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 207028 kb
Host smart-d82321d7-3442-4d28-87b4-88da76909748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79966
6864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.799666864
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3110883038
Short name T1872
Test name
Test status
Simulation time 170891283 ps
CPU time 0.83 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:33:14 PM PDT 24
Peak memory 206816 kb
Host smart-df2e3e83-e11f-42da-bac9-4a2c4e2a6b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31108
83038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3110883038
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2785023780
Short name T1639
Test name
Test status
Simulation time 23284087902 ps
CPU time 23.2 seconds
Started Jul 12 05:33:29 PM PDT 24
Finished Jul 12 05:33:54 PM PDT 24
Peak memory 206872 kb
Host smart-900d6f0b-ebb9-4cb4-a1fe-2c89a1681e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27850
23780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2785023780
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1683273347
Short name T1410
Test name
Test status
Simulation time 3257242418 ps
CPU time 3.47 seconds
Started Jul 12 05:33:19 PM PDT 24
Finished Jul 12 05:33:24 PM PDT 24
Peak memory 206780 kb
Host smart-455c76f9-6074-4ff8-9124-2626483d06c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
73347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1683273347
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.928602176
Short name T2395
Test name
Test status
Simulation time 9424832734 ps
CPU time 67.89 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:34:22 PM PDT 24
Peak memory 207088 kb
Host smart-f438621f-a6eb-4f11-8f2d-36c8bf8c64a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92860
2176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.928602176
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3075721851
Short name T1763
Test name
Test status
Simulation time 2974930654 ps
CPU time 78.55 seconds
Started Jul 12 05:33:21 PM PDT 24
Finished Jul 12 05:34:40 PM PDT 24
Peak memory 206888 kb
Host smart-aaf4a989-ebdc-4035-8829-0008f4d05a1d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3075721851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3075721851
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1646644457
Short name T368
Test name
Test status
Simulation time 242031000 ps
CPU time 0.96 seconds
Started Jul 12 05:33:12 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206828 kb
Host smart-681061bb-dda6-4453-a112-50c6e3b60117
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1646644457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1646644457
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2563657678
Short name T1596
Test name
Test status
Simulation time 187970400 ps
CPU time 0.86 seconds
Started Jul 12 05:33:13 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206832 kb
Host smart-8e7ee941-2fc4-4b09-adf2-1fb737b7ac7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25636
57678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2563657678
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2797689178
Short name T936
Test name
Test status
Simulation time 5868240116 ps
CPU time 42.67 seconds
Started Jul 12 05:33:11 PM PDT 24
Finished Jul 12 05:33:58 PM PDT 24
Peak memory 207108 kb
Host smart-82b86ba3-868e-4b48-b0e2-f05a76a0f0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27976
89178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2797689178
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.854350377
Short name T332
Test name
Test status
Simulation time 7437182073 ps
CPU time 50.72 seconds
Started Jul 12 05:33:19 PM PDT 24
Finished Jul 12 05:34:16 PM PDT 24
Peak memory 207064 kb
Host smart-64859da5-debb-4c44-a5b4-9294143d6c7e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=854350377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.854350377
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.549264613
Short name T1381
Test name
Test status
Simulation time 169865489 ps
CPU time 0.86 seconds
Started Jul 12 05:33:30 PM PDT 24
Finished Jul 12 05:33:32 PM PDT 24
Peak memory 206676 kb
Host smart-a4b69be5-ebf5-4e17-b1f8-a98b7518217f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=549264613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.549264613
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1548958445
Short name T1372
Test name
Test status
Simulation time 142431840 ps
CPU time 0.8 seconds
Started Jul 12 05:33:23 PM PDT 24
Finished Jul 12 05:33:26 PM PDT 24
Peak memory 206812 kb
Host smart-03ef774b-8900-4f67-b027-acb76ada482f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15489
58445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1548958445
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.24609446
Short name T125
Test name
Test status
Simulation time 217676952 ps
CPU time 0.87 seconds
Started Jul 12 05:33:11 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 206804 kb
Host smart-2c89b62d-61e5-4d1b-ad51-2ff36cb5dd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24609
446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.24609446
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1090668116
Short name T2080
Test name
Test status
Simulation time 242544514 ps
CPU time 0.9 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:18 PM PDT 24
Peak memory 206716 kb
Host smart-8484b952-76c3-4dc4-929b-af87e4e8158c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10906
68116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1090668116
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1851707269
Short name T2655
Test name
Test status
Simulation time 209713230 ps
CPU time 0.86 seconds
Started Jul 12 05:33:19 PM PDT 24
Finished Jul 12 05:33:20 PM PDT 24
Peak memory 206676 kb
Host smart-99ed2985-0345-4f78-bd2a-d98165a079f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18517
07269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1851707269
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3809032461
Short name T206
Test name
Test status
Simulation time 192114028 ps
CPU time 0.8 seconds
Started Jul 12 05:33:29 PM PDT 24
Finished Jul 12 05:33:31 PM PDT 24
Peak memory 206796 kb
Host smart-df62241f-77a7-4f96-bfc6-7643afddcef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38090
32461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3809032461
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3544920346
Short name T178
Test name
Test status
Simulation time 172270555 ps
CPU time 0.8 seconds
Started Jul 12 05:33:10 PM PDT 24
Finished Jul 12 05:33:15 PM PDT 24
Peak memory 206800 kb
Host smart-6b021fad-92d7-46a6-bead-7380f4bf3b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35449
20346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3544920346
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.781667006
Short name T784
Test name
Test status
Simulation time 230078865 ps
CPU time 0.95 seconds
Started Jul 12 05:33:02 PM PDT 24
Finished Jul 12 05:33:09 PM PDT 24
Peak memory 206824 kb
Host smart-fcb20ba3-295a-4233-95e6-c49347e86c2b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=781667006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.781667006
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.796554159
Short name T1251
Test name
Test status
Simulation time 135997976 ps
CPU time 0.74 seconds
Started Jul 12 05:33:14 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206716 kb
Host smart-0e5b1768-62a0-4843-81e1-a380aa8b6be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79655
4159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.796554159
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3598061293
Short name T901
Test name
Test status
Simulation time 51357415 ps
CPU time 0.66 seconds
Started Jul 12 05:33:10 PM PDT 24
Finished Jul 12 05:33:15 PM PDT 24
Peak memory 206696 kb
Host smart-5bcf0d1a-34f3-48ad-b790-f5d2261b3dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35980
61293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3598061293
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2179633438
Short name T252
Test name
Test status
Simulation time 7483922989 ps
CPU time 18.75 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:32 PM PDT 24
Peak memory 207116 kb
Host smart-72521bbf-0c59-4eed-b777-b670fa2c693b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21796
33438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2179633438
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2121605589
Short name T975
Test name
Test status
Simulation time 171075514 ps
CPU time 0.78 seconds
Started Jul 12 05:33:26 PM PDT 24
Finished Jul 12 05:33:28 PM PDT 24
Peak memory 206820 kb
Host smart-ba6dad0f-7899-4e41-9aa4-44b3c4376d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21216
05589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2121605589
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1166988464
Short name T992
Test name
Test status
Simulation time 199635915 ps
CPU time 0.9 seconds
Started Jul 12 05:33:12 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206808 kb
Host smart-e38100db-da43-49bb-8133-10f67fc2accd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11669
88464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1166988464
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3197630051
Short name T2214
Test name
Test status
Simulation time 285881209 ps
CPU time 1.01 seconds
Started Jul 12 05:33:27 PM PDT 24
Finished Jul 12 05:33:30 PM PDT 24
Peak memory 206768 kb
Host smart-d5e2043c-74ec-4c25-9c37-ecc5f8c62a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31976
30051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3197630051
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3643904705
Short name T1788
Test name
Test status
Simulation time 167786439 ps
CPU time 0.79 seconds
Started Jul 12 05:38:31 PM PDT 24
Finished Jul 12 05:38:42 PM PDT 24
Peak memory 206808 kb
Host smart-a6cdf388-1c86-43ee-8a99-dbebf81aba1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36439
04705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3643904705
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.40927546
Short name T1687
Test name
Test status
Simulation time 225679774 ps
CPU time 0.83 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:15 PM PDT 24
Peak memory 206804 kb
Host smart-a7917d96-e557-4795-8210-bb79bac5a63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40927
546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.40927546
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.985860638
Short name T1549
Test name
Test status
Simulation time 166461493 ps
CPU time 0.79 seconds
Started Jul 12 05:33:20 PM PDT 24
Finished Jul 12 05:33:22 PM PDT 24
Peak memory 206692 kb
Host smart-d42eddd9-2619-43de-8911-fe03b6f77d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98586
0638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.985860638
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2415766490
Short name T94
Test name
Test status
Simulation time 152877918 ps
CPU time 0.78 seconds
Started Jul 12 05:33:22 PM PDT 24
Finished Jul 12 05:33:24 PM PDT 24
Peak memory 206820 kb
Host smart-1ebb8891-05c7-41c3-bc47-28652bfad47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24157
66490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2415766490
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1086168978
Short name T1484
Test name
Test status
Simulation time 222984990 ps
CPU time 0.89 seconds
Started Jul 12 05:33:04 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206812 kb
Host smart-c8916ca8-feb9-4232-8362-3e05aa17c073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
68978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1086168978
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.440151540
Short name T1458
Test name
Test status
Simulation time 5876583234 ps
CPU time 55.34 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:34:09 PM PDT 24
Peak memory 207104 kb
Host smart-a6e5f2e3-47f9-47ee-a21f-5a60ee05d03c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=440151540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.440151540
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2082729545
Short name T1969
Test name
Test status
Simulation time 216698748 ps
CPU time 0.94 seconds
Started Jul 12 05:33:27 PM PDT 24
Finished Jul 12 05:33:30 PM PDT 24
Peak memory 206820 kb
Host smart-bc4fbb21-378a-400a-b4a6-0d91bdeccff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20827
29545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2082729545
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1496678392
Short name T2314
Test name
Test status
Simulation time 171672797 ps
CPU time 0.86 seconds
Started Jul 12 05:33:23 PM PDT 24
Finished Jul 12 05:33:26 PM PDT 24
Peak memory 206808 kb
Host smart-2e882212-df2b-4c36-a240-e248f802da76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966
78392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1496678392
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2989434559
Short name T744
Test name
Test status
Simulation time 286349915 ps
CPU time 0.97 seconds
Started Jul 12 05:33:25 PM PDT 24
Finished Jul 12 05:33:27 PM PDT 24
Peak memory 206772 kb
Host smart-2cb50fd9-4af2-4f43-9236-accd49580d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29894
34559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2989434559
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.286188289
Short name T2386
Test name
Test status
Simulation time 3034015683 ps
CPU time 21.87 seconds
Started Jul 12 05:33:15 PM PDT 24
Finished Jul 12 05:33:39 PM PDT 24
Peak memory 207052 kb
Host smart-91f04a24-0156-4ac4-8d8a-cb5e42eedfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
8289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.286188289
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.4002513024
Short name T2521
Test name
Test status
Simulation time 55580571 ps
CPU time 0.74 seconds
Started Jul 12 05:33:44 PM PDT 24
Finished Jul 12 05:33:50 PM PDT 24
Peak memory 206816 kb
Host smart-b5d2836f-337e-4956-82b2-105188ac2d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4002513024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.4002513024
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3881968623
Short name T2575
Test name
Test status
Simulation time 4107974968 ps
CPU time 4.58 seconds
Started Jul 12 05:33:38 PM PDT 24
Finished Jul 12 05:33:47 PM PDT 24
Peak memory 207036 kb
Host smart-cfc65230-1a5a-4959-8799-6577689ac0a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3881968623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.3881968623
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1956306213
Short name T1640
Test name
Test status
Simulation time 13368286218 ps
CPU time 11.82 seconds
Started Jul 12 05:33:12 PM PDT 24
Finished Jul 12 05:33:27 PM PDT 24
Peak memory 207060 kb
Host smart-08c3d151-c863-454f-930f-0224da7de175
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1956306213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1956306213
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.295392308
Short name T909
Test name
Test status
Simulation time 23325328705 ps
CPU time 22.61 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:35 PM PDT 24
Peak memory 207032 kb
Host smart-2ce93705-859f-47f3-a5fa-b2b8a2265a59
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=295392308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.295392308
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1605498721
Short name T1569
Test name
Test status
Simulation time 154640627 ps
CPU time 0.86 seconds
Started Jul 12 05:33:05 PM PDT 24
Finished Jul 12 05:33:11 PM PDT 24
Peak memory 206632 kb
Host smart-bdeb2470-f846-4038-8243-7954feda3133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16054
98721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1605498721
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2233602530
Short name T56
Test name
Test status
Simulation time 153624462 ps
CPU time 0.82 seconds
Started Jul 12 05:33:26 PM PDT 24
Finished Jul 12 05:33:34 PM PDT 24
Peak memory 206820 kb
Host smart-462b3098-3483-4316-a4a7-c5c2decd53c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22336
02530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2233602530
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.687278219
Short name T1559
Test name
Test status
Simulation time 296670408 ps
CPU time 1.17 seconds
Started Jul 12 05:33:18 PM PDT 24
Finished Jul 12 05:33:20 PM PDT 24
Peak memory 206816 kb
Host smart-050ba70c-c8dd-4692-8b8f-927fbebc170a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68727
8219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.687278219
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3655500066
Short name T1135
Test name
Test status
Simulation time 1012121564 ps
CPU time 2.19 seconds
Started Jul 12 05:33:02 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206928 kb
Host smart-d9fbc472-38af-45bd-bb66-8fce1aa2788a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36555
00066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3655500066
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.511964770
Short name T2187
Test name
Test status
Simulation time 18282027640 ps
CPU time 40.29 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:33:53 PM PDT 24
Peak memory 207068 kb
Host smart-f350d169-4692-4387-9d16-9c9181a442ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51196
4770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.511964770
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2308810918
Short name T1886
Test name
Test status
Simulation time 480286598 ps
CPU time 1.35 seconds
Started Jul 12 05:33:05 PM PDT 24
Finished Jul 12 05:33:12 PM PDT 24
Peak memory 206768 kb
Host smart-b2e435f2-e785-4b0d-bf64-0de1d49db674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23088
10918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2308810918
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.169479929
Short name T1731
Test name
Test status
Simulation time 147754924 ps
CPU time 0.81 seconds
Started Jul 12 05:33:14 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206828 kb
Host smart-5329c9d1-ccca-4b7f-9ff1-0167135c3a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16947
9929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.169479929
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2575400933
Short name T505
Test name
Test status
Simulation time 44926124 ps
CPU time 0.65 seconds
Started Jul 12 05:33:04 PM PDT 24
Finished Jul 12 05:33:10 PM PDT 24
Peak memory 206672 kb
Host smart-41901367-4f8b-4553-8bf1-719fb0e98834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25754
00933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2575400933
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.3915624576
Short name T626
Test name
Test status
Simulation time 909323019 ps
CPU time 2.04 seconds
Started Jul 12 05:33:10 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 206884 kb
Host smart-bdbfb2d7-9186-4691-a998-8e729b8aa64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39156
24576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3915624576
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2331942623
Short name T2075
Test name
Test status
Simulation time 264338352 ps
CPU time 1.71 seconds
Started Jul 12 05:33:11 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 206972 kb
Host smart-25796fb6-37b7-4bd7-b0e1-80b1bde787f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23319
42623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2331942623
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3896585346
Short name T755
Test name
Test status
Simulation time 235431918 ps
CPU time 0.87 seconds
Started Jul 12 05:33:22 PM PDT 24
Finished Jul 12 05:33:24 PM PDT 24
Peak memory 206820 kb
Host smart-9fd666db-580e-4fdf-a471-6bd1724c674d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38965
85346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3896585346
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2429003977
Short name T2437
Test name
Test status
Simulation time 133838228 ps
CPU time 0.77 seconds
Started Jul 12 05:33:18 PM PDT 24
Finished Jul 12 05:33:20 PM PDT 24
Peak memory 206804 kb
Host smart-8700fd3c-5e30-48ff-91bb-1e34b55c2b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24290
03977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2429003977
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3889101765
Short name T2428
Test name
Test status
Simulation time 235697490 ps
CPU time 0.93 seconds
Started Jul 12 05:33:11 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 206716 kb
Host smart-babadaaf-5a63-4a36-b77a-bcf8b0b6b71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38891
01765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3889101765
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.489052150
Short name T1510
Test name
Test status
Simulation time 4778859951 ps
CPU time 40.69 seconds
Started Jul 12 05:33:33 PM PDT 24
Finished Jul 12 05:34:16 PM PDT 24
Peak memory 207284 kb
Host smart-a209ec45-10cc-46c6-bc37-902c69ee68a8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=489052150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.489052150
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.3827256420
Short name T1374
Test name
Test status
Simulation time 11542038068 ps
CPU time 89.17 seconds
Started Jul 12 05:33:08 PM PDT 24
Finished Jul 12 05:34:42 PM PDT 24
Peak memory 207040 kb
Host smart-3a8e995f-d016-485a-8d5a-77baa2867cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38272
56420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.3827256420
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3628345885
Short name T1092
Test name
Test status
Simulation time 188794814 ps
CPU time 0.81 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:33:41 PM PDT 24
Peak memory 206976 kb
Host smart-3d0c02bd-8133-4979-9703-ce62f23fdc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36283
45885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3628345885
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1584537638
Short name T2651
Test name
Test status
Simulation time 23348611186 ps
CPU time 23.65 seconds
Started Jul 12 05:33:09 PM PDT 24
Finished Jul 12 05:33:38 PM PDT 24
Peak memory 206740 kb
Host smart-c098a9c3-4229-4a1b-9aea-3ab7e52a2ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845
37638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1584537638
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2044388019
Short name T1741
Test name
Test status
Simulation time 3303466865 ps
CPU time 3.81 seconds
Started Jul 12 05:33:13 PM PDT 24
Finished Jul 12 05:33:20 PM PDT 24
Peak memory 206780 kb
Host smart-95572359-723e-4040-97d4-727e97abdc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
88019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2044388019
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3091035736
Short name T965
Test name
Test status
Simulation time 8810263372 ps
CPU time 236.94 seconds
Started Jul 12 05:33:02 PM PDT 24
Finished Jul 12 05:37:05 PM PDT 24
Peak memory 206980 kb
Host smart-6a9224e4-bb0e-41c5-9bf3-32b0ce695180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30910
35736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3091035736
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2796996144
Short name T1843
Test name
Test status
Simulation time 7259673940 ps
CPU time 207.31 seconds
Started Jul 12 05:33:27 PM PDT 24
Finished Jul 12 05:36:55 PM PDT 24
Peak memory 207004 kb
Host smart-8722325c-2630-4412-8901-871cd77708ed
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2796996144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2796996144
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3906115114
Short name T433
Test name
Test status
Simulation time 239199267 ps
CPU time 0.89 seconds
Started Jul 12 05:33:10 PM PDT 24
Finished Jul 12 05:33:15 PM PDT 24
Peak memory 206824 kb
Host smart-c3acac04-ba03-4b09-8f20-e4a605947620
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3906115114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3906115114
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2219814673
Short name T891
Test name
Test status
Simulation time 189498648 ps
CPU time 0.9 seconds
Started Jul 12 05:33:13 PM PDT 24
Finished Jul 12 05:33:17 PM PDT 24
Peak memory 206828 kb
Host smart-18330f37-dc26-49c6-86ed-dd56fb34f02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22198
14673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2219814673
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2858454391
Short name T624
Test name
Test status
Simulation time 5614719198 ps
CPU time 152.2 seconds
Started Jul 12 05:33:23 PM PDT 24
Finished Jul 12 05:35:57 PM PDT 24
Peak memory 207040 kb
Host smart-f0fbd1c9-744c-4ce7-8e87-04f342e08e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28584
54391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2858454391
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.37797219
Short name T1898
Test name
Test status
Simulation time 7342672720 ps
CPU time 202.47 seconds
Started Jul 12 05:33:42 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 206984 kb
Host smart-7478fbd2-5003-4173-894b-95ae46b7fc32
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=37797219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.37797219
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.234690043
Short name T2094
Test name
Test status
Simulation time 155007194 ps
CPU time 0.81 seconds
Started Jul 12 05:33:30 PM PDT 24
Finished Jul 12 05:33:33 PM PDT 24
Peak memory 206700 kb
Host smart-4be757da-e380-4b2f-bfe9-9cd0e66e076c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=234690043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.234690043
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.132248775
Short name T1196
Test name
Test status
Simulation time 145477074 ps
CPU time 0.8 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 206824 kb
Host smart-782e201c-a016-4711-abc4-6363401f2165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13224
8775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.132248775
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.4015448643
Short name T565
Test name
Test status
Simulation time 181832766 ps
CPU time 0.87 seconds
Started Jul 12 05:33:38 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 206716 kb
Host smart-0cce9850-29a9-4ce0-aaed-cdea6e81023d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
48643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.4015448643
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1338762237
Short name T1909
Test name
Test status
Simulation time 179237539 ps
CPU time 0.88 seconds
Started Jul 12 05:33:38 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 206716 kb
Host smart-5efda2b4-7cc6-4c05-ac1b-1f22f6985b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13387
62237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1338762237
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.134998576
Short name T724
Test name
Test status
Simulation time 173667553 ps
CPU time 0.79 seconds
Started Jul 12 05:33:25 PM PDT 24
Finished Jul 12 05:33:27 PM PDT 24
Peak memory 206812 kb
Host smart-d8586eb8-d655-4fe2-99a2-f89b55cdce9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13499
8576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.134998576
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.865763104
Short name T2251
Test name
Test status
Simulation time 196948907 ps
CPU time 0.88 seconds
Started Jul 12 05:33:22 PM PDT 24
Finished Jul 12 05:33:25 PM PDT 24
Peak memory 206816 kb
Host smart-6df47f7f-2ccf-4aab-9d6d-fa31e0a27066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86576
3104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.865763104
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.947149547
Short name T880
Test name
Test status
Simulation time 222263263 ps
CPU time 0.86 seconds
Started Jul 12 05:33:29 PM PDT 24
Finished Jul 12 05:33:32 PM PDT 24
Peak memory 206760 kb
Host smart-2adb2d37-a04f-4191-8102-6a31bd06f473
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=947149547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.947149547
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1078679218
Short name T1572
Test name
Test status
Simulation time 191106583 ps
CPU time 0.8 seconds
Started Jul 12 05:33:29 PM PDT 24
Finished Jul 12 05:33:31 PM PDT 24
Peak memory 206804 kb
Host smart-13c821fc-6a7c-43e3-bc60-dfa1ad028c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10786
79218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1078679218
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3767030814
Short name T2666
Test name
Test status
Simulation time 89855557 ps
CPU time 0.73 seconds
Started Jul 12 05:33:12 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 206804 kb
Host smart-f3ab591d-92e4-4302-b1f6-dec71d14043c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37670
30814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3767030814
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3377704743
Short name T254
Test name
Test status
Simulation time 23330225135 ps
CPU time 57.29 seconds
Started Jul 12 05:33:34 PM PDT 24
Finished Jul 12 05:34:33 PM PDT 24
Peak memory 207116 kb
Host smart-6d30575e-a4d8-4905-9422-001f07b0088e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33777
04743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3377704743
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1268735738
Short name T1503
Test name
Test status
Simulation time 191196442 ps
CPU time 0.79 seconds
Started Jul 12 05:33:23 PM PDT 24
Finished Jul 12 05:33:25 PM PDT 24
Peak memory 206804 kb
Host smart-72135baf-4d71-44fe-a949-2f7fbef8bd75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12687
35738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1268735738
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3509201111
Short name T1771
Test name
Test status
Simulation time 254649424 ps
CPU time 0.92 seconds
Started Jul 12 05:33:38 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 206816 kb
Host smart-8cfcaeec-62b8-4e8e-8225-e6d8f394a55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35092
01111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3509201111
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1211107505
Short name T684
Test name
Test status
Simulation time 220374262 ps
CPU time 0.87 seconds
Started Jul 12 05:33:39 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 206720 kb
Host smart-1f78b122-eb57-474a-afa9-0feff4dc2b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12111
07505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1211107505
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.647111140
Short name T1471
Test name
Test status
Simulation time 196392650 ps
CPU time 0.83 seconds
Started Jul 12 05:33:07 PM PDT 24
Finished Jul 12 05:33:13 PM PDT 24
Peak memory 206696 kb
Host smart-cc7ed890-ccd5-41ee-888b-50c0ff596b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64711
1140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.647111140
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1722490602
Short name T1738
Test name
Test status
Simulation time 155393541 ps
CPU time 0.76 seconds
Started Jul 12 05:33:23 PM PDT 24
Finished Jul 12 05:33:25 PM PDT 24
Peak memory 206660 kb
Host smart-caa911e5-25e5-4d78-a961-9bde6f5dbdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
90602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1722490602
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2948859886
Short name T1746
Test name
Test status
Simulation time 184308445 ps
CPU time 0.86 seconds
Started Jul 12 05:33:46 PM PDT 24
Finished Jul 12 05:33:51 PM PDT 24
Peak memory 206628 kb
Host smart-f05c7886-c50c-4d8f-b00d-0262fb26dabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29488
59886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2948859886
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.424501800
Short name T2516
Test name
Test status
Simulation time 161008673 ps
CPU time 0.8 seconds
Started Jul 12 05:33:26 PM PDT 24
Finished Jul 12 05:33:27 PM PDT 24
Peak memory 206788 kb
Host smart-201d3c52-afda-4f9d-9b2e-1bec05c31b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42450
1800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.424501800
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1743173023
Short name T2271
Test name
Test status
Simulation time 184782233 ps
CPU time 0.87 seconds
Started Jul 12 05:33:26 PM PDT 24
Finished Jul 12 05:33:28 PM PDT 24
Peak memory 206816 kb
Host smart-0f7afecf-20af-4d52-89fa-5fb54de97d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17431
73023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1743173023
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.1044105116
Short name T2665
Test name
Test status
Simulation time 5025661390 ps
CPU time 136.87 seconds
Started Jul 12 05:33:32 PM PDT 24
Finished Jul 12 05:35:51 PM PDT 24
Peak memory 206884 kb
Host smart-2aa89473-6601-4a95-9e2b-27f9c88137be
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1044105116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.1044105116
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3058170731
Short name T358
Test name
Test status
Simulation time 205979670 ps
CPU time 0.92 seconds
Started Jul 12 05:33:12 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 206704 kb
Host smart-df62efa3-3aa1-48b0-a8c1-3125518a7cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30581
70731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3058170731
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2488134168
Short name T374
Test name
Test status
Simulation time 163689874 ps
CPU time 0.79 seconds
Started Jul 12 05:33:12 PM PDT 24
Finished Jul 12 05:33:16 PM PDT 24
Peak memory 206816 kb
Host smart-f582e4fc-6b4b-47e7-bdd2-682d8309ca34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24881
34168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2488134168
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.480709571
Short name T2627
Test name
Test status
Simulation time 789835499 ps
CPU time 1.74 seconds
Started Jul 12 05:33:13 PM PDT 24
Finished Jul 12 05:33:18 PM PDT 24
Peak memory 206916 kb
Host smart-722c7f40-14f4-446f-a4da-050abd937069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48070
9571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.480709571
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.3907369648
Short name T1352
Test name
Test status
Simulation time 3738144668 ps
CPU time 104.39 seconds
Started Jul 12 05:33:10 PM PDT 24
Finished Jul 12 05:34:59 PM PDT 24
Peak memory 207008 kb
Host smart-5f254c06-de30-4103-8580-c710c411c05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39073
69648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.3907369648
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.195652178
Short name T984
Test name
Test status
Simulation time 41913389 ps
CPU time 0.67 seconds
Started Jul 12 05:33:43 PM PDT 24
Finished Jul 12 05:33:48 PM PDT 24
Peak memory 206864 kb
Host smart-9c90a4ef-6cf9-4b48-93ca-ed9ffe07bf2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=195652178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.195652178
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.966630790
Short name T490
Test name
Test status
Simulation time 4127390720 ps
CPU time 4.84 seconds
Started Jul 12 05:33:33 PM PDT 24
Finished Jul 12 05:33:41 PM PDT 24
Peak memory 206956 kb
Host smart-18af55e2-aad8-448d-a948-41324181e8db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=966630790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.966630790
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3314113925
Short name T746
Test name
Test status
Simulation time 13533028448 ps
CPU time 15.33 seconds
Started Jul 12 05:33:29 PM PDT 24
Finished Jul 12 05:33:46 PM PDT 24
Peak memory 207076 kb
Host smart-878bf00b-d818-4d19-b907-f9d20ff91021
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3314113925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3314113925
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.1390671683
Short name T2202
Test name
Test status
Simulation time 23315940828 ps
CPU time 23 seconds
Started Jul 12 05:33:34 PM PDT 24
Finished Jul 12 05:34:00 PM PDT 24
Peak memory 206884 kb
Host smart-d33912de-310a-4d5e-b690-d24d9331575c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1390671683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.1390671683
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1940072735
Short name T2391
Test name
Test status
Simulation time 174667864 ps
CPU time 0.87 seconds
Started Jul 12 05:33:39 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 206796 kb
Host smart-1b73a988-afae-474b-9f93-6951af34b97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19400
72735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1940072735
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.624009213
Short name T1883
Test name
Test status
Simulation time 163069922 ps
CPU time 0.81 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 206816 kb
Host smart-a1ef246c-0887-4f50-a622-efa122e91b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62400
9213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.624009213
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1214493403
Short name T1880
Test name
Test status
Simulation time 261584966 ps
CPU time 1 seconds
Started Jul 12 05:33:45 PM PDT 24
Finished Jul 12 05:33:50 PM PDT 24
Peak memory 206804 kb
Host smart-c7a51818-284f-4a46-bfd9-ba2ed994b8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
93403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1214493403
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2517536883
Short name T1382
Test name
Test status
Simulation time 834075624 ps
CPU time 2.02 seconds
Started Jul 12 05:33:26 PM PDT 24
Finished Jul 12 05:33:29 PM PDT 24
Peak memory 207012 kb
Host smart-8edf9af0-52ca-4ab9-b7d9-821119e5d715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25175
36883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2517536883
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.2426848293
Short name T1995
Test name
Test status
Simulation time 15168631987 ps
CPU time 31.32 seconds
Started Jul 12 05:33:35 PM PDT 24
Finished Jul 12 05:34:08 PM PDT 24
Peak memory 207072 kb
Host smart-4a55eb8e-7252-49c3-834f-025c84eeda2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24268
48293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.2426848293
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1362239284
Short name T874
Test name
Test status
Simulation time 301083734 ps
CPU time 1.08 seconds
Started Jul 12 05:33:28 PM PDT 24
Finished Jul 12 05:33:31 PM PDT 24
Peak memory 206760 kb
Host smart-cc1b1337-b0d6-49be-afb8-8603c05b4246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13622
39284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1362239284
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.504172878
Short name T531
Test name
Test status
Simulation time 147403465 ps
CPU time 0.75 seconds
Started Jul 12 05:33:28 PM PDT 24
Finished Jul 12 05:33:31 PM PDT 24
Peak memory 206836 kb
Host smart-31ca29c8-8c27-44f7-aa1f-0393a82919d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50417
2878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.504172878
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.41256004
Short name T326
Test name
Test status
Simulation time 39497642 ps
CPU time 0.69 seconds
Started Jul 12 05:33:38 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 206784 kb
Host smart-ebc8da11-c91a-4e06-90ee-b9f0c9c655b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41256
004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.41256004
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.955620285
Short name T507
Test name
Test status
Simulation time 954525175 ps
CPU time 2.59 seconds
Started Jul 12 05:33:39 PM PDT 24
Finished Jul 12 05:33:47 PM PDT 24
Peak memory 206956 kb
Host smart-e849dbaa-e9a6-4ca7-82be-bc40dc8bb4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95562
0285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.955620285
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.4047257872
Short name T2544
Test name
Test status
Simulation time 202358646 ps
CPU time 1.96 seconds
Started Jul 12 05:33:30 PM PDT 24
Finished Jul 12 05:33:34 PM PDT 24
Peak memory 206964 kb
Host smart-78ec9254-53d6-4728-8867-e8891729cfc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40472
57872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.4047257872
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1788610729
Short name T1636
Test name
Test status
Simulation time 153652091 ps
CPU time 0.79 seconds
Started Jul 12 05:33:31 PM PDT 24
Finished Jul 12 05:33:34 PM PDT 24
Peak memory 206808 kb
Host smart-1e8a1277-47f3-46eb-9a62-5cb4e21d87cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17886
10729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1788610729
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2410286180
Short name T1462
Test name
Test status
Simulation time 139425739 ps
CPU time 0.78 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:33:41 PM PDT 24
Peak memory 206764 kb
Host smart-747f52ad-e5d6-44d5-9602-4229a9135a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24102
86180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2410286180
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1562005868
Short name T1936
Test name
Test status
Simulation time 257972953 ps
CPU time 0.97 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 206756 kb
Host smart-eec0ea50-4706-4779-b266-77a836b1c5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15620
05868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1562005868
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.2231707259
Short name T2049
Test name
Test status
Simulation time 8211269579 ps
CPU time 27.34 seconds
Started Jul 12 05:33:46 PM PDT 24
Finished Jul 12 05:34:17 PM PDT 24
Peak memory 207016 kb
Host smart-459575a8-bee6-491f-9a28-6e091282da77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22317
07259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.2231707259
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.978443810
Short name T1764
Test name
Test status
Simulation time 245154782 ps
CPU time 0.93 seconds
Started Jul 12 05:33:33 PM PDT 24
Finished Jul 12 05:33:36 PM PDT 24
Peak memory 206808 kb
Host smart-6e7eec42-5b15-48d7-b7be-4c4a63841742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97844
3810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.978443810
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3819722795
Short name T858
Test name
Test status
Simulation time 23344278329 ps
CPU time 22.84 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:34:04 PM PDT 24
Peak memory 206876 kb
Host smart-fd88b72a-ab91-405c-966a-c3e15567d62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38197
22795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3819722795
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2249573084
Short name T681
Test name
Test status
Simulation time 3311360184 ps
CPU time 3.74 seconds
Started Jul 12 05:33:29 PM PDT 24
Finished Jul 12 05:33:35 PM PDT 24
Peak memory 206876 kb
Host smart-1692a532-21d4-47d7-bf7f-c0577b534cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22495
73084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2249573084
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1777153156
Short name T580
Test name
Test status
Simulation time 9620715228 ps
CPU time 94.97 seconds
Started Jul 12 05:33:28 PM PDT 24
Finished Jul 12 05:35:04 PM PDT 24
Peak memory 207108 kb
Host smart-d5d4eaab-d790-4042-8a2d-6d858c025e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17771
53156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1777153156
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2971383763
Short name T2376
Test name
Test status
Simulation time 5916484234 ps
CPU time 162.38 seconds
Started Jul 12 05:33:28 PM PDT 24
Finished Jul 12 05:36:11 PM PDT 24
Peak memory 207000 kb
Host smart-b45b7923-6eec-4e38-9cd1-203f6e7ae55f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2971383763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2971383763
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3109811456
Short name T1221
Test name
Test status
Simulation time 244711057 ps
CPU time 0.87 seconds
Started Jul 12 05:33:26 PM PDT 24
Finished Jul 12 05:33:28 PM PDT 24
Peak memory 206704 kb
Host smart-dc45bfa1-1847-427f-a03a-cbaece8df5b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3109811456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3109811456
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1840874496
Short name T2004
Test name
Test status
Simulation time 217539238 ps
CPU time 0.9 seconds
Started Jul 12 05:33:40 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 206820 kb
Host smart-fc007987-a25c-4ac0-8274-cf749b3fd541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18408
74496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1840874496
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.358095182
Short name T2028
Test name
Test status
Simulation time 3835414713 ps
CPU time 102.71 seconds
Started Jul 12 05:33:35 PM PDT 24
Finished Jul 12 05:35:20 PM PDT 24
Peak memory 206984 kb
Host smart-a15c4214-6bc7-49bf-abb9-ae863aab0e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
5182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.358095182
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2199592266
Short name T2266
Test name
Test status
Simulation time 4667541307 ps
CPU time 128.19 seconds
Started Jul 12 05:33:50 PM PDT 24
Finished Jul 12 05:36:04 PM PDT 24
Peak memory 207012 kb
Host smart-1ff1bc44-fd53-4e74-8f78-4b9b96d29275
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2199592266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2199592266
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1415606756
Short name T1542
Test name
Test status
Simulation time 175468393 ps
CPU time 0.82 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:33:39 PM PDT 24
Peak memory 206688 kb
Host smart-77fb0bfe-880d-4009-8c55-36efa9dbea27
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1415606756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1415606756
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2517825815
Short name T2026
Test name
Test status
Simulation time 153975270 ps
CPU time 0.77 seconds
Started Jul 12 05:33:43 PM PDT 24
Finished Jul 12 05:33:48 PM PDT 24
Peak memory 206800 kb
Host smart-fc3614e1-312e-470f-ba16-8f49534083f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25178
25815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2517825815
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.522205534
Short name T111
Test name
Test status
Simulation time 231981075 ps
CPU time 0.88 seconds
Started Jul 12 05:33:33 PM PDT 24
Finished Jul 12 05:33:37 PM PDT 24
Peak memory 206760 kb
Host smart-2820117f-4cdc-4c5b-b2cc-7aa426938869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52220
5534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.522205534
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.195541782
Short name T1432
Test name
Test status
Simulation time 192045410 ps
CPU time 0.89 seconds
Started Jul 12 05:33:45 PM PDT 24
Finished Jul 12 05:33:51 PM PDT 24
Peak memory 206680 kb
Host smart-ebd59913-c1f5-43d4-8f67-0fff3a3fccc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19554
1782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.195541782
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3426574972
Short name T1197
Test name
Test status
Simulation time 211490846 ps
CPU time 0.94 seconds
Started Jul 12 05:33:43 PM PDT 24
Finished Jul 12 05:33:49 PM PDT 24
Peak memory 206688 kb
Host smart-ac601e2b-fb9e-4b7e-a47b-43b52fa41e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34265
74972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3426574972
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1960960629
Short name T2497
Test name
Test status
Simulation time 182276319 ps
CPU time 0.81 seconds
Started Jul 12 05:33:31 PM PDT 24
Finished Jul 12 05:33:34 PM PDT 24
Peak memory 206808 kb
Host smart-9f841e63-0cb4-4fbf-ba68-56cccbd1137f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19609
60629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1960960629
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3764354211
Short name T1644
Test name
Test status
Simulation time 165914056 ps
CPU time 0.83 seconds
Started Jul 12 05:33:44 PM PDT 24
Finished Jul 12 05:33:50 PM PDT 24
Peak memory 206780 kb
Host smart-2819eb17-6e12-45fe-9940-af32ee854e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37643
54211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3764354211
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1572056561
Short name T1892
Test name
Test status
Simulation time 210220981 ps
CPU time 0.9 seconds
Started Jul 12 05:33:42 PM PDT 24
Finished Jul 12 05:33:48 PM PDT 24
Peak memory 206792 kb
Host smart-020bd356-0337-4830-ad91-18f463742418
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1572056561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1572056561
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3057010918
Short name T2708
Test name
Test status
Simulation time 162252519 ps
CPU time 0.8 seconds
Started Jul 12 05:33:32 PM PDT 24
Finished Jul 12 05:33:35 PM PDT 24
Peak memory 206808 kb
Host smart-bda72d27-740f-4791-93b1-06cab6f36c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30570
10918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3057010918
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2379252835
Short name T2186
Test name
Test status
Simulation time 36800702 ps
CPU time 0.69 seconds
Started Jul 12 05:33:53 PM PDT 24
Finished Jul 12 05:34:11 PM PDT 24
Peak memory 206804 kb
Host smart-81073117-529c-4826-bb8a-095f9c50412e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
52835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2379252835
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.324558830
Short name T1005
Test name
Test status
Simulation time 11030888819 ps
CPU time 25.51 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:34:05 PM PDT 24
Peak memory 207076 kb
Host smart-4fdd984d-5aab-4717-88bc-012350e3543d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455
8830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.324558830
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3582969207
Short name T2255
Test name
Test status
Simulation time 207162527 ps
CPU time 0.86 seconds
Started Jul 12 05:33:41 PM PDT 24
Finished Jul 12 05:33:47 PM PDT 24
Peak memory 206816 kb
Host smart-555f93df-f9f3-4027-ae4b-2cfd572f6e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35829
69207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3582969207
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2116743370
Short name T1991
Test name
Test status
Simulation time 244536223 ps
CPU time 0.93 seconds
Started Jul 12 05:33:56 PM PDT 24
Finished Jul 12 05:34:14 PM PDT 24
Peak memory 206820 kb
Host smart-c1c25019-e434-44f7-b4ac-b40af9c4de4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21167
43370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2116743370
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2046242482
Short name T1604
Test name
Test status
Simulation time 203490299 ps
CPU time 0.86 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:33:39 PM PDT 24
Peak memory 206808 kb
Host smart-606163af-be29-4ecc-9d64-57eb43698c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20462
42482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2046242482
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1892815818
Short name T1118
Test name
Test status
Simulation time 175820723 ps
CPU time 0.84 seconds
Started Jul 12 05:33:31 PM PDT 24
Finished Jul 12 05:33:33 PM PDT 24
Peak memory 206836 kb
Host smart-405ada4e-0e84-42c7-9608-c781f4c2a06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18928
15818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1892815818
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.790479161
Short name T472
Test name
Test status
Simulation time 147541064 ps
CPU time 0.76 seconds
Started Jul 12 05:33:40 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 206632 kb
Host smart-94b719b0-26b8-4ca7-8af4-d770b1285f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79047
9161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.790479161
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3746390714
Short name T1280
Test name
Test status
Simulation time 153830773 ps
CPU time 0.77 seconds
Started Jul 12 05:33:27 PM PDT 24
Finished Jul 12 05:33:29 PM PDT 24
Peak memory 206800 kb
Host smart-a40b88a3-becd-43ad-a7a7-21ae16074439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37463
90714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3746390714
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2641360488
Short name T2498
Test name
Test status
Simulation time 147460833 ps
CPU time 0.83 seconds
Started Jul 12 05:33:45 PM PDT 24
Finished Jul 12 05:33:50 PM PDT 24
Peak memory 206820 kb
Host smart-62337171-81f2-422b-9014-8f4ef587d14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
60488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2641360488
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.622644389
Short name T22
Test name
Test status
Simulation time 252414545 ps
CPU time 0.95 seconds
Started Jul 12 05:33:50 PM PDT 24
Finished Jul 12 05:33:57 PM PDT 24
Peak memory 206808 kb
Host smart-004527bd-f7c8-4504-800f-2bb3965ca60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62264
4389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.622644389
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2992713864
Short name T2193
Test name
Test status
Simulation time 5357093048 ps
CPU time 52.83 seconds
Started Jul 12 05:33:48 PM PDT 24
Finished Jul 12 05:34:45 PM PDT 24
Peak memory 207020 kb
Host smart-07bc44fd-00c1-4ce5-8345-a8f42f04a5c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2992713864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2992713864
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3719094829
Short name T141
Test name
Test status
Simulation time 191777248 ps
CPU time 0.81 seconds
Started Jul 12 05:33:49 PM PDT 24
Finished Jul 12 05:33:55 PM PDT 24
Peak memory 206692 kb
Host smart-c05aa6d5-9ee9-44ec-934e-4f122910c93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
94829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3719094829
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.865605707
Short name T915
Test name
Test status
Simulation time 149157054 ps
CPU time 0.79 seconds
Started Jul 12 05:33:32 PM PDT 24
Finished Jul 12 05:33:35 PM PDT 24
Peak memory 206816 kb
Host smart-186f7d67-bc3d-4b75-85ea-9e530c785464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86560
5707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.865605707
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.1861386629
Short name T819
Test name
Test status
Simulation time 1063904560 ps
CPU time 2.25 seconds
Started Jul 12 05:33:52 PM PDT 24
Finished Jul 12 05:34:04 PM PDT 24
Peak memory 206848 kb
Host smart-7bbf082c-8fb0-4f6e-8efe-ed0b39855196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18613
86629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1861386629
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2712683978
Short name T2400
Test name
Test status
Simulation time 4268777144 ps
CPU time 119.02 seconds
Started Jul 12 05:33:33 PM PDT 24
Finished Jul 12 05:35:35 PM PDT 24
Peak memory 207024 kb
Host smart-de99e314-4fbf-4acf-a0ed-c338d42fc177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27126
83978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2712683978
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.128171139
Short name T959
Test name
Test status
Simulation time 47699317 ps
CPU time 0.68 seconds
Started Jul 12 05:33:50 PM PDT 24
Finished Jul 12 05:33:56 PM PDT 24
Peak memory 206736 kb
Host smart-90159444-7fe4-42cd-a22b-1143e7c399d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=128171139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.128171139
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3227227099
Short name T1772
Test name
Test status
Simulation time 4050982622 ps
CPU time 4.54 seconds
Started Jul 12 05:33:51 PM PDT 24
Finished Jul 12 05:34:02 PM PDT 24
Peak memory 207076 kb
Host smart-61241aca-3613-4acf-abb6-26cb4aa54d6f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3227227099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3227227099
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3166204975
Short name T2230
Test name
Test status
Simulation time 13477231096 ps
CPU time 13.7 seconds
Started Jul 12 05:33:51 PM PDT 24
Finished Jul 12 05:34:10 PM PDT 24
Peak memory 207080 kb
Host smart-473f2bc2-3aa0-414f-84bb-281733813594
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3166204975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3166204975
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.87589129
Short name T8
Test name
Test status
Simulation time 23387398429 ps
CPU time 23.6 seconds
Started Jul 12 05:33:43 PM PDT 24
Finished Jul 12 05:34:11 PM PDT 24
Peak memory 206856 kb
Host smart-e6a67fd4-5686-4edf-b483-a48a00c354ee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=87589129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.87589129
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3313383763
Short name T2216
Test name
Test status
Simulation time 164102483 ps
CPU time 0.79 seconds
Started Jul 12 05:33:43 PM PDT 24
Finished Jul 12 05:33:48 PM PDT 24
Peak memory 206812 kb
Host smart-2e60516a-7aeb-4cdf-9ec6-40d02f41e20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33133
83763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3313383763
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2559496445
Short name T629
Test name
Test status
Simulation time 142023698 ps
CPU time 0.76 seconds
Started Jul 12 05:33:49 PM PDT 24
Finished Jul 12 05:33:55 PM PDT 24
Peak memory 206796 kb
Host smart-9b2bba3d-1bb5-436a-b67b-33ed0f10233b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25594
96445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2559496445
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.945271029
Short name T512
Test name
Test status
Simulation time 294190717 ps
CPU time 1.04 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:33:41 PM PDT 24
Peak memory 206772 kb
Host smart-896f2db5-00e7-43ff-8b3b-2d7c795b0d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94527
1029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.945271029
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3344008980
Short name T1394
Test name
Test status
Simulation time 301355835 ps
CPU time 0.99 seconds
Started Jul 12 05:33:38 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 206812 kb
Host smart-b63c524a-f280-4ccf-8e01-876a9a6e74a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33440
08980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3344008980
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3026774529
Short name T1987
Test name
Test status
Simulation time 7049325225 ps
CPU time 13.38 seconds
Started Jul 12 05:33:34 PM PDT 24
Finished Jul 12 05:33:50 PM PDT 24
Peak memory 207248 kb
Host smart-29bc1ca9-55b3-42f1-936f-0a25bf598cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267
74529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3026774529
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1004269873
Short name T2252
Test name
Test status
Simulation time 447728266 ps
CPU time 1.47 seconds
Started Jul 12 05:33:31 PM PDT 24
Finished Jul 12 05:33:35 PM PDT 24
Peak memory 206760 kb
Host smart-be5f36b7-d179-4066-b49c-fee9f885d22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10042
69873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1004269873
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1886573504
Short name T652
Test name
Test status
Simulation time 230121520 ps
CPU time 0.87 seconds
Started Jul 12 05:33:47 PM PDT 24
Finished Jul 12 05:33:53 PM PDT 24
Peak memory 206800 kb
Host smart-830a1161-e968-47a2-a50f-1ed74bcdf28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
73504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1886573504
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3126637357
Short name T754
Test name
Test status
Simulation time 44489944 ps
CPU time 0.71 seconds
Started Jul 12 05:33:50 PM PDT 24
Finished Jul 12 05:33:56 PM PDT 24
Peak memory 206828 kb
Host smart-3b0388d2-73f6-4df8-b35b-3ef2438b02aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31266
37357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3126637357
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1388116280
Short name T598
Test name
Test status
Simulation time 1075817978 ps
CPU time 2.23 seconds
Started Jul 12 05:33:30 PM PDT 24
Finished Jul 12 05:33:34 PM PDT 24
Peak memory 206848 kb
Host smart-bc01ce04-b041-47c5-9da4-934a5bab82a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13881
16280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1388116280
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2378297186
Short name T948
Test name
Test status
Simulation time 186274716 ps
CPU time 1.24 seconds
Started Jul 12 05:33:31 PM PDT 24
Finished Jul 12 05:33:35 PM PDT 24
Peak memory 206804 kb
Host smart-16ee4f49-0ce3-4363-bc32-1daa052d9c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23782
97186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2378297186
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.196253001
Short name T1344
Test name
Test status
Simulation time 216061892 ps
CPU time 0.85 seconds
Started Jul 12 05:33:57 PM PDT 24
Finished Jul 12 05:34:15 PM PDT 24
Peak memory 206816 kb
Host smart-a355324f-48c9-49a5-94dc-4f941bebabad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19625
3001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.196253001
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1728076023
Short name T2415
Test name
Test status
Simulation time 168387799 ps
CPU time 0.84 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:33:41 PM PDT 24
Peak memory 206560 kb
Host smart-40766711-f77e-4aaf-aa9b-a97abb918c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17280
76023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1728076023
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2541049684
Short name T1011
Test name
Test status
Simulation time 263035873 ps
CPU time 0.9 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 206752 kb
Host smart-9075f7f4-731d-4e94-bb17-d6c18f67d053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
49684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2541049684
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.314497695
Short name T1603
Test name
Test status
Simulation time 5532406093 ps
CPU time 21.45 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:34:02 PM PDT 24
Peak memory 206860 kb
Host smart-a2698708-c6af-4c91-b856-4b1a6237dc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31449
7695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.314497695
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2958049401
Short name T2702
Test name
Test status
Simulation time 178632265 ps
CPU time 0.82 seconds
Started Jul 12 05:33:44 PM PDT 24
Finished Jul 12 05:33:50 PM PDT 24
Peak memory 206812 kb
Host smart-2bd809d3-5ce4-491f-b13f-86eba11ebc06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580
49401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2958049401
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1675021542
Short name T2411
Test name
Test status
Simulation time 23307826540 ps
CPU time 22.23 seconds
Started Jul 12 05:33:38 PM PDT 24
Finished Jul 12 05:34:05 PM PDT 24
Peak memory 206880 kb
Host smart-ba0a4dd2-2bef-40ee-9012-25225729d7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16750
21542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1675021542
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2726357189
Short name T1497
Test name
Test status
Simulation time 3338118659 ps
CPU time 3.7 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 206876 kb
Host smart-c5aadde7-fb5a-47c2-a13e-dc7d97bb0c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27263
57189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2726357189
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.4047551759
Short name T1734
Test name
Test status
Simulation time 11503076206 ps
CPU time 80.93 seconds
Started Jul 12 05:33:41 PM PDT 24
Finished Jul 12 05:35:07 PM PDT 24
Peak memory 207088 kb
Host smart-b647e801-5bdc-4bb3-95ed-b043d4f9d6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40475
51759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.4047551759
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.240087667
Short name T1282
Test name
Test status
Simulation time 4066715393 ps
CPU time 26.9 seconds
Started Jul 12 05:33:36 PM PDT 24
Finished Jul 12 05:34:07 PM PDT 24
Peak memory 207064 kb
Host smart-1747e1f9-8f7a-4008-83f2-b0ee551d5dbb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=240087667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.240087667
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3681736868
Short name T2626
Test name
Test status
Simulation time 265779355 ps
CPU time 0.91 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:33:42 PM PDT 24
Peak memory 206716 kb
Host smart-1d989d94-26c4-419c-9ba1-9fddbdc50990
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3681736868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3681736868
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3051706779
Short name T1051
Test name
Test status
Simulation time 184523303 ps
CPU time 0.84 seconds
Started Jul 12 05:33:41 PM PDT 24
Finished Jul 12 05:33:47 PM PDT 24
Peak memory 206832 kb
Host smart-1ea4f5b1-ae10-495e-93ee-886b3675fd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30517
06779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3051706779
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3147766926
Short name T2095
Test name
Test status
Simulation time 5881310584 ps
CPU time 41.12 seconds
Started Jul 12 05:33:43 PM PDT 24
Finished Jul 12 05:34:29 PM PDT 24
Peak memory 207032 kb
Host smart-17c5bb36-295c-405e-8d66-d8f483cdf011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31477
66926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3147766926
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3001091002
Short name T2517
Test name
Test status
Simulation time 6877903760 ps
CPU time 47.64 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:34:29 PM PDT 24
Peak memory 207016 kb
Host smart-cc823352-3c3e-4a8c-82d3-6f4431eec7f1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3001091002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3001091002
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.3857708781
Short name T2430
Test name
Test status
Simulation time 169619213 ps
CPU time 0.89 seconds
Started Jul 12 05:33:40 PM PDT 24
Finished Jul 12 05:33:46 PM PDT 24
Peak memory 206696 kb
Host smart-479bfbad-615e-4187-b3aa-a3c402712d84
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3857708781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.3857708781
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3599038550
Short name T536
Test name
Test status
Simulation time 169396686 ps
CPU time 0.78 seconds
Started Jul 12 05:33:35 PM PDT 24
Finished Jul 12 05:33:39 PM PDT 24
Peak memory 206796 kb
Host smart-78927cde-7c10-4dfb-a484-f7788172b023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35990
38550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3599038550
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3903113974
Short name T114
Test name
Test status
Simulation time 198679749 ps
CPU time 0.84 seconds
Started Jul 12 05:33:52 PM PDT 24
Finished Jul 12 05:34:01 PM PDT 24
Peak memory 206792 kb
Host smart-8f9d1422-11a3-4eb7-8690-9239675d098c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39031
13974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3903113974
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.330250251
Short name T1715
Test name
Test status
Simulation time 155614858 ps
CPU time 0.76 seconds
Started Jul 12 05:33:47 PM PDT 24
Finished Jul 12 05:33:52 PM PDT 24
Peak memory 206816 kb
Host smart-7fc10cdb-0084-448c-9706-e44dffedbde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33025
0251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.330250251
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1507093806
Short name T738
Test name
Test status
Simulation time 196755984 ps
CPU time 0.83 seconds
Started Jul 12 05:33:35 PM PDT 24
Finished Jul 12 05:33:38 PM PDT 24
Peak memory 206800 kb
Host smart-7c673497-e498-4c66-abcf-5fb4180b81f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15070
93806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1507093806
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2101711081
Short name T400
Test name
Test status
Simulation time 190993523 ps
CPU time 0.86 seconds
Started Jul 12 05:33:34 PM PDT 24
Finished Jul 12 05:33:37 PM PDT 24
Peak memory 206828 kb
Host smart-a899e162-4b56-4fbe-9e3e-9d62a0d93e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21017
11081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2101711081
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1872223896
Short name T611
Test name
Test status
Simulation time 143294357 ps
CPU time 0.81 seconds
Started Jul 12 05:33:39 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 206832 kb
Host smart-d7af919e-d82e-4068-b839-1ab127cdc2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18722
23896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1872223896
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1511026904
Short name T432
Test name
Test status
Simulation time 233413501 ps
CPU time 0.96 seconds
Started Jul 12 05:33:40 PM PDT 24
Finished Jul 12 05:33:46 PM PDT 24
Peak memory 206672 kb
Host smart-06a086f4-1e7c-4c12-a2fa-df8cc062d0fe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1511026904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1511026904
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.358067005
Short name T742
Test name
Test status
Simulation time 141571896 ps
CPU time 0.74 seconds
Started Jul 12 05:33:42 PM PDT 24
Finished Jul 12 05:33:48 PM PDT 24
Peak memory 206820 kb
Host smart-a80254a8-f10b-4aa0-bfb9-fb161f4c1b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
7005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.358067005
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2324049536
Short name T23
Test name
Test status
Simulation time 65265279 ps
CPU time 0.68 seconds
Started Jul 12 05:33:40 PM PDT 24
Finished Jul 12 05:33:45 PM PDT 24
Peak memory 206688 kb
Host smart-5abc1fbb-ae9e-46af-8ad5-ddffeeb9d9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23240
49536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2324049536
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.53126823
Short name T2032
Test name
Test status
Simulation time 6980874370 ps
CPU time 18.07 seconds
Started Jul 12 05:33:40 PM PDT 24
Finished Jul 12 05:34:03 PM PDT 24
Peak memory 207084 kb
Host smart-d25b1633-6527-461a-8290-7f18a8e464d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53126
823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.53126823
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1468631488
Short name T1444
Test name
Test status
Simulation time 167841802 ps
CPU time 0.81 seconds
Started Jul 12 05:33:44 PM PDT 24
Finished Jul 12 05:33:50 PM PDT 24
Peak memory 206820 kb
Host smart-ddd9c41e-dc2a-4032-834a-66db842bdf6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14686
31488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1468631488
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2141913012
Short name T2700
Test name
Test status
Simulation time 220530235 ps
CPU time 0.93 seconds
Started Jul 12 05:33:37 PM PDT 24
Finished Jul 12 05:33:43 PM PDT 24
Peak memory 206816 kb
Host smart-e09e17b3-1d03-477b-a798-d617b3bd8749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21419
13012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2141913012
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1666773714
Short name T594
Test name
Test status
Simulation time 225479278 ps
CPU time 0.9 seconds
Started Jul 12 05:33:41 PM PDT 24
Finished Jul 12 05:33:47 PM PDT 24
Peak memory 206820 kb
Host smart-d99b4771-a2d7-48ce-bf1c-47e20f6d7b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16667
73714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1666773714
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3891825563
Short name T821
Test name
Test status
Simulation time 214353223 ps
CPU time 0.82 seconds
Started Jul 12 05:33:48 PM PDT 24
Finished Jul 12 05:33:54 PM PDT 24
Peak memory 206820 kb
Host smart-1db5a314-15f2-4a8a-b34f-2941bb84d7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38918
25563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3891825563
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.511808181
Short name T683
Test name
Test status
Simulation time 150604999 ps
CPU time 0.83 seconds
Started Jul 12 05:33:48 PM PDT 24
Finished Jul 12 05:33:54 PM PDT 24
Peak memory 206824 kb
Host smart-a1f064cc-50df-4b0d-b195-2d10b0412a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51180
8181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.511808181
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.751667551
Short name T1402
Test name
Test status
Simulation time 156152886 ps
CPU time 0.79 seconds
Started Jul 12 05:33:50 PM PDT 24
Finished Jul 12 05:33:56 PM PDT 24
Peak memory 206792 kb
Host smart-0f684b49-9035-4190-bc55-4c4a71785101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75166
7551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.751667551
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.937452850
Short name T844
Test name
Test status
Simulation time 159212258 ps
CPU time 0.81 seconds
Started Jul 12 05:33:46 PM PDT 24
Finished Jul 12 05:33:51 PM PDT 24
Peak memory 206812 kb
Host smart-1873247b-4ef0-4354-8608-e4365a218dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93745
2850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.937452850
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.813875990
Short name T1288
Test name
Test status
Simulation time 216731330 ps
CPU time 0.97 seconds
Started Jul 12 05:33:53 PM PDT 24
Finished Jul 12 05:34:09 PM PDT 24
Peak memory 206792 kb
Host smart-f8ffabdc-ba9a-4f1b-ad48-9ac6323f4c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81387
5990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.813875990
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1839138821
Short name T2209
Test name
Test status
Simulation time 5288242071 ps
CPU time 48.61 seconds
Started Jul 12 05:33:48 PM PDT 24
Finished Jul 12 05:34:41 PM PDT 24
Peak memory 206928 kb
Host smart-42e433a1-8d3c-4731-aa1b-8c9c931c4b3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1839138821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1839138821
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1106283529
Short name T394
Test name
Test status
Simulation time 188002377 ps
CPU time 0.8 seconds
Started Jul 12 05:33:54 PM PDT 24
Finished Jul 12 05:34:11 PM PDT 24
Peak memory 206700 kb
Host smart-c774279e-4adf-4349-8b79-2a6046aa22ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
83529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1106283529
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.309842469
Short name T886
Test name
Test status
Simulation time 177039305 ps
CPU time 0.84 seconds
Started Jul 12 05:33:52 PM PDT 24
Finished Jul 12 05:34:03 PM PDT 24
Peak memory 206816 kb
Host smart-db7e885f-4990-45c4-b398-931ee4243d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
2469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.309842469
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1947632547
Short name T2069
Test name
Test status
Simulation time 391611240 ps
CPU time 1.15 seconds
Started Jul 12 05:33:39 PM PDT 24
Finished Jul 12 05:33:44 PM PDT 24
Peak memory 206756 kb
Host smart-a4af5ff4-a88d-4d7b-bad2-82ea3724b5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19476
32547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1947632547
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.779331781
Short name T1600
Test name
Test status
Simulation time 3390182818 ps
CPU time 32.42 seconds
Started Jul 12 05:33:51 PM PDT 24
Finished Jul 12 05:34:29 PM PDT 24
Peak memory 207080 kb
Host smart-17f4488b-09e5-478e-addb-20411b0edff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77933
1781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.779331781
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.4019008105
Short name T801
Test name
Test status
Simulation time 50931658 ps
CPU time 0.7 seconds
Started Jul 12 05:27:14 PM PDT 24
Finished Jul 12 05:27:16 PM PDT 24
Peak memory 206844 kb
Host smart-b8eebed2-a7b8-44ea-b086-cb810a78ce65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4019008105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.4019008105
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2218029155
Short name T1629
Test name
Test status
Simulation time 4410959352 ps
CPU time 4.96 seconds
Started Jul 12 05:26:56 PM PDT 24
Finished Jul 12 05:27:02 PM PDT 24
Peak memory 207060 kb
Host smart-6d14ec43-2572-484b-94ba-4e9a5394d376
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2218029155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2218029155
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2627601322
Short name T1960
Test name
Test status
Simulation time 13418982882 ps
CPU time 14.88 seconds
Started Jul 12 05:26:55 PM PDT 24
Finished Jul 12 05:27:12 PM PDT 24
Peak memory 207036 kb
Host smart-661563ce-0f41-4f70-8f3d-724d2cedc83f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2627601322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2627601322
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.202474827
Short name T7
Test name
Test status
Simulation time 23364496387 ps
CPU time 22.74 seconds
Started Jul 12 05:27:00 PM PDT 24
Finished Jul 12 05:27:25 PM PDT 24
Peak memory 206968 kb
Host smart-ead2f407-a87e-4502-9303-29b7356ba810
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=202474827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.202474827
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.193351055
Short name T950
Test name
Test status
Simulation time 158406788 ps
CPU time 0.79 seconds
Started Jul 12 05:26:57 PM PDT 24
Finished Jul 12 05:26:59 PM PDT 24
Peak memory 206720 kb
Host smart-e487ebcf-27d2-42e0-9fe9-eaafcae6a954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19335
1055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.193351055
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3180937488
Short name T55
Test name
Test status
Simulation time 178560529 ps
CPU time 0.82 seconds
Started Jul 12 05:27:12 PM PDT 24
Finished Jul 12 05:27:15 PM PDT 24
Peak memory 206808 kb
Host smart-2b4b03de-6915-4660-a97f-ad724f653f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31809
37488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3180937488
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.723595425
Short name T1779
Test name
Test status
Simulation time 244140987 ps
CPU time 1.04 seconds
Started Jul 12 05:26:55 PM PDT 24
Finished Jul 12 05:26:57 PM PDT 24
Peak memory 206636 kb
Host smart-424ded8e-8367-4202-be4f-1abf03506683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72359
5425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.723595425
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.905941754
Short name T355
Test name
Test status
Simulation time 1189029660 ps
CPU time 2.6 seconds
Started Jul 12 05:27:00 PM PDT 24
Finished Jul 12 05:27:04 PM PDT 24
Peak memory 206992 kb
Host smart-6d7c9e0b-104e-4a07-9f3a-c65453057553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90594
1754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.905941754
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.347371224
Short name T174
Test name
Test status
Simulation time 19793978130 ps
CPU time 38.96 seconds
Started Jul 12 05:27:00 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 207080 kb
Host smart-0f780002-b2a6-41dd-89f7-38fd24683463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34737
1224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.347371224
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3354292452
Short name T410
Test name
Test status
Simulation time 357834879 ps
CPU time 1.11 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:08 PM PDT 24
Peak memory 206816 kb
Host smart-412142a4-484b-4498-8cec-ec4a38078633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33542
92452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3354292452
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3082176424
Short name T1361
Test name
Test status
Simulation time 150569695 ps
CPU time 0.79 seconds
Started Jul 12 05:27:12 PM PDT 24
Finished Jul 12 05:27:13 PM PDT 24
Peak memory 206772 kb
Host smart-ca1ee354-9692-46bd-b5e6-e9a1ae8cf17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30821
76424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3082176424
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2783905247
Short name T2224
Test name
Test status
Simulation time 39406017 ps
CPU time 0.69 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:06 PM PDT 24
Peak memory 206804 kb
Host smart-8b0dfea2-71bb-40d6-9ed7-0fd60954e741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27839
05247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2783905247
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3100845043
Short name T2393
Test name
Test status
Simulation time 936629136 ps
CPU time 2.08 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:27:11 PM PDT 24
Peak memory 206980 kb
Host smart-f4655210-d00b-4735-8f2e-95ef60d17a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31008
45043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3100845043
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4278816841
Short name T2205
Test name
Test status
Simulation time 172258786 ps
CPU time 1.81 seconds
Started Jul 12 05:27:03 PM PDT 24
Finished Jul 12 05:27:06 PM PDT 24
Peak memory 206960 kb
Host smart-1d10f3a7-38b2-4c2c-8264-54a63350939d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42788
16841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4278816841
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2078006646
Short name T1180
Test name
Test status
Simulation time 225642918 ps
CPU time 0.98 seconds
Started Jul 12 05:27:05 PM PDT 24
Finished Jul 12 05:27:08 PM PDT 24
Peak memory 206712 kb
Host smart-de371e70-c355-4612-a683-c1265fa034cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20780
06646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2078006646
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1655814092
Short name T1261
Test name
Test status
Simulation time 150787046 ps
CPU time 0.76 seconds
Started Jul 12 05:27:07 PM PDT 24
Finished Jul 12 05:27:09 PM PDT 24
Peak memory 206816 kb
Host smart-6d39c589-4c15-4934-8729-6ead284b8629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16558
14092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1655814092
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3424203122
Short name T1065
Test name
Test status
Simulation time 228153105 ps
CPU time 0.91 seconds
Started Jul 12 05:27:03 PM PDT 24
Finished Jul 12 05:27:04 PM PDT 24
Peak memory 206816 kb
Host smart-9f97ed3d-ebca-46ad-b6f9-0f07090a1d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34242
03122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3424203122
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.4112245276
Short name T662
Test name
Test status
Simulation time 5236213773 ps
CPU time 150.17 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:29:37 PM PDT 24
Peak memory 206864 kb
Host smart-068eeaa9-fdeb-4947-b028-823dd9b9c82c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4112245276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.4112245276
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1553501347
Short name T1387
Test name
Test status
Simulation time 4412540383 ps
CPU time 38.91 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:27:48 PM PDT 24
Peak memory 207060 kb
Host smart-9166c559-9f14-4de5-99ca-9cb37cce61e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15535
01347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1553501347
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1861264762
Short name T1818
Test name
Test status
Simulation time 232427180 ps
CPU time 0.88 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:07 PM PDT 24
Peak memory 206812 kb
Host smart-d15b1c41-8d8c-41e0-b6b8-537c76a35196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18612
64762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1861264762
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.840933127
Short name T2733
Test name
Test status
Simulation time 23339466354 ps
CPU time 22.31 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206820 kb
Host smart-ac08d9ce-1feb-4ec8-ae48-c60ac651892d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84093
3127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.840933127
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3788021649
Short name T2447
Test name
Test status
Simulation time 3348181499 ps
CPU time 4.01 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:27:14 PM PDT 24
Peak memory 206904 kb
Host smart-99d710f1-f730-4550-905e-e3e9f0d6a6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37880
21649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3788021649
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.2897893924
Short name T1002
Test name
Test status
Simulation time 7594700436 ps
CPU time 55.37 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:28:04 PM PDT 24
Peak memory 207076 kb
Host smart-dc0e778e-f03a-478d-826c-35e9edd09420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28978
93924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.2897893924
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1374406569
Short name T2413
Test name
Test status
Simulation time 5118249658 ps
CPU time 37.88 seconds
Started Jul 12 05:27:15 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 207008 kb
Host smart-49a2a65d-1200-412c-b86b-eb7e83261d1b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1374406569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1374406569
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2199068092
Short name T1255
Test name
Test status
Simulation time 282873008 ps
CPU time 1 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:27:10 PM PDT 24
Peak memory 206688 kb
Host smart-9af80777-2e52-4644-be51-195d6a0c633d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2199068092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2199068092
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3483190567
Short name T2309
Test name
Test status
Simulation time 193875877 ps
CPU time 0.9 seconds
Started Jul 12 05:27:06 PM PDT 24
Finished Jul 12 05:27:08 PM PDT 24
Peak memory 206824 kb
Host smart-7dcf579b-acd7-4895-a4d1-7e0117430319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34831
90567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3483190567
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3988040834
Short name T1704
Test name
Test status
Simulation time 3245414280 ps
CPU time 81.84 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:28:31 PM PDT 24
Peak memory 206968 kb
Host smart-375a482b-3b4e-4582-a42f-3e1719c33e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39880
40834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3988040834
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.3195024652
Short name T146
Test name
Test status
Simulation time 5729001953 ps
CPU time 147.71 seconds
Started Jul 12 05:27:07 PM PDT 24
Finished Jul 12 05:29:36 PM PDT 24
Peak memory 207016 kb
Host smart-7eb71458-dfb7-4dc8-a716-fbc60e07a245
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3195024652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.3195024652
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1225696484
Short name T2275
Test name
Test status
Simulation time 163560628 ps
CPU time 0.78 seconds
Started Jul 12 05:27:12 PM PDT 24
Finished Jul 12 05:27:15 PM PDT 24
Peak memory 206772 kb
Host smart-7a505a07-42bc-46e0-aa59-aba6e9e45857
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1225696484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1225696484
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2046360639
Short name T1981
Test name
Test status
Simulation time 146125394 ps
CPU time 0.79 seconds
Started Jul 12 05:27:09 PM PDT 24
Finished Jul 12 05:27:11 PM PDT 24
Peak memory 206840 kb
Host smart-38bd7631-365a-4304-a061-5ffdf7c2b1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20463
60639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2046360639
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2555668153
Short name T139
Test name
Test status
Simulation time 217269697 ps
CPU time 0.84 seconds
Started Jul 12 05:27:06 PM PDT 24
Finished Jul 12 05:27:09 PM PDT 24
Peak memory 206820 kb
Host smart-aae2ceb5-8a60-4c1a-8e3c-6aa7d0b803f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25556
68153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2555668153
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2932998844
Short name T1707
Test name
Test status
Simulation time 186795703 ps
CPU time 0.83 seconds
Started Jul 12 05:27:05 PM PDT 24
Finished Jul 12 05:27:08 PM PDT 24
Peak memory 206804 kb
Host smart-13015892-5fcd-48f1-a27b-43960ea00ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29329
98844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2932998844
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1233860483
Short name T2550
Test name
Test status
Simulation time 148988296 ps
CPU time 0.79 seconds
Started Jul 12 05:27:06 PM PDT 24
Finished Jul 12 05:27:08 PM PDT 24
Peak memory 206824 kb
Host smart-42914b63-9354-4590-8572-b9fd41160512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12338
60483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1233860483
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2882548371
Short name T2308
Test name
Test status
Simulation time 172823916 ps
CPU time 0.84 seconds
Started Jul 12 05:27:13 PM PDT 24
Finished Jul 12 05:27:16 PM PDT 24
Peak memory 206816 kb
Host smart-4eb3fafc-fea2-4d33-972f-014014fc81e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825
48371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2882548371
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.759450501
Short name T1138
Test name
Test status
Simulation time 171245760 ps
CPU time 0.79 seconds
Started Jul 12 05:27:03 PM PDT 24
Finished Jul 12 05:27:04 PM PDT 24
Peak memory 206812 kb
Host smart-427cb13b-54b4-439d-b9f0-e6e29a82a077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75945
0501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.759450501
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1308224377
Short name T1018
Test name
Test status
Simulation time 210345376 ps
CPU time 0.9 seconds
Started Jul 12 05:27:14 PM PDT 24
Finished Jul 12 05:27:17 PM PDT 24
Peak memory 206820 kb
Host smart-4283e870-bd57-4769-a8b3-607bb7ca046a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1308224377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1308224377
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1883356074
Short name T2690
Test name
Test status
Simulation time 145427038 ps
CPU time 0.77 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:07 PM PDT 24
Peak memory 206804 kb
Host smart-654c9718-72ca-4b8b-b34d-4389c9565b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18833
56074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1883356074
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2495234873
Short name T24
Test name
Test status
Simulation time 60803591 ps
CPU time 0.71 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:27:10 PM PDT 24
Peak memory 206788 kb
Host smart-30869934-8081-400f-b310-8382dc793444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24952
34873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2495234873
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2698579570
Short name T87
Test name
Test status
Simulation time 19070016271 ps
CPU time 42.35 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:48 PM PDT 24
Peak memory 206932 kb
Host smart-16a0b473-7000-4732-8f9b-7b895be8d579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26985
79570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2698579570
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.562267023
Short name T1289
Test name
Test status
Simulation time 198631390 ps
CPU time 0.84 seconds
Started Jul 12 05:27:03 PM PDT 24
Finished Jul 12 05:27:05 PM PDT 24
Peak memory 206812 kb
Host smart-01b097aa-5ab4-43b3-8bba-2e375eabeb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56226
7023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.562267023
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3158434254
Short name T1783
Test name
Test status
Simulation time 163538836 ps
CPU time 0.84 seconds
Started Jul 12 05:27:15 PM PDT 24
Finished Jul 12 05:27:17 PM PDT 24
Peak memory 206820 kb
Host smart-6eba50c6-be13-410d-b0c0-566ba27b1629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31584
34254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3158434254
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2879353877
Short name T1145
Test name
Test status
Simulation time 13903216457 ps
CPU time 94.24 seconds
Started Jul 12 05:27:03 PM PDT 24
Finished Jul 12 05:28:38 PM PDT 24
Peak memory 207092 kb
Host smart-4752cf0d-bf5a-4d59-8af7-c150405a2118
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2879353877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2879353877
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.41097750
Short name T1195
Test name
Test status
Simulation time 197932429 ps
CPU time 0.85 seconds
Started Jul 12 05:27:04 PM PDT 24
Finished Jul 12 05:27:06 PM PDT 24
Peak memory 206720 kb
Host smart-417872bc-e5c3-41bf-a687-1232538d04c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41097
750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.41097750
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1067010414
Short name T758
Test name
Test status
Simulation time 178056730 ps
CPU time 0.84 seconds
Started Jul 12 05:27:15 PM PDT 24
Finished Jul 12 05:27:17 PM PDT 24
Peak memory 206820 kb
Host smart-d7d3af13-27fa-45a9-b885-019cac161293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10670
10414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1067010414
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2635159911
Short name T822
Test name
Test status
Simulation time 173248981 ps
CPU time 0.79 seconds
Started Jul 12 05:27:06 PM PDT 24
Finished Jul 12 05:27:09 PM PDT 24
Peak memory 206820 kb
Host smart-c22074bc-1323-4600-97e3-160799f4217f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26351
59911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2635159911
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2229602021
Short name T2705
Test name
Test status
Simulation time 154523949 ps
CPU time 0.78 seconds
Started Jul 12 05:27:05 PM PDT 24
Finished Jul 12 05:27:08 PM PDT 24
Peak memory 206632 kb
Host smart-bdb8c382-d3a0-42ef-8d7d-322d93e43d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22296
02021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2229602021
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3912281503
Short name T2079
Test name
Test status
Simulation time 173499277 ps
CPU time 0.78 seconds
Started Jul 12 05:27:11 PM PDT 24
Finished Jul 12 05:27:12 PM PDT 24
Peak memory 206792 kb
Host smart-b1d20bc8-f151-4389-83b4-0a8ff1b49d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39122
81503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3912281503
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.4266618458
Short name T980
Test name
Test status
Simulation time 261805890 ps
CPU time 1.02 seconds
Started Jul 12 05:27:15 PM PDT 24
Finished Jul 12 05:27:18 PM PDT 24
Peak memory 206812 kb
Host smart-2b94963b-c682-4a0d-a651-de5835439a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
18458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.4266618458
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.4167255897
Short name T1810
Test name
Test status
Simulation time 5038345496 ps
CPU time 52.09 seconds
Started Jul 12 05:27:08 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 206980 kb
Host smart-542625ef-0a78-4c97-9ec8-818a6c414dab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4167255897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.4167255897
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1356002212
Short name T529
Test name
Test status
Simulation time 187808843 ps
CPU time 0.85 seconds
Started Jul 12 05:27:12 PM PDT 24
Finished Jul 12 05:27:13 PM PDT 24
Peak memory 206800 kb
Host smart-ec5fa9a1-c9d9-42c6-a6d7-091035d064dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
02212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1356002212
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.506020761
Short name T399
Test name
Test status
Simulation time 168279550 ps
CPU time 0.8 seconds
Started Jul 12 05:27:15 PM PDT 24
Finished Jul 12 05:27:17 PM PDT 24
Peak memory 206820 kb
Host smart-8e98f3c9-d50f-42c2-bf96-5df4dbd7e2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50602
0761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.506020761
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.609727480
Short name T1379
Test name
Test status
Simulation time 531587292 ps
CPU time 1.43 seconds
Started Jul 12 05:27:20 PM PDT 24
Finished Jul 12 05:27:23 PM PDT 24
Peak memory 206840 kb
Host smart-45398832-3793-4630-830c-2a9691046b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60972
7480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.609727480
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2532756394
Short name T1625
Test name
Test status
Simulation time 4117152105 ps
CPU time 115.39 seconds
Started Jul 12 05:27:12 PM PDT 24
Finished Jul 12 05:29:09 PM PDT 24
Peak memory 207052 kb
Host smart-12c37921-b0d1-4443-8b14-2a58c3212c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25327
56394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2532756394
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1451350356
Short name T1532
Test name
Test status
Simulation time 54014125 ps
CPU time 0.7 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206636 kb
Host smart-75988db9-52dc-4ec4-a83b-13471e6cfa7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1451350356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1451350356
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2352712277
Short name T1515
Test name
Test status
Simulation time 4233563779 ps
CPU time 4.92 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:27:25 PM PDT 24
Peak memory 206860 kb
Host smart-26b98d0e-4cad-48c4-9661-e5f73926444d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2352712277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.2352712277
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3635651103
Short name T41
Test name
Test status
Simulation time 13324977251 ps
CPU time 12.27 seconds
Started Jul 12 05:27:12 PM PDT 24
Finished Jul 12 05:27:26 PM PDT 24
Peak memory 206852 kb
Host smart-64ade03a-84c7-4db4-8b97-b545e2da0c22
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3635651103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3635651103
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.827080631
Short name T12
Test name
Test status
Simulation time 23365057091 ps
CPU time 23.49 seconds
Started Jul 12 05:27:14 PM PDT 24
Finished Jul 12 05:27:39 PM PDT 24
Peak memory 206864 kb
Host smart-3967484b-45a4-412b-8afa-eb2441c19182
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=827080631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.827080631
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2696067214
Short name T2315
Test name
Test status
Simulation time 152410069 ps
CPU time 0.78 seconds
Started Jul 12 05:27:13 PM PDT 24
Finished Jul 12 05:27:15 PM PDT 24
Peak memory 206796 kb
Host smart-15c13f76-fa0f-458a-80bb-3d9cab605e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26960
67214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2696067214
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3708785218
Short name T761
Test name
Test status
Simulation time 163210728 ps
CPU time 0.81 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:27:21 PM PDT 24
Peak memory 206824 kb
Host smart-e31c3608-b1d6-482d-879e-199f8b24f7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37087
85218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3708785218
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.4178886800
Short name T105
Test name
Test status
Simulation time 325881295 ps
CPU time 1.12 seconds
Started Jul 12 05:27:13 PM PDT 24
Finished Jul 12 05:27:16 PM PDT 24
Peak memory 206980 kb
Host smart-80a685b0-2f4e-4a78-9134-57781acd5f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41788
86800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.4178886800
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.894193726
Short name T2597
Test name
Test status
Simulation time 800924332 ps
CPU time 1.93 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:27:21 PM PDT 24
Peak memory 206960 kb
Host smart-dbefbdc1-a119-4195-aeef-d47d9bc165c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89419
3726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.894193726
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.1027985840
Short name T2153
Test name
Test status
Simulation time 517783687 ps
CPU time 1.49 seconds
Started Jul 12 05:27:15 PM PDT 24
Finished Jul 12 05:27:18 PM PDT 24
Peak memory 206768 kb
Host smart-6a4a905d-d55a-4a0c-b6ec-4488b58d753b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10279
85840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.1027985840
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.4132182581
Short name T2461
Test name
Test status
Simulation time 159147678 ps
CPU time 0.76 seconds
Started Jul 12 05:27:19 PM PDT 24
Finished Jul 12 05:27:21 PM PDT 24
Peak memory 206820 kb
Host smart-e06b5f87-e501-447d-a0ae-bfb3519a30c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41321
82581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.4132182581
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1847698093
Short name T1133
Test name
Test status
Simulation time 43510905 ps
CPU time 0.67 seconds
Started Jul 12 05:27:14 PM PDT 24
Finished Jul 12 05:27:17 PM PDT 24
Peak memory 206976 kb
Host smart-c24991d6-29d1-4f06-bf8b-c711ceea1aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18476
98093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1847698093
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2578816824
Short name T2092
Test name
Test status
Simulation time 1006042462 ps
CPU time 2.09 seconds
Started Jul 12 05:27:15 PM PDT 24
Finished Jul 12 05:27:19 PM PDT 24
Peak memory 206968 kb
Host smart-d1954cd9-3f12-4cbb-9e4a-feab30637358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25788
16824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2578816824
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2907725066
Short name T1488
Test name
Test status
Simulation time 278395445 ps
CPU time 1.65 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 206960 kb
Host smart-cb0b61f0-8152-4e49-af06-3cff6a776cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29077
25066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2907725066
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.410629592
Short name T1660
Test name
Test status
Simulation time 263927776 ps
CPU time 0.96 seconds
Started Jul 12 05:27:13 PM PDT 24
Finished Jul 12 05:27:15 PM PDT 24
Peak memory 206828 kb
Host smart-8a1cfb6e-24e1-4212-af71-bcfacb545a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41062
9592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.410629592
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.635431577
Short name T2688
Test name
Test status
Simulation time 141380372 ps
CPU time 0.78 seconds
Started Jul 12 05:27:13 PM PDT 24
Finished Jul 12 05:27:15 PM PDT 24
Peak memory 206692 kb
Host smart-3cb865c8-802f-4eb7-af39-901d46dc1a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63543
1577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.635431577
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3173824733
Short name T1470
Test name
Test status
Simulation time 217291696 ps
CPU time 0.89 seconds
Started Jul 12 05:27:14 PM PDT 24
Finished Jul 12 05:27:17 PM PDT 24
Peak memory 206808 kb
Host smart-57c8382a-0e56-45da-bff8-130544ece058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31738
24733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3173824733
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3364119384
Short name T1199
Test name
Test status
Simulation time 180948684 ps
CPU time 0.82 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:27:21 PM PDT 24
Peak memory 206816 kb
Host smart-b01ad56d-9afb-4077-988e-fdbdf10ba445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
19384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3364119384
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.4227402558
Short name T1409
Test name
Test status
Simulation time 23340661200 ps
CPU time 22.05 seconds
Started Jul 12 05:27:20 PM PDT 24
Finished Jul 12 05:27:43 PM PDT 24
Peak memory 206760 kb
Host smart-eacb1d41-9de0-4633-b79b-6a03de158408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
02558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.4227402558
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.4087130945
Short name T2375
Test name
Test status
Simulation time 3295489008 ps
CPU time 4.56 seconds
Started Jul 12 05:27:21 PM PDT 24
Finished Jul 12 05:27:27 PM PDT 24
Peak memory 206884 kb
Host smart-079f0f20-ec98-44f4-9e32-66004c3d66c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40871
30945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.4087130945
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1793833552
Short name T1965
Test name
Test status
Simulation time 5914975587 ps
CPU time 41.87 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 207076 kb
Host smart-f499fe77-f8dc-4640-951a-a91e87fc4bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17938
33552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1793833552
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.4197221155
Short name T1692
Test name
Test status
Simulation time 6924730518 ps
CPU time 63.92 seconds
Started Jul 12 05:27:20 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 207016 kb
Host smart-3201b9ee-768a-4b10-9b47-a9854029e50a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4197221155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.4197221155
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.3585513979
Short name T1962
Test name
Test status
Simulation time 237169018 ps
CPU time 0.94 seconds
Started Jul 12 05:27:22 PM PDT 24
Finished Jul 12 05:27:24 PM PDT 24
Peak memory 206836 kb
Host smart-5bb0e173-af66-41f9-a421-bb01387573d4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3585513979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.3585513979
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3532151404
Short name T1702
Test name
Test status
Simulation time 201114516 ps
CPU time 0.94 seconds
Started Jul 12 05:27:26 PM PDT 24
Finished Jul 12 05:27:28 PM PDT 24
Peak memory 206824 kb
Host smart-99b1be98-634e-467c-a724-e5c80fe00857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35321
51404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3532151404
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.764798404
Short name T599
Test name
Test status
Simulation time 3694137725 ps
CPU time 25.64 seconds
Started Jul 12 05:27:17 PM PDT 24
Finished Jul 12 05:27:43 PM PDT 24
Peak memory 207072 kb
Host smart-c715a42d-118f-475c-bfdf-723172cf0248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76479
8404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.764798404
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3971038950
Short name T2113
Test name
Test status
Simulation time 5218171490 ps
CPU time 146.54 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:29:57 PM PDT 24
Peak memory 207056 kb
Host smart-1c1f2818-fe06-4e9b-8e4c-666c8df75c6d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3971038950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3971038950
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3477744125
Short name T1974
Test name
Test status
Simulation time 158888891 ps
CPU time 0.79 seconds
Started Jul 12 05:27:22 PM PDT 24
Finished Jul 12 05:27:24 PM PDT 24
Peak memory 206936 kb
Host smart-cb5bf0a8-12df-4152-b7a1-894a33b520bc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3477744125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3477744125
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1189434774
Short name T1876
Test name
Test status
Simulation time 211890267 ps
CPU time 0.82 seconds
Started Jul 12 05:27:20 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 206824 kb
Host smart-0581671a-382b-483e-b664-64726f0080b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11894
34774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1189434774
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3207639438
Short name T130
Test name
Test status
Simulation time 223424341 ps
CPU time 0.93 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:27:31 PM PDT 24
Peak memory 206816 kb
Host smart-49031937-b1d6-4905-8a10-5e84e50bcfcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32076
39438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3207639438
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.996935565
Short name T722
Test name
Test status
Simulation time 162611201 ps
CPU time 0.82 seconds
Started Jul 12 05:27:23 PM PDT 24
Finished Jul 12 05:27:24 PM PDT 24
Peak memory 206920 kb
Host smart-d92c7b83-6158-454e-a05d-15fb947e9f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99693
5565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.996935565
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.4049201830
Short name T455
Test name
Test status
Simulation time 175839487 ps
CPU time 0.87 seconds
Started Jul 12 05:27:17 PM PDT 24
Finished Jul 12 05:27:19 PM PDT 24
Peak memory 206700 kb
Host smart-5dcde99a-af38-45e0-a02e-d1217f35255c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40492
01830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.4049201830
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.949869810
Short name T348
Test name
Test status
Simulation time 200214904 ps
CPU time 0.84 seconds
Started Jul 12 05:27:21 PM PDT 24
Finished Jul 12 05:27:23 PM PDT 24
Peak memory 206808 kb
Host smart-aa2060e8-a1e8-4595-8c3b-a0baeb806490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94986
9810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.949869810
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2568150632
Short name T2048
Test name
Test status
Simulation time 155858509 ps
CPU time 0.8 seconds
Started Jul 12 05:27:20 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 206704 kb
Host smart-bc2169db-2973-4d5c-bffc-a6eaa93009c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25681
50632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2568150632
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.694402537
Short name T939
Test name
Test status
Simulation time 243555920 ps
CPU time 1.03 seconds
Started Jul 12 05:27:17 PM PDT 24
Finished Jul 12 05:27:19 PM PDT 24
Peak memory 206816 kb
Host smart-6657d1f6-1dad-49df-80c8-2cf02343fedd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=694402537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.694402537
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2619102373
Short name T925
Test name
Test status
Simulation time 164297087 ps
CPU time 0.78 seconds
Started Jul 12 05:27:17 PM PDT 24
Finished Jul 12 05:27:19 PM PDT 24
Peak memory 206800 kb
Host smart-bb4792d7-a66e-4010-9b91-18fd540731e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26191
02373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2619102373
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3652669328
Short name T25
Test name
Test status
Simulation time 76260140 ps
CPU time 0.72 seconds
Started Jul 12 05:27:20 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 206804 kb
Host smart-2348ab6b-49fd-4992-ad0b-02bc6fcc4e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36526
69328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3652669328
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2157247920
Short name T255
Test name
Test status
Simulation time 6758278997 ps
CPU time 14.13 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:27:34 PM PDT 24
Peak memory 207100 kb
Host smart-77c8f1ca-83d9-4024-92d8-dbdbad6a0d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21572
47920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2157247920
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3409357410
Short name T1369
Test name
Test status
Simulation time 216791266 ps
CPU time 0.87 seconds
Started Jul 12 05:27:20 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 206840 kb
Host smart-a7c89fb4-331e-48d7-b948-93a195dab561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34093
57410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3409357410
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.4122582400
Short name T2244
Test name
Test status
Simulation time 192874705 ps
CPU time 0.84 seconds
Started Jul 12 05:27:19 PM PDT 24
Finished Jul 12 05:27:21 PM PDT 24
Peak memory 206804 kb
Host smart-4940a625-baae-479d-b090-aff78b2d8c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41225
82400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.4122582400
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.430395649
Short name T2149
Test name
Test status
Simulation time 13491770177 ps
CPU time 88.62 seconds
Started Jul 12 05:27:19 PM PDT 24
Finished Jul 12 05:28:49 PM PDT 24
Peak memory 207032 kb
Host smart-95f9fcd0-d7a3-442a-8ae2-277f71149337
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=430395649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.430395649
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1653085265
Short name T664
Test name
Test status
Simulation time 16507963195 ps
CPU time 366.37 seconds
Started Jul 12 05:27:22 PM PDT 24
Finished Jul 12 05:33:29 PM PDT 24
Peak memory 207188 kb
Host smart-06fdd88f-48f3-4aab-b334-fa0e8860e18d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1653085265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1653085265
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1838808111
Short name T1690
Test name
Test status
Simulation time 198470324 ps
CPU time 0.91 seconds
Started Jul 12 05:27:22 PM PDT 24
Finished Jul 12 05:27:24 PM PDT 24
Peak memory 206812 kb
Host smart-332a4d46-edc1-4511-b7e4-59dfd71debdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18388
08111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1838808111
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2214025529
Short name T609
Test name
Test status
Simulation time 215465862 ps
CPU time 0.92 seconds
Started Jul 12 05:27:24 PM PDT 24
Finished Jul 12 05:27:25 PM PDT 24
Peak memory 206808 kb
Host smart-8f7350a5-d241-42ae-bafe-c3f7980ca8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22140
25529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2214025529
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2986978126
Short name T765
Test name
Test status
Simulation time 181828720 ps
CPU time 0.84 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:27:20 PM PDT 24
Peak memory 206804 kb
Host smart-d93ed29b-0c2f-4973-9f18-081e56d04d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29869
78126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2986978126
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3915822362
Short name T1275
Test name
Test status
Simulation time 174865544 ps
CPU time 0.79 seconds
Started Jul 12 05:27:19 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 206812 kb
Host smart-745bc728-40b4-42c9-a4f8-1df978c7ff45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39158
22362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3915822362
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1771981263
Short name T1711
Test name
Test status
Simulation time 153293303 ps
CPU time 0.81 seconds
Started Jul 12 05:27:20 PM PDT 24
Finished Jul 12 05:27:22 PM PDT 24
Peak memory 206688 kb
Host smart-fd6d3418-9496-4c76-bf9d-7c51139892ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17719
81263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1771981263
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2599822218
Short name T2405
Test name
Test status
Simulation time 260421540 ps
CPU time 0.95 seconds
Started Jul 12 05:27:25 PM PDT 24
Finished Jul 12 05:27:27 PM PDT 24
Peak memory 206816 kb
Host smart-f8f8dc41-7677-495d-bad5-6e6aa574a81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25998
22218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2599822218
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3407269017
Short name T530
Test name
Test status
Simulation time 5023432961 ps
CPU time 37.63 seconds
Started Jul 12 05:27:19 PM PDT 24
Finished Jul 12 05:27:59 PM PDT 24
Peak memory 207088 kb
Host smart-b7a19f5d-a835-426f-a5d1-4412c67d6730
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3407269017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3407269017
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.757044883
Short name T1252
Test name
Test status
Simulation time 173790944 ps
CPU time 0.79 seconds
Started Jul 12 05:27:18 PM PDT 24
Finished Jul 12 05:27:20 PM PDT 24
Peak memory 206808 kb
Host smart-a89e3d4c-9de9-41e5-885b-8e3c476e5b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75704
4883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.757044883
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1970725311
Short name T431
Test name
Test status
Simulation time 182553742 ps
CPU time 0.82 seconds
Started Jul 12 05:27:27 PM PDT 24
Finished Jul 12 05:27:29 PM PDT 24
Peak memory 206768 kb
Host smart-a1a61d44-2b8c-47ea-943e-14fff190c7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
25311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1970725311
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.242037052
Short name T1264
Test name
Test status
Simulation time 844839695 ps
CPU time 1.89 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:34 PM PDT 24
Peak memory 206868 kb
Host smart-53f26001-0b00-4bdc-8371-c41c26567e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
7052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.242037052
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3998732407
Short name T823
Test name
Test status
Simulation time 5876408804 ps
CPU time 39.78 seconds
Started Jul 12 05:27:26 PM PDT 24
Finished Jul 12 05:28:07 PM PDT 24
Peak memory 206932 kb
Host smart-74d8c45d-953d-4435-a74a-6907ac6ca5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39987
32407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3998732407
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2312948150
Short name T1228
Test name
Test status
Simulation time 43407996 ps
CPU time 0.7 seconds
Started Jul 12 05:27:35 PM PDT 24
Finished Jul 12 05:27:38 PM PDT 24
Peak memory 206844 kb
Host smart-6091e179-4b8f-4bb8-ba52-8eea9e821eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2312948150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2312948150
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3691898058
Short name T1599
Test name
Test status
Simulation time 3731302345 ps
CPU time 4.23 seconds
Started Jul 12 05:27:27 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 207004 kb
Host smart-f7ff280f-4bc4-43a3-95d9-c2badb50f59c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3691898058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.3691898058
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.725184271
Short name T1418
Test name
Test status
Simulation time 13351451580 ps
CPU time 11.54 seconds
Started Jul 12 05:27:26 PM PDT 24
Finished Jul 12 05:27:38 PM PDT 24
Peak memory 207040 kb
Host smart-5bcfc3b3-91d5-4829-9f8d-9dbab15cbe3a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=725184271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.725184271
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.965275099
Short name T653
Test name
Test status
Simulation time 23364004746 ps
CPU time 22.11 seconds
Started Jul 12 06:23:27 PM PDT 24
Finished Jul 12 06:23:50 PM PDT 24
Peak memory 206840 kb
Host smart-a3455eaa-8c75-40e2-ba91-bd091b9e98cc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=965275099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.965275099
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.405270956
Short name T2114
Test name
Test status
Simulation time 167879326 ps
CPU time 0.81 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:27:33 PM PDT 24
Peak memory 206812 kb
Host smart-612f51f5-13df-467a-9aa7-d66c1863fc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40527
0956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.405270956
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3597788884
Short name T539
Test name
Test status
Simulation time 152689510 ps
CPU time 0.77 seconds
Started Jul 12 05:27:32 PM PDT 24
Finished Jul 12 05:27:35 PM PDT 24
Peak memory 206824 kb
Host smart-4b12abd1-514f-43bd-a84a-b0f33a3cd71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35977
88884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3597788884
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3725865068
Short name T1550
Test name
Test status
Simulation time 241138251 ps
CPU time 0.92 seconds
Started Jul 12 05:27:26 PM PDT 24
Finished Jul 12 05:27:28 PM PDT 24
Peak memory 206712 kb
Host smart-65b5b63e-5b6c-413e-8dd0-4fc55313f8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
65068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3725865068
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2513396415
Short name T1802
Test name
Test status
Simulation time 782799049 ps
CPU time 2.18 seconds
Started Jul 12 05:27:32 PM PDT 24
Finished Jul 12 05:27:37 PM PDT 24
Peak memory 206964 kb
Host smart-c272b70c-b15e-47e7-820b-a4061858214d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25133
96415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2513396415
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.787781309
Short name T1682
Test name
Test status
Simulation time 6322544995 ps
CPU time 11.19 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:42 PM PDT 24
Peak memory 206944 kb
Host smart-22071d7d-a29e-49a7-ae38-7a5256cfabf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78778
1309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.787781309
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.258863959
Short name T2317
Test name
Test status
Simulation time 460223514 ps
CPU time 1.42 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:27:34 PM PDT 24
Peak memory 206820 kb
Host smart-81b6b9c5-8122-41c8-80d2-68145353c352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25886
3959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.258863959
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2001530316
Short name T1371
Test name
Test status
Simulation time 139645127 ps
CPU time 0.73 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:27:31 PM PDT 24
Peak memory 206720 kb
Host smart-f97f4445-f3c7-456a-ac05-87dee90b73cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20015
30316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2001530316
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3767776581
Short name T1006
Test name
Test status
Simulation time 37300790 ps
CPU time 0.63 seconds
Started Jul 12 05:27:25 PM PDT 24
Finished Jul 12 05:27:26 PM PDT 24
Peak memory 206696 kb
Host smart-15237aa9-bc75-4fd4-a266-d52ce613930a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37677
76581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3767776581
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1724590170
Short name T2587
Test name
Test status
Simulation time 976699134 ps
CPU time 2.18 seconds
Started Jul 12 05:27:32 PM PDT 24
Finished Jul 12 05:27:36 PM PDT 24
Peak memory 206896 kb
Host smart-bfc7fbdc-acf2-4016-8eb9-1e6d9e6d5160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
90170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1724590170
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3844826625
Short name T1735
Test name
Test status
Simulation time 297235395 ps
CPU time 2.17 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206840 kb
Host smart-de86aad2-d4f7-4e36-a3dc-d0108757336a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38448
26625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3844826625
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.164287292
Short name T1007
Test name
Test status
Simulation time 195520497 ps
CPU time 0.91 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:27:34 PM PDT 24
Peak memory 206812 kb
Host smart-1211f0ce-dccd-4a31-9a67-0f03a3f803d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16428
7292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.164287292
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.733681687
Short name T2207
Test name
Test status
Simulation time 136644434 ps
CPU time 0.76 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206792 kb
Host smart-d667e06e-c4ea-43b5-84d7-8a196988b4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73368
1687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.733681687
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.945248049
Short name T387
Test name
Test status
Simulation time 294955531 ps
CPU time 0.95 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:33 PM PDT 24
Peak memory 206920 kb
Host smart-d3849c60-14cb-4d07-89f1-d7723550dfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94524
8049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.945248049
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1148659126
Short name T620
Test name
Test status
Simulation time 7377334619 ps
CPU time 53.41 seconds
Started Jul 12 05:27:25 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 207072 kb
Host smart-9030c002-4abf-49ec-81ff-608799fdc241
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1148659126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1148659126
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.1674727327
Short name T1997
Test name
Test status
Simulation time 11987581956 ps
CPU time 45.09 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:28:17 PM PDT 24
Peak memory 207028 kb
Host smart-a6d14b8c-be30-4673-877e-5257d9c8b885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16747
27327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.1674727327
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1560185346
Short name T2160
Test name
Test status
Simulation time 206488261 ps
CPU time 0.86 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:27:31 PM PDT 24
Peak memory 206828 kb
Host smart-9896c218-a194-41e5-a85e-71c6b53f70ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15601
85346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1560185346
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2395626656
Short name T2318
Test name
Test status
Simulation time 23288825041 ps
CPU time 27.18 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:58 PM PDT 24
Peak memory 206868 kb
Host smart-b7030612-c8ae-4b38-802a-e422c189026c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23956
26656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2395626656
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2330866029
Short name T1986
Test name
Test status
Simulation time 3254995705 ps
CPU time 4.33 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:36 PM PDT 24
Peak memory 206888 kb
Host smart-4046b2df-e347-4d63-90a1-8ea9ce01e2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23308
66029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2330866029
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.979830400
Short name T2323
Test name
Test status
Simulation time 13321268504 ps
CPU time 358.92 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:33:29 PM PDT 24
Peak memory 207108 kb
Host smart-dba309e3-610b-4b90-a909-aeee3cb40e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97983
0400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.979830400
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3056295358
Short name T972
Test name
Test status
Simulation time 4605065667 ps
CPU time 31.26 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 207004 kb
Host smart-7f7f8f29-c012-46ba-91ca-5a1ffdba5690
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3056295358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3056295358
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2727885096
Short name T1085
Test name
Test status
Simulation time 262237205 ps
CPU time 1.02 seconds
Started Jul 12 05:27:26 PM PDT 24
Finished Jul 12 05:27:28 PM PDT 24
Peak memory 206820 kb
Host smart-169614a8-b5bc-4efa-8f86-b80d105390e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2727885096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2727885096
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.700423515
Short name T1103
Test name
Test status
Simulation time 185400089 ps
CPU time 0.9 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206832 kb
Host smart-7e000bb2-0a5a-4253-966f-bb88b05be258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70042
3515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.700423515
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1189452992
Short name T379
Test name
Test status
Simulation time 6406100388 ps
CPU time 47.82 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:28:21 PM PDT 24
Peak memory 207028 kb
Host smart-b438fa65-183e-48db-b844-50d410e5c37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11894
52992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1189452992
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1058330324
Short name T2042
Test name
Test status
Simulation time 4921814261 ps
CPU time 46.95 seconds
Started Jul 12 05:27:27 PM PDT 24
Finished Jul 12 05:28:15 PM PDT 24
Peak memory 207024 kb
Host smart-2b16d7ec-7b24-4911-ab80-40a531c2d17f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1058330324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1058330324
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2787769744
Short name T1902
Test name
Test status
Simulation time 181082873 ps
CPU time 0.82 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:27:34 PM PDT 24
Peak memory 206692 kb
Host smart-ce139c92-b0ee-4b1a-8e03-1056925da31b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2787769744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2787769744
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.158193858
Short name T453
Test name
Test status
Simulation time 149289500 ps
CPU time 0.78 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206828 kb
Host smart-d0eec83e-5d71-4567-8d98-90ba338ba231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15819
3858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.158193858
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3923821127
Short name T132
Test name
Test status
Simulation time 198772839 ps
CPU time 0.86 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:27:31 PM PDT 24
Peak memory 206820 kb
Host smart-e74ffa0c-0bd1-4875-b289-fa57928fd760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39238
21127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3923821127
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2962146721
Short name T2046
Test name
Test status
Simulation time 244338537 ps
CPU time 1.02 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:27:31 PM PDT 24
Peak memory 206800 kb
Host smart-59cb745e-22da-4bdf-b414-dafd71408f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29621
46721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2962146721
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2691934851
Short name T1635
Test name
Test status
Simulation time 164326983 ps
CPU time 0.77 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:27:34 PM PDT 24
Peak memory 206804 kb
Host smart-af8626ab-7774-436e-b503-f432810acf68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26919
34851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2691934851
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.4047702574
Short name T1851
Test name
Test status
Simulation time 184920478 ps
CPU time 0.84 seconds
Started Jul 12 05:27:33 PM PDT 24
Finished Jul 12 05:27:36 PM PDT 24
Peak memory 206820 kb
Host smart-595b79d7-6aa1-44fc-8208-6e08e65d6df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40477
02574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.4047702574
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.799616043
Short name T1657
Test name
Test status
Simulation time 158320653 ps
CPU time 0.76 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206692 kb
Host smart-80bea1ec-8813-4729-a2f2-f3d0904971e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79961
6043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.799616043
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.279957834
Short name T625
Test name
Test status
Simulation time 225501193 ps
CPU time 0.94 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:27:31 PM PDT 24
Peak memory 206816 kb
Host smart-92e62b52-242e-476d-8576-c116af9ce8c0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=279957834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.279957834
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2748232223
Short name T1357
Test name
Test status
Simulation time 157803329 ps
CPU time 0.79 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:27:30 PM PDT 24
Peak memory 206812 kb
Host smart-ec1746d9-5b24-4978-9a31-8d1ff9459c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27482
32223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2748232223
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2850863398
Short name T2602
Test name
Test status
Simulation time 27510651 ps
CPU time 0.65 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:33 PM PDT 24
Peak memory 206832 kb
Host smart-fb12e5ac-350a-47f1-baf8-a4ce0af2f728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28508
63398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2850863398
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3226826283
Short name T1315
Test name
Test status
Simulation time 10040437190 ps
CPU time 20.38 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:52 PM PDT 24
Peak memory 206908 kb
Host smart-3cb8bb03-4af9-4dfb-9779-6f2eda0022b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32268
26283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3226826283
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1157420553
Short name T1208
Test name
Test status
Simulation time 152858246 ps
CPU time 0.79 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:27:33 PM PDT 24
Peak memory 206820 kb
Host smart-89bef7ce-d5db-4285-9a7c-d2bb90200bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11574
20553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1157420553
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.137817684
Short name T485
Test name
Test status
Simulation time 216411141 ps
CPU time 0.85 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206788 kb
Host smart-39a0b193-320c-4032-9d9c-f7be303e1880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13781
7684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.137817684
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.4151355102
Short name T1338
Test name
Test status
Simulation time 11086916223 ps
CPU time 218.6 seconds
Started Jul 12 05:27:27 PM PDT 24
Finished Jul 12 05:31:07 PM PDT 24
Peak memory 206996 kb
Host smart-d638425e-ae32-4bc4-af76-9fd89d052b8e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4151355102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.4151355102
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1682632036
Short name T1605
Test name
Test status
Simulation time 11415739606 ps
CPU time 73.8 seconds
Started Jul 12 05:27:28 PM PDT 24
Finished Jul 12 05:28:44 PM PDT 24
Peak memory 206988 kb
Host smart-7adf613b-ed10-48a4-ae45-caf12f40430b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1682632036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1682632036
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1381421575
Short name T1491
Test name
Test status
Simulation time 7432455799 ps
CPU time 108.49 seconds
Started Jul 12 05:27:26 PM PDT 24
Finished Jul 12 05:29:16 PM PDT 24
Peak memory 206988 kb
Host smart-6a4c55b8-74e4-4b5b-9f73-505a6c6c2ba5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1381421575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1381421575
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.2216662988
Short name T2610
Test name
Test status
Simulation time 213317865 ps
CPU time 0.92 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:33 PM PDT 24
Peak memory 206616 kb
Host smart-095b39a5-1a17-4428-8682-54d3cdd26603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22166
62988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2216662988
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2886339088
Short name T2493
Test name
Test status
Simulation time 190119179 ps
CPU time 0.9 seconds
Started Jul 12 05:27:29 PM PDT 24
Finished Jul 12 05:27:32 PM PDT 24
Peak memory 206820 kb
Host smart-efc019bc-a251-49e7-8f13-cbc76ec3ff19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28863
39088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2886339088
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3502690410
Short name T2100
Test name
Test status
Simulation time 214870708 ps
CPU time 0.81 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:27:33 PM PDT 24
Peak memory 206820 kb
Host smart-8dd157df-1ebd-46d6-9fc1-84217c90659e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35026
90410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3502690410
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3565227944
Short name T1284
Test name
Test status
Simulation time 173305416 ps
CPU time 0.83 seconds
Started Jul 12 05:27:36 PM PDT 24
Finished Jul 12 05:27:39 PM PDT 24
Peak memory 206800 kb
Host smart-1e6f9ffe-94f6-47a0-b5b9-563151d1b17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35652
27944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3565227944
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.491732279
Short name T918
Test name
Test status
Simulation time 155040793 ps
CPU time 0.82 seconds
Started Jul 12 05:27:31 PM PDT 24
Finished Jul 12 05:27:35 PM PDT 24
Peak memory 206812 kb
Host smart-5d203f73-659c-45a4-8e6a-dafc3be69217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49173
2279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.491732279
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2442915947
Short name T869
Test name
Test status
Simulation time 219028234 ps
CPU time 0.98 seconds
Started Jul 12 05:27:37 PM PDT 24
Finished Jul 12 05:27:40 PM PDT 24
Peak memory 206804 kb
Host smart-2125faf2-5608-44cb-b382-d92055051c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24429
15947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2442915947
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2699618920
Short name T165
Test name
Test status
Simulation time 6206439402 ps
CPU time 171.06 seconds
Started Jul 12 05:27:37 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 207016 kb
Host smart-7fa795bb-f6ec-463c-9622-745deb0faec7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2699618920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2699618920
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1896590962
Short name T1706
Test name
Test status
Simulation time 162903836 ps
CPU time 0.79 seconds
Started Jul 12 05:27:34 PM PDT 24
Finished Jul 12 05:27:38 PM PDT 24
Peak memory 206792 kb
Host smart-af08ca8d-299d-4c6d-b3ea-0af546966315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18965
90962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1896590962
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.4277728059
Short name T2563
Test name
Test status
Simulation time 146421079 ps
CPU time 0.79 seconds
Started Jul 12 05:27:32 PM PDT 24
Finished Jul 12 05:27:36 PM PDT 24
Peak memory 206788 kb
Host smart-43447b15-04cf-4366-98fe-e1ee95c685f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42777
28059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4277728059
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2094210631
Short name T311
Test name
Test status
Simulation time 1236735817 ps
CPU time 2.59 seconds
Started Jul 12 05:27:32 PM PDT 24
Finished Jul 12 05:27:38 PM PDT 24
Peak memory 206992 kb
Host smart-b44a5f1f-3fa9-4125-9f68-ac0ae386fee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20942
10631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2094210631
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2044357634
Short name T390
Test name
Test status
Simulation time 7281365821 ps
CPU time 68.9 seconds
Started Jul 12 05:27:37 PM PDT 24
Finished Jul 12 05:28:48 PM PDT 24
Peak memory 207084 kb
Host smart-920da3ac-b1e0-4c3f-9bc7-35160e6e8fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
57634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2044357634
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2834103108
Short name T608
Test name
Test status
Simulation time 67625567 ps
CPU time 0.73 seconds
Started Jul 12 05:27:40 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 206844 kb
Host smart-9963bbb3-37ff-4e33-adab-1d706dc703f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2834103108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2834103108
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.4078766154
Short name T2125
Test name
Test status
Simulation time 3457581354 ps
CPU time 4.26 seconds
Started Jul 12 05:27:34 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 206812 kb
Host smart-84cef074-0521-4663-b37e-8417496ea716
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4078766154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.4078766154
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1391003689
Short name T13
Test name
Test status
Simulation time 13346407230 ps
CPU time 15.78 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:28:06 PM PDT 24
Peak memory 206824 kb
Host smart-8f0db460-3134-45cc-a811-68e9c0b57786
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1391003689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1391003689
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2521846081
Short name T2612
Test name
Test status
Simulation time 23384365529 ps
CPU time 21.49 seconds
Started Jul 12 05:27:37 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 207080 kb
Host smart-3dadb6d6-bb2f-406a-ab8b-19beca93c967
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2521846081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2521846081
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.4250830196
Short name T1545
Test name
Test status
Simulation time 207387769 ps
CPU time 0.88 seconds
Started Jul 12 05:27:36 PM PDT 24
Finished Jul 12 05:27:39 PM PDT 24
Peak memory 206704 kb
Host smart-b80e6cbc-c745-48f5-bb66-41f6c99ac60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42508
30196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.4250830196
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1296264317
Short name T1700
Test name
Test status
Simulation time 141678694 ps
CPU time 0.71 seconds
Started Jul 12 05:27:30 PM PDT 24
Finished Jul 12 05:27:34 PM PDT 24
Peak memory 206828 kb
Host smart-c0839dd9-868c-4262-909f-82d4a8ea74c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12962
64317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1296264317
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.4156356401
Short name T1666
Test name
Test status
Simulation time 629038616 ps
CPU time 1.7 seconds
Started Jul 12 05:27:33 PM PDT 24
Finished Jul 12 05:27:37 PM PDT 24
Peak memory 207008 kb
Host smart-b4e8fbb7-e12b-4be9-b0d6-b62e83a80a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41563
56401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.4156356401
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.870188304
Short name T840
Test name
Test status
Simulation time 1032919731 ps
CPU time 2.43 seconds
Started Jul 12 05:27:36 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 206968 kb
Host smart-a07d1141-1e58-4ff7-9abc-b12549e95348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87018
8304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.870188304
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2073358982
Short name T152
Test name
Test status
Simulation time 9983184102 ps
CPU time 22 seconds
Started Jul 12 05:27:34 PM PDT 24
Finished Jul 12 05:27:58 PM PDT 24
Peak memory 207076 kb
Host smart-1baa1f67-e680-4042-b936-14859a77eec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20733
58982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2073358982
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2311714439
Short name T1399
Test name
Test status
Simulation time 410730816 ps
CPU time 1.21 seconds
Started Jul 12 05:27:33 PM PDT 24
Finished Jul 12 05:27:37 PM PDT 24
Peak memory 206724 kb
Host smart-68c8d80d-3d00-4e8f-98da-0b60cf7e30e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23117
14439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2311714439
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2677710675
Short name T492
Test name
Test status
Simulation time 148017994 ps
CPU time 0.77 seconds
Started Jul 12 05:27:34 PM PDT 24
Finished Jul 12 05:27:37 PM PDT 24
Peak memory 206808 kb
Host smart-dcd8af1d-7de2-4892-9139-48f363d853f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26777
10675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2677710675
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2377390154
Short name T2045
Test name
Test status
Simulation time 45167428 ps
CPU time 0.68 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:27:51 PM PDT 24
Peak memory 206784 kb
Host smart-bc79fa26-c19d-428e-9906-c24d27e1df4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23773
90154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2377390154
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.46989668
Short name T1253
Test name
Test status
Simulation time 963583919 ps
CPU time 2.17 seconds
Started Jul 12 05:27:34 PM PDT 24
Finished Jul 12 05:27:39 PM PDT 24
Peak memory 206960 kb
Host smart-61d3fd7f-e8bc-43e4-8d11-d54741e1ebca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46989
668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.46989668
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1207043138
Short name T1963
Test name
Test status
Simulation time 189935915 ps
CPU time 2.03 seconds
Started Jul 12 05:27:37 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 207008 kb
Host smart-146aa795-d62f-400b-b693-fdc4d6549bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12070
43138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1207043138
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3664553474
Short name T2406
Test name
Test status
Simulation time 187604264 ps
CPU time 0.85 seconds
Started Jul 12 05:27:32 PM PDT 24
Finished Jul 12 05:27:36 PM PDT 24
Peak memory 206680 kb
Host smart-c8c7bed6-305c-4176-be86-1765123be06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36645
53474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3664553474
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3260535061
Short name T741
Test name
Test status
Simulation time 155638395 ps
CPU time 0.76 seconds
Started Jul 12 05:27:34 PM PDT 24
Finished Jul 12 05:27:37 PM PDT 24
Peak memory 206808 kb
Host smart-6f26ffb9-6e39-471d-9e46-2252237b0c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32605
35061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3260535061
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.422979540
Short name T1242
Test name
Test status
Simulation time 159728267 ps
CPU time 0.79 seconds
Started Jul 12 05:27:35 PM PDT 24
Finished Jul 12 05:27:38 PM PDT 24
Peak memory 206676 kb
Host smart-9934d053-afc7-4e63-acd8-64444840a5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42297
9540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.422979540
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.1968308019
Short name T37
Test name
Test status
Simulation time 11117938273 ps
CPU time 41.45 seconds
Started Jul 12 05:27:36 PM PDT 24
Finished Jul 12 05:28:19 PM PDT 24
Peak memory 207088 kb
Host smart-03e955ea-147b-4751-a96a-b4c1bc261be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19683
08019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.1968308019
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.707412087
Short name T1
Test name
Test status
Simulation time 253502116 ps
CPU time 0.9 seconds
Started Jul 12 05:27:34 PM PDT 24
Finished Jul 12 05:27:37 PM PDT 24
Peak memory 206808 kb
Host smart-c55950bc-1b6d-4fc2-8cc0-a410300f0d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70741
2087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.707412087
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.306826522
Short name T1841
Test name
Test status
Simulation time 23307737833 ps
CPU time 22.94 seconds
Started Jul 12 05:27:33 PM PDT 24
Finished Jul 12 05:27:59 PM PDT 24
Peak memory 206876 kb
Host smart-18b3c16d-9cdc-4392-b489-99df9b2d15b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30682
6522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.306826522
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3959202933
Short name T511
Test name
Test status
Simulation time 3297566059 ps
CPU time 3.89 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:27:54 PM PDT 24
Peak memory 206732 kb
Host smart-2873f1e7-0a40-483f-b38c-f9256ad9f375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39592
02933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3959202933
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2301701951
Short name T1239
Test name
Test status
Simulation time 6276219584 ps
CPU time 166.98 seconds
Started Jul 12 05:27:35 PM PDT 24
Finished Jul 12 05:30:24 PM PDT 24
Peak memory 207120 kb
Host smart-99b30477-80b3-400f-bad0-36f49b0dad54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23017
01951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2301701951
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.3901375837
Short name T328
Test name
Test status
Simulation time 3670281524 ps
CPU time 27.98 seconds
Started Jul 12 05:27:35 PM PDT 24
Finished Jul 12 05:28:05 PM PDT 24
Peak memory 207032 kb
Host smart-474cc7ad-1bf7-4701-8335-da79bcb922b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3901375837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.3901375837
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1984026358
Short name T1328
Test name
Test status
Simulation time 242732017 ps
CPU time 0.91 seconds
Started Jul 12 05:27:35 PM PDT 24
Finished Jul 12 05:27:38 PM PDT 24
Peak memory 206808 kb
Host smart-4d85ab76-4888-488c-9b70-8c7379ffa279
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1984026358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1984026358
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.591995471
Short name T2680
Test name
Test status
Simulation time 196364284 ps
CPU time 0.95 seconds
Started Jul 12 05:27:36 PM PDT 24
Finished Jul 12 05:27:40 PM PDT 24
Peak memory 206692 kb
Host smart-8369586c-a0ab-49b8-968c-e86d04bb9a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59199
5471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.591995471
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.146244782
Short name T1985
Test name
Test status
Simulation time 6591010540 ps
CPU time 62.27 seconds
Started Jul 12 05:27:47 PM PDT 24
Finished Jul 12 05:28:51 PM PDT 24
Peak memory 207024 kb
Host smart-c15e1747-981e-43b4-8d01-66a9053d4953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14624
4782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.146244782
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1750214453
Short name T2142
Test name
Test status
Simulation time 5627008050 ps
CPU time 155.86 seconds
Started Jul 12 05:27:32 PM PDT 24
Finished Jul 12 05:30:11 PM PDT 24
Peak memory 207036 kb
Host smart-d14bc802-d8e6-4406-9d1c-3ad3fd17ed04
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1750214453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1750214453
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1651247198
Short name T1926
Test name
Test status
Simulation time 175425081 ps
CPU time 0.81 seconds
Started Jul 12 05:27:36 PM PDT 24
Finished Jul 12 05:27:39 PM PDT 24
Peak memory 206688 kb
Host smart-3e2506bf-6e29-4d17-ab95-ce2165940dd3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1651247198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1651247198
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.125041146
Short name T2143
Test name
Test status
Simulation time 142977451 ps
CPU time 0.76 seconds
Started Jul 12 05:27:36 PM PDT 24
Finished Jul 12 05:27:39 PM PDT 24
Peak memory 206824 kb
Host smart-97ca6c13-4fe4-4663-9eb1-5bfc432deaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12504
1146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.125041146
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3659817575
Short name T2438
Test name
Test status
Simulation time 247644480 ps
CPU time 0.86 seconds
Started Jul 12 05:27:34 PM PDT 24
Finished Jul 12 05:27:38 PM PDT 24
Peak memory 206800 kb
Host smart-1a29fa47-a29d-4018-945a-6bebd7315456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36598
17575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3659817575
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.3310326488
Short name T95
Test name
Test status
Simulation time 173730353 ps
CPU time 0.86 seconds
Started Jul 12 05:27:44 PM PDT 24
Finished Jul 12 05:27:46 PM PDT 24
Peak memory 206820 kb
Host smart-f0b55158-75d7-4c5c-9db1-fbabd173c08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33103
26488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3310326488
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.25448087
Short name T2526
Test name
Test status
Simulation time 173616513 ps
CPU time 0.83 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:27:51 PM PDT 24
Peak memory 206700 kb
Host smart-63707e78-8a58-4b42-8d9b-7e1913bb5d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25448
087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.25448087
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1686908071
Short name T2053
Test name
Test status
Simulation time 239410661 ps
CPU time 0.86 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:27:51 PM PDT 24
Peak memory 206800 kb
Host smart-f62da2ed-24d7-49e7-99b1-978e7f88abd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
08071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1686908071
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2548257254
Short name T1759
Test name
Test status
Simulation time 158912037 ps
CPU time 0.78 seconds
Started Jul 12 05:27:43 PM PDT 24
Finished Jul 12 05:27:45 PM PDT 24
Peak memory 206704 kb
Host smart-68998c0d-a286-4504-9b57-3dc52765a7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
57254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2548257254
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2084417983
Short name T208
Test name
Test status
Simulation time 178566561 ps
CPU time 0.81 seconds
Started Jul 12 05:27:47 PM PDT 24
Finished Jul 12 05:27:50 PM PDT 24
Peak memory 206832 kb
Host smart-038e69a5-bc57-49ef-90f8-9055a6dda034
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2084417983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2084417983
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3950282337
Short name T459
Test name
Test status
Simulation time 154782471 ps
CPU time 0.8 seconds
Started Jul 12 05:27:42 PM PDT 24
Finished Jul 12 05:27:44 PM PDT 24
Peak memory 206700 kb
Host smart-83308fe2-4af6-4d50-801f-0e49a93ea129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39502
82337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3950282337
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2266574
Short name T2429
Test name
Test status
Simulation time 49190856 ps
CPU time 0.67 seconds
Started Jul 12 05:27:41 PM PDT 24
Finished Jul 12 05:27:43 PM PDT 24
Peak memory 206748 kb
Host smart-652b3d1b-ab50-44ac-a3e4-dbafec57cf32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665
74 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2266574
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.919609702
Short name T2494
Test name
Test status
Simulation time 10682892628 ps
CPU time 24.77 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:28:14 PM PDT 24
Peak memory 207128 kb
Host smart-a1a6ffdb-ada1-42f4-96c8-e03a415620c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91960
9702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.919609702
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1294204002
Short name T2434
Test name
Test status
Simulation time 172230380 ps
CPU time 0.84 seconds
Started Jul 12 05:27:43 PM PDT 24
Finished Jul 12 05:27:45 PM PDT 24
Peak memory 206816 kb
Host smart-24f09783-144c-4070-90ee-45204c3fea3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12942
04002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1294204002
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2363508790
Short name T2126
Test name
Test status
Simulation time 204919217 ps
CPU time 0.88 seconds
Started Jul 12 05:27:39 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 206672 kb
Host smart-cd683a46-12f0-4e2a-8957-2a02d01753c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23635
08790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2363508790
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2847436223
Short name T180
Test name
Test status
Simulation time 9372687448 ps
CPU time 57.94 seconds
Started Jul 12 05:27:39 PM PDT 24
Finished Jul 12 05:28:38 PM PDT 24
Peak memory 206900 kb
Host smart-ba792ebb-9264-4512-a6cd-b85b2b77d14a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2847436223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2847436223
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1024104163
Short name T1955
Test name
Test status
Simulation time 12120864271 ps
CPU time 224.33 seconds
Started Jul 12 05:27:38 PM PDT 24
Finished Jul 12 05:31:24 PM PDT 24
Peak memory 207124 kb
Host smart-6515825f-d153-490e-8d71-edb0a7bc94f8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1024104163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1024104163
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2811569313
Short name T1847
Test name
Test status
Simulation time 11591270777 ps
CPU time 74.12 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:29:04 PM PDT 24
Peak memory 206980 kb
Host smart-8c90c9ea-c3c9-44f6-bf97-0b1440d27f26
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2811569313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2811569313
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2368418078
Short name T437
Test name
Test status
Simulation time 220274430 ps
CPU time 0.87 seconds
Started Jul 12 05:27:43 PM PDT 24
Finished Jul 12 05:27:44 PM PDT 24
Peak memory 206824 kb
Host smart-e49008a1-9d52-4016-be38-b14654affd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23684
18078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2368418078
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.543025027
Short name T1193
Test name
Test status
Simulation time 171704472 ps
CPU time 0.84 seconds
Started Jul 12 05:27:43 PM PDT 24
Finished Jul 12 05:27:45 PM PDT 24
Peak memory 206820 kb
Host smart-f91aa810-a335-4e5f-aea7-70289923d3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54302
5027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.543025027
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1063529120
Short name T428
Test name
Test status
Simulation time 144871697 ps
CPU time 0.75 seconds
Started Jul 12 05:27:38 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 206816 kb
Host smart-711628e7-111d-4bbc-9310-04dcc64382b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10635
29120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1063529120
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2900648278
Short name T439
Test name
Test status
Simulation time 155589323 ps
CPU time 0.82 seconds
Started Jul 12 05:27:40 PM PDT 24
Finished Jul 12 05:27:42 PM PDT 24
Peak memory 206808 kb
Host smart-7a14e5af-5b91-43e3-aadb-37a70282ceb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
48278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2900648278
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3754905080
Short name T1514
Test name
Test status
Simulation time 150335157 ps
CPU time 0.81 seconds
Started Jul 12 05:27:40 PM PDT 24
Finished Jul 12 05:27:42 PM PDT 24
Peak memory 206800 kb
Host smart-5def4d87-f999-41e9-95a2-cc0fe7dd0569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
05080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3754905080
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2444451078
Short name T595
Test name
Test status
Simulation time 247350853 ps
CPU time 0.95 seconds
Started Jul 12 05:27:43 PM PDT 24
Finished Jul 12 05:27:45 PM PDT 24
Peak memory 206816 kb
Host smart-f36f3d86-6f30-4c71-882f-d4cc2e68284b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24444
51078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2444451078
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1810171975
Short name T1809
Test name
Test status
Simulation time 3715454370 ps
CPU time 33.42 seconds
Started Jul 12 05:27:41 PM PDT 24
Finished Jul 12 05:28:16 PM PDT 24
Peak memory 207048 kb
Host smart-41ba7808-ec76-433b-8566-6974caf82e68
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1810171975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1810171975
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3570004959
Short name T1587
Test name
Test status
Simulation time 196066515 ps
CPU time 0.83 seconds
Started Jul 12 05:27:41 PM PDT 24
Finished Jul 12 05:27:43 PM PDT 24
Peak memory 206804 kb
Host smart-1338ba2c-2665-4f4f-a997-3e11e09214ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35700
04959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3570004959
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.760989606
Short name T923
Test name
Test status
Simulation time 205778705 ps
CPU time 0.81 seconds
Started Jul 12 05:27:47 PM PDT 24
Finished Jul 12 05:27:50 PM PDT 24
Peak memory 206824 kb
Host smart-099764ae-25df-4461-b951-b2862f974623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76098
9606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.760989606
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2319127667
Short name T1053
Test name
Test status
Simulation time 1188457629 ps
CPU time 2.41 seconds
Started Jul 12 05:27:41 PM PDT 24
Finished Jul 12 05:27:44 PM PDT 24
Peak memory 206896 kb
Host smart-2d63a0bd-3aa3-4650-a3b8-95b65005aafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
27667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2319127667
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2756338239
Short name T2616
Test name
Test status
Simulation time 4125653346 ps
CPU time 115.71 seconds
Started Jul 12 05:27:42 PM PDT 24
Finished Jul 12 05:29:39 PM PDT 24
Peak memory 206840 kb
Host smart-f519314a-e3e3-4ef5-8977-749b3ec9c6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
38239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2756338239
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.367184546
Short name T183
Test name
Test status
Simulation time 43644562 ps
CPU time 0.68 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:07 PM PDT 24
Peak memory 206848 kb
Host smart-e91b1ec0-f91d-43ce-a0ce-da4d60814a08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=367184546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.367184546
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.603555392
Short name T2334
Test name
Test status
Simulation time 3738240613 ps
CPU time 4.02 seconds
Started Jul 12 05:27:42 PM PDT 24
Finished Jul 12 05:27:47 PM PDT 24
Peak memory 207016 kb
Host smart-57b09a4c-8cc6-4395-8288-39aca9dfd5cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=603555392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.603555392
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.908996547
Short name T737
Test name
Test status
Simulation time 13359132828 ps
CPU time 13.55 seconds
Started Jul 12 05:27:47 PM PDT 24
Finished Jul 12 05:28:02 PM PDT 24
Peak memory 206868 kb
Host smart-43b8cbee-174a-45ff-b2d0-605ede8c4599
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=908996547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.908996547
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.4207372737
Short name T2615
Test name
Test status
Simulation time 23377636531 ps
CPU time 22.42 seconds
Started Jul 12 05:27:43 PM PDT 24
Finished Jul 12 05:28:06 PM PDT 24
Peak memory 206840 kb
Host smart-91e2a601-7339-4361-8fbb-37101df99e2f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4207372737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.4207372737
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1013950187
Short name T1786
Test name
Test status
Simulation time 175665934 ps
CPU time 0.81 seconds
Started Jul 12 05:27:40 PM PDT 24
Finished Jul 12 05:27:42 PM PDT 24
Peak memory 206720 kb
Host smart-eacbba13-8317-43f8-a765-aa79f8fa3af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139
50187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1013950187
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1938936919
Short name T57
Test name
Test status
Simulation time 152545318 ps
CPU time 0.74 seconds
Started Jul 12 05:27:38 PM PDT 24
Finished Jul 12 05:27:41 PM PDT 24
Peak memory 206824 kb
Host smart-ae5b450d-b018-49eb-98d1-aae5b2441e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19389
36919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1938936919
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.486997164
Short name T946
Test name
Test status
Simulation time 249046348 ps
CPU time 1.11 seconds
Started Jul 12 05:27:39 PM PDT 24
Finished Jul 12 05:27:42 PM PDT 24
Peak memory 206704 kb
Host smart-4f13bb11-6241-4255-9ba0-22ba7e20e0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48699
7164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.486997164
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3326859392
Short name T879
Test name
Test status
Simulation time 461139721 ps
CPU time 1.34 seconds
Started Jul 12 05:27:43 PM PDT 24
Finished Jul 12 05:27:45 PM PDT 24
Peak memory 206696 kb
Host smart-1a167883-f766-4d79-9453-4146c8c8576d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
59392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3326859392
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2052749717
Short name T2663
Test name
Test status
Simulation time 17587021138 ps
CPU time 31.86 seconds
Started Jul 12 05:27:42 PM PDT 24
Finished Jul 12 05:28:15 PM PDT 24
Peak memory 206984 kb
Host smart-86335b11-bb5e-4301-8c62-8ff5c57ef2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20527
49717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2052749717
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.4016385704
Short name T1701
Test name
Test status
Simulation time 418896664 ps
CPU time 1.33 seconds
Started Jul 12 05:27:51 PM PDT 24
Finished Jul 12 05:27:54 PM PDT 24
Peak memory 206720 kb
Host smart-c6ecdbbe-97a6-446f-99d5-1582a5ba9e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40163
85704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.4016385704
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.34415954
Short name T1537
Test name
Test status
Simulation time 179262847 ps
CPU time 0.78 seconds
Started Jul 12 05:27:51 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206816 kb
Host smart-2e0a23d2-a8a7-442d-9509-a9318ce230a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34415
954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.34415954
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1538660133
Short name T779
Test name
Test status
Simulation time 38931858 ps
CPU time 0.68 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:27:52 PM PDT 24
Peak memory 206708 kb
Host smart-701b212d-613b-43f9-b58f-4995618116f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15386
60133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1538660133
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.4107372547
Short name T714
Test name
Test status
Simulation time 797429133 ps
CPU time 1.85 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:27:54 PM PDT 24
Peak memory 206804 kb
Host smart-1cf71fcd-4390-4f98-b98c-afd55ac2fff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41073
72547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.4107372547
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3403158296
Short name T749
Test name
Test status
Simulation time 377242686 ps
CPU time 2.49 seconds
Started Jul 12 05:27:51 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 206952 kb
Host smart-8b52b849-2945-4034-a9c6-8ca7edcfe8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34031
58296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3403158296
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1012866961
Short name T1590
Test name
Test status
Simulation time 199469414 ps
CPU time 0.86 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206688 kb
Host smart-b1163758-5044-4037-98dc-a2f3ee5d8142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10128
66961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1012866961
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3653246999
Short name T2443
Test name
Test status
Simulation time 148346972 ps
CPU time 0.78 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206816 kb
Host smart-9163df8d-07f4-4053-b201-637885f99684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36532
46999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3653246999
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2495411313
Short name T2277
Test name
Test status
Simulation time 232035491 ps
CPU time 0.88 seconds
Started Jul 12 05:27:47 PM PDT 24
Finished Jul 12 05:27:48 PM PDT 24
Peak memory 206816 kb
Host smart-abc96ae8-0f07-41b6-b5c5-f7cf0cdcc1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24954
11313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2495411313
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.2173675857
Short name T897
Test name
Test status
Simulation time 11816392465 ps
CPU time 43.09 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:28:35 PM PDT 24
Peak memory 207036 kb
Host smart-915bbccc-3369-4866-a265-fe3c8e125db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21736
75857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.2173675857
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1345695940
Short name T829
Test name
Test status
Simulation time 194688647 ps
CPU time 0.86 seconds
Started Jul 12 05:27:52 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 206808 kb
Host smart-bd25a6ab-d158-4de5-afb9-0dd876637835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13456
95940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1345695940
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.455862637
Short name T2652
Test name
Test status
Simulation time 23304355550 ps
CPU time 21.18 seconds
Started Jul 12 05:27:49 PM PDT 24
Finished Jul 12 05:28:12 PM PDT 24
Peak memory 206880 kb
Host smart-9315e9c9-feb7-4a37-828b-c2686d60b027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45586
2637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.455862637
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1719502866
Short name T534
Test name
Test status
Simulation time 3299442813 ps
CPU time 3.95 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206880 kb
Host smart-81ed6414-6456-4c3f-80e2-e3e864613766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17195
02866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1719502866
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2045487311
Short name T2489
Test name
Test status
Simulation time 5758785250 ps
CPU time 158.14 seconds
Started Jul 12 05:27:51 PM PDT 24
Finished Jul 12 05:30:31 PM PDT 24
Peak memory 207040 kb
Host smart-8d4ae342-377d-4269-a1a5-882a5afd7a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20454
87311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2045487311
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.981570108
Short name T2223
Test name
Test status
Simulation time 5232491329 ps
CPU time 35.85 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:28:25 PM PDT 24
Peak memory 206964 kb
Host smart-32bdc76a-b15d-42c6-87cb-6eb303e31ac0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=981570108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.981570108
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1925971829
Short name T1501
Test name
Test status
Simulation time 297161441 ps
CPU time 0.98 seconds
Started Jul 12 05:27:52 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 206772 kb
Host smart-60c1c2f6-a897-43c5-aae7-e26f86bfc2f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1925971829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1925971829
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1692537235
Short name T16
Test name
Test status
Simulation time 201087427 ps
CPU time 0.88 seconds
Started Jul 12 05:27:51 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206832 kb
Host smart-ba628b4c-50a8-429c-aa86-39ed1a305143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16925
37235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1692537235
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2824112871
Short name T1953
Test name
Test status
Simulation time 5684015296 ps
CPU time 159.12 seconds
Started Jul 12 05:27:55 PM PDT 24
Finished Jul 12 05:30:35 PM PDT 24
Peak memory 207024 kb
Host smart-e892381b-93b9-45ea-a5b0-c78c4e0b209e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28241
12871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2824112871
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.659164907
Short name T1464
Test name
Test status
Simulation time 3860334002 ps
CPU time 27.76 seconds
Started Jul 12 05:27:52 PM PDT 24
Finished Jul 12 05:28:22 PM PDT 24
Peak memory 207088 kb
Host smart-86f49857-ddb7-431b-ad31-b97b6e91186f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=659164907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.659164907
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.4064248686
Short name T940
Test name
Test status
Simulation time 152459879 ps
CPU time 0.84 seconds
Started Jul 12 05:27:52 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 206820 kb
Host smart-59a3fb75-de7e-49b4-bc1d-18e9448a1f3f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4064248686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.4064248686
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.134546100
Short name T1863
Test name
Test status
Simulation time 175800235 ps
CPU time 0.79 seconds
Started Jul 12 05:27:53 PM PDT 24
Finished Jul 12 05:27:55 PM PDT 24
Peak memory 206812 kb
Host smart-dbf9865f-174e-4a48-8d7c-1c8fa007fec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13454
6100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.134546100
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1260486501
Short name T2712
Test name
Test status
Simulation time 261774897 ps
CPU time 0.99 seconds
Started Jul 12 05:27:51 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206836 kb
Host smart-76103ea5-43b8-4173-b742-16ac54ba0b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12604
86501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1260486501
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.587930491
Short name T630
Test name
Test status
Simulation time 160139300 ps
CPU time 0.8 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:27:51 PM PDT 24
Peak memory 206816 kb
Host smart-4b2a21f9-978b-441c-bcb4-1f201d8386bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58793
0491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.587930491
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2040712432
Short name T2171
Test name
Test status
Simulation time 158035798 ps
CPU time 0.8 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206692 kb
Host smart-3595c4df-5b9c-442d-bb57-125940c4fd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20407
12432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2040712432
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3197034075
Short name T1582
Test name
Test status
Simulation time 188222470 ps
CPU time 0.89 seconds
Started Jul 12 05:27:51 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206820 kb
Host smart-3daba30e-c28e-43d7-8488-c4ab92c83d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31970
34075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3197034075
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1121636389
Short name T775
Test name
Test status
Simulation time 145535333 ps
CPU time 0.75 seconds
Started Jul 12 05:27:47 PM PDT 24
Finished Jul 12 05:27:49 PM PDT 24
Peak memory 206808 kb
Host smart-d44f397f-bddd-4915-b3f7-4495f712651b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11216
36389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1121636389
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1255344521
Short name T1198
Test name
Test status
Simulation time 204729757 ps
CPU time 1.02 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:27:51 PM PDT 24
Peak memory 206640 kb
Host smart-259b92e0-a996-4ed0-a7a1-091feaa81d25
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1255344521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1255344521
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.4277809282
Short name T727
Test name
Test status
Simulation time 146861446 ps
CPU time 0.87 seconds
Started Jul 12 05:27:47 PM PDT 24
Finished Jul 12 05:27:49 PM PDT 24
Peak memory 206816 kb
Host smart-b48be6bf-9b07-4584-a9d9-ed27ae9f4f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42778
09282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.4277809282
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2689342300
Short name T464
Test name
Test status
Simulation time 33942462 ps
CPU time 0.64 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:27:52 PM PDT 24
Peak memory 206828 kb
Host smart-ed0816fd-6218-46c0-800b-8d34f96fc2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26893
42300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2689342300
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3206441749
Short name T1789
Test name
Test status
Simulation time 13641718013 ps
CPU time 32.76 seconds
Started Jul 12 05:27:48 PM PDT 24
Finished Jul 12 05:28:22 PM PDT 24
Peak memory 207048 kb
Host smart-4927db11-3408-418c-acd4-cc4bdccc2fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064
41749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3206441749
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1588157888
Short name T1105
Test name
Test status
Simulation time 173265695 ps
CPU time 0.85 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:27:53 PM PDT 24
Peak memory 206816 kb
Host smart-51784412-9ded-400a-b67d-ba469ca46216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15881
57888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1588157888
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1010472192
Short name T1434
Test name
Test status
Simulation time 192312007 ps
CPU time 0.85 seconds
Started Jul 12 05:27:50 PM PDT 24
Finished Jul 12 05:27:52 PM PDT 24
Peak memory 206828 kb
Host smart-2908cd86-3fb2-4d3d-ab45-8a5d11846d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
72192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1010472192
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.865654281
Short name T2234
Test name
Test status
Simulation time 5480817619 ps
CPU time 45.11 seconds
Started Jul 12 05:27:54 PM PDT 24
Finished Jul 12 05:28:40 PM PDT 24
Peak memory 207072 kb
Host smart-91610fea-47e9-47d5-936d-a3702053cc6f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=865654281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.865654281
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3241812033
Short name T1760
Test name
Test status
Simulation time 4944573598 ps
CPU time 31.13 seconds
Started Jul 12 05:28:00 PM PDT 24
Finished Jul 12 05:28:32 PM PDT 24
Peak memory 207104 kb
Host smart-50a328cd-bd41-4108-bb71-3241265ed945
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3241812033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3241812033
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1470714332
Short name T1189
Test name
Test status
Simulation time 16570937940 ps
CPU time 115.79 seconds
Started Jul 12 05:28:08 PM PDT 24
Finished Jul 12 05:30:06 PM PDT 24
Peak memory 206996 kb
Host smart-66e9f274-bbb0-4a1c-a61c-d95f52b7373d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1470714332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1470714332
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2172476209
Short name T2741
Test name
Test status
Simulation time 166090662 ps
CPU time 0.81 seconds
Started Jul 12 05:27:49 PM PDT 24
Finished Jul 12 05:27:51 PM PDT 24
Peak memory 206812 kb
Host smart-38c75c59-2f00-4550-b796-a6ceeb028ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21724
76209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2172476209
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.4178927279
Short name T2669
Test name
Test status
Simulation time 175248785 ps
CPU time 0.84 seconds
Started Jul 12 05:27:55 PM PDT 24
Finished Jul 12 05:27:57 PM PDT 24
Peak memory 206816 kb
Host smart-f997980a-3c69-439c-9631-5e49d165e927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41789
27279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.4178927279
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.230004229
Short name T1171
Test name
Test status
Simulation time 172332135 ps
CPU time 0.78 seconds
Started Jul 12 05:27:58 PM PDT 24
Finished Jul 12 05:28:00 PM PDT 24
Peak memory 206804 kb
Host smart-fc92dbd1-533a-4493-9dda-062ad77ec108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23000
4229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.230004229
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3573845986
Short name T1014
Test name
Test status
Simulation time 151271031 ps
CPU time 0.76 seconds
Started Jul 12 05:28:05 PM PDT 24
Finished Jul 12 05:28:08 PM PDT 24
Peak memory 206800 kb
Host smart-0b21c482-6b43-4d50-aa74-bb6af6df401a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35738
45986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3573845986
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.916962076
Short name T1179
Test name
Test status
Simulation time 154703700 ps
CPU time 0.77 seconds
Started Jul 12 05:27:57 PM PDT 24
Finished Jul 12 05:27:59 PM PDT 24
Peak memory 206700 kb
Host smart-34a2bd78-bf2a-4caa-aee4-ae8aaa70b111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91696
2076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.916962076
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3759834609
Short name T1048
Test name
Test status
Simulation time 253336456 ps
CPU time 1.07 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:28:10 PM PDT 24
Peak memory 206808 kb
Host smart-4a466e9f-e01c-4687-b96f-6620e346443c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37598
34609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3759834609
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.659435902
Short name T5
Test name
Test status
Simulation time 3729158542 ps
CPU time 36.65 seconds
Started Jul 12 05:27:59 PM PDT 24
Finished Jul 12 05:28:37 PM PDT 24
Peak memory 207076 kb
Host smart-9bb383f1-3405-4262-b2b0-0a0b5e1afdb6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=659435902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.659435902
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2966521304
Short name T1076
Test name
Test status
Simulation time 220741408 ps
CPU time 0.93 seconds
Started Jul 12 05:28:03 PM PDT 24
Finished Jul 12 05:28:05 PM PDT 24
Peak memory 206756 kb
Host smart-fdbd8911-0b28-411a-a91e-541a96f62a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29665
21304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2966521304
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.517110049
Short name T1322
Test name
Test status
Simulation time 160713233 ps
CPU time 0.84 seconds
Started Jul 12 05:27:59 PM PDT 24
Finished Jul 12 05:28:01 PM PDT 24
Peak memory 206820 kb
Host smart-78bdbc1f-61ca-4acf-a578-d3ce0d9cc277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51711
0049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.517110049
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.19065839
Short name T1782
Test name
Test status
Simulation time 682845775 ps
CPU time 1.63 seconds
Started Jul 12 05:27:58 PM PDT 24
Finished Jul 12 05:28:02 PM PDT 24
Peak memory 206816 kb
Host smart-8de1e8d1-73a6-4426-aab9-ccc608ab5c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19065
839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.19065839
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1272144068
Short name T542
Test name
Test status
Simulation time 7158187288 ps
CPU time 200.06 seconds
Started Jul 12 05:28:07 PM PDT 24
Finished Jul 12 05:31:29 PM PDT 24
Peak memory 207016 kb
Host smart-8f9341ca-dc84-44cc-bc9d-26110ebf7aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12721
44068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1272144068
Directory /workspace/9.usbdev_streaming_out/latest
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