Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	78385	1		T1	3		T2	2		T3	2
all_values[1]	78385	1		T1	3		T2	2		T3	2
all_values[2]	78385	1		T1	3		T2	2		T3	2
all_values[3]	78385	1		T1	3		T2	2		T3	2
all_values[4]	78385	1		T1	3		T2	2		T3	2
all_values[5]	78385	1		T1	3		T2	2		T3	2
all_values[6]	78385	1		T1	3		T2	2		T3	2
all_values[7]	78385	1		T1	3		T2	2		T3	2
all_values[8]	78385	1		T1	3		T2	2		T3	2
all_values[9]	78385	1		T1	3		T2	2		T3	2
all_values[10]	78385	1		T1	3		T2	2		T3	2
all_values[11]	78385	1		T1	3		T2	2		T3	2
all_values[12]	78385	1		T1	3		T2	2		T3	2
all_values[13]	78385	1		T1	3		T2	2		T3	2
all_values[14]	78385	1		T1	3		T2	2		T3	2
all_values[15]	78385	1		T1	3		T2	2		T3	2
all_values[16]	78385	1		T1	3		T2	2		T3	2
all_values[17]	78385	1		T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1404174	1		T1	54		T2	36		T3	36
auto[1]	6756	1		T27	2		T32	2		T6	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1406207	1		T1	54		T2	36		T3	36
auto[1]	4723	1		T185	69		T186	75		T187	111

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	77417	1		T1	3		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	139	1		T185	5		T186	1		T187	2
all_values[0]	auto[1]	auto[0]	692	1		T44	3		T45	3		T46	4
all_values[0]	auto[1]	auto[1]	137	1		T186	4		T187	6		T188	2
all_values[1]	auto[0]	auto[0]	76602	1		T1	3		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	128	1		T185	3		T186	2		T187	6
all_values[1]	auto[1]	auto[0]	1526	1		T27	2		T6	2		T24	3
all_values[1]	auto[1]	auto[1]	129	1		T185	2		T186	3		T187	2
all_values[2]	auto[0]	auto[0]	78006	1		T1	3		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	117	1		T185	2		T187	3		T188	4
all_values[2]	auto[1]	auto[0]	129	1		T40	2		T41	2		T42	2
all_values[2]	auto[1]	auto[1]	133	1		T185	3		T186	3		T187	4
all_values[3]	auto[0]	auto[0]	76609	1		T1	3		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	124	1		T186	3		T187	4		T188	6
all_values[3]	auto[1]	auto[0]	1510	1		T65	1485		T185	1		T187	2
all_values[3]	auto[1]	auto[1]	142	1		T185	3		T187	1		T188	2
all_values[4]	auto[0]	auto[0]	78096	1		T1	3		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	127	1		T185	3		T188	5		T189	4
all_values[4]	auto[1]	auto[0]	40	1		T66	2		T186	2		T187	4
all_values[4]	auto[1]	auto[1]	122	1		T185	2		T186	3		T187	3
all_values[5]	auto[0]	auto[0]	78100	1		T1	3		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	141	1		T186	4		T187	5		T188	6
all_values[5]	auto[1]	auto[0]	31	1		T187	2		T250	1		T251	1
all_values[5]	auto[1]	auto[1]	113	1		T185	3		T186	1		T187	1
all_values[6]	auto[0]	auto[0]	78095	1		T1	3		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	145	1		T185	3		T187	1		T188	6
all_values[6]	auto[1]	auto[0]	26	1		T186	1		T252	1		T253	1
all_values[6]	auto[1]	auto[1]	119	1		T186	4		T187	7		T188	2
all_values[7]	auto[0]	auto[0]	78087	1		T1	3		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	117	1		T186	4		T187	5		T188	4
all_values[7]	auto[1]	auto[0]	37	1		T48	2		T49	2		T50	2
all_values[7]	auto[1]	auto[1]	144	1		T186	1		T187	3		T254	1
all_values[8]	auto[0]	auto[0]	78095	1		T1	3		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	133	1		T185	4		T186	4		T188	4
all_values[8]	auto[1]	auto[0]	41	1		T52	11		T187	4		T249	1
all_values[8]	auto[1]	auto[1]	116	1		T185	1		T186	1		T188	4
all_values[9]	auto[0]	auto[0]	78064	1		T1	3		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	131	1		T186	1		T187	5		T188	2
all_values[9]	auto[1]	auto[0]	47	1		T62	5		T63	5		T64	5
all_values[9]	auto[1]	auto[1]	143	1		T186	4		T187	3		T188	6
all_values[10]	auto[0]	auto[0]	78110	1		T1	3		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	129	1		T188	4		T249	5		T255	5
all_values[10]	auto[1]	auto[0]	41	1		T186	2		T187	7		T254	4
all_values[10]	auto[1]	auto[1]	105	1		T185	4		T188	4		T189	3
all_values[11]	auto[0]	auto[0]	78019	1		T1	3		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	127	1		T186	4		T188	3		T189	5
all_values[11]	auto[1]	auto[0]	127	1		T32	2		T71	2		T72	2
all_values[11]	auto[1]	auto[1]	112	1		T185	4		T187	6		T254	3
all_values[12]	auto[0]	auto[0]	78076	1		T1	3		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	131	1		T185	1		T187	7		T188	6
all_values[12]	auto[1]	auto[0]	35	1		T70	3		T74	3		T75	3
all_values[12]	auto[1]	auto[1]	143	1		T185	3		T186	5		T187	1
all_values[13]	auto[0]	auto[0]	78098	1		T1	3		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	146	1		T185	4		T186	1		T187	5
all_values[13]	auto[1]	auto[0]	21	1		T187	2		T254	1		T256	1
all_values[13]	auto[1]	auto[1]	120	1		T186	4		T187	1		T188	2
all_values[14]	auto[0]	auto[0]	78083	1		T1	3		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	124	1		T185	4		T187	5		T188	4
all_values[14]	auto[1]	auto[0]	22	1		T186	1		T256	1		T257	2
all_values[14]	auto[1]	auto[1]	156	1		T185	1		T186	3		T187	2
all_values[15]	auto[0]	auto[0]	78085	1		T1	3		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	152	1		T185	4		T187	5		T188	5
all_values[15]	auto[1]	auto[0]	20	1		T185	1		T188	1		T189	1
all_values[15]	auto[1]	auto[1]	128	1		T186	5		T187	3		T189	1
all_values[16]	auto[0]	auto[0]	78067	1		T1	3		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	128	1		T185	4		T186	1		T187	1
all_values[16]	auto[1]	auto[0]	48	1		T67	8		T68	8		T69	8
all_values[16]	auto[1]	auto[1]	142	1		T185	1		T186	4		T187	6
all_values[17]	auto[0]	auto[0]	78082	1		T1	3		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	144	1		T185	2		T186	1		T187	4
all_values[17]	auto[1]	auto[0]	23	1		T55	2		T56	2		T188	3
all_values[17]	auto[1]	auto[1]	136	1		T185	3		T186	4		T187	4