Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	78385	1		T1	3		T2	2		T3	2
all_pins[1]	78385	1		T1	3		T2	2		T3	2
all_pins[2]	78385	1		T1	3		T2	2		T3	2
all_pins[3]	78385	1		T1	3		T2	2		T3	2
all_pins[4]	78385	1		T1	3		T2	2		T3	2
all_pins[5]	78385	1		T1	3		T2	2		T3	2
all_pins[6]	78385	1		T1	3		T2	2		T3	2
all_pins[7]	78385	1		T1	3		T2	2		T3	2
all_pins[8]	78385	1		T1	3		T2	2		T3	2
all_pins[9]	78385	1		T1	3		T2	2		T3	2
all_pins[10]	78385	1		T1	3		T2	2		T3	2
all_pins[11]	78385	1		T1	3		T2	2		T3	2
all_pins[12]	78385	1		T1	3		T2	2		T3	2
all_pins[13]	78385	1		T1	3		T2	2		T3	2
all_pins[14]	78385	1		T1	3		T2	2		T3	2
all_pins[15]	78385	1		T1	3		T2	2		T3	2
all_pins[16]	78385	1		T1	3		T2	2		T3	2
all_pins[17]	78385	1		T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1408714	1		T1	54		T2	36		T3	36
values[0x1]	2216	1		T27	1		T32	1		T6	1
transitions[0x0=>0x1]	1942	1		T27	1		T32	1		T6	1
transitions[0x1=>0x0]	1959	1		T27	1		T32	1		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	78289	1		T1	3		T2	2		T3	2
all_pins[0]	values[0x1]	96	1		T46	1		T258	1		T259	1
all_pins[0]	transitions[0x0=>0x1]	83	1		T46	1		T258	1		T259	1
all_pins[0]	transitions[0x1=>0x0]	992	1		T27	1		T6	1		T24	1
all_pins[1]	values[0x0]	77380	1		T1	3		T2	2		T3	2
all_pins[1]	values[0x1]	1005	1		T27	1		T6	1		T24	1
all_pins[1]	transitions[0x0=>0x1]	988	1		T27	1		T6	1		T24	1
all_pins[1]	transitions[0x1=>0x0]	108	1		T40	1		T41	1		T42	1
all_pins[2]	values[0x0]	78260	1		T1	3		T2	2		T3	2
all_pins[2]	values[0x1]	125	1		T40	1		T41	1		T42	1
all_pins[2]	transitions[0x0=>0x1]	107	1		T40	1		T41	1		T42	1
all_pins[2]	transitions[0x1=>0x0]	46	1		T65	1		T185	2		T254	2
all_pins[3]	values[0x0]	78321	1		T1	3		T2	2		T3	2
all_pins[3]	values[0x1]	64	1		T65	1		T185	2		T254	2
all_pins[3]	transitions[0x0=>0x1]	46	1		T65	1		T185	2		T254	2
all_pins[3]	transitions[0x1=>0x0]	55	1		T66	1		T185	1		T186	2
all_pins[4]	values[0x0]	78312	1		T1	3		T2	2		T3	2
all_pins[4]	values[0x1]	73	1		T66	1		T185	1		T186	2
all_pins[4]	transitions[0x0=>0x1]	51	1		T66	1		T185	1		T186	2
all_pins[4]	transitions[0x1=>0x0]	39	1		T185	2		T187	1		T254	1
all_pins[5]	values[0x0]	78324	1		T1	3		T2	2		T3	2
all_pins[5]	values[0x1]	61	1		T185	2		T187	1		T254	1
all_pins[5]	transitions[0x0=>0x1]	50	1		T185	2		T249	2		T250	3
all_pins[5]	transitions[0x1=>0x0]	44	1		T186	3		T187	5		T189	1
all_pins[6]	values[0x0]	78330	1		T1	3		T2	2		T3	2
all_pins[6]	values[0x1]	55	1		T186	3		T187	6		T254	1
all_pins[6]	transitions[0x0=>0x1]	47	1		T186	3		T187	4		T254	1
all_pins[6]	transitions[0x1=>0x0]	44	1		T48	1		T49	1		T50	1
all_pins[7]	values[0x0]	78333	1		T1	3		T2	2		T3	2
all_pins[7]	values[0x1]	52	1		T48	1		T49	1		T50	1
all_pins[7]	transitions[0x0=>0x1]	40	1		T48	1		T49	1		T50	1
all_pins[7]	transitions[0x1=>0x0]	45	1		T52	1		T188	3		T189	2
all_pins[8]	values[0x0]	78328	1		T1	3		T2	2		T3	2
all_pins[8]	values[0x1]	57	1		T52	1		T186	1		T188	3
all_pins[8]	transitions[0x0=>0x1]	51	1		T52	1		T186	1		T188	3
all_pins[8]	transitions[0x1=>0x0]	66	1		T62	2		T63	2		T64	2
all_pins[9]	values[0x0]	78313	1		T1	3		T2	2		T3	2
all_pins[9]	values[0x1]	72	1		T62	2		T63	2		T64	2
all_pins[9]	transitions[0x0=>0x1]	59	1		T62	2		T63	2		T64	2
all_pins[9]	transitions[0x1=>0x0]	47	1		T185	1		T188	3		T189	2
all_pins[10]	values[0x0]	78325	1		T1	3		T2	2		T3	2
all_pins[10]	values[0x1]	60	1		T185	1		T188	3		T189	2
all_pins[10]	transitions[0x0=>0x1]	44	1		T185	1		T188	3		T189	2
all_pins[10]	transitions[0x1=>0x0]	95	1		T32	1		T71	1		T72	1
all_pins[11]	values[0x0]	78274	1		T1	3		T2	2		T3	2
all_pins[11]	values[0x1]	111	1		T32	1		T71	1		T72	1
all_pins[11]	transitions[0x0=>0x1]	89	1		T32	1		T71	1		T72	1
all_pins[11]	transitions[0x1=>0x0]	56	1		T70	1		T74	1		T75	1
all_pins[12]	values[0x0]	78307	1		T1	3		T2	2		T3	2
all_pins[12]	values[0x1]	78	1		T70	1		T74	1		T75	1
all_pins[12]	transitions[0x0=>0x1]	60	1		T70	1		T74	1		T75	1
all_pins[12]	transitions[0x1=>0x0]	33	1		T186	1		T187	1		T189	1
all_pins[13]	values[0x0]	78334	1		T1	3		T2	2		T3	2
all_pins[13]	values[0x1]	51	1		T186	1		T187	1		T189	1
all_pins[13]	transitions[0x0=>0x1]	37	1		T186	1		T187	1		T249	2
all_pins[13]	transitions[0x1=>0x0]	41	1		T186	2		T187	1		T188	1
all_pins[14]	values[0x0]	78330	1		T1	3		T2	2		T3	2
all_pins[14]	values[0x1]	55	1		T186	2		T187	1		T188	1
all_pins[14]	transitions[0x0=>0x1]	41	1		T188	1		T189	1		T250	1
all_pins[14]	transitions[0x1=>0x0]	45	1		T186	2		T187	1		T189	1
all_pins[15]	values[0x0]	78326	1		T1	3		T2	2		T3	2
all_pins[15]	values[0x1]	59	1		T186	4		T187	2		T189	1
all_pins[15]	transitions[0x0=>0x1]	41	1		T186	3		T187	2		T249	1
all_pins[15]	transitions[0x1=>0x0]	68	1		T67	4		T68	4		T69	4
all_pins[16]	values[0x0]	78299	1		T1	3		T2	2		T3	2
all_pins[16]	values[0x1]	86	1		T67	4		T68	4		T69	4
all_pins[16]	transitions[0x0=>0x1]	76	1		T67	4		T68	4		T69	4
all_pins[16]	transitions[0x1=>0x0]	46	1		T55	1		T56	1		T185	1
all_pins[17]	values[0x0]	78329	1		T1	3		T2	2		T3	2
all_pins[17]	values[0x1]	56	1		T55	1		T56	1		T185	1
all_pins[17]	transitions[0x0=>0x1]	32	1		T55	1		T56	1		T185	1
all_pins[17]	transitions[0x1=>0x0]	89	1		T46	1		T258	1		T259	1