Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T185	4		T186	4		T187	7
all_values[1]	266	1		T185	4		T186	4		T187	7
all_values[2]	266	1		T185	4		T186	4		T187	7
all_values[3]	266	1		T185	4		T186	4		T187	7
all_values[4]	266	1		T185	4		T186	4		T187	7
all_values[5]	266	1		T185	4		T186	4		T187	7
all_values[6]	266	1		T185	4		T186	4		T187	7
all_values[7]	266	1		T185	4		T186	4		T187	7
all_values[8]	266	1		T185	4		T186	4		T187	7
all_values[9]	266	1		T185	4		T186	4		T187	7
all_values[10]	266	1		T185	4		T186	4		T187	7
all_values[11]	266	1		T185	4		T186	4		T187	7
all_values[12]	266	1		T185	4		T186	4		T187	7
all_values[13]	266	1		T185	4		T186	4		T187	7
all_values[14]	266	1		T185	4		T186	4		T187	7
all_values[15]	266	1		T185	4		T186	4		T187	7
all_values[16]	266	1		T185	4		T186	4		T187	7
all_values[17]	266	1		T185	4		T186	4		T187	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2648	1		T185	49		T186	40		T187	62
auto[1]	2140	1		T185	23		T186	32		T187	64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	898	1		T185	19		T186	14		T187	31
auto[1]	3890	1		T185	53		T186	58		T187	95

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2863	1		T185	45		T186	43		T187	78
auto[1]	1925	1		T185	27		T186	29		T187	48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1		T254	1		T249	2		T255	1
all_values[0]	auto[0]	auto[0]	auto[1]	67	1		T185	2		T186	1		T187	3
all_values[0]	auto[0]	auto[1]	auto[0]	9	1		T254	1		T189	1		T260	1
all_values[0]	auto[0]	auto[1]	auto[1]	61	1		T186	1		T187	1		T254	1
all_values[0]	auto[1]	auto[0]	auto[1]	59	1		T185	2		T186	1		T188	2
all_values[0]	auto[1]	auto[1]	auto[1]	41	1		T186	1		T187	3		T188	2
all_values[1]	auto[0]	auto[0]	auto[0]	32	1		T254	3		T249	2		T250	1
all_values[1]	auto[0]	auto[0]	auto[1]	48	1		T185	1		T187	4		T188	1
all_values[1]	auto[0]	auto[1]	auto[0]	20	1		T254	1		T249	5		T255	1
all_values[1]	auto[0]	auto[1]	auto[1]	55	1		T185	2		T186	2		T187	1
all_values[1]	auto[1]	auto[0]	auto[1]	68	1		T185	1		T186	2		T187	2
all_values[1]	auto[1]	auto[1]	auto[1]	43	1		T255	1		T250	2		T257	2
all_values[2]	auto[0]	auto[0]	auto[0]	38	1		T186	2		T187	1		T254	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1		T185	1		T187	1		T188	2
all_values[2]	auto[0]	auto[1]	auto[0]	24	1		T188	1		T255	1		T252	2
all_values[2]	auto[0]	auto[1]	auto[1]	61	1		T185	1		T186	1		T187	1
all_values[2]	auto[1]	auto[0]	auto[1]	52	1		T185	2		T187	3		T188	1
all_values[2]	auto[1]	auto[1]	auto[1]	41	1		T186	1		T187	1		T188	1
all_values[3]	auto[0]	auto[0]	auto[0]	30	1		T185	2		T186	2		T187	1
all_values[3]	auto[0]	auto[0]	auto[1]	51	1		T186	1		T187	1		T188	4
all_values[3]	auto[0]	auto[1]	auto[0]	18	1		T187	2		T252	4		T257	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1		T185	1		T188	2		T254	1
all_values[3]	auto[1]	auto[0]	auto[1]	52	1		T186	1		T187	2		T254	3
all_values[3]	auto[1]	auto[1]	auto[1]	51	1		T185	1		T187	1		T188	1
all_values[4]	auto[0]	auto[0]	auto[0]	34	1		T186	1		T187	1		T188	1
all_values[4]	auto[0]	auto[0]	auto[1]	44	1		T185	1		T188	1		T189	2
all_values[4]	auto[0]	auto[1]	auto[0]	29	1		T186	1		T187	4		T189	1
all_values[4]	auto[0]	auto[1]	auto[1]	54	1		T185	1		T186	1		T187	1
all_values[4]	auto[1]	auto[0]	auto[1]	58	1		T185	1		T188	2		T249	3
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T185	1		T186	1		T187	1
all_values[5]	auto[0]	auto[0]	auto[0]	34	1		T185	2		T188	1		T189	1
all_values[5]	auto[0]	auto[0]	auto[1]	57	1		T186	3		T187	2		T188	2
all_values[5]	auto[0]	auto[1]	auto[0]	24	1		T187	2		T251	1		T261	1
all_values[5]	auto[0]	auto[1]	auto[1]	43	1		T185	1		T188	1		T249	1
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T185	1		T186	1		T187	1
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T187	2		T249	1		T250	3
all_values[6]	auto[0]	auto[0]	auto[0]	35	1		T185	2		T186	1		T249	1
all_values[6]	auto[0]	auto[0]	auto[1]	56	1		T185	1		T188	3		T254	1
all_values[6]	auto[0]	auto[1]	auto[0]	15	1		T252	1		T262	1		T263	1
all_values[6]	auto[0]	auto[1]	auto[1]	41	1		T186	1		T187	3		T188	2
all_values[6]	auto[1]	auto[0]	auto[1]	67	1		T185	1		T187	1		T188	1
all_values[6]	auto[1]	auto[1]	auto[1]	52	1		T186	2		T187	3		T188	1
all_values[7]	auto[0]	auto[0]	auto[0]	31	1		T185	1		T188	1		T249	1
all_values[7]	auto[0]	auto[0]	auto[1]	51	1		T186	1		T187	2		T188	2
all_values[7]	auto[0]	auto[1]	auto[0]	19	1		T185	3		T188	3		T250	2
all_values[7]	auto[0]	auto[1]	auto[1]	67	1		T187	1		T254	2		T189	2
all_values[7]	auto[1]	auto[0]	auto[1]	49	1		T186	3		T187	3		T254	1
all_values[7]	auto[1]	auto[1]	auto[1]	49	1		T187	1		T188	1		T249	2
all_values[8]	auto[0]	auto[0]	auto[0]	37	1		T187	2		T249	1		T250	1
all_values[8]	auto[0]	auto[0]	auto[1]	60	1		T185	2		T186	1		T188	2
all_values[8]	auto[0]	auto[1]	auto[0]	24	1		T187	5		T264	4		T261	3
all_values[8]	auto[0]	auto[1]	auto[1]	44	1		T185	1		T188	1		T254	1
all_values[8]	auto[1]	auto[0]	auto[1]	52	1		T185	1		T186	3		T188	1
all_values[8]	auto[1]	auto[1]	auto[1]	49	1		T188	3		T254	1		T189	3
all_values[9]	auto[0]	auto[0]	auto[0]	26	1		T185	3		T254	1		T250	1
all_values[9]	auto[0]	auto[0]	auto[1]	53	1		T187	3		T188	3		T254	1
all_values[9]	auto[0]	auto[1]	auto[0]	13	1		T185	1		T189	1		T252	2
all_values[9]	auto[0]	auto[1]	auto[1]	60	1		T186	3		T188	3		T249	2
all_values[9]	auto[1]	auto[0]	auto[1]	64	1		T186	1		T187	2		T188	1
all_values[9]	auto[1]	auto[1]	auto[1]	50	1		T187	2		T254	2		T189	1
all_values[10]	auto[0]	auto[0]	auto[0]	47	1		T185	1		T186	3		T187	2
all_values[10]	auto[0]	auto[0]	auto[1]	50	1		T188	2		T249	2		T255	2
all_values[10]	auto[0]	auto[1]	auto[0]	27	1		T186	1		T187	5		T254	1
all_values[10]	auto[0]	auto[1]	auto[1]	47	1		T185	2		T188	1		T189	1
all_values[10]	auto[1]	auto[0]	auto[1]	57	1		T185	1		T188	1		T249	2
all_values[10]	auto[1]	auto[1]	auto[1]	38	1		T188	3		T189	1		T249	1
all_values[11]	auto[0]	auto[0]	auto[0]	53	1		T185	1		T186	1		T187	1
all_values[11]	auto[0]	auto[0]	auto[1]	48	1		T186	2		T188	1		T189	2
all_values[11]	auto[0]	auto[1]	auto[0]	18	1		T187	1		T188	3		T254	1
all_values[11]	auto[0]	auto[1]	auto[1]	42	1		T185	1		T187	3		T254	1
all_values[11]	auto[1]	auto[0]	auto[1]	60	1		T185	1		T186	1		T188	1
all_values[11]	auto[1]	auto[1]	auto[1]	45	1		T185	1		T187	2		T254	1
all_values[12]	auto[0]	auto[0]	auto[0]	28	1		T185	1		T188	1		T264	1
all_values[12]	auto[0]	auto[0]	auto[1]	47	1		T187	3		T188	4		T254	2
all_values[12]	auto[0]	auto[1]	auto[0]	12	1		T252	1		T260	1		T251	1
all_values[12]	auto[0]	auto[1]	auto[1]	62	1		T185	1		T186	2		T187	1
all_values[12]	auto[1]	auto[0]	auto[1]	67	1		T185	1		T186	1		T187	3
all_values[12]	auto[1]	auto[1]	auto[1]	50	1		T185	1		T186	1		T249	2
all_values[13]	auto[0]	auto[0]	auto[0]	30	1		T185	1		T254	1		T250	1
all_values[13]	auto[0]	auto[0]	auto[1]	65	1		T185	1		T186	1		T187	3
all_values[13]	auto[0]	auto[1]	auto[0]	16	1		T187	2		T264	1		T260	1
all_values[13]	auto[0]	auto[1]	auto[1]	49	1		T186	2		T188	2		T189	1
all_values[13]	auto[1]	auto[0]	auto[1]	66	1		T185	2		T186	1		T187	2
all_values[13]	auto[1]	auto[1]	auto[1]	40	1		T189	2		T249	2		T255	1
all_values[14]	auto[0]	auto[0]	auto[0]	21	1		T186	2		T187	1		T255	1
all_values[14]	auto[0]	auto[0]	auto[1]	60	1		T185	2		T187	4		T188	1
all_values[14]	auto[0]	auto[1]	auto[0]	13	1		T257	1		T262	1		T264	1
all_values[14]	auto[0]	auto[1]	auto[1]	70	1		T185	1		T186	1		T188	1
all_values[14]	auto[1]	auto[0]	auto[1]	54	1		T185	1		T188	3		T254	1
all_values[14]	auto[1]	auto[1]	auto[1]	48	1		T186	1		T187	2		T188	2
all_values[15]	auto[0]	auto[0]	auto[0]	29	1		T185	1		T188	3		T254	2
all_values[15]	auto[0]	auto[0]	auto[1]	66	1		T185	1		T187	3		T188	3
all_values[15]	auto[0]	auto[1]	auto[0]	6	1		T189	1		T260	4		T265	1
all_values[15]	auto[0]	auto[1]	auto[1]	53	1		T186	2		T187	1		T249	2
all_values[15]	auto[1]	auto[0]	auto[1]	63	1		T185	1		T186	1		T187	1
all_values[15]	auto[1]	auto[1]	auto[1]	49	1		T185	1		T186	1		T187	2
all_values[16]	auto[0]	auto[0]	auto[0]	27	1		T249	4		T253	1		T262	3
all_values[16]	auto[0]	auto[0]	auto[1]	47	1		T185	1		T188	1		T189	1
all_values[16]	auto[0]	auto[1]	auto[0]	16	1		T187	1		T249	3		T262	1
all_values[16]	auto[0]	auto[1]	auto[1]	61	1		T186	2		T187	3		T188	4
all_values[16]	auto[1]	auto[0]	auto[1]	72	1		T185	2		T186	1		T187	1
all_values[16]	auto[1]	auto[1]	auto[1]	43	1		T185	1		T186	1		T187	2
all_values[17]	auto[0]	auto[0]	auto[0]	18	1		T188	1		T257	2		T266	1
all_values[17]	auto[0]	auto[0]	auto[1]	55	1		T187	1		T254	1		T189	1
all_values[17]	auto[0]	auto[1]	auto[0]	16	1		T188	3		T266	4		T251	1
all_values[17]	auto[0]	auto[1]	auto[1]	56	1		T185	1		T186	1		T187	1
all_values[17]	auto[1]	auto[0]	auto[1]	73	1		T185	3		T186	1		T187	2
all_values[17]	auto[1]	auto[1]	auto[1]	48	1		T186	2		T187	3		T188	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal