Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.80 97.86 93.72 97.44 76.56 96.30 98.17 96.58


Total test records in report: 2855
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T2764 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3931527281 Jul 13 06:58:38 PM PDT 24 Jul 13 06:58:43 PM PDT 24 361278515 ps
T2765 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2408106905 Jul 13 06:58:58 PM PDT 24 Jul 13 06:58:59 PM PDT 24 72780026 ps
T2766 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1628125636 Jul 13 06:58:55 PM PDT 24 Jul 13 06:58:58 PM PDT 24 95854365 ps
T277 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1005654067 Jul 13 06:58:38 PM PDT 24 Jul 13 06:58:43 PM PDT 24 817222720 ps
T2767 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3192385701 Jul 13 06:58:40 PM PDT 24 Jul 13 06:58:44 PM PDT 24 140854168 ps
T2768 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1625800324 Jul 13 06:58:59 PM PDT 24 Jul 13 06:59:03 PM PDT 24 445416586 ps
T239 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2116604056 Jul 13 06:58:37 PM PDT 24 Jul 13 06:58:40 PM PDT 24 210654756 ps
T240 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3722357975 Jul 13 06:58:37 PM PDT 24 Jul 13 06:58:40 PM PDT 24 117548632 ps
T261 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3178585703 Jul 13 06:59:00 PM PDT 24 Jul 13 06:59:01 PM PDT 24 51019147 ps
T2769 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.943798235 Jul 13 06:58:30 PM PDT 24 Jul 13 06:58:33 PM PDT 24 96312868 ps
T274 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3737542312 Jul 13 06:58:44 PM PDT 24 Jul 13 06:58:50 PM PDT 24 1607271591 ps
T2770 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.348516447 Jul 13 06:58:54 PM PDT 24 Jul 13 06:58:56 PM PDT 24 88251108 ps
T2771 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1546359434 Jul 13 06:58:35 PM PDT 24 Jul 13 06:58:37 PM PDT 24 43106444 ps
T2772 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.222570378 Jul 13 06:58:40 PM PDT 24 Jul 13 06:58:42 PM PDT 24 120085268 ps
T2773 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4101575495 Jul 13 06:58:50 PM PDT 24 Jul 13 06:58:51 PM PDT 24 37035138 ps
T2774 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1307367731 Jul 13 06:58:40 PM PDT 24 Jul 13 06:58:41 PM PDT 24 52898922 ps
T268 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1743967622 Jul 13 06:58:51 PM PDT 24 Jul 13 06:58:58 PM PDT 24 2186729127 ps
T2775 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2394296547 Jul 13 06:59:02 PM PDT 24 Jul 13 06:59:06 PM PDT 24 464073208 ps
T2776 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.999457643 Jul 13 06:58:38 PM PDT 24 Jul 13 06:58:40 PM PDT 24 129550563 ps
T2777 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2971394898 Jul 13 06:59:02 PM PDT 24 Jul 13 06:59:04 PM PDT 24 37296616 ps
T269 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.445123883 Jul 13 06:58:49 PM PDT 24 Jul 13 06:58:52 PM PDT 24 458556609 ps
T2778 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1834677333 Jul 13 06:59:00 PM PDT 24 Jul 13 06:59:01 PM PDT 24 147737880 ps
T2779 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1103625709 Jul 13 06:58:35 PM PDT 24 Jul 13 06:58:37 PM PDT 24 54014684 ps
T2780 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2439139269 Jul 13 06:58:49 PM PDT 24 Jul 13 06:58:50 PM PDT 24 131549441 ps
T2781 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2399925552 Jul 13 06:59:02 PM PDT 24 Jul 13 06:59:04 PM PDT 24 47540256 ps
T2782 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.677162856 Jul 13 06:58:38 PM PDT 24 Jul 13 06:58:42 PM PDT 24 264720474 ps
T270 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1946395211 Jul 13 06:58:40 PM PDT 24 Jul 13 06:58:46 PM PDT 24 709264698 ps
T2783 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2610786982 Jul 13 06:58:39 PM PDT 24 Jul 13 06:58:41 PM PDT 24 58180444 ps
T2784 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1569063338 Jul 13 06:58:29 PM PDT 24 Jul 13 06:58:32 PM PDT 24 36332802 ps
T2785 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1050241208 Jul 13 06:58:35 PM PDT 24 Jul 13 06:58:40 PM PDT 24 307257195 ps
T2786 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.541446652 Jul 13 06:58:27 PM PDT 24 Jul 13 06:58:30 PM PDT 24 318292180 ps
T2787 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3208198684 Jul 13 06:58:52 PM PDT 24 Jul 13 06:58:54 PM PDT 24 69108663 ps
T2788 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3920891288 Jul 13 06:58:38 PM PDT 24 Jul 13 06:58:42 PM PDT 24 98526009 ps
T2789 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3992900269 Jul 13 06:58:41 PM PDT 24 Jul 13 06:58:43 PM PDT 24 142386997 ps
T2790 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3607215449 Jul 13 06:58:37 PM PDT 24 Jul 13 06:58:43 PM PDT 24 721690019 ps
T265 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3050390960 Jul 13 06:59:04 PM PDT 24 Jul 13 06:59:06 PM PDT 24 40771780 ps
T2791 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3096762587 Jul 13 06:58:53 PM PDT 24 Jul 13 06:58:55 PM PDT 24 39808499 ps
T2792 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2121335310 Jul 13 06:59:03 PM PDT 24 Jul 13 06:59:06 PM PDT 24 38457608 ps
T2793 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2001066517 Jul 13 06:59:04 PM PDT 24 Jul 13 06:59:07 PM PDT 24 43925292 ps
T2794 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3157171776 Jul 13 06:58:49 PM PDT 24 Jul 13 06:58:50 PM PDT 24 109193367 ps
T2795 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1499249175 Jul 13 06:58:39 PM PDT 24 Jul 13 06:58:48 PM PDT 24 1194201472 ps
T2796 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.504002282 Jul 13 06:58:53 PM PDT 24 Jul 13 06:58:57 PM PDT 24 262709389 ps
T2797 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.300496785 Jul 13 06:58:57 PM PDT 24 Jul 13 06:58:59 PM PDT 24 98708383 ps
T2798 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.792356705 Jul 13 06:58:53 PM PDT 24 Jul 13 06:58:56 PM PDT 24 67834240 ps
T2799 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.962189789 Jul 13 06:58:53 PM PDT 24 Jul 13 06:58:56 PM PDT 24 165578956 ps
T2800 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.262175127 Jul 13 06:58:37 PM PDT 24 Jul 13 06:58:40 PM PDT 24 175660670 ps
T2801 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2289518971 Jul 13 06:59:00 PM PDT 24 Jul 13 06:59:03 PM PDT 24 207648994 ps
T2802 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2870176835 Jul 13 06:59:02 PM PDT 24 Jul 13 06:59:05 PM PDT 24 58535844 ps
T2803 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3852696757 Jul 13 06:58:52 PM PDT 24 Jul 13 06:58:55 PM PDT 24 60789408 ps
T273 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3501369220 Jul 13 06:58:34 PM PDT 24 Jul 13 06:58:38 PM PDT 24 507381422 ps
T2804 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2636998701 Jul 13 06:58:49 PM PDT 24 Jul 13 06:58:51 PM PDT 24 75690041 ps
T2805 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3555085837 Jul 13 06:58:44 PM PDT 24 Jul 13 06:58:49 PM PDT 24 317123867 ps
T2806 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.964815481 Jul 13 06:58:53 PM PDT 24 Jul 13 06:58:55 PM PDT 24 72533116 ps
T2807 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.90203603 Jul 13 06:58:43 PM PDT 24 Jul 13 06:58:45 PM PDT 24 94991518 ps
T2808 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1729750778 Jul 13 06:58:37 PM PDT 24 Jul 13 06:58:41 PM PDT 24 316872528 ps
T2809 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2030229874 Jul 13 06:58:57 PM PDT 24 Jul 13 06:58:58 PM PDT 24 38196321 ps
T2810 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1110879078 Jul 13 06:58:37 PM PDT 24 Jul 13 06:58:42 PM PDT 24 162513908 ps
T2811 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.93229069 Jul 13 06:58:53 PM PDT 24 Jul 13 06:58:56 PM PDT 24 89075089 ps
T2812 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2206073082 Jul 13 06:58:35 PM PDT 24 Jul 13 06:58:44 PM PDT 24 1067488313 ps
T2813 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2677221211 Jul 13 06:58:52 PM PDT 24 Jul 13 06:58:54 PM PDT 24 165919666 ps
T2814 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2090151849 Jul 13 06:59:00 PM PDT 24 Jul 13 06:59:01 PM PDT 24 33594821 ps
T2815 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.328647909 Jul 13 06:58:51 PM PDT 24 Jul 13 06:58:53 PM PDT 24 40714046 ps
T2816 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4148217323 Jul 13 06:59:03 PM PDT 24 Jul 13 06:59:06 PM PDT 24 43044622 ps
T2817 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.481235764 Jul 13 06:58:52 PM PDT 24 Jul 13 06:58:54 PM PDT 24 141928452 ps
T2818 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1285313536 Jul 13 06:58:51 PM PDT 24 Jul 13 06:58:53 PM PDT 24 78932524 ps
T2819 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1152081139 Jul 13 06:58:58 PM PDT 24 Jul 13 06:59:00 PM PDT 24 42250912 ps
T2820 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.793209802 Jul 13 06:59:02 PM PDT 24 Jul 13 06:59:04 PM PDT 24 70022525 ps
T2821 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1598624690 Jul 13 06:59:03 PM PDT 24 Jul 13 06:59:07 PM PDT 24 83266601 ps
T2822 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.961006342 Jul 13 06:58:51 PM PDT 24 Jul 13 06:58:53 PM PDT 24 241572260 ps
T271 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1365410189 Jul 13 06:58:36 PM PDT 24 Jul 13 06:58:41 PM PDT 24 411360377 ps
T2823 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.4171326464 Jul 13 06:58:41 PM PDT 24 Jul 13 06:58:43 PM PDT 24 116797684 ps
T276 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.785856535 Jul 13 06:58:43 PM PDT 24 Jul 13 06:58:46 PM PDT 24 335808821 ps
T2824 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3632139618 Jul 13 06:58:54 PM PDT 24 Jul 13 06:58:57 PM PDT 24 95907612 ps
T2825 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1189539354 Jul 13 06:58:59 PM PDT 24 Jul 13 06:59:01 PM PDT 24 41066656 ps
T2826 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1100563656 Jul 13 06:59:05 PM PDT 24 Jul 13 06:59:10 PM PDT 24 270388548 ps
T2827 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3984237312 Jul 13 06:58:45 PM PDT 24 Jul 13 06:58:48 PM PDT 24 209944153 ps
T2828 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1749058845 Jul 13 06:59:02 PM PDT 24 Jul 13 06:59:04 PM PDT 24 51964758 ps
T2829 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4115080807 Jul 13 06:58:44 PM PDT 24 Jul 13 06:58:45 PM PDT 24 36819158 ps
T2830 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1880771114 Jul 13 06:58:33 PM PDT 24 Jul 13 06:58:38 PM PDT 24 326640802 ps
T2831 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.457465810 Jul 13 06:58:52 PM PDT 24 Jul 13 06:58:54 PM PDT 24 79628075 ps
T2832 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3784839226 Jul 13 06:58:40 PM PDT 24 Jul 13 06:58:45 PM PDT 24 778079357 ps
T2833 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.918902665 Jul 13 06:58:33 PM PDT 24 Jul 13 06:58:35 PM PDT 24 86321155 ps
T2834 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.609528489 Jul 13 06:58:51 PM PDT 24 Jul 13 06:58:53 PM PDT 24 81045693 ps
T2835 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2366102611 Jul 13 06:58:43 PM PDT 24 Jul 13 06:58:44 PM PDT 24 33183135 ps
T2836 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1853904106 Jul 13 06:58:32 PM PDT 24 Jul 13 06:58:34 PM PDT 24 94494625 ps
T2837 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4022293898 Jul 13 06:59:00 PM PDT 24 Jul 13 06:59:01 PM PDT 24 31761499 ps
T2838 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3289328606 Jul 13 06:58:42 PM PDT 24 Jul 13 06:58:45 PM PDT 24 204464080 ps
T2839 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1423239043 Jul 13 06:58:48 PM PDT 24 Jul 13 06:58:50 PM PDT 24 70758388 ps
T2840 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.530282450 Jul 13 06:58:40 PM PDT 24 Jul 13 06:58:46 PM PDT 24 644735169 ps
T2841 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1606872976 Jul 13 06:58:51 PM PDT 24 Jul 13 06:58:54 PM PDT 24 108614786 ps
T2842 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.651216294 Jul 13 06:59:02 PM PDT 24 Jul 13 06:59:05 PM PDT 24 73885015 ps
T2843 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.450789590 Jul 13 06:58:30 PM PDT 24 Jul 13 06:58:32 PM PDT 24 31199044 ps
T2844 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2940380547 Jul 13 06:58:36 PM PDT 24 Jul 13 06:58:38 PM PDT 24 73473964 ps
T2845 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.344273710 Jul 13 06:58:48 PM PDT 24 Jul 13 06:58:49 PM PDT 24 42083427 ps
T2846 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.179419253 Jul 13 06:58:40 PM PDT 24 Jul 13 06:58:41 PM PDT 24 59744949 ps
T2847 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1997891910 Jul 13 06:58:34 PM PDT 24 Jul 13 06:58:37 PM PDT 24 122906472 ps
T2848 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1876194923 Jul 13 06:59:01 PM PDT 24 Jul 13 06:59:04 PM PDT 24 43978068 ps
T2849 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1281536088 Jul 13 06:58:36 PM PDT 24 Jul 13 06:58:38 PM PDT 24 134828559 ps
T2850 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1542500321 Jul 13 06:59:11 PM PDT 24 Jul 13 06:59:13 PM PDT 24 39278667 ps
T2851 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2253261143 Jul 13 06:58:51 PM PDT 24 Jul 13 06:58:53 PM PDT 24 84885774 ps
T275 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2177543226 Jul 13 06:58:55 PM PDT 24 Jul 13 06:58:58 PM PDT 24 387066867 ps
T2852 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4098384789 Jul 13 06:58:52 PM PDT 24 Jul 13 06:58:54 PM PDT 24 48079475 ps
T2853 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.710087953 Jul 13 06:59:05 PM PDT 24 Jul 13 06:59:07 PM PDT 24 55748688 ps
T2854 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1860501905 Jul 13 06:58:44 PM PDT 24 Jul 13 06:58:48 PM PDT 24 159607630 ps
T2855 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1605730139 Jul 13 06:58:50 PM PDT 24 Jul 13 06:58:54 PM PDT 24 993435005 ps

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3121471373
Short name T4
Test name
Test status
Simulation time 4390376509 ps
CPU time 32.4 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:48 PM PDT 24
Peak memory 207100 kb
Host smart-eba4304d-42bb-497a-a19b-0bf0a4e6ce52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31214
71373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3121471373
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3961906953
Short name T249
Test name
Test status
Simulation time 55011513 ps
CPU time 0.73 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:03 PM PDT 24
Peak memory 206348 kb
Host smart-db7fa073-2c6c-4d7d-a449-93995f4b97a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3961906953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3961906953
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2483910917
Short name T6
Test name
Test status
Simulation time 13359818204 ps
CPU time 13.39 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:15 PM PDT 24
Peak memory 206924 kb
Host smart-43c3d2dc-c3f1-472b-977d-99f0535b7f0e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2483910917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2483910917
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3513974980
Short name T83
Test name
Test status
Simulation time 16788510136 ps
CPU time 33.81 seconds
Started Jul 13 07:16:03 PM PDT 24
Finished Jul 13 07:16:38 PM PDT 24
Peak memory 206920 kb
Host smart-79331083-edb3-4a27-abb7-52582eb59dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35139
74980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3513974980
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.860754866
Short name T206
Test name
Test status
Simulation time 983739051 ps
CPU time 4.81 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 206508 kb
Host smart-24b606b0-0732-4b51-988e-a4ace9639a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=860754866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.860754866
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3132365569
Short name T187
Test name
Test status
Simulation time 47913033 ps
CPU time 0.71 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 206384 kb
Host smart-0b4d238b-9082-40ca-9057-93f8b10d5f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3132365569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3132365569
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2356650227
Short name T94
Test name
Test status
Simulation time 186755361 ps
CPU time 0.8 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:22 PM PDT 24
Peak memory 206864 kb
Host smart-ee5cc3f4-0c82-46e6-bc6d-cc1315d1e238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23566
50227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2356650227
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3591085783
Short name T106
Test name
Test status
Simulation time 186461276 ps
CPU time 0.86 seconds
Started Jul 13 07:12:25 PM PDT 24
Finished Jul 13 07:12:28 PM PDT 24
Peak memory 206852 kb
Host smart-0d7ba5ba-c5e1-4dc7-92c5-ba337456db77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35910
85783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3591085783
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.629096830
Short name T40
Test name
Test status
Simulation time 172791784 ps
CPU time 0.78 seconds
Started Jul 13 07:12:29 PM PDT 24
Finished Jul 13 07:12:30 PM PDT 24
Peak memory 206856 kb
Host smart-89920af1-6aae-41ba-a2a2-c180e435abc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62909
6830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.629096830
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3104236629
Short name T184
Test name
Test status
Simulation time 4191888318 ps
CPU time 5.12 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:20 PM PDT 24
Peak memory 207144 kb
Host smart-d09b8f74-7135-49be-8c9e-e0daeda962ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3104236629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.3104236629
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.29109657
Short name T61
Test name
Test status
Simulation time 9218306732 ps
CPU time 49.94 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:56 PM PDT 24
Peak memory 207144 kb
Host smart-7559537a-ac28-4fa3-9d10-64d7fd9ad98d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=29109657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.29109657
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2633849745
Short name T130
Test name
Test status
Simulation time 215561388 ps
CPU time 0.85 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:15 PM PDT 24
Peak memory 206864 kb
Host smart-f87c912b-66c2-456c-9071-b0f489a861a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26338
49745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2633849745
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3780098425
Short name T207
Test name
Test status
Simulation time 272775788 ps
CPU time 1.87 seconds
Started Jul 13 06:59:00 PM PDT 24
Finished Jul 13 06:59:03 PM PDT 24
Peak memory 214848 kb
Host smart-0c068292-386d-4d31-8c8e-283c9c05eebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780098425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3780098425
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.2919064331
Short name T546
Test name
Test status
Simulation time 165403508 ps
CPU time 0.83 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:07:15 PM PDT 24
Peak memory 206856 kb
Host smart-2e169fd8-3eb6-4451-b748-52a73414c6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29190
64331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.2919064331
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.710476691
Short name T39
Test name
Test status
Simulation time 8856249938 ps
CPU time 226.43 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:11:59 PM PDT 24
Peak memory 207124 kb
Host smart-927cfc78-7283-4e31-8988-5fdfd5af2dc4
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=710476691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.710476691
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1593016950
Short name T33
Test name
Test status
Simulation time 32157525 ps
CPU time 0.67 seconds
Started Jul 13 07:07:34 PM PDT 24
Finished Jul 13 07:07:34 PM PDT 24
Peak memory 206868 kb
Host smart-a7923d92-b1c1-4795-9338-b0231665c708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15930
16950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1593016950
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2025863272
Short name T185
Test name
Test status
Simulation time 40150092 ps
CPU time 0.68 seconds
Started Jul 13 06:59:05 PM PDT 24
Finished Jul 13 06:59:08 PM PDT 24
Peak memory 206352 kb
Host smart-10439ba4-6b1d-40a9-ba06-95523c8fe2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2025863272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2025863272
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3789947302
Short name T190
Test name
Test status
Simulation time 204493560 ps
CPU time 1.03 seconds
Started Jul 13 07:07:52 PM PDT 24
Finished Jul 13 07:07:53 PM PDT 24
Peak memory 224580 kb
Host smart-d1cce124-f0b0-465a-bded-9d332bbd5896
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3789947302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3789947302
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3187095331
Short name T387
Test name
Test status
Simulation time 67539193 ps
CPU time 0.75 seconds
Started Jul 13 07:13:26 PM PDT 24
Finished Jul 13 07:13:28 PM PDT 24
Peak memory 206948 kb
Host smart-13e0a754-b278-4275-a2df-438fe84ce48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3187095331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3187095331
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.106877471
Short name T77
Test name
Test status
Simulation time 302352384 ps
CPU time 0.94 seconds
Started Jul 13 07:07:30 PM PDT 24
Finished Jul 13 07:07:32 PM PDT 24
Peak memory 206860 kb
Host smart-cbc3e24e-0fa0-41f5-bb4d-29f0c238914b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10687
7471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.106877471
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3772145691
Short name T43
Test name
Test status
Simulation time 20164349014 ps
CPU time 21.14 seconds
Started Jul 13 07:07:40 PM PDT 24
Finished Jul 13 07:08:02 PM PDT 24
Peak memory 206936 kb
Host smart-ce482ffb-032d-4554-8e2c-8386852b3dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37721
45691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3772145691
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3317061300
Short name T58
Test name
Test status
Simulation time 1266005665 ps
CPU time 2.74 seconds
Started Jul 13 07:16:57 PM PDT 24
Finished Jul 13 07:17:07 PM PDT 24
Peak memory 207004 kb
Host smart-6c01479b-7774-4a06-8c96-9caa86a7250e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33170
61300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3317061300
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1845629813
Short name T233
Test name
Test status
Simulation time 1162701022 ps
CPU time 7.62 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 206476 kb
Host smart-cfec0253-b9e2-4b8e-bccf-df3cdc22c953
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1845629813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1845629813
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2350943736
Short name T262
Test name
Test status
Simulation time 52167036 ps
CPU time 0.69 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206364 kb
Host smart-75c9105a-5f49-46e8-92cb-e63331c52e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2350943736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2350943736
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1848554850
Short name T209
Test name
Test status
Simulation time 302863363 ps
CPU time 3.61 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:55 PM PDT 24
Peak memory 214884 kb
Host smart-8a16b7ae-e3fa-4c42-944c-6f02fb14ef08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1848554850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1848554850
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.371948900
Short name T518
Test name
Test status
Simulation time 222246316 ps
CPU time 0.87 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206860 kb
Host smart-f73e8b94-bc98-4402-bbe8-9dcc723379a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
8900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.371948900
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3104590678
Short name T258
Test name
Test status
Simulation time 171519418 ps
CPU time 0.84 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206852 kb
Host smart-70d6e86f-47b7-4d2d-a336-2fdb25f6d5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31045
90678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3104590678
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4000834888
Short name T175
Test name
Test status
Simulation time 548450209 ps
CPU time 4.06 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:58 PM PDT 24
Peak memory 206628 kb
Host smart-0bf9efe3-e660-4531-819e-474e66b619c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4000834888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.4000834888
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2436618337
Short name T251
Test name
Test status
Simulation time 96127139 ps
CPU time 0.72 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 206368 kb
Host smart-3c931d0f-ed68-4c2b-9459-dc24dd6e4115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2436618337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2436618337
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3339547936
Short name T222
Test name
Test status
Simulation time 1072397394 ps
CPU time 4.94 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 206560 kb
Host smart-6b11e24d-c5f5-4d1f-8224-f1351facb137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3339547936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3339547936
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1459763278
Short name T67
Test name
Test status
Simulation time 530838776 ps
CPU time 1.39 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:07:15 PM PDT 24
Peak memory 206876 kb
Host smart-9916a102-42d9-45c2-a2d2-91ceafd64643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14597
63278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.1459763278
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.328647909
Short name T2815
Test name
Test status
Simulation time 40714046 ps
CPU time 0.73 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 206384 kb
Host smart-f09990bb-1a6a-4e3c-b4be-c0ce82a69aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=328647909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.328647909
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1416398400
Short name T31
Test name
Test status
Simulation time 5986417747 ps
CPU time 171.41 seconds
Started Jul 13 07:12:53 PM PDT 24
Finished Jul 13 07:15:49 PM PDT 24
Peak memory 207048 kb
Host smart-b6fa876d-c48c-4eba-a9c2-f9f738c49825
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1416398400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1416398400
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2767829921
Short name T145
Test name
Test status
Simulation time 4870540067 ps
CPU time 29.18 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:08:41 PM PDT 24
Peak memory 207132 kb
Host smart-a9cb03a0-7bfb-4ca8-87eb-8c5ca2f2733e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2767829921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2767829921
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2688450919
Short name T52
Test name
Test status
Simulation time 290500166 ps
CPU time 1 seconds
Started Jul 13 07:07:43 PM PDT 24
Finished Jul 13 07:07:44 PM PDT 24
Peak memory 206772 kb
Host smart-b94bf6d9-6f51-4c04-aadc-4a1a7df69b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26884
50919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2688450919
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1551761164
Short name T245
Test name
Test status
Simulation time 281029392 ps
CPU time 1.88 seconds
Started Jul 13 06:58:35 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 206572 kb
Host smart-71dbc363-bdfc-463b-beef-38cc2e64ce5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1551761164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1551761164
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1150692673
Short name T62
Test name
Test status
Simulation time 138872270 ps
CPU time 0.75 seconds
Started Jul 13 07:07:11 PM PDT 24
Finished Jul 13 07:07:12 PM PDT 24
Peak memory 206840 kb
Host smart-2b62baff-c037-43fb-9179-40b7bea632be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11506
92673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1150692673
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.274015538
Short name T260
Test name
Test status
Simulation time 75208604 ps
CPU time 0.74 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:03 PM PDT 24
Peak memory 206384 kb
Host smart-7fbf45db-0021-44c7-911f-dbebd105f1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=274015538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.274015538
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.988802818
Short name T73
Test name
Test status
Simulation time 8764873243 ps
CPU time 245.23 seconds
Started Jul 13 07:15:47 PM PDT 24
Finished Jul 13 07:19:53 PM PDT 24
Peak memory 207072 kb
Host smart-fa42ee34-8c36-4899-996f-43f913e9cb58
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=988802818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.988802818
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3924232896
Short name T35
Test name
Test status
Simulation time 40161828 ps
CPU time 0.65 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206864 kb
Host smart-48c18a04-88e6-45a3-a910-66f53d0a94e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242
32896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3924232896
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3752006070
Short name T448
Test name
Test status
Simulation time 185958995 ps
CPU time 0.81 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 206852 kb
Host smart-ed47298c-5b12-4bc1-a25c-66cf74e58992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37520
06070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3752006070
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1086753848
Short name T1860
Test name
Test status
Simulation time 4270263416 ps
CPU time 5.06 seconds
Started Jul 13 07:11:20 PM PDT 24
Finished Jul 13 07:11:29 PM PDT 24
Peak memory 206932 kb
Host smart-d5f71a9c-8c92-48ed-a922-6150c0e6259f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1086753848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.1086753848
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1056776237
Short name T584
Test name
Test status
Simulation time 261952268 ps
CPU time 1.87 seconds
Started Jul 13 07:11:06 PM PDT 24
Finished Jul 13 07:11:09 PM PDT 24
Peak memory 207040 kb
Host smart-06db985d-a29d-4d0c-995c-f572c045b733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
76237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1056776237
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2408908242
Short name T208
Test name
Test status
Simulation time 290354644 ps
CPU time 3.09 seconds
Started Jul 13 06:58:26 PM PDT 24
Finished Jul 13 06:58:29 PM PDT 24
Peak memory 206596 kb
Host smart-3b53dea7-5772-4381-8877-3a74ab24824e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2408908242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2408908242
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.572976473
Short name T50
Test name
Test status
Simulation time 182447299 ps
CPU time 0.82 seconds
Started Jul 13 07:07:11 PM PDT 24
Finished Jul 13 07:07:13 PM PDT 24
Peak memory 206872 kb
Host smart-1235fbb1-de51-43cc-83d0-c483230923f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57297
6473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.572976473
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.530163305
Short name T65
Test name
Test status
Simulation time 4202777090 ps
CPU time 8.64 seconds
Started Jul 13 07:07:12 PM PDT 24
Finished Jul 13 07:07:22 PM PDT 24
Peak memory 207132 kb
Host smart-0a2aeaa8-f273-47ed-8d11-89736cc4173c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53016
3305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.530163305
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2812702761
Short name T66
Test name
Test status
Simulation time 174610930 ps
CPU time 0.81 seconds
Started Jul 13 07:07:22 PM PDT 24
Finished Jul 13 07:07:24 PM PDT 24
Peak memory 206860 kb
Host smart-60861cc9-3f98-4846-b0ad-7256d33f1ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28127
02761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2812702761
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.835319569
Short name T75
Test name
Test status
Simulation time 189796660 ps
CPU time 0.82 seconds
Started Jul 13 07:07:40 PM PDT 24
Finished Jul 13 07:07:42 PM PDT 24
Peak memory 206856 kb
Host smart-118ac0b7-4665-40bd-ba0f-53d77525a68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83531
9569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.835319569
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2974500660
Short name T56
Test name
Test status
Simulation time 161024144 ps
CPU time 0.81 seconds
Started Jul 13 07:08:14 PM PDT 24
Finished Jul 13 07:08:15 PM PDT 24
Peak memory 206872 kb
Host smart-7d9c789e-6535-46bd-88fa-e1d579db2294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29745
00660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2974500660
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3461390156
Short name T219
Test name
Test status
Simulation time 383373340 ps
CPU time 2.7 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 206580 kb
Host smart-9299dad1-ba47-4c77-a06b-db707bcbe584
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3461390156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3461390156
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1624008021
Short name T136
Test name
Test status
Simulation time 229053421 ps
CPU time 0.96 seconds
Started Jul 13 07:07:31 PM PDT 24
Finished Jul 13 07:07:33 PM PDT 24
Peak memory 206856 kb
Host smart-0b484c84-de36-4953-9400-3c3a434eb235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16240
08021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1624008021
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2025559719
Short name T157
Test name
Test status
Simulation time 7685135670 ps
CPU time 66.21 seconds
Started Jul 13 07:07:42 PM PDT 24
Finished Jul 13 07:08:49 PM PDT 24
Peak memory 207080 kb
Host smart-ab21cbd2-2238-4f7d-a1ac-3c387ae8b764
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2025559719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2025559719
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3899887293
Short name T2669
Test name
Test status
Simulation time 390030673 ps
CPU time 1.25 seconds
Started Jul 13 07:07:43 PM PDT 24
Finished Jul 13 07:07:44 PM PDT 24
Peak memory 206868 kb
Host smart-9085027d-d6c5-4ea9-8fad-76c2affd02e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38998
87293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3899887293
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1221853273
Short name T1761
Test name
Test status
Simulation time 200872971 ps
CPU time 0.88 seconds
Started Jul 13 07:08:09 PM PDT 24
Finished Jul 13 07:08:11 PM PDT 24
Peak memory 206872 kb
Host smart-f42a5c63-6596-4ba0-a82c-87cb8162e7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12218
53273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1221853273
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2510938766
Short name T112
Test name
Test status
Simulation time 253579370 ps
CPU time 0.95 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206868 kb
Host smart-930e4dc2-c65f-4cb1-81c7-f2fdac409f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25109
38766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2510938766
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.486371813
Short name T1168
Test name
Test status
Simulation time 4502224216 ps
CPU time 39.37 seconds
Started Jul 13 07:11:20 PM PDT 24
Finished Jul 13 07:12:03 PM PDT 24
Peak memory 207136 kb
Host smart-2e66b1b1-fb0c-4587-9fdc-c5cb4f1945b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48637
1813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.486371813
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2787792017
Short name T134
Test name
Test status
Simulation time 168422368 ps
CPU time 0.79 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:20 PM PDT 24
Peak memory 206856 kb
Host smart-83e275fe-466b-43ee-92e9-b760a31512ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
92017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2787792017
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1479931819
Short name T129
Test name
Test status
Simulation time 189807105 ps
CPU time 0.88 seconds
Started Jul 13 07:12:07 PM PDT 24
Finished Jul 13 07:12:10 PM PDT 24
Peak memory 206868 kb
Host smart-fe66ea47-4776-41ad-800f-36940b7b2421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14799
31819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1479931819
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3136593392
Short name T115
Test name
Test status
Simulation time 223488458 ps
CPU time 0.88 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:21 PM PDT 24
Peak memory 206808 kb
Host smart-0d1c9842-d742-44a0-a287-f850b73ebfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31365
93392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3136593392
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.892281480
Short name T122
Test name
Test status
Simulation time 202296884 ps
CPU time 0.85 seconds
Started Jul 13 07:12:40 PM PDT 24
Finished Jul 13 07:12:41 PM PDT 24
Peak memory 206864 kb
Host smart-e983a120-98d1-4d65-a2da-365fba76e6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89228
1480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.892281480
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.660640037
Short name T117
Test name
Test status
Simulation time 204921342 ps
CPU time 0.93 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 206884 kb
Host smart-6ad8490b-a0be-4007-a910-4e91bae615a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66064
0037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.660640037
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1670645158
Short name T2277
Test name
Test status
Simulation time 201510104 ps
CPU time 0.93 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206868 kb
Host smart-6fe48484-a8b0-49c4-a4d0-91a2245d842c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16706
45158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1670645158
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.396311740
Short name T127
Test name
Test status
Simulation time 184584740 ps
CPU time 0.9 seconds
Started Jul 13 07:16:23 PM PDT 24
Finished Jul 13 07:16:25 PM PDT 24
Peak memory 206864 kb
Host smart-bd947a34-31f3-47db-9b7a-bfc27a15d051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39631
1740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.396311740
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2325532280
Short name T2760
Test name
Test status
Simulation time 112122918 ps
CPU time 2.05 seconds
Started Jul 13 06:58:29 PM PDT 24
Finished Jul 13 06:58:33 PM PDT 24
Peak memory 206440 kb
Host smart-8840d3a5-2469-46cf-8a19-70f55f397b16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2325532280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2325532280
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1853904106
Short name T2836
Test name
Test status
Simulation time 94494625 ps
CPU time 0.91 seconds
Started Jul 13 06:58:32 PM PDT 24
Finished Jul 13 06:58:34 PM PDT 24
Peak memory 206360 kb
Host smart-64f520ef-c34f-4b6d-ae7c-58586d84bf11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1853904106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1853904106
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4032733213
Short name T248
Test name
Test status
Simulation time 163299501 ps
CPU time 1.77 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:32 PM PDT 24
Peak memory 215048 kb
Host smart-a9fdf8fc-a606-42de-ac0a-e0ee29e3cf5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032733213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.4032733213
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1910705780
Short name T235
Test name
Test status
Simulation time 70700066 ps
CPU time 0.93 seconds
Started Jul 13 06:58:28 PM PDT 24
Finished Jul 13 06:58:31 PM PDT 24
Peak memory 206528 kb
Host smart-70d74fc3-e52b-4532-af72-e4f5b9c0f2bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1910705780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1910705780
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1569063338
Short name T2784
Test name
Test status
Simulation time 36332802 ps
CPU time 0.65 seconds
Started Jul 13 06:58:29 PM PDT 24
Finished Jul 13 06:58:32 PM PDT 24
Peak memory 206532 kb
Host smart-2b3f21e3-39eb-4787-a97a-c432a5265992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1569063338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1569063338
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1353546995
Short name T237
Test name
Test status
Simulation time 70752524 ps
CPU time 1.38 seconds
Started Jul 13 06:58:26 PM PDT 24
Finished Jul 13 06:58:29 PM PDT 24
Peak memory 214836 kb
Host smart-181e1216-b15f-4e54-a3a2-5fbf6a7c7c24
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1353546995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1353546995
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3589169425
Short name T2761
Test name
Test status
Simulation time 166924621 ps
CPU time 4.09 seconds
Started Jul 13 06:58:30 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 206472 kb
Host smart-74a70770-c20c-46af-ae2d-5eee37379bd4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3589169425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3589169425
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.541446652
Short name T2786
Test name
Test status
Simulation time 318292180 ps
CPU time 1.17 seconds
Started Jul 13 06:58:27 PM PDT 24
Finished Jul 13 06:58:30 PM PDT 24
Peak memory 206604 kb
Host smart-bb35215e-a67c-402d-9443-1debc46ac40d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=541446652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.541446652
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3501369220
Short name T273
Test name
Test status
Simulation time 507381422 ps
CPU time 2.77 seconds
Started Jul 13 06:58:34 PM PDT 24
Finished Jul 13 06:58:38 PM PDT 24
Peak memory 206648 kb
Host smart-131865a5-33e1-4b28-90aa-43982c61362a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3501369220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3501369220
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3795185081
Short name T218
Test name
Test status
Simulation time 178101975 ps
CPU time 2.05 seconds
Started Jul 13 06:58:34 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 206556 kb
Host smart-61754444-6527-433f-a424-89c642219ee3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3795185081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3795185081
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3189075265
Short name T236
Test name
Test status
Simulation time 1041229608 ps
CPU time 5.17 seconds
Started Jul 13 06:58:30 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 206528 kb
Host smart-63d9e27c-0295-45b3-97ee-6806f9a353b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3189075265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3189075265
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.525061442
Short name T231
Test name
Test status
Simulation time 79930950 ps
CPU time 0.88 seconds
Started Jul 13 06:58:35 PM PDT 24
Finished Jul 13 06:58:36 PM PDT 24
Peak memory 206384 kb
Host smart-2eb6a0cc-f8d0-4d84-bf7a-4dfbfa9e3bbf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=525061442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.525061442
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.999457643
Short name T2776
Test name
Test status
Simulation time 129550563 ps
CPU time 1.4 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:40 PM PDT 24
Peak memory 214816 kb
Host smart-fec623c3-ed72-43ef-b032-527f8837db61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999457643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.999457643
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.918902665
Short name T2833
Test name
Test status
Simulation time 86321155 ps
CPU time 1.04 seconds
Started Jul 13 06:58:33 PM PDT 24
Finished Jul 13 06:58:35 PM PDT 24
Peak memory 206556 kb
Host smart-8a5cdce0-dcb2-49cb-b60c-886d6d913b87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=918902665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.918902665
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.450789590
Short name T2843
Test name
Test status
Simulation time 31199044 ps
CPU time 0.67 seconds
Started Jul 13 06:58:30 PM PDT 24
Finished Jul 13 06:58:32 PM PDT 24
Peak memory 206380 kb
Host smart-a700f572-3c56-4440-b16a-5b24249e6d8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=450789590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.450789590
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.943798235
Short name T2769
Test name
Test status
Simulation time 96312868 ps
CPU time 1.4 seconds
Started Jul 13 06:58:30 PM PDT 24
Finished Jul 13 06:58:33 PM PDT 24
Peak memory 214748 kb
Host smart-998e69c0-6400-4693-bcf6-2be75909ac56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=943798235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.943798235
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1918009714
Short name T2753
Test name
Test status
Simulation time 378633930 ps
CPU time 2.6 seconds
Started Jul 13 06:58:29 PM PDT 24
Finished Jul 13 06:58:34 PM PDT 24
Peak memory 206440 kb
Host smart-7fe9ad4f-9ff0-4679-bfa7-50b05631abe7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1918009714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1918009714
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1880771114
Short name T2830
Test name
Test status
Simulation time 326640802 ps
CPU time 3.64 seconds
Started Jul 13 06:58:33 PM PDT 24
Finished Jul 13 06:58:38 PM PDT 24
Peak memory 222708 kb
Host smart-5a8c6ad2-41a0-48e2-b7cc-77376842d16f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1880771114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1880771114
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2636998701
Short name T2804
Test name
Test status
Simulation time 75690041 ps
CPU time 1.43 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:51 PM PDT 24
Peak memory 214812 kb
Host smart-452f2f61-63b5-4a87-8092-ce4faaa50810
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636998701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2636998701
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.609528489
Short name T2834
Test name
Test status
Simulation time 81045693 ps
CPU time 1.14 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 206572 kb
Host smart-897915c6-c138-47fd-94f6-b1eda29af2c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=609528489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.609528489
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3157171776
Short name T2794
Test name
Test status
Simulation time 109193367 ps
CPU time 0.73 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:50 PM PDT 24
Peak memory 206356 kb
Host smart-0f94b7c5-ee6b-407f-bf43-c4bfc8c9227d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3157171776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3157171776
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2221863299
Short name T242
Test name
Test status
Simulation time 94674156 ps
CPU time 1.01 seconds
Started Jul 13 06:58:50 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 206628 kb
Host smart-4c2d66db-0f18-4c62-99d8-9494fa2db17a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2221863299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2221863299
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1628125636
Short name T2766
Test name
Test status
Simulation time 95854365 ps
CPU time 2.79 seconds
Started Jul 13 06:58:55 PM PDT 24
Finished Jul 13 06:58:58 PM PDT 24
Peak memory 214884 kb
Host smart-4b4d0db1-0862-40b9-a754-68826337b506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1628125636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1628125636
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.785856535
Short name T276
Test name
Test status
Simulation time 335808821 ps
CPU time 2.52 seconds
Started Jul 13 06:58:43 PM PDT 24
Finished Jul 13 06:58:46 PM PDT 24
Peak memory 206616 kb
Host smart-699608d6-d525-4508-a09a-4264967c281b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=785856535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.785856535
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.961006342
Short name T2822
Test name
Test status
Simulation time 241572260 ps
CPU time 1.99 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 218592 kb
Host smart-40c13a76-7ce8-420e-8d4c-155831ea15b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961006342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.961006342
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2439139269
Short name T2780
Test name
Test status
Simulation time 131549441 ps
CPU time 1.01 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:50 PM PDT 24
Peak memory 206560 kb
Host smart-63c60137-32a0-4f3f-bcde-657ceb28b835
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2439139269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2439139269
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2366102611
Short name T2835
Test name
Test status
Simulation time 33183135 ps
CPU time 0.69 seconds
Started Jul 13 06:58:43 PM PDT 24
Finished Jul 13 06:58:44 PM PDT 24
Peak memory 206364 kb
Host smart-ac73bf8b-869c-43d0-8915-f7055e2a8ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2366102611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2366102611
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.90203603
Short name T2807
Test name
Test status
Simulation time 94991518 ps
CPU time 1.28 seconds
Started Jul 13 06:58:43 PM PDT 24
Finished Jul 13 06:58:45 PM PDT 24
Peak memory 206576 kb
Host smart-31f1e14e-161c-48f4-9127-80fe52c392a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=90203603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.90203603
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3289328606
Short name T2838
Test name
Test status
Simulation time 204464080 ps
CPU time 2.2 seconds
Started Jul 13 06:58:42 PM PDT 24
Finished Jul 13 06:58:45 PM PDT 24
Peak memory 206668 kb
Host smart-cb217ec2-6d6c-4a58-a04f-37f63070f9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3289328606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3289328606
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.300496785
Short name T2797
Test name
Test status
Simulation time 98708383 ps
CPU time 1.32 seconds
Started Jul 13 06:58:57 PM PDT 24
Finished Jul 13 06:58:59 PM PDT 24
Peak memory 214880 kb
Host smart-4b8d2227-1f75-4572-9cd3-2fafa5d874a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300496785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.300496785
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3414236214
Short name T232
Test name
Test status
Simulation time 88105922 ps
CPU time 1.04 seconds
Started Jul 13 06:58:57 PM PDT 24
Finished Jul 13 06:58:59 PM PDT 24
Peak memory 206596 kb
Host smart-d741e6a5-f123-455c-99bf-dffbbf5c9b16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3414236214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3414236214
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4098384789
Short name T2852
Test name
Test status
Simulation time 48079475 ps
CPU time 0.69 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:54 PM PDT 24
Peak memory 206380 kb
Host smart-e94ab397-a254-41f6-8e6f-5e4cf5a03740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098384789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.4098384789
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2591639033
Short name T241
Test name
Test status
Simulation time 93316693 ps
CPU time 1.09 seconds
Started Jul 13 06:58:56 PM PDT 24
Finished Jul 13 06:58:58 PM PDT 24
Peak memory 206572 kb
Host smart-7d41cf4e-b258-46e3-8e32-30a83d043a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2591639033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2591639033
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1619636225
Short name T214
Test name
Test status
Simulation time 138499084 ps
CPU time 2.95 seconds
Started Jul 13 06:58:43 PM PDT 24
Finished Jul 13 06:58:46 PM PDT 24
Peak memory 222316 kb
Host smart-bcd071a2-b7b8-433a-9ef8-23c042869ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1619636225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1619636225
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1743967622
Short name T268
Test name
Test status
Simulation time 2186729127 ps
CPU time 6.73 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:58 PM PDT 24
Peak memory 206660 kb
Host smart-ab74ba02-6d5b-4433-8252-bf9c48602035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1743967622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1743967622
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1177519091
Short name T216
Test name
Test status
Simulation time 192435943 ps
CPU time 1.88 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 214856 kb
Host smart-4459fb9a-76c9-4336-8af6-85a9a9f42f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177519091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1177519091
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.292959894
Short name T2754
Test name
Test status
Simulation time 53472584 ps
CPU time 1.06 seconds
Started Jul 13 06:58:57 PM PDT 24
Finished Jul 13 06:58:59 PM PDT 24
Peak memory 206504 kb
Host smart-d7445be1-6fbb-4901-9fb2-57e66ce881de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=292959894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.292959894
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4116695163
Short name T2752
Test name
Test status
Simulation time 110955473 ps
CPU time 1.24 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:54 PM PDT 24
Peak memory 206620 kb
Host smart-06f4ec15-d516-4204-adb3-962a63e64c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4116695163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.4116695163
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.792356705
Short name T2798
Test name
Test status
Simulation time 67834240 ps
CPU time 1.33 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:56 PM PDT 24
Peak memory 206600 kb
Host smart-aca03fa1-3865-44f6-8aef-26173d1574ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=792356705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.792356705
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.648245953
Short name T267
Test name
Test status
Simulation time 1405800761 ps
CPU time 5.55 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:59 PM PDT 24
Peak memory 206556 kb
Host smart-9df360f1-41f0-48c9-a2d4-987c60eb3c15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=648245953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.648245953
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2253261143
Short name T2851
Test name
Test status
Simulation time 84885774 ps
CPU time 1.16 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 216544 kb
Host smart-6da3097d-cd17-4f49-8ba7-994194bc2e82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253261143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2253261143
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.765199038
Short name T238
Test name
Test status
Simulation time 80262229 ps
CPU time 1.07 seconds
Started Jul 13 06:58:54 PM PDT 24
Finished Jul 13 06:58:56 PM PDT 24
Peak memory 206500 kb
Host smart-6fdba269-2fda-4a05-9a22-b450332d8e4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=765199038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.765199038
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2677221211
Short name T2813
Test name
Test status
Simulation time 165919666 ps
CPU time 1.22 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:54 PM PDT 24
Peak memory 206560 kb
Host smart-9e25020a-693b-4d48-917f-06c53adbd74d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2677221211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2677221211
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1625800324
Short name T2768
Test name
Test status
Simulation time 445416586 ps
CPU time 2.76 seconds
Started Jul 13 06:58:59 PM PDT 24
Finished Jul 13 06:59:03 PM PDT 24
Peak memory 206624 kb
Host smart-32e4fac3-a36e-4df2-b709-58b0190a096c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1625800324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1625800324
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.867937709
Short name T2763
Test name
Test status
Simulation time 95370988 ps
CPU time 1.15 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:56 PM PDT 24
Peak memory 216644 kb
Host smart-aef95953-34f4-4e16-9601-390b053de3e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867937709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.867937709
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.457465810
Short name T2831
Test name
Test status
Simulation time 79628075 ps
CPU time 0.98 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:54 PM PDT 24
Peak memory 206496 kb
Host smart-3c1932d4-2419-436d-879d-58cde46f7bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=457465810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.457465810
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2587203581
Short name T257
Test name
Test status
Simulation time 63829497 ps
CPU time 0.7 seconds
Started Jul 13 06:58:58 PM PDT 24
Finished Jul 13 06:59:00 PM PDT 24
Peak memory 206356 kb
Host smart-0188f2ac-2096-41c5-8684-a4bff3e0717e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2587203581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2587203581
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2289518971
Short name T2801
Test name
Test status
Simulation time 207648994 ps
CPU time 1.26 seconds
Started Jul 13 06:59:00 PM PDT 24
Finished Jul 13 06:59:03 PM PDT 24
Peak memory 206568 kb
Host smart-1dbe97cc-8adf-49ff-92d6-b792693eb554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2289518971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2289518971
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1606872976
Short name T2841
Test name
Test status
Simulation time 108614786 ps
CPU time 1.46 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:54 PM PDT 24
Peak memory 222508 kb
Host smart-40bfac76-4456-4d7f-936f-4c47f6f23969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606872976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1606872976
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1706737132
Short name T203
Test name
Test status
Simulation time 1027779597 ps
CPU time 3.23 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:58 PM PDT 24
Peak memory 206636 kb
Host smart-b983690c-dfd3-49b7-9eea-a50403c7494b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1706737132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1706737132
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3632139618
Short name T2824
Test name
Test status
Simulation time 95907612 ps
CPU time 2.19 seconds
Started Jul 13 06:58:54 PM PDT 24
Finished Jul 13 06:58:57 PM PDT 24
Peak memory 214812 kb
Host smart-17c49874-4df4-42fd-986a-a8fbd1037038
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632139618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3632139618
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.348516447
Short name T2770
Test name
Test status
Simulation time 88251108 ps
CPU time 0.82 seconds
Started Jul 13 06:58:54 PM PDT 24
Finished Jul 13 06:58:56 PM PDT 24
Peak memory 206384 kb
Host smart-887cde04-fdc3-40ff-ad40-e089d90bc208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=348516447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.348516447
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3096762587
Short name T2791
Test name
Test status
Simulation time 39808499 ps
CPU time 0.64 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:55 PM PDT 24
Peak memory 206368 kb
Host smart-0e40423f-aeb4-48b3-8e53-47c48855ba21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3096762587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3096762587
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.443564381
Short name T243
Test name
Test status
Simulation time 134355634 ps
CPU time 1.77 seconds
Started Jul 13 06:58:54 PM PDT 24
Finished Jul 13 06:58:57 PM PDT 24
Peak memory 206600 kb
Host smart-04916891-313c-44d5-8de2-8d999e2c6ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=443564381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.443564381
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3852696757
Short name T2803
Test name
Test status
Simulation time 60789408 ps
CPU time 1.62 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:55 PM PDT 24
Peak memory 206616 kb
Host smart-418c9382-25fd-4b4a-9738-a496343574b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3852696757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3852696757
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2177543226
Short name T275
Test name
Test status
Simulation time 387066867 ps
CPU time 2.87 seconds
Started Jul 13 06:58:55 PM PDT 24
Finished Jul 13 06:58:58 PM PDT 24
Peak memory 206596 kb
Host smart-f4db44e6-0e7a-4767-b2c2-fc8773fe2933
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2177543226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2177543226
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3208198684
Short name T2787
Test name
Test status
Simulation time 69108663 ps
CPU time 1.12 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:54 PM PDT 24
Peak memory 214816 kb
Host smart-8bc16506-7cfc-4500-b541-f483233cc9e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208198684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3208198684
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1642352870
Short name T228
Test name
Test status
Simulation time 64972556 ps
CPU time 0.85 seconds
Started Jul 13 06:58:56 PM PDT 24
Finished Jul 13 06:58:57 PM PDT 24
Peak memory 206416 kb
Host smart-0f658104-f0be-4538-9243-f2cff00ab669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1642352870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1642352870
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1973906213
Short name T255
Test name
Test status
Simulation time 85102899 ps
CPU time 0.68 seconds
Started Jul 13 06:59:00 PM PDT 24
Finished Jul 13 06:59:02 PM PDT 24
Peak memory 206364 kb
Host smart-cf202a28-7d9f-4c81-9066-2cdd4b9a0a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1973906213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1973906213
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2968102258
Short name T178
Test name
Test status
Simulation time 207342914 ps
CPU time 1.12 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 206556 kb
Host smart-63231d9a-682f-4833-beb3-7dd89e7f13cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2968102258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2968102258
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.481235764
Short name T2817
Test name
Test status
Simulation time 141928452 ps
CPU time 1.58 seconds
Started Jul 13 06:58:52 PM PDT 24
Finished Jul 13 06:58:54 PM PDT 24
Peak memory 206676 kb
Host smart-974f0618-418f-43ca-b094-6998020bec57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=481235764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.481235764
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1598624690
Short name T2821
Test name
Test status
Simulation time 83266601 ps
CPU time 1.33 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:07 PM PDT 24
Peak memory 214868 kb
Host smart-469a2f21-6f8b-4c4b-af01-7be0d9530144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598624690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1598624690
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.964815481
Short name T2806
Test name
Test status
Simulation time 72533116 ps
CPU time 0.83 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:55 PM PDT 24
Peak memory 206424 kb
Host smart-b78f7116-bb56-402b-a36d-29e11211d7b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=964815481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.964815481
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1203544872
Short name T252
Test name
Test status
Simulation time 39581212 ps
CPU time 0.68 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 206352 kb
Host smart-d9004f67-8eb5-4ec0-9afb-7c28e108886b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1203544872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1203544872
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2394296547
Short name T2775
Test name
Test status
Simulation time 464073208 ps
CPU time 2.28 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 206604 kb
Host smart-2cf53163-54a0-4914-bb28-863dc569838a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2394296547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2394296547
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.93229069
Short name T2811
Test name
Test status
Simulation time 89075089 ps
CPU time 2.02 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:56 PM PDT 24
Peak memory 222736 kb
Host smart-6cc9420f-dcf4-4bdc-b296-02a96304f271
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=93229069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.93229069
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.504002282
Short name T2796
Test name
Test status
Simulation time 262709389 ps
CPU time 2.55 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:57 PM PDT 24
Peak memory 206632 kb
Host smart-ddec6750-2048-4c94-9ee9-0a9a8df167d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=504002282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.504002282
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2870176835
Short name T2802
Test name
Test status
Simulation time 58535844 ps
CPU time 1 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:05 PM PDT 24
Peak memory 206484 kb
Host smart-3c015af4-4f9c-40cf-8267-2c8dd8fb16ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2870176835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2870176835
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.399241290
Short name T186
Test name
Test status
Simulation time 35213067 ps
CPU time 0.68 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 206280 kb
Host smart-fa112d03-b3e4-4739-b612-51b86a40edb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=399241290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.399241290
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1834677333
Short name T2778
Test name
Test status
Simulation time 147737880 ps
CPU time 1.24 seconds
Started Jul 13 06:59:00 PM PDT 24
Finished Jul 13 06:59:01 PM PDT 24
Peak memory 206592 kb
Host smart-8b5b1d07-1599-477f-bbb1-3c88ea294de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1834677333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1834677333
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1100563656
Short name T2826
Test name
Test status
Simulation time 270388548 ps
CPU time 2.89 seconds
Started Jul 13 06:59:05 PM PDT 24
Finished Jul 13 06:59:10 PM PDT 24
Peak memory 206600 kb
Host smart-930e9feb-c4dd-4e22-962f-f7c789a1f69e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1100563656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1100563656
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3013806275
Short name T272
Test name
Test status
Simulation time 245409804 ps
CPU time 2.46 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:08 PM PDT 24
Peak memory 206540 kb
Host smart-1aca37b5-b1fc-4cde-9109-2fcd5d589473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3013806275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3013806275
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1860501905
Short name T2854
Test name
Test status
Simulation time 159607630 ps
CPU time 3.25 seconds
Started Jul 13 06:58:44 PM PDT 24
Finished Jul 13 06:58:48 PM PDT 24
Peak memory 206504 kb
Host smart-5c3860d9-ff0e-4415-8398-a747746ee0b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1860501905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1860501905
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4064540138
Short name T229
Test name
Test status
Simulation time 863199522 ps
CPU time 5.16 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 206476 kb
Host smart-4a6a6767-9c1b-4308-8c07-ce1154ac999b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4064540138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4064540138
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1307367731
Short name T2774
Test name
Test status
Simulation time 52898922 ps
CPU time 0.79 seconds
Started Jul 13 06:58:40 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 206360 kb
Host smart-6de91065-d5fd-4f86-a892-936a717b76ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1307367731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1307367731
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3192385701
Short name T2767
Test name
Test status
Simulation time 140854168 ps
CPU time 2.81 seconds
Started Jul 13 06:58:40 PM PDT 24
Finished Jul 13 06:58:44 PM PDT 24
Peak memory 214868 kb
Host smart-24534ea9-ce02-463a-b4b2-0947d4853b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192385701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3192385701
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2610786982
Short name T2783
Test name
Test status
Simulation time 58180444 ps
CPU time 0.99 seconds
Started Jul 13 06:58:39 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 206472 kb
Host smart-c78badee-bde5-4b73-9456-be942f76d0d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2610786982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2610786982
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1197292866
Short name T188
Test name
Test status
Simulation time 38038984 ps
CPU time 0.7 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:40 PM PDT 24
Peak memory 206380 kb
Host smart-6d1f256b-72ee-4deb-b76b-efbed34359a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1197292866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1197292866
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2116604056
Short name T239
Test name
Test status
Simulation time 210654756 ps
CPU time 2.43 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:40 PM PDT 24
Peak memory 214780 kb
Host smart-48efea53-5822-4fec-8ccd-a6011ba7801f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2116604056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2116604056
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3607215449
Short name T2790
Test name
Test status
Simulation time 721690019 ps
CPU time 5.02 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 206460 kb
Host smart-cc4fe087-73fd-4230-b956-b1afcea49259
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3607215449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3607215449
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.4171326464
Short name T2823
Test name
Test status
Simulation time 116797684 ps
CPU time 1.56 seconds
Started Jul 13 06:58:41 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 206556 kb
Host smart-28620ce0-0374-4787-a96a-8b4575af9e72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4171326464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.4171326464
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1371941487
Short name T213
Test name
Test status
Simulation time 134408561 ps
CPU time 3.9 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 214880 kb
Host smart-2aff81f4-9643-4cfa-8cab-f5e83e4932bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1371941487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1371941487
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1365410189
Short name T271
Test name
Test status
Simulation time 411360377 ps
CPU time 2.95 seconds
Started Jul 13 06:58:36 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 206544 kb
Host smart-06646566-df44-4f2f-9b73-2afc2d5b5ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1365410189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1365410189
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2030229874
Short name T2809
Test name
Test status
Simulation time 38196321 ps
CPU time 0.64 seconds
Started Jul 13 06:58:57 PM PDT 24
Finished Jul 13 06:58:58 PM PDT 24
Peak memory 206352 kb
Host smart-19e49e29-966a-4424-9e78-575057ad306e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2030229874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2030229874
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1191182478
Short name T264
Test name
Test status
Simulation time 39668417 ps
CPU time 0.71 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:02 PM PDT 24
Peak memory 206364 kb
Host smart-bcb0da58-3cb4-4467-8a77-961221908470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1191182478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1191182478
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1542500321
Short name T2850
Test name
Test status
Simulation time 39278667 ps
CPU time 0.71 seconds
Started Jul 13 06:59:11 PM PDT 24
Finished Jul 13 06:59:13 PM PDT 24
Peak memory 206376 kb
Host smart-ce7e5c66-06db-40c0-b6f0-640c9302588c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1542500321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1542500321
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1708518884
Short name T253
Test name
Test status
Simulation time 50970269 ps
CPU time 0.72 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 206356 kb
Host smart-f42fa19e-27fe-4f8e-8ef2-953981903700
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1708518884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1708518884
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.710087953
Short name T2853
Test name
Test status
Simulation time 55748688 ps
CPU time 0.72 seconds
Started Jul 13 06:59:05 PM PDT 24
Finished Jul 13 06:59:07 PM PDT 24
Peak memory 206532 kb
Host smart-e7c3c2df-ee7c-485c-b583-3fce0ca86ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=710087953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.710087953
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2408106905
Short name T2765
Test name
Test status
Simulation time 72780026 ps
CPU time 0.69 seconds
Started Jul 13 06:58:58 PM PDT 24
Finished Jul 13 06:58:59 PM PDT 24
Peak memory 206356 kb
Host smart-b9827e40-ae8d-498a-8b45-db765a17b0ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2408106905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2408106905
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1189539354
Short name T2825
Test name
Test status
Simulation time 41066656 ps
CPU time 0.73 seconds
Started Jul 13 06:58:59 PM PDT 24
Finished Jul 13 06:59:01 PM PDT 24
Peak memory 206336 kb
Host smart-84ea2d07-bcdc-4231-8c19-66dcd28e3c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1189539354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1189539354
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3042501540
Short name T254
Test name
Test status
Simulation time 48809331 ps
CPU time 0.67 seconds
Started Jul 13 06:59:00 PM PDT 24
Finished Jul 13 06:59:01 PM PDT 24
Peak memory 206352 kb
Host smart-19d0060f-c9b8-4b91-a299-a3e8a2ea1031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3042501540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3042501540
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1050241208
Short name T2785
Test name
Test status
Simulation time 307257195 ps
CPU time 3.71 seconds
Started Jul 13 06:58:35 PM PDT 24
Finished Jul 13 06:58:40 PM PDT 24
Peak memory 206444 kb
Host smart-6373020a-0759-4c8a-976e-95a6b456b4ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1050241208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1050241208
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2206073082
Short name T2812
Test name
Test status
Simulation time 1067488313 ps
CPU time 8.15 seconds
Started Jul 13 06:58:35 PM PDT 24
Finished Jul 13 06:58:44 PM PDT 24
Peak memory 206528 kb
Host smart-f354b380-d58b-4f34-af81-d8b0394e4108
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2206073082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2206073082
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3992900269
Short name T2789
Test name
Test status
Simulation time 142386997 ps
CPU time 1.01 seconds
Started Jul 13 06:58:41 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 206280 kb
Host smart-bfc1e089-0cca-443b-8d64-97221f36ee51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3992900269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3992900269
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.184561126
Short name T2758
Test name
Test status
Simulation time 109121458 ps
CPU time 1.58 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 214916 kb
Host smart-b3d8e5d6-dc4f-4f30-bcf6-e7908409f343
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184561126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.184561126
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1285313536
Short name T2818
Test name
Test status
Simulation time 78932524 ps
CPU time 1.07 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 206556 kb
Host smart-7a50d8b7-d2c6-4971-86b5-167f3bf852b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1285313536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1285313536
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.179419253
Short name T2846
Test name
Test status
Simulation time 59744949 ps
CPU time 0.7 seconds
Started Jul 13 06:58:40 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 206380 kb
Host smart-564cfa6e-ac7c-4ea2-b454-4f0a3542a99b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=179419253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.179419253
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3984237312
Short name T2827
Test name
Test status
Simulation time 209944153 ps
CPU time 2.48 seconds
Started Jul 13 06:58:45 PM PDT 24
Finished Jul 13 06:58:48 PM PDT 24
Peak memory 214804 kb
Host smart-c9db3813-6754-4c23-b319-817f10d1c1c0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3984237312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3984237312
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1110879078
Short name T2810
Test name
Test status
Simulation time 162513908 ps
CPU time 4.05 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 206516 kb
Host smart-7de289dd-107e-4ebf-96c4-81abc46ea7c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1110879078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1110879078
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1055422927
Short name T246
Test name
Test status
Simulation time 76956814 ps
CPU time 1.14 seconds
Started Jul 13 06:58:40 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 206460 kb
Host smart-f8bdb906-8124-4d83-bb48-832a0f9952c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1055422927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1055422927
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.677162856
Short name T2782
Test name
Test status
Simulation time 264720474 ps
CPU time 2.58 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 214744 kb
Host smart-90d058db-db60-4950-88c8-b56b97f2d404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=677162856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.677162856
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1005654067
Short name T277
Test name
Test status
Simulation time 817222720 ps
CPU time 3.15 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 206608 kb
Host smart-1bc68785-b21e-4e98-a217-b6004e7eb95f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1005654067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1005654067
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2399925552
Short name T2781
Test name
Test status
Simulation time 47540256 ps
CPU time 0.7 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206364 kb
Host smart-a8b68f06-79cd-4e45-a403-d9e96f47ce27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2399925552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2399925552
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.793209802
Short name T2820
Test name
Test status
Simulation time 70022525 ps
CPU time 0.77 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206348 kb
Host smart-c8259874-d80f-40c1-a569-fec5d5c72b45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=793209802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.793209802
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.427365703
Short name T256
Test name
Test status
Simulation time 41445651 ps
CPU time 0.69 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206376 kb
Host smart-2f5a281f-1bc3-4e9f-b740-da692648f7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=427365703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.427365703
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3178585703
Short name T261
Test name
Test status
Simulation time 51019147 ps
CPU time 0.69 seconds
Started Jul 13 06:59:00 PM PDT 24
Finished Jul 13 06:59:01 PM PDT 24
Peak memory 206356 kb
Host smart-1e91eb8c-6d33-4a14-a94a-e96f9e774116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3178585703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3178585703
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.651216294
Short name T2842
Test name
Test status
Simulation time 73885015 ps
CPU time 0.75 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:05 PM PDT 24
Peak memory 206344 kb
Host smart-7b7882af-6991-4d97-8029-0ef194d46468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=651216294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.651216294
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4148217323
Short name T2816
Test name
Test status
Simulation time 43044622 ps
CPU time 0.7 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 206352 kb
Host smart-175d0124-58f3-4588-b76e-9122646711dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4148217323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4148217323
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3392967764
Short name T250
Test name
Test status
Simulation time 39532423 ps
CPU time 0.69 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206388 kb
Host smart-34fcea1c-8d30-437f-8225-80711a9f9a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3392967764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3392967764
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1876194923
Short name T2848
Test name
Test status
Simulation time 43978068 ps
CPU time 0.77 seconds
Started Jul 13 06:59:01 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206372 kb
Host smart-a025b26e-2d5a-4f00-bfd7-d73b3a57d00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1876194923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1876194923
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1152081139
Short name T2819
Test name
Test status
Simulation time 42250912 ps
CPU time 0.64 seconds
Started Jul 13 06:58:58 PM PDT 24
Finished Jul 13 06:59:00 PM PDT 24
Peak memory 206372 kb
Host smart-0f5d8c36-0a4a-41df-b08c-34f4563da174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1152081139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1152081139
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1729750778
Short name T2808
Test name
Test status
Simulation time 316872528 ps
CPU time 3.49 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 206548 kb
Host smart-8eaa8467-e499-4761-989b-95bcff29fb79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1729750778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1729750778
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1499249175
Short name T2795
Test name
Test status
Simulation time 1194201472 ps
CPU time 8.56 seconds
Started Jul 13 06:58:39 PM PDT 24
Finished Jul 13 06:58:48 PM PDT 24
Peak memory 206556 kb
Host smart-7b5798d4-82b5-4c92-9b57-f802b6e79420
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1499249175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1499249175
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.222570378
Short name T2772
Test name
Test status
Simulation time 120085268 ps
CPU time 0.91 seconds
Started Jul 13 06:58:40 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 206360 kb
Host smart-38370fa4-36ff-43d1-9b62-d6a5d70a6976
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=222570378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.222570378
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1696804558
Short name T176
Test name
Test status
Simulation time 168141125 ps
CPU time 2.62 seconds
Started Jul 13 06:58:36 PM PDT 24
Finished Jul 13 06:58:40 PM PDT 24
Peak memory 214808 kb
Host smart-bcceb561-5fce-4782-babd-8766a3a71d0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696804558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1696804558
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2898093715
Short name T230
Test name
Test status
Simulation time 100506887 ps
CPU time 0.96 seconds
Started Jul 13 06:58:36 PM PDT 24
Finished Jul 13 06:58:38 PM PDT 24
Peak memory 206500 kb
Host smart-fb698791-ed64-41cc-8f2f-cabaf54ca901
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2898093715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2898093715
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.234834902
Short name T266
Test name
Test status
Simulation time 54628595 ps
CPU time 0.7 seconds
Started Jul 13 06:58:39 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 206384 kb
Host smart-0d1f5813-1977-4597-b7c8-000d38961bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=234834902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.234834902
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3722357975
Short name T240
Test name
Test status
Simulation time 117548632 ps
CPU time 1.52 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:40 PM PDT 24
Peak memory 216096 kb
Host smart-cb24ae5a-0859-4cc6-8a75-6275546c7a0a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3722357975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3722357975
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.530282450
Short name T2840
Test name
Test status
Simulation time 644735169 ps
CPU time 4.34 seconds
Started Jul 13 06:58:40 PM PDT 24
Finished Jul 13 06:58:46 PM PDT 24
Peak memory 206364 kb
Host smart-d5f8d84c-cd2d-46fb-a8b4-f1db9c5cb10c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=530282450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.530282450
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1997891910
Short name T2847
Test name
Test status
Simulation time 122906472 ps
CPU time 1.72 seconds
Started Jul 13 06:58:34 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 206648 kb
Host smart-5165889e-8776-4188-819c-015f0784d243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997891910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1997891910
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3931527281
Short name T2764
Test name
Test status
Simulation time 361278515 ps
CPU time 3.78 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:43 PM PDT 24
Peak memory 214848 kb
Host smart-08e2cdf7-9f33-414d-bccf-3f3f06517d65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3931527281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3931527281
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1946395211
Short name T270
Test name
Test status
Simulation time 709264698 ps
CPU time 4.54 seconds
Started Jul 13 06:58:40 PM PDT 24
Finished Jul 13 06:58:46 PM PDT 24
Peak memory 206564 kb
Host smart-fbdacd5a-923f-4128-b4b7-d1d3fdf3e23c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1946395211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1946395211
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1749058845
Short name T2828
Test name
Test status
Simulation time 51964758 ps
CPU time 0.66 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206600 kb
Host smart-31ec6750-c54f-4882-b6b8-f962941189d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1749058845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1749058845
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4022293898
Short name T2837
Test name
Test status
Simulation time 31761499 ps
CPU time 0.67 seconds
Started Jul 13 06:59:00 PM PDT 24
Finished Jul 13 06:59:01 PM PDT 24
Peak memory 206348 kb
Host smart-4b4495ff-8320-4910-9aaa-6e60077f59ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4022293898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4022293898
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.65836300
Short name T189
Test name
Test status
Simulation time 29351490 ps
CPU time 0.68 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206384 kb
Host smart-d7b240a4-b31f-4b5d-90ad-0797f7c51974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=65836300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.65836300
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.369156909
Short name T263
Test name
Test status
Simulation time 78194348 ps
CPU time 0.78 seconds
Started Jul 13 06:59:05 PM PDT 24
Finished Jul 13 06:59:08 PM PDT 24
Peak memory 206380 kb
Host smart-92e83e27-6a0b-4e88-a07e-a2c8ed99f437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=369156909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.369156909
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2090151849
Short name T2814
Test name
Test status
Simulation time 33594821 ps
CPU time 0.68 seconds
Started Jul 13 06:59:00 PM PDT 24
Finished Jul 13 06:59:01 PM PDT 24
Peak memory 206352 kb
Host smart-2c3dacc1-6f2f-4e4d-a7e7-f12b346ffdae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2090151849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2090151849
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2001066517
Short name T2793
Test name
Test status
Simulation time 43925292 ps
CPU time 0.7 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 06:59:07 PM PDT 24
Peak memory 206364 kb
Host smart-62e37b7a-81f0-43e5-bc71-b9cc319d5b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2001066517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2001066517
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3050390960
Short name T265
Test name
Test status
Simulation time 40771780 ps
CPU time 0.7 seconds
Started Jul 13 06:59:04 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 206352 kb
Host smart-19bee671-c1f9-4ef8-b7ed-a39869f35fdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3050390960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3050390960
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2121335310
Short name T2792
Test name
Test status
Simulation time 38457608 ps
CPU time 0.67 seconds
Started Jul 13 06:59:03 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 206356 kb
Host smart-a62c5a39-c34b-4ee4-9989-a13602d664b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2121335310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2121335310
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2971394898
Short name T2777
Test name
Test status
Simulation time 37296616 ps
CPU time 0.73 seconds
Started Jul 13 06:59:02 PM PDT 24
Finished Jul 13 06:59:04 PM PDT 24
Peak memory 206356 kb
Host smart-8541f8cf-65b1-4462-92a0-176fabd8bfaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2971394898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2971394898
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.339223994
Short name T177
Test name
Test status
Simulation time 68819708 ps
CPU time 1.53 seconds
Started Jul 13 06:58:51 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 214836 kb
Host smart-988c1adf-4231-4834-b4c5-d74d91907219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339223994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.339223994
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.334955000
Short name T2759
Test name
Test status
Simulation time 63608677 ps
CPU time 0.99 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:39 PM PDT 24
Peak memory 206496 kb
Host smart-68563428-e225-4b2b-83cc-9e68b8784bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=334955000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.334955000
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1103625709
Short name T2779
Test name
Test status
Simulation time 54014684 ps
CPU time 1.06 seconds
Started Jul 13 06:58:35 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 206552 kb
Host smart-120dd2a5-2b88-48e4-91bb-30b8e90c6065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1103625709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1103625709
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3920891288
Short name T2788
Test name
Test status
Simulation time 98526009 ps
CPU time 2.44 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 216012 kb
Host smart-6f785235-2999-418b-a2b5-30e6c73890e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3920891288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3920891288
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3784839226
Short name T2832
Test name
Test status
Simulation time 778079357 ps
CPU time 4.64 seconds
Started Jul 13 06:58:40 PM PDT 24
Finished Jul 13 06:58:45 PM PDT 24
Peak memory 206564 kb
Host smart-7122e4dd-6e8c-4a44-ab88-eeab010a246e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3784839226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3784839226
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.262175127
Short name T2800
Test name
Test status
Simulation time 175660670 ps
CPU time 1.92 seconds
Started Jul 13 06:58:37 PM PDT 24
Finished Jul 13 06:58:40 PM PDT 24
Peak memory 214872 kb
Host smart-d885bba3-3e6b-43ae-8b97-ceb89da52da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262175127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.262175127
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2940380547
Short name T2844
Test name
Test status
Simulation time 73473964 ps
CPU time 0.97 seconds
Started Jul 13 06:58:36 PM PDT 24
Finished Jul 13 06:58:38 PM PDT 24
Peak memory 206536 kb
Host smart-8d65e24d-34b7-4502-85a1-92e8730cfb5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2940380547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2940380547
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1546359434
Short name T2771
Test name
Test status
Simulation time 43106444 ps
CPU time 0.72 seconds
Started Jul 13 06:58:35 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 206348 kb
Host smart-da47c2ab-695e-4a93-be7c-56db4617d80b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1546359434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1546359434
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1281536088
Short name T2849
Test name
Test status
Simulation time 134828559 ps
CPU time 1.1 seconds
Started Jul 13 06:58:36 PM PDT 24
Finished Jul 13 06:58:38 PM PDT 24
Peak memory 206560 kb
Host smart-28a3974a-4115-425d-8479-2d50a11f7ccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1281536088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1281536088
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3460577674
Short name T202
Test name
Test status
Simulation time 131913564 ps
CPU time 1.68 seconds
Started Jul 13 06:58:38 PM PDT 24
Finished Jul 13 06:58:41 PM PDT 24
Peak memory 214756 kb
Host smart-a215dbec-2858-4661-b82c-3d76fcfb0534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3460577674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3460577674
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1423239043
Short name T2839
Test name
Test status
Simulation time 70758388 ps
CPU time 1.4 seconds
Started Jul 13 06:58:48 PM PDT 24
Finished Jul 13 06:58:50 PM PDT 24
Peak memory 214800 kb
Host smart-f4d2659b-9c6b-4850-b09f-643e0679144d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423239043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1423239043
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.601064694
Short name T2756
Test name
Test status
Simulation time 117674511 ps
CPU time 1.03 seconds
Started Jul 13 06:58:50 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 206480 kb
Host smart-08842c37-f19f-4ea1-8e77-8214bcdf7b06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=601064694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.601064694
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.344273710
Short name T2845
Test name
Test status
Simulation time 42083427 ps
CPU time 0.7 seconds
Started Jul 13 06:58:48 PM PDT 24
Finished Jul 13 06:58:49 PM PDT 24
Peak memory 206348 kb
Host smart-a03558a8-009b-4719-9693-41bda2a0b3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=344273710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.344273710
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2398512276
Short name T2755
Test name
Test status
Simulation time 93617138 ps
CPU time 1.68 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 206420 kb
Host smart-f90b8098-91f3-4e2a-bfef-eb7e00f38437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2398512276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2398512276
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.115434604
Short name T215
Test name
Test status
Simulation time 216707542 ps
CPU time 2.23 seconds
Started Jul 13 06:58:35 PM PDT 24
Finished Jul 13 06:58:38 PM PDT 24
Peak memory 206604 kb
Host smart-8b07c686-e92b-4e0d-9bc4-d4926454e838
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=115434604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.115434604
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1605730139
Short name T2855
Test name
Test status
Simulation time 993435005 ps
CPU time 3.31 seconds
Started Jul 13 06:58:50 PM PDT 24
Finished Jul 13 06:58:54 PM PDT 24
Peak memory 206568 kb
Host smart-c6df9ced-620b-4f48-9eef-f517ae91c100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1605730139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1605730139
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2409868852
Short name T2762
Test name
Test status
Simulation time 165809408 ps
CPU time 1.68 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 214804 kb
Host smart-fc3a136c-23b0-4e8a-93b7-ac4bdc506c7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409868852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2409868852
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3199929928
Short name T2757
Test name
Test status
Simulation time 52452161 ps
CPU time 0.84 seconds
Started Jul 13 06:58:43 PM PDT 24
Finished Jul 13 06:58:45 PM PDT 24
Peak memory 206344 kb
Host smart-1126a342-ee2d-4355-be40-3a0ac4c57129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3199929928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3199929928
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4115080807
Short name T2829
Test name
Test status
Simulation time 36819158 ps
CPU time 0.73 seconds
Started Jul 13 06:58:44 PM PDT 24
Finished Jul 13 06:58:45 PM PDT 24
Peak memory 206332 kb
Host smart-261bc079-280f-4e37-887e-193ca4759e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4115080807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4115080807
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3335395678
Short name T244
Test name
Test status
Simulation time 144485367 ps
CPU time 1.24 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 206320 kb
Host smart-2f22ea85-f485-4d26-89d7-b366084fe1f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3335395678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3335395678
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3555085837
Short name T2805
Test name
Test status
Simulation time 317123867 ps
CPU time 3.59 seconds
Started Jul 13 06:58:44 PM PDT 24
Finished Jul 13 06:58:49 PM PDT 24
Peak memory 222144 kb
Host smart-ed84e17e-e9df-4afc-b007-0a08fd1baacf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3555085837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3555085837
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3737542312
Short name T274
Test name
Test status
Simulation time 1607271591 ps
CPU time 5.43 seconds
Started Jul 13 06:58:44 PM PDT 24
Finished Jul 13 06:58:50 PM PDT 24
Peak memory 206616 kb
Host smart-831c4cf0-3dfd-47b8-ac11-3be5be0f52ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3737542312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3737542312
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4228176359
Short name T221
Test name
Test status
Simulation time 172490991 ps
CPU time 2.03 seconds
Started Jul 13 06:58:43 PM PDT 24
Finished Jul 13 06:58:45 PM PDT 24
Peak memory 214816 kb
Host smart-00d60b05-b10f-4c07-ab7f-5b9388c464cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228176359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.4228176359
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3034090015
Short name T234
Test name
Test status
Simulation time 94911809 ps
CPU time 1.11 seconds
Started Jul 13 06:58:45 PM PDT 24
Finished Jul 13 06:58:47 PM PDT 24
Peak memory 206420 kb
Host smart-bee3f092-6089-4325-b0e2-3e9121dee63b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3034090015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3034090015
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4101575495
Short name T2773
Test name
Test status
Simulation time 37035138 ps
CPU time 0.68 seconds
Started Jul 13 06:58:50 PM PDT 24
Finished Jul 13 06:58:51 PM PDT 24
Peak memory 206356 kb
Host smart-4dc600a6-971c-4f4d-8393-13da25078578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4101575495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4101575495
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2556990915
Short name T204
Test name
Test status
Simulation time 122724619 ps
CPU time 1.11 seconds
Started Jul 13 06:58:43 PM PDT 24
Finished Jul 13 06:58:45 PM PDT 24
Peak memory 206584 kb
Host smart-3ae1aeb3-9ab8-4dd5-a150-a234591781dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2556990915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2556990915
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.962189789
Short name T2799
Test name
Test status
Simulation time 165578956 ps
CPU time 1.77 seconds
Started Jul 13 06:58:53 PM PDT 24
Finished Jul 13 06:58:56 PM PDT 24
Peak memory 206636 kb
Host smart-8435006b-9958-4730-a469-740443b0f79d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=962189789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.962189789
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.445123883
Short name T269
Test name
Test status
Simulation time 458556609 ps
CPU time 2.9 seconds
Started Jul 13 06:58:49 PM PDT 24
Finished Jul 13 06:58:52 PM PDT 24
Peak memory 206540 kb
Host smart-ff907465-cb24-4c1c-bc89-230dbcce426f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=445123883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.445123883
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1554368479
Short name T957
Test name
Test status
Simulation time 52437276 ps
CPU time 0.74 seconds
Started Jul 13 07:07:52 PM PDT 24
Finished Jul 13 07:07:54 PM PDT 24
Peak memory 206940 kb
Host smart-5d79b1fb-586c-455a-9825-f9af81ec0b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1554368479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1554368479
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1795259623
Short name T2488
Test name
Test status
Simulation time 4174508803 ps
CPU time 5.07 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:07:19 PM PDT 24
Peak memory 206900 kb
Host smart-1dddf223-c901-4cc2-8cd2-5a13f1987e47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1795259623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.1795259623
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2522528060
Short name T432
Test name
Test status
Simulation time 13357535941 ps
CPU time 12.19 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:07:26 PM PDT 24
Peak memory 206924 kb
Host smart-7c068573-6b67-4dca-ae73-cda898ec3711
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2522528060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2522528060
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.407237061
Short name T1977
Test name
Test status
Simulation time 23471136936 ps
CPU time 23.05 seconds
Started Jul 13 07:07:11 PM PDT 24
Finished Jul 13 07:07:35 PM PDT 24
Peak memory 207076 kb
Host smart-c6c24d38-b02f-45c2-8152-3735f93a597e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=407237061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.407237061
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1875773385
Short name T1490
Test name
Test status
Simulation time 140982758 ps
CPU time 0.81 seconds
Started Jul 13 07:07:11 PM PDT 24
Finished Jul 13 07:07:12 PM PDT 24
Peak memory 206864 kb
Host smart-960394e8-08cf-4300-8ff7-3af5ea61bef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18757
73385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1875773385
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1910542332
Short name T792
Test name
Test status
Simulation time 184335677 ps
CPU time 0.84 seconds
Started Jul 13 07:07:12 PM PDT 24
Finished Jul 13 07:07:14 PM PDT 24
Peak memory 206852 kb
Host smart-f47c6aba-0320-49ba-8067-708195987f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
42332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1910542332
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.4143055019
Short name T519
Test name
Test status
Simulation time 1425531894 ps
CPU time 3.32 seconds
Started Jul 13 07:07:12 PM PDT 24
Finished Jul 13 07:07:16 PM PDT 24
Peak memory 207080 kb
Host smart-b527f783-ae00-4207-bf24-603ca4b663e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41430
55019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.4143055019
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2926053480
Short name T1371
Test name
Test status
Simulation time 13498042607 ps
CPU time 22.94 seconds
Started Jul 13 07:07:12 PM PDT 24
Finished Jul 13 07:07:36 PM PDT 24
Peak memory 207148 kb
Host smart-8df1770a-1a6d-4270-8deb-79fd111846a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29260
53480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2926053480
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.4117879956
Short name T454
Test name
Test status
Simulation time 500021696 ps
CPU time 1.44 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:07:15 PM PDT 24
Peak memory 206848 kb
Host smart-2fff8943-0e6e-4372-8628-f1b4434b373a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41178
79956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.4117879956
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.875264115
Short name T2634
Test name
Test status
Simulation time 139884523 ps
CPU time 0.75 seconds
Started Jul 13 07:07:14 PM PDT 24
Finished Jul 13 07:07:15 PM PDT 24
Peak memory 206864 kb
Host smart-9461ce5c-650c-4fe3-b629-77113deda491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87526
4115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.875264115
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3885041575
Short name T1422
Test name
Test status
Simulation time 5154455949 ps
CPU time 32.2 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:07:46 PM PDT 24
Peak memory 207068 kb
Host smart-ca849c71-cb6a-42a1-81e1-3cec8bb0670a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38850
41575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3885041575
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1323186176
Short name T412
Test name
Test status
Simulation time 33584686 ps
CPU time 0.65 seconds
Started Jul 13 07:07:12 PM PDT 24
Finished Jul 13 07:07:13 PM PDT 24
Peak memory 206860 kb
Host smart-94976128-dc97-4172-93d5-7b7c50686409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13231
86176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1323186176
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3056691400
Short name T1179
Test name
Test status
Simulation time 897986190 ps
CPU time 2.01 seconds
Started Jul 13 07:07:10 PM PDT 24
Finished Jul 13 07:07:12 PM PDT 24
Peak memory 207012 kb
Host smart-a0c7d484-c75b-4787-8eb8-92fa2813b2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30566
91400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3056691400
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1961616040
Short name T1072
Test name
Test status
Simulation time 319888480 ps
CPU time 1.87 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:07:16 PM PDT 24
Peak memory 207008 kb
Host smart-cf7ae9bf-c3e9-4c6e-b215-da7a8ab1c570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19616
16040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1961616040
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2538030383
Short name T506
Test name
Test status
Simulation time 89175626118 ps
CPU time 126.42 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:09:21 PM PDT 24
Peak memory 207088 kb
Host smart-6727ad32-0965-47e6-8ec1-bfd90bb60d83
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2538030383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2538030383
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.410478640
Short name T716
Test name
Test status
Simulation time 102145271275 ps
CPU time 156.02 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:09:50 PM PDT 24
Peak memory 207120 kb
Host smart-1f90a4f4-c130-4f07-908d-2870c3efdb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410478640 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.410478640
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1197069674
Short name T318
Test name
Test status
Simulation time 109097094328 ps
CPU time 163.07 seconds
Started Jul 13 07:07:12 PM PDT 24
Finished Jul 13 07:09:56 PM PDT 24
Peak memory 207080 kb
Host smart-24966dd1-8750-4895-ad15-464e5724133f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1197069674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1197069674
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.1779329062
Short name T655
Test name
Test status
Simulation time 110142147617 ps
CPU time 160.7 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:09:55 PM PDT 24
Peak memory 207232 kb
Host smart-268793fa-d538-4a89-a3eb-6f0c2109e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779329062 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.1779329062
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.2801139210
Short name T1973
Test name
Test status
Simulation time 104163501670 ps
CPU time 155.03 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:09:49 PM PDT 24
Peak memory 207076 kb
Host smart-c76844e4-9fd4-4bd0-a548-6eb5686a1841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28011
39210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2801139210
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.305779992
Short name T2155
Test name
Test status
Simulation time 198335027 ps
CPU time 0.87 seconds
Started Jul 13 07:07:23 PM PDT 24
Finished Jul 13 07:07:24 PM PDT 24
Peak memory 206860 kb
Host smart-4db6736c-3e5a-466d-a164-e6df9c029041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30577
9992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.305779992
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.703372309
Short name T2251
Test name
Test status
Simulation time 182500007 ps
CPU time 0.77 seconds
Started Jul 13 07:07:24 PM PDT 24
Finished Jul 13 07:07:25 PM PDT 24
Peak memory 206848 kb
Host smart-a3a80f17-f85a-4b80-812f-8dad48afce0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70337
2309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.703372309
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3505674516
Short name T391
Test name
Test status
Simulation time 222856958 ps
CPU time 0.89 seconds
Started Jul 13 07:07:20 PM PDT 24
Finished Jul 13 07:07:21 PM PDT 24
Peak memory 206868 kb
Host smart-7cc8965d-f1f5-43d3-acfd-603342b0dc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35056
74516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3505674516
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.172417496
Short name T944
Test name
Test status
Simulation time 5184561686 ps
CPU time 51.49 seconds
Started Jul 13 07:07:13 PM PDT 24
Finished Jul 13 07:08:06 PM PDT 24
Peak memory 207092 kb
Host smart-38d806b1-0676-42a6-8c8b-7f946407b526
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=172417496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.172417496
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1874901298
Short name T1235
Test name
Test status
Simulation time 12422598279 ps
CPU time 96.21 seconds
Started Jul 13 07:07:21 PM PDT 24
Finished Jul 13 07:08:58 PM PDT 24
Peak memory 207096 kb
Host smart-2d57b866-64a7-471b-a91a-7a216f6a8c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18749
01298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1874901298
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3465261403
Short name T1933
Test name
Test status
Simulation time 230887028 ps
CPU time 0.86 seconds
Started Jul 13 07:07:22 PM PDT 24
Finished Jul 13 07:07:24 PM PDT 24
Peak memory 206876 kb
Host smart-907bcdd4-c9df-4555-ae1f-ee72a5feac91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34652
61403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3465261403
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.860032914
Short name T68
Test name
Test status
Simulation time 422972363 ps
CPU time 1.22 seconds
Started Jul 13 07:07:21 PM PDT 24
Finished Jul 13 07:07:23 PM PDT 24
Peak memory 206876 kb
Host smart-1a3dfab5-cf59-403c-92fc-0e97ff733ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86003
2914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.860032914
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.911525207
Short name T2305
Test name
Test status
Simulation time 23307375853 ps
CPU time 27.15 seconds
Started Jul 13 07:07:24 PM PDT 24
Finished Jul 13 07:07:51 PM PDT 24
Peak memory 206912 kb
Host smart-cb7e30bb-5a51-4cf6-9d7e-91ca0ffab839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91152
5207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.911525207
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2187415380
Short name T2497
Test name
Test status
Simulation time 3340342940 ps
CPU time 3.7 seconds
Started Jul 13 07:07:25 PM PDT 24
Finished Jul 13 07:07:29 PM PDT 24
Peak memory 206912 kb
Host smart-6e749107-ac76-43c1-accc-22caeaab6b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21874
15380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2187415380
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.566161827
Short name T972
Test name
Test status
Simulation time 10512651245 ps
CPU time 71.83 seconds
Started Jul 13 07:07:22 PM PDT 24
Finished Jul 13 07:08:34 PM PDT 24
Peak memory 207156 kb
Host smart-e9761111-efaa-418a-9367-67850863ddc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56616
1827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.566161827
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3663189729
Short name T1902
Test name
Test status
Simulation time 4042290473 ps
CPU time 28.41 seconds
Started Jul 13 07:07:21 PM PDT 24
Finished Jul 13 07:07:50 PM PDT 24
Peak memory 207104 kb
Host smart-17691bdd-0dac-4159-94ff-01166eaa3937
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3663189729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3663189729
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2411454673
Short name T1016
Test name
Test status
Simulation time 277643954 ps
CPU time 1.04 seconds
Started Jul 13 07:07:22 PM PDT 24
Finished Jul 13 07:07:24 PM PDT 24
Peak memory 206868 kb
Host smart-9d95aa70-853d-4771-9c8b-d477481729e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2411454673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2411454673
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.90754453
Short name T1155
Test name
Test status
Simulation time 190578491 ps
CPU time 0.87 seconds
Started Jul 13 07:07:23 PM PDT 24
Finished Jul 13 07:07:24 PM PDT 24
Peak memory 206864 kb
Host smart-9bc31f12-7ef4-46a6-bcbd-56173baf62f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90754
453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.90754453
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.348559788
Short name T455
Test name
Test status
Simulation time 4994803992 ps
CPU time 46.52 seconds
Started Jul 13 07:07:24 PM PDT 24
Finished Jul 13 07:08:11 PM PDT 24
Peak memory 207128 kb
Host smart-b068a792-c838-496c-aaf9-77d5ee541846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34855
9788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.348559788
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.69906546
Short name T1883
Test name
Test status
Simulation time 6268468674 ps
CPU time 178.32 seconds
Started Jul 13 07:07:22 PM PDT 24
Finished Jul 13 07:10:20 PM PDT 24
Peak memory 207088 kb
Host smart-ceba72c2-5241-4c94-a554-ff5674e4885b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=69906546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.69906546
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1358384305
Short name T2649
Test name
Test status
Simulation time 167485097 ps
CPU time 0.83 seconds
Started Jul 13 07:07:21 PM PDT 24
Finished Jul 13 07:07:22 PM PDT 24
Peak memory 206884 kb
Host smart-e0e13395-e62b-4291-ac13-da30fa80f598
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1358384305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1358384305
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1941019798
Short name T2043
Test name
Test status
Simulation time 153247487 ps
CPU time 0.76 seconds
Started Jul 13 07:07:21 PM PDT 24
Finished Jul 13 07:07:22 PM PDT 24
Peak memory 206876 kb
Host smart-84994d12-0ce0-4d0c-b63e-94f3bdaaab63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19410
19798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1941019798
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2200400670
Short name T69
Test name
Test status
Simulation time 515772116 ps
CPU time 1.52 seconds
Started Jul 13 07:07:31 PM PDT 24
Finished Jul 13 07:07:34 PM PDT 24
Peak memory 206864 kb
Host smart-00d66487-afbb-4391-b356-bd19e8009f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22004
00670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2200400670
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3255310504
Short name T1832
Test name
Test status
Simulation time 168924448 ps
CPU time 0.84 seconds
Started Jul 13 07:07:32 PM PDT 24
Finished Jul 13 07:07:33 PM PDT 24
Peak memory 206868 kb
Host smart-23e26c8d-c5fa-4e53-b9e9-5d504950889c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32553
10504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3255310504
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.970738826
Short name T881
Test name
Test status
Simulation time 155903558 ps
CPU time 0.76 seconds
Started Jul 13 07:07:32 PM PDT 24
Finished Jul 13 07:07:33 PM PDT 24
Peak memory 206868 kb
Host smart-5d266d0a-47c2-4f07-b67d-122e601b7074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97073
8826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.970738826
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.4211116727
Short name T1823
Test name
Test status
Simulation time 266009472 ps
CPU time 0.86 seconds
Started Jul 13 07:07:31 PM PDT 24
Finished Jul 13 07:07:32 PM PDT 24
Peak memory 206856 kb
Host smart-098649a1-a905-4d59-86e4-3d673b5f00bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42111
16727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.4211116727
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3834952852
Short name T159
Test name
Test status
Simulation time 171435009 ps
CPU time 0.8 seconds
Started Jul 13 07:07:29 PM PDT 24
Finished Jul 13 07:07:30 PM PDT 24
Peak memory 206808 kb
Host smart-afc01068-1e26-45d2-bec5-737984a1927e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38349
52852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3834952852
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1344216562
Short name T2226
Test name
Test status
Simulation time 184701677 ps
CPU time 0.88 seconds
Started Jul 13 07:07:34 PM PDT 24
Finished Jul 13 07:07:35 PM PDT 24
Peak memory 206868 kb
Host smart-86e34b63-eb28-43ef-8cc0-29540e2d7371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13442
16562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1344216562
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.47357328
Short name T2609
Test name
Test status
Simulation time 205373459 ps
CPU time 0.89 seconds
Started Jul 13 07:07:31 PM PDT 24
Finished Jul 13 07:07:32 PM PDT 24
Peak memory 206876 kb
Host smart-45a406d6-b275-4516-9d73-21180ef1e130
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=47357328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.47357328
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1872967936
Short name T2723
Test name
Test status
Simulation time 222608575 ps
CPU time 0.89 seconds
Started Jul 13 07:07:31 PM PDT 24
Finished Jul 13 07:07:33 PM PDT 24
Peak memory 206860 kb
Host smart-f85e9f46-ebbf-4ec8-acb9-5a9c8250db17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18729
67936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1872967936
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.307686813
Short name T2066
Test name
Test status
Simulation time 222047830 ps
CPU time 0.93 seconds
Started Jul 13 07:07:31 PM PDT 24
Finished Jul 13 07:07:32 PM PDT 24
Peak memory 206844 kb
Host smart-2ba03ea4-9b90-4f8e-8ba9-43ef888f5075
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=307686813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.307686813
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.3215788449
Short name T181
Test name
Test status
Simulation time 213189372 ps
CPU time 0.89 seconds
Started Jul 13 07:07:32 PM PDT 24
Finished Jul 13 07:07:34 PM PDT 24
Peak memory 206856 kb
Host smart-14c6b776-c659-41d3-9b02-46cd0d4b6cb8
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3215788449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.3215788449
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.183391834
Short name T897
Test name
Test status
Simulation time 148001207 ps
CPU time 0.75 seconds
Started Jul 13 07:07:31 PM PDT 24
Finished Jul 13 07:07:32 PM PDT 24
Peak memory 206848 kb
Host smart-83556972-775d-4fe2-9815-4f55e908bef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18339
1834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.183391834
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3934219480
Short name T1517
Test name
Test status
Simulation time 10887072650 ps
CPU time 23.12 seconds
Started Jul 13 07:07:31 PM PDT 24
Finished Jul 13 07:07:55 PM PDT 24
Peak memory 207160 kb
Host smart-a9daab45-db40-4ab6-905c-02013897f349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39342
19480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3934219480
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1078321967
Short name T1726
Test name
Test status
Simulation time 160962508 ps
CPU time 0.79 seconds
Started Jul 13 07:07:40 PM PDT 24
Finished Jul 13 07:07:41 PM PDT 24
Peak memory 206804 kb
Host smart-d7b97418-6e26-459a-a9a0-76014ebf2877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10783
21967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1078321967
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.354095419
Short name T807
Test name
Test status
Simulation time 216650688 ps
CPU time 0.91 seconds
Started Jul 13 07:07:39 PM PDT 24
Finished Jul 13 07:07:40 PM PDT 24
Peak memory 206828 kb
Host smart-f4e028e3-87b6-4c6f-ac6b-54adf69cf7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35409
5419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.354095419
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2837427125
Short name T1417
Test name
Test status
Simulation time 9028361897 ps
CPU time 56.84 seconds
Started Jul 13 07:07:41 PM PDT 24
Finished Jul 13 07:08:38 PM PDT 24
Peak memory 207056 kb
Host smart-1cdd3f12-c296-4a8f-91d1-be5c7d555522
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2837427125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2837427125
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.907105972
Short name T2134
Test name
Test status
Simulation time 15604507275 ps
CPU time 355.32 seconds
Started Jul 13 07:07:41 PM PDT 24
Finished Jul 13 07:13:37 PM PDT 24
Peak memory 207132 kb
Host smart-6bf74d4c-d3bc-429a-a7f7-7d0bb5e3af62
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=907105972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.907105972
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.390021532
Short name T988
Test name
Test status
Simulation time 221849569 ps
CPU time 0.91 seconds
Started Jul 13 07:07:40 PM PDT 24
Finished Jul 13 07:07:41 PM PDT 24
Peak memory 206864 kb
Host smart-84d6664f-bf63-4552-b911-4e05e63a01b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39002
1532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.390021532
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1803166921
Short name T2086
Test name
Test status
Simulation time 172937392 ps
CPU time 0.83 seconds
Started Jul 13 07:07:41 PM PDT 24
Finished Jul 13 07:07:42 PM PDT 24
Peak memory 206868 kb
Host smart-cb8a8a94-6a2e-408d-9f99-801ff771e041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18031
66921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1803166921
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1083746268
Short name T1387
Test name
Test status
Simulation time 137969040 ps
CPU time 0.75 seconds
Started Jul 13 07:07:41 PM PDT 24
Finished Jul 13 07:07:43 PM PDT 24
Peak memory 206868 kb
Host smart-f44325e3-e0fa-44b4-be4a-a152d4218dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10837
46268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1083746268
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.4263211299
Short name T2340
Test name
Test status
Simulation time 183391019 ps
CPU time 0.83 seconds
Started Jul 13 07:07:39 PM PDT 24
Finished Jul 13 07:07:40 PM PDT 24
Peak memory 206868 kb
Host smart-dd349e4d-c082-4387-b4e7-66146dbe3200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42632
11299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.4263211299
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3216910885
Short name T1128
Test name
Test status
Simulation time 152726385 ps
CPU time 0.84 seconds
Started Jul 13 07:07:42 PM PDT 24
Finished Jul 13 07:07:43 PM PDT 24
Peak memory 206864 kb
Host smart-e21ecef5-6c01-47a0-8d54-b4c838e6a416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32169
10885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3216910885
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1761504150
Short name T977
Test name
Test status
Simulation time 153249356 ps
CPU time 0.78 seconds
Started Jul 13 07:07:42 PM PDT 24
Finished Jul 13 07:07:43 PM PDT 24
Peak memory 206864 kb
Host smart-e6783c77-fa46-45d6-831b-ead642e16b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17615
04150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1761504150
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3243603007
Short name T1601
Test name
Test status
Simulation time 229434857 ps
CPU time 0.97 seconds
Started Jul 13 07:07:43 PM PDT 24
Finished Jul 13 07:07:44 PM PDT 24
Peak memory 206772 kb
Host smart-d66df01c-9ecd-468a-903a-09417c23113b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32436
03007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3243603007
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.504242989
Short name T2446
Test name
Test status
Simulation time 5393677518 ps
CPU time 48.51 seconds
Started Jul 13 07:07:41 PM PDT 24
Finished Jul 13 07:08:30 PM PDT 24
Peak memory 207064 kb
Host smart-0581668d-93dc-4358-9e00-f4599a21bcfc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=504242989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.504242989
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2312132458
Short name T1259
Test name
Test status
Simulation time 181321383 ps
CPU time 0.8 seconds
Started Jul 13 07:07:39 PM PDT 24
Finished Jul 13 07:07:40 PM PDT 24
Peak memory 206880 kb
Host smart-5dc4833a-12dd-47c9-a849-66f18e9364d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23121
32458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2312132458
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3605179271
Short name T279
Test name
Test status
Simulation time 183102710 ps
CPU time 0.85 seconds
Started Jul 13 07:07:40 PM PDT 24
Finished Jul 13 07:07:42 PM PDT 24
Peak memory 206820 kb
Host smart-3f8df7fb-6648-4fb9-9e7a-004d67a9b18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36051
79271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3605179271
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.3518504958
Short name T1115
Test name
Test status
Simulation time 1324560489 ps
CPU time 2.92 seconds
Started Jul 13 07:07:53 PM PDT 24
Finished Jul 13 07:07:56 PM PDT 24
Peak memory 207048 kb
Host smart-0d75f1f6-ba0a-45e1-a08f-6e8841b72d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
04958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.3518504958
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1356797189
Short name T1838
Test name
Test status
Simulation time 5786631531 ps
CPU time 159.13 seconds
Started Jul 13 07:07:52 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 207052 kb
Host smart-849cd82b-6a55-48e9-b8b7-8ca1af3db219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13567
97189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1356797189
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3974817483
Short name T95
Test name
Test status
Simulation time 13232374160 ps
CPU time 94.27 seconds
Started Jul 13 07:07:53 PM PDT 24
Finished Jul 13 07:09:28 PM PDT 24
Peak memory 207112 kb
Host smart-1fb61909-bbe2-4399-84d4-cb903c49da08
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3974817483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3974817483
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2521852177
Short name T2486
Test name
Test status
Simulation time 56773383 ps
CPU time 0.72 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206884 kb
Host smart-353c5cf0-f803-410e-a8c0-515bdb48d7b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2521852177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2521852177
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2213160948
Short name T2659
Test name
Test status
Simulation time 4183269352 ps
CPU time 4.61 seconds
Started Jul 13 07:07:53 PM PDT 24
Finished Jul 13 07:07:58 PM PDT 24
Peak memory 207112 kb
Host smart-25564753-ab33-4f5b-94df-337e9d7dbc81
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2213160948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.2213160948
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2773543055
Short name T2590
Test name
Test status
Simulation time 13287022019 ps
CPU time 15.13 seconds
Started Jul 13 07:07:53 PM PDT 24
Finished Jul 13 07:08:08 PM PDT 24
Peak memory 207072 kb
Host smart-24e11688-711a-4096-9143-8dea1a46cfc4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2773543055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2773543055
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1166752065
Short name T479
Test name
Test status
Simulation time 23363694660 ps
CPU time 21.93 seconds
Started Jul 13 07:07:53 PM PDT 24
Finished Jul 13 07:08:16 PM PDT 24
Peak memory 207092 kb
Host smart-0886a01f-aa2d-436b-b984-b87e091602fd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1166752065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.1166752065
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1972032312
Short name T428
Test name
Test status
Simulation time 187392544 ps
CPU time 0.86 seconds
Started Jul 13 07:07:54 PM PDT 24
Finished Jul 13 07:07:55 PM PDT 24
Peak memory 206864 kb
Host smart-6146f401-3470-418e-b4ef-2ae225346036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19720
32312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1972032312
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.14927232
Short name T48
Test name
Test status
Simulation time 193188511 ps
CPU time 0.9 seconds
Started Jul 13 07:07:53 PM PDT 24
Finished Jul 13 07:07:55 PM PDT 24
Peak memory 206836 kb
Host smart-ffa240e5-ca0c-406c-931f-2a0666772ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14927
232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.14927232
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.861359237
Short name T2626
Test name
Test status
Simulation time 196694680 ps
CPU time 0.89 seconds
Started Jul 13 07:07:55 PM PDT 24
Finished Jul 13 07:07:56 PM PDT 24
Peak memory 206872 kb
Host smart-5d8a2dce-96fb-42b7-86db-64afa1948cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86135
9237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.861359237
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2182433961
Short name T60
Test name
Test status
Simulation time 157093624 ps
CPU time 0.79 seconds
Started Jul 13 07:07:55 PM PDT 24
Finished Jul 13 07:07:56 PM PDT 24
Peak memory 206848 kb
Host smart-110bf3c5-1754-43bd-9c7a-c4e45d217596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21824
33961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2182433961
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1194174140
Short name T522
Test name
Test status
Simulation time 462024315 ps
CPU time 1.39 seconds
Started Jul 13 07:07:54 PM PDT 24
Finished Jul 13 07:07:56 PM PDT 24
Peak memory 206848 kb
Host smart-3c163c77-77bd-4acb-89a3-aa972a384f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11941
74140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1194174140
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3607846222
Short name T2329
Test name
Test status
Simulation time 1386147541 ps
CPU time 3.09 seconds
Started Jul 13 07:07:53 PM PDT 24
Finished Jul 13 07:07:57 PM PDT 24
Peak memory 207308 kb
Host smart-4a8228aa-9b7f-4e61-988c-5f3d4fd2510d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36078
46222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3607846222
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.342187460
Short name T2745
Test name
Test status
Simulation time 10346423400 ps
CPU time 18.97 seconds
Started Jul 13 07:07:55 PM PDT 24
Finished Jul 13 07:08:15 PM PDT 24
Peak memory 207120 kb
Host smart-3360c48b-1999-412f-ad22-09f3523a36ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34218
7460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.342187460
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1952632625
Short name T2508
Test name
Test status
Simulation time 470010451 ps
CPU time 1.41 seconds
Started Jul 13 07:07:53 PM PDT 24
Finished Jul 13 07:07:55 PM PDT 24
Peak memory 206880 kb
Host smart-a1add1c6-2c46-401b-a08a-5e2f59e0303a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19526
32625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1952632625
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.524247519
Short name T1993
Test name
Test status
Simulation time 151127562 ps
CPU time 0.88 seconds
Started Jul 13 07:08:09 PM PDT 24
Finished Jul 13 07:08:11 PM PDT 24
Peak memory 206832 kb
Host smart-1247cb82-9d80-4d84-a1d8-afc1f2f53e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52424
7519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.524247519
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2894765548
Short name T574
Test name
Test status
Simulation time 42686276 ps
CPU time 0.64 seconds
Started Jul 13 07:08:08 PM PDT 24
Finished Jul 13 07:08:09 PM PDT 24
Peak memory 206852 kb
Host smart-3b0dbf81-6ef6-4f74-ab9f-848ed21fc876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28947
65548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2894765548
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2494799998
Short name T624
Test name
Test status
Simulation time 817516983 ps
CPU time 1.82 seconds
Started Jul 13 07:08:02 PM PDT 24
Finished Jul 13 07:08:05 PM PDT 24
Peak memory 207072 kb
Host smart-5d8c9a72-35a7-4204-9884-c0cb43e806aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24947
99998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2494799998
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.650410480
Short name T1296
Test name
Test status
Simulation time 162604120 ps
CPU time 1.57 seconds
Started Jul 13 07:08:01 PM PDT 24
Finished Jul 13 07:08:03 PM PDT 24
Peak memory 207000 kb
Host smart-6df5fbbc-eae6-4ac6-a528-c23d2be69199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65041
0480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.650410480
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.237787465
Short name T80
Test name
Test status
Simulation time 97197669306 ps
CPU time 131.04 seconds
Started Jul 13 07:08:01 PM PDT 24
Finished Jul 13 07:10:12 PM PDT 24
Peak memory 207076 kb
Host smart-c7676e3b-c735-463f-92d5-f271521c3045
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=237787465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.237787465
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.3291612362
Short name T1096
Test name
Test status
Simulation time 93292053380 ps
CPU time 124.04 seconds
Started Jul 13 07:08:03 PM PDT 24
Finished Jul 13 07:10:08 PM PDT 24
Peak memory 207056 kb
Host smart-4d401be0-e25c-4236-a475-bed7c9235887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291612362 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3291612362
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.578404274
Short name T1342
Test name
Test status
Simulation time 97112939565 ps
CPU time 135.62 seconds
Started Jul 13 07:08:09 PM PDT 24
Finished Jul 13 07:10:26 PM PDT 24
Peak memory 207076 kb
Host smart-59010972-6756-462b-b3d8-168ba4db6962
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=578404274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.578404274
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.3811598025
Short name T846
Test name
Test status
Simulation time 105104139357 ps
CPU time 146.8 seconds
Started Jul 13 07:08:08 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 207072 kb
Host smart-936cc526-4958-444c-ba41-7cd20945dd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811598025 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3811598025
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.2537254141
Short name T1403
Test name
Test status
Simulation time 110197917898 ps
CPU time 147.82 seconds
Started Jul 13 07:08:03 PM PDT 24
Finished Jul 13 07:10:31 PM PDT 24
Peak memory 207080 kb
Host smart-fb5d7359-2b7e-4416-81e0-caf65bf73208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
54141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.2537254141
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2019617983
Short name T341
Test name
Test status
Simulation time 232252581 ps
CPU time 0.89 seconds
Started Jul 13 07:08:09 PM PDT 24
Finished Jul 13 07:08:10 PM PDT 24
Peak memory 206876 kb
Host smart-0aafc24b-7d11-4b67-bb47-0b39ec562d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20196
17983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2019617983
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.4253368771
Short name T1355
Test name
Test status
Simulation time 164951829 ps
CPU time 0.79 seconds
Started Jul 13 07:08:02 PM PDT 24
Finished Jul 13 07:08:03 PM PDT 24
Peak memory 206880 kb
Host smart-f5559e75-02dd-4aef-9df5-f289c53bd757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42533
68771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.4253368771
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.439575169
Short name T701
Test name
Test status
Simulation time 189374386 ps
CPU time 0.91 seconds
Started Jul 13 07:08:08 PM PDT 24
Finished Jul 13 07:08:10 PM PDT 24
Peak memory 206872 kb
Host smart-25165794-4771-4087-b083-b01daeb88d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43957
5169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.439575169
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.3334450062
Short name T2681
Test name
Test status
Simulation time 9872011313 ps
CPU time 292.35 seconds
Started Jul 13 07:08:03 PM PDT 24
Finished Jul 13 07:12:56 PM PDT 24
Peak memory 207092 kb
Host smart-dda359ed-0f7d-404e-9650-2548f9d7f479
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3334450062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3334450062
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.3844073876
Short name T395
Test name
Test status
Simulation time 6691806501 ps
CPU time 61.24 seconds
Started Jul 13 07:08:09 PM PDT 24
Finished Jul 13 07:09:12 PM PDT 24
Peak memory 207368 kb
Host smart-c32223b6-ea35-4161-8a44-d88b14aa568d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38440
73876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3844073876
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2053056979
Short name T1702
Test name
Test status
Simulation time 191508005 ps
CPU time 0.82 seconds
Started Jul 13 07:08:08 PM PDT 24
Finished Jul 13 07:08:09 PM PDT 24
Peak memory 206844 kb
Host smart-4b1eeea3-2a03-450f-af05-804b6a3ca881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20530
56979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2053056979
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.1174910873
Short name T1765
Test name
Test status
Simulation time 23368702288 ps
CPU time 24.67 seconds
Started Jul 13 07:08:01 PM PDT 24
Finished Jul 13 07:08:26 PM PDT 24
Peak memory 206960 kb
Host smart-62ca800c-4fb2-4883-b8bf-30064e2567b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11749
10873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.1174910873
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1419396166
Short name T2064
Test name
Test status
Simulation time 3313376848 ps
CPU time 4.76 seconds
Started Jul 13 07:08:03 PM PDT 24
Finished Jul 13 07:08:09 PM PDT 24
Peak memory 206924 kb
Host smart-cd2a905c-e136-4ede-9d4f-8da3f034d0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14193
96166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1419396166
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2716615214
Short name T1415
Test name
Test status
Simulation time 9367773630 ps
CPU time 65.72 seconds
Started Jul 13 07:08:04 PM PDT 24
Finished Jul 13 07:09:10 PM PDT 24
Peak memory 207124 kb
Host smart-698bd3de-8c83-49a0-aee2-375dde792730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27166
15214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2716615214
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1900426567
Short name T568
Test name
Test status
Simulation time 7684024025 ps
CPU time 212.27 seconds
Started Jul 13 07:08:02 PM PDT 24
Finished Jul 13 07:11:35 PM PDT 24
Peak memory 207088 kb
Host smart-abb8f049-ee77-4689-b597-8f5d836424ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1900426567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1900426567
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.471043361
Short name T2498
Test name
Test status
Simulation time 301817580 ps
CPU time 0.98 seconds
Started Jul 13 07:08:01 PM PDT 24
Finished Jul 13 07:08:03 PM PDT 24
Peak memory 206868 kb
Host smart-c795d84b-0f6a-4370-88c9-0557a7b9bd26
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=471043361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.471043361
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2957719418
Short name T316
Test name
Test status
Simulation time 199047923 ps
CPU time 0.88 seconds
Started Jul 13 07:08:02 PM PDT 24
Finished Jul 13 07:08:03 PM PDT 24
Peak memory 206872 kb
Host smart-4a84d02d-2cf6-45d7-b6e4-6b96b27e3968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577
19418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2957719418
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2044136517
Short name T1220
Test name
Test status
Simulation time 5544183797 ps
CPU time 54.63 seconds
Started Jul 13 07:08:07 PM PDT 24
Finished Jul 13 07:09:02 PM PDT 24
Peak memory 207128 kb
Host smart-5e343b62-c60c-43d6-91f5-bb0c2e4c5eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20441
36517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2044136517
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2793594441
Short name T1940
Test name
Test status
Simulation time 3239144301 ps
CPU time 24.8 seconds
Started Jul 13 07:08:01 PM PDT 24
Finished Jul 13 07:08:27 PM PDT 24
Peak memory 207088 kb
Host smart-eddff339-429f-4445-9fd0-495880e276ce
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2793594441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2793594441
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2388980665
Short name T1745
Test name
Test status
Simulation time 150635874 ps
CPU time 0.78 seconds
Started Jul 13 07:08:09 PM PDT 24
Finished Jul 13 07:08:11 PM PDT 24
Peak memory 206876 kb
Host smart-d0af7715-29df-427b-a207-9d2f95f7fa02
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2388980665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2388980665
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.537868894
Short name T2094
Test name
Test status
Simulation time 159372644 ps
CPU time 0.78 seconds
Started Jul 13 07:08:03 PM PDT 24
Finished Jul 13 07:08:05 PM PDT 24
Peak memory 206872 kb
Host smart-a4603715-8409-40ca-8416-acf4ff895fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53786
8894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.537868894
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1912775338
Short name T2380
Test name
Test status
Simulation time 189631295 ps
CPU time 0.81 seconds
Started Jul 13 07:08:08 PM PDT 24
Finished Jul 13 07:08:10 PM PDT 24
Peak memory 206848 kb
Host smart-2498160a-8f05-4e98-8e15-0f667c746115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19127
75338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1912775338
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.615071930
Short name T984
Test name
Test status
Simulation time 186862442 ps
CPU time 0.82 seconds
Started Jul 13 07:08:03 PM PDT 24
Finished Jul 13 07:08:04 PM PDT 24
Peak memory 206868 kb
Host smart-cebdfe60-04e3-4a2b-9b48-2c9608177a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61507
1930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.615071930
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1787312146
Short name T1182
Test name
Test status
Simulation time 181744994 ps
CPU time 0.85 seconds
Started Jul 13 07:08:03 PM PDT 24
Finished Jul 13 07:08:04 PM PDT 24
Peak memory 206868 kb
Host smart-6ec63b6c-9a23-45c6-b0db-debdc76ea830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17873
12146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1787312146
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1617673013
Short name T396
Test name
Test status
Simulation time 170706155 ps
CPU time 0.81 seconds
Started Jul 13 07:08:02 PM PDT 24
Finished Jul 13 07:08:03 PM PDT 24
Peak memory 206860 kb
Host smart-d8db37c5-9cc8-4959-9cd9-bf141c6cd587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16176
73013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1617673013
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3495653148
Short name T1230
Test name
Test status
Simulation time 237034853 ps
CPU time 0.94 seconds
Started Jul 13 07:08:04 PM PDT 24
Finished Jul 13 07:08:05 PM PDT 24
Peak memory 206872 kb
Host smart-8f0f5ed7-2d5d-436d-81fc-3f3d84f656f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3495653148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3495653148
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1003600190
Short name T1247
Test name
Test status
Simulation time 224917654 ps
CPU time 0.96 seconds
Started Jul 13 07:08:08 PM PDT 24
Finished Jul 13 07:08:10 PM PDT 24
Peak memory 206868 kb
Host smart-f282d0bd-7b13-4417-abb6-7483d8d13b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036
00190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1003600190
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2462489802
Short name T2592
Test name
Test status
Simulation time 139501730 ps
CPU time 0.82 seconds
Started Jul 13 07:08:02 PM PDT 24
Finished Jul 13 07:08:03 PM PDT 24
Peak memory 206864 kb
Host smart-24fec7c1-9f84-4b52-8727-31c2bd68a36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24624
89802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2462489802
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1221285023
Short name T2049
Test name
Test status
Simulation time 47151241 ps
CPU time 0.67 seconds
Started Jul 13 07:08:04 PM PDT 24
Finished Jul 13 07:08:05 PM PDT 24
Peak memory 206860 kb
Host smart-c175eef3-d54b-46fa-bbc3-8bdfcd5842dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12212
85023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1221285023
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.956192118
Short name T226
Test name
Test status
Simulation time 11084011678 ps
CPU time 22.78 seconds
Started Jul 13 07:08:09 PM PDT 24
Finished Jul 13 07:08:32 PM PDT 24
Peak memory 207108 kb
Host smart-5692e31f-8f89-417e-b48c-accd9cca89e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95619
2118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.956192118
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1244755427
Short name T778
Test name
Test status
Simulation time 180457362 ps
CPU time 0.79 seconds
Started Jul 13 07:08:10 PM PDT 24
Finished Jul 13 07:08:12 PM PDT 24
Peak memory 206856 kb
Host smart-b49f1ed7-a469-4250-988d-1e21146df0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12447
55427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1244755427
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3718713212
Short name T2363
Test name
Test status
Simulation time 248506020 ps
CPU time 0.94 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206848 kb
Host smart-5ba09f7c-0c26-43dc-b630-4e15e7d72313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37187
13212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3718713212
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2764041638
Short name T149
Test name
Test status
Simulation time 16220372741 ps
CPU time 351.1 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:14:04 PM PDT 24
Peak memory 207168 kb
Host smart-08882273-eb28-42d9-b4d8-bba97e2084a0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2764041638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2764041638
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3449919486
Short name T1472
Test name
Test status
Simulation time 13082442560 ps
CPU time 95.21 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:09:48 PM PDT 24
Peak memory 207080 kb
Host smart-daaf8f41-374b-4d85-8407-ba4dbc2dd6c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3449919486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3449919486
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3431114404
Short name T611
Test name
Test status
Simulation time 251650955 ps
CPU time 0.96 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206872 kb
Host smart-0b9a0883-5a9c-4e85-a4cc-c6fa90373e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311
14404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3431114404
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.404834244
Short name T491
Test name
Test status
Simulation time 178087552 ps
CPU time 0.84 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206904 kb
Host smart-646492f1-a78f-4b5b-a23e-c86ae52b4cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40483
4244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.404834244
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1577155577
Short name T722
Test name
Test status
Simulation time 190983510 ps
CPU time 0.92 seconds
Started Jul 13 07:08:10 PM PDT 24
Finished Jul 13 07:08:12 PM PDT 24
Peak memory 206888 kb
Host smart-45abfc30-f1e4-46b8-b1f9-c27fa4219e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15771
55577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1577155577
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3933534257
Short name T2642
Test name
Test status
Simulation time 165440440 ps
CPU time 0.81 seconds
Started Jul 13 07:08:14 PM PDT 24
Finished Jul 13 07:08:16 PM PDT 24
Peak memory 206860 kb
Host smart-54f7644b-2c8e-43bd-8d56-56fff41fd8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39335
34257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3933534257
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2844350758
Short name T173
Test name
Test status
Simulation time 1835274795 ps
CPU time 3.09 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:16 PM PDT 24
Peak memory 224564 kb
Host smart-690e741a-eb6b-4cb2-bf95-a202df5c304b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2844350758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2844350758
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1593440974
Short name T53
Test name
Test status
Simulation time 429873344 ps
CPU time 1.29 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:15 PM PDT 24
Peak memory 206892 kb
Host smart-0558b85c-e5e0-40d2-9eb1-1ef614cf6d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15934
40974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1593440974
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2475490708
Short name T2370
Test name
Test status
Simulation time 207213192 ps
CPU time 0.86 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206900 kb
Host smart-0789c69a-70da-4422-b7ec-d103a5970810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
90708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2475490708
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2719900761
Short name T2383
Test name
Test status
Simulation time 150228983 ps
CPU time 0.78 seconds
Started Jul 13 07:08:14 PM PDT 24
Finished Jul 13 07:08:15 PM PDT 24
Peak memory 206872 kb
Host smart-3bba5339-0038-4039-8be5-ee6161c2c7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27199
00761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2719900761
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3088365684
Short name T1966
Test name
Test status
Simulation time 157919082 ps
CPU time 0.77 seconds
Started Jul 13 07:08:10 PM PDT 24
Finished Jul 13 07:08:13 PM PDT 24
Peak memory 206864 kb
Host smart-acd6050e-1616-4aa7-a992-fede5c2c3e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30883
65684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3088365684
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.4049162244
Short name T644
Test name
Test status
Simulation time 194037802 ps
CPU time 0.92 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206804 kb
Host smart-4991c890-d6b1-4477-bb43-2f9a75bbdcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40491
62244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.4049162244
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2915759827
Short name T2190
Test name
Test status
Simulation time 3373113826 ps
CPU time 92.74 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:09:46 PM PDT 24
Peak memory 207012 kb
Host smart-dc5ecaa9-751f-40f0-92f4-360d85d17157
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2915759827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2915759827
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1921230098
Short name T1338
Test name
Test status
Simulation time 183049412 ps
CPU time 0.82 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206880 kb
Host smart-ab162c6d-93c1-4c50-8e72-85854fca0938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19212
30098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1921230098
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.250548052
Short name T2257
Test name
Test status
Simulation time 169117314 ps
CPU time 0.8 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206864 kb
Host smart-da54b208-d264-4622-a2b4-b4f2543b0767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25054
8052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.250548052
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.2319087010
Short name T2532
Test name
Test status
Simulation time 1220225709 ps
CPU time 2.76 seconds
Started Jul 13 07:08:10 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 207048 kb
Host smart-0cd2c37e-a191-4060-8745-48ba43832ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23190
87010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2319087010
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2520814516
Short name T1736
Test name
Test status
Simulation time 4384263441 ps
CPU time 42.31 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:08:55 PM PDT 24
Peak memory 207136 kb
Host smart-5925a61d-2415-436c-9fa6-0a6d0013a723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25208
14516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2520814516
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1967800447
Short name T1429
Test name
Test status
Simulation time 63140463 ps
CPU time 0.77 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:19 PM PDT 24
Peak memory 206944 kb
Host smart-a341740c-2991-4a5e-9d05-09062c45c2e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1967800447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1967800447
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2242782990
Short name T917
Test name
Test status
Simulation time 4131079094 ps
CPU time 5.31 seconds
Started Jul 13 07:11:00 PM PDT 24
Finished Jul 13 07:11:06 PM PDT 24
Peak memory 206948 kb
Host smart-58c41d25-a23c-4aad-aa51-166f30b8942c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2242782990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2242782990
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.410101834
Short name T664
Test name
Test status
Simulation time 13522787721 ps
CPU time 15.48 seconds
Started Jul 13 07:10:57 PM PDT 24
Finished Jul 13 07:11:13 PM PDT 24
Peak memory 207120 kb
Host smart-11a50f89-1666-47b5-a941-305a2a44382d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=410101834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.410101834
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.559283132
Short name T1373
Test name
Test status
Simulation time 23341581204 ps
CPU time 22.54 seconds
Started Jul 13 07:10:56 PM PDT 24
Finished Jul 13 07:11:19 PM PDT 24
Peak memory 206824 kb
Host smart-84cf9937-df31-4a01-915c-3c15fa8bffaa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=559283132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.559283132
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2906890833
Short name T1654
Test name
Test status
Simulation time 143109060 ps
CPU time 0.77 seconds
Started Jul 13 07:10:58 PM PDT 24
Finished Jul 13 07:10:59 PM PDT 24
Peak memory 206864 kb
Host smart-cd9f69c9-07fd-4730-8ec2-024860b80422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
90833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2906890833
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1497864216
Short name T297
Test name
Test status
Simulation time 200118595 ps
CPU time 0.81 seconds
Started Jul 13 07:10:59 PM PDT 24
Finished Jul 13 07:11:01 PM PDT 24
Peak memory 206856 kb
Host smart-1b459b80-b9b6-4518-804e-f7eedad34dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14978
64216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1497864216
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3136559416
Short name T1974
Test name
Test status
Simulation time 411504727 ps
CPU time 1.34 seconds
Started Jul 13 07:10:56 PM PDT 24
Finished Jul 13 07:10:58 PM PDT 24
Peak memory 206864 kb
Host smart-08029f6c-80f6-4c2b-956c-1b92ea67b049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31365
59416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3136559416
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2549791672
Short name T978
Test name
Test status
Simulation time 1067775745 ps
CPU time 2.4 seconds
Started Jul 13 07:10:56 PM PDT 24
Finished Jul 13 07:10:59 PM PDT 24
Peak memory 207028 kb
Host smart-53913767-c40d-4053-b261-56781f97eb3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25497
91672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2549791672
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1521008003
Short name T1604
Test name
Test status
Simulation time 19985084440 ps
CPU time 41.71 seconds
Started Jul 13 07:10:58 PM PDT 24
Finished Jul 13 07:11:40 PM PDT 24
Peak memory 207088 kb
Host smart-b3c72afa-d221-4987-91dc-834960e47297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
08003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1521008003
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.224564579
Short name T1872
Test name
Test status
Simulation time 418403719 ps
CPU time 1.3 seconds
Started Jul 13 07:10:59 PM PDT 24
Finished Jul 13 07:11:01 PM PDT 24
Peak memory 206872 kb
Host smart-da39b91f-c7eb-45c7-82f6-a8806934ad2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22456
4579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.224564579
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2821063363
Short name T2613
Test name
Test status
Simulation time 181952253 ps
CPU time 0.8 seconds
Started Jul 13 07:10:58 PM PDT 24
Finished Jul 13 07:11:00 PM PDT 24
Peak memory 206880 kb
Host smart-9b73bddf-fd9b-410e-bf53-aeb9da780e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28210
63363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2821063363
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1125286248
Short name T1525
Test name
Test status
Simulation time 59440450 ps
CPU time 0.67 seconds
Started Jul 13 07:10:58 PM PDT 24
Finished Jul 13 07:10:59 PM PDT 24
Peak memory 206860 kb
Host smart-a1e5cfd5-3255-4597-b9c1-58828a1b4222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11252
86248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1125286248
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2022406654
Short name T1559
Test name
Test status
Simulation time 895073616 ps
CPU time 2.1 seconds
Started Jul 13 07:11:00 PM PDT 24
Finished Jul 13 07:11:02 PM PDT 24
Peak memory 207004 kb
Host smart-9b8b8518-ee0b-4b23-9677-ba774735e847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20224
06654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2022406654
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1411576490
Short name T2467
Test name
Test status
Simulation time 220892248 ps
CPU time 0.95 seconds
Started Jul 13 07:11:09 PM PDT 24
Finished Jul 13 07:11:12 PM PDT 24
Peak memory 207104 kb
Host smart-4587e9af-9910-47a9-a0bb-f4f1a3ca79c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14115
76490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1411576490
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2312838222
Short name T509
Test name
Test status
Simulation time 149014367 ps
CPU time 0.77 seconds
Started Jul 13 07:11:06 PM PDT 24
Finished Jul 13 07:11:08 PM PDT 24
Peak memory 206868 kb
Host smart-90c000e6-4867-4000-be76-f272d09da488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23128
38222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2312838222
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.438371308
Short name T1366
Test name
Test status
Simulation time 195291559 ps
CPU time 0.92 seconds
Started Jul 13 07:11:12 PM PDT 24
Finished Jul 13 07:11:13 PM PDT 24
Peak memory 206880 kb
Host smart-b99405d1-e225-4fca-b93f-859831a480d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43837
1308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.438371308
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.2620922789
Short name T2551
Test name
Test status
Simulation time 8789256519 ps
CPU time 80.53 seconds
Started Jul 13 07:11:05 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 207084 kb
Host smart-8ca98ce8-ed65-4987-9e06-a70d4e0e37b4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2620922789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2620922789
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1970898571
Short name T372
Test name
Test status
Simulation time 11572338836 ps
CPU time 42.54 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:51 PM PDT 24
Peak memory 207148 kb
Host smart-41d52fe6-082b-45a2-a6fd-561c51696ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19708
98571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1970898571
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1971422061
Short name T1592
Test name
Test status
Simulation time 234515442 ps
CPU time 0.96 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:09 PM PDT 24
Peak memory 206864 kb
Host smart-dbd1d7be-248f-4af1-92d4-1431018df68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19714
22061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1971422061
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3759593690
Short name T1261
Test name
Test status
Simulation time 23307141549 ps
CPU time 22.66 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:11:32 PM PDT 24
Peak memory 206948 kb
Host smart-40b6ca92-7cc2-4065-badd-a1f87eb97454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37595
93690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3759593690
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2552522478
Short name T1580
Test name
Test status
Simulation time 3346962190 ps
CPU time 3.59 seconds
Started Jul 13 07:11:06 PM PDT 24
Finished Jul 13 07:11:10 PM PDT 24
Peak memory 206940 kb
Host smart-d1d3ca0f-0387-4e2d-b99f-d3c228d588a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25525
22478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2552522478
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2409130828
Short name T2334
Test name
Test status
Simulation time 8456360340 ps
CPU time 222.68 seconds
Started Jul 13 07:11:06 PM PDT 24
Finished Jul 13 07:14:49 PM PDT 24
Peak memory 207156 kb
Host smart-926df272-3661-4165-a499-4be4c4ec2e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24091
30828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2409130828
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1052250918
Short name T2589
Test name
Test status
Simulation time 6962020048 ps
CPU time 65.36 seconds
Started Jul 13 07:11:06 PM PDT 24
Finished Jul 13 07:12:12 PM PDT 24
Peak memory 207124 kb
Host smart-e2112f48-d18c-4cdd-9e6b-16b768d10d99
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1052250918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1052250918
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1001505677
Short name T1729
Test name
Test status
Simulation time 242526549 ps
CPU time 0.91 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:09 PM PDT 24
Peak memory 206868 kb
Host smart-8d7be591-cd5b-455f-8ff9-5421d7ac0d30
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1001505677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1001505677
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1986830548
Short name T2191
Test name
Test status
Simulation time 200446565 ps
CPU time 0.87 seconds
Started Jul 13 07:11:09 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 207112 kb
Host smart-9dbda0ef-11dd-4010-a932-d8fd751d629a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19868
30548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1986830548
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.146958398
Short name T144
Test name
Test status
Simulation time 4618572812 ps
CPU time 129.27 seconds
Started Jul 13 07:11:10 PM PDT 24
Finished Jul 13 07:13:20 PM PDT 24
Peak memory 207068 kb
Host smart-43a5cce8-7a6b-44ba-94ab-035fb582321f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14695
8398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.146958398
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2263303407
Short name T1294
Test name
Test status
Simulation time 3451945347 ps
CPU time 23.79 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:11:33 PM PDT 24
Peak memory 207080 kb
Host smart-c04c56b5-c316-4418-965a-616df3eb780e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2263303407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2263303407
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1471199344
Short name T1305
Test name
Test status
Simulation time 154435039 ps
CPU time 0.78 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:09 PM PDT 24
Peak memory 206860 kb
Host smart-0d92f2d0-8463-4942-8f52-5867f2bb5e2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1471199344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1471199344
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2021580955
Short name T2648
Test name
Test status
Simulation time 145215481 ps
CPU time 0.78 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:09 PM PDT 24
Peak memory 206868 kb
Host smart-02064414-2338-4426-b7e6-cd8e786ac259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20215
80955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2021580955
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.203325732
Short name T1992
Test name
Test status
Simulation time 176864739 ps
CPU time 0.88 seconds
Started Jul 13 07:11:04 PM PDT 24
Finished Jul 13 07:11:06 PM PDT 24
Peak memory 206896 kb
Host smart-8a5b342b-3399-40cc-a115-ccc3a33d90ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20332
5732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.203325732
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2160859886
Short name T2588
Test name
Test status
Simulation time 173113964 ps
CPU time 0.86 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:09 PM PDT 24
Peak memory 206864 kb
Host smart-bac36382-4843-4f3a-9803-8d0ad2d0c338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21608
59886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2160859886
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1741587651
Short name T1875
Test name
Test status
Simulation time 171215344 ps
CPU time 0.81 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:09 PM PDT 24
Peak memory 206852 kb
Host smart-c4ed5e45-ae2b-4d33-8cfa-b4f1428af97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17415
87651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1741587651
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1027420527
Short name T368
Test name
Test status
Simulation time 156175178 ps
CPU time 0.8 seconds
Started Jul 13 07:11:06 PM PDT 24
Finished Jul 13 07:11:07 PM PDT 24
Peak memory 206872 kb
Host smart-e1474bf3-39cf-4d2c-8b0e-cfe77b193137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
20527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1027420527
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.376396293
Short name T1888
Test name
Test status
Simulation time 246862874 ps
CPU time 0.97 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:10 PM PDT 24
Peak memory 206872 kb
Host smart-b3c75013-8582-4366-a52e-d5c554d88a94
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=376396293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.376396293
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3483220593
Short name T731
Test name
Test status
Simulation time 140819999 ps
CPU time 0.8 seconds
Started Jul 13 07:11:09 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206804 kb
Host smart-a5f54a53-6959-456a-a3af-a5c335cbeff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34832
20593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3483220593
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1144536818
Short name T2479
Test name
Test status
Simulation time 58738672 ps
CPU time 0.71 seconds
Started Jul 13 07:11:09 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206820 kb
Host smart-fc50c4db-df91-4f13-86cb-b7d03a222b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11445
36818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1144536818
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3667381423
Short name T1897
Test name
Test status
Simulation time 16116640444 ps
CPU time 39.42 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:48 PM PDT 24
Peak memory 207080 kb
Host smart-ec17a9bc-6ca4-40eb-b3ca-87e9380a98b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36673
81423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3667381423
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3486094806
Short name T487
Test name
Test status
Simulation time 166383479 ps
CPU time 0.82 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:11:10 PM PDT 24
Peak memory 206800 kb
Host smart-cfb0bedd-69b7-4c50-9ee7-9690cad51499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34860
94806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3486094806
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3986713046
Short name T902
Test name
Test status
Simulation time 217555956 ps
CPU time 0.86 seconds
Started Jul 13 07:11:06 PM PDT 24
Finished Jul 13 07:11:08 PM PDT 24
Peak memory 206892 kb
Host smart-aad6cf69-eb4a-4bbe-99d4-8a14d2d62375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39867
13046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3986713046
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1088417533
Short name T1723
Test name
Test status
Simulation time 239715538 ps
CPU time 1.01 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206884 kb
Host smart-8b435277-06e0-4179-9891-000ee85b77e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
17533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1088417533
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.623801982
Short name T1925
Test name
Test status
Simulation time 214759517 ps
CPU time 0.99 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206868 kb
Host smart-f9a4f11e-4ba0-4258-96a8-d5f287afcf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62380
1982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.623801982
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3919595283
Short name T2701
Test name
Test status
Simulation time 158722612 ps
CPU time 0.75 seconds
Started Jul 13 07:11:09 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206812 kb
Host smart-51254f58-5dfa-4c38-8f8c-d7ff2b5a390d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39195
95283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3919595283
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.142887999
Short name T294
Test name
Test status
Simulation time 178840485 ps
CPU time 0.76 seconds
Started Jul 13 07:11:09 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206808 kb
Host smart-2bb8f64b-70dc-418f-85b0-dfcaefa49d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14288
7999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.142887999
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1123317290
Short name T2474
Test name
Test status
Simulation time 255235680 ps
CPU time 1.02 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:11:10 PM PDT 24
Peak memory 206864 kb
Host smart-20113e3c-85c2-4bbd-9aca-85cceab873f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11233
17290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1123317290
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.952944321
Short name T908
Test name
Test status
Simulation time 5309337725 ps
CPU time 56.15 seconds
Started Jul 13 07:11:08 PM PDT 24
Finished Jul 13 07:12:05 PM PDT 24
Peak memory 207048 kb
Host smart-af4344da-dfaa-4138-91a2-cf17577568ae
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=952944321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.952944321
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.4039993123
Short name T723
Test name
Test status
Simulation time 150366445 ps
CPU time 0.81 seconds
Started Jul 13 07:11:07 PM PDT 24
Finished Jul 13 07:11:10 PM PDT 24
Peak memory 206860 kb
Host smart-2bef9375-e5ea-4e64-8ad1-18b01a6f3ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40399
93123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.4039993123
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3036548963
Short name T1998
Test name
Test status
Simulation time 185921421 ps
CPU time 0.83 seconds
Started Jul 13 07:11:09 PM PDT 24
Finished Jul 13 07:11:11 PM PDT 24
Peak memory 206804 kb
Host smart-4ccda329-1dff-43e9-8b16-e621b14a2da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30365
48963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3036548963
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3298047376
Short name T1855
Test name
Test status
Simulation time 380869084 ps
CPU time 1.17 seconds
Started Jul 13 07:11:05 PM PDT 24
Finished Jul 13 07:11:07 PM PDT 24
Peak memory 206852 kb
Host smart-59fd60b8-728f-4de8-a3c4-4144f7c359ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32980
47376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3298047376
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2252924832
Short name T1297
Test name
Test status
Simulation time 6524966383 ps
CPU time 186.53 seconds
Started Jul 13 07:11:09 PM PDT 24
Finished Jul 13 07:14:17 PM PDT 24
Peak memory 207144 kb
Host smart-b01e2d37-b429-4c48-bb9d-b84fead32dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22529
24832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2252924832
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3141532837
Short name T834
Test name
Test status
Simulation time 86624888 ps
CPU time 0.73 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 206928 kb
Host smart-dbf06402-f13c-410e-8863-fa39b7641e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3141532837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3141532837
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1848080193
Short name T2012
Test name
Test status
Simulation time 4331951403 ps
CPU time 4.78 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 206964 kb
Host smart-8640676a-c022-483b-85d3-50c02ac32e64
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1848080193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.1848080193
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2282968843
Short name T1208
Test name
Test status
Simulation time 13488851618 ps
CPU time 12.28 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:31 PM PDT 24
Peak memory 207120 kb
Host smart-fadfe735-986b-48d5-acfb-c115cc89f90b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2282968843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2282968843
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1744243583
Short name T12
Test name
Test status
Simulation time 23393595600 ps
CPU time 25.84 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:11:48 PM PDT 24
Peak memory 206920 kb
Host smart-17c91bf5-b4b6-4859-880d-d14aca81a482
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1744243583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1744243583
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1385698836
Short name T888
Test name
Test status
Simulation time 158695316 ps
CPU time 0.81 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:18 PM PDT 24
Peak memory 206860 kb
Host smart-91fef9f5-ce23-4fb0-ac89-21f24e2e5763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
98836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1385698836
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1876738561
Short name T1065
Test name
Test status
Simulation time 187847348 ps
CPU time 0.84 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:19 PM PDT 24
Peak memory 206868 kb
Host smart-97c27f1c-862d-4818-82cd-d7f569e6d3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18767
38561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1876738561
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.151562917
Short name T2409
Test name
Test status
Simulation time 366504693 ps
CPU time 1.25 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:18 PM PDT 24
Peak memory 206912 kb
Host smart-9ff8323a-bb57-4359-837a-be2671cd76b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15156
2917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.151562917
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2788513433
Short name T1960
Test name
Test status
Simulation time 992715974 ps
CPU time 2.38 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 207008 kb
Host smart-e5c0edea-0df5-4593-bdee-bc6bb30c4bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
13433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2788513433
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2446668321
Short name T1376
Test name
Test status
Simulation time 9179011356 ps
CPU time 17.65 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:38 PM PDT 24
Peak memory 207100 kb
Host smart-6b0d5ad3-ce9a-4f46-9900-5cc70801adad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24466
68321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2446668321
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1157927158
Short name T547
Test name
Test status
Simulation time 473609612 ps
CPU time 1.39 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 206872 kb
Host smart-fb54c39a-a241-4e79-9798-d32fa080f1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11579
27158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1157927158
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1042366373
Short name T776
Test name
Test status
Simulation time 161818877 ps
CPU time 0.81 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:20 PM PDT 24
Peak memory 206860 kb
Host smart-9957a475-f7f6-4108-a0c5-aa7056323d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10423
66373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1042366373
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3329298986
Short name T2742
Test name
Test status
Simulation time 71658914 ps
CPU time 0.71 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:18 PM PDT 24
Peak memory 206868 kb
Host smart-50933cff-7499-4a1d-a6c6-ba5de6d2b00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33292
98986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3329298986
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1711245895
Short name T938
Test name
Test status
Simulation time 808628920 ps
CPU time 2.09 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 207108 kb
Host smart-a569a243-4f29-4779-a9d1-e0f1bfc1e721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17112
45895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1711245895
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.424222128
Short name T1231
Test name
Test status
Simulation time 435035412 ps
CPU time 2.8 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:20 PM PDT 24
Peak memory 206996 kb
Host smart-91d0012b-92a0-4e54-a8bd-6f1e3ff35573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42422
2128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.424222128
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1178083049
Short name T784
Test name
Test status
Simulation time 163761691 ps
CPU time 0.8 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 206888 kb
Host smart-3c4ef5b7-47b0-4e73-9e71-1a2191e46700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11780
83049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1178083049
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3098869561
Short name T327
Test name
Test status
Simulation time 165718962 ps
CPU time 0.82 seconds
Started Jul 13 07:11:15 PM PDT 24
Finished Jul 13 07:11:17 PM PDT 24
Peak memory 206880 kb
Host smart-e86c81c3-e69d-4ea0-a48a-0a97dd5939df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30988
69561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3098869561
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1440982970
Short name T437
Test name
Test status
Simulation time 242184150 ps
CPU time 0.97 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 206864 kb
Host smart-4e97b93a-6787-4e66-8a3a-30ab1000b397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14409
82970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1440982970
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3562911794
Short name T2647
Test name
Test status
Simulation time 232307189 ps
CPU time 0.95 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:20 PM PDT 24
Peak memory 206804 kb
Host smart-c15f6082-fc6d-407a-80d5-26a71f0e2fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35629
11794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3562911794
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.455000979
Short name T1714
Test name
Test status
Simulation time 23321560081 ps
CPU time 21.25 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:38 PM PDT 24
Peak memory 206928 kb
Host smart-251187eb-ffa1-4d41-bd86-c68ab447d2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45500
0979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.455000979
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3535876084
Short name T1609
Test name
Test status
Simulation time 3261389758 ps
CPU time 3.69 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 206940 kb
Host smart-426867de-889a-46f0-8c9e-57c75d22910c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35358
76084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3535876084
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3635545010
Short name T2104
Test name
Test status
Simulation time 9434446763 ps
CPU time 248.49 seconds
Started Jul 13 07:11:20 PM PDT 24
Finished Jul 13 07:15:32 PM PDT 24
Peak memory 207136 kb
Host smart-b30d45ec-9b6e-4d09-8d53-caeebbbacdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36355
45010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3635545010
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.515827962
Short name T1071
Test name
Test status
Simulation time 3800672155 ps
CPU time 37.77 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:59 PM PDT 24
Peak memory 207088 kb
Host smart-55d4d805-9e0f-4081-a37f-93dec94bb938
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=515827962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.515827962
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2589573667
Short name T1092
Test name
Test status
Simulation time 283478971 ps
CPU time 1 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:22 PM PDT 24
Peak memory 206824 kb
Host smart-d86a216e-fca8-49ab-8fc7-b81aa36b4dca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2589573667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2589573667
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.509344742
Short name T755
Test name
Test status
Simulation time 233733936 ps
CPU time 0.85 seconds
Started Jul 13 07:11:14 PM PDT 24
Finished Jul 13 07:11:15 PM PDT 24
Peak memory 206852 kb
Host smart-bf32970d-333d-4252-b856-5368cac3d552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50934
4742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.509344742
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3288935047
Short name T1156
Test name
Test status
Simulation time 5711648054 ps
CPU time 160.47 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:14:02 PM PDT 24
Peak memory 207112 kb
Host smart-2b66b3f9-9ebe-4ab2-8e95-3b862f3655f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32889
35047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3288935047
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.411444127
Short name T1049
Test name
Test status
Simulation time 3549465301 ps
CPU time 95.06 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:12:53 PM PDT 24
Peak memory 207100 kb
Host smart-3f307792-1330-48c9-93f0-1d6351d67095
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=411444127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.411444127
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2154138619
Short name T2258
Test name
Test status
Simulation time 162756556 ps
CPU time 0.83 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 206872 kb
Host smart-bc951597-0878-4fec-8e65-16626a69c243
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2154138619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2154138619
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1455780330
Short name T2534
Test name
Test status
Simulation time 218033977 ps
CPU time 0.84 seconds
Started Jul 13 07:11:23 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 206880 kb
Host smart-5d25c1af-718b-42dd-a740-229ba72238f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14557
80330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1455780330
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3222425073
Short name T836
Test name
Test status
Simulation time 192836421 ps
CPU time 0.97 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 206876 kb
Host smart-c1e6298e-c6ee-454b-a5ef-816fe0ef61fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32224
25073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3222425073
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1430389128
Short name T2163
Test name
Test status
Simulation time 211858566 ps
CPU time 0.82 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:26 PM PDT 24
Peak memory 206872 kb
Host smart-f5d1e0b4-cf2e-456a-9ef0-12c4deacdddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
89128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1430389128
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2363878925
Short name T835
Test name
Test status
Simulation time 173993575 ps
CPU time 0.86 seconds
Started Jul 13 07:11:15 PM PDT 24
Finished Jul 13 07:11:16 PM PDT 24
Peak memory 206872 kb
Host smart-a3649488-bbb9-48c6-86da-b4c04d81b2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23638
78925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2363878925
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1946129488
Short name T1808
Test name
Test status
Simulation time 207585123 ps
CPU time 0.9 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:18 PM PDT 24
Peak memory 206812 kb
Host smart-242f1ef3-802e-417d-8e67-d03cb63935f3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1946129488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1946129488
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1288683893
Short name T2657
Test name
Test status
Simulation time 37040003 ps
CPU time 0.65 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:20 PM PDT 24
Peak memory 206860 kb
Host smart-d8864697-795e-4dfc-9b27-4f301512cf2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886
83893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1288683893
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.91673850
Short name T220
Test name
Test status
Simulation time 21600600550 ps
CPU time 53.88 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:12:16 PM PDT 24
Peak memory 207096 kb
Host smart-8535cd09-a39a-40c1-83fb-c1b808462c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91673
850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.91673850
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3789584288
Short name T2391
Test name
Test status
Simulation time 176111653 ps
CPU time 0.85 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:17 PM PDT 24
Peak memory 206860 kb
Host smart-65243786-81ab-42fd-b305-7af0fbf3aa27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37895
84288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3789584288
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3108649030
Short name T340
Test name
Test status
Simulation time 236183626 ps
CPU time 0.94 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 206864 kb
Host smart-45d76157-6673-4ac3-ba24-ce0500b28248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31086
49030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3108649030
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.4224144656
Short name T394
Test name
Test status
Simulation time 211837004 ps
CPU time 0.86 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 206872 kb
Host smart-c66b4a51-3047-4bfb-be7e-d489dcccbdb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42241
44656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.4224144656
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3098440487
Short name T1799
Test name
Test status
Simulation time 193203704 ps
CPU time 0.85 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:25 PM PDT 24
Peak memory 206868 kb
Host smart-45215142-1141-4793-a3ad-575ea7d02b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
40487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3098440487
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2065245135
Short name T1379
Test name
Test status
Simulation time 208156616 ps
CPU time 0.89 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:19 PM PDT 24
Peak memory 206892 kb
Host smart-5235f24d-6e91-4e8c-8b15-c117167dcfa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20652
45135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2065245135
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3375343924
Short name T457
Test name
Test status
Simulation time 176473944 ps
CPU time 0.79 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:17 PM PDT 24
Peak memory 206828 kb
Host smart-1b92c14a-8a67-4f66-98eb-e991071774b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33753
43924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3375343924
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1370208650
Short name T1457
Test name
Test status
Simulation time 162774677 ps
CPU time 0.79 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:11:24 PM PDT 24
Peak memory 206868 kb
Host smart-e1576d17-63b3-4d71-8098-61ddb200cff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13702
08650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1370208650
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.316191538
Short name T1657
Test name
Test status
Simulation time 207893254 ps
CPU time 0.88 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 206876 kb
Host smart-c6ec1626-d423-4f37-a2db-0de5ff76c3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31619
1538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.316191538
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3769343226
Short name T1024
Test name
Test status
Simulation time 4267283362 ps
CPU time 115.76 seconds
Started Jul 13 07:11:23 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 207060 kb
Host smart-0c15a304-f606-4e89-9bcc-b4aa9d975a5d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3769343226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3769343226
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3483822861
Short name T1894
Test name
Test status
Simulation time 185454075 ps
CPU time 0.81 seconds
Started Jul 13 07:11:17 PM PDT 24
Finished Jul 13 07:11:20 PM PDT 24
Peak memory 206868 kb
Host smart-db0906dd-cfcb-4d42-80d9-20c308308c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34838
22861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3483822861
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.381820235
Short name T1786
Test name
Test status
Simulation time 188066981 ps
CPU time 0.89 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:11:24 PM PDT 24
Peak memory 206884 kb
Host smart-03002fbd-d43a-4984-bb7d-3fcb74f788b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38182
0235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.381820235
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.1500200610
Short name T2073
Test name
Test status
Simulation time 674429422 ps
CPU time 1.66 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:26 PM PDT 24
Peak memory 207068 kb
Host smart-2af3d93e-51d0-4f9d-98ed-74da45921766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15002
00610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.1500200610
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2323466529
Short name T1075
Test name
Test status
Simulation time 5389856275 ps
CPU time 55.33 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:12:16 PM PDT 24
Peak memory 207132 kb
Host smart-f0312672-b2ea-4da8-9bc0-7ab83001b3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23234
66529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2323466529
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2214433999
Short name T1431
Test name
Test status
Simulation time 40749146 ps
CPU time 0.68 seconds
Started Jul 13 07:11:23 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 206888 kb
Host smart-1bf3650e-03f0-4248-9011-1d6a57221f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2214433999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2214433999
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1771782150
Short name T1893
Test name
Test status
Simulation time 13340797060 ps
CPU time 13.62 seconds
Started Jul 13 07:11:20 PM PDT 24
Finished Jul 13 07:11:37 PM PDT 24
Peak memory 206932 kb
Host smart-bf5e000e-ba61-4810-93da-6402de4152a1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1771782150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1771782150
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2120679117
Short name T171
Test name
Test status
Simulation time 23500615879 ps
CPU time 30.01 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:54 PM PDT 24
Peak memory 207132 kb
Host smart-1d08b833-ab3a-4761-9b29-bcef623f8207
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2120679117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2120679117
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3365958445
Short name T2254
Test name
Test status
Simulation time 152297524 ps
CPU time 0.81 seconds
Started Jul 13 07:11:20 PM PDT 24
Finished Jul 13 07:11:25 PM PDT 24
Peak memory 206756 kb
Host smart-cde85ef9-6465-438c-8848-de9ac8d41cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
58445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3365958445
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3669342000
Short name T1928
Test name
Test status
Simulation time 145760235 ps
CPU time 0.76 seconds
Started Jul 13 07:11:16 PM PDT 24
Finished Jul 13 07:11:18 PM PDT 24
Peak memory 206892 kb
Host smart-721e2519-b1fd-438d-8e63-8f05d9e81beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36693
42000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3669342000
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2025262328
Short name T101
Test name
Test status
Simulation time 627122856 ps
CPU time 1.92 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:11:25 PM PDT 24
Peak memory 207064 kb
Host smart-d84dedae-7b09-49c5-bcb1-951ac41fe944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20252
62328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2025262328
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3029674285
Short name T1906
Test name
Test status
Simulation time 1102715860 ps
CPU time 2.61 seconds
Started Jul 13 07:11:20 PM PDT 24
Finished Jul 13 07:11:26 PM PDT 24
Peak memory 206988 kb
Host smart-0ca66613-c69a-4869-91ae-1951566313f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30296
74285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3029674285
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1141870384
Short name T91
Test name
Test status
Simulation time 9764620896 ps
CPU time 20.68 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:11:44 PM PDT 24
Peak memory 207084 kb
Host smart-5051cfdd-c7f6-4ea4-a2e4-c084e1a73959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11418
70384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1141870384
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3755755940
Short name T1159
Test name
Test status
Simulation time 385955455 ps
CPU time 1.24 seconds
Started Jul 13 07:11:19 PM PDT 24
Finished Jul 13 07:11:24 PM PDT 24
Peak memory 206752 kb
Host smart-5784e9cd-c8c2-474a-b601-513f56bfacb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37557
55940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3755755940
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2008928205
Short name T1498
Test name
Test status
Simulation time 164683669 ps
CPU time 0.75 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:23 PM PDT 24
Peak memory 206868 kb
Host smart-31706e85-4e70-4aa5-a0db-40fa6b3330f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20089
28205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2008928205
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.377584569
Short name T1711
Test name
Test status
Simulation time 36667575 ps
CPU time 0.68 seconds
Started Jul 13 07:11:20 PM PDT 24
Finished Jul 13 07:11:24 PM PDT 24
Peak memory 206720 kb
Host smart-ec727ea8-6c97-47c6-9dc4-08263feeabf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37758
4569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.377584569
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.808506533
Short name T1495
Test name
Test status
Simulation time 837123657 ps
CPU time 2.02 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 207080 kb
Host smart-da277666-c7be-4856-b50c-a6ed5df465bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80850
6533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.808506533
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2512452249
Short name T1773
Test name
Test status
Simulation time 421870912 ps
CPU time 2.34 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 207068 kb
Host smart-093da9ce-3957-44bf-a648-0700bc66c967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25124
52249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2512452249
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1445200370
Short name T975
Test name
Test status
Simulation time 171252904 ps
CPU time 0.85 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:25 PM PDT 24
Peak memory 206876 kb
Host smart-50940995-dc8c-40f3-8d29-8277af5b365d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14452
00370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1445200370
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.43611619
Short name T2707
Test name
Test status
Simulation time 205454248 ps
CPU time 0.82 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:26 PM PDT 24
Peak memory 207108 kb
Host smart-453b7c1e-3223-47fd-b389-8147f643efc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43611
619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.43611619
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.907279174
Short name T2010
Test name
Test status
Simulation time 203695158 ps
CPU time 0.84 seconds
Started Jul 13 07:11:23 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 206876 kb
Host smart-65300373-df93-4666-baa1-bd0f20948f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90727
9174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.907279174
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3579310277
Short name T2378
Test name
Test status
Simulation time 210699881 ps
CPU time 0.86 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:22 PM PDT 24
Peak memory 206872 kb
Host smart-fabaa361-6052-45da-854e-c7e82398f8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35793
10277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3579310277
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.3733130783
Short name T1853
Test name
Test status
Simulation time 23360460737 ps
CPU time 23.3 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:49 PM PDT 24
Peak memory 206208 kb
Host smart-6da2fdb8-f05f-4812-957c-b8c24087c966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37331
30783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.3733130783
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1621023393
Short name T866
Test name
Test status
Simulation time 3345131746 ps
CPU time 4.34 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:11:25 PM PDT 24
Peak memory 206912 kb
Host smart-91ff52c3-4280-45e8-9737-aa558c6112e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16210
23393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1621023393
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2451519940
Short name T2573
Test name
Test status
Simulation time 9451362049 ps
CPU time 261.74 seconds
Started Jul 13 07:11:18 PM PDT 24
Finished Jul 13 07:15:44 PM PDT 24
Peak memory 207148 kb
Host smart-baa864de-3a57-4f40-9bab-e22d8fa5fdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24515
19940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2451519940
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3536472890
Short name T2352
Test name
Test status
Simulation time 4072975498 ps
CPU time 38.26 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:12:03 PM PDT 24
Peak memory 207092 kb
Host smart-387ba630-0d20-4f74-8b3d-206d2d35a7e7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3536472890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3536472890
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3515089776
Short name T929
Test name
Test status
Simulation time 266996364 ps
CPU time 0.94 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206880 kb
Host smart-6a79eeae-4317-4461-9980-066399c8464a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3515089776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3515089776
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.487845334
Short name T2113
Test name
Test status
Simulation time 219755822 ps
CPU time 0.95 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 207112 kb
Host smart-d47a80dc-c267-4085-a051-283f90f53f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48784
5334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.487845334
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2792276972
Short name T992
Test name
Test status
Simulation time 4498441448 ps
CPU time 126.01 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:13:33 PM PDT 24
Peak memory 207072 kb
Host smart-0cd93d49-a2ca-4ca7-87bc-537d74a76e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27922
76972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2792276972
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.3689689106
Short name T2548
Test name
Test status
Simulation time 5557084836 ps
CPU time 55.91 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 207092 kb
Host smart-0dff2e82-0076-4f1c-81b3-bec1ee28591b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3689689106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.3689689106
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3238094304
Short name T1099
Test name
Test status
Simulation time 164494808 ps
CPU time 0.84 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206868 kb
Host smart-da5310da-2bc8-4bc4-9fa4-c0bdad9df987
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3238094304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3238094304
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.405259148
Short name T1777
Test name
Test status
Simulation time 156941355 ps
CPU time 0.79 seconds
Started Jul 13 07:11:25 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206864 kb
Host smart-e08dba84-9697-4795-b09c-a10587242db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
9148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.405259148
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2019271318
Short name T137
Test name
Test status
Simulation time 204494621 ps
CPU time 0.81 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:25 PM PDT 24
Peak memory 206844 kb
Host smart-334f761c-aa0a-49f0-b49e-26cf50e143c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20192
71318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2019271318
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3032923347
Short name T2292
Test name
Test status
Simulation time 177744183 ps
CPU time 0.85 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:11:30 PM PDT 24
Peak memory 206876 kb
Host smart-e5d247cf-5d80-427f-92ad-7da2cb2d03b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329
23347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3032923347
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.738799112
Short name T425
Test name
Test status
Simulation time 174752617 ps
CPU time 0.84 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 206860 kb
Host smart-a2a6e24b-a7cd-443d-ad22-eadb54d8dfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73879
9112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.738799112
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1179211459
Short name T713
Test name
Test status
Simulation time 181468609 ps
CPU time 0.86 seconds
Started Jul 13 07:11:25 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206872 kb
Host smart-ff6efcb3-cb17-4bdf-bfc9-0f7f1570e8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11792
11459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1179211459
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.288052821
Short name T2271
Test name
Test status
Simulation time 152981543 ps
CPU time 0.78 seconds
Started Jul 13 07:11:29 PM PDT 24
Finished Jul 13 07:11:31 PM PDT 24
Peak memory 206872 kb
Host smart-822c3cf1-2076-4d3e-b671-915a3632d6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28805
2821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.288052821
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2713942205
Short name T1427
Test name
Test status
Simulation time 199568848 ps
CPU time 0.91 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:11:30 PM PDT 24
Peak memory 206876 kb
Host smart-6e93ed43-3516-4a45-ad99-ba09ad429d77
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2713942205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2713942205
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3158485258
Short name T1899
Test name
Test status
Simulation time 139972625 ps
CPU time 0.77 seconds
Started Jul 13 07:11:29 PM PDT 24
Finished Jul 13 07:11:31 PM PDT 24
Peak memory 206856 kb
Host smart-dd9ef7bf-ec9e-4a28-85d9-e468366acaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31584
85258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3158485258
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1029141556
Short name T2234
Test name
Test status
Simulation time 36090524 ps
CPU time 0.65 seconds
Started Jul 13 07:11:29 PM PDT 24
Finished Jul 13 07:11:31 PM PDT 24
Peak memory 206868 kb
Host smart-b89fa405-b012-41d0-9609-4c3e9f42fde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10291
41556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1029141556
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1670239050
Short name T475
Test name
Test status
Simulation time 20050382216 ps
CPU time 49.47 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:12:16 PM PDT 24
Peak memory 207100 kb
Host smart-9cda38a7-17f6-48da-b325-70bd41fa5cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16702
39050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1670239050
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1629026725
Short name T2125
Test name
Test status
Simulation time 178363519 ps
CPU time 0.8 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 206872 kb
Host smart-51cbbd84-71f9-4792-b353-d23beb499d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
26725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1629026725
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.357713202
Short name T1411
Test name
Test status
Simulation time 242503115 ps
CPU time 0.9 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:11:30 PM PDT 24
Peak memory 206852 kb
Host smart-dd75e20c-63ce-4f8c-8a54-8f1b8ba08bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35771
3202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.357713202
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3855291940
Short name T847
Test name
Test status
Simulation time 221333961 ps
CPU time 0.89 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206872 kb
Host smart-d0646712-1160-4954-8834-1235a236ac46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38552
91940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3855291940
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.360997779
Short name T2484
Test name
Test status
Simulation time 180275423 ps
CPU time 0.8 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:11:30 PM PDT 24
Peak memory 206860 kb
Host smart-ee405838-3f81-4951-8867-173be43c3df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36099
7779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.360997779
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3836011437
Short name T2285
Test name
Test status
Simulation time 194866865 ps
CPU time 0.85 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 206864 kb
Host smart-0c196064-e42a-45a2-b7ea-9ae03e8b9b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38360
11437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3836011437
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3972276908
Short name T1408
Test name
Test status
Simulation time 151010207 ps
CPU time 0.79 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206868 kb
Host smart-06ab0063-7ac9-45c1-ac69-16381c0340f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39722
76908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3972276908
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1913613006
Short name T1372
Test name
Test status
Simulation time 151053001 ps
CPU time 0.8 seconds
Started Jul 13 07:11:23 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 206856 kb
Host smart-64e3ce72-f51e-4d97-b92e-89354f0afaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19136
13006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1913613006
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.902394362
Short name T591
Test name
Test status
Simulation time 179458324 ps
CPU time 0.84 seconds
Started Jul 13 07:11:21 PM PDT 24
Finished Jul 13 07:11:25 PM PDT 24
Peak memory 206876 kb
Host smart-9b5f77c1-9e34-4795-bf27-fff1edd58b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90239
4362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.902394362
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3383709988
Short name T2265
Test name
Test status
Simulation time 6021533653 ps
CPU time 166.7 seconds
Started Jul 13 07:11:25 PM PDT 24
Finished Jul 13 07:14:14 PM PDT 24
Peak memory 207068 kb
Host smart-45833adb-75e7-410a-98d7-b477ab2af1cd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3383709988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3383709988
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3681196775
Short name T2262
Test name
Test status
Simulation time 194187148 ps
CPU time 0.89 seconds
Started Jul 13 07:11:22 PM PDT 24
Finished Jul 13 07:11:27 PM PDT 24
Peak memory 206872 kb
Host smart-170a8626-9c26-4d5a-b834-eaa2bc8fbab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811
96775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3681196775
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.364620900
Short name T1997
Test name
Test status
Simulation time 197954386 ps
CPU time 0.81 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206876 kb
Host smart-d4146d38-079c-4442-b487-3a1e3a66fc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36462
0900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.364620900
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.781237397
Short name T2288
Test name
Test status
Simulation time 493413301 ps
CPU time 1.28 seconds
Started Jul 13 07:11:29 PM PDT 24
Finished Jul 13 07:11:32 PM PDT 24
Peak memory 206876 kb
Host smart-135de2ac-8c34-4d90-a1bb-907472577511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78123
7397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.781237397
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.667723646
Short name T153
Test name
Test status
Simulation time 4529293905 ps
CPU time 41.95 seconds
Started Jul 13 07:11:29 PM PDT 24
Finished Jul 13 07:12:12 PM PDT 24
Peak memory 207116 kb
Host smart-abe9840e-77d0-4a01-9133-aeb07a417b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66772
3646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.667723646
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.813776828
Short name T2349
Test name
Test status
Simulation time 56143434 ps
CPU time 0.7 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:11:43 PM PDT 24
Peak memory 206916 kb
Host smart-7be07251-2c48-47cf-b653-4ffa83f03b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=813776828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.813776828
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.4047813838
Short name T2431
Test name
Test status
Simulation time 3670265254 ps
CPU time 4.77 seconds
Started Jul 13 07:11:23 PM PDT 24
Finished Jul 13 07:11:31 PM PDT 24
Peak memory 207292 kb
Host smart-5b38cd10-b75a-4b46-ab72-10c8c7247701
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4047813838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.4047813838
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1897890986
Short name T1549
Test name
Test status
Simulation time 13328833579 ps
CPU time 13.37 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:40 PM PDT 24
Peak memory 206916 kb
Host smart-e21d54e6-1c7b-4733-80a0-689b0bf1c8f6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1897890986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1897890986
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3555522144
Short name T843
Test name
Test status
Simulation time 23405022760 ps
CPU time 21.41 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:11:51 PM PDT 24
Peak memory 207040 kb
Host smart-af6df85c-3fd9-49c7-898d-366521685639
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3555522144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3555522144
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1645644468
Short name T411
Test name
Test status
Simulation time 157910462 ps
CPU time 0.79 seconds
Started Jul 13 07:11:27 PM PDT 24
Finished Jul 13 07:11:29 PM PDT 24
Peak memory 206860 kb
Host smart-7bdd7952-d637-443d-853e-b53d3450c3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16456
44468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1645644468
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2570755349
Short name T352
Test name
Test status
Simulation time 174138714 ps
CPU time 0.81 seconds
Started Jul 13 07:11:25 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206868 kb
Host smart-923ef6cc-2413-4248-85cb-d7cab94f486d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25707
55349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2570755349
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2825406995
Short name T973
Test name
Test status
Simulation time 308577012 ps
CPU time 1.09 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:11:31 PM PDT 24
Peak memory 206856 kb
Host smart-54f235d2-8042-45ac-96ed-080c371b4d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28254
06995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2825406995
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.820113435
Short name T1116
Test name
Test status
Simulation time 1289396425 ps
CPU time 2.63 seconds
Started Jul 13 07:11:23 PM PDT 24
Finished Jul 13 07:11:29 PM PDT 24
Peak memory 207004 kb
Host smart-b211dc8e-718f-459d-8a26-ce478d68ed67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82011
3435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.820113435
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3542342055
Short name T861
Test name
Test status
Simulation time 17215700947 ps
CPU time 33.61 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:12:01 PM PDT 24
Peak memory 207016 kb
Host smart-2a7307d8-491b-4202-a9c1-513b79dec1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35423
42055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3542342055
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1458259720
Short name T303
Test name
Test status
Simulation time 387514377 ps
CPU time 1.23 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:11:30 PM PDT 24
Peak memory 206860 kb
Host smart-33ec93d0-a5f4-437d-8969-cd205c812384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14582
59720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1458259720
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.761347133
Short name T2252
Test name
Test status
Simulation time 200088521 ps
CPU time 0.83 seconds
Started Jul 13 07:11:25 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206864 kb
Host smart-b7a7ee8d-d6fa-4288-9504-fbc9274166be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76134
7133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.761347133
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.89190491
Short name T1965
Test name
Test status
Simulation time 40567244 ps
CPU time 0.68 seconds
Started Jul 13 07:11:24 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 206860 kb
Host smart-7cb6433d-f24c-4660-8be5-6bf20f949597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89190
491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.89190491
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.430920259
Short name T2410
Test name
Test status
Simulation time 859202263 ps
CPU time 1.98 seconds
Started Jul 13 07:11:29 PM PDT 24
Finished Jul 13 07:11:32 PM PDT 24
Peak memory 207064 kb
Host smart-e89969cd-437e-45c2-bef8-98952fd66ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43092
0259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.430920259
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3338381412
Short name T23
Test name
Test status
Simulation time 236865511 ps
CPU time 2.18 seconds
Started Jul 13 07:11:28 PM PDT 24
Finished Jul 13 07:11:32 PM PDT 24
Peak memory 207032 kb
Host smart-dd72355e-6af4-4432-9ccd-ca9004a74dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33383
81412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3338381412
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1842871767
Short name T2585
Test name
Test status
Simulation time 216112579 ps
CPU time 0.88 seconds
Started Jul 13 07:11:37 PM PDT 24
Finished Jul 13 07:11:39 PM PDT 24
Peak memory 206864 kb
Host smart-c39eadbc-4852-4dcc-ac3a-255d822f6b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18428
71767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1842871767
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3823607177
Short name T891
Test name
Test status
Simulation time 145057054 ps
CPU time 0.75 seconds
Started Jul 13 07:11:34 PM PDT 24
Finished Jul 13 07:11:35 PM PDT 24
Peak memory 206828 kb
Host smart-b754f3df-8998-4585-944a-66980583426b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38236
07177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3823607177
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2228428177
Short name T1290
Test name
Test status
Simulation time 240442757 ps
CPU time 0.97 seconds
Started Jul 13 07:11:36 PM PDT 24
Finished Jul 13 07:11:38 PM PDT 24
Peak memory 206876 kb
Host smart-987e8ec2-9b12-4841-8c62-47dbe60b833d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22284
28177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2228428177
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.3868865131
Short name T2375
Test name
Test status
Simulation time 6439515563 ps
CPU time 21.1 seconds
Started Jul 13 07:11:35 PM PDT 24
Finished Jul 13 07:11:57 PM PDT 24
Peak memory 207052 kb
Host smart-5f5c5ba0-5f62-482e-8447-655fb5725d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38688
65131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3868865131
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2346512717
Short name T2507
Test name
Test status
Simulation time 239311470 ps
CPU time 0.9 seconds
Started Jul 13 07:11:32 PM PDT 24
Finished Jul 13 07:11:34 PM PDT 24
Peak memory 206860 kb
Host smart-3edfe6f7-6155-4734-b214-07e694bf09c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
12717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2346512717
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.562531396
Short name T2212
Test name
Test status
Simulation time 23292425221 ps
CPU time 22.88 seconds
Started Jul 13 07:11:36 PM PDT 24
Finished Jul 13 07:12:00 PM PDT 24
Peak memory 206940 kb
Host smart-0a838633-2704-4a86-a2fc-eb04a33b2564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56253
1396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.562531396
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.130183366
Short name T2319
Test name
Test status
Simulation time 3322338757 ps
CPU time 4.01 seconds
Started Jul 13 07:11:36 PM PDT 24
Finished Jul 13 07:11:41 PM PDT 24
Peak memory 206872 kb
Host smart-4891f3e3-462d-4637-8eab-dbe07eac490d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13018
3366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.130183366
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3655803627
Short name T1629
Test name
Test status
Simulation time 6822120248 ps
CPU time 68.96 seconds
Started Jul 13 07:11:36 PM PDT 24
Finished Jul 13 07:12:46 PM PDT 24
Peak memory 207136 kb
Host smart-f7a02934-e6a8-44b0-8eef-07ea160e25c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36558
03627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3655803627
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1419381797
Short name T2740
Test name
Test status
Simulation time 6490515470 ps
CPU time 48 seconds
Started Jul 13 07:11:35 PM PDT 24
Finished Jul 13 07:12:24 PM PDT 24
Peak memory 207092 kb
Host smart-598f14aa-5e3c-4f44-9e51-b4b14e6b7f3a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1419381797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1419381797
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.237359841
Short name T1782
Test name
Test status
Simulation time 231115170 ps
CPU time 0.92 seconds
Started Jul 13 07:11:34 PM PDT 24
Finished Jul 13 07:11:36 PM PDT 24
Peak memory 206876 kb
Host smart-49c20c93-1f93-403c-af1a-4bc77deb5d40
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=237359841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.237359841
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2010431424
Short name T2065
Test name
Test status
Simulation time 191152754 ps
CPU time 0.86 seconds
Started Jul 13 07:11:32 PM PDT 24
Finished Jul 13 07:11:33 PM PDT 24
Peak memory 206868 kb
Host smart-ab099b56-bee7-41d0-ab78-7b2d8768940b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20104
31424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2010431424
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.881858592
Short name T356
Test name
Test status
Simulation time 6165725768 ps
CPU time 62.64 seconds
Started Jul 13 07:11:35 PM PDT 24
Finished Jul 13 07:12:39 PM PDT 24
Peak memory 206888 kb
Host smart-ea3a4708-eee4-4885-8da2-a6a9d17c6961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88185
8592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.881858592
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3336257920
Short name T1370
Test name
Test status
Simulation time 5351495783 ps
CPU time 38.09 seconds
Started Jul 13 07:11:37 PM PDT 24
Finished Jul 13 07:12:16 PM PDT 24
Peak memory 207128 kb
Host smart-d6f9b035-e200-4a08-8f88-6f1285d8d064
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3336257920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3336257920
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1865957559
Short name T605
Test name
Test status
Simulation time 151546567 ps
CPU time 0.8 seconds
Started Jul 13 07:11:34 PM PDT 24
Finished Jul 13 07:11:35 PM PDT 24
Peak memory 206868 kb
Host smart-7584918e-7fa9-4902-adc3-d881c284563e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1865957559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1865957559
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3883362795
Short name T625
Test name
Test status
Simulation time 144444582 ps
CPU time 0.75 seconds
Started Jul 13 07:11:34 PM PDT 24
Finished Jul 13 07:11:36 PM PDT 24
Peak memory 206868 kb
Host smart-3bba9767-78ff-4d8f-8a69-677fae1d6e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38833
62795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3883362795
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.729776931
Short name T119
Test name
Test status
Simulation time 213641408 ps
CPU time 0.89 seconds
Started Jul 13 07:11:35 PM PDT 24
Finished Jul 13 07:11:37 PM PDT 24
Peak memory 206656 kb
Host smart-ec7bb3df-885d-4d28-ada9-bff2a31ef90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72977
6931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.729776931
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1041650896
Short name T837
Test name
Test status
Simulation time 167653449 ps
CPU time 0.82 seconds
Started Jul 13 07:11:36 PM PDT 24
Finished Jul 13 07:11:38 PM PDT 24
Peak memory 206848 kb
Host smart-ee530345-b002-41f0-8683-4fc583e7bbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10416
50896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1041650896
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1580643258
Short name T2146
Test name
Test status
Simulation time 188919505 ps
CPU time 0.88 seconds
Started Jul 13 07:11:36 PM PDT 24
Finished Jul 13 07:11:38 PM PDT 24
Peak memory 206860 kb
Host smart-dea8de08-f669-48f0-93f4-2bd2c9a0546f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
43258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1580643258
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2176221128
Short name T441
Test name
Test status
Simulation time 165459407 ps
CPU time 0.87 seconds
Started Jul 13 07:11:38 PM PDT 24
Finished Jul 13 07:11:40 PM PDT 24
Peak memory 206860 kb
Host smart-d5ff94b2-95e3-43c1-9b99-61b8a06ff497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762
21128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2176221128
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3345851278
Short name T2602
Test name
Test status
Simulation time 161268008 ps
CPU time 0.79 seconds
Started Jul 13 07:11:33 PM PDT 24
Finished Jul 13 07:11:35 PM PDT 24
Peak memory 206864 kb
Host smart-464763c9-dbe6-450a-8ba4-1bc854945dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458
51278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3345851278
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.4045611060
Short name T1106
Test name
Test status
Simulation time 223563432 ps
CPU time 0.97 seconds
Started Jul 13 07:11:34 PM PDT 24
Finished Jul 13 07:11:37 PM PDT 24
Peak memory 206864 kb
Host smart-5a977c6a-bcae-45ad-8b29-2c1052ad9f42
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4045611060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.4045611060
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3499774972
Short name T1027
Test name
Test status
Simulation time 148950930 ps
CPU time 0.78 seconds
Started Jul 13 07:11:36 PM PDT 24
Finished Jul 13 07:11:38 PM PDT 24
Peak memory 206868 kb
Host smart-048ae867-8a54-4e67-a5b0-7b3e3e4e52dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34997
74972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3499774972
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2577903810
Short name T2655
Test name
Test status
Simulation time 44338768 ps
CPU time 0.64 seconds
Started Jul 13 07:11:36 PM PDT 24
Finished Jul 13 07:11:38 PM PDT 24
Peak memory 206872 kb
Host smart-3d1f2ee3-1c88-4e71-be87-4601ad993e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
03810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2577903810
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.4150150358
Short name T1122
Test name
Test status
Simulation time 14285797278 ps
CPU time 31.35 seconds
Started Jul 13 07:11:34 PM PDT 24
Finished Jul 13 07:12:06 PM PDT 24
Peak memory 207084 kb
Host smart-b7551e5b-bf4e-4fc7-9565-ec7b7029ec1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41501
50358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.4150150358
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.620580550
Short name T1506
Test name
Test status
Simulation time 203837853 ps
CPU time 0.86 seconds
Started Jul 13 07:11:32 PM PDT 24
Finished Jul 13 07:11:33 PM PDT 24
Peak memory 206864 kb
Host smart-3384788e-c196-49fe-bea7-960f38f8aaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62058
0550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.620580550
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1661519560
Short name T540
Test name
Test status
Simulation time 209070628 ps
CPU time 0.91 seconds
Started Jul 13 07:11:45 PM PDT 24
Finished Jul 13 07:11:46 PM PDT 24
Peak memory 206876 kb
Host smart-d41bfc31-e20c-4a66-be8c-de6a1445ebd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16615
19560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1661519560
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3300907718
Short name T2706
Test name
Test status
Simulation time 171087981 ps
CPU time 0.82 seconds
Started Jul 13 07:11:41 PM PDT 24
Finished Jul 13 07:11:42 PM PDT 24
Peak memory 206888 kb
Host smart-af1d410a-e0c0-4e1d-a261-f19e789cf912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33009
07718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3300907718
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3824929682
Short name T403
Test name
Test status
Simulation time 175446586 ps
CPU time 0.92 seconds
Started Jul 13 07:11:46 PM PDT 24
Finished Jul 13 07:11:47 PM PDT 24
Peak memory 206800 kb
Host smart-447e0152-4d9e-4bb3-98f8-48c11a9fa3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38249
29682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3824929682
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1712438616
Short name T1438
Test name
Test status
Simulation time 161613722 ps
CPU time 0.8 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:11:43 PM PDT 24
Peak memory 206892 kb
Host smart-5354f5c8-8a86-446b-80ff-ebf51a5c11d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
38616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1712438616
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.4150676530
Short name T1666
Test name
Test status
Simulation time 166822757 ps
CPU time 0.8 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:11:43 PM PDT 24
Peak memory 206748 kb
Host smart-a6ea8429-9842-46ca-bb9d-91fb5aa265a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41506
76530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.4150676530
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2730681913
Short name T1432
Test name
Test status
Simulation time 155687532 ps
CPU time 0.78 seconds
Started Jul 13 07:11:44 PM PDT 24
Finished Jul 13 07:11:45 PM PDT 24
Peak memory 206856 kb
Host smart-a3cdb895-f2c0-4822-817c-990443631b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27306
81913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2730681913
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1379878762
Short name T2365
Test name
Test status
Simulation time 242214743 ps
CPU time 0.9 seconds
Started Jul 13 07:11:43 PM PDT 24
Finished Jul 13 07:11:45 PM PDT 24
Peak memory 206848 kb
Host smart-d929423e-36a3-4186-82ee-e8730baf9b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
78762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1379878762
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2864081120
Short name T1500
Test name
Test status
Simulation time 3691401057 ps
CPU time 101.56 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:13:25 PM PDT 24
Peak memory 207068 kb
Host smart-452765e0-2cde-4a20-8222-aa17fdf1a5fa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2864081120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2864081120
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2708135055
Short name T893
Test name
Test status
Simulation time 180005642 ps
CPU time 0.82 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:11:44 PM PDT 24
Peak memory 206860 kb
Host smart-8dbb8f32-347f-4cb1-a5fd-64e6484d110e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27081
35055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2708135055
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.4199345233
Short name T1364
Test name
Test status
Simulation time 166791113 ps
CPU time 0.8 seconds
Started Jul 13 07:11:47 PM PDT 24
Finished Jul 13 07:11:48 PM PDT 24
Peak memory 206816 kb
Host smart-5524d73f-5cc7-48ff-bbaf-be7f6cc0d31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41993
45233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.4199345233
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3019152573
Short name T2501
Test name
Test status
Simulation time 402373239 ps
CPU time 1.27 seconds
Started Jul 13 07:11:45 PM PDT 24
Finished Jul 13 07:11:47 PM PDT 24
Peak memory 206868 kb
Host smart-7f3a2519-987d-49ca-a590-0931e58936a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30191
52573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3019152573
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.1481781254
Short name T590
Test name
Test status
Simulation time 4225202195 ps
CPU time 40.74 seconds
Started Jul 13 07:11:47 PM PDT 24
Finished Jul 13 07:12:28 PM PDT 24
Peak memory 207084 kb
Host smart-654bc8cf-3345-49a4-9fe5-199a7429d593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14817
81254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1481781254
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2116010543
Short name T2351
Test name
Test status
Simulation time 31759261 ps
CPU time 0.68 seconds
Started Jul 13 07:11:57 PM PDT 24
Finished Jul 13 07:11:58 PM PDT 24
Peak memory 207144 kb
Host smart-9024bec6-602e-49c3-8573-73503241abc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2116010543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2116010543
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3734826919
Short name T1988
Test name
Test status
Simulation time 3752597693 ps
CPU time 4.72 seconds
Started Jul 13 07:11:41 PM PDT 24
Finished Jul 13 07:11:47 PM PDT 24
Peak memory 207076 kb
Host smart-090293ac-f6df-4889-86fd-6693003ed5fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3734826919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3734826919
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.976437545
Short name T1544
Test name
Test status
Simulation time 13494772597 ps
CPU time 13.36 seconds
Started Jul 13 07:11:46 PM PDT 24
Finished Jul 13 07:12:00 PM PDT 24
Peak memory 207016 kb
Host smart-02c50c19-76fd-4dc2-9070-c69f76f5fb63
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=976437545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.976437545
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2724000752
Short name T1223
Test name
Test status
Simulation time 23386895268 ps
CPU time 22.51 seconds
Started Jul 13 07:11:46 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 207084 kb
Host smart-e8a47a80-4bd7-418f-88b3-c88219db60a9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2724000752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2724000752
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.107824282
Short name T752
Test name
Test status
Simulation time 167703680 ps
CPU time 0.81 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:11:44 PM PDT 24
Peak memory 206864 kb
Host smart-aad89698-4cc5-488f-b382-5efab1c2017c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10782
4282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.107824282
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1879510162
Short name T2355
Test name
Test status
Simulation time 147470599 ps
CPU time 0.82 seconds
Started Jul 13 07:11:46 PM PDT 24
Finished Jul 13 07:11:47 PM PDT 24
Peak memory 206812 kb
Host smart-3de08390-2cc5-4971-bd6a-04087056664d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18795
10162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1879510162
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2255218050
Short name T463
Test name
Test status
Simulation time 270321323 ps
CPU time 1.07 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:11:43 PM PDT 24
Peak memory 206880 kb
Host smart-c2873608-7b57-4f28-bee6-b14538ada2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22552
18050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2255218050
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2929961334
Short name T2629
Test name
Test status
Simulation time 513653380 ps
CPU time 1.33 seconds
Started Jul 13 07:11:44 PM PDT 24
Finished Jul 13 07:11:46 PM PDT 24
Peak memory 206852 kb
Host smart-a7ca09f9-1506-4425-a981-46e9202e4293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29299
61334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2929961334
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.2602423279
Short name T1035
Test name
Test status
Simulation time 11809364453 ps
CPU time 26.63 seconds
Started Jul 13 07:11:44 PM PDT 24
Finished Jul 13 07:12:11 PM PDT 24
Peak memory 207076 kb
Host smart-a70051e9-c1c7-45f8-875b-04669ccf73ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26024
23279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.2602423279
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3985189912
Short name T2158
Test name
Test status
Simulation time 441638465 ps
CPU time 1.43 seconds
Started Jul 13 07:11:43 PM PDT 24
Finished Jul 13 07:11:45 PM PDT 24
Peak memory 206872 kb
Host smart-a1d06eb7-6099-4490-86df-2c8eb0d706b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39851
89912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3985189912
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.4292104911
Short name T1228
Test name
Test status
Simulation time 138090177 ps
CPU time 0.77 seconds
Started Jul 13 07:11:43 PM PDT 24
Finished Jul 13 07:11:45 PM PDT 24
Peak memory 206868 kb
Host smart-e6a0ec48-a1e8-4f25-80c8-28068ea428b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42921
04911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.4292104911
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2983397292
Short name T1306
Test name
Test status
Simulation time 48904603 ps
CPU time 0.68 seconds
Started Jul 13 07:11:45 PM PDT 24
Finished Jul 13 07:11:47 PM PDT 24
Peak memory 206864 kb
Host smart-33768744-d2b3-46ab-94ba-986584dd6be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29833
97292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2983397292
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3891605855
Short name T1383
Test name
Test status
Simulation time 845526816 ps
CPU time 1.99 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:11:45 PM PDT 24
Peak memory 207016 kb
Host smart-7e19a1a4-ebf1-444f-9a65-ac0054fdd826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38916
05855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3891605855
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2976085498
Short name T1890
Test name
Test status
Simulation time 374759881 ps
CPU time 2.37 seconds
Started Jul 13 07:11:42 PM PDT 24
Finished Jul 13 07:11:45 PM PDT 24
Peak memory 207092 kb
Host smart-dcb97756-8c04-4d22-96b1-45ec541fb402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760
85498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2976085498
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.119814770
Short name T1178
Test name
Test status
Simulation time 209728752 ps
CPU time 0.86 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:11:53 PM PDT 24
Peak memory 206872 kb
Host smart-7e5bc3a4-a5c9-4366-9351-025a4a1cde3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11981
4770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.119814770
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2156152314
Short name T1248
Test name
Test status
Simulation time 140867474 ps
CPU time 0.76 seconds
Started Jul 13 07:12:01 PM PDT 24
Finished Jul 13 07:12:02 PM PDT 24
Peak memory 206812 kb
Host smart-e512e19f-c53d-4ecf-8dd7-e95dadeb5776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
52314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2156152314
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2398889265
Short name T2175
Test name
Test status
Simulation time 254771238 ps
CPU time 0.97 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:11:54 PM PDT 24
Peak memory 206896 kb
Host smart-0e90a7d2-e6ce-47fc-b53c-e77e69b6c52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23988
89265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2398889265
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.1136296499
Short name T1732
Test name
Test status
Simulation time 7248231677 ps
CPU time 57.33 seconds
Started Jul 13 07:11:50 PM PDT 24
Finished Jul 13 07:12:47 PM PDT 24
Peak memory 207148 kb
Host smart-c239ca5f-0247-4af2-bfba-5e542a3a00cc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1136296499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1136296499
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.2079254546
Short name T1103
Test name
Test status
Simulation time 10735927947 ps
CPU time 91.32 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:13:23 PM PDT 24
Peak memory 207052 kb
Host smart-d74ddd69-3c1e-4589-98ae-a02d5aedf0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20792
54546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.2079254546
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.475603956
Short name T801
Test name
Test status
Simulation time 210222227 ps
CPU time 0.86 seconds
Started Jul 13 07:11:53 PM PDT 24
Finished Jul 13 07:11:55 PM PDT 24
Peak memory 207048 kb
Host smart-ff79c8f8-b2ae-427f-8db1-5109bbfcb8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47560
3956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.475603956
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2956622588
Short name T1139
Test name
Test status
Simulation time 23353786039 ps
CPU time 22.85 seconds
Started Jul 13 07:11:50 PM PDT 24
Finished Jul 13 07:12:14 PM PDT 24
Peak memory 206936 kb
Host smart-84ecf893-92cf-42ae-8c29-4d9b7926b341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29566
22588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2956622588
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1828460185
Short name T1558
Test name
Test status
Simulation time 3279454185 ps
CPU time 4.17 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:11:56 PM PDT 24
Peak memory 206940 kb
Host smart-15162254-3790-4130-ba9f-6537291e94ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
60185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1828460185
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.2135842984
Short name T1696
Test name
Test status
Simulation time 12237355824 ps
CPU time 347.06 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:17:40 PM PDT 24
Peak memory 207128 kb
Host smart-20400732-d233-4e6b-8bb9-8cb5f689921c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21358
42984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2135842984
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.4250473824
Short name T2024
Test name
Test status
Simulation time 7611915109 ps
CPU time 212.16 seconds
Started Jul 13 07:11:53 PM PDT 24
Finished Jul 13 07:15:26 PM PDT 24
Peak memory 207240 kb
Host smart-b7ac4f64-0d2a-44bb-8b44-5cef345ec3f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4250473824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.4250473824
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2013454157
Short name T892
Test name
Test status
Simulation time 312374512 ps
CPU time 0.96 seconds
Started Jul 13 07:11:50 PM PDT 24
Finished Jul 13 07:11:52 PM PDT 24
Peak memory 206884 kb
Host smart-2f674ba9-6ecc-4f35-bd99-16111edcc1ab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2013454157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2013454157
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4026967652
Short name T1660
Test name
Test status
Simulation time 200823913 ps
CPU time 0.97 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:11:53 PM PDT 24
Peak memory 206868 kb
Host smart-0226ff97-6a30-496d-8f9d-626c82b95c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40269
67652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4026967652
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3443273957
Short name T2001
Test name
Test status
Simulation time 5875718712 ps
CPU time 56.8 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:12:50 PM PDT 24
Peak memory 207140 kb
Host smart-98c36bd2-7ca3-4cad-9c03-9bbe03499761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34432
73957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3443273957
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2775084215
Short name T1021
Test name
Test status
Simulation time 2727294239 ps
CPU time 25.41 seconds
Started Jul 13 07:11:50 PM PDT 24
Finished Jul 13 07:12:17 PM PDT 24
Peak memory 207092 kb
Host smart-c95a03a7-f37a-458b-aacf-1b3bfcd66613
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2775084215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2775084215
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.335546060
Short name T566
Test name
Test status
Simulation time 170516849 ps
CPU time 0.89 seconds
Started Jul 13 07:11:50 PM PDT 24
Finished Jul 13 07:11:51 PM PDT 24
Peak memory 206868 kb
Host smart-2ddd11cd-83cc-4de9-9c2b-ead8c58ab608
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=335546060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.335546060
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2813279492
Short name T307
Test name
Test status
Simulation time 141420802 ps
CPU time 0.79 seconds
Started Jul 13 07:11:50 PM PDT 24
Finished Jul 13 07:11:51 PM PDT 24
Peak memory 206868 kb
Host smart-3ed9abe8-6504-4066-96bc-8d4cb11f1758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28132
79492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2813279492
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1092941916
Short name T135
Test name
Test status
Simulation time 239665245 ps
CPU time 0.89 seconds
Started Jul 13 07:11:53 PM PDT 24
Finished Jul 13 07:11:55 PM PDT 24
Peak memory 206864 kb
Host smart-7d271360-05f1-4ae7-aede-e2538bef7102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929
41916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1092941916
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2809060582
Short name T2162
Test name
Test status
Simulation time 184502977 ps
CPU time 0.83 seconds
Started Jul 13 07:11:54 PM PDT 24
Finished Jul 13 07:11:55 PM PDT 24
Peak memory 206868 kb
Host smart-25051089-e31e-4bd4-973e-de79f76372d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28090
60582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2809060582
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3279526490
Short name T1143
Test name
Test status
Simulation time 153122351 ps
CPU time 0.8 seconds
Started Jul 13 07:11:50 PM PDT 24
Finished Jul 13 07:11:52 PM PDT 24
Peak memory 206864 kb
Host smart-3ea0899e-cceb-4967-a336-be7249c7a2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32795
26490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3279526490
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1787783384
Short name T211
Test name
Test status
Simulation time 213329043 ps
CPU time 0.96 seconds
Started Jul 13 07:11:54 PM PDT 24
Finished Jul 13 07:11:56 PM PDT 24
Peak memory 206872 kb
Host smart-7f2c3cb1-f782-4d42-8560-760ed070e02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17877
83384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1787783384
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.643682047
Short name T2418
Test name
Test status
Simulation time 157480704 ps
CPU time 0.83 seconds
Started Jul 13 07:12:00 PM PDT 24
Finished Jul 13 07:12:01 PM PDT 24
Peak memory 206820 kb
Host smart-d883715b-3cb0-42cd-b1f9-0e72e9192b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64368
2047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.643682047
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2410699807
Short name T1835
Test name
Test status
Simulation time 226242998 ps
CPU time 0.92 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:11:54 PM PDT 24
Peak memory 206844 kb
Host smart-3b33a3bf-a231-40e7-8d19-2b627c6e4f2e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2410699807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2410699807
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3735373171
Short name T1554
Test name
Test status
Simulation time 148711704 ps
CPU time 0.76 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:11:53 PM PDT 24
Peak memory 206876 kb
Host smart-5ad39d98-b1c5-43cc-b6ce-9a9fb96d68b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37353
73171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3735373171
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3792103599
Short name T1909
Test name
Test status
Simulation time 38951724 ps
CPU time 0.68 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:11:53 PM PDT 24
Peak memory 206860 kb
Host smart-a1046d9a-d700-4291-ad1d-2fa3640504b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37921
03599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3792103599
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3561619000
Short name T225
Test name
Test status
Simulation time 16458370215 ps
CPU time 39.09 seconds
Started Jul 13 07:11:59 PM PDT 24
Finished Jul 13 07:12:39 PM PDT 24
Peak memory 215252 kb
Host smart-f61f8c1c-737d-4b18-b58d-e975c3430506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35616
19000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3561619000
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4210092254
Short name T1171
Test name
Test status
Simulation time 171339784 ps
CPU time 0.79 seconds
Started Jul 13 07:11:55 PM PDT 24
Finished Jul 13 07:11:56 PM PDT 24
Peak memory 206748 kb
Host smart-cfcb9032-2456-4e5a-9eff-8e20d7e26fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42100
92254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4210092254
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2624272427
Short name T2599
Test name
Test status
Simulation time 220491601 ps
CPU time 0.86 seconds
Started Jul 13 07:11:55 PM PDT 24
Finished Jul 13 07:11:56 PM PDT 24
Peak memory 206820 kb
Host smart-0bc6eae4-2483-4e2a-9b19-8a8334c32916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26242
72427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2624272427
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3099553510
Short name T1560
Test name
Test status
Simulation time 266641897 ps
CPU time 0.97 seconds
Started Jul 13 07:11:54 PM PDT 24
Finished Jul 13 07:11:56 PM PDT 24
Peak memory 206868 kb
Host smart-daa93919-34ff-4792-8f74-9a7bcf852989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30995
53510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3099553510
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1757750326
Short name T1279
Test name
Test status
Simulation time 210816512 ps
CPU time 0.89 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:11:52 PM PDT 24
Peak memory 206872 kb
Host smart-64f18ff7-c2ee-43ab-acdf-6d1f4522dda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17577
50326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1757750326
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1979419689
Short name T826
Test name
Test status
Simulation time 162277370 ps
CPU time 0.85 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:11:53 PM PDT 24
Peak memory 206864 kb
Host smart-2ef7cd83-4954-463c-b269-68ba8c119717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
19689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1979419689
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3969026849
Short name T197
Test name
Test status
Simulation time 180063195 ps
CPU time 0.79 seconds
Started Jul 13 07:11:51 PM PDT 24
Finished Jul 13 07:11:53 PM PDT 24
Peak memory 206864 kb
Host smart-a8b50e31-af08-4330-814a-c8440dea7c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39690
26849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3969026849
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3085559848
Short name T2477
Test name
Test status
Simulation time 165497929 ps
CPU time 0.83 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:11:54 PM PDT 24
Peak memory 206892 kb
Host smart-d16cc744-859d-4ba1-affd-cb30f21517b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30855
59848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3085559848
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2887995675
Short name T2440
Test name
Test status
Simulation time 252406425 ps
CPU time 0.99 seconds
Started Jul 13 07:11:53 PM PDT 24
Finished Jul 13 07:11:55 PM PDT 24
Peak memory 206804 kb
Host smart-10f5caf3-e62e-4067-a8cf-27720705a005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28879
95675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2887995675
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.4218654937
Short name T2017
Test name
Test status
Simulation time 6550856550 ps
CPU time 66.22 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:13:00 PM PDT 24
Peak memory 207108 kb
Host smart-066527d6-fb6e-4e0a-8b44-ee57e982251e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4218654937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.4218654937
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2289411369
Short name T2554
Test name
Test status
Simulation time 168761848 ps
CPU time 0.82 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:11:54 PM PDT 24
Peak memory 206568 kb
Host smart-46ef6b13-618b-4240-9403-37703a564b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22894
11369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2289411369
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.686255455
Short name T1987
Test name
Test status
Simulation time 174580486 ps
CPU time 0.87 seconds
Started Jul 13 07:11:54 PM PDT 24
Finished Jul 13 07:11:55 PM PDT 24
Peak memory 207100 kb
Host smart-c2d45e13-1303-4a86-b8f2-85de9b7256ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68625
5455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.686255455
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.4120326609
Short name T1537
Test name
Test status
Simulation time 1326416561 ps
CPU time 2.73 seconds
Started Jul 13 07:11:50 PM PDT 24
Finished Jul 13 07:11:53 PM PDT 24
Peak memory 207076 kb
Host smart-14a227d1-2887-4897-a776-daab840684fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41203
26609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.4120326609
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.477940717
Short name T156
Test name
Test status
Simulation time 7407675232 ps
CPU time 71.81 seconds
Started Jul 13 07:12:00 PM PDT 24
Finished Jul 13 07:13:12 PM PDT 24
Peak memory 207076 kb
Host smart-8ff0a8b3-4872-4a63-b91f-71dcdfb8569f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47794
0717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.477940717
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.774119439
Short name T1834
Test name
Test status
Simulation time 47495003 ps
CPU time 0.64 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:07 PM PDT 24
Peak memory 206872 kb
Host smart-24dc4e59-a76c-420a-bfe9-cae040b14447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=774119439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.774119439
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1605536658
Short name T1771
Test name
Test status
Simulation time 3698260018 ps
CPU time 4.43 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:11:57 PM PDT 24
Peak memory 206688 kb
Host smart-6a519f5f-ffca-4606-9e00-f9e4fd56c35c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1605536658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1605536658
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2326732291
Short name T2700
Test name
Test status
Simulation time 13337450214 ps
CPU time 13.05 seconds
Started Jul 13 07:11:52 PM PDT 24
Finished Jul 13 07:12:07 PM PDT 24
Peak memory 206872 kb
Host smart-42cad848-fcd5-41c4-9b6b-7e1b64b0e2f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2326732291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2326732291
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2634119905
Short name T1461
Test name
Test status
Simulation time 23397423096 ps
CPU time 21.54 seconds
Started Jul 13 07:12:08 PM PDT 24
Finished Jul 13 07:12:31 PM PDT 24
Peak memory 207140 kb
Host smart-f7929e11-766b-473b-b205-ab6c7afc03e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2634119905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.2634119905
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2618598468
Short name T1409
Test name
Test status
Simulation time 153321186 ps
CPU time 0.88 seconds
Started Jul 13 07:12:01 PM PDT 24
Finished Jul 13 07:12:03 PM PDT 24
Peak memory 206864 kb
Host smart-fd36cd0c-dcfd-4828-abce-90e296881d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26185
98468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2618598468
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1061815657
Short name T1395
Test name
Test status
Simulation time 142113267 ps
CPU time 0.76 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:08 PM PDT 24
Peak memory 206868 kb
Host smart-11ffc0be-4243-46c4-a494-bb9a64646fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618
15657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1061815657
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.559678678
Short name T2566
Test name
Test status
Simulation time 360917022 ps
CPU time 1.15 seconds
Started Jul 13 07:12:07 PM PDT 24
Finished Jul 13 07:12:10 PM PDT 24
Peak memory 206872 kb
Host smart-c6120221-bd1f-4a61-9fa7-e3d7efd48fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55967
8678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.559678678
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2383773698
Short name T59
Test name
Test status
Simulation time 1274056994 ps
CPU time 3.15 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:12:08 PM PDT 24
Peak memory 207052 kb
Host smart-447a95bc-7108-4fe8-8181-6dcfab09ed48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23837
73698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2383773698
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3654228437
Short name T848
Test name
Test status
Simulation time 19212957806 ps
CPU time 40.41 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:47 PM PDT 24
Peak memory 207132 kb
Host smart-bd558e47-3b2d-495a-a3b4-d3bcab282699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36542
28437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3654228437
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.1077160991
Short name T319
Test name
Test status
Simulation time 330024994 ps
CPU time 1.18 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:08 PM PDT 24
Peak memory 206892 kb
Host smart-c4c2b712-b68f-4377-9a39-3198461db07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10771
60991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1077160991
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.983341166
Short name T1924
Test name
Test status
Simulation time 142076209 ps
CPU time 0.84 seconds
Started Jul 13 07:12:09 PM PDT 24
Finished Jul 13 07:12:11 PM PDT 24
Peak memory 206816 kb
Host smart-397cd882-d8b8-45bb-b96b-85e84f5af1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98334
1166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.983341166
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.4065007482
Short name T1375
Test name
Test status
Simulation time 49439588 ps
CPU time 0.66 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:07 PM PDT 24
Peak memory 206748 kb
Host smart-82e1d565-dec4-4b02-aef5-f7c9853338d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40650
07482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.4065007482
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1662602826
Short name T435
Test name
Test status
Simulation time 723326904 ps
CPU time 1.84 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:08 PM PDT 24
Peak memory 207072 kb
Host smart-37236b8d-db71-4241-841e-c2131c36cc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16626
02826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1662602826
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2608810277
Short name T2204
Test name
Test status
Simulation time 197440780 ps
CPU time 2.27 seconds
Started Jul 13 07:12:02 PM PDT 24
Finished Jul 13 07:12:05 PM PDT 24
Peak memory 207024 kb
Host smart-23fb7bb6-0d3c-4476-82b6-0667226eba90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26088
10277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2608810277
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3921313772
Short name T1920
Test name
Test status
Simulation time 152748897 ps
CPU time 0.8 seconds
Started Jul 13 07:12:03 PM PDT 24
Finished Jul 13 07:12:04 PM PDT 24
Peak memory 206876 kb
Host smart-9e26c633-ee61-4518-a8ad-0dd5c58b14ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39213
13772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3921313772
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3186929976
Short name T2641
Test name
Test status
Simulation time 144257701 ps
CPU time 0.79 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:12:05 PM PDT 24
Peak memory 206860 kb
Host smart-68ae94dc-1e98-4778-8f58-e451ac9646c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31869
29976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3186929976
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3753277329
Short name T1534
Test name
Test status
Simulation time 256385603 ps
CPU time 0.98 seconds
Started Jul 13 07:12:06 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206864 kb
Host smart-16ff7594-e77e-4799-923e-ae27570dc8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37532
77329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3753277329
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.4075192577
Short name T2542
Test name
Test status
Simulation time 8288282397 ps
CPU time 77.21 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:13:23 PM PDT 24
Peak memory 207108 kb
Host smart-dc7e7e4c-af67-4775-ac56-99d231a31cd6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4075192577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.4075192577
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.4164629010
Short name T2616
Test name
Test status
Simulation time 7469851455 ps
CPU time 59.46 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 207140 kb
Host smart-ae367082-a5a6-4504-ac37-97d0a8a6ccdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41646
29010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.4164629010
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.244925285
Short name T1769
Test name
Test status
Simulation time 216997968 ps
CPU time 0.85 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:12:06 PM PDT 24
Peak memory 206872 kb
Host smart-30165ebf-169a-487c-8568-5b2b1dafd36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24492
5285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.244925285
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.236854477
Short name T315
Test name
Test status
Simulation time 23309703952 ps
CPU time 22.41 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 206864 kb
Host smart-145c20b6-5575-4c42-88b0-d64732c0156c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23685
4477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.236854477
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2336630223
Short name T1976
Test name
Test status
Simulation time 3307059960 ps
CPU time 3.87 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:10 PM PDT 24
Peak memory 206928 kb
Host smart-17eb439e-31e1-4e67-af3d-94ef16f01319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23366
30223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2336630223
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1516371197
Short name T1354
Test name
Test status
Simulation time 7829716397 ps
CPU time 55.74 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:13:03 PM PDT 24
Peak memory 207136 kb
Host smart-d4b55c08-16c3-4305-8988-2fc0d6489096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15163
71197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1516371197
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2145479530
Short name T2207
Test name
Test status
Simulation time 4912509136 ps
CPU time 46.94 seconds
Started Jul 13 07:12:06 PM PDT 24
Finished Jul 13 07:12:55 PM PDT 24
Peak memory 206788 kb
Host smart-cc12fe6c-6695-4ee0-82c5-0cb386bfa0b6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2145479530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2145479530
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2281657673
Short name T2228
Test name
Test status
Simulation time 279631777 ps
CPU time 0.97 seconds
Started Jul 13 07:12:07 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206880 kb
Host smart-2fca8cb9-1e66-4242-96cc-d532bf710320
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2281657673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2281657673
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2094637656
Short name T2372
Test name
Test status
Simulation time 196179050 ps
CPU time 0.89 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:12:06 PM PDT 24
Peak memory 206868 kb
Host smart-25db77cf-f72c-4a89-9cb6-845d5c5d3bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
37656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2094637656
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.319605602
Short name T2607
Test name
Test status
Simulation time 4111270311 ps
CPU time 29.07 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 207012 kb
Host smart-387e060c-adbb-42d3-bbaf-85401775954e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31960
5602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.319605602
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3584959689
Short name T1871
Test name
Test status
Simulation time 5638081596 ps
CPU time 44.65 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:52 PM PDT 24
Peak memory 207076 kb
Host smart-13dd08bd-6b59-4815-8858-81bfbc15088a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3584959689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3584959689
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.474564078
Short name T1023
Test name
Test status
Simulation time 191288094 ps
CPU time 0.85 seconds
Started Jul 13 07:12:06 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206868 kb
Host smart-3ddeef7e-56ad-4f78-ae80-2405da1b2a9a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=474564078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.474564078
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3811704011
Short name T1109
Test name
Test status
Simulation time 159155956 ps
CPU time 0.78 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:07 PM PDT 24
Peak memory 206808 kb
Host smart-62a74457-3079-4755-9770-b7abaefc2a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38117
04011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3811704011
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3540129649
Short name T1076
Test name
Test status
Simulation time 171306243 ps
CPU time 0.8 seconds
Started Jul 13 07:12:07 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206876 kb
Host smart-80023aa9-912c-4463-ad97-f594032b83ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35401
29649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3540129649
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1015585207
Short name T2092
Test name
Test status
Simulation time 182459102 ps
CPU time 0.85 seconds
Started Jul 13 07:12:07 PM PDT 24
Finished Jul 13 07:12:10 PM PDT 24
Peak memory 206856 kb
Host smart-cef0c50d-9810-496e-9f5b-6a772a828176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10155
85207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1015585207
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.520954423
Short name T2289
Test name
Test status
Simulation time 221975540 ps
CPU time 0.83 seconds
Started Jul 13 07:12:07 PM PDT 24
Finished Jul 13 07:12:10 PM PDT 24
Peak memory 206900 kb
Host smart-5447eb42-2eb5-4515-9f56-46f1c7b34e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52095
4423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.520954423
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1870823639
Short name T1067
Test name
Test status
Simulation time 155425877 ps
CPU time 0.78 seconds
Started Jul 13 07:12:07 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206900 kb
Host smart-2c671c9d-92e5-45b3-9846-86c6da735b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708
23639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1870823639
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2232841633
Short name T1141
Test name
Test status
Simulation time 264583601 ps
CPU time 0.97 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:08 PM PDT 24
Peak memory 206876 kb
Host smart-fde3cb55-d149-45be-939c-e9f24484e247
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2232841633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2232841633
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2623982551
Short name T2478
Test name
Test status
Simulation time 157866005 ps
CPU time 0.84 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:08 PM PDT 24
Peak memory 206892 kb
Host smart-ced2605e-d02f-4212-bdcf-a1d858f13abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26239
82551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2623982551
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1637639503
Short name T2152
Test name
Test status
Simulation time 39463188 ps
CPU time 0.69 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:12:05 PM PDT 24
Peak memory 206852 kb
Host smart-867a70c2-e757-4bf3-8a47-2e889ef79759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16376
39503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1637639503
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1903700083
Short name T2097
Test name
Test status
Simulation time 12749476689 ps
CPU time 27.62 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:34 PM PDT 24
Peak memory 207156 kb
Host smart-657c1c7d-ede2-41b9-a0ae-df5f328f447b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19037
00083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1903700083
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2592823998
Short name T768
Test name
Test status
Simulation time 199282932 ps
CPU time 0.9 seconds
Started Jul 13 07:12:06 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206868 kb
Host smart-7a806c61-0bab-4d0b-a788-eba289a4a8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
23998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2592823998
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3487776767
Short name T595
Test name
Test status
Simulation time 171585736 ps
CPU time 0.83 seconds
Started Jul 13 07:12:03 PM PDT 24
Finished Jul 13 07:12:04 PM PDT 24
Peak memory 206832 kb
Host smart-098ecd77-b8b2-4b81-b624-2b68e5500dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
76767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3487776767
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.341937347
Short name T2011
Test name
Test status
Simulation time 245345396 ps
CPU time 0.97 seconds
Started Jul 13 07:12:02 PM PDT 24
Finished Jul 13 07:12:04 PM PDT 24
Peak memory 206884 kb
Host smart-fa7ff999-d111-4277-9506-29998196a175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34193
7347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.341937347
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2641362912
Short name T2448
Test name
Test status
Simulation time 191566064 ps
CPU time 0.86 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:08 PM PDT 24
Peak memory 206848 kb
Host smart-32477b47-1c38-4821-9130-295fc83ba936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
62912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2641362912
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3923387129
Short name T2493
Test name
Test status
Simulation time 139910652 ps
CPU time 0.77 seconds
Started Jul 13 07:12:03 PM PDT 24
Finished Jul 13 07:12:04 PM PDT 24
Peak memory 206872 kb
Host smart-f032ae50-88ae-440d-b614-6ce006bc0e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39233
87129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3923387129
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2985308392
Short name T1766
Test name
Test status
Simulation time 163458207 ps
CPU time 0.76 seconds
Started Jul 13 07:12:06 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206892 kb
Host smart-8be2b8af-e06e-4abc-b340-5679f7443474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29853
08392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2985308392
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2937217944
Short name T2037
Test name
Test status
Simulation time 153857959 ps
CPU time 0.82 seconds
Started Jul 13 07:12:08 PM PDT 24
Finished Jul 13 07:12:11 PM PDT 24
Peak memory 206868 kb
Host smart-75ab7787-9f80-4780-ae4c-220f8b9fa825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29372
17944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2937217944
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3730286996
Short name T47
Test name
Test status
Simulation time 217222522 ps
CPU time 0.96 seconds
Started Jul 13 07:12:06 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206560 kb
Host smart-4f963850-b024-4bf8-a54f-53610c446bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37302
86996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3730286996
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.864834848
Short name T1426
Test name
Test status
Simulation time 5007001430 ps
CPU time 131.65 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:14:18 PM PDT 24
Peak memory 207012 kb
Host smart-393f5302-d9c9-4976-a51e-dc36b1db3514
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=864834848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.864834848
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1040083864
Short name T729
Test name
Test status
Simulation time 165556971 ps
CPU time 0.85 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:07 PM PDT 24
Peak memory 207052 kb
Host smart-bed793aa-4458-4be6-a09a-857e8f220938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10400
83864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1040083864
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.559729519
Short name T458
Test name
Test status
Simulation time 194745612 ps
CPU time 0.89 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:08 PM PDT 24
Peak memory 206868 kb
Host smart-d1bd2629-2a5d-49a2-a1b3-6656e79dd99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55972
9519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.559729519
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3190582947
Short name T1968
Test name
Test status
Simulation time 316438853 ps
CPU time 1.07 seconds
Started Jul 13 07:12:08 PM PDT 24
Finished Jul 13 07:12:10 PM PDT 24
Peak memory 206868 kb
Host smart-5d56c902-610f-448e-8c5f-c39e5d2cb70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31905
82947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3190582947
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3713717235
Short name T2
Test name
Test status
Simulation time 5408784394 ps
CPU time 38.42 seconds
Started Jul 13 07:12:05 PM PDT 24
Finished Jul 13 07:12:45 PM PDT 24
Peak memory 207072 kb
Host smart-e72e271a-fcd4-49a7-a9f5-07637d79660c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37137
17235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3713717235
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3980684586
Short name T830
Test name
Test status
Simulation time 42591687 ps
CPU time 0.67 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206884 kb
Host smart-2bec0e4b-f0ab-4c0d-b8d5-13a0f29ee3e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3980684586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3980684586
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1219552280
Short name T2688
Test name
Test status
Simulation time 4277824506 ps
CPU time 4.54 seconds
Started Jul 13 07:12:08 PM PDT 24
Finished Jul 13 07:12:14 PM PDT 24
Peak memory 207292 kb
Host smart-78ddaae4-7688-4fde-bcfc-175790498713
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1219552280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1219552280
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1935512702
Short name T8
Test name
Test status
Simulation time 13354453462 ps
CPU time 12.21 seconds
Started Jul 13 07:12:03 PM PDT 24
Finished Jul 13 07:12:15 PM PDT 24
Peak memory 207132 kb
Host smart-345a3508-d57a-4627-afda-53365551704f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1935512702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1935512702
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3816128323
Short name T501
Test name
Test status
Simulation time 23373504884 ps
CPU time 24.06 seconds
Started Jul 13 07:12:04 PM PDT 24
Finished Jul 13 07:12:28 PM PDT 24
Peak memory 206960 kb
Host smart-aad88f40-82f5-456a-a6cf-773dee3fcb5e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3816128323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3816128323
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1320137976
Short name T927
Test name
Test status
Simulation time 198981505 ps
CPU time 0.89 seconds
Started Jul 13 07:12:09 PM PDT 24
Finished Jul 13 07:12:11 PM PDT 24
Peak memory 206868 kb
Host smart-1377abeb-b4a4-4a81-bb39-facf6c5cb722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13201
37976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1320137976
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3057814352
Short name T596
Test name
Test status
Simulation time 156587071 ps
CPU time 0.79 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:16 PM PDT 24
Peak memory 206868 kb
Host smart-43350e39-ac4a-42b3-be81-2042b5915588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30578
14352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3057814352
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1630611687
Short name T805
Test name
Test status
Simulation time 318533003 ps
CPU time 1.1 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:12:19 PM PDT 24
Peak memory 206884 kb
Host smart-ac77ae0f-82bd-48ac-9262-60f39f2bd55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16306
11687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1630611687
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.2761642428
Short name T937
Test name
Test status
Simulation time 1450261610 ps
CPU time 3.01 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:22 PM PDT 24
Peak memory 207012 kb
Host smart-46458c91-8675-4f16-96b3-c8d0726aa13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27616
42428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2761642428
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.595999807
Short name T152
Test name
Test status
Simulation time 13794781285 ps
CPU time 24.32 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:12:42 PM PDT 24
Peak memory 207136 kb
Host smart-1a6ec1f0-b999-4fc6-9348-ef892ade455d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59599
9807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.595999807
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3163495448
Short name T2350
Test name
Test status
Simulation time 499111248 ps
CPU time 1.4 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:20 PM PDT 24
Peak memory 206852 kb
Host smart-a78319e6-904f-4492-acfc-c1be5548b452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31634
95448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3163495448
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3127573768
Short name T1704
Test name
Test status
Simulation time 179956488 ps
CPU time 0.79 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:17 PM PDT 24
Peak memory 206856 kb
Host smart-862fd6c4-b534-4548-9ec7-a771cbdbd1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31275
73768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3127573768
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3363365557
Short name T1550
Test name
Test status
Simulation time 38176723 ps
CPU time 0.66 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:12:18 PM PDT 24
Peak memory 206860 kb
Host smart-67a7e685-cb00-4ebe-a6ad-e0afc5e7b19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
65557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3363365557
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.333221035
Short name T1307
Test name
Test status
Simulation time 925268574 ps
CPU time 2.19 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:17 PM PDT 24
Peak memory 207004 kb
Host smart-ea113d78-d16c-4e77-8077-f215a025428b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33322
1035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.333221035
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3526922992
Short name T423
Test name
Test status
Simulation time 310287934 ps
CPU time 2.16 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:19 PM PDT 24
Peak memory 207024 kb
Host smart-37aa9df3-77e7-45ed-afbd-15eb41c4c634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35269
22992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3526922992
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.4254551451
Short name T2747
Test name
Test status
Simulation time 242200616 ps
CPU time 0.96 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:20 PM PDT 24
Peak memory 206864 kb
Host smart-49646dd9-05d0-4a73-bef3-675f646ade02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42545
51451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.4254551451
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.52950269
Short name T989
Test name
Test status
Simulation time 146502885 ps
CPU time 0.78 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:17 PM PDT 24
Peak memory 206880 kb
Host smart-7d5ac6b2-7d46-4ee9-bf71-e5fdf07b1ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52950
269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.52950269
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1627080861
Short name T1802
Test name
Test status
Simulation time 238055268 ps
CPU time 0.88 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:16 PM PDT 24
Peak memory 206864 kb
Host smart-b47805fd-03fb-43c9-814f-cca11ed6f9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16270
80861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1627080861
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.2349212507
Short name T1651
Test name
Test status
Simulation time 13509711168 ps
CPU time 53.09 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:13:11 PM PDT 24
Peak memory 207140 kb
Host smart-99ee5cbb-d617-45fe-be5c-38d15721bbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23492
12507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.2349212507
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2088939849
Short name T510
Test name
Test status
Simulation time 270931666 ps
CPU time 0.94 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:18 PM PDT 24
Peak memory 206864 kb
Host smart-0daa120c-ef4f-4eb9-a7a8-1396ec9c4a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20889
39849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2088939849
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1603410673
Short name T2174
Test name
Test status
Simulation time 23336793951 ps
CPU time 22.05 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:39 PM PDT 24
Peak memory 206936 kb
Host smart-97b61776-36ae-4107-8617-10ccf3cc5b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16034
10673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1603410673
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.522095701
Short name T642
Test name
Test status
Simulation time 3287656892 ps
CPU time 3.8 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:24 PM PDT 24
Peak memory 206932 kb
Host smart-67c9bfe6-2fe1-4f47-a4ae-264e0e2e584f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52209
5701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.522095701
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.4150330975
Short name T1939
Test name
Test status
Simulation time 9669893992 ps
CPU time 72.33 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:13:29 PM PDT 24
Peak memory 207156 kb
Host smart-1547c456-bfeb-4c0b-bd57-168dbf5b3f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41503
30975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.4150330975
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.2628429078
Short name T821
Test name
Test status
Simulation time 5268873480 ps
CPU time 152.16 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 207096 kb
Host smart-3305993b-c50e-493f-9dad-22f8a92c8571
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2628429078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.2628429078
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1616280341
Short name T673
Test name
Test status
Simulation time 236675260 ps
CPU time 0.98 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:20 PM PDT 24
Peak memory 206860 kb
Host smart-f8fa218d-d832-4a3f-889f-6013305543aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1616280341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1616280341
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1684843664
Short name T696
Test name
Test status
Simulation time 197134463 ps
CPU time 0.91 seconds
Started Jul 13 07:12:13 PM PDT 24
Finished Jul 13 07:12:15 PM PDT 24
Peak memory 206856 kb
Host smart-92b9cc0a-81fd-45a1-ad28-29786d69730d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16848
43664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1684843664
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2532988724
Short name T1287
Test name
Test status
Simulation time 4515789461 ps
CPU time 32.39 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:52 PM PDT 24
Peak memory 207128 kb
Host smart-632ce81a-52d4-4aec-9fe7-a7750a371aa6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2532988724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2532988724
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3779954851
Short name T499
Test name
Test status
Simulation time 165858636 ps
CPU time 0.85 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:20 PM PDT 24
Peak memory 206884 kb
Host smart-1830d93f-30cf-4290-b82c-1f5a714b54ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3779954851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3779954851
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3786861617
Short name T1336
Test name
Test status
Simulation time 136232764 ps
CPU time 0.85 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206868 kb
Host smart-b4e1f258-9a5a-4f2e-81fc-9b69b5723e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37868
61617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3786861617
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3655888497
Short name T585
Test name
Test status
Simulation time 184211798 ps
CPU time 0.84 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:17 PM PDT 24
Peak memory 206864 kb
Host smart-98594891-3408-44d0-ac9c-018b5f16ca51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36558
88497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3655888497
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1128684262
Short name T293
Test name
Test status
Simulation time 194246685 ps
CPU time 0.85 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:20 PM PDT 24
Peak memory 206868 kb
Host smart-7e819012-016b-4166-99f7-ce34065afc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11286
84262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1128684262
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.202570480
Short name T829
Test name
Test status
Simulation time 261098510 ps
CPU time 0.99 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:12:19 PM PDT 24
Peak memory 206864 kb
Host smart-177ec343-cbe3-475d-8acc-43a7f687f1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257
0480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.202570480
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3417603570
Short name T2013
Test name
Test status
Simulation time 165631188 ps
CPU time 0.83 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:20 PM PDT 24
Peak memory 206796 kb
Host smart-27623ac6-11cf-4d41-8714-9e5695097aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34176
03570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3417603570
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.618690037
Short name T714
Test name
Test status
Simulation time 248792870 ps
CPU time 0.97 seconds
Started Jul 13 07:12:21 PM PDT 24
Finished Jul 13 07:12:24 PM PDT 24
Peak memory 206872 kb
Host smart-ae348413-78e9-4b23-b766-a37904b77838
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=618690037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.618690037
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1731699119
Short name T2299
Test name
Test status
Simulation time 149871053 ps
CPU time 0.79 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:15 PM PDT 24
Peak memory 206872 kb
Host smart-fb685ba3-aab6-4929-b48c-176e9d80d559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17316
99119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1731699119
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1392306692
Short name T2034
Test name
Test status
Simulation time 36410709 ps
CPU time 0.73 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:15 PM PDT 24
Peak memory 206904 kb
Host smart-5a4733b4-22a8-4b72-b06a-9652db7f368e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13923
06692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1392306692
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3417608994
Short name T381
Test name
Test status
Simulation time 15520381025 ps
CPU time 38.52 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:12:57 PM PDT 24
Peak memory 207124 kb
Host smart-50e097b1-a98b-4abe-b762-02e4f532c4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34176
08994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3417608994
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3502950893
Short name T764
Test name
Test status
Simulation time 181092369 ps
CPU time 0.85 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:12:19 PM PDT 24
Peak memory 206860 kb
Host smart-1992b270-f5ca-4943-a06a-b298ccc5ce37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35029
50893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3502950893
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.11680823
Short name T2458
Test name
Test status
Simulation time 236881105 ps
CPU time 0.92 seconds
Started Jul 13 07:12:19 PM PDT 24
Finished Jul 13 07:12:22 PM PDT 24
Peak memory 206868 kb
Host smart-8e4dc671-305c-46f5-9910-555f497062cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11680
823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.11680823
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3332333608
Short name T711
Test name
Test status
Simulation time 224643450 ps
CPU time 0.87 seconds
Started Jul 13 07:12:19 PM PDT 24
Finished Jul 13 07:12:22 PM PDT 24
Peak memory 206852 kb
Host smart-37460c4d-3eed-4054-887a-27acad4fd045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33323
33608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3332333608
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1975298578
Short name T1760
Test name
Test status
Simulation time 241365030 ps
CPU time 0.89 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:20 PM PDT 24
Peak memory 207052 kb
Host smart-d29797f9-5024-49af-a18c-e9e2e38afb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19752
98578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1975298578
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.140385145
Short name T1045
Test name
Test status
Simulation time 136500335 ps
CPU time 0.76 seconds
Started Jul 13 07:12:21 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206864 kb
Host smart-d5615710-c50b-4b19-8ed2-a5b8484e1bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14038
5145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.140385145
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3842126542
Short name T1361
Test name
Test status
Simulation time 142821183 ps
CPU time 0.81 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:16 PM PDT 24
Peak memory 206872 kb
Host smart-e151a8f3-b3a3-49e0-9304-eeca8904a67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38421
26542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3842126542
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.619640271
Short name T1571
Test name
Test status
Simulation time 144363053 ps
CPU time 0.74 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:20 PM PDT 24
Peak memory 206860 kb
Host smart-586599ac-77e7-4a17-81d8-0249fe9f07c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61964
0271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.619640271
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.4192418017
Short name T2027
Test name
Test status
Simulation time 227557003 ps
CPU time 0.95 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:16 PM PDT 24
Peak memory 206832 kb
Host smart-700db301-6131-4993-af42-5be8e90cb6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41924
18017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.4192418017
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2636999946
Short name T646
Test name
Test status
Simulation time 3475181612 ps
CPU time 23.86 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:12:42 PM PDT 24
Peak memory 207148 kb
Host smart-b97b242c-e646-45b4-9401-087061539503
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2636999946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2636999946
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1947659368
Short name T2466
Test name
Test status
Simulation time 157715472 ps
CPU time 0.78 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:21 PM PDT 24
Peak memory 206868 kb
Host smart-855ad31a-397b-4e3b-84fd-45eb740d7aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19476
59368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1947659368
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3861822018
Short name T1275
Test name
Test status
Simulation time 199849408 ps
CPU time 0.84 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206844 kb
Host smart-0d8cbb70-0b65-4116-87c8-2e8c87f096ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38618
22018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3861822018
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3379236594
Short name T750
Test name
Test status
Simulation time 764996077 ps
CPU time 1.83 seconds
Started Jul 13 07:12:17 PM PDT 24
Finished Jul 13 07:12:21 PM PDT 24
Peak memory 207020 kb
Host smart-3497d697-9c14-4382-affe-314d0d1af892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33792
36594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3379236594
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1250212001
Short name T1485
Test name
Test status
Simulation time 4585127352 ps
CPU time 41.31 seconds
Started Jul 13 07:12:14 PM PDT 24
Finished Jul 13 07:12:56 PM PDT 24
Peak memory 207124 kb
Host smart-155f2024-0a46-4880-8f7f-77c366759901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12502
12001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1250212001
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.2006935473
Short name T2731
Test name
Test status
Simulation time 35901100 ps
CPU time 0.72 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 206936 kb
Host smart-721eb0a0-3775-440f-a377-eb14843d3140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2006935473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.2006935473
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2653950214
Short name T2736
Test name
Test status
Simulation time 4272959979 ps
CPU time 5.51 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 207136 kb
Host smart-c135d158-8ce8-4dbd-b343-71806809fbfe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2653950214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2653950214
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2732514046
Short name T2537
Test name
Test status
Simulation time 13382833405 ps
CPU time 15.59 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 207136 kb
Host smart-35622e73-089b-4cdb-b01f-6e8431d39216
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2732514046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2732514046
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2886865162
Short name T1510
Test name
Test status
Simulation time 23401005107 ps
CPU time 25.02 seconds
Started Jul 13 07:12:19 PM PDT 24
Finished Jul 13 07:12:46 PM PDT 24
Peak memory 206936 kb
Host smart-8fa3b340-4db5-4460-be43-dee828803376
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2886865162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2886865162
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.81207513
Short name T1337
Test name
Test status
Simulation time 182064493 ps
CPU time 0.86 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206864 kb
Host smart-cd729247-b631-4a80-afb9-8856650c088d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81207
513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.81207513
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1890725843
Short name T1643
Test name
Test status
Simulation time 186831752 ps
CPU time 0.8 seconds
Started Jul 13 07:12:19 PM PDT 24
Finished Jul 13 07:12:22 PM PDT 24
Peak memory 206868 kb
Host smart-7f1a81ec-9199-403e-9907-b6bd8dd68a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18907
25843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1890725843
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1569981817
Short name T1867
Test name
Test status
Simulation time 288878388 ps
CPU time 1.11 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206864 kb
Host smart-082b3a34-3046-442a-a468-cecfd34772a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15699
81817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1569981817
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2803959307
Short name T2735
Test name
Test status
Simulation time 660992778 ps
CPU time 1.58 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:21 PM PDT 24
Peak memory 207012 kb
Host smart-ce9eb4ac-11c9-4d98-9052-2411e5833db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28039
59307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2803959307
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3842508720
Short name T30
Test name
Test status
Simulation time 11690611256 ps
CPU time 23.66 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:44 PM PDT 24
Peak memory 207136 kb
Host smart-871de1a0-0168-4612-93d4-6ca6f7a23912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38425
08720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3842508720
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.4032828955
Short name T300
Test name
Test status
Simulation time 426691162 ps
CPU time 1.27 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:18 PM PDT 24
Peak memory 206900 kb
Host smart-52125c86-5bde-4441-9a9b-8b5e32b7ffc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40328
28955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.4032828955
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.147072453
Short name T2188
Test name
Test status
Simulation time 142216473 ps
CPU time 0.74 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206844 kb
Host smart-2fcf6159-57f6-42ef-98c1-2cfbc4e12be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14707
2453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.147072453
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2059491962
Short name T704
Test name
Test status
Simulation time 36519370 ps
CPU time 0.65 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206844 kb
Host smart-53258f2a-b30e-4ba3-ac5a-2804126053fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20594
91962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2059491962
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2663316357
Short name T199
Test name
Test status
Simulation time 855118874 ps
CPU time 2.02 seconds
Started Jul 13 07:12:22 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 207048 kb
Host smart-a2666c6d-962b-4459-93ab-0db02ba2d011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26633
16357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2663316357
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2442222062
Short name T1505
Test name
Test status
Simulation time 370427905 ps
CPU time 2.4 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:12:21 PM PDT 24
Peak memory 206988 kb
Host smart-d29e7c06-b727-4f7c-a037-47b7113677a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24422
22062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2442222062
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2203507895
Short name T2098
Test name
Test status
Simulation time 228448947 ps
CPU time 0.9 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:22 PM PDT 24
Peak memory 206864 kb
Host smart-cde40c27-1ca9-4aaf-a736-8c625352c743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22035
07895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2203507895
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2887062191
Short name T1716
Test name
Test status
Simulation time 182832195 ps
CPU time 0.78 seconds
Started Jul 13 07:12:18 PM PDT 24
Finished Jul 13 07:12:21 PM PDT 24
Peak memory 206892 kb
Host smart-34f826c2-2718-41ff-bd29-7b4cfa21e887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
62191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2887062191
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1319348911
Short name T1744
Test name
Test status
Simulation time 242918379 ps
CPU time 0.98 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206872 kb
Host smart-7a1bcead-03f5-4fe4-8d85-6ccfce6695ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13193
48911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1319348911
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.1943862454
Short name T1538
Test name
Test status
Simulation time 6569332909 ps
CPU time 61.54 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:13:26 PM PDT 24
Peak memory 207028 kb
Host smart-bd55d3c8-ed1c-477d-b37f-3e13071b2b35
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1943862454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1943862454
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1158926691
Short name T962
Test name
Test status
Simulation time 240516480 ps
CPU time 0.91 seconds
Started Jul 13 07:12:21 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206872 kb
Host smart-85ff5762-3b07-48ff-a098-41b783133882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11589
26691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1158926691
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.4219301952
Short name T2714
Test name
Test status
Simulation time 23303312599 ps
CPU time 20.58 seconds
Started Jul 13 07:12:22 PM PDT 24
Finished Jul 13 07:12:45 PM PDT 24
Peak memory 206904 kb
Host smart-c09d0c03-1d7d-4825-b658-e3717624d491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42193
01952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.4219301952
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3352888895
Short name T2543
Test name
Test status
Simulation time 3332313953 ps
CPU time 4.11 seconds
Started Jul 13 07:12:21 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 206940 kb
Host smart-b0f65d58-1065-45ef-92bc-97f9b1de3577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33528
88895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3352888895
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.2262985328
Short name T1671
Test name
Test status
Simulation time 9949726021 ps
CPU time 283.08 seconds
Started Jul 13 07:12:22 PM PDT 24
Finished Jul 13 07:17:07 PM PDT 24
Peak memory 207112 kb
Host smart-78c00dd9-5930-44ee-97ba-4445adbbe845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22629
85328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.2262985328
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2551109121
Short name T405
Test name
Test status
Simulation time 5591319239 ps
CPU time 40.19 seconds
Started Jul 13 07:12:21 PM PDT 24
Finished Jul 13 07:13:03 PM PDT 24
Peak memory 207036 kb
Host smart-9f4eb479-68e8-42a1-bdae-dfcaf10d3028
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2551109121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2551109121
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1633191059
Short name T884
Test name
Test status
Simulation time 282320297 ps
CPU time 0.91 seconds
Started Jul 13 07:12:15 PM PDT 24
Finished Jul 13 07:12:18 PM PDT 24
Peak memory 206876 kb
Host smart-3687b8e8-baa8-435a-b002-35fcadc3e4aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1633191059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1633191059
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2393659361
Short name T922
Test name
Test status
Simulation time 191084331 ps
CPU time 0.85 seconds
Started Jul 13 07:12:21 PM PDT 24
Finished Jul 13 07:12:24 PM PDT 24
Peak memory 206876 kb
Host smart-8d52b05e-a987-4946-afad-fd7b378964c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23936
59361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2393659361
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.3456598621
Short name T1151
Test name
Test status
Simulation time 4398027926 ps
CPU time 42.82 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 207144 kb
Host smart-51a26263-4d59-4f0e-96fd-c4da119d25dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34565
98621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.3456598621
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2887092711
Short name T889
Test name
Test status
Simulation time 4846939996 ps
CPU time 48.32 seconds
Started Jul 13 07:12:16 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 207092 kb
Host smart-c1745cfa-74db-4956-bf3b-12fc8f27c099
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2887092711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2887092711
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.793410277
Short name T1252
Test name
Test status
Simulation time 168563189 ps
CPU time 0.8 seconds
Started Jul 13 07:12:20 PM PDT 24
Finished Jul 13 07:12:23 PM PDT 24
Peak memory 206868 kb
Host smart-c4b50a88-6c05-48c3-a631-81f78fd6a0f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=793410277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.793410277
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.853362049
Short name T1597
Test name
Test status
Simulation time 157365817 ps
CPU time 0.8 seconds
Started Jul 13 07:12:19 PM PDT 24
Finished Jul 13 07:12:22 PM PDT 24
Peak memory 206868 kb
Host smart-01d0b79e-5acd-41dc-a0c1-713264cd3a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85336
2049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.853362049
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1069933005
Short name T2550
Test name
Test status
Simulation time 224667115 ps
CPU time 0.83 seconds
Started Jul 13 07:12:25 PM PDT 24
Finished Jul 13 07:12:28 PM PDT 24
Peak memory 206884 kb
Host smart-084381ed-e2fe-4a8b-b494-53483c1dd409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699
33005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1069933005
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3009318049
Short name T1806
Test name
Test status
Simulation time 198454327 ps
CPU time 0.86 seconds
Started Jul 13 07:12:27 PM PDT 24
Finished Jul 13 07:12:29 PM PDT 24
Peak memory 206004 kb
Host smart-6bab458a-048f-42cc-8e68-1ffa8c3de108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30093
18049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3009318049
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2010622264
Short name T1722
Test name
Test status
Simulation time 175944232 ps
CPU time 0.89 seconds
Started Jul 13 07:12:27 PM PDT 24
Finished Jul 13 07:12:29 PM PDT 24
Peak memory 206868 kb
Host smart-0ea403e0-9ade-411a-9642-ea7d1a46a7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20106
22264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2010622264
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1827598127
Short name T930
Test name
Test status
Simulation time 157535229 ps
CPU time 0.83 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 206872 kb
Host smart-2b878fe9-8ee3-4e35-8731-03f9fea3d3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18275
98127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1827598127
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.881451339
Short name T1217
Test name
Test status
Simulation time 198106990 ps
CPU time 0.89 seconds
Started Jul 13 07:12:22 PM PDT 24
Finished Jul 13 07:12:25 PM PDT 24
Peak memory 206904 kb
Host smart-43e4b48b-789f-4eb1-aedf-b51180ddbc85
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=881451339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.881451339
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3796592215
Short name T2674
Test name
Test status
Simulation time 157072609 ps
CPU time 0.78 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 206856 kb
Host smart-ec97ca26-fee5-41b3-96f9-865a5d6dcc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
92215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3796592215
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.449504052
Short name T2007
Test name
Test status
Simulation time 41342161 ps
CPU time 0.67 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 206860 kb
Host smart-19909b13-1352-4459-8cca-ef8ae1c3b67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44950
4052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.449504052
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2597553709
Short name T618
Test name
Test status
Simulation time 9954584396 ps
CPU time 23.87 seconds
Started Jul 13 07:12:25 PM PDT 24
Finished Jul 13 07:12:51 PM PDT 24
Peak memory 207160 kb
Host smart-4f264cca-7884-4e63-9cc0-e958441e959b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25975
53709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2597553709
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3308606598
Short name T809
Test name
Test status
Simulation time 167878977 ps
CPU time 0.88 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 206868 kb
Host smart-594faa4c-7408-4642-b77b-7aba43f0a9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
06598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3308606598
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2814331090
Short name T1673
Test name
Test status
Simulation time 172567148 ps
CPU time 0.88 seconds
Started Jul 13 07:12:25 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 206852 kb
Host smart-e15cb430-ffbd-4da4-9c07-94ae9468ae1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28143
31090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2814331090
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3643803182
Short name T1396
Test name
Test status
Simulation time 223411477 ps
CPU time 0.88 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 206880 kb
Host smart-a5e05c8c-39bf-46b9-934a-3a203a8f53a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36438
03182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3643803182
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1982499631
Short name T2342
Test name
Test status
Simulation time 245375181 ps
CPU time 0.91 seconds
Started Jul 13 07:12:29 PM PDT 24
Finished Jul 13 07:12:30 PM PDT 24
Peak memory 206860 kb
Host smart-4cc0750e-1204-409e-8dec-a8f36922b590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19824
99631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1982499631
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1598667692
Short name T1044
Test name
Test status
Simulation time 182559701 ps
CPU time 0.83 seconds
Started Jul 13 07:12:22 PM PDT 24
Finished Jul 13 07:12:25 PM PDT 24
Peak memory 206880 kb
Host smart-c8aa1fd3-077f-4c1d-8f13-047a5eefff8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15986
67692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1598667692
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2310624102
Short name T839
Test name
Test status
Simulation time 149263457 ps
CPU time 0.81 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 206860 kb
Host smart-d2a02b50-2a07-48f7-a0ca-334a302ec5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23106
24102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2310624102
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2281805022
Short name T1265
Test name
Test status
Simulation time 164220786 ps
CPU time 0.79 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 206868 kb
Host smart-f0b78cae-a1ed-4994-9aac-60f2ae600ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22818
05022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2281805022
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2250194422
Short name T1964
Test name
Test status
Simulation time 241983083 ps
CPU time 0.93 seconds
Started Jul 13 07:12:27 PM PDT 24
Finished Jul 13 07:12:29 PM PDT 24
Peak memory 206136 kb
Host smart-d50cdce7-313a-411f-8a8c-b3a4d39f4227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22501
94422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2250194422
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2747044327
Short name T982
Test name
Test status
Simulation time 5520195969 ps
CPU time 52.2 seconds
Started Jul 13 07:12:22 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 207068 kb
Host smart-d4a6ecb5-3b02-47d1-aa82-7f22d0a4ed49
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2747044327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2747044327
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1675651119
Short name T1042
Test name
Test status
Simulation time 158277057 ps
CPU time 0.8 seconds
Started Jul 13 07:12:21 PM PDT 24
Finished Jul 13 07:12:24 PM PDT 24
Peak memory 206856 kb
Host smart-3112ebb4-822e-47ae-bc3b-035650522268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16756
51119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1675651119
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.339525944
Short name T193
Test name
Test status
Simulation time 170014939 ps
CPU time 0.77 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 206752 kb
Host smart-cd6e55ff-b268-4cae-8017-f6cdb2d860da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
5944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.339525944
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.2581537312
Short name T1482
Test name
Test status
Simulation time 1007952235 ps
CPU time 2.27 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:28 PM PDT 24
Peak memory 207020 kb
Host smart-6b266082-b952-4f6f-ad7b-adaaf54c2f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25815
37312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.2581537312
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2292738665
Short name T524
Test name
Test status
Simulation time 5520592935 ps
CPU time 155.39 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 207104 kb
Host smart-1709fa8b-6a16-4727-9019-38c7fd12849d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22927
38665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2292738665
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.13253948
Short name T1504
Test name
Test status
Simulation time 117835603 ps
CPU time 0.76 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:12:35 PM PDT 24
Peak memory 206972 kb
Host smart-1ef58539-6aa6-4ae5-b3f8-c627afbfb622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=13253948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.13253948
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.358129519
Short name T183
Test name
Test status
Simulation time 4006496015 ps
CPU time 4.95 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:30 PM PDT 24
Peak memory 206944 kb
Host smart-44da2b5f-6b86-42cf-a4f2-6b8b2162a09c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=358129519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.358129519
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2166451243
Short name T1191
Test name
Test status
Simulation time 13435845053 ps
CPU time 13.39 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:39 PM PDT 24
Peak memory 206944 kb
Host smart-a4fb8642-ed09-46a3-9e5b-1b5dfbe615da
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2166451243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2166451243
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1679693573
Short name T13
Test name
Test status
Simulation time 23305218077 ps
CPU time 23.21 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:50 PM PDT 24
Peak memory 206936 kb
Host smart-d07ac8eb-20bd-49c4-8351-60d816602482
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1679693573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1679693573
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2494253153
Short name T2250
Test name
Test status
Simulation time 161291318 ps
CPU time 0.85 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 206844 kb
Host smart-8781da53-c788-4096-a5b1-729d0b96d371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24942
53153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2494253153
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1895497
Short name T2606
Test name
Test status
Simulation time 237472714 ps
CPU time 0.8 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 206888 kb
Host smart-dfd464df-f798-4f93-91d9-6734825f6edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18954
97 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1895497
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.2539186814
Short name T2281
Test name
Test status
Simulation time 238381803 ps
CPU time 0.93 seconds
Started Jul 13 07:12:26 PM PDT 24
Finished Jul 13 07:12:28 PM PDT 24
Peak memory 206860 kb
Host smart-3b51a6fb-6cf8-4a34-b711-7c7a29b2c00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391
86814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.2539186814
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3770645660
Short name T2000
Test name
Test status
Simulation time 558519237 ps
CPU time 1.7 seconds
Started Jul 13 07:12:26 PM PDT 24
Finished Jul 13 07:12:29 PM PDT 24
Peak memory 206828 kb
Host smart-6642100e-4cec-4cd6-ba17-05839268accd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37706
45660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3770645660
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.228676623
Short name T905
Test name
Test status
Simulation time 15552673870 ps
CPU time 31.24 seconds
Started Jul 13 07:12:28 PM PDT 24
Finished Jul 13 07:13:00 PM PDT 24
Peak memory 207084 kb
Host smart-d66cc5c3-c3d0-4985-98fc-854ca5a03d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22867
6623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.228676623
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1622897841
Short name T2323
Test name
Test status
Simulation time 501115380 ps
CPU time 1.33 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:26 PM PDT 24
Peak memory 206884 kb
Host smart-7801e0ed-86c5-4c9f-8e36-1b77054e4362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
97841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1622897841
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_enable.782326303
Short name T1828
Test name
Test status
Simulation time 39065652 ps
CPU time 0.65 seconds
Started Jul 13 07:12:28 PM PDT 24
Finished Jul 13 07:12:29 PM PDT 24
Peak memory 206848 kb
Host smart-2862e4be-11b7-4000-964b-d235d6ce6bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78232
6303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.782326303
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3186654377
Short name T2076
Test name
Test status
Simulation time 1028808219 ps
CPU time 2.38 seconds
Started Jul 13 07:12:24 PM PDT 24
Finished Jul 13 07:12:29 PM PDT 24
Peak memory 207016 kb
Host smart-cf79457b-a2af-4e6c-baa2-120b993c21b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31866
54377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3186654377
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1864758350
Short name T2665
Test name
Test status
Simulation time 218263054 ps
CPU time 2.09 seconds
Started Jul 13 07:12:23 PM PDT 24
Finished Jul 13 07:12:27 PM PDT 24
Peak memory 207068 kb
Host smart-5453a0af-b1c3-41ad-9b43-d15f79d4c033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18647
58350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1864758350
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3259795922
Short name T383
Test name
Test status
Simulation time 141068168 ps
CPU time 0.77 seconds
Started Jul 13 07:12:29 PM PDT 24
Finished Jul 13 07:12:30 PM PDT 24
Peak memory 206872 kb
Host smart-80de17ad-5a8d-4edf-ad24-71705023e09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597
95922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3259795922
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3296912304
Short name T473
Test name
Test status
Simulation time 194831873 ps
CPU time 0.89 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:12:35 PM PDT 24
Peak memory 206804 kb
Host smart-998ad268-eec9-4bde-8cc0-56b3e4088961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32969
12304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3296912304
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.765827009
Short name T1528
Test name
Test status
Simulation time 10216624785 ps
CPU time 281.23 seconds
Started Jul 13 07:12:27 PM PDT 24
Finished Jul 13 07:17:09 PM PDT 24
Peak memory 207056 kb
Host smart-3151c825-0892-49fe-bb54-2703f3e5f8bf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=765827009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.765827009
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.3517847450
Short name T1676
Test name
Test status
Simulation time 3813075582 ps
CPU time 30.74 seconds
Started Jul 13 07:12:32 PM PDT 24
Finished Jul 13 07:13:03 PM PDT 24
Peak memory 207140 kb
Host smart-1699aa28-66f3-44d7-8482-fdff0c3a175e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35178
47450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.3517847450
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3424339246
Short name T453
Test name
Test status
Simulation time 227455356 ps
CPU time 0.92 seconds
Started Jul 13 07:12:35 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 206864 kb
Host smart-febc7dcf-693f-4efc-a351-bae3f13d12aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34243
39246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3424339246
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.2774967908
Short name T1059
Test name
Test status
Simulation time 23352658822 ps
CPU time 22.31 seconds
Started Jul 13 07:12:32 PM PDT 24
Finished Jul 13 07:12:55 PM PDT 24
Peak memory 206940 kb
Host smart-474daec7-d643-4479-baf3-00d78a862cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27749
67908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.2774967908
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1753121283
Short name T2206
Test name
Test status
Simulation time 3366250921 ps
CPU time 4.16 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:12:38 PM PDT 24
Peak memory 206868 kb
Host smart-ca98802e-334e-4025-9f78-31a433d4bd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17531
21283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1753121283
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3823679874
Short name T1164
Test name
Test status
Simulation time 9214166954 ps
CPU time 94 seconds
Started Jul 13 07:12:36 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 207136 kb
Host smart-81ed898e-5cc7-44e5-b746-f6b331354e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38236
79874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3823679874
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.909836136
Short name T2022
Test name
Test status
Simulation time 4748074607 ps
CPU time 45 seconds
Started Jul 13 07:12:36 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 207348 kb
Host smart-3ac7ca9d-ae7f-4891-bddf-059ad0d67865
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=909836136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.909836136
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2732086438
Short name T1174
Test name
Test status
Simulation time 246645639 ps
CPU time 0.87 seconds
Started Jul 13 07:12:32 PM PDT 24
Finished Jul 13 07:12:33 PM PDT 24
Peak memory 206844 kb
Host smart-11af2baa-3c61-47cb-b7ba-0bc63f469724
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2732086438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2732086438
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1974472627
Short name T563
Test name
Test status
Simulation time 204429336 ps
CPU time 0.87 seconds
Started Jul 13 07:12:35 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 206868 kb
Host smart-ae82f232-8fe2-4c43-8524-78cde5a03aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19744
72627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1974472627
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3733997980
Short name T853
Test name
Test status
Simulation time 4554867832 ps
CPU time 34.2 seconds
Started Jul 13 07:12:32 PM PDT 24
Finished Jul 13 07:13:07 PM PDT 24
Peak memory 207140 kb
Host smart-1919293a-c90e-4401-a199-8f3052eaf36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
97980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3733997980
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.499086924
Short name T212
Test name
Test status
Simulation time 5123459334 ps
CPU time 135.13 seconds
Started Jul 13 07:12:36 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 207056 kb
Host smart-2a4f0693-1bed-4a4c-83f5-3876de688892
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=499086924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.499086924
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3082253295
Short name T854
Test name
Test status
Simulation time 157482167 ps
CPU time 0.8 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:12:35 PM PDT 24
Peak memory 206868 kb
Host smart-15b479ee-9605-4a10-9e82-60923f3f3eae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3082253295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3082253295
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3601519436
Short name T2182
Test name
Test status
Simulation time 182479614 ps
CPU time 0.84 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 206900 kb
Host smart-a127e5ea-58e3-4d2a-ba9f-474fcf8228e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36015
19436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3601519436
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1841042575
Short name T2632
Test name
Test status
Simulation time 222224298 ps
CPU time 0.86 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 206860 kb
Host smart-f29316d8-55c0-4c12-add1-057d4099adcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18410
42575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1841042575
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.271571856
Short name T2238
Test name
Test status
Simulation time 187255040 ps
CPU time 0.89 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 206864 kb
Host smart-4064bd8e-ef86-4fba-95e5-57dc66869b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27157
1856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.271571856
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1178598725
Short name T1344
Test name
Test status
Simulation time 155305213 ps
CPU time 0.84 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 206872 kb
Host smart-afc96d84-353a-4b97-b4fd-84c30ef6da3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11785
98725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1178598725
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2844283010
Short name T283
Test name
Test status
Simulation time 197052321 ps
CPU time 0.9 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 206860 kb
Host smart-b528b528-dccc-437c-a75b-92c4bf5f70ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28442
83010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2844283010
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1567318037
Short name T772
Test name
Test status
Simulation time 161622839 ps
CPU time 0.85 seconds
Started Jul 13 07:12:36 PM PDT 24
Finished Jul 13 07:12:38 PM PDT 24
Peak memory 207112 kb
Host smart-309d5b2b-e64c-4fda-9449-c37346c2612a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673
18037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1567318037
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2165141112
Short name T2337
Test name
Test status
Simulation time 226039549 ps
CPU time 0.98 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 206876 kb
Host smart-2565891f-9514-4c4a-9af1-cb471a5ac415
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2165141112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2165141112
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3554646458
Short name T311
Test name
Test status
Simulation time 165124327 ps
CPU time 0.77 seconds
Started Jul 13 07:12:35 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 206864 kb
Host smart-502b32e6-e6a1-4f0d-b859-936f7a8b819d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35546
46458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3554646458
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2538187524
Short name T926
Test name
Test status
Simulation time 27792680 ps
CPU time 0.66 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:12:34 PM PDT 24
Peak memory 206840 kb
Host smart-1d268295-6ab4-4f44-854b-47dcb511a82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25381
87524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2538187524
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.683470800
Short name T1548
Test name
Test status
Simulation time 10538270885 ps
CPU time 23.31 seconds
Started Jul 13 07:12:36 PM PDT 24
Finished Jul 13 07:13:00 PM PDT 24
Peak memory 207168 kb
Host smart-e58197b1-a89b-41c3-8941-1bc2e43b4b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68347
0800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.683470800
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.953605661
Short name T1295
Test name
Test status
Simulation time 163076375 ps
CPU time 0.99 seconds
Started Jul 13 07:12:36 PM PDT 24
Finished Jul 13 07:12:38 PM PDT 24
Peak memory 206864 kb
Host smart-b6ed9107-bfa2-442e-ba4b-bee762952289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95360
5661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.953605661
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1769667026
Short name T361
Test name
Test status
Simulation time 257822983 ps
CPU time 0.92 seconds
Started Jul 13 07:12:32 PM PDT 24
Finished Jul 13 07:12:34 PM PDT 24
Peak memory 206820 kb
Host smart-bea34227-ff22-4b54-96e2-653702f21b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17696
67026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1769667026
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.113064571
Short name T770
Test name
Test status
Simulation time 199211081 ps
CPU time 0.85 seconds
Started Jul 13 07:12:35 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 206868 kb
Host smart-0469f61f-49a2-480f-8a4a-5bde8ea9c5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11306
4571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.113064571
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.4040890238
Short name T660
Test name
Test status
Simulation time 152701359 ps
CPU time 0.78 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 206868 kb
Host smart-6972fe9f-209e-4f4c-b204-70cacd2f220a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40408
90238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.4040890238
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2027387732
Short name T1467
Test name
Test status
Simulation time 156626130 ps
CPU time 0.8 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 206856 kb
Host smart-60acf356-f2b7-4fd1-ac2c-9a8316b1c99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273
87732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2027387732
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.420927634
Short name T2114
Test name
Test status
Simulation time 170389954 ps
CPU time 0.82 seconds
Started Jul 13 07:12:35 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 206860 kb
Host smart-93d21d98-ed8c-43b1-9575-1e9b71457685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42092
7634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.420927634
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3878715856
Short name T1350
Test name
Test status
Simulation time 185621894 ps
CPU time 0.85 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 206872 kb
Host smart-a21cffb2-d2af-486a-87fe-adb527fb378f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38787
15856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3878715856
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3009353250
Short name T1594
Test name
Test status
Simulation time 209734213 ps
CPU time 0.96 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:12:34 PM PDT 24
Peak memory 206880 kb
Host smart-eac61975-178a-487c-a95e-877c47f34605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30093
53250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3009353250
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3616656186
Short name T377
Test name
Test status
Simulation time 4569465455 ps
CPU time 128.82 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 207104 kb
Host smart-5453b5b9-3aff-4f31-aeff-9763c416b152
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3616656186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3616656186
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3925353453
Short name T2400
Test name
Test status
Simulation time 172413002 ps
CPU time 0.88 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:36 PM PDT 24
Peak memory 206856 kb
Host smart-1de2cb7c-a260-416e-ac7f-8a234cc9854c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39253
53453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3925353453
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1026445217
Short name T2476
Test name
Test status
Simulation time 150505199 ps
CPU time 0.83 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:12:34 PM PDT 24
Peak memory 206864 kb
Host smart-02ba88d3-6dbd-4878-bae3-42167b51664e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264
45217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1026445217
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.2458141784
Short name T1358
Test name
Test status
Simulation time 1271213592 ps
CPU time 2.58 seconds
Started Jul 13 07:12:35 PM PDT 24
Finished Jul 13 07:12:39 PM PDT 24
Peak memory 207244 kb
Host smart-be42036f-fbe6-4e1d-9c50-87daaee140a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24581
41784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.2458141784
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3034903083
Short name T2176
Test name
Test status
Simulation time 3875396942 ps
CPU time 109.06 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:14:23 PM PDT 24
Peak memory 207068 kb
Host smart-74a74664-e068-46b2-bdbf-43f62b3b6479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30349
03083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3034903083
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.3355681912
Short name T1462
Test name
Test status
Simulation time 54898991 ps
CPU time 0.7 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:51 PM PDT 24
Peak memory 206956 kb
Host smart-7fd8c10f-3c1b-4dea-bb93-40de17f859b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3355681912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.3355681912
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.3843072198
Short name T1356
Test name
Test status
Simulation time 3987753005 ps
CPU time 4.5 seconds
Started Jul 13 07:12:33 PM PDT 24
Finished Jul 13 07:12:39 PM PDT 24
Peak memory 206932 kb
Host smart-80c6fd59-7315-4f04-805c-ed9f01865999
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3843072198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.3843072198
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.314941089
Short name T1532
Test name
Test status
Simulation time 13468223494 ps
CPU time 13.36 seconds
Started Jul 13 07:12:34 PM PDT 24
Finished Jul 13 07:12:49 PM PDT 24
Peak memory 206928 kb
Host smart-332c5af6-4e56-4546-9182-b334c03fe12a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=314941089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.314941089
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1543048868
Short name T2103
Test name
Test status
Simulation time 23363079264 ps
CPU time 23.66 seconds
Started Jul 13 07:12:35 PM PDT 24
Finished Jul 13 07:13:00 PM PDT 24
Peak memory 206936 kb
Host smart-4cdbdfbf-75c1-40ee-8538-0e6f03627d70
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1543048868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1543048868
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1033387605
Short name T466
Test name
Test status
Simulation time 146825562 ps
CPU time 0.82 seconds
Started Jul 13 07:12:35 PM PDT 24
Finished Jul 13 07:12:37 PM PDT 24
Peak memory 206868 kb
Host smart-64d2d1cb-30c1-4eae-9abf-ff405ad76cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10333
87605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1033387605
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2428714222
Short name T2236
Test name
Test status
Simulation time 189215205 ps
CPU time 0.8 seconds
Started Jul 13 07:12:43 PM PDT 24
Finished Jul 13 07:12:44 PM PDT 24
Peak memory 206856 kb
Host smart-4ae1d5a9-dcc6-4fe4-a6b0-b94733151b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24287
14222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2428714222
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.994193885
Short name T2180
Test name
Test status
Simulation time 531190774 ps
CPU time 1.69 seconds
Started Jul 13 07:12:46 PM PDT 24
Finished Jul 13 07:12:49 PM PDT 24
Peak memory 207016 kb
Host smart-b9c51faa-6cdb-4cae-8855-c289b3fbd28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99419
3885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.994193885
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.511106216
Short name T597
Test name
Test status
Simulation time 569132050 ps
CPU time 1.46 seconds
Started Jul 13 07:12:42 PM PDT 24
Finished Jul 13 07:12:44 PM PDT 24
Peak memory 206864 kb
Host smart-2ead304c-eb43-4f4a-a3d4-4f8f03641fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51110
6216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.511106216
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1940717917
Short name T2726
Test name
Test status
Simulation time 15968951967 ps
CPU time 29.77 seconds
Started Jul 13 07:12:41 PM PDT 24
Finished Jul 13 07:13:11 PM PDT 24
Peak memory 207092 kb
Host smart-b4fc061b-692f-4795-ab91-4414467ee3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19407
17917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1940717917
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1580393983
Short name T2061
Test name
Test status
Simulation time 465255644 ps
CPU time 1.29 seconds
Started Jul 13 07:12:42 PM PDT 24
Finished Jul 13 07:12:44 PM PDT 24
Peak memory 206848 kb
Host smart-b6b6ada8-3eab-47bd-ba75-825f39a435de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15803
93983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1580393983
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2179452373
Short name T700
Test name
Test status
Simulation time 147374660 ps
CPU time 0.78 seconds
Started Jul 13 07:12:42 PM PDT 24
Finished Jul 13 07:12:43 PM PDT 24
Peak memory 206800 kb
Host smart-0c5503fd-e147-4556-bf4d-b9caf450386a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21794
52373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2179452373
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2333314673
Short name T2330
Test name
Test status
Simulation time 53603297 ps
CPU time 0.65 seconds
Started Jul 13 07:12:41 PM PDT 24
Finished Jul 13 07:12:42 PM PDT 24
Peak memory 206832 kb
Host smart-c8411d19-b155-4806-ab8b-2323864cc285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23333
14673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2333314673
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2724581095
Short name T1833
Test name
Test status
Simulation time 723325303 ps
CPU time 1.91 seconds
Started Jul 13 07:12:52 PM PDT 24
Finished Jul 13 07:12:55 PM PDT 24
Peak memory 207064 kb
Host smart-cb53ee8e-7fa8-4d5f-9191-49d979a242d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27245
81095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2724581095
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.616401689
Short name T1420
Test name
Test status
Simulation time 266089506 ps
CPU time 2.03 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:12:55 PM PDT 24
Peak memory 207056 kb
Host smart-78605599-73c7-4895-be45-eb4ae61f712d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61640
1689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.616401689
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3131557775
Short name T537
Test name
Test status
Simulation time 187084492 ps
CPU time 0.87 seconds
Started Jul 13 07:12:43 PM PDT 24
Finished Jul 13 07:12:44 PM PDT 24
Peak memory 206864 kb
Host smart-874a8988-bb8b-4f87-a8f6-be3b05132adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31315
57775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3131557775
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1572544625
Short name T777
Test name
Test status
Simulation time 139495552 ps
CPU time 0.77 seconds
Started Jul 13 07:12:45 PM PDT 24
Finished Jul 13 07:12:47 PM PDT 24
Peak memory 206844 kb
Host smart-7ba5703b-091c-4274-8f29-e8d01c27ac1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15725
44625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1572544625
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.4172605439
Short name T1948
Test name
Test status
Simulation time 241977517 ps
CPU time 0.94 seconds
Started Jul 13 07:12:43 PM PDT 24
Finished Jul 13 07:12:45 PM PDT 24
Peak memory 206884 kb
Host smart-b0438ad3-75b0-4012-8759-772a008f63ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41726
05439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.4172605439
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.1617464130
Short name T305
Test name
Test status
Simulation time 3926894032 ps
CPU time 31.41 seconds
Started Jul 13 07:12:43 PM PDT 24
Finished Jul 13 07:13:15 PM PDT 24
Peak memory 207136 kb
Host smart-cc10ea3c-8788-4521-9b57-a7e209639a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16174
64130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.1617464130
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3621853551
Short name T1022
Test name
Test status
Simulation time 165768560 ps
CPU time 0.82 seconds
Started Jul 13 07:12:43 PM PDT 24
Finished Jul 13 07:12:44 PM PDT 24
Peak memory 206876 kb
Host smart-a31e8248-cd57-4a43-84fe-ee46393409cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36218
53551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3621853551
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3978994047
Short name T2072
Test name
Test status
Simulation time 23307137388 ps
CPU time 23.69 seconds
Started Jul 13 07:12:46 PM PDT 24
Finished Jul 13 07:13:10 PM PDT 24
Peak memory 206876 kb
Host smart-dcd6f552-74d9-43b7-a515-97a432825f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39789
94047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3978994047
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2153557154
Short name T1313
Test name
Test status
Simulation time 3321861637 ps
CPU time 4 seconds
Started Jul 13 07:12:43 PM PDT 24
Finished Jul 13 07:12:47 PM PDT 24
Peak memory 206916 kb
Host smart-067613ad-dda3-4dfb-ab77-e1aedd451d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21535
57154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2153557154
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.3808166140
Short name T1567
Test name
Test status
Simulation time 8908310127 ps
CPU time 82.08 seconds
Started Jul 13 07:12:43 PM PDT 24
Finished Jul 13 07:14:05 PM PDT 24
Peak memory 207136 kb
Host smart-9cd7c317-243b-4c65-b4ae-616b50d01e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38081
66140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.3808166140
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2619205931
Short name T632
Test name
Test status
Simulation time 7284387310 ps
CPU time 67.61 seconds
Started Jul 13 07:12:52 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 207080 kb
Host smart-c0561bb1-2789-499e-ad68-166237a55c0a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2619205931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2619205931
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3762406693
Short name T1201
Test name
Test status
Simulation time 237768062 ps
CPU time 0.91 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:12:54 PM PDT 24
Peak memory 206864 kb
Host smart-4aa57dfe-a765-45ab-9420-490658670fd1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3762406693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3762406693
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3160175263
Short name T947
Test name
Test status
Simulation time 221834274 ps
CPU time 0.9 seconds
Started Jul 13 07:12:48 PM PDT 24
Finished Jul 13 07:12:49 PM PDT 24
Peak memory 206816 kb
Host smart-7b919f04-771f-4895-b81a-6d0ac45baffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31601
75263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3160175263
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2611079014
Short name T2325
Test name
Test status
Simulation time 4958236376 ps
CPU time 142.31 seconds
Started Jul 13 07:12:46 PM PDT 24
Finished Jul 13 07:15:09 PM PDT 24
Peak memory 207080 kb
Host smart-4efe749f-4920-44cf-9bb1-a13f085463aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26110
79014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2611079014
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1608056970
Short name T2025
Test name
Test status
Simulation time 5728756175 ps
CPU time 55 seconds
Started Jul 13 07:12:45 PM PDT 24
Finished Jul 13 07:13:41 PM PDT 24
Peak memory 207116 kb
Host smart-a773f52a-7600-46ea-a436-843b5436e581
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1608056970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1608056970
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.533251951
Short name T2574
Test name
Test status
Simulation time 146598728 ps
CPU time 0.83 seconds
Started Jul 13 07:12:42 PM PDT 24
Finished Jul 13 07:12:43 PM PDT 24
Peak memory 206880 kb
Host smart-9a94bf87-ada4-4ab2-9b7a-091742a9abf0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=533251951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.533251951
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3904391300
Short name T339
Test name
Test status
Simulation time 163276147 ps
CPU time 0.81 seconds
Started Jul 13 07:12:39 PM PDT 24
Finished Jul 13 07:12:40 PM PDT 24
Peak memory 206864 kb
Host smart-8466444a-b23a-49e9-9ee8-8b7a48970f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39043
91300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3904391300
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.823816870
Short name T1638
Test name
Test status
Simulation time 161220217 ps
CPU time 0.87 seconds
Started Jul 13 07:12:43 PM PDT 24
Finished Jul 13 07:12:45 PM PDT 24
Peak memory 206856 kb
Host smart-c84fd00a-3fa1-4b02-a1bf-c716f57a2ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82381
6870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.823816870
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2974919295
Short name T2153
Test name
Test status
Simulation time 193722312 ps
CPU time 0.83 seconds
Started Jul 13 07:12:48 PM PDT 24
Finished Jul 13 07:12:49 PM PDT 24
Peak memory 206816 kb
Host smart-d704b501-65a9-4bed-b539-cd2e1a86b574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
19295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2974919295
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3380403793
Short name T693
Test name
Test status
Simulation time 194378048 ps
CPU time 0.88 seconds
Started Jul 13 07:12:40 PM PDT 24
Finished Jul 13 07:12:41 PM PDT 24
Peak memory 206888 kb
Host smart-5c217fa1-f307-4ffa-9d9c-c857dad252d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804
03793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3380403793
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3060086783
Short name T1172
Test name
Test status
Simulation time 178475947 ps
CPU time 0.8 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:12:53 PM PDT 24
Peak memory 206864 kb
Host smart-f4956b27-7106-4ec5-84df-15525a485b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30600
86783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3060086783
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2420927756
Short name T2539
Test name
Test status
Simulation time 225254540 ps
CPU time 0.97 seconds
Started Jul 13 07:12:42 PM PDT 24
Finished Jul 13 07:12:43 PM PDT 24
Peak memory 206832 kb
Host smart-a5a4b617-d2df-4a64-96ed-943fbf91f3d7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2420927756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2420927756
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3042558025
Short name T1738
Test name
Test status
Simulation time 155803793 ps
CPU time 0.76 seconds
Started Jul 13 07:12:41 PM PDT 24
Finished Jul 13 07:12:42 PM PDT 24
Peak memory 206864 kb
Host smart-dedf9ed6-6eef-4401-94db-cc43b38b4978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30425
58025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3042558025
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.110121234
Short name T1936
Test name
Test status
Simulation time 56516877 ps
CPU time 0.69 seconds
Started Jul 13 07:12:45 PM PDT 24
Finished Jul 13 07:12:46 PM PDT 24
Peak memory 206868 kb
Host smart-53e39e47-e977-4f93-9236-d5c7faef3500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11012
1234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.110121234
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1574854122
Short name T1844
Test name
Test status
Simulation time 13363100807 ps
CPU time 31.38 seconds
Started Jul 13 07:12:49 PM PDT 24
Finished Jul 13 07:13:21 PM PDT 24
Peak memory 207144 kb
Host smart-6c57e34a-5858-4da0-8a63-01c14180e73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
54122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1574854122
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2791456258
Short name T2324
Test name
Test status
Simulation time 193408756 ps
CPU time 0.85 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:53 PM PDT 24
Peak memory 206868 kb
Host smart-48721154-18ec-4481-a55c-3f3139e7e78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27914
56258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2791456258
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1949739741
Short name T877
Test name
Test status
Simulation time 234981763 ps
CPU time 0.9 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:52 PM PDT 24
Peak memory 206864 kb
Host smart-9d87c13d-0e29-44e2-96af-533ef1b703f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19497
39741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1949739741
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2320063840
Short name T2331
Test name
Test status
Simulation time 215746346 ps
CPU time 0.94 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:52 PM PDT 24
Peak memory 206872 kb
Host smart-49937c89-7ec3-4447-afa7-66196c7004be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23200
63840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2320063840
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1940402069
Short name T622
Test name
Test status
Simulation time 170678501 ps
CPU time 0.86 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:02 PM PDT 24
Peak memory 206860 kb
Host smart-95d18b45-0924-4bff-bdf6-39a944a72eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
02069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1940402069
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3878461819
Short name T32
Test name
Test status
Simulation time 196278560 ps
CPU time 0.86 seconds
Started Jul 13 07:12:49 PM PDT 24
Finished Jul 13 07:12:50 PM PDT 24
Peak memory 206860 kb
Host smart-1f0f10b6-dedc-42f0-bd82-1fbf869fa75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38784
61819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3878461819
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2130270867
Short name T1605
Test name
Test status
Simulation time 167310083 ps
CPU time 0.8 seconds
Started Jul 13 07:12:53 PM PDT 24
Finished Jul 13 07:12:55 PM PDT 24
Peak memory 206848 kb
Host smart-22523dbc-3b20-4d02-9b49-23a32dcb2c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21302
70867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2130270867
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3682667290
Short name T1503
Test name
Test status
Simulation time 173342583 ps
CPU time 0.77 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:12:53 PM PDT 24
Peak memory 206888 kb
Host smart-f0dec114-0d74-49ff-8b09-3615a6950c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36826
67290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3682667290
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1563925947
Short name T2183
Test name
Test status
Simulation time 322164967 ps
CPU time 1 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:51 PM PDT 24
Peak memory 206872 kb
Host smart-8ae3a67e-5c14-419e-837a-b077af98ca0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15639
25947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1563925947
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.4076224655
Short name T1568
Test name
Test status
Simulation time 174604002 ps
CPU time 0.85 seconds
Started Jul 13 07:12:55 PM PDT 24
Finished Jul 13 07:12:59 PM PDT 24
Peak memory 206884 kb
Host smart-a102eb2a-89e9-4c60-a8b0-95fd8b6be301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40762
24655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.4076224655
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2619370444
Short name T2273
Test name
Test status
Simulation time 198564175 ps
CPU time 0.81 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:52 PM PDT 24
Peak memory 206876 kb
Host smart-0168119e-f0f9-4b22-8b1a-6fd26f597690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26193
70444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2619370444
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.755191714
Short name T575
Test name
Test status
Simulation time 263298624 ps
CPU time 0.98 seconds
Started Jul 13 07:12:53 PM PDT 24
Finished Jul 13 07:12:58 PM PDT 24
Peak memory 206868 kb
Host smart-e5f2537f-d72d-4152-a181-30fe35d1e8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75519
1714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.755191714
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1157707808
Short name T1734
Test name
Test status
Simulation time 4879833036 ps
CPU time 46.26 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:13:39 PM PDT 24
Peak memory 206940 kb
Host smart-3c410d8b-381e-4113-af65-7a7417ad4166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577
07808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1157707808
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.2051028958
Short name T2584
Test name
Test status
Simulation time 43131317 ps
CPU time 0.73 seconds
Started Jul 13 07:08:39 PM PDT 24
Finished Jul 13 07:08:41 PM PDT 24
Peak memory 207088 kb
Host smart-7639e9d0-8a8c-45fe-a54a-aee787c16b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2051028958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2051028958
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2204283432
Short name T2345
Test name
Test status
Simulation time 4390565562 ps
CPU time 5.34 seconds
Started Jul 13 07:08:09 PM PDT 24
Finished Jul 13 07:08:16 PM PDT 24
Peak memory 207148 kb
Host smart-5b28919e-938a-4e82-8777-d0ba9a4cfd3b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2204283432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.2204283432
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.4230459277
Short name T907
Test name
Test status
Simulation time 13368053737 ps
CPU time 13.53 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:08:26 PM PDT 24
Peak memory 206936 kb
Host smart-99f38faa-9e50-4195-9454-615a75bc026f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4230459277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.4230459277
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2954952240
Short name T2222
Test name
Test status
Simulation time 23323287222 ps
CPU time 22.68 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:36 PM PDT 24
Peak memory 206924 kb
Host smart-3285581c-65b7-4788-a803-bf8d9cb2a5d5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2954952240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2954952240
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.439562818
Short name T1633
Test name
Test status
Simulation time 158758841 ps
CPU time 0.8 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:08:13 PM PDT 24
Peak memory 206900 kb
Host smart-de49874b-bcad-41f7-acc4-66fb79d383d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43956
2818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.439562818
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.3939516524
Short name T63
Test name
Test status
Simulation time 133386118 ps
CPU time 0.8 seconds
Started Jul 13 07:08:15 PM PDT 24
Finished Jul 13 07:08:16 PM PDT 24
Peak memory 206872 kb
Host smart-238f797c-a0d2-45ac-9dff-4c046a4ed872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39395
16524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.3939516524
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1692904842
Short name T734
Test name
Test status
Simulation time 165224171 ps
CPU time 0.8 seconds
Started Jul 13 07:08:12 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206856 kb
Host smart-07e7d389-ef84-429b-8d45-f85b8c8be2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16929
04842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1692904842
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.380110119
Short name T1449
Test name
Test status
Simulation time 343372650 ps
CPU time 1.21 seconds
Started Jul 13 07:08:11 PM PDT 24
Finished Jul 13 07:08:14 PM PDT 24
Peak memory 206872 kb
Host smart-78f6e32c-f01d-43ce-b6fb-0840020b8228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38011
0119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.380110119
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.367216416
Short name T1805
Test name
Test status
Simulation time 614891382 ps
CPU time 1.53 seconds
Started Jul 13 07:08:10 PM PDT 24
Finished Jul 13 07:08:13 PM PDT 24
Peak memory 206864 kb
Host smart-6aae6ae1-cc57-4bb8-83b2-f54ed27a2832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36721
6416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.367216416
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1294468180
Short name T2672
Test name
Test status
Simulation time 19534988819 ps
CPU time 36.99 seconds
Started Jul 13 07:08:10 PM PDT 24
Finished Jul 13 07:08:48 PM PDT 24
Peak memory 207080 kb
Host smart-cc959b0f-f765-4f3a-91bf-66440010c639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12944
68180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1294468180
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.555613035
Short name T1941
Test name
Test status
Simulation time 422259943 ps
CPU time 1.46 seconds
Started Jul 13 07:08:21 PM PDT 24
Finished Jul 13 07:08:23 PM PDT 24
Peak memory 206868 kb
Host smart-819d7e19-e345-455b-a3ce-ca5c5551aa15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55561
3035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.555613035
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3680116519
Short name T1401
Test name
Test status
Simulation time 183056852 ps
CPU time 0.87 seconds
Started Jul 13 07:08:21 PM PDT 24
Finished Jul 13 07:08:22 PM PDT 24
Peak memory 206868 kb
Host smart-8ae88cb9-9fc5-4819-982a-ceeb9c292e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36801
16519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3680116519
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3226353323
Short name T2579
Test name
Test status
Simulation time 41625492 ps
CPU time 0.66 seconds
Started Jul 13 07:08:20 PM PDT 24
Finished Jul 13 07:08:22 PM PDT 24
Peak memory 206864 kb
Host smart-aec7e890-180e-403f-8dc4-091e7d8c0ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32263
53323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3226353323
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.4221159496
Short name T299
Test name
Test status
Simulation time 788121921 ps
CPU time 1.84 seconds
Started Jul 13 07:08:20 PM PDT 24
Finished Jul 13 07:08:22 PM PDT 24
Peak memory 207008 kb
Host smart-65bd60e7-7bf2-4036-91dc-c2190119b528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42211
59496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.4221159496
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2643401939
Short name T956
Test name
Test status
Simulation time 286804525 ps
CPU time 1.72 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:08:25 PM PDT 24
Peak memory 206964 kb
Host smart-ab6709d0-2915-43ec-b17f-a085bf566efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26434
01939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2643401939
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.2960003502
Short name T1967
Test name
Test status
Simulation time 112202660142 ps
CPU time 173.28 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:11:16 PM PDT 24
Peak memory 207092 kb
Host smart-54e333ce-3154-4822-964f-265dacd833ec
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2960003502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.2960003502
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.2688472507
Short name T2315
Test name
Test status
Simulation time 115367194265 ps
CPU time 154.31 seconds
Started Jul 13 07:08:19 PM PDT 24
Finished Jul 13 07:10:53 PM PDT 24
Peak memory 207080 kb
Host smart-8452d120-e39d-4e42-9768-1fac933a34ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688472507 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.2688472507
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.2826700268
Short name T525
Test name
Test status
Simulation time 82141050600 ps
CPU time 136.22 seconds
Started Jul 13 07:08:17 PM PDT 24
Finished Jul 13 07:10:34 PM PDT 24
Peak memory 207072 kb
Host smart-4619faac-94c3-472e-ba17-d01050ceb952
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2826700268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2826700268
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1517747628
Short name T674
Test name
Test status
Simulation time 109167360194 ps
CPU time 143.35 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:10:46 PM PDT 24
Peak memory 207128 kb
Host smart-8defd6bf-abd4-41fe-b470-cd116629a629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517747628 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1517747628
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.892276021
Short name T1938
Test name
Test status
Simulation time 119136722717 ps
CPU time 150.33 seconds
Started Jul 13 07:08:19 PM PDT 24
Finished Jul 13 07:10:50 PM PDT 24
Peak memory 207024 kb
Host smart-566929d0-453e-4a9d-8e83-d7c50aa1595c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89227
6021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.892276021
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2519291414
Short name T1038
Test name
Test status
Simulation time 212845158 ps
CPU time 0.85 seconds
Started Jul 13 07:08:19 PM PDT 24
Finished Jul 13 07:08:20 PM PDT 24
Peak memory 206868 kb
Host smart-43accb5f-a747-40cd-8ecf-bfbfe6805c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25192
91414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2519291414
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.500872254
Short name T1239
Test name
Test status
Simulation time 206052596 ps
CPU time 0.81 seconds
Started Jul 13 07:08:24 PM PDT 24
Finished Jul 13 07:08:25 PM PDT 24
Peak memory 206844 kb
Host smart-2f0e1b02-f6bd-45f3-b624-a0510606c278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50087
2254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.500872254
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1060324982
Short name T1929
Test name
Test status
Simulation time 225799331 ps
CPU time 0.98 seconds
Started Jul 13 07:08:24 PM PDT 24
Finished Jul 13 07:08:26 PM PDT 24
Peak memory 206848 kb
Host smart-fec15c65-43eb-4381-a2c4-6ea312e388ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10603
24982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1060324982
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2863099284
Short name T1790
Test name
Test status
Simulation time 216002617 ps
CPU time 0.94 seconds
Started Jul 13 07:08:21 PM PDT 24
Finished Jul 13 07:08:23 PM PDT 24
Peak memory 206864 kb
Host smart-b61d890b-cd1f-4d93-bc0e-b0417d0925f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28630
99284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2863099284
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.2901579810
Short name T421
Test name
Test status
Simulation time 23378168886 ps
CPU time 22.99 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:08:46 PM PDT 24
Peak memory 206928 kb
Host smart-ed66f393-6a69-46b8-bf1d-eed36058e781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29015
79810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.2901579810
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2415080704
Short name T1590
Test name
Test status
Simulation time 3395165670 ps
CPU time 3.54 seconds
Started Jul 13 07:08:23 PM PDT 24
Finished Jul 13 07:08:27 PM PDT 24
Peak memory 206932 kb
Host smart-051e5e76-ac33-4496-9a85-6084033e2d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24150
80704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2415080704
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1317470418
Short name T2083
Test name
Test status
Simulation time 7298566982 ps
CPU time 205.19 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:11:48 PM PDT 24
Peak memory 207156 kb
Host smart-5fbce436-87b4-42c6-918b-8401c5e62be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13174
70418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1317470418
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2626232532
Short name T2067
Test name
Test status
Simulation time 4821640322 ps
CPU time 34.22 seconds
Started Jul 13 07:08:20 PM PDT 24
Finished Jul 13 07:08:55 PM PDT 24
Peak memory 207092 kb
Host smart-f2151c5a-6c7f-4698-93a8-8744026b9b8a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2626232532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2626232532
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.783860491
Short name T1903
Test name
Test status
Simulation time 263658606 ps
CPU time 0.95 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:08:23 PM PDT 24
Peak memory 206868 kb
Host smart-9ce58490-e90d-4f8b-ab37-e7269091712b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=783860491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.783860491
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1209298567
Short name T2718
Test name
Test status
Simulation time 190584028 ps
CPU time 0.94 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:08:23 PM PDT 24
Peak memory 207052 kb
Host smart-d1a8ccf9-498a-43e0-ab80-cf098a94f320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
98567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1209298567
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1330762614
Short name T879
Test name
Test status
Simulation time 4832667451 ps
CPU time 32.82 seconds
Started Jul 13 07:08:19 PM PDT 24
Finished Jul 13 07:08:52 PM PDT 24
Peak memory 207136 kb
Host smart-60beadae-e3dc-4a0a-9991-37a336223fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13307
62614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1330762614
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1438581355
Short name T2042
Test name
Test status
Simulation time 5391335304 ps
CPU time 146.08 seconds
Started Jul 13 07:08:20 PM PDT 24
Finished Jul 13 07:10:46 PM PDT 24
Peak memory 207088 kb
Host smart-470b843c-40a4-4061-a151-18c44c565b87
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1438581355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1438581355
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.691531679
Short name T2594
Test name
Test status
Simulation time 159333596 ps
CPU time 0.78 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:08:24 PM PDT 24
Peak memory 206868 kb
Host smart-816e5a63-68b1-4091-93c7-f31db8e5b208
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=691531679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.691531679
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3064926004
Short name T682
Test name
Test status
Simulation time 152670394 ps
CPU time 0.82 seconds
Started Jul 13 07:08:19 PM PDT 24
Finished Jul 13 07:08:20 PM PDT 24
Peak memory 206884 kb
Host smart-f9a4eb31-57dc-4a36-b56b-a4790d7df4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30649
26004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3064926004
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3002244951
Short name T108
Test name
Test status
Simulation time 199763216 ps
CPU time 0.85 seconds
Started Jul 13 07:08:21 PM PDT 24
Finished Jul 13 07:08:23 PM PDT 24
Peak memory 206864 kb
Host smart-e312c55d-fa80-46b4-b8d8-80926d156b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30022
44951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3002244951
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1588949535
Short name T1292
Test name
Test status
Simulation time 217418695 ps
CPU time 0.9 seconds
Started Jul 13 07:08:19 PM PDT 24
Finished Jul 13 07:08:21 PM PDT 24
Peak memory 206812 kb
Host smart-f55a5d73-48ef-4c21-b4d2-938d60efd773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15889
49535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1588949535
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3178688310
Short name T717
Test name
Test status
Simulation time 166520951 ps
CPU time 0.79 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:08:24 PM PDT 24
Peak memory 206852 kb
Host smart-c248dff8-a611-422d-b103-dfe68eb353a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31786
88310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3178688310
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2032914829
Short name T289
Test name
Test status
Simulation time 198930587 ps
CPU time 0.89 seconds
Started Jul 13 07:08:22 PM PDT 24
Finished Jul 13 07:08:24 PM PDT 24
Peak memory 206868 kb
Host smart-e6bd8f3e-3dce-4fd3-a349-e1abf0dacec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20329
14829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2032914829
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.4187494408
Short name T570
Test name
Test status
Simulation time 154053989 ps
CPU time 0.78 seconds
Started Jul 13 07:08:30 PM PDT 24
Finished Jul 13 07:08:31 PM PDT 24
Peak memory 206868 kb
Host smart-1e535be6-b3ba-4cbd-b9e6-428d87ea1458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
94408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.4187494408
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2300324582
Short name T1755
Test name
Test status
Simulation time 215375468 ps
CPU time 0.89 seconds
Started Jul 13 07:08:28 PM PDT 24
Finished Jul 13 07:08:29 PM PDT 24
Peak memory 206848 kb
Host smart-c5026743-d8be-4ee9-891d-0b1a455406e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2300324582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2300324582
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.2240050459
Short name T179
Test name
Test status
Simulation time 250353821 ps
CPU time 0.93 seconds
Started Jul 13 07:08:31 PM PDT 24
Finished Jul 13 07:08:32 PM PDT 24
Peak memory 206872 kb
Host smart-320516c0-a698-4f6f-ac4d-59a6a5b2637a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22400
50459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.2240050459
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2407746925
Short name T963
Test name
Test status
Simulation time 162540717 ps
CPU time 0.8 seconds
Started Jul 13 07:08:29 PM PDT 24
Finished Jul 13 07:08:30 PM PDT 24
Peak memory 206880 kb
Host smart-5d191b26-c235-4c02-b504-997ca3d6bdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24077
46925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2407746925
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.910943827
Short name T1856
Test name
Test status
Simulation time 117207242 ps
CPU time 0.69 seconds
Started Jul 13 07:08:26 PM PDT 24
Finished Jul 13 07:08:27 PM PDT 24
Peak memory 206864 kb
Host smart-823f8ed1-bccb-40e1-91e7-a493416e8b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91094
3827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.910943827
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3344185471
Short name T1459
Test name
Test status
Simulation time 9568359108 ps
CPU time 22.16 seconds
Started Jul 13 07:08:30 PM PDT 24
Finished Jul 13 07:08:52 PM PDT 24
Peak memory 207112 kb
Host smart-03bfbf99-7634-4eaa-a5bb-520cc599b878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33441
85471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3344185471
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.401829296
Short name T2295
Test name
Test status
Simulation time 173400615 ps
CPU time 0.83 seconds
Started Jul 13 07:08:28 PM PDT 24
Finished Jul 13 07:08:29 PM PDT 24
Peak memory 206860 kb
Host smart-9f595f8c-5664-4ea2-bc46-4ac325a4aec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40182
9296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.401829296
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.450879579
Short name T1509
Test name
Test status
Simulation time 211527296 ps
CPU time 0.91 seconds
Started Jul 13 07:08:33 PM PDT 24
Finished Jul 13 07:08:34 PM PDT 24
Peak memory 206864 kb
Host smart-def9ddfb-9026-4ad8-b334-30aa784f38b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45087
9579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.450879579
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.402033445
Short name T148
Test name
Test status
Simulation time 13058346841 ps
CPU time 352.79 seconds
Started Jul 13 07:08:33 PM PDT 24
Finished Jul 13 07:14:26 PM PDT 24
Peak memory 207132 kb
Host smart-e3b63c41-20f2-45e7-9a31-5ed3566ef774
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=402033445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.402033445
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.707221604
Short name T161
Test name
Test status
Simulation time 14945939822 ps
CPU time 411.65 seconds
Started Jul 13 07:08:31 PM PDT 24
Finished Jul 13 07:15:23 PM PDT 24
Peak memory 207140 kb
Host smart-b9fb948e-dac7-4218-b087-bfd94923f411
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=707221604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.707221604
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.1251787907
Short name T170
Test name
Test status
Simulation time 12891625638 ps
CPU time 69.9 seconds
Started Jul 13 07:08:28 PM PDT 24
Finished Jul 13 07:09:38 PM PDT 24
Peak memory 207060 kb
Host smart-03998919-6041-481f-af46-b21e0a9f13c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1251787907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1251787907
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3569506349
Short name T407
Test name
Test status
Simulation time 215254296 ps
CPU time 0.88 seconds
Started Jul 13 07:08:30 PM PDT 24
Finished Jul 13 07:08:32 PM PDT 24
Peak memory 206872 kb
Host smart-be8fcfb1-8cc7-4ae1-883c-c47c582bd02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35695
06349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3569506349
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.833461905
Short name T1194
Test name
Test status
Simulation time 225948287 ps
CPU time 0.96 seconds
Started Jul 13 07:08:28 PM PDT 24
Finished Jul 13 07:08:30 PM PDT 24
Peak memory 206812 kb
Host smart-2ba79e8f-eefe-4c16-bca7-13a4f869d5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83346
1905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.833461905
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3859774045
Short name T576
Test name
Test status
Simulation time 160669074 ps
CPU time 0.8 seconds
Started Jul 13 07:08:27 PM PDT 24
Finished Jul 13 07:08:28 PM PDT 24
Peak memory 206864 kb
Host smart-db82b105-e02a-4472-8b1f-2073d100fd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
74045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3859774045
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.4143894698
Short name T74
Test name
Test status
Simulation time 184745913 ps
CPU time 0.8 seconds
Started Jul 13 07:08:38 PM PDT 24
Finished Jul 13 07:08:40 PM PDT 24
Peak memory 206868 kb
Host smart-6046adbc-b961-4b79-a6d6-bf47f0a95e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41438
94698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.4143894698
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2435929496
Short name T191
Test name
Test status
Simulation time 558657210 ps
CPU time 1.5 seconds
Started Jul 13 07:08:40 PM PDT 24
Finished Jul 13 07:08:43 PM PDT 24
Peak memory 225608 kb
Host smart-49289af0-1521-4f5f-abe9-4119f602a0ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2435929496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2435929496
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3334015357
Short name T51
Test name
Test status
Simulation time 379015050 ps
CPU time 1.27 seconds
Started Jul 13 07:08:37 PM PDT 24
Finished Jul 13 07:08:40 PM PDT 24
Peak memory 206876 kb
Host smart-f4152558-225c-42ca-ac68-9404891b52e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
15357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3334015357
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3349422080
Short name T1098
Test name
Test status
Simulation time 297081881 ps
CPU time 0.99 seconds
Started Jul 13 07:08:38 PM PDT 24
Finished Jul 13 07:08:41 PM PDT 24
Peak memory 206900 kb
Host smart-c53a9bfb-9e9b-4bb6-b455-01ad513addd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33494
22080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3349422080
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.120657934
Short name T555
Test name
Test status
Simulation time 182610266 ps
CPU time 0.83 seconds
Started Jul 13 07:08:39 PM PDT 24
Finished Jul 13 07:08:42 PM PDT 24
Peak memory 206800 kb
Host smart-6112d111-738b-4842-af7d-012a1ca374b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12065
7934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.120657934
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1495697553
Short name T2430
Test name
Test status
Simulation time 163389451 ps
CPU time 0.77 seconds
Started Jul 13 07:08:38 PM PDT 24
Finished Jul 13 07:08:41 PM PDT 24
Peak memory 206876 kb
Host smart-fb57f4d0-e173-4457-9a25-5279e9c043c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14956
97553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1495697553
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4043916803
Short name T326
Test name
Test status
Simulation time 240304021 ps
CPU time 0.96 seconds
Started Jul 13 07:08:37 PM PDT 24
Finished Jul 13 07:08:40 PM PDT 24
Peak memory 206864 kb
Host smart-8e9ddece-ac0d-4c22-9f66-36859294949e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439
16803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4043916803
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3166244312
Short name T512
Test name
Test status
Simulation time 3915808277 ps
CPU time 35.95 seconds
Started Jul 13 07:08:37 PM PDT 24
Finished Jul 13 07:09:13 PM PDT 24
Peak memory 207032 kb
Host smart-6bce7e89-51e9-4caa-9581-4bbef1929eec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3166244312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3166244312
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.675298195
Short name T629
Test name
Test status
Simulation time 210059729 ps
CPU time 0.85 seconds
Started Jul 13 07:08:39 PM PDT 24
Finished Jul 13 07:08:42 PM PDT 24
Peak memory 206872 kb
Host smart-6ac9c745-3ad1-4ee9-8cc0-a7abf5de0e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67529
8195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.675298195
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.259651335
Short name T324
Test name
Test status
Simulation time 169957377 ps
CPU time 0.81 seconds
Started Jul 13 07:08:38 PM PDT 24
Finished Jul 13 07:08:41 PM PDT 24
Peak memory 206876 kb
Host smart-c0331d01-0726-45c8-896f-e1337badbc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25965
1335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.259651335
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.3118278314
Short name T1582
Test name
Test status
Simulation time 638440961 ps
CPU time 1.63 seconds
Started Jul 13 07:08:38 PM PDT 24
Finished Jul 13 07:08:41 PM PDT 24
Peak memory 206756 kb
Host smart-06fceb1f-baa2-4381-b032-8a3da34eb04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31182
78314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.3118278314
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1718204752
Short name T360
Test name
Test status
Simulation time 5438822173 ps
CPU time 53.73 seconds
Started Jul 13 07:08:39 PM PDT 24
Finished Jul 13 07:09:34 PM PDT 24
Peak memory 207012 kb
Host smart-0b13c588-1f03-4cc7-875f-5de2fd302fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17182
04752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1718204752
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2924363448
Short name T2008
Test name
Test status
Simulation time 19794388253 ps
CPU time 108.42 seconds
Started Jul 13 07:08:39 PM PDT 24
Finished Jul 13 07:10:29 PM PDT 24
Peak memory 207160 kb
Host smart-d3d2bf64-cd0c-48c0-ad5b-181823811962
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2924363448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2924363448
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3294366658
Short name T1520
Test name
Test status
Simulation time 80035412 ps
CPU time 0.72 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:06 PM PDT 24
Peak memory 206908 kb
Host smart-73bd80ad-eaa1-4000-acef-6fd622bfe7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3294366658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3294366658
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.4243208919
Short name T1741
Test name
Test status
Simulation time 3945129158 ps
CPU time 4.43 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:12:57 PM PDT 24
Peak memory 206936 kb
Host smart-3784fdf5-f3b6-4946-998f-3827b3390f00
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4243208919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.4243208919
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3275627939
Short name T1236
Test name
Test status
Simulation time 23391821611 ps
CPU time 23.31 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 207136 kb
Host smart-2a1b2533-edd7-467a-8486-b136834f43cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3275627939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3275627939
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.826337821
Short name T995
Test name
Test status
Simulation time 146408302 ps
CPU time 0.77 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:51 PM PDT 24
Peak memory 206860 kb
Host smart-c542f773-1b23-4a86-a941-e0b89230c324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82633
7821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.826337821
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1435078870
Short name T452
Test name
Test status
Simulation time 149819479 ps
CPU time 0.78 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:52 PM PDT 24
Peak memory 206804 kb
Host smart-db3854d5-a803-4c34-87be-91770a0dc3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14350
78870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1435078870
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2827293758
Short name T1618
Test name
Test status
Simulation time 266629240 ps
CPU time 0.97 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:51 PM PDT 24
Peak memory 206856 kb
Host smart-77de8228-c52b-4d0b-925d-32d7c0de0301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28272
93758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2827293758
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2682098168
Short name T1121
Test name
Test status
Simulation time 1103282136 ps
CPU time 2.56 seconds
Started Jul 13 07:12:53 PM PDT 24
Finished Jul 13 07:13:00 PM PDT 24
Peak memory 206992 kb
Host smart-6e536392-d84f-4c4e-81d2-f85a81cd7297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26820
98168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2682098168
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2176054251
Short name T735
Test name
Test status
Simulation time 20977303889 ps
CPU time 37.4 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:13:30 PM PDT 24
Peak memory 207128 kb
Host smart-a79e404a-d6ed-4a0f-8a00-008a2b4ae0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21760
54251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2176054251
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1795158027
Short name T1440
Test name
Test status
Simulation time 332514534 ps
CPU time 1.1 seconds
Started Jul 13 07:12:49 PM PDT 24
Finished Jul 13 07:12:51 PM PDT 24
Peak memory 206856 kb
Host smart-17e37c51-3792-4695-9fc5-fa987dec7b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17951
58027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1795158027
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3575202103
Short name T1547
Test name
Test status
Simulation time 159555495 ps
CPU time 0.76 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:53 PM PDT 24
Peak memory 206900 kb
Host smart-6f60f3ca-921a-4ced-96e3-ea467841c919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35752
02103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3575202103
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.2465805851
Short name T579
Test name
Test status
Simulation time 36692092 ps
CPU time 0.65 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:01 PM PDT 24
Peak memory 206852 kb
Host smart-f17a0a68-0d78-44da-bdba-721f6719d758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24658
05851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2465805851
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3466644744
Short name T2559
Test name
Test status
Simulation time 884811671 ps
CPU time 1.99 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:53 PM PDT 24
Peak memory 207172 kb
Host smart-e46bec9a-0e47-48ae-b32f-febb2773dcc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34666
44744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3466644744
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.4221376865
Short name T342
Test name
Test status
Simulation time 153685993 ps
CPU time 1.26 seconds
Started Jul 13 07:12:52 PM PDT 24
Finished Jul 13 07:12:55 PM PDT 24
Peak memory 206996 kb
Host smart-280152e6-d49f-46ca-bc63-9e21e7b951ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42213
76865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.4221376865
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3531920728
Short name T1849
Test name
Test status
Simulation time 248797161 ps
CPU time 0.92 seconds
Started Jul 13 07:12:54 PM PDT 24
Finished Jul 13 07:12:58 PM PDT 24
Peak memory 206828 kb
Host smart-143834b5-a79d-40cf-a11d-d5f8aa641916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35319
20728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3531920728
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4292794830
Short name T968
Test name
Test status
Simulation time 187555461 ps
CPU time 0.8 seconds
Started Jul 13 07:12:54 PM PDT 24
Finished Jul 13 07:12:58 PM PDT 24
Peak memory 206808 kb
Host smart-b108bb1f-57f1-458e-a1ab-701ab5964e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42927
94830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4292794830
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.869180132
Short name T751
Test name
Test status
Simulation time 232219505 ps
CPU time 0.96 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:02 PM PDT 24
Peak memory 206748 kb
Host smart-0e67b3c3-8d5e-4946-8ae8-be23faa9a246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86918
0132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.869180132
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2772336982
Short name T1280
Test name
Test status
Simulation time 4868459075 ps
CPU time 38.62 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:13:30 PM PDT 24
Peak memory 207132 kb
Host smart-b4d5f9f9-7cc6-407b-b8a4-2d3c7bf68f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27723
36982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2772336982
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1464071038
Short name T2307
Test name
Test status
Simulation time 232204267 ps
CPU time 0.92 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:12:54 PM PDT 24
Peak memory 206896 kb
Host smart-205e6291-aa87-4761-ae44-f68c134ddf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14640
71038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1464071038
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1799717235
Short name T2270
Test name
Test status
Simulation time 23317925516 ps
CPU time 23.19 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:13:15 PM PDT 24
Peak memory 206936 kb
Host smart-f010aa2d-455c-4131-936e-20a416447b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17997
17235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1799717235
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.4146415265
Short name T718
Test name
Test status
Simulation time 3323742862 ps
CPU time 3.7 seconds
Started Jul 13 07:12:51 PM PDT 24
Finished Jul 13 07:12:56 PM PDT 24
Peak memory 206964 kb
Host smart-4d1de1fc-81ad-4704-a909-8e9f9fdcd5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
15265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.4146415265
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.1955931974
Short name T999
Test name
Test status
Simulation time 8103673915 ps
CPU time 223.27 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 207060 kb
Host smart-29b1d36d-ce02-4660-8fc1-51ac5b64afcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19559
31974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1955931974
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2884885097
Short name T21
Test name
Test status
Simulation time 7062082866 ps
CPU time 200.6 seconds
Started Jul 13 07:12:53 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 207004 kb
Host smart-c90181c7-016c-4822-ae94-ec42ffb5ae8a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2884885097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2884885097
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.689472259
Short name T2215
Test name
Test status
Simulation time 240275321 ps
CPU time 0.92 seconds
Started Jul 13 07:12:52 PM PDT 24
Finished Jul 13 07:12:55 PM PDT 24
Peak memory 206816 kb
Host smart-b9739e02-59fa-4a21-a890-3d6080c21f2c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=689472259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.689472259
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2901053638
Short name T1719
Test name
Test status
Simulation time 189986646 ps
CPU time 0.82 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:12:52 PM PDT 24
Peak memory 206864 kb
Host smart-00cb8cc2-c3a5-4a2d-8ed8-1cc85a99d4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29010
53638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2901053638
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.1162638991
Short name T1278
Test name
Test status
Simulation time 3864278853 ps
CPU time 108.25 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 207072 kb
Host smart-14a9c205-7552-4cac-931e-2965b30c47a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11626
38991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.1162638991
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2363981174
Short name T446
Test name
Test status
Simulation time 3573985176 ps
CPU time 24.55 seconds
Started Jul 13 07:12:50 PM PDT 24
Finished Jul 13 07:13:15 PM PDT 24
Peak memory 207140 kb
Host smart-b1bb6d13-088f-4662-9721-575cb28c5202
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2363981174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2363981174
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3766391950
Short name T2278
Test name
Test status
Simulation time 159997528 ps
CPU time 0.84 seconds
Started Jul 13 07:12:53 PM PDT 24
Finished Jul 13 07:12:56 PM PDT 24
Peak memory 207080 kb
Host smart-95bb05f9-fcff-4dc4-8fa9-601128cd5c50
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3766391950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3766391950
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2698246562
Short name T1884
Test name
Test status
Simulation time 212128418 ps
CPU time 0.92 seconds
Started Jul 13 07:12:53 PM PDT 24
Finished Jul 13 07:12:56 PM PDT 24
Peak memory 206868 kb
Host smart-68f92e10-75a0-4fcd-a6d1-a66cf874e989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26982
46562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2698246562
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1688201575
Short name T2075
Test name
Test status
Simulation time 231392034 ps
CPU time 1.01 seconds
Started Jul 13 07:12:55 PM PDT 24
Finished Jul 13 07:12:59 PM PDT 24
Peak memory 206880 kb
Host smart-99029b23-9b97-4561-8e3d-2956c7aee606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
01575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1688201575
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2221600993
Short name T1822
Test name
Test status
Simulation time 165548558 ps
CPU time 0.83 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:06 PM PDT 24
Peak memory 206856 kb
Host smart-fdab5084-82a2-4d8e-8a1f-da67d16c7d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22216
00993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2221600993
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3432393848
Short name T932
Test name
Test status
Simulation time 175167182 ps
CPU time 0.79 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:01 PM PDT 24
Peak memory 206864 kb
Host smart-382ae2f4-c46f-4b22-be8b-9b17da6667b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34323
93848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3432393848
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2185645451
Short name T2060
Test name
Test status
Simulation time 226474322 ps
CPU time 0.82 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 206876 kb
Host smart-83b3678d-a870-4f05-9d3c-e3b7e18f6da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21856
45451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2185645451
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2285773353
Short name T1502
Test name
Test status
Simulation time 168826365 ps
CPU time 0.87 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:02 PM PDT 24
Peak memory 206872 kb
Host smart-2439ad87-e9e1-4841-b764-c8c77d2f14d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22857
73353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2285773353
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1988945684
Short name T1889
Test name
Test status
Simulation time 214437732 ps
CPU time 0.87 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 206848 kb
Host smart-074debf3-733d-4851-bb73-5d955cf6191a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1988945684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1988945684
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1484262343
Short name T400
Test name
Test status
Simulation time 164944579 ps
CPU time 0.83 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:03 PM PDT 24
Peak memory 206868 kb
Host smart-c436e0db-dace-4fe1-a92e-9611265ead8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842
62343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1484262343
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.4163969160
Short name T1640
Test name
Test status
Simulation time 37158080 ps
CPU time 0.67 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 206884 kb
Host smart-eb547d8e-c684-4398-8bfa-9669b29d1d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41639
69160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.4163969160
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1688544176
Short name T1628
Test name
Test status
Simulation time 13309142497 ps
CPU time 27.59 seconds
Started Jul 13 07:12:58 PM PDT 24
Finished Jul 13 07:13:27 PM PDT 24
Peak memory 207104 kb
Host smart-d13ba8a5-3123-46af-b65b-f79c54229a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16885
44176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1688544176
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.4017971176
Short name T1589
Test name
Test status
Simulation time 166275195 ps
CPU time 0.85 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:03 PM PDT 24
Peak memory 206868 kb
Host smart-bce8d3be-608b-4465-88d4-7935d46dc382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40179
71176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.4017971176
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1768337162
Short name T2695
Test name
Test status
Simulation time 239680737 ps
CPU time 0.89 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:02 PM PDT 24
Peak memory 206860 kb
Host smart-863818e6-012c-4480-80f7-04421bd85d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17683
37162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1768337162
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.273167555
Short name T864
Test name
Test status
Simulation time 167739893 ps
CPU time 0.83 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:01 PM PDT 24
Peak memory 206880 kb
Host smart-139f3caa-bece-467f-aec1-9cb56a5bb8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27316
7555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.273167555
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.838727731
Short name T817
Test name
Test status
Simulation time 147011870 ps
CPU time 0.82 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:06 PM PDT 24
Peak memory 206852 kb
Host smart-bf03ac5b-14c8-499a-9edb-a4d4acbad97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83872
7731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.838727731
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2633169252
Short name T71
Test name
Test status
Simulation time 165374761 ps
CPU time 0.83 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:01 PM PDT 24
Peak memory 206864 kb
Host smart-49050496-2421-460f-af90-eed81e333e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26331
69252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2633169252
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1034509827
Short name T424
Test name
Test status
Simulation time 176090684 ps
CPU time 0.81 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 206872 kb
Host smart-84f77358-8cc8-4c19-8be5-0baf3d38928e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10345
09827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1034509827
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1118587298
Short name T2480
Test name
Test status
Simulation time 154509572 ps
CPU time 0.82 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 206820 kb
Host smart-05797e5d-7686-41c6-a59e-8548cb7ba05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11185
87298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1118587298
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.613214844
Short name T1433
Test name
Test status
Simulation time 224615422 ps
CPU time 0.99 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 206884 kb
Host smart-6b9453ed-7170-4493-9acd-f140aae44373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61321
4844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.613214844
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1889321162
Short name T2454
Test name
Test status
Simulation time 5660699925 ps
CPU time 162.18 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:15:46 PM PDT 24
Peak memory 207072 kb
Host smart-231666c9-f925-45d1-8a03-9907b69589db
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1889321162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1889321162
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2279467001
Short name T1842
Test name
Test status
Simulation time 202830593 ps
CPU time 0.89 seconds
Started Jul 13 07:12:57 PM PDT 24
Finished Jul 13 07:12:59 PM PDT 24
Peak memory 206816 kb
Host smart-ae17d310-0808-4531-b21b-e15902dbdac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22794
67001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2279467001
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1690285920
Short name T1895
Test name
Test status
Simulation time 199669380 ps
CPU time 0.81 seconds
Started Jul 13 07:12:57 PM PDT 24
Finished Jul 13 07:12:59 PM PDT 24
Peak memory 206864 kb
Host smart-5b9fd027-c668-4993-8007-7c87220786fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16902
85920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1690285920
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.3336080018
Short name T1566
Test name
Test status
Simulation time 1084503369 ps
CPU time 2.22 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 207084 kb
Host smart-1df8c8b2-36eb-4c69-a2d2-49d8c9193628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
80018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.3336080018
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.61120123
Short name T2598
Test name
Test status
Simulation time 6287686408 ps
CPU time 175.82 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 207072 kb
Host smart-aae6e6cf-91cd-4700-97c9-d3474ed66835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61120
123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.61120123
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.811483884
Short name T2290
Test name
Test status
Simulation time 53901028 ps
CPU time 0.69 seconds
Started Jul 13 07:13:08 PM PDT 24
Finished Jul 13 07:13:10 PM PDT 24
Peak memory 206920 kb
Host smart-ed9f4219-3c75-41d5-9cf0-c9edc797597b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=811483884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.811483884
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.4189541556
Short name T1384
Test name
Test status
Simulation time 3539430173 ps
CPU time 3.95 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:08 PM PDT 24
Peak memory 206948 kb
Host smart-72af91a8-5999-4c1c-a245-0d0f9cad304d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4189541556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.4189541556
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3698761556
Short name T640
Test name
Test status
Simulation time 13499642012 ps
CPU time 13.6 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:18 PM PDT 24
Peak memory 207136 kb
Host smart-ea9bc224-db42-4c8d-bd64-17d4150744bd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3698761556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3698761556
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2687188887
Short name T7
Test name
Test status
Simulation time 23395810580 ps
CPU time 21.37 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:25 PM PDT 24
Peak memory 207068 kb
Host smart-240eccae-65c6-498d-92f5-010bc2986c82
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2687188887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2687188887
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3629137229
Short name T1240
Test name
Test status
Simulation time 151894970 ps
CPU time 0.85 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 206888 kb
Host smart-3797712a-4bc6-4faa-9695-796e97f10253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36291
37229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3629137229
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.44612803
Short name T1258
Test name
Test status
Simulation time 146607473 ps
CPU time 0.82 seconds
Started Jul 13 07:12:58 PM PDT 24
Finished Jul 13 07:13:00 PM PDT 24
Peak memory 206880 kb
Host smart-fb6c9b93-3a8b-4527-9f04-4b52ba1a2d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44612
803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.44612803
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1839303886
Short name T2121
Test name
Test status
Simulation time 224837727 ps
CPU time 0.94 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:06 PM PDT 24
Peak memory 206864 kb
Host smart-a07193de-27f2-4484-8220-f8f1dd32ae7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18393
03886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1839303886
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2952528199
Short name T388
Test name
Test status
Simulation time 526371725 ps
CPU time 1.38 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 207048 kb
Host smart-2dc7c758-5fc8-4f85-bc9b-661ecc20696c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29525
28199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2952528199
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3760071625
Short name T1670
Test name
Test status
Simulation time 10876199908 ps
CPU time 22.85 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:27 PM PDT 24
Peak memory 207088 kb
Host smart-b199d908-d004-4b82-94c8-5d8c5277a933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37600
71625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3760071625
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1993359156
Short name T2620
Test name
Test status
Simulation time 436939508 ps
CPU time 1.32 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 206860 kb
Host smart-980a990e-d4a7-4645-bda8-f07babfa3aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19933
59156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1993359156
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1263060434
Short name T443
Test name
Test status
Simulation time 155284896 ps
CPU time 0.79 seconds
Started Jul 13 07:12:58 PM PDT 24
Finished Jul 13 07:13:00 PM PDT 24
Peak memory 206876 kb
Host smart-7de4ee3a-e800-4f76-9388-e52779356580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12630
60434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1263060434
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3035672864
Short name T389
Test name
Test status
Simulation time 38700641 ps
CPU time 0.69 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:06 PM PDT 24
Peak memory 207096 kb
Host smart-8846fa17-7f68-4b0b-8e3c-8259584a9c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30356
72864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3035672864
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1709220826
Short name T1801
Test name
Test status
Simulation time 902329991 ps
CPU time 2.31 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 207096 kb
Host smart-759f34bd-379d-49ab-b20a-f675dc25fe74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092
20826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1709220826
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2744905129
Short name T880
Test name
Test status
Simulation time 346441213 ps
CPU time 2.15 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:03 PM PDT 24
Peak memory 206892 kb
Host smart-217afacd-c451-43f7-b745-6e67070f92a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27449
05129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2744905129
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.647015992
Short name T1982
Test name
Test status
Simulation time 203496210 ps
CPU time 0.86 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 206864 kb
Host smart-604c7c0e-e015-4d04-a6db-4b23959984d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64701
5992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.647015992
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1773611422
Short name T909
Test name
Test status
Simulation time 140594432 ps
CPU time 0.8 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 206880 kb
Host smart-8b3894d9-102f-4349-ad6c-9664d3ea0460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17736
11422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1773611422
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.4050875612
Short name T1095
Test name
Test status
Simulation time 195962598 ps
CPU time 0.94 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:06 PM PDT 24
Peak memory 206848 kb
Host smart-ac54b307-7e7a-41fa-9f6c-aa1f01d7c334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40508
75612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.4050875612
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.556966505
Short name T855
Test name
Test status
Simulation time 4983428640 ps
CPU time 144.05 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 207076 kb
Host smart-eebdf5d9-cf03-4ce5-a1d1-a101b7558f38
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=556966505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.556966505
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.1328566310
Short name T2111
Test name
Test status
Simulation time 6996649421 ps
CPU time 60.3 seconds
Started Jul 13 07:13:03 PM PDT 24
Finished Jul 13 07:14:06 PM PDT 24
Peak memory 207136 kb
Host smart-1f505a40-6e9f-455d-9339-004d10fd645d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13285
66310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1328566310
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1554337826
Short name T2282
Test name
Test status
Simulation time 220918876 ps
CPU time 0.92 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:06 PM PDT 24
Peak memory 206852 kb
Host smart-71320abf-6a33-4622-917d-155e1081c3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15543
37826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1554337826
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2260837774
Short name T38
Test name
Test status
Simulation time 23355896589 ps
CPU time 23.4 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:26 PM PDT 24
Peak memory 206940 kb
Host smart-ef30023e-ff37-4ada-86ba-86ee252c88bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22608
37774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2260837774
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1798362337
Short name T681
Test name
Test status
Simulation time 3341966234 ps
CPU time 3.56 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:09 PM PDT 24
Peak memory 206920 kb
Host smart-3cdbe7a9-659e-4abf-ae31-1d1eb258e1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17983
62337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1798362337
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.3360291492
Short name T2727
Test name
Test status
Simulation time 12057638228 ps
CPU time 121.05 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:15:03 PM PDT 24
Peak memory 207136 kb
Host smart-436b1336-2969-411a-8eb0-1929f1fcf306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33602
91492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.3360291492
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3890854895
Short name T1794
Test name
Test status
Simulation time 6959534216 ps
CPU time 191.85 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:16:15 PM PDT 24
Peak memory 207120 kb
Host smart-f8641855-ff55-43fd-b25b-af8383ab32ef
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3890854895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3890854895
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2605366676
Short name T2618
Test name
Test status
Simulation time 245363752 ps
CPU time 0.95 seconds
Started Jul 13 07:13:02 PM PDT 24
Finished Jul 13 07:13:06 PM PDT 24
Peak memory 206860 kb
Host smart-e397b7bc-6bfd-4885-8241-533e148e8e0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2605366676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2605366676
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1267402106
Short name T285
Test name
Test status
Simulation time 253669947 ps
CPU time 0.95 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:03 PM PDT 24
Peak memory 206896 kb
Host smart-56926385-63c8-4944-a334-7bff25152167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
02106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1267402106
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2778673859
Short name T738
Test name
Test status
Simulation time 5598472949 ps
CPU time 52.13 seconds
Started Jul 13 07:12:59 PM PDT 24
Finished Jul 13 07:13:53 PM PDT 24
Peak memory 207028 kb
Host smart-d381f772-e1ae-47f5-a946-f75e19acc6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
73859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2778673859
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3999270174
Short name T504
Test name
Test status
Simulation time 3773487402 ps
CPU time 38.5 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:42 PM PDT 24
Peak memory 207072 kb
Host smart-b4c9fe55-23f6-4768-9122-bcfddb88da27
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3999270174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3999270174
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2599322458
Short name T2615
Test name
Test status
Simulation time 156978146 ps
CPU time 0.81 seconds
Started Jul 13 07:13:01 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 206876 kb
Host smart-51f25299-2fe6-4519-9374-3a2f17798bab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2599322458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2599322458
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1870072965
Short name T1315
Test name
Test status
Simulation time 166019674 ps
CPU time 0.85 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 206904 kb
Host smart-b0273051-41d7-4574-9b79-8bea376fe68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18700
72965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1870072965
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3633740152
Short name T1167
Test name
Test status
Simulation time 150761838 ps
CPU time 0.83 seconds
Started Jul 13 07:13:00 PM PDT 24
Finished Jul 13 07:13:04 PM PDT 24
Peak memory 206848 kb
Host smart-76e31b36-a56c-449d-9c41-2615926b992f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36337
40152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3633740152
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.4096154200
Short name T2249
Test name
Test status
Simulation time 141111789 ps
CPU time 0.75 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:11 PM PDT 24
Peak memory 206860 kb
Host smart-25e8e450-7cf9-4d23-a661-a17c60771e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40961
54200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.4096154200
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.483134959
Short name T1229
Test name
Test status
Simulation time 169851433 ps
CPU time 0.82 seconds
Started Jul 13 07:13:14 PM PDT 24
Finished Jul 13 07:13:17 PM PDT 24
Peak memory 206848 kb
Host smart-78c1b585-dc3a-4ed0-9051-13e66b204c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48313
4959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.483134959
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3645070198
Short name T2560
Test name
Test status
Simulation time 165666794 ps
CPU time 0.78 seconds
Started Jul 13 07:13:07 PM PDT 24
Finished Jul 13 07:13:08 PM PDT 24
Peak memory 206884 kb
Host smart-f430b981-76d9-4b60-ad70-42a2c78307c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36450
70198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3645070198
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3472449960
Short name T586
Test name
Test status
Simulation time 227122898 ps
CPU time 0.94 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206732 kb
Host smart-e2b8a875-16d4-4f39-be4e-07b4da3ae32a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3472449960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3472449960
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2156455475
Short name T1754
Test name
Test status
Simulation time 155507940 ps
CPU time 0.77 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:12 PM PDT 24
Peak memory 206800 kb
Host smart-97fa05a0-4ee0-42ed-b15f-b8b2f239d5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21564
55475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2156455475
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1415435891
Short name T1508
Test name
Test status
Simulation time 39771715 ps
CPU time 0.66 seconds
Started Jul 13 07:13:13 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206880 kb
Host smart-cb9fb4a8-aafa-43f8-9070-2b4256950444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154
35891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1415435891
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3165715093
Short name T1250
Test name
Test status
Simulation time 17489471885 ps
CPU time 40.62 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:53 PM PDT 24
Peak memory 207116 kb
Host smart-3bca33c2-9b30-4b13-aa64-91ca075fa21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31657
15093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3165715093
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.414873608
Short name T1129
Test name
Test status
Simulation time 178425196 ps
CPU time 0.87 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:13 PM PDT 24
Peak memory 206844 kb
Host smart-4291d6d7-e93d-422f-8e0b-41721d4910ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
3608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.414873608
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1555397922
Short name T1026
Test name
Test status
Simulation time 240333715 ps
CPU time 0.87 seconds
Started Jul 13 07:13:13 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206844 kb
Host smart-908545de-507f-44e3-9d55-0b75acc1b323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15553
97922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1555397922
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3779461317
Short name T471
Test name
Test status
Simulation time 232235865 ps
CPU time 0.85 seconds
Started Jul 13 07:13:11 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206904 kb
Host smart-00db8cf5-dc3c-4b4d-9bb3-821840ff34ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37794
61317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3779461317
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.873441704
Short name T1196
Test name
Test status
Simulation time 152360832 ps
CPU time 0.82 seconds
Started Jul 13 07:13:08 PM PDT 24
Finished Jul 13 07:13:09 PM PDT 24
Peak memory 206876 kb
Host smart-6713c356-6613-4852-be04-d3ddc2db8d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87344
1704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.873441704
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3102088623
Short name T2087
Test name
Test status
Simulation time 168781237 ps
CPU time 0.81 seconds
Started Jul 13 07:13:12 PM PDT 24
Finished Jul 13 07:13:15 PM PDT 24
Peak memory 207104 kb
Host smart-a60d0109-7b26-47ef-9355-c4fe2bcdc292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31020
88623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3102088623
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3944914649
Short name T661
Test name
Test status
Simulation time 148575503 ps
CPU time 0.77 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:11 PM PDT 24
Peak memory 206864 kb
Host smart-6e862fc9-3fd2-4fbd-8e81-33f2fbb456ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39449
14649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3944914649
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.178573998
Short name T1374
Test name
Test status
Simulation time 160872071 ps
CPU time 0.77 seconds
Started Jul 13 07:13:11 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206896 kb
Host smart-23d239a3-a8ae-4906-a5d6-417fbfd2c0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17857
3998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.178573998
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2129764969
Short name T1276
Test name
Test status
Simulation time 195001472 ps
CPU time 0.85 seconds
Started Jul 13 07:13:12 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206848 kb
Host smart-040e7175-8b8e-4795-83da-c2ec2e0810be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297
64969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2129764969
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1014710786
Short name T530
Test name
Test status
Simulation time 6837772778 ps
CPU time 64.89 seconds
Started Jul 13 07:13:12 PM PDT 24
Finished Jul 13 07:14:19 PM PDT 24
Peak memory 207108 kb
Host smart-b39b710a-9df3-434f-a992-21aea2bb6cfb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1014710786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1014710786
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2893982913
Short name T20
Test name
Test status
Simulation time 159497779 ps
CPU time 0.82 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:11 PM PDT 24
Peak memory 206868 kb
Host smart-194b9286-7f67-4b93-8491-f382024fda7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28939
82913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2893982913
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.506977668
Short name T554
Test name
Test status
Simulation time 182141534 ps
CPU time 0.8 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:12 PM PDT 24
Peak memory 206884 kb
Host smart-deff5099-b156-4118-8dee-11a4b4cf69da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50697
7668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.506977668
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.1230696719
Short name T2426
Test name
Test status
Simulation time 671955010 ps
CPU time 1.76 seconds
Started Jul 13 07:13:14 PM PDT 24
Finished Jul 13 07:13:17 PM PDT 24
Peak memory 207080 kb
Host smart-2b9f8310-1ab4-444f-8e19-5005acf41e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12306
96719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.1230696719
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3346202545
Short name T1226
Test name
Test status
Simulation time 5100764723 ps
CPU time 47.09 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 207124 kb
Host smart-af0b0df1-50be-44e7-bc58-3958e3045178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33462
02545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3346202545
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.3189490766
Short name T1764
Test name
Test status
Simulation time 40327835 ps
CPU time 0.71 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 206908 kb
Host smart-3bb4aa8b-676c-495d-9821-ac445ab8d77d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3189490766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.3189490766
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2622115314
Short name T749
Test name
Test status
Simulation time 3419221484 ps
CPU time 4.33 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206908 kb
Host smart-ab773e19-1d45-485a-b016-7c20bdd7fc50
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2622115314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2622115314
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.255983047
Short name T1646
Test name
Test status
Simulation time 13297938024 ps
CPU time 11.76 seconds
Started Jul 13 07:13:13 PM PDT 24
Finished Jul 13 07:13:26 PM PDT 24
Peak memory 207052 kb
Host smart-3132f030-baec-4e3b-a9a2-49ec7e56ef48
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=255983047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.255983047
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1298617108
Short name T78
Test name
Test status
Simulation time 23318957007 ps
CPU time 27.07 seconds
Started Jul 13 07:13:07 PM PDT 24
Finished Jul 13 07:13:35 PM PDT 24
Peak memory 206960 kb
Host smart-a9f3ba66-38ff-480d-ac6f-e201fa6009f4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1298617108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1298617108
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2660692035
Short name T1158
Test name
Test status
Simulation time 162671536 ps
CPU time 0.84 seconds
Started Jul 13 07:13:11 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206852 kb
Host smart-0dbe846d-8d54-494a-9f82-d7eda962700c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26606
92035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2660692035
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.4093757687
Short name T2443
Test name
Test status
Simulation time 150626458 ps
CPU time 0.79 seconds
Started Jul 13 07:13:14 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206848 kb
Host smart-8f4967dc-5180-4b2d-9d6a-99df9846e289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
57687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.4093757687
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1938808825
Short name T617
Test name
Test status
Simulation time 451266252 ps
CPU time 1.43 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:13 PM PDT 24
Peak memory 206864 kb
Host smart-7406d24c-3d82-49c9-99c5-92a0ee68fda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19388
08825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1938808825
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3404771083
Short name T2133
Test name
Test status
Simulation time 1306176640 ps
CPU time 3.12 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 207020 kb
Host smart-57867584-c787-4178-9c38-2568d004ece4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047
71083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3404771083
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2989998531
Short name T85
Test name
Test status
Simulation time 12779403274 ps
CPU time 25.85 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:36 PM PDT 24
Peak memory 207084 kb
Host smart-56940426-a676-4db3-bd4a-4a3baa02a4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899
98531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2989998531
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2374249309
Short name T336
Test name
Test status
Simulation time 439065814 ps
CPU time 1.37 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:11 PM PDT 24
Peak memory 206864 kb
Host smart-fb8f05c0-90c7-4ae4-94af-5b0f14374067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23742
49309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2374249309
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2906785447
Short name T1347
Test name
Test status
Simulation time 157871327 ps
CPU time 0.8 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:12 PM PDT 24
Peak memory 206856 kb
Host smart-08d854a8-8b39-4f39-b2f7-24e25ce77c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29067
85447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2906785447
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.618653772
Short name T1759
Test name
Test status
Simulation time 39426923 ps
CPU time 0.67 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:13 PM PDT 24
Peak memory 206808 kb
Host smart-28c32dd5-958b-4d5a-a732-9cdb59ec5aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61865
3772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.618653772
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2040154766
Short name T442
Test name
Test status
Simulation time 802901518 ps
CPU time 2.33 seconds
Started Jul 13 07:13:12 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 207076 kb
Host smart-128f78dd-6f3c-49d5-9edf-f379b34e1f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20401
54766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2040154766
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.328290854
Short name T1271
Test name
Test status
Simulation time 217245861 ps
CPU time 1.49 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:11 PM PDT 24
Peak memory 207000 kb
Host smart-79262c22-e601-4727-ba52-95016f16e3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32829
0854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.328290854
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.413240455
Short name T1496
Test name
Test status
Simulation time 233083375 ps
CPU time 0.86 seconds
Started Jul 13 07:13:14 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206876 kb
Host smart-156e2e13-a8df-49d7-87f8-37e3476e7972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41324
0455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.413240455
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1079667147
Short name T676
Test name
Test status
Simulation time 144480348 ps
CPU time 0.77 seconds
Started Jul 13 07:13:08 PM PDT 24
Finished Jul 13 07:13:10 PM PDT 24
Peak memory 206864 kb
Host smart-c16cabf2-09db-4d15-88d0-59414d3a6036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10796
67147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1079667147
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.325531879
Short name T1238
Test name
Test status
Simulation time 225363989 ps
CPU time 0.94 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206868 kb
Host smart-5877f7e8-c40b-4668-a930-a8be923b80d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32553
1879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.325531879
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1938931423
Short name T493
Test name
Test status
Simulation time 4116994511 ps
CPU time 16.48 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:28 PM PDT 24
Peak memory 207028 kb
Host smart-3b01e974-87ab-4c1b-ace6-cffe09e34eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19389
31423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1938931423
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3582414606
Short name T2227
Test name
Test status
Simulation time 178510945 ps
CPU time 0.85 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:11 PM PDT 24
Peak memory 206876 kb
Host smart-4f2c0f41-2999-41e8-8476-8e6e3a997e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35824
14606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3582414606
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1432457232
Short name T612
Test name
Test status
Simulation time 23304667548 ps
CPU time 30.14 seconds
Started Jul 13 07:13:14 PM PDT 24
Finished Jul 13 07:13:46 PM PDT 24
Peak memory 206908 kb
Host smart-8ee64c61-ac08-438f-9552-74fb27558b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
57232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1432457232
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.790109789
Short name T994
Test name
Test status
Simulation time 3342325595 ps
CPU time 4.04 seconds
Started Jul 13 07:13:12 PM PDT 24
Finished Jul 13 07:13:18 PM PDT 24
Peak memory 206920 kb
Host smart-8432a256-a0c9-4bab-9d2e-3eb88b3c0ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79010
9789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.790109789
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.3967760567
Short name T2555
Test name
Test status
Simulation time 7293040283 ps
CPU time 51.91 seconds
Started Jul 13 07:13:12 PM PDT 24
Finished Jul 13 07:14:06 PM PDT 24
Peak memory 207136 kb
Host smart-a623371d-d93a-43e5-adb8-f2c8466e945b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39677
60567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3967760567
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3666091126
Short name T1935
Test name
Test status
Simulation time 4947506216 ps
CPU time 128.79 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:15:20 PM PDT 24
Peak memory 207060 kb
Host smart-fd7bd3de-c2c6-41db-ae12-496a87c8ef0b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3666091126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3666091126
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3063145984
Short name T945
Test name
Test status
Simulation time 235003370 ps
CPU time 0.92 seconds
Started Jul 13 07:13:13 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206544 kb
Host smart-73f9ca72-ef56-4f64-b93f-c8ac6b541cfb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3063145984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3063145984
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3678849480
Short name T329
Test name
Test status
Simulation time 194901724 ps
CPU time 0.9 seconds
Started Jul 13 07:13:11 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206896 kb
Host smart-6d74188b-4dec-46fc-a994-6fef923fb445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36788
49480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3678849480
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3898837213
Short name T320
Test name
Test status
Simulation time 4100525408 ps
CPU time 39.86 seconds
Started Jul 13 07:13:14 PM PDT 24
Finished Jul 13 07:13:55 PM PDT 24
Peak memory 207148 kb
Host smart-9a422fce-5e1c-4eb1-9daf-6ed27fdc88aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38988
37213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3898837213
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3270701619
Short name T1891
Test name
Test status
Simulation time 4383062592 ps
CPU time 33.24 seconds
Started Jul 13 07:13:08 PM PDT 24
Finished Jul 13 07:13:42 PM PDT 24
Peak memory 207120 kb
Host smart-1fbe3284-d551-4b3a-9101-91af97923af3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3270701619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3270701619
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1680446112
Short name T1900
Test name
Test status
Simulation time 159565258 ps
CPU time 0.82 seconds
Started Jul 13 07:13:13 PM PDT 24
Finished Jul 13 07:13:15 PM PDT 24
Peak memory 206868 kb
Host smart-03097c05-60c0-4a88-908a-bb305dc36fa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1680446112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1680446112
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3181447089
Short name T2145
Test name
Test status
Simulation time 143382715 ps
CPU time 0.76 seconds
Started Jul 13 07:13:08 PM PDT 24
Finished Jul 13 07:13:09 PM PDT 24
Peak memory 206864 kb
Host smart-cfe067b1-5046-4d12-9343-fe27f84b0564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31814
47089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3181447089
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1765482766
Short name T138
Test name
Test status
Simulation time 184875101 ps
CPU time 0.86 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:12 PM PDT 24
Peak memory 206868 kb
Host smart-95a3754a-cb74-4870-952c-3e4dd6cfdcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17654
82766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1765482766
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.854080422
Short name T1162
Test name
Test status
Simulation time 177443330 ps
CPU time 0.8 seconds
Started Jul 13 07:13:13 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206844 kb
Host smart-a4350ccb-256b-4229-abbf-2c6cd0d05036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85408
0422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.854080422
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.117899000
Short name T2047
Test name
Test status
Simulation time 165773070 ps
CPU time 0.8 seconds
Started Jul 13 07:13:13 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206876 kb
Host smart-a35b6b99-890b-4254-856e-e5eb73581c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11789
9000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.117899000
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1505779799
Short name T2332
Test name
Test status
Simulation time 191059229 ps
CPU time 0.82 seconds
Started Jul 13 07:13:09 PM PDT 24
Finished Jul 13 07:13:12 PM PDT 24
Peak memory 206872 kb
Host smart-9da908a1-e345-4597-8144-fc34e6be232a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15057
79799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1505779799
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1796449821
Short name T402
Test name
Test status
Simulation time 156013398 ps
CPU time 0.79 seconds
Started Jul 13 07:13:11 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206892 kb
Host smart-83a34387-a9b1-4236-adbd-631ea50d005b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17964
49821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1796449821
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3120029665
Short name T1572
Test name
Test status
Simulation time 215832842 ps
CPU time 0.91 seconds
Started Jul 13 07:13:10 PM PDT 24
Finished Jul 13 07:13:13 PM PDT 24
Peak memory 206868 kb
Host smart-d79c061f-4d79-4c17-94ab-25bc33923479
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3120029665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3120029665
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2377794493
Short name T1697
Test name
Test status
Simulation time 149875408 ps
CPU time 0.8 seconds
Started Jul 13 07:13:11 PM PDT 24
Finished Jul 13 07:13:14 PM PDT 24
Peak memory 206856 kb
Host smart-31584b1f-35e3-49e1-b08c-1f763566a75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23777
94493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2377794493
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3385277133
Short name T814
Test name
Test status
Simulation time 61887732 ps
CPU time 0.67 seconds
Started Jul 13 07:13:13 PM PDT 24
Finished Jul 13 07:13:16 PM PDT 24
Peak memory 206384 kb
Host smart-ed96dcc0-301a-4031-af8c-521f57b4a0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33852
77133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3385277133
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.755801827
Short name T1942
Test name
Test status
Simulation time 10591917900 ps
CPU time 23.62 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:13:43 PM PDT 24
Peak memory 207108 kb
Host smart-957efb21-4b79-40a5-8ba1-07feb667564f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75580
1827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.755801827
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1693697620
Short name T386
Test name
Test status
Simulation time 198957537 ps
CPU time 0.86 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 206868 kb
Host smart-d44db2a8-41cd-4c23-a2b9-65560947ebc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16936
97620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1693697620
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3749753810
Short name T2412
Test name
Test status
Simulation time 217352956 ps
CPU time 0.93 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:13:21 PM PDT 24
Peak memory 206804 kb
Host smart-ff6dceaf-1d7f-4001-865d-1b989d3e0d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37497
53810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3749753810
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1451746405
Short name T1789
Test name
Test status
Simulation time 193236750 ps
CPU time 0.8 seconds
Started Jul 13 07:13:17 PM PDT 24
Finished Jul 13 07:13:19 PM PDT 24
Peak memory 206880 kb
Host smart-d3b7e53b-2b20-4219-9642-cb73a839d3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14517
46405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1451746405
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.865271426
Short name T532
Test name
Test status
Simulation time 195329568 ps
CPU time 0.85 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:13:23 PM PDT 24
Peak memory 206868 kb
Host smart-8ee99945-7cf5-4a1a-ac47-21625d903aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86527
1426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.865271426
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.4281760320
Short name T2052
Test name
Test status
Simulation time 189499708 ps
CPU time 0.81 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:13:23 PM PDT 24
Peak memory 206864 kb
Host smart-ce803662-6059-42a8-ab78-09aaf8219101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42817
60320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.4281760320
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3829643623
Short name T1132
Test name
Test status
Simulation time 176129880 ps
CPU time 0.78 seconds
Started Jul 13 07:13:16 PM PDT 24
Finished Jul 13 07:13:18 PM PDT 24
Peak memory 206860 kb
Host smart-b1a7b49d-3684-43fc-aa16-29efcd613f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38296
43623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3829643623
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1240761532
Short name T1063
Test name
Test status
Simulation time 151374915 ps
CPU time 0.81 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:13:21 PM PDT 24
Peak memory 207048 kb
Host smart-52894efb-852d-4de5-955e-29f4cf85cf92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12407
61532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1240761532
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.4070233972
Short name T2117
Test name
Test status
Simulation time 273403403 ps
CPU time 1 seconds
Started Jul 13 07:13:17 PM PDT 24
Finished Jul 13 07:13:19 PM PDT 24
Peak memory 206896 kb
Host smart-c3421f7b-9d65-4faf-9e70-fcbf47e5c286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40702
33972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4070233972
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3439131018
Short name T810
Test name
Test status
Simulation time 3536871837 ps
CPU time 35.7 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:13:57 PM PDT 24
Peak memory 207120 kb
Host smart-d9077d50-ff5f-4f36-bca5-ba9fd210ee5c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3439131018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3439131018
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2375762033
Short name T2187
Test name
Test status
Simulation time 187984071 ps
CPU time 0.88 seconds
Started Jul 13 07:13:24 PM PDT 24
Finished Jul 13 07:13:26 PM PDT 24
Peak memory 206704 kb
Host smart-1fb7025e-3bac-490d-8652-e95e53b69edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23757
62033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2375762033
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2049041613
Short name T869
Test name
Test status
Simulation time 213865203 ps
CPU time 0.9 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 206848 kb
Host smart-137f300a-6f64-4c45-82fd-f4741cf506b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490
41613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2049041613
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3660859982
Short name T1648
Test name
Test status
Simulation time 267302476 ps
CPU time 0.96 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 206872 kb
Host smart-19a6f1ac-2b24-47c5-a4ae-a0c22061323b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36608
59982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3660859982
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.575103933
Short name T1845
Test name
Test status
Simulation time 3442832664 ps
CPU time 32.3 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 207140 kb
Host smart-2d852034-1111-45b9-bd67-f1671d1c9161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57510
3933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.575103933
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3894978826
Short name T1346
Test name
Test status
Simulation time 3787277997 ps
CPU time 4.07 seconds
Started Jul 13 07:13:17 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 207092 kb
Host smart-8baff3f7-ac20-44bc-b6bc-e3790313f12a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3894978826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3894978826
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3236099066
Short name T1978
Test name
Test status
Simulation time 13325329981 ps
CPU time 11.85 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:13:34 PM PDT 24
Peak memory 207068 kb
Host smart-c5403beb-3660-4aae-a5c4-0949a5812601
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3236099066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3236099066
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.222047809
Short name T2503
Test name
Test status
Simulation time 23336020848 ps
CPU time 20.88 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:13:43 PM PDT 24
Peak memory 207064 kb
Host smart-71202107-2c63-45c1-a037-752ec30a0760
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=222047809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.222047809
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.29409789
Short name T1474
Test name
Test status
Simulation time 240549169 ps
CPU time 0.88 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:13:20 PM PDT 24
Peak memory 206860 kb
Host smart-950ac8a7-5de0-4d40-8485-85891b182ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29409
789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.29409789
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2553747458
Short name T1952
Test name
Test status
Simulation time 147019272 ps
CPU time 0.78 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:13:20 PM PDT 24
Peak memory 206860 kb
Host smart-322b0657-3edb-425f-9af7-59baf183a578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25537
47458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2553747458
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2237637540
Short name T2509
Test name
Test status
Simulation time 237175145 ps
CPU time 0.93 seconds
Started Jul 13 07:13:17 PM PDT 24
Finished Jul 13 07:13:19 PM PDT 24
Peak memory 206864 kb
Host smart-25450c7b-9f95-477e-af6a-7a6e018ff3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22376
37540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2237637540
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2434349232
Short name T783
Test name
Test status
Simulation time 451952833 ps
CPU time 1.35 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:13:23 PM PDT 24
Peak memory 206856 kb
Host smart-a61d170e-6d81-4005-8ddd-cdeb1ba71e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24343
49232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2434349232
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.3710777464
Short name T1199
Test name
Test status
Simulation time 19298050789 ps
CPU time 40.68 seconds
Started Jul 13 07:13:17 PM PDT 24
Finished Jul 13 07:13:59 PM PDT 24
Peak memory 207084 kb
Host smart-5acfafab-df36-46c6-9872-ddac3837c869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107
77464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.3710777464
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3468758748
Short name T1840
Test name
Test status
Simulation time 335087523 ps
CPU time 1.14 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:13:21 PM PDT 24
Peak memory 206816 kb
Host smart-f9f027f0-8014-4366-820c-d08730b16a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34687
58748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3468758748
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.4137269878
Short name T1491
Test name
Test status
Simulation time 167819395 ps
CPU time 0.82 seconds
Started Jul 13 07:13:24 PM PDT 24
Finished Jul 13 07:13:26 PM PDT 24
Peak memory 206848 kb
Host smart-232e2145-0e42-47ed-b7d9-224cee5060a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41372
69878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.4137269878
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3129193549
Short name T653
Test name
Test status
Simulation time 97044946 ps
CPU time 0.73 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 206876 kb
Host smart-d87811d8-c7d2-48d2-9007-97a0c3db895e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31291
93549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3129193549
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1925735135
Short name T2368
Test name
Test status
Simulation time 834051421 ps
CPU time 2 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:13:23 PM PDT 24
Peak memory 207068 kb
Host smart-fe187620-2a6f-4b3a-a822-63ed7f39a18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19257
35135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1925735135
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3728679902
Short name T857
Test name
Test status
Simulation time 190648406 ps
CPU time 2.09 seconds
Started Jul 13 07:13:22 PM PDT 24
Finished Jul 13 07:13:25 PM PDT 24
Peak memory 206936 kb
Host smart-823cec00-7de8-4fe6-89d5-578a17de4346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
79902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3728679902
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1408749110
Short name T2392
Test name
Test status
Simulation time 223730371 ps
CPU time 0.88 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:13:20 PM PDT 24
Peak memory 206880 kb
Host smart-42bd3f5e-4468-4c71-b8eb-33bf29453d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
49110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1408749110
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.280192577
Short name T2646
Test name
Test status
Simulation time 183804004 ps
CPU time 0.78 seconds
Started Jul 13 07:13:17 PM PDT 24
Finished Jul 13 07:13:18 PM PDT 24
Peak memory 206860 kb
Host smart-50cb07f5-147e-4175-9bc6-57202d12a186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28019
2577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.280192577
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.72651990
Short name T1206
Test name
Test status
Simulation time 218996207 ps
CPU time 0.87 seconds
Started Jul 13 07:13:17 PM PDT 24
Finished Jul 13 07:13:18 PM PDT 24
Peak memory 206868 kb
Host smart-32a01d50-a416-4d9d-9933-7952172e0836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72651
990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.72651990
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.203064643
Short name T1514
Test name
Test status
Simulation time 8105734040 ps
CPU time 65.68 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:14:25 PM PDT 24
Peak memory 207080 kb
Host smart-01677590-eb4b-456b-af4e-8da13333c729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20306
4643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.203064643
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.863110258
Short name T1202
Test name
Test status
Simulation time 236494933 ps
CPU time 0.93 seconds
Started Jul 13 07:13:24 PM PDT 24
Finished Jul 13 07:13:26 PM PDT 24
Peak memory 206720 kb
Host smart-b1faa715-5f75-4e47-af3c-174769d6e31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86311
0258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.863110258
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2182239076
Short name T1812
Test name
Test status
Simulation time 23287090072 ps
CPU time 21.19 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:13:43 PM PDT 24
Peak memory 207168 kb
Host smart-401371f6-9ff4-4404-81d1-dd0e7be016b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21822
39076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2182239076
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3657488526
Short name T1197
Test name
Test status
Simulation time 3312239150 ps
CPU time 3.69 seconds
Started Jul 13 07:13:22 PM PDT 24
Finished Jul 13 07:13:26 PM PDT 24
Peak memory 206836 kb
Host smart-1b73712d-0cf2-4848-a90e-0d7a0da33ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36574
88526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3657488526
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.2384304434
Short name T1529
Test name
Test status
Simulation time 10389926212 ps
CPU time 73.41 seconds
Started Jul 13 07:13:21 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 207136 kb
Host smart-68a59b34-af8d-4a00-8ed4-8e378c8071f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23843
04434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.2384304434
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1951019192
Short name T422
Test name
Test status
Simulation time 5251770402 ps
CPU time 38.68 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 207148 kb
Host smart-6322ed8f-aad6-4506-ab9d-0735028b9601
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1951019192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1951019192
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.327371804
Short name T2031
Test name
Test status
Simulation time 294709460 ps
CPU time 0.94 seconds
Started Jul 13 07:13:21 PM PDT 24
Finished Jul 13 07:13:23 PM PDT 24
Peak memory 206884 kb
Host smart-0aa82bcf-cee8-4ca9-8460-b0a426d5bbf5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=327371804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.327371804
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.447719405
Short name T1535
Test name
Test status
Simulation time 198138874 ps
CPU time 0.87 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 206848 kb
Host smart-437fe394-8618-4150-8185-d326174cf0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44771
9405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.447719405
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1413867018
Short name T390
Test name
Test status
Simulation time 4135567058 ps
CPU time 116.28 seconds
Started Jul 13 07:13:20 PM PDT 24
Finished Jul 13 07:15:18 PM PDT 24
Peak memory 207048 kb
Host smart-45d76cd7-17de-4a77-b2fe-8942b2cdb9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14138
67018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1413867018
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.662823730
Short name T2492
Test name
Test status
Simulation time 6794575994 ps
CPU time 193.24 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:16:34 PM PDT 24
Peak memory 207116 kb
Host smart-f9ccfa30-329f-4887-9472-1d17181d137c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=662823730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.662823730
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1430775227
Short name T1693
Test name
Test status
Simulation time 168906333 ps
CPU time 0.78 seconds
Started Jul 13 07:13:16 PM PDT 24
Finished Jul 13 07:13:18 PM PDT 24
Peak memory 206864 kb
Host smart-e878f2f6-b3a4-4fec-a9f0-64b78403b535
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1430775227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1430775227
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.727787582
Short name T786
Test name
Test status
Simulation time 146107703 ps
CPU time 0.78 seconds
Started Jul 13 07:13:18 PM PDT 24
Finished Jul 13 07:13:20 PM PDT 24
Peak memory 206864 kb
Host smart-196d9a8e-3667-4788-816e-e211c1fbb3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72778
7582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.727787582
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1405963313
Short name T116
Test name
Test status
Simulation time 184821952 ps
CPU time 0.87 seconds
Started Jul 13 07:13:19 PM PDT 24
Finished Jul 13 07:13:21 PM PDT 24
Peak memory 206868 kb
Host smart-a0f09b2c-5303-4f23-b14c-ada185f43339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
63313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1405963313
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1220985316
Short name T539
Test name
Test status
Simulation time 154961838 ps
CPU time 0.79 seconds
Started Jul 13 07:13:28 PM PDT 24
Finished Jul 13 07:13:30 PM PDT 24
Peak memory 206864 kb
Host smart-768b5ca6-6e9a-4e2a-9613-bda43e60d246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12209
85316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1220985316
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2205293194
Short name T2583
Test name
Test status
Simulation time 194588957 ps
CPU time 0.86 seconds
Started Jul 13 07:13:28 PM PDT 24
Finished Jul 13 07:13:30 PM PDT 24
Peak memory 206888 kb
Host smart-72e2d997-bded-43c5-98b7-4b93a75d624e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
93194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2205293194
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.492480981
Short name T1788
Test name
Test status
Simulation time 159670437 ps
CPU time 0.79 seconds
Started Jul 13 07:13:26 PM PDT 24
Finished Jul 13 07:13:28 PM PDT 24
Peak memory 206856 kb
Host smart-92060604-32a4-4bdf-b1c9-015c173f0d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49248
0981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.492480981
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3629522063
Short name T2202
Test name
Test status
Simulation time 156310748 ps
CPU time 0.81 seconds
Started Jul 13 07:13:28 PM PDT 24
Finished Jul 13 07:13:29 PM PDT 24
Peak memory 206864 kb
Host smart-c4f9ab64-5817-426b-a793-36ef89a43e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36295
22063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3629522063
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.4204587522
Short name T1149
Test name
Test status
Simulation time 273853436 ps
CPU time 1.02 seconds
Started Jul 13 07:13:29 PM PDT 24
Finished Jul 13 07:13:31 PM PDT 24
Peak memory 206868 kb
Host smart-800de7ff-00d4-4b6e-a9a9-fb2f2e50a96f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4204587522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.4204587522
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1402837930
Short name T2425
Test name
Test status
Simulation time 137594583 ps
CPU time 0.76 seconds
Started Jul 13 07:13:27 PM PDT 24
Finished Jul 13 07:13:29 PM PDT 24
Peak memory 206856 kb
Host smart-a2e9de6a-2a3a-4d5d-b140-994d86cb7eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14028
37930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1402837930
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3597959419
Short name T196
Test name
Test status
Simulation time 46152414 ps
CPU time 0.75 seconds
Started Jul 13 07:13:29 PM PDT 24
Finished Jul 13 07:13:31 PM PDT 24
Peak memory 206864 kb
Host smart-af3ea8c2-75ad-41a9-82d7-855eed50277d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35979
59419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3597959419
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3090205389
Short name T2581
Test name
Test status
Simulation time 21155167033 ps
CPU time 43.08 seconds
Started Jul 13 07:13:29 PM PDT 24
Finished Jul 13 07:14:13 PM PDT 24
Peak memory 207168 kb
Host smart-cd434f43-8408-4eef-bef6-bc26b3894c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30902
05389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3090205389
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.624529591
Short name T1631
Test name
Test status
Simulation time 171579763 ps
CPU time 0.84 seconds
Started Jul 13 07:13:28 PM PDT 24
Finished Jul 13 07:13:30 PM PDT 24
Peak memory 206864 kb
Host smart-7d094968-9287-4ca2-a39b-41f87e6e6dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62452
9591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.624529591
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.316587750
Short name T1599
Test name
Test status
Simulation time 206600001 ps
CPU time 0.86 seconds
Started Jul 13 07:13:28 PM PDT 24
Finished Jul 13 07:13:30 PM PDT 24
Peak memory 206864 kb
Host smart-709f838c-c37d-491c-8a3c-609e9a1c8f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31658
7750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.316587750
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.2864718237
Short name T686
Test name
Test status
Simulation time 197789482 ps
CPU time 0.9 seconds
Started Jul 13 07:13:32 PM PDT 24
Finished Jul 13 07:13:33 PM PDT 24
Peak memory 206880 kb
Host smart-25272137-011e-47ff-a117-4234073912fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28647
18237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.2864718237
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3886477518
Short name T333
Test name
Test status
Simulation time 204777928 ps
CPU time 0.92 seconds
Started Jul 13 07:13:27 PM PDT 24
Finished Jul 13 07:13:29 PM PDT 24
Peak memory 206872 kb
Host smart-6f08e7f4-0816-4e1b-aa3c-7906ba1bd4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38864
77518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3886477518
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3374489078
Short name T820
Test name
Test status
Simulation time 154773745 ps
CPU time 0.78 seconds
Started Jul 13 07:13:31 PM PDT 24
Finished Jul 13 07:13:32 PM PDT 24
Peak memory 206872 kb
Host smart-5517c72b-b314-4170-a924-0707c5294302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33744
89078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3374489078
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1603113001
Short name T822
Test name
Test status
Simulation time 166800736 ps
CPU time 0.8 seconds
Started Jul 13 07:13:26 PM PDT 24
Finished Jul 13 07:13:28 PM PDT 24
Peak memory 206844 kb
Host smart-3b310138-cf67-4f6c-a62e-ffe3e95ba5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
13001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1603113001
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2674894859
Short name T295
Test name
Test status
Simulation time 156597236 ps
CPU time 0.79 seconds
Started Jul 13 07:13:26 PM PDT 24
Finished Jul 13 07:13:27 PM PDT 24
Peak memory 206868 kb
Host smart-ea6d621e-1e0c-47e1-8650-1cfec2b0b944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26748
94859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2674894859
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3993635808
Short name T2225
Test name
Test status
Simulation time 212820931 ps
CPU time 0.92 seconds
Started Jul 13 07:13:28 PM PDT 24
Finished Jul 13 07:13:31 PM PDT 24
Peak memory 206580 kb
Host smart-65d8ece4-b1b8-4758-81c2-59ae9c4ddae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936
35808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3993635808
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2927008490
Short name T2194
Test name
Test status
Simulation time 5588307867 ps
CPU time 41.72 seconds
Started Jul 13 07:13:27 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 207120 kb
Host smart-7e94750e-197d-42a6-bbf9-680b2d288f5b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2927008490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2927008490
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3234402928
Short name T825
Test name
Test status
Simulation time 181137111 ps
CPU time 0.82 seconds
Started Jul 13 07:13:32 PM PDT 24
Finished Jul 13 07:13:34 PM PDT 24
Peak memory 206856 kb
Host smart-6a6d56ad-957a-413e-8f03-cc8b18f5d602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32344
02928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3234402928
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.477851668
Short name T2298
Test name
Test status
Simulation time 192372774 ps
CPU time 0.87 seconds
Started Jul 13 07:13:29 PM PDT 24
Finished Jul 13 07:13:31 PM PDT 24
Peak memory 206872 kb
Host smart-b7ea029c-4577-4014-a77e-ee87bbf80d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47785
1668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.477851668
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.3298609891
Short name T2413
Test name
Test status
Simulation time 539540014 ps
CPU time 1.48 seconds
Started Jul 13 07:13:27 PM PDT 24
Finished Jul 13 07:13:29 PM PDT 24
Peak memory 206868 kb
Host smart-26b7a1fa-0ef1-4657-9d06-d5edbe2ea475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32986
09891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.3298609891
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.4276645698
Short name T1146
Test name
Test status
Simulation time 6231592796 ps
CPU time 174.96 seconds
Started Jul 13 07:13:25 PM PDT 24
Finished Jul 13 07:16:21 PM PDT 24
Peak memory 207072 kb
Host smart-e5d3dfef-a915-413e-8677-7a36becd47af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42766
45698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.4276645698
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.1908048771
Short name T478
Test name
Test status
Simulation time 35324919 ps
CPU time 0.65 seconds
Started Jul 13 07:13:36 PM PDT 24
Finished Jul 13 07:13:38 PM PDT 24
Peak memory 206888 kb
Host smart-b9615afb-f3d3-4fbc-9be1-324ec5e21d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1908048771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1908048771
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.28023813
Short name T182
Test name
Test status
Simulation time 3993554178 ps
CPU time 5.42 seconds
Started Jul 13 07:13:32 PM PDT 24
Finished Jul 13 07:13:38 PM PDT 24
Peak memory 206944 kb
Host smart-09f2884d-b0dd-41a7-b191-c7eabc2b2604
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=28023813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.28023813
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1574226648
Short name T2256
Test name
Test status
Simulation time 13345280418 ps
CPU time 15.16 seconds
Started Jul 13 07:13:29 PM PDT 24
Finished Jul 13 07:13:45 PM PDT 24
Peak memory 206920 kb
Host smart-057d60ab-2f89-4899-831b-0c93881dafa8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1574226648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1574226648
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2740078822
Short name T769
Test name
Test status
Simulation time 23480484464 ps
CPU time 27.1 seconds
Started Jul 13 07:13:31 PM PDT 24
Finished Jul 13 07:13:58 PM PDT 24
Peak memory 207068 kb
Host smart-8011a030-6afd-4bd6-b093-7d4d0b547296
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2740078822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2740078822
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2506110332
Short name T641
Test name
Test status
Simulation time 150972291 ps
CPU time 0.82 seconds
Started Jul 13 07:13:28 PM PDT 24
Finished Jul 13 07:13:30 PM PDT 24
Peak memory 206608 kb
Host smart-3279ac75-f22f-453c-b678-ee7df310c7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061
10332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2506110332
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3322215062
Short name T1273
Test name
Test status
Simulation time 153317616 ps
CPU time 0.78 seconds
Started Jul 13 07:13:25 PM PDT 24
Finished Jul 13 07:13:26 PM PDT 24
Peak memory 206844 kb
Host smart-f494974c-50b2-4f75-807d-dd36e72dfc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33222
15062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3322215062
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1577831571
Short name T803
Test name
Test status
Simulation time 143694561 ps
CPU time 0.88 seconds
Started Jul 13 07:13:30 PM PDT 24
Finished Jul 13 07:13:32 PM PDT 24
Peak memory 206808 kb
Host smart-a6889d35-af45-44bd-ac73-0483c24b72a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15778
31571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1577831571
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.686941941
Short name T57
Test name
Test status
Simulation time 331666077 ps
CPU time 1.2 seconds
Started Jul 13 07:13:31 PM PDT 24
Finished Jul 13 07:13:33 PM PDT 24
Peak memory 206812 kb
Host smart-03d30235-675f-4626-82df-a57ff3552ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68694
1941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.686941941
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.4210937827
Short name T2239
Test name
Test status
Simulation time 10371908747 ps
CPU time 18.39 seconds
Started Jul 13 07:13:30 PM PDT 24
Finished Jul 13 07:13:49 PM PDT 24
Peak memory 207132 kb
Host smart-95a50c97-2c0a-410b-840f-6ea8d5793d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
37827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.4210937827
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.1517034452
Short name T467
Test name
Test status
Simulation time 357159205 ps
CPU time 1.28 seconds
Started Jul 13 07:13:29 PM PDT 24
Finished Jul 13 07:13:31 PM PDT 24
Peak memory 206872 kb
Host smart-3acf479d-0fe3-4de7-ae79-72e070a07628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15170
34452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.1517034452
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3865730528
Short name T740
Test name
Test status
Simulation time 136635121 ps
CPU time 0.75 seconds
Started Jul 13 07:13:26 PM PDT 24
Finished Jul 13 07:13:28 PM PDT 24
Peak memory 206856 kb
Host smart-bd5092ff-3bab-4c4f-95ac-383b0c1ae2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
30528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3865730528
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.3114807947
Short name T332
Test name
Test status
Simulation time 37190443 ps
CPU time 0.67 seconds
Started Jul 13 07:13:27 PM PDT 24
Finished Jul 13 07:13:29 PM PDT 24
Peak memory 206864 kb
Host smart-70733345-893f-4da4-9f08-b2cc6c1f857d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31148
07947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3114807947
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.285278163
Short name T1061
Test name
Test status
Simulation time 961790097 ps
CPU time 2.35 seconds
Started Jul 13 07:13:27 PM PDT 24
Finished Jul 13 07:13:31 PM PDT 24
Peak memory 207096 kb
Host smart-b9660108-1a42-42b5-ba61-dc3a8c879fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28527
8163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.285278163
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2009367606
Short name T284
Test name
Test status
Simulation time 180240989 ps
CPU time 1.55 seconds
Started Jul 13 07:13:26 PM PDT 24
Finished Jul 13 07:13:29 PM PDT 24
Peak memory 206960 kb
Host smart-dc0cafdf-9bdd-4a7a-aaef-bffa614c9d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20093
67606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2009367606
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3757175866
Short name T1437
Test name
Test status
Simulation time 207676822 ps
CPU time 0.85 seconds
Started Jul 13 07:13:37 PM PDT 24
Finished Jul 13 07:13:38 PM PDT 24
Peak memory 207044 kb
Host smart-b4b38b48-b28c-4e24-a139-d6b0553b07c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571
75866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3757175866
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.21430917
Short name T1051
Test name
Test status
Simulation time 139417270 ps
CPU time 0.75 seconds
Started Jul 13 07:13:38 PM PDT 24
Finished Jul 13 07:13:40 PM PDT 24
Peak memory 206884 kb
Host smart-87bcad00-d774-4fbc-8e9a-1e1e443d1ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21430
917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.21430917
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.936629625
Short name T1624
Test name
Test status
Simulation time 259795253 ps
CPU time 0.9 seconds
Started Jul 13 07:13:42 PM PDT 24
Finished Jul 13 07:13:44 PM PDT 24
Peak memory 206872 kb
Host smart-7b299231-ee3b-49c4-b6c7-8680b06ea621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93662
9625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.936629625
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.3219115937
Short name T536
Test name
Test status
Simulation time 7806927432 ps
CPU time 56.55 seconds
Started Jul 13 07:13:26 PM PDT 24
Finished Jul 13 07:14:24 PM PDT 24
Peak memory 207072 kb
Host smart-179271a2-eafa-44c5-b9ec-030a0d440bc3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3219115937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3219115937
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.2897543823
Short name T1962
Test name
Test status
Simulation time 4067313660 ps
CPU time 13.46 seconds
Started Jul 13 07:13:42 PM PDT 24
Finished Jul 13 07:13:56 PM PDT 24
Peak memory 206964 kb
Host smart-fe41b984-3d75-4eb1-af52-5f75e6936ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28975
43823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.2897543823
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3406237059
Short name T1795
Test name
Test status
Simulation time 211357692 ps
CPU time 0.92 seconds
Started Jul 13 07:13:34 PM PDT 24
Finished Jul 13 07:13:36 PM PDT 24
Peak memory 206804 kb
Host smart-fab0d824-ed86-4dc6-ad9f-18cc4f44e3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34062
37059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3406237059
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.180959436
Short name T2578
Test name
Test status
Simulation time 23290523392 ps
CPU time 25.44 seconds
Started Jul 13 07:13:44 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206928 kb
Host smart-8a14b98f-702a-41fc-aa0c-bae2d7d67ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18095
9436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.180959436
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1292231049
Short name T1625
Test name
Test status
Simulation time 3337973242 ps
CPU time 4.04 seconds
Started Jul 13 07:13:35 PM PDT 24
Finished Jul 13 07:13:40 PM PDT 24
Peak memory 206932 kb
Host smart-14c6c8a3-41ed-4d23-a4be-2d836c0f9236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12922
31049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1292231049
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1848390095
Short name T1908
Test name
Test status
Simulation time 11179749493 ps
CPU time 107.33 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:15:34 PM PDT 24
Peak memory 207164 kb
Host smart-9ce3de71-8cb1-4511-b271-0a3ef553a13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18483
90095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1848390095
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1539157313
Short name T1627
Test name
Test status
Simulation time 4402779398 ps
CPU time 127.48 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:15:55 PM PDT 24
Peak memory 207136 kb
Host smart-812e3f3b-70be-4016-98e6-4459e4ad4e9c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1539157313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1539157313
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.476835807
Short name T2487
Test name
Test status
Simulation time 276809866 ps
CPU time 0.99 seconds
Started Jul 13 07:13:40 PM PDT 24
Finished Jul 13 07:13:42 PM PDT 24
Peak memory 206876 kb
Host smart-23309476-de99-4ed6-a982-a7ae29497447
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=476835807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.476835807
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2841057481
Short name T301
Test name
Test status
Simulation time 190038860 ps
CPU time 0.9 seconds
Started Jul 13 07:13:44 PM PDT 24
Finished Jul 13 07:13:46 PM PDT 24
Peak memory 206884 kb
Host smart-98765756-4c37-4baa-8710-90ceb0a457be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28410
57481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2841057481
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.1862403850
Short name T142
Test name
Test status
Simulation time 6103246907 ps
CPU time 171.94 seconds
Started Jul 13 07:13:43 PM PDT 24
Finished Jul 13 07:16:35 PM PDT 24
Peak memory 207068 kb
Host smart-7d15882f-479b-42ec-b679-696be05c1dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18624
03850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.1862403850
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3546731893
Short name T292
Test name
Test status
Simulation time 6022378599 ps
CPU time 161.89 seconds
Started Jul 13 07:13:42 PM PDT 24
Finished Jul 13 07:16:25 PM PDT 24
Peak memory 207092 kb
Host smart-738a8970-e058-4430-af52-a33bbfc8030b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3546731893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3546731893
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.108643753
Short name T2460
Test name
Test status
Simulation time 157031683 ps
CPU time 0.84 seconds
Started Jul 13 07:13:36 PM PDT 24
Finished Jul 13 07:13:38 PM PDT 24
Peak memory 206868 kb
Host smart-c8fbe8c3-f701-4c00-9205-36acab18a776
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=108643753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.108643753
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1716296685
Short name T2090
Test name
Test status
Simulation time 142444724 ps
CPU time 0.73 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 206864 kb
Host smart-25cb22a8-9d65-48a1-ab67-0636d5f4c13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17162
96685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1716296685
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.4134141383
Short name T131
Test name
Test status
Simulation time 222757904 ps
CPU time 0.91 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 206860 kb
Host smart-4860c524-6d7e-4b12-a135-35bb98eec88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41341
41383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.4134141383
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2178684557
Short name T1953
Test name
Test status
Simulation time 173148111 ps
CPU time 0.81 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 206868 kb
Host smart-57a07f7e-01a5-40aa-9762-bb2025c901cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21786
84557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2178684557
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1912682972
Short name T2344
Test name
Test status
Simulation time 161910612 ps
CPU time 0.77 seconds
Started Jul 13 07:13:34 PM PDT 24
Finished Jul 13 07:13:36 PM PDT 24
Peak memory 206864 kb
Host smart-9a847192-ff49-441a-9e04-917fa2731dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126
82972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1912682972
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.702160908
Short name T1611
Test name
Test status
Simulation time 151869607 ps
CPU time 0.8 seconds
Started Jul 13 07:13:36 PM PDT 24
Finished Jul 13 07:13:38 PM PDT 24
Peak memory 206844 kb
Host smart-b2c25f54-6072-4aa3-bf19-1176ed9d52ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70216
0908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.702160908
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1110692150
Short name T2605
Test name
Test status
Simulation time 154573947 ps
CPU time 0.85 seconds
Started Jul 13 07:13:38 PM PDT 24
Finished Jul 13 07:13:40 PM PDT 24
Peak memory 206860 kb
Host smart-6e4fb08c-1cd3-404f-ac1a-984f2e040fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11106
92150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1110692150
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1001952103
Short name T2442
Test name
Test status
Simulation time 183011396 ps
CPU time 0.86 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 206216 kb
Host smart-a21c1354-e89e-4e80-80aa-9cf0dfe3201f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1001952103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1001952103
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.4042190973
Short name T756
Test name
Test status
Simulation time 158616872 ps
CPU time 0.8 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 206864 kb
Host smart-180d4d2a-f184-4bfc-8919-0731b4d0c052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40421
90973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.4042190973
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.239064573
Short name T2415
Test name
Test status
Simulation time 48991786 ps
CPU time 0.64 seconds
Started Jul 13 07:13:36 PM PDT 24
Finished Jul 13 07:13:38 PM PDT 24
Peak memory 206880 kb
Host smart-3851c8c2-a9a0-4608-8cc7-eb8df3e0819f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23906
4573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.239064573
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1228298897
Short name T896
Test name
Test status
Simulation time 14058875886 ps
CPU time 30.02 seconds
Started Jul 13 07:13:37 PM PDT 24
Finished Jul 13 07:14:07 PM PDT 24
Peak memory 207168 kb
Host smart-f2d60f16-7b69-4c91-817c-fed5ac4177f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12282
98897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1228298897
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3219984763
Short name T1813
Test name
Test status
Simulation time 176955396 ps
CPU time 0.91 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:13:49 PM PDT 24
Peak memory 206860 kb
Host smart-b955a99d-04cc-443c-9447-a2c33996cd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199
84763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3219984763
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.4272457939
Short name T1904
Test name
Test status
Simulation time 168301806 ps
CPU time 0.8 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 206872 kb
Host smart-4d718da2-25fd-490b-9818-255363ade91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42724
57939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.4272457939
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.718925967
Short name T1084
Test name
Test status
Simulation time 216700250 ps
CPU time 0.92 seconds
Started Jul 13 07:13:43 PM PDT 24
Finished Jul 13 07:13:45 PM PDT 24
Peak memory 206868 kb
Host smart-6a451acc-9da2-44b5-870a-604f0fb0e220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71892
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.718925967
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1232785081
Short name T1778
Test name
Test status
Simulation time 145515354 ps
CPU time 0.77 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 206288 kb
Host smart-1d6c8f33-3f56-4230-bd3e-85bcfb06e6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12327
85081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1232785081
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1290069880
Short name T2468
Test name
Test status
Simulation time 184709963 ps
CPU time 0.81 seconds
Started Jul 13 07:13:35 PM PDT 24
Finished Jul 13 07:13:37 PM PDT 24
Peak memory 206872 kb
Host smart-79c3ca3e-0219-4248-8dbc-d2f5b1ca7f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12900
69880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1290069880
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.501826436
Short name T1242
Test name
Test status
Simulation time 166460757 ps
CPU time 0.83 seconds
Started Jul 13 07:13:44 PM PDT 24
Finished Jul 13 07:13:45 PM PDT 24
Peak memory 206856 kb
Host smart-21f9ae21-6d20-486f-9206-f76318624e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50182
6436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.501826436
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.502758201
Short name T1423
Test name
Test status
Simulation time 150916366 ps
CPU time 0.86 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206808 kb
Host smart-a35b93ab-2e84-4215-9abb-2b2b28237ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50275
8201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.502758201
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1280417151
Short name T2481
Test name
Test status
Simulation time 212234821 ps
CPU time 0.86 seconds
Started Jul 13 07:13:35 PM PDT 24
Finished Jul 13 07:13:36 PM PDT 24
Peak memory 206876 kb
Host smart-13a77ce8-88ae-4ba2-a2c8-0db4ee31be56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12804
17151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1280417151
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3096159556
Short name T1934
Test name
Test status
Simulation time 4337860232 ps
CPU time 43.26 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:14:31 PM PDT 24
Peak memory 207068 kb
Host smart-62b441d1-cd19-4f27-b29b-f5daf47c4e34
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3096159556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3096159556
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3719810601
Short name T1033
Test name
Test status
Simulation time 218422842 ps
CPU time 0.87 seconds
Started Jul 13 07:13:38 PM PDT 24
Finished Jul 13 07:13:40 PM PDT 24
Peak memory 206848 kb
Host smart-6c3065ba-ea0a-493e-a4b0-71517ef8db87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37198
10601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3719810601
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1410467020
Short name T2338
Test name
Test status
Simulation time 194600296 ps
CPU time 0.86 seconds
Started Jul 13 07:13:37 PM PDT 24
Finished Jul 13 07:13:39 PM PDT 24
Peak memory 206876 kb
Host smart-086a9b57-5902-46c4-8af0-6577cab54227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14104
67020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1410467020
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1003793605
Short name T690
Test name
Test status
Simulation time 1335787605 ps
CPU time 2.81 seconds
Started Jul 13 07:13:36 PM PDT 24
Finished Jul 13 07:13:40 PM PDT 24
Peak memory 207068 kb
Host smart-99958f0b-d463-4805-a95f-a40aab01e194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10037
93605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1003793605
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.971563272
Short name T364
Test name
Test status
Simulation time 5073637542 ps
CPU time 141.64 seconds
Started Jul 13 07:13:39 PM PDT 24
Finished Jul 13 07:16:02 PM PDT 24
Peak memory 207104 kb
Host smart-aeb6c85d-a67e-449d-89d5-1201b6edb209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97156
3272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.971563272
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1998698775
Short name T166
Test name
Test status
Simulation time 38816020 ps
CPU time 0.67 seconds
Started Jul 13 07:13:52 PM PDT 24
Finished Jul 13 07:13:54 PM PDT 24
Peak memory 206916 kb
Host smart-eff06940-41d5-4386-be36-1543a70a429b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1998698775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1998698775
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2833118901
Short name T1407
Test name
Test status
Simulation time 3742818935 ps
CPU time 4.25 seconds
Started Jul 13 07:13:36 PM PDT 24
Finished Jul 13 07:13:41 PM PDT 24
Peak memory 207144 kb
Host smart-49e80621-ef06-4f99-a1f8-c2a3c153f730
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2833118901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2833118901
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1471995122
Short name T2716
Test name
Test status
Simulation time 13309373705 ps
CPU time 14.96 seconds
Started Jul 13 07:13:40 PM PDT 24
Finished Jul 13 07:13:56 PM PDT 24
Peak memory 207068 kb
Host smart-8e5c31fb-e117-4321-81a1-ed38e217f235
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1471995122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1471995122
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2480091669
Short name T899
Test name
Test status
Simulation time 23329821698 ps
CPU time 30.92 seconds
Started Jul 13 07:13:39 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 206936 kb
Host smart-3eb0969b-4d7e-440f-a4e2-a1ab47caf251
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2480091669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2480091669
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1395284339
Short name T2456
Test name
Test status
Simulation time 204307097 ps
CPU time 0.82 seconds
Started Jul 13 07:13:37 PM PDT 24
Finished Jul 13 07:13:38 PM PDT 24
Peak memory 206816 kb
Host smart-145cda7c-60e0-4b1b-8dcc-40f35ae94b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13952
84339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1395284339
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1337637440
Short name T2610
Test name
Test status
Simulation time 161483575 ps
CPU time 0.79 seconds
Started Jul 13 07:13:38 PM PDT 24
Finished Jul 13 07:13:40 PM PDT 24
Peak memory 207104 kb
Host smart-da3716df-e37b-499f-97a9-05427a4cc94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13376
37440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1337637440
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1569789227
Short name T2164
Test name
Test status
Simulation time 357298143 ps
CPU time 1.27 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206828 kb
Host smart-52858971-e048-4855-8e15-72cb582015c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
89227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1569789227
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2664129155
Short name T417
Test name
Test status
Simulation time 375779616 ps
CPU time 1.17 seconds
Started Jul 13 07:13:44 PM PDT 24
Finished Jul 13 07:13:45 PM PDT 24
Peak memory 206868 kb
Host smart-65167b61-ebce-4797-b64f-f6a458926c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26641
29155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2664129155
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.206882585
Short name T2445
Test name
Test status
Simulation time 9251891522 ps
CPU time 17.13 seconds
Started Jul 13 07:13:44 PM PDT 24
Finished Jul 13 07:14:02 PM PDT 24
Peak memory 207136 kb
Host smart-cd99aa6d-6e83-4f1d-918c-2dc7c4e27f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20688
2585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.206882585
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.1086790152
Short name T1152
Test name
Test status
Simulation time 158979604 ps
CPU time 0.81 seconds
Started Jul 13 07:13:38 PM PDT 24
Finished Jul 13 07:13:39 PM PDT 24
Peak memory 206876 kb
Host smart-5bfbf80b-11f8-4763-a894-4f8d8876bc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10867
90152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.1086790152
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1631162864
Short name T2266
Test name
Test status
Simulation time 424689877 ps
CPU time 1.3 seconds
Started Jul 13 07:13:47 PM PDT 24
Finished Jul 13 07:13:50 PM PDT 24
Peak memory 206868 kb
Host smart-51d93728-5484-45f1-8f31-c756503fd3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16311
62864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1631162864
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3285625443
Short name T2549
Test name
Test status
Simulation time 158787581 ps
CPU time 0.76 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:50 PM PDT 24
Peak memory 206868 kb
Host smart-ed3af48a-a50e-4ce5-9152-56e2dfc03474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32856
25443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3285625443
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1905382612
Short name T1367
Test name
Test status
Simulation time 38504464 ps
CPU time 0.64 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206896 kb
Host smart-b943ab32-53a3-49e4-b2ac-601b548d6dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19053
82612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1905382612
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.336948749
Short name T1780
Test name
Test status
Simulation time 984746749 ps
CPU time 2.28 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206836 kb
Host smart-95cf9923-1d02-401b-9b16-99d19b0241dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33694
8749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.336948749
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3149181493
Short name T416
Test name
Test status
Simulation time 356393651 ps
CPU time 2.31 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:53 PM PDT 24
Peak memory 206940 kb
Host smart-c28b86e8-ecc0-4690-a21c-8bfd4ece2410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31491
81493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3149181493
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1595305341
Short name T1414
Test name
Test status
Simulation time 218493206 ps
CPU time 0.89 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206868 kb
Host smart-62ef7ecf-253d-40e4-a7cb-6faea34f7059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15953
05341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1595305341
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1393112815
Short name T1081
Test name
Test status
Simulation time 149800595 ps
CPU time 0.82 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206888 kb
Host smart-b7440afa-8d00-401e-83a6-986c977dc903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13931
12815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1393112815
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1132624361
Short name T623
Test name
Test status
Simulation time 306860709 ps
CPU time 0.97 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206884 kb
Host smart-61bbebcb-9f46-418f-94bc-f97ddf7150df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326
24361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1132624361
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.2024488814
Short name T1796
Test name
Test status
Simulation time 4311210187 ps
CPU time 13.49 seconds
Started Jul 13 07:13:50 PM PDT 24
Finished Jul 13 07:14:05 PM PDT 24
Peak memory 207136 kb
Host smart-6c28cd04-dd61-46d1-80b5-c1dcba2c05de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244
88814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.2024488814
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3149597423
Short name T1323
Test name
Test status
Simulation time 196752064 ps
CPU time 0.88 seconds
Started Jul 13 07:13:52 PM PDT 24
Finished Jul 13 07:13:54 PM PDT 24
Peak memory 206812 kb
Host smart-76223636-32bd-4076-b773-f7ea39fdf35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
97423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3149597423
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.793454415
Short name T1632
Test name
Test status
Simulation time 23352327255 ps
CPU time 23.82 seconds
Started Jul 13 07:13:50 PM PDT 24
Finished Jul 13 07:14:16 PM PDT 24
Peak memory 206904 kb
Host smart-f5185099-8528-4604-a3c4-632c277714d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79345
4415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.793454415
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2765964468
Short name T1015
Test name
Test status
Simulation time 3333498231 ps
CPU time 3.69 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206944 kb
Host smart-b28b7acb-5d18-401b-80dc-5a7ecf429654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659
64468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2765964468
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.104703528
Short name T1843
Test name
Test status
Simulation time 10771030676 ps
CPU time 308.47 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:19:01 PM PDT 24
Peak memory 207120 kb
Host smart-2145738f-1eec-49ce-829a-55474853158f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10470
3528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.104703528
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3923219767
Short name T2243
Test name
Test status
Simulation time 5072532837 ps
CPU time 49.12 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 207116 kb
Host smart-c9fabfeb-6bef-4089-824f-d7035b59a9fe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3923219767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3923219767
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.704852806
Short name T710
Test name
Test status
Simulation time 251590241 ps
CPU time 0.91 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:13:54 PM PDT 24
Peak memory 206860 kb
Host smart-daaad0c6-629e-434c-8c1f-43afe1d5b022
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=704852806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.704852806
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.906645804
Short name T1062
Test name
Test status
Simulation time 192540953 ps
CPU time 0.86 seconds
Started Jul 13 07:13:47 PM PDT 24
Finished Jul 13 07:13:49 PM PDT 24
Peak memory 206892 kb
Host smart-b2138631-2b3e-4779-a54b-152b40dcbfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90664
5804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.906645804
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.3638900894
Short name T2738
Test name
Test status
Simulation time 4914217957 ps
CPU time 35.2 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:14:22 PM PDT 24
Peak memory 207132 kb
Host smart-f7af3258-8a2f-4166-b366-9b78c9a8a398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36389
00894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.3638900894
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1225583747
Short name T2675
Test name
Test status
Simulation time 5213418072 ps
CPU time 50.19 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 207116 kb
Host smart-40646aee-b2b2-4319-88be-cc52d27621b9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1225583747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1225583747
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2884562466
Short name T1681
Test name
Test status
Simulation time 162765292 ps
CPU time 0.8 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206868 kb
Host smart-38355be1-a633-4877-a018-57834f346d2e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2884562466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2884562466
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1124198556
Short name T2116
Test name
Test status
Simulation time 145436477 ps
CPU time 0.74 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206896 kb
Host smart-e9000220-d273-4734-a6b7-24c053f3fae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11241
98556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1124198556
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3249505886
Short name T128
Test name
Test status
Simulation time 209430440 ps
CPU time 0.9 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206868 kb
Host smart-334a470e-64a6-4655-9ee5-b2ea40796e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32495
05886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3249505886
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.4091282479
Short name T93
Test name
Test status
Simulation time 178035666 ps
CPU time 0.84 seconds
Started Jul 13 07:13:53 PM PDT 24
Finished Jul 13 07:13:56 PM PDT 24
Peak memory 206880 kb
Host smart-a2925f97-7d54-4050-bc9d-1469c1433a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912
82479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.4091282479
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1741651999
Short name T1753
Test name
Test status
Simulation time 162118178 ps
CPU time 0.82 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206808 kb
Host smart-3c68c440-fbdb-4f3c-859a-faf9cc5a2c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
51999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1741651999
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.4264413008
Short name T2198
Test name
Test status
Simulation time 187759452 ps
CPU time 0.8 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206904 kb
Host smart-a01188bc-41d8-419c-a623-23402b566e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42644
13008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.4264413008
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.4267818292
Short name T2627
Test name
Test status
Simulation time 166809264 ps
CPU time 0.83 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206908 kb
Host smart-092b867d-dbdc-472b-83e1-027b02d9fb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42678
18292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.4267818292
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2023960279
Short name T1291
Test name
Test status
Simulation time 203744444 ps
CPU time 0.94 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206868 kb
Host smart-a01e4155-b0c8-4963-ad03-ab2c57220e5a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2023960279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2023960279
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.982511220
Short name T308
Test name
Test status
Simulation time 141595331 ps
CPU time 0.79 seconds
Started Jul 13 07:13:45 PM PDT 24
Finished Jul 13 07:13:47 PM PDT 24
Peak memory 206876 kb
Host smart-d08cd851-1e49-46e9-bfc0-80cc6438159b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98251
1220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.982511220
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.153838845
Short name T2054
Test name
Test status
Simulation time 14457805771 ps
CPU time 33.05 seconds
Started Jul 13 07:13:47 PM PDT 24
Finished Jul 13 07:14:22 PM PDT 24
Peak memory 207024 kb
Host smart-6a43ff22-c5e8-4a50-81ed-dd27a6f3cf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15383
8845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.153838845
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.305322335
Short name T808
Test name
Test status
Simulation time 180757102 ps
CPU time 0.85 seconds
Started Jul 13 07:13:53 PM PDT 24
Finished Jul 13 07:13:56 PM PDT 24
Peak memory 206880 kb
Host smart-63a7848c-2630-44d4-adbd-17c37a2bbb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
2335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.305322335
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.4203937416
Short name T1357
Test name
Test status
Simulation time 221229139 ps
CPU time 0.86 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206896 kb
Host smart-a3927aea-7286-420b-8ca7-df628c65aa36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42039
37416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.4203937416
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2437504240
Short name T1028
Test name
Test status
Simulation time 212666235 ps
CPU time 0.84 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:13:48 PM PDT 24
Peak memory 206880 kb
Host smart-3255fb3f-ceae-4c42-8356-467d2f2279bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24375
04240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2437504240
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.1231846303
Short name T1792
Test name
Test status
Simulation time 185158589 ps
CPU time 0.88 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:13:54 PM PDT 24
Peak memory 206816 kb
Host smart-c05faf42-abed-446b-997f-bff4a95c9e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12318
46303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1231846303
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.234334408
Short name T1288
Test name
Test status
Simulation time 209968579 ps
CPU time 0.88 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206868 kb
Host smart-eb14ccba-e5e9-44a2-9b6b-d703bdef46b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23433
4408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.234334408
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.4025213711
Short name T511
Test name
Test status
Simulation time 196881970 ps
CPU time 0.81 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:13:48 PM PDT 24
Peak memory 206860 kb
Host smart-c70be8ba-9dec-400d-bdac-d8fc989a2a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40252
13711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.4025213711
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.161196520
Short name T1585
Test name
Test status
Simulation time 155100990 ps
CPU time 0.81 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 206896 kb
Host smart-bd58cdb0-6e30-46b8-8e89-93ec53d43684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
6520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.161196520
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2864420755
Short name T1543
Test name
Test status
Simulation time 284293213 ps
CPU time 1.01 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206864 kb
Host smart-f66d0f14-97a9-41c3-8bd6-b7677e51e481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
20755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2864420755
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3002208794
Short name T529
Test name
Test status
Simulation time 5127561773 ps
CPU time 35.68 seconds
Started Jul 13 07:13:47 PM PDT 24
Finished Jul 13 07:14:24 PM PDT 24
Peak memory 207116 kb
Host smart-fe530410-b49d-46ec-a29b-091f11c02bcd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3002208794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3002208794
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3702102492
Short name T684
Test name
Test status
Simulation time 162160467 ps
CPU time 0.79 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:13:54 PM PDT 24
Peak memory 206872 kb
Host smart-3bdbd604-7853-4b0c-9b6e-3cbb3f543033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37021
02492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3702102492
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.426004977
Short name T399
Test name
Test status
Simulation time 164356851 ps
CPU time 0.77 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:13:48 PM PDT 24
Peak memory 206880 kb
Host smart-f3e772ee-2340-4c80-9306-5cf1ea4137a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42600
4977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.426004977
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1561510646
Short name T2390
Test name
Test status
Simulation time 758150105 ps
CPU time 1.79 seconds
Started Jul 13 07:13:47 PM PDT 24
Finished Jul 13 07:13:50 PM PDT 24
Peak memory 207048 kb
Host smart-c07021e9-7b31-4b2b-8cf8-73ae4804b31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15615
10646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1561510646
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.21547136
Short name T663
Test name
Test status
Simulation time 5244057254 ps
CPU time 141.32 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 207084 kb
Host smart-0edf691d-26f5-4984-8221-c7c97ad17182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21547
136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.21547136
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2583487379
Short name T2354
Test name
Test status
Simulation time 37302001 ps
CPU time 0.68 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:13:57 PM PDT 24
Peak memory 206928 kb
Host smart-4c7b116d-d49f-4650-8b62-eb06da0e75cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2583487379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2583487379
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2279278705
Short name T2050
Test name
Test status
Simulation time 3788396228 ps
CPU time 4.22 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:54 PM PDT 24
Peak memory 207292 kb
Host smart-f4ce29b5-d8eb-4856-bc80-fff7c63d5bb9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2279278705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2279278705
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2530121491
Short name T1331
Test name
Test status
Simulation time 13333068282 ps
CPU time 12.26 seconds
Started Jul 13 07:13:49 PM PDT 24
Finished Jul 13 07:14:03 PM PDT 24
Peak memory 206944 kb
Host smart-0a676d99-3943-4b26-981a-bc0e6c1a3e80
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2530121491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2530121491
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3166061449
Short name T1244
Test name
Test status
Simulation time 23337014138 ps
CPU time 22.29 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:14:16 PM PDT 24
Peak memory 207096 kb
Host smart-1202069f-8629-4025-83b3-009161cf68ee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3166061449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.3166061449
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2205679417
Short name T287
Test name
Test status
Simulation time 182144897 ps
CPU time 0.85 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:13:48 PM PDT 24
Peak memory 206860 kb
Host smart-f84d7dbd-973f-4faa-a219-94863a65282f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22056
79417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2205679417
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2682713172
Short name T1839
Test name
Test status
Simulation time 143359788 ps
CPU time 0.78 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:13:54 PM PDT 24
Peak memory 206828 kb
Host smart-36435ad7-6c83-401f-907a-4bd41d1aa7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26827
13172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2682713172
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3358435502
Short name T2471
Test name
Test status
Simulation time 352181131 ps
CPU time 1.18 seconds
Started Jul 13 07:13:47 PM PDT 24
Finished Jul 13 07:13:50 PM PDT 24
Peak memory 206864 kb
Host smart-81954e3b-006e-4546-b2c2-e4bcdcd5fb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33584
35502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3358435502
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1781824839
Short name T758
Test name
Test status
Simulation time 879672710 ps
CPU time 2.08 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:13:55 PM PDT 24
Peak memory 207028 kb
Host smart-9288df15-e8de-45d7-b036-bf8c60f3df54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
24839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1781824839
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1495361552
Short name T163
Test name
Test status
Simulation time 10257375302 ps
CPU time 22.54 seconds
Started Jul 13 07:13:51 PM PDT 24
Finished Jul 13 07:14:16 PM PDT 24
Peak memory 207136 kb
Host smart-194a12eb-9d26-46be-b070-358265ffa68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14953
61552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1495361552
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.2619924433
Short name T1672
Test name
Test status
Simulation time 313333186 ps
CPU time 1.17 seconds
Started Jul 13 07:13:47 PM PDT 24
Finished Jul 13 07:13:49 PM PDT 24
Peak memory 206872 kb
Host smart-f976fbe8-708d-44fd-9eba-659d56278234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26199
24433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.2619924433
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3613013838
Short name T607
Test name
Test status
Simulation time 173548476 ps
CPU time 0.81 seconds
Started Jul 13 07:13:52 PM PDT 24
Finished Jul 13 07:13:54 PM PDT 24
Peak memory 206816 kb
Host smart-6d5d7c89-6f5b-4a2c-86cb-0f1f3bbec40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36130
13838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3613013838
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3012709692
Short name T2062
Test name
Test status
Simulation time 38930121 ps
CPU time 0.71 seconds
Started Jul 13 07:13:52 PM PDT 24
Finished Jul 13 07:13:55 PM PDT 24
Peak memory 206852 kb
Host smart-98366783-d76f-4fe0-9ebc-2ab83bcecbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30127
09692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3012709692
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3139108125
Short name T1705
Test name
Test status
Simulation time 935113512 ps
CPU time 2.32 seconds
Started Jul 13 07:13:46 PM PDT 24
Finished Jul 13 07:13:50 PM PDT 24
Peak memory 207004 kb
Host smart-3f8df67f-b63a-4ba6-956b-90d72c0d2d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31391
08125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3139108125
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1014051966
Short name T2687
Test name
Test status
Simulation time 282773717 ps
CPU time 1.78 seconds
Started Jul 13 07:13:48 PM PDT 24
Finished Jul 13 07:13:51 PM PDT 24
Peak memory 206872 kb
Host smart-a8b88515-5d09-4a00-8946-351825b4cd15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10140
51966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1014051966
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1694427918
Short name T2358
Test name
Test status
Simulation time 181326182 ps
CPU time 0.84 seconds
Started Jul 13 07:13:52 PM PDT 24
Finished Jul 13 07:13:55 PM PDT 24
Peak memory 206812 kb
Host smart-2a0edfb4-251f-4442-9415-bc49df5985cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16944
27918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1694427918
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2181823860
Short name T2223
Test name
Test status
Simulation time 147454334 ps
CPU time 0.8 seconds
Started Jul 13 07:13:50 PM PDT 24
Finished Jul 13 07:13:53 PM PDT 24
Peak memory 206872 kb
Host smart-168e279a-848e-448c-8f8c-7db55074d3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21818
23860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2181823860
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2268583024
Short name T1330
Test name
Test status
Simulation time 190326408 ps
CPU time 0.87 seconds
Started Jul 13 07:13:55 PM PDT 24
Finished Jul 13 07:13:58 PM PDT 24
Peak memory 206804 kb
Host smart-bfef1d99-6432-4c4b-8434-8dfd3adbb7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
83024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2268583024
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.2371247065
Short name T593
Test name
Test status
Simulation time 7149059785 ps
CPU time 59 seconds
Started Jul 13 07:13:56 PM PDT 24
Finished Jul 13 07:14:57 PM PDT 24
Peak memory 207132 kb
Host smart-6bb19b83-e552-4567-8338-52bf1a5b57d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23712
47065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.2371247065
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.911849254
Short name T2571
Test name
Test status
Simulation time 174439073 ps
CPU time 0.87 seconds
Started Jul 13 07:13:55 PM PDT 24
Finished Jul 13 07:13:58 PM PDT 24
Peak memory 206864 kb
Host smart-522ea28b-9b65-40c2-9f3d-b8b3543c6440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91184
9254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.911849254
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.1669955811
Short name T1896
Test name
Test status
Simulation time 23274598730 ps
CPU time 22.28 seconds
Started Jul 13 07:13:55 PM PDT 24
Finished Jul 13 07:14:20 PM PDT 24
Peak memory 206928 kb
Host smart-fd47f768-0634-4ab0-90ff-605a5680131c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16699
55811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1669955811
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2796839902
Short name T2301
Test name
Test status
Simulation time 3285975757 ps
CPU time 3.98 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 206864 kb
Host smart-eb5e8eb5-c666-453d-8ed0-cdc06a0e1282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968
39902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2796839902
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2765953392
Short name T2586
Test name
Test status
Simulation time 11719618308 ps
CPU time 330.29 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:19:27 PM PDT 24
Peak memory 207168 kb
Host smart-b5e30542-6aac-4d5a-984a-79422837764a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659
53392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2765953392
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1520026044
Short name T2670
Test name
Test status
Simulation time 6768017016 ps
CPU time 63.88 seconds
Started Jul 13 07:14:01 PM PDT 24
Finished Jul 13 07:15:06 PM PDT 24
Peak memory 207124 kb
Host smart-d3717ac5-e21d-4506-8f5f-274214f3d2e6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1520026044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1520026044
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1079053823
Short name T581
Test name
Test status
Simulation time 239572759 ps
CPU time 0.91 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:13:57 PM PDT 24
Peak memory 206868 kb
Host smart-5c3c1e31-9060-4a55-aaa1-089b6286fdfe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1079053823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1079053823
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2809510660
Short name T790
Test name
Test status
Simulation time 189568602 ps
CPU time 0.91 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206868 kb
Host smart-c329240e-f80d-4e72-9c30-5e09eae7dbc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28095
10660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2809510660
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3441964691
Short name T2567
Test name
Test status
Simulation time 4024486445 ps
CPU time 29.07 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 207164 kb
Host smart-2a5fcab3-3466-4a64-a871-1101982df6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34419
64691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3441964691
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2042715752
Short name T2600
Test name
Test status
Simulation time 4101636473 ps
CPU time 41.31 seconds
Started Jul 13 07:13:53 PM PDT 24
Finished Jul 13 07:14:37 PM PDT 24
Peak memory 207064 kb
Host smart-dad9fbb6-9c87-4690-a232-d863c5339fba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2042715752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2042715752
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3976915225
Short name T1713
Test name
Test status
Simulation time 220835476 ps
CPU time 0.84 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:13:57 PM PDT 24
Peak memory 206868 kb
Host smart-4a501a16-143c-42ca-931f-2786c98b1a80
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3976915225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3976915225
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1883710442
Short name T1866
Test name
Test status
Simulation time 142135358 ps
CPU time 0.79 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:13:57 PM PDT 24
Peak memory 206752 kb
Host smart-1ce0b981-5c0f-4172-8863-f0a1d9af0d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18837
10442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1883710442
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1777331700
Short name T109
Test name
Test status
Simulation time 263266086 ps
CPU time 1.09 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206844 kb
Host smart-59facb8d-3099-4334-b3e5-89991f99ec74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17773
31700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1777331700
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.4164898272
Short name T1157
Test name
Test status
Simulation time 197337321 ps
CPU time 0.89 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:13:57 PM PDT 24
Peak memory 206868 kb
Host smart-0b789d73-bd93-4afe-a0ef-784ee0bfeb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41648
98272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.4164898272
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2229727753
Short name T1921
Test name
Test status
Simulation time 182417276 ps
CPU time 0.82 seconds
Started Jul 13 07:14:04 PM PDT 24
Finished Jul 13 07:14:05 PM PDT 24
Peak memory 206868 kb
Host smart-20bc3912-c2e9-4bb4-afdc-1f0036471155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22297
27753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2229727753
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3714508577
Short name T1057
Test name
Test status
Simulation time 174950534 ps
CPU time 0.85 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 206888 kb
Host smart-341bcb43-b859-47bf-b1b4-7c6cbfcdd62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37145
08577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3714508577
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.4063594688
Short name T2587
Test name
Test status
Simulation time 176698804 ps
CPU time 0.8 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206800 kb
Host smart-c7603d6b-d70e-4e58-bd15-1f3fd5ed3451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40635
94688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.4063594688
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.991391594
Short name T2167
Test name
Test status
Simulation time 226197618 ps
CPU time 0.9 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:13:58 PM PDT 24
Peak memory 206824 kb
Host smart-f65773c2-1336-4665-a64d-84ed3eef3e54
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=991391594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.991391594
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1601527038
Short name T2518
Test name
Test status
Simulation time 143330343 ps
CPU time 0.78 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206856 kb
Host smart-c541c008-1da7-4549-9587-50cdaddeb107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16015
27038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1601527038
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.629255065
Short name T1368
Test name
Test status
Simulation time 33592330 ps
CPU time 0.66 seconds
Started Jul 13 07:13:56 PM PDT 24
Finished Jul 13 07:13:59 PM PDT 24
Peak memory 206836 kb
Host smart-b9b7a8f2-cac2-49fb-836a-d4029491af2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62925
5065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.629255065
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3016726598
Short name T1269
Test name
Test status
Simulation time 15026969865 ps
CPU time 34.69 seconds
Started Jul 13 07:14:01 PM PDT 24
Finished Jul 13 07:14:37 PM PDT 24
Peak memory 207180 kb
Host smart-0dad466c-b609-4e76-84eb-4e3ee51badce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30167
26598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3016726598
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3753117598
Short name T1293
Test name
Test status
Simulation time 168564560 ps
CPU time 0.83 seconds
Started Jul 13 07:13:56 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 206868 kb
Host smart-17c58b0d-6e0e-4d19-bb4c-18b8e7956bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37531
17598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3753117598
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1486571690
Short name T2734
Test name
Test status
Simulation time 192630039 ps
CPU time 0.89 seconds
Started Jul 13 07:13:56 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 206856 kb
Host smart-3ba0d0b6-71d2-4be8-9097-28f0b29ee358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14865
71690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1486571690
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3750728290
Short name T2371
Test name
Test status
Simulation time 185647930 ps
CPU time 0.91 seconds
Started Jul 13 07:13:53 PM PDT 24
Finished Jul 13 07:13:56 PM PDT 24
Peak memory 206868 kb
Host smart-aebb9b60-6d01-4877-9f29-ea52a89db047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37507
28290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3750728290
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.24430216
Short name T2455
Test name
Test status
Simulation time 176474921 ps
CPU time 0.89 seconds
Started Jul 13 07:14:00 PM PDT 24
Finished Jul 13 07:14:02 PM PDT 24
Peak memory 206860 kb
Host smart-3e94131c-6095-4784-a506-d844e775d9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.24430216
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2527728634
Short name T2106
Test name
Test status
Simulation time 154174607 ps
CPU time 0.78 seconds
Started Jul 13 07:14:02 PM PDT 24
Finished Jul 13 07:14:04 PM PDT 24
Peak memory 206876 kb
Host smart-0cac23af-d2d8-4100-8eaa-df4a6c7fd151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25277
28634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2527728634
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2315754358
Short name T762
Test name
Test status
Simulation time 152375246 ps
CPU time 0.75 seconds
Started Jul 13 07:13:53 PM PDT 24
Finished Jul 13 07:13:56 PM PDT 24
Peak memory 206860 kb
Host smart-457e45b7-950a-4be5-8a3c-bee2fe14dae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23157
54358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2315754358
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.105208380
Short name T2279
Test name
Test status
Simulation time 159818253 ps
CPU time 0.81 seconds
Started Jul 13 07:13:56 PM PDT 24
Finished Jul 13 07:13:59 PM PDT 24
Peak memory 206864 kb
Host smart-145626ba-796f-470d-b2d8-3692b5244f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
8380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.105208380
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.734062944
Short name T1004
Test name
Test status
Simulation time 258867335 ps
CPU time 1.02 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206896 kb
Host smart-67b16644-43b2-48ca-aee4-9332fabc0054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73406
2944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.734062944
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.213062925
Short name T2617
Test name
Test status
Simulation time 4383249370 ps
CPU time 122.6 seconds
Started Jul 13 07:13:55 PM PDT 24
Finished Jul 13 07:16:00 PM PDT 24
Peak memory 207088 kb
Host smart-bd39e0b3-7b0a-4d33-8e89-d0c8639b16e8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=213062925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.213062925
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1617403448
Short name T1195
Test name
Test status
Simulation time 201686730 ps
CPU time 0.83 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 206872 kb
Host smart-80d02927-f849-429e-a306-24ac987876ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16174
03448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1617403448
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1236310406
Short name T2671
Test name
Test status
Simulation time 181406282 ps
CPU time 0.82 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206844 kb
Host smart-c583a47c-c271-478f-ba5f-1229dedec906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12363
10406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1236310406
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.983689156
Short name T589
Test name
Test status
Simulation time 1416974167 ps
CPU time 3.18 seconds
Started Jul 13 07:14:00 PM PDT 24
Finished Jul 13 07:14:05 PM PDT 24
Peak memory 206792 kb
Host smart-4c025c86-6a8f-4640-8c0a-7b3bde8a629e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98368
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.983689156
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1745772143
Short name T1545
Test name
Test status
Simulation time 6151486252 ps
CPU time 46.25 seconds
Started Jul 13 07:13:56 PM PDT 24
Finished Jul 13 07:14:45 PM PDT 24
Peak memory 207072 kb
Host smart-9a3fbed9-820f-46d6-8e58-57b33a4718b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17457
72143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1745772143
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2140289327
Short name T2360
Test name
Test status
Simulation time 44341630 ps
CPU time 0.69 seconds
Started Jul 13 07:14:05 PM PDT 24
Finished Jul 13 07:14:07 PM PDT 24
Peak memory 206904 kb
Host smart-efa5317f-9b57-4058-8976-012781f4fb84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2140289327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2140289327
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1509886572
Short name T894
Test name
Test status
Simulation time 4364105679 ps
CPU time 5.67 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:06 PM PDT 24
Peak memory 206912 kb
Host smart-9ece462a-8f14-4c5f-a2a7-b3e8a0da0e07
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1509886572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1509886572
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1176177669
Short name T2221
Test name
Test status
Simulation time 13316355644 ps
CPU time 15.06 seconds
Started Jul 13 07:13:55 PM PDT 24
Finished Jul 13 07:14:13 PM PDT 24
Peak memory 206928 kb
Host smart-460b045f-8785-4bcb-b27c-6e0a938ed160
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1176177669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1176177669
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2018139281
Short name T1249
Test name
Test status
Simulation time 23368685798 ps
CPU time 24.7 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:25 PM PDT 24
Peak memory 207108 kb
Host smart-df36a24b-a54b-4a27-97ce-5ed716905310
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2018139281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.2018139281
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3605877894
Short name T1393
Test name
Test status
Simulation time 180776329 ps
CPU time 0.82 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206796 kb
Host smart-6727a6e0-20f7-4d50-b9de-71f368b57795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36058
77894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3605877894
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.165303698
Short name T2219
Test name
Test status
Simulation time 166000853 ps
CPU time 0.77 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:13:57 PM PDT 24
Peak memory 206880 kb
Host smart-e9047d94-cbe0-4e3a-b510-7e5f1120030c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16530
3698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.165303698
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2202388821
Short name T875
Test name
Test status
Simulation time 339765757 ps
CPU time 1.31 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206864 kb
Host smart-952408c7-ba42-4bcb-bb28-8ebd83696392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22023
88821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2202388821
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3542515623
Short name T832
Test name
Test status
Simulation time 1247301479 ps
CPU time 3.07 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:03 PM PDT 24
Peak memory 207040 kb
Host smart-4a35bb13-cfe0-4b04-a178-e97d2f1305ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35425
15623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3542515623
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.1982783796
Short name T619
Test name
Test status
Simulation time 19764813897 ps
CPU time 41.51 seconds
Started Jul 13 07:13:55 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 207080 kb
Host smart-4c5b41c7-8d57-4b5c-8c41-ab6df340a3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19827
83796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1982783796
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1166451207
Short name T823
Test name
Test status
Simulation time 419939870 ps
CPU time 1.41 seconds
Started Jul 13 07:13:56 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 207112 kb
Host smart-99ed0dd9-6db2-4765-b9a7-7950b77c50c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11664
51207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1166451207
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.4049150520
Short name T2561
Test name
Test status
Simulation time 134848148 ps
CPU time 0.76 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206844 kb
Host smart-64e3b913-05ba-4aca-b63d-fd41b44320f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40491
50520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.4049150520
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1064132328
Short name T464
Test name
Test status
Simulation time 39961071 ps
CPU time 0.71 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 206848 kb
Host smart-09e05ce1-b226-4949-855e-178a846c8b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10641
32328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1064132328
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.468445169
Short name T1612
Test name
Test status
Simulation time 829147469 ps
CPU time 1.98 seconds
Started Jul 13 07:13:54 PM PDT 24
Finished Jul 13 07:13:59 PM PDT 24
Peak memory 207000 kb
Host smart-0811ae00-7011-4b29-b7ff-773ce075375c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46844
5169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.468445169
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3843993521
Short name T1810
Test name
Test status
Simulation time 163286284 ps
CPU time 1.36 seconds
Started Jul 13 07:13:59 PM PDT 24
Finished Jul 13 07:14:02 PM PDT 24
Peak memory 207008 kb
Host smart-2f1178b3-394d-486b-a7c7-98e88103616b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38439
93521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3843993521
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1629404108
Short name T2143
Test name
Test status
Simulation time 244034376 ps
CPU time 0.91 seconds
Started Jul 13 07:13:53 PM PDT 24
Finished Jul 13 07:13:57 PM PDT 24
Peak memory 206864 kb
Host smart-a0a31eb3-692a-4499-973c-8d943abe2543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16294
04108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1629404108
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2688001376
Short name T2541
Test name
Test status
Simulation time 149977493 ps
CPU time 0.75 seconds
Started Jul 13 07:13:56 PM PDT 24
Finished Jul 13 07:14:00 PM PDT 24
Peak memory 206860 kb
Host smart-68008b8b-866a-4e78-abe0-d64f7de861ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26880
01376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2688001376
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2313433032
Short name T1321
Test name
Test status
Simulation time 236269939 ps
CPU time 0.94 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:01 PM PDT 24
Peak memory 206872 kb
Host smart-1869edca-a274-4350-835b-34cf73b4a628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23134
33032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2313433032
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3533834696
Short name T2512
Test name
Test status
Simulation time 6481934085 ps
CPU time 63.43 seconds
Started Jul 13 07:14:01 PM PDT 24
Finished Jul 13 07:15:06 PM PDT 24
Peak memory 207076 kb
Host smart-bb197f5a-1ead-445d-bd6c-7ff69af525a3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3533834696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3533834696
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.3756073744
Short name T2506
Test name
Test status
Simulation time 11632034294 ps
CPU time 37 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 207092 kb
Host smart-897562ff-cffd-401e-ac9c-93a91b0a32c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37560
73744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.3756073744
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3905134149
Short name T1740
Test name
Test status
Simulation time 217442552 ps
CPU time 0.88 seconds
Started Jul 13 07:14:01 PM PDT 24
Finished Jul 13 07:14:04 PM PDT 24
Peak memory 206884 kb
Host smart-9d97d5b7-e971-41ad-8fe8-a7a88d427052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39051
34149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3905134149
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2498595448
Short name T707
Test name
Test status
Simulation time 23361091569 ps
CPU time 23.56 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:14:24 PM PDT 24
Peak memory 206936 kb
Host smart-3b40984b-5e95-460e-8e86-b17ac2c0abb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24985
95448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2498595448
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.622108844
Short name T1512
Test name
Test status
Simulation time 3310924262 ps
CPU time 3.54 seconds
Started Jul 13 07:13:58 PM PDT 24
Finished Jul 13 07:14:04 PM PDT 24
Peak memory 206964 kb
Host smart-4bf5ce9b-0cce-4c4f-9a75-970a6f99a934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62210
8844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.622108844
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2812923169
Short name T88
Test name
Test status
Simulation time 6478394569 ps
CPU time 183.24 seconds
Started Jul 13 07:14:01 PM PDT 24
Finished Jul 13 07:17:05 PM PDT 24
Peak memory 207160 kb
Host smart-14d0a004-d313-45ea-b061-a22b29c94166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28129
23169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2812923169
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.174294008
Short name T1318
Test name
Test status
Simulation time 5127710350 ps
CPU time 142.79 seconds
Started Jul 13 07:13:57 PM PDT 24
Finished Jul 13 07:16:22 PM PDT 24
Peak memory 207104 kb
Host smart-750b89b6-66d2-4091-a693-0513b92b54cf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=174294008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.174294008
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1908607472
Short name T439
Test name
Test status
Simulation time 269008845 ps
CPU time 0.93 seconds
Started Jul 13 07:14:00 PM PDT 24
Finished Jul 13 07:14:03 PM PDT 24
Peak memory 206860 kb
Host smart-a50ef9ef-2a2a-4150-87c7-07a75b4a02f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1908607472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1908607472
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1606672878
Short name T910
Test name
Test status
Simulation time 206425553 ps
CPU time 0.82 seconds
Started Jul 13 07:14:01 PM PDT 24
Finished Jul 13 07:14:03 PM PDT 24
Peak memory 206840 kb
Host smart-15493256-df83-4787-a84f-b50190f7e190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16066
72878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1606672878
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3528885614
Short name T2536
Test name
Test status
Simulation time 4480138181 ps
CPU time 31.74 seconds
Started Jul 13 07:14:01 PM PDT 24
Finished Jul 13 07:14:34 PM PDT 24
Peak memory 207136 kb
Host smart-698adbfd-eb1e-42e0-ad03-5c240f1239f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35288
85614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3528885614
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.3356207751
Short name T2140
Test name
Test status
Simulation time 5340795085 ps
CPU time 37.84 seconds
Started Jul 13 07:14:02 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 207096 kb
Host smart-147f0bd3-e7f5-45f1-be46-586c84a5d5fd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3356207751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3356207751
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3357471398
Short name T2040
Test name
Test status
Simulation time 152547270 ps
CPU time 0.83 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206876 kb
Host smart-9c224725-15c0-43c6-8da9-8e5f62843c81
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3357471398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3357471398
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.4151675889
Short name T732
Test name
Test status
Simulation time 163376363 ps
CPU time 0.77 seconds
Started Jul 13 07:14:06 PM PDT 24
Finished Jul 13 07:14:08 PM PDT 24
Peak memory 207052 kb
Host smart-a81d1181-e01e-4c8b-a64c-5d896d65ead0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41516
75889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.4151675889
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.356994708
Short name T2102
Test name
Test status
Simulation time 187589403 ps
CPU time 0.95 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 207104 kb
Host smart-dfb8988e-3e51-497e-a7a0-e5b07a183a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35699
4708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.356994708
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.705818902
Short name T1523
Test name
Test status
Simulation time 199984932 ps
CPU time 0.86 seconds
Started Jul 13 07:14:06 PM PDT 24
Finished Jul 13 07:14:08 PM PDT 24
Peak memory 206864 kb
Host smart-49087dc0-2e64-473a-be0e-7c4030d3cfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70581
8902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.705818902
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.692463111
Short name T1841
Test name
Test status
Simulation time 168982546 ps
CPU time 0.8 seconds
Started Jul 13 07:14:11 PM PDT 24
Finished Jul 13 07:14:13 PM PDT 24
Peak memory 206864 kb
Host smart-df7f13a4-c0c9-43ff-9fdf-1e92067000be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69246
3111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.692463111
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.885548370
Short name T2177
Test name
Test status
Simulation time 156806843 ps
CPU time 0.8 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206808 kb
Host smart-8055157f-d78b-4389-bfb0-3908834abd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88554
8370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.885548370
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2465514496
Short name T1684
Test name
Test status
Simulation time 251341650 ps
CPU time 1.02 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206644 kb
Host smart-65931dab-6180-4deb-9ec4-193175b149dd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2465514496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2465514496
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3290112922
Short name T379
Test name
Test status
Simulation time 187180847 ps
CPU time 0.82 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206856 kb
Host smart-f9f3c83a-55e4-4204-ae1c-9670ffbb6d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32901
12922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3290112922
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3073696091
Short name T1876
Test name
Test status
Simulation time 43882897 ps
CPU time 0.67 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206864 kb
Host smart-66b8257c-98c7-4e95-83a0-e6d033687e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30736
96091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3073696091
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1711831508
Short name T2284
Test name
Test status
Simulation time 12680124377 ps
CPU time 27.52 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 207160 kb
Host smart-426eb1a9-17bd-4ba1-929d-1c6dab3ef5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17118
31508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1711831508
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2348101115
Short name T1944
Test name
Test status
Simulation time 185064439 ps
CPU time 0.85 seconds
Started Jul 13 07:14:05 PM PDT 24
Finished Jul 13 07:14:07 PM PDT 24
Peak memory 206804 kb
Host smart-988b350d-f7b5-44b9-8a0e-c3aaf97bb13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
01115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2348101115
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1320253009
Short name T1818
Test name
Test status
Simulation time 199608224 ps
CPU time 0.84 seconds
Started Jul 13 07:14:05 PM PDT 24
Finished Jul 13 07:14:06 PM PDT 24
Peak memory 206872 kb
Host smart-ee6e62fb-7856-4224-8c22-97ba05c7613f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13202
53009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1320253009
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2836382961
Short name T638
Test name
Test status
Simulation time 220913404 ps
CPU time 0.93 seconds
Started Jul 13 07:14:10 PM PDT 24
Finished Jul 13 07:14:12 PM PDT 24
Peak memory 206632 kb
Host smart-5a85fe20-ba44-4051-aea3-eed777aecf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28363
82961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2836382961
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.1377735061
Short name T2451
Test name
Test status
Simulation time 172617049 ps
CPU time 0.81 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 206900 kb
Host smart-5dbe6d7d-c649-4d14-8e0b-056603217fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13777
35061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.1377735061
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2660945534
Short name T656
Test name
Test status
Simulation time 142605796 ps
CPU time 0.76 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:09 PM PDT 24
Peak memory 206872 kb
Host smart-fd5f86f3-ea12-4c1c-bca7-dc07a56004b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26609
45534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2660945534
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3637599983
Short name T1263
Test name
Test status
Simulation time 152873870 ps
CPU time 0.76 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206852 kb
Host smart-c7189717-b7b4-4755-be71-99e932522fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36375
99983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3637599983
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2779200974
Short name T1541
Test name
Test status
Simulation time 181893344 ps
CPU time 0.78 seconds
Started Jul 13 07:14:10 PM PDT 24
Finished Jul 13 07:14:12 PM PDT 24
Peak memory 206880 kb
Host smart-06d32849-3bf1-4620-8778-cdf51951fadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27792
00974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2779200974
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3375998963
Short name T1519
Test name
Test status
Simulation time 249859588 ps
CPU time 0.96 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 206864 kb
Host smart-95636ed7-094b-4b5f-bce3-ef7f069a70f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33759
98963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3375998963
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.3996502241
Short name T541
Test name
Test status
Simulation time 6256364977 ps
CPU time 58.23 seconds
Started Jul 13 07:14:06 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 207052 kb
Host smart-2a111f86-9475-42ce-b2cb-e868b5a156a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3996502241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.3996502241
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1131448664
Short name T979
Test name
Test status
Simulation time 187525600 ps
CPU time 0.9 seconds
Started Jul 13 07:14:09 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 206848 kb
Host smart-232f0be2-4b6e-463c-8057-e4c915f2e242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11314
48664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1131448664
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.440889567
Short name T1112
Test name
Test status
Simulation time 156631960 ps
CPU time 0.83 seconds
Started Jul 13 07:14:11 PM PDT 24
Finished Jul 13 07:14:13 PM PDT 24
Peak memory 206812 kb
Host smart-518acb8f-406e-4094-a2ad-1cf452194340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44088
9567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.440889567
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.1920228620
Short name T2744
Test name
Test status
Simulation time 1167714154 ps
CPU time 2.4 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 207068 kb
Host smart-9216af2b-6bdd-408b-a1f1-dd9c48973702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19202
28620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.1920228620
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2415692590
Short name T1945
Test name
Test status
Simulation time 5411573493 ps
CPU time 51.09 seconds
Started Jul 13 07:14:12 PM PDT 24
Finished Jul 13 07:15:04 PM PDT 24
Peak memory 207132 kb
Host smart-d07637dd-90f1-4edc-8fa4-40dd99af69a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24156
92590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2415692590
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.1933057734
Short name T2434
Test name
Test status
Simulation time 27490679 ps
CPU time 0.66 seconds
Started Jul 13 07:14:16 PM PDT 24
Finished Jul 13 07:14:18 PM PDT 24
Peak memory 206920 kb
Host smart-75d90d5f-1ffa-476d-920b-c96b3b0ba617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1933057734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1933057734
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1171859958
Short name T1937
Test name
Test status
Simulation time 3574779141 ps
CPU time 4.57 seconds
Started Jul 13 07:14:10 PM PDT 24
Finished Jul 13 07:14:16 PM PDT 24
Peak memory 207140 kb
Host smart-15a9ec05-c227-4c03-83dd-f32000b7e00b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1171859958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1171859958
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3805624561
Short name T1882
Test name
Test status
Simulation time 13317783629 ps
CPU time 14.49 seconds
Started Jul 13 07:14:06 PM PDT 24
Finished Jul 13 07:14:22 PM PDT 24
Peak memory 207156 kb
Host smart-63f649bd-a7d9-42a5-8dbb-083e3dbb2ea1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3805624561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3805624561
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3925338707
Short name T2423
Test name
Test status
Simulation time 23450056061 ps
CPU time 22.49 seconds
Started Jul 13 07:14:10 PM PDT 24
Finished Jul 13 07:14:34 PM PDT 24
Peak memory 207132 kb
Host smart-6449d411-880c-42f2-8ef5-d398c3966c6a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3925338707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3925338707
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2242701225
Short name T2393
Test name
Test status
Simulation time 153679881 ps
CPU time 0.76 seconds
Started Jul 13 07:14:05 PM PDT 24
Finished Jul 13 07:14:06 PM PDT 24
Peak memory 206864 kb
Host smart-a0bdb821-84d2-47c7-b905-de711257d20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22427
01225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2242701225
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.4070087773
Short name T2614
Test name
Test status
Simulation time 179198841 ps
CPU time 0.82 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:09 PM PDT 24
Peak memory 206868 kb
Host smart-34a42d1d-efab-4ca7-a7fb-9b917ccccaf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40700
87773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.4070087773
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3286500710
Short name T553
Test name
Test status
Simulation time 359820034 ps
CPU time 1.21 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 206844 kb
Host smart-4cc22d87-9edd-40f9-8d2e-39f01cc3e615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32865
00710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3286500710
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3587343930
Short name T931
Test name
Test status
Simulation time 448928564 ps
CPU time 1.24 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206856 kb
Host smart-cc130cf9-7c2a-4e54-9afa-d55834415eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
43930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3587343930
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3259209286
Short name T2185
Test name
Test status
Simulation time 12951411030 ps
CPU time 25.13 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:34 PM PDT 24
Peak memory 207136 kb
Host smart-1704f65f-0e76-470c-9456-61e40f07a3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32592
09286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3259209286
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1464364964
Short name T347
Test name
Test status
Simulation time 425581031 ps
CPU time 1.33 seconds
Started Jul 13 07:14:06 PM PDT 24
Finished Jul 13 07:14:09 PM PDT 24
Peak memory 206860 kb
Host smart-83155c50-93cd-4e2a-9e18-a3e57b602806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14643
64964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1464364964
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.548031705
Short name T2084
Test name
Test status
Simulation time 142961062 ps
CPU time 0.78 seconds
Started Jul 13 07:14:05 PM PDT 24
Finished Jul 13 07:14:07 PM PDT 24
Peak memory 206868 kb
Host smart-cc967870-d28b-48cf-8228-1a2e2c49a241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54803
1705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.548031705
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1007516440
Short name T1031
Test name
Test status
Simulation time 39441979 ps
CPU time 0.69 seconds
Started Jul 13 07:14:10 PM PDT 24
Finished Jul 13 07:14:12 PM PDT 24
Peak memory 206536 kb
Host smart-c45a8bfe-e9dd-4251-b8d8-61375334f4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10075
16440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1007516440
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1056140296
Short name T950
Test name
Test status
Simulation time 813849226 ps
CPU time 1.91 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:12 PM PDT 24
Peak memory 207012 kb
Host smart-e090f2bf-b562-4f8b-ad17-36f7f759aec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
40296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1056140296
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.726508633
Short name T165
Test name
Test status
Simulation time 214022223 ps
CPU time 2.11 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 207004 kb
Host smart-e5ef4d72-ab50-40cb-8628-1abd72030bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72650
8633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.726508633
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3372218419
Short name T871
Test name
Test status
Simulation time 188183104 ps
CPU time 0.82 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206632 kb
Host smart-da29cbcf-7d91-446d-ac92-1c76ffe85ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33722
18419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3372218419
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1051179269
Short name T2453
Test name
Test status
Simulation time 146615662 ps
CPU time 0.79 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206848 kb
Host smart-c50e3e17-6733-408b-9635-363199f91818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10511
79269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1051179269
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1279847602
Short name T288
Test name
Test status
Simulation time 192798771 ps
CPU time 0.88 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206844 kb
Host smart-5f56784d-cf4b-4b0b-a25f-8483318e16d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798
47602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1279847602
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.345143701
Short name T98
Test name
Test status
Simulation time 9952621822 ps
CPU time 97.48 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:15:46 PM PDT 24
Peak memory 207108 kb
Host smart-a7c2e2a4-e082-433f-a8c0-7dcd0136b10b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=345143701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.345143701
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.1253115149
Short name T2404
Test name
Test status
Simulation time 5441566958 ps
CPU time 20.82 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:31 PM PDT 24
Peak memory 207080 kb
Host smart-c14176d1-bc01-4f5f-b96d-ce9ecddb56c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12531
15149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.1253115149
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3775235599
Short name T2628
Test name
Test status
Simulation time 182740337 ps
CPU time 0.85 seconds
Started Jul 13 07:14:09 PM PDT 24
Finished Jul 13 07:14:12 PM PDT 24
Peak memory 206864 kb
Host smart-272f6a15-4dae-4d33-8c92-b1425832d5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37752
35599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3775235599
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2414485597
Short name T1041
Test name
Test status
Simulation time 23271070684 ps
CPU time 29.7 seconds
Started Jul 13 07:14:10 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 206924 kb
Host smart-d8c4317b-20b1-422a-9e96-4f8d736574cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24144
85597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2414485597
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3995803155
Short name T2131
Test name
Test status
Simulation time 3271876082 ps
CPU time 3.7 seconds
Started Jul 13 07:14:05 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 206924 kb
Host smart-0d6fc8d5-fd4a-447a-8e4c-1a28ed01f010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39958
03155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3995803155
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1154431240
Short name T1539
Test name
Test status
Simulation time 8462260900 ps
CPU time 78.02 seconds
Started Jul 13 07:14:12 PM PDT 24
Finished Jul 13 07:15:31 PM PDT 24
Peak memory 207136 kb
Host smart-813cb206-2ea8-410c-bfb1-5c861ac2c353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11544
31240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1154431240
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.4281083415
Short name T323
Test name
Test status
Simulation time 5851013461 ps
CPU time 164.29 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 207032 kb
Host smart-450dcc61-d4f7-4ddb-8e6a-8a67c54e7d5f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4281083415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.4281083415
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1312402430
Short name T1691
Test name
Test status
Simulation time 262046194 ps
CPU time 0.92 seconds
Started Jul 13 07:14:06 PM PDT 24
Finished Jul 13 07:14:07 PM PDT 24
Peak memory 206860 kb
Host smart-d887d51d-b803-4adf-a6a7-775871e60846
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1312402430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1312402430
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.775060004
Short name T1394
Test name
Test status
Simulation time 216153271 ps
CPU time 0.91 seconds
Started Jul 13 07:14:07 PM PDT 24
Finished Jul 13 07:14:09 PM PDT 24
Peak memory 206884 kb
Host smart-8d2ae9ed-f503-4b61-8e8d-7af5d18bdedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77506
0004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.775060004
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.347016668
Short name T1000
Test name
Test status
Simulation time 4694039656 ps
CPU time 47.21 seconds
Started Jul 13 07:14:06 PM PDT 24
Finished Jul 13 07:14:55 PM PDT 24
Peak memory 207080 kb
Host smart-c7962155-5443-45b7-8805-2e0d60f46c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34701
6668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.347016668
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1274804804
Short name T520
Test name
Test status
Simulation time 4430524206 ps
CPU time 31.87 seconds
Started Jul 13 07:14:06 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 207080 kb
Host smart-47223de3-b19d-46be-8100-9953726f1473
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1274804804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1274804804
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.3615184678
Short name T730
Test name
Test status
Simulation time 198055607 ps
CPU time 0.87 seconds
Started Jul 13 07:14:08 PM PDT 24
Finished Jul 13 07:14:11 PM PDT 24
Peak memory 206868 kb
Host smart-a9dd2852-d193-495c-83c8-5971770e3150
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3615184678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.3615184678
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.4236494647
Short name T1622
Test name
Test status
Simulation time 142498499 ps
CPU time 0.79 seconds
Started Jul 13 07:14:16 PM PDT 24
Finished Jul 13 07:14:18 PM PDT 24
Peak memory 206912 kb
Host smart-c52ce8d5-295e-4929-ae73-9b50ee060348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364
94647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.4236494647
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2533867008
Short name T1752
Test name
Test status
Simulation time 189260263 ps
CPU time 0.92 seconds
Started Jul 13 07:14:16 PM PDT 24
Finished Jul 13 07:14:18 PM PDT 24
Peak memory 206864 kb
Host smart-00c0f87b-2e4e-4857-923c-561da1b5569e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25338
67008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2533867008
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1017016540
Short name T2074
Test name
Test status
Simulation time 170580303 ps
CPU time 0.8 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:19 PM PDT 24
Peak memory 206820 kb
Host smart-3c5ea99b-bbec-45a5-94ba-a292b3c73d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10170
16540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1017016540
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.409128585
Short name T1797
Test name
Test status
Simulation time 195297578 ps
CPU time 0.86 seconds
Started Jul 13 07:14:16 PM PDT 24
Finished Jul 13 07:14:17 PM PDT 24
Peak memory 206848 kb
Host smart-63178086-63d3-42e1-aeff-30a4b44dbbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912
8585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.409128585
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.4033371764
Short name T282
Test name
Test status
Simulation time 148432323 ps
CPU time 0.79 seconds
Started Jul 13 07:14:16 PM PDT 24
Finished Jul 13 07:14:18 PM PDT 24
Peak memory 206860 kb
Host smart-89a0aa54-aa7c-4c0d-a0a1-0cfd33d64d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40333
71764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.4033371764
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1023989360
Short name T2339
Test name
Test status
Simulation time 163825973 ps
CPU time 0.76 seconds
Started Jul 13 07:14:14 PM PDT 24
Finished Jul 13 07:14:15 PM PDT 24
Peak memory 206808 kb
Host smart-4e13a866-4a54-4c81-bf68-6fe4ed671056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10239
89360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1023989360
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3428521356
Short name T2235
Test name
Test status
Simulation time 210186056 ps
CPU time 0.91 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206864 kb
Host smart-3d3b51be-25b1-46d0-be53-05f0013bd19f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3428521356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3428521356
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3170928390
Short name T223
Test name
Test status
Simulation time 196578667 ps
CPU time 0.82 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:19 PM PDT 24
Peak memory 206864 kb
Host smart-00562ca6-b80f-4cda-a725-a127ed15c5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31709
28390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3170928390
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1385772125
Short name T608
Test name
Test status
Simulation time 104147818 ps
CPU time 0.72 seconds
Started Jul 13 07:14:15 PM PDT 24
Finished Jul 13 07:14:16 PM PDT 24
Peak memory 206872 kb
Host smart-f2cd6ce3-6681-4451-a7c1-c5842778f96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13857
72125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1385772125
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.875529870
Short name T2496
Test name
Test status
Simulation time 16615665698 ps
CPU time 32.87 seconds
Started Jul 13 07:14:15 PM PDT 24
Finished Jul 13 07:14:48 PM PDT 24
Peak memory 207352 kb
Host smart-5cb05862-1a66-496f-8b04-2d8fff365979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87552
9870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.875529870
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.1833306397
Short name T695
Test name
Test status
Simulation time 182548123 ps
CPU time 0.86 seconds
Started Jul 13 07:14:22 PM PDT 24
Finished Jul 13 07:14:23 PM PDT 24
Peak memory 206852 kb
Host smart-ae1121e7-4071-4811-8b34-7db925e7e33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
06397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.1833306397
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2722971321
Short name T2240
Test name
Test status
Simulation time 208441364 ps
CPU time 0.89 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206864 kb
Host smart-95193d72-32fb-4ecc-bf5b-6e5544d02f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27229
71321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2722971321
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2392650780
Short name T2248
Test name
Test status
Simulation time 207630082 ps
CPU time 0.93 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:28 PM PDT 24
Peak memory 206872 kb
Host smart-1ed4a0db-08f8-4d9a-918d-ca6b5413f681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23926
50780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2392650780
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.463477184
Short name T1749
Test name
Test status
Simulation time 151244454 ps
CPU time 0.79 seconds
Started Jul 13 07:14:19 PM PDT 24
Finished Jul 13 07:14:21 PM PDT 24
Peak memory 206812 kb
Host smart-6da1d750-bf3a-4e23-bcac-ce996611ffec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46347
7184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.463477184
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3627840758
Short name T1917
Test name
Test status
Simulation time 183673156 ps
CPU time 0.83 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:28 PM PDT 24
Peak memory 206860 kb
Host smart-a439855d-4f58-4d4e-b054-284e46c8e410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36278
40758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3627840758
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3555066461
Short name T1927
Test name
Test status
Simulation time 153366489 ps
CPU time 0.77 seconds
Started Jul 13 07:14:15 PM PDT 24
Finished Jul 13 07:14:17 PM PDT 24
Peak memory 206872 kb
Host smart-3204edac-3cb9-4375-8bea-af096aa9f30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35550
66461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3555066461
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.764417365
Short name T2698
Test name
Test status
Simulation time 164052968 ps
CPU time 0.82 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:19 PM PDT 24
Peak memory 206864 kb
Host smart-a576324c-9278-4d5d-85d9-f114534a41b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76441
7365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.764417365
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2911705824
Short name T781
Test name
Test status
Simulation time 183092145 ps
CPU time 0.86 seconds
Started Jul 13 07:14:20 PM PDT 24
Finished Jul 13 07:14:21 PM PDT 24
Peak memory 206812 kb
Host smart-728b8106-6496-4dd3-bdba-7baa1b8608f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29117
05824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2911705824
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3602732253
Short name T1563
Test name
Test status
Simulation time 4633461636 ps
CPU time 126.72 seconds
Started Jul 13 07:14:16 PM PDT 24
Finished Jul 13 07:16:24 PM PDT 24
Peak memory 207048 kb
Host smart-9d3f9666-eab3-4369-8f0d-6e0435fe1cc5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3602732253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3602732253
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3443730856
Short name T2563
Test name
Test status
Simulation time 194243489 ps
CPU time 0.88 seconds
Started Jul 13 07:14:21 PM PDT 24
Finished Jul 13 07:14:22 PM PDT 24
Peak memory 206860 kb
Host smart-ffcf8260-7926-45c2-81a7-6fff70b5e815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34437
30856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3443730856
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.229973008
Short name T488
Test name
Test status
Simulation time 164929961 ps
CPU time 0.82 seconds
Started Jul 13 07:14:16 PM PDT 24
Finished Jul 13 07:14:18 PM PDT 24
Peak memory 206844 kb
Host smart-361c3d0f-9014-44d9-9794-cb7e8f54e97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22997
3008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.229973008
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.3323466603
Short name T1225
Test name
Test status
Simulation time 869387644 ps
CPU time 2.23 seconds
Started Jul 13 07:14:15 PM PDT 24
Finished Jul 13 07:14:19 PM PDT 24
Peak memory 207048 kb
Host smart-f8299ecb-7d57-4afd-b2b3-c9f29d549007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234
66603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.3323466603
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3853178920
Short name T1682
Test name
Test status
Simulation time 4973190681 ps
CPU time 36.5 seconds
Started Jul 13 07:14:16 PM PDT 24
Finished Jul 13 07:14:54 PM PDT 24
Peak memory 207124 kb
Host smart-4f3f71ba-c2ee-4b45-ba35-8f8039bcf5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38531
78920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3853178920
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3200544609
Short name T2499
Test name
Test status
Simulation time 86415130 ps
CPU time 0.75 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206908 kb
Host smart-f0374d8a-71d2-4e30-970f-c6a533ac6046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3200544609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3200544609
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.4220958396
Short name T2245
Test name
Test status
Simulation time 3674522362 ps
CPU time 4.45 seconds
Started Jul 13 07:14:21 PM PDT 24
Finished Jul 13 07:14:27 PM PDT 24
Peak memory 207144 kb
Host smart-f9b7271f-d5f7-4814-a8a2-cbed499e6997
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4220958396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.4220958396
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2151507168
Short name T1285
Test name
Test status
Simulation time 13321200873 ps
CPU time 12.55 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:31 PM PDT 24
Peak memory 206936 kb
Host smart-4aba012c-9a78-442a-aa40-c14e1270261b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2151507168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2151507168
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2188629299
Short name T1739
Test name
Test status
Simulation time 23339698959 ps
CPU time 24.98 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 207016 kb
Host smart-c0243a59-9781-4f60-93ee-3b139d0af64e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2188629299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2188629299
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3081936431
Short name T2601
Test name
Test status
Simulation time 177392843 ps
CPU time 0.82 seconds
Started Jul 13 07:14:20 PM PDT 24
Finished Jul 13 07:14:21 PM PDT 24
Peak memory 206816 kb
Host smart-b3d94aba-0312-49f2-a1e2-a1c6c2506299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30819
36431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3081936431
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3739581972
Short name T1776
Test name
Test status
Simulation time 153698288 ps
CPU time 0.76 seconds
Started Jul 13 07:14:15 PM PDT 24
Finished Jul 13 07:14:16 PM PDT 24
Peak memory 206860 kb
Host smart-8f5a148d-d23d-4c39-bd45-4144977775f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37395
81972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3739581972
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.4085081633
Short name T1637
Test name
Test status
Simulation time 459143154 ps
CPU time 1.45 seconds
Started Jul 13 07:14:27 PM PDT 24
Finished Jul 13 07:14:32 PM PDT 24
Peak memory 206876 kb
Host smart-1c8c59b7-94f5-4d0b-976f-1f284aab4c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850
81633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.4085081633
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.915932948
Short name T683
Test name
Test status
Simulation time 807689052 ps
CPU time 1.77 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:20 PM PDT 24
Peak memory 207068 kb
Host smart-8885e90d-47b6-46dd-a788-600b4a2f086a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91593
2948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.915932948
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3506027966
Short name T2528
Test name
Test status
Simulation time 20771361601 ps
CPU time 36.71 seconds
Started Jul 13 07:14:18 PM PDT 24
Finished Jul 13 07:14:56 PM PDT 24
Peak memory 207144 kb
Host smart-cc2ad065-b549-41ba-b67b-177f141b1783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35060
27966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3506027966
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.2007429962
Short name T451
Test name
Test status
Simulation time 420018444 ps
CPU time 1.29 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:20 PM PDT 24
Peak memory 206804 kb
Host smart-ae4d0b66-20be-445a-87e2-f757bb1d5443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20074
29962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.2007429962
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3072680840
Short name T845
Test name
Test status
Simulation time 140754429 ps
CPU time 0.76 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:20 PM PDT 24
Peak memory 206852 kb
Host smart-6bfc13e0-df93-4652-a5a3-e3cd892c6471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30726
80840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3072680840
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3717839043
Short name T1419
Test name
Test status
Simulation time 38203582 ps
CPU time 0.64 seconds
Started Jul 13 07:14:26 PM PDT 24
Finished Jul 13 07:14:30 PM PDT 24
Peak memory 206392 kb
Host smart-0a27d39d-2ac6-4780-94f4-22d5469cedba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37178
39043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3717839043
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.559806512
Short name T900
Test name
Test status
Simulation time 793726945 ps
CPU time 2.06 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:14:32 PM PDT 24
Peak memory 207068 kb
Host smart-1b11bb0f-cd6f-4d6d-b9d0-884db8a4d321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55980
6512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.559806512
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1363915826
Short name T1150
Test name
Test status
Simulation time 208275562 ps
CPU time 1.97 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:30 PM PDT 24
Peak memory 207000 kb
Host smart-27abf9c7-9fa0-4ab9-8838-434d7ac5f19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13639
15826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1363915826
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1777771848
Short name T1165
Test name
Test status
Simulation time 188634096 ps
CPU time 0.83 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:14:32 PM PDT 24
Peak memory 206876 kb
Host smart-2c57801a-db26-4b16-8c1c-4545abdfeaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17777
71848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1777771848
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2732437538
Short name T705
Test name
Test status
Simulation time 149739217 ps
CPU time 0.77 seconds
Started Jul 13 07:14:22 PM PDT 24
Finished Jul 13 07:14:23 PM PDT 24
Peak memory 206872 kb
Host smart-8962a004-8dad-47a4-8669-96a68437f9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27324
37538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2732437538
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1966784680
Short name T1378
Test name
Test status
Simulation time 167413070 ps
CPU time 0.84 seconds
Started Jul 13 07:14:19 PM PDT 24
Finished Jul 13 07:14:21 PM PDT 24
Peak memory 206832 kb
Host smart-40a96f24-0b96-4264-9186-067890d6ce24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19667
84680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1966784680
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.367279308
Short name T1039
Test name
Test status
Simulation time 6686586639 ps
CPU time 184.75 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:17:33 PM PDT 24
Peak memory 207056 kb
Host smart-d7ed398a-7243-4476-93c9-d6ccd0cd3d31
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=367279308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.367279308
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.4214635091
Short name T306
Test name
Test status
Simulation time 8387634964 ps
CPU time 69.56 seconds
Started Jul 13 07:14:26 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206964 kb
Host smart-4fab3471-7752-48b4-954c-380040d2eebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146
35091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.4214635091
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1265229127
Short name T2730
Test name
Test status
Simulation time 172462039 ps
CPU time 0.83 seconds
Started Jul 13 07:14:22 PM PDT 24
Finished Jul 13 07:14:24 PM PDT 24
Peak memory 206876 kb
Host smart-17a195f2-b504-4e1d-9a6b-d2d577833be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12652
29127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1265229127
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1927704693
Short name T692
Test name
Test status
Simulation time 23336300716 ps
CPU time 29.69 seconds
Started Jul 13 07:14:18 PM PDT 24
Finished Jul 13 07:14:49 PM PDT 24
Peak memory 206908 kb
Host smart-8a45c4ed-b971-4536-9976-0e8ea5b47aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19277
04693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1927704693
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1603182261
Short name T720
Test name
Test status
Simulation time 3312720375 ps
CPU time 3.68 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:14:22 PM PDT 24
Peak memory 206932 kb
Host smart-eff2091f-3c38-4a0b-a467-4bf9f76a9529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
82261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1603182261
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1086401309
Short name T1557
Test name
Test status
Simulation time 8998758134 ps
CPU time 254.56 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:18:33 PM PDT 24
Peak memory 207136 kb
Host smart-1a402ee3-c205-4100-8603-54079c65614c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10864
01309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1086401309
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3728201370
Short name T1954
Test name
Test status
Simulation time 5608768011 ps
CPU time 52.88 seconds
Started Jul 13 07:14:17 PM PDT 24
Finished Jul 13 07:15:11 PM PDT 24
Peak memory 207132 kb
Host smart-01cf67cd-bd9d-4b2a-b2a8-3dc4af99fbe8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3728201370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3728201370
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.2397195028
Short name T688
Test name
Test status
Simulation time 301096677 ps
CPU time 1.03 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206864 kb
Host smart-5fe433ca-b298-4253-be69-ed3f55613cac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2397195028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2397195028
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1413703233
Short name T2530
Test name
Test status
Simulation time 191870905 ps
CPU time 0.78 seconds
Started Jul 13 07:14:15 PM PDT 24
Finished Jul 13 07:14:17 PM PDT 24
Peak memory 206648 kb
Host smart-6dfde852-1382-4802-98ea-0ed263b5c978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14137
03233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1413703233
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.1174088417
Short name T1391
Test name
Test status
Simulation time 6804085768 ps
CPU time 196.44 seconds
Started Jul 13 07:14:22 PM PDT 24
Finished Jul 13 07:17:40 PM PDT 24
Peak memory 207072 kb
Host smart-5d3a88d3-ef00-46e3-be47-8b4673123a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11740
88417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.1174088417
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2961951226
Short name T414
Test name
Test status
Simulation time 7329257608 ps
CPU time 68.48 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 207116 kb
Host smart-207799c5-cbd2-4a16-9ca2-ad99064c4056
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2961951226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2961951226
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2430502970
Short name T1481
Test name
Test status
Simulation time 155933607 ps
CPU time 0.81 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:14:27 PM PDT 24
Peak memory 206868 kb
Host smart-499d61bc-f5a6-4319-aa0e-05ffcaa9ef84
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2430502970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2430502970
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3158337166
Short name T2427
Test name
Test status
Simulation time 155806919 ps
CPU time 0.77 seconds
Started Jul 13 07:14:22 PM PDT 24
Finished Jul 13 07:14:24 PM PDT 24
Peak memory 206880 kb
Host smart-eb46c56c-7168-4fa7-bdc3-d593a3f470ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31583
37166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3158337166
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.151026780
Short name T2196
Test name
Test status
Simulation time 240625312 ps
CPU time 0.98 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:30 PM PDT 24
Peak memory 206856 kb
Host smart-2efe31a9-b1a3-4708-b7c9-e14d9f034edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15102
6780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.151026780
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1379359819
Short name T1477
Test name
Test status
Simulation time 174454343 ps
CPU time 0.88 seconds
Started Jul 13 07:14:22 PM PDT 24
Finished Jul 13 07:14:24 PM PDT 24
Peak memory 206832 kb
Host smart-a3d90301-0a09-47fd-83fe-32b5a0ea8a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13793
59819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1379359819
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1707517572
Short name T1763
Test name
Test status
Simulation time 191332894 ps
CPU time 0.94 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:28 PM PDT 24
Peak memory 206860 kb
Host smart-5e720f8f-6914-4a1e-9f50-f8cbdb7defdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
17572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1707517572
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1843591485
Short name T2136
Test name
Test status
Simulation time 198507599 ps
CPU time 0.8 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:28 PM PDT 24
Peak memory 206880 kb
Host smart-7a02f56c-d78d-47c5-adfc-e71600ef5a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18435
91485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1843591485
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1669786975
Short name T1725
Test name
Test status
Simulation time 149092931 ps
CPU time 0.8 seconds
Started Jul 13 07:14:30 PM PDT 24
Finished Jul 13 07:14:33 PM PDT 24
Peak memory 206892 kb
Host smart-5a247cde-dbd6-449e-ae96-2b053c97721e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16697
86975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1669786975
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1755783602
Short name T2230
Test name
Test status
Simulation time 214077944 ps
CPU time 0.97 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:14:27 PM PDT 24
Peak memory 206892 kb
Host smart-5bf984ed-777a-4286-bed1-8ab6fbc13521
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1755783602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1755783602
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2222145378
Short name T1421
Test name
Test status
Simulation time 165514761 ps
CPU time 0.8 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206856 kb
Host smart-fd4c2c70-4d76-4801-9365-c069fae9aeed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
45378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2222145378
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1804229995
Short name T2397
Test name
Test status
Simulation time 41611807 ps
CPU time 0.69 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:27 PM PDT 24
Peak memory 206812 kb
Host smart-7e728863-a64b-4f6b-b3bd-a951dab7daee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18042
29995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1804229995
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1938721895
Short name T841
Test name
Test status
Simulation time 14946131369 ps
CPU time 32.19 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:15:00 PM PDT 24
Peak memory 207164 kb
Host smart-ac48ca42-e5a6-4de5-bed1-5766f173cc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19387
21895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1938721895
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1830340762
Short name T1533
Test name
Test status
Simulation time 234659175 ps
CPU time 0.9 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206848 kb
Host smart-4e4afd63-363c-493b-bbab-ab51f2a3e606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18303
40762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1830340762
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.430162360
Short name T2053
Test name
Test status
Simulation time 158241232 ps
CPU time 0.78 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:14:32 PM PDT 24
Peak memory 206884 kb
Host smart-7bd7fef6-7080-4815-b4ec-eb2b6bc2ff92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43016
2360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.430162360
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.2989193189
Short name T385
Test name
Test status
Simulation time 240584965 ps
CPU time 0.85 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:14:32 PM PDT 24
Peak memory 206892 kb
Host smart-4536e362-f566-4193-bc9c-903d723ce4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29891
93189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.2989193189
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3985161271
Short name T583
Test name
Test status
Simulation time 145541922 ps
CPU time 0.8 seconds
Started Jul 13 07:14:26 PM PDT 24
Finished Jul 13 07:14:30 PM PDT 24
Peak memory 207100 kb
Host smart-738604ba-e816-4a1c-aaee-627e5bbc5e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39851
61271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3985161271
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.4199203695
Short name T2020
Test name
Test status
Simulation time 156800936 ps
CPU time 0.82 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:28 PM PDT 24
Peak memory 206860 kb
Host smart-7f9d927c-50be-4570-9983-25750a4d31ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41992
03695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.4199203695
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2359753282
Short name T1333
Test name
Test status
Simulation time 149705573 ps
CPU time 0.82 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:27 PM PDT 24
Peak memory 206844 kb
Host smart-bebbee00-e74d-427a-ade6-a40b05e344ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23597
53282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2359753282
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2115566425
Short name T1807
Test name
Test status
Simulation time 249208493 ps
CPU time 1.05 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:14:27 PM PDT 24
Peak memory 206844 kb
Host smart-de5cffab-8060-4b6e-be9e-b52981c6051e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21155
66425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2115566425
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.634323291
Short name T1005
Test name
Test status
Simulation time 4868580508 ps
CPU time 133.05 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 207072 kb
Host smart-e5758517-db33-435f-b68f-032da7b6e97b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=634323291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.634323291
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2087750283
Short name T1105
Test name
Test status
Simulation time 203417420 ps
CPU time 0.83 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206860 kb
Host smart-e4ddc57b-f0b7-41e0-85c7-f92207c2fa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877
50283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2087750283
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.82878387
Short name T1703
Test name
Test status
Simulation time 159901307 ps
CPU time 0.8 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:14:27 PM PDT 24
Peak memory 206872 kb
Host smart-d7d7a199-6733-4f7b-b961-21b69c85e1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82878
387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.82878387
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2199927850
Short name T2596
Test name
Test status
Simulation time 900817196 ps
CPU time 1.95 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:28 PM PDT 24
Peak memory 207036 kb
Host smart-002e8a1a-8832-4104-b29e-8605cf458abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21999
27850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2199927850
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1448631351
Short name T2199
Test name
Test status
Simulation time 5662999859 ps
CPU time 149.75 seconds
Started Jul 13 07:14:26 PM PDT 24
Finished Jul 13 07:16:59 PM PDT 24
Peak memory 207312 kb
Host smart-20546bb5-2f8f-4fdc-af17-7179d5062276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14486
31351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1448631351
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3618484995
Short name T481
Test name
Test status
Simulation time 36922496 ps
CPU time 0.68 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:06 PM PDT 24
Peak memory 206940 kb
Host smart-2077c310-2c47-4552-9e8d-86e57b7c43c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3618484995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3618484995
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.673364706
Short name T904
Test name
Test status
Simulation time 4303431300 ps
CPU time 4.71 seconds
Started Jul 13 07:08:38 PM PDT 24
Finished Jul 13 07:08:45 PM PDT 24
Peak memory 206940 kb
Host smart-a2826033-6481-479a-be42-170e3821478c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=673364706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.673364706
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3982461280
Short name T15
Test name
Test status
Simulation time 13419780514 ps
CPU time 12.58 seconds
Started Jul 13 07:08:37 PM PDT 24
Finished Jul 13 07:08:51 PM PDT 24
Peak memory 207120 kb
Host smart-527b9b30-7653-4a8a-a36b-58d028c993d0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3982461280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3982461280
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1362078809
Short name T1237
Test name
Test status
Simulation time 23332245491 ps
CPU time 27.76 seconds
Started Jul 13 07:08:37 PM PDT 24
Finished Jul 13 07:09:06 PM PDT 24
Peak memory 207076 kb
Host smart-a3048ee0-0495-4327-9d0a-c5b7b3c6bc2c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1362078809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.1362078809
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.829536514
Short name T328
Test name
Test status
Simulation time 142757272 ps
CPU time 0.77 seconds
Started Jul 13 07:08:40 PM PDT 24
Finished Jul 13 07:08:42 PM PDT 24
Peak memory 206880 kb
Host smart-de595019-b69c-4814-ae49-1d4a8734745a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82953
6514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.829536514
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.4208506255
Short name T49
Test name
Test status
Simulation time 198528943 ps
CPU time 0.87 seconds
Started Jul 13 07:08:37 PM PDT 24
Finished Jul 13 07:08:39 PM PDT 24
Peak memory 206864 kb
Host smart-f2451f19-4a3e-4dbb-865d-88c4927cc2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42085
06255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.4208506255
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.414536320
Short name T64
Test name
Test status
Simulation time 148416353 ps
CPU time 0.77 seconds
Started Jul 13 07:08:36 PM PDT 24
Finished Jul 13 07:08:37 PM PDT 24
Peak memory 206876 kb
Host smart-f57dfd06-0401-495f-9e3b-4f4fb3196217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41453
6320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.414536320
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3893722238
Short name T1134
Test name
Test status
Simulation time 160349807 ps
CPU time 0.92 seconds
Started Jul 13 07:08:39 PM PDT 24
Finished Jul 13 07:08:42 PM PDT 24
Peak memory 206848 kb
Host smart-635db9f3-dda9-4414-b2c1-bfb46907d639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38937
22238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3893722238
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1708916013
Short name T1531
Test name
Test status
Simulation time 368629805 ps
CPU time 1.2 seconds
Started Jul 13 07:08:39 PM PDT 24
Finished Jul 13 07:08:42 PM PDT 24
Peak memory 206876 kb
Host smart-9e2271d8-9e7c-43dd-bc31-e902ba667c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17089
16013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1708916013
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.118217545
Short name T1488
Test name
Test status
Simulation time 476308731 ps
CPU time 1.23 seconds
Started Jul 13 07:08:37 PM PDT 24
Finished Jul 13 07:08:40 PM PDT 24
Peak memory 206856 kb
Host smart-9836a00b-5880-4db1-b94c-ea53303452fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11821
7545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.118217545
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3721285224
Short name T2591
Test name
Test status
Simulation time 14456552061 ps
CPU time 25.76 seconds
Started Jul 13 07:08:38 PM PDT 24
Finished Jul 13 07:09:06 PM PDT 24
Peak memory 207140 kb
Host smart-a2d45fec-a770-40b8-ae48-5e47abd8ce3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37212
85224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3721285224
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2451676791
Short name T648
Test name
Test status
Simulation time 341398294 ps
CPU time 1.19 seconds
Started Jul 13 07:08:39 PM PDT 24
Finished Jul 13 07:08:42 PM PDT 24
Peak memory 206868 kb
Host smart-f49eb38b-a223-4e59-90d1-d2a8c5786560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24516
76791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2451676791
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.729105546
Short name T1416
Test name
Test status
Simulation time 139771012 ps
CPU time 0.75 seconds
Started Jul 13 07:08:37 PM PDT 24
Finished Jul 13 07:08:39 PM PDT 24
Peak memory 206864 kb
Host smart-ae543b87-7fcd-477c-94ea-e8ee6ae50945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72910
5546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.729105546
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1517650622
Short name T1404
Test name
Test status
Simulation time 42091602 ps
CPU time 0.69 seconds
Started Jul 13 07:08:49 PM PDT 24
Finished Jul 13 07:08:50 PM PDT 24
Peak memory 206872 kb
Host smart-b95c6c17-eeb1-4b0c-9b0f-264fbd61a1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15176
50622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1517650622
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1381782061
Short name T84
Test name
Test status
Simulation time 858426298 ps
CPU time 1.97 seconds
Started Jul 13 07:08:48 PM PDT 24
Finished Jul 13 07:08:51 PM PDT 24
Peak memory 207012 kb
Host smart-f4866670-1ae2-4906-bd6b-73d466b42bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13817
82061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1381782061
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1360294416
Short name T2112
Test name
Test status
Simulation time 189317963 ps
CPU time 2.26 seconds
Started Jul 13 07:08:47 PM PDT 24
Finished Jul 13 07:08:49 PM PDT 24
Peak memory 207088 kb
Host smart-8a6733e8-3bd4-4b8e-af06-b06257d717d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13602
94416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1360294416
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3035401403
Short name T1735
Test name
Test status
Simulation time 104186105736 ps
CPU time 153.52 seconds
Started Jul 13 07:08:47 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 207052 kb
Host smart-ab7038d2-b9bb-46f2-8ce2-742f846df1d7
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3035401403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3035401403
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.844850261
Short name T2572
Test name
Test status
Simulation time 110146046616 ps
CPU time 152.39 seconds
Started Jul 13 07:08:48 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 207076 kb
Host smart-aeb76dd5-e482-48df-8496-f89bd934c86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844850261 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.844850261
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.3997853593
Short name T1692
Test name
Test status
Simulation time 112095676891 ps
CPU time 152.15 seconds
Started Jul 13 07:08:50 PM PDT 24
Finished Jul 13 07:11:22 PM PDT 24
Peak memory 207092 kb
Host smart-2942aed4-00e7-4aad-bf76-5e21845bcb4c
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3997853593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3997853593
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1273315876
Short name T1530
Test name
Test status
Simulation time 120045206589 ps
CPU time 160.01 seconds
Started Jul 13 07:08:49 PM PDT 24
Finished Jul 13 07:11:29 PM PDT 24
Peak memory 207072 kb
Host smart-b6146700-1fbf-4d7b-9069-9edbe03af102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273315876 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1273315876
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.3775543563
Short name T2197
Test name
Test status
Simulation time 85151835376 ps
CPU time 105.28 seconds
Started Jul 13 07:08:49 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 207116 kb
Host smart-c63e7073-4abf-4208-b41f-fb8ccc051c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37755
43563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.3775543563
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1020902920
Short name T1695
Test name
Test status
Simulation time 172231741 ps
CPU time 0.8 seconds
Started Jul 13 07:08:49 PM PDT 24
Finished Jul 13 07:08:50 PM PDT 24
Peak memory 206876 kb
Host smart-ddb0b40c-ca0a-4bf4-8935-8d8da7d5c49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10209
02920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1020902920
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.123172930
Short name T107
Test name
Test status
Simulation time 131273485 ps
CPU time 0.77 seconds
Started Jul 13 07:08:47 PM PDT 24
Finished Jul 13 07:08:48 PM PDT 24
Peak memory 206852 kb
Host smart-6bd8acdb-f8f2-45e1-9441-bea2dea336b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12317
2930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.123172930
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2080090180
Short name T1536
Test name
Test status
Simulation time 243006905 ps
CPU time 1.05 seconds
Started Jul 13 07:08:47 PM PDT 24
Finished Jul 13 07:08:49 PM PDT 24
Peak memory 206832 kb
Host smart-88866aba-698b-4cde-982a-2489f675c5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
90180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2080090180
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.465680854
Short name T2690
Test name
Test status
Simulation time 8521924750 ps
CPU time 79.79 seconds
Started Jul 13 07:08:47 PM PDT 24
Finished Jul 13 07:10:07 PM PDT 24
Peak memory 207136 kb
Host smart-efbe54db-fedd-47c7-9f08-0d20d8fbb238
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=465680854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.465680854
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2788101224
Short name T1064
Test name
Test status
Simulation time 10329263635 ps
CPU time 90.65 seconds
Started Jul 13 07:08:48 PM PDT 24
Finished Jul 13 07:10:20 PM PDT 24
Peak memory 207088 kb
Host smart-d3bd806b-eeac-47db-8ae8-3ca850c42d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
01224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2788101224
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1452153819
Short name T643
Test name
Test status
Simulation time 172631778 ps
CPU time 0.81 seconds
Started Jul 13 07:08:48 PM PDT 24
Finished Jul 13 07:08:49 PM PDT 24
Peak memory 206876 kb
Host smart-7996ee86-93de-4e84-9362-da4dd5501183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14521
53819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1452153819
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.676362249
Short name T2407
Test name
Test status
Simulation time 23365908250 ps
CPU time 22.13 seconds
Started Jul 13 07:08:51 PM PDT 24
Finished Jul 13 07:09:13 PM PDT 24
Peak memory 206920 kb
Host smart-7c52c800-a43a-44ee-be15-9f81830f5549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67636
2249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.676362249
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2567469803
Short name T798
Test name
Test status
Simulation time 3305270778 ps
CPU time 4.83 seconds
Started Jul 13 07:08:47 PM PDT 24
Finished Jul 13 07:08:52 PM PDT 24
Peak memory 206920 kb
Host smart-27f5be2e-8b69-4a41-9fdb-c07885bbb9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25674
69803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2567469803
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.921303138
Short name T2077
Test name
Test status
Simulation time 12349988325 ps
CPU time 92.96 seconds
Started Jul 13 07:08:48 PM PDT 24
Finished Jul 13 07:10:22 PM PDT 24
Peak memory 207124 kb
Host smart-7f71c78c-ff20-4787-a6ef-176a07220fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92130
3138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.921303138
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2083265950
Short name T603
Test name
Test status
Simulation time 7653913205 ps
CPU time 54.75 seconds
Started Jul 13 07:08:50 PM PDT 24
Finished Jul 13 07:09:46 PM PDT 24
Peak memory 207128 kb
Host smart-b27bf26c-3442-4c0b-8fc9-4f0d873822ed
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2083265950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2083265950
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2633874906
Short name T635
Test name
Test status
Simulation time 262108426 ps
CPU time 0.91 seconds
Started Jul 13 07:08:47 PM PDT 24
Finished Jul 13 07:08:49 PM PDT 24
Peak memory 206868 kb
Host smart-59747cf9-cce8-4b6b-a495-e077c8b961aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2633874906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2633874906
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2832908758
Short name T941
Test name
Test status
Simulation time 192491623 ps
CPU time 0.83 seconds
Started Jul 13 07:08:48 PM PDT 24
Finished Jul 13 07:08:49 PM PDT 24
Peak memory 206872 kb
Host smart-d177f354-da5c-424a-96dd-65f84949d2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28329
08758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2832908758
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1749056532
Short name T2732
Test name
Test status
Simulation time 3321440710 ps
CPU time 92.61 seconds
Started Jul 13 07:08:48 PM PDT 24
Finished Jul 13 07:10:21 PM PDT 24
Peak memory 207084 kb
Host smart-e3da9e91-6e8b-46bc-b0a3-c93ee12325bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17490
56532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1749056532
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.957203027
Short name T1963
Test name
Test status
Simulation time 6309124700 ps
CPU time 48.39 seconds
Started Jul 13 07:08:49 PM PDT 24
Finished Jul 13 07:09:38 PM PDT 24
Peak memory 207136 kb
Host smart-914581b5-71af-49b7-97ad-cc6c9ffa7f5b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=957203027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.957203027
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.124692035
Short name T548
Test name
Test status
Simulation time 150231218 ps
CPU time 0.72 seconds
Started Jul 13 07:08:47 PM PDT 24
Finished Jul 13 07:08:49 PM PDT 24
Peak memory 206844 kb
Host smart-2757ba24-ddb4-4ea3-b503-f63d3ac4855c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=124692035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.124692035
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1469228953
Short name T280
Test name
Test status
Simulation time 161515520 ps
CPU time 0.75 seconds
Started Jul 13 07:08:49 PM PDT 24
Finished Jul 13 07:08:51 PM PDT 24
Peak memory 206876 kb
Host smart-87542db4-929d-4071-98d3-f4c70ba7f4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14692
28953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1469228953
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.528274627
Short name T118
Test name
Test status
Simulation time 210893511 ps
CPU time 0.91 seconds
Started Jul 13 07:08:48 PM PDT 24
Finished Jul 13 07:08:50 PM PDT 24
Peak memory 206868 kb
Host smart-7b13159f-c305-4197-ac52-171f43764bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52827
4627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.528274627
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2075329652
Short name T1227
Test name
Test status
Simulation time 166196492 ps
CPU time 0.84 seconds
Started Jul 13 07:08:51 PM PDT 24
Finished Jul 13 07:08:52 PM PDT 24
Peak memory 206856 kb
Host smart-0be0ed24-bb33-424f-abd2-114b256de335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20753
29652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2075329652
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.473231233
Short name T1642
Test name
Test status
Simulation time 219648417 ps
CPU time 0.9 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:07 PM PDT 24
Peak memory 206864 kb
Host smart-e4804e05-00d0-4a6a-8e7b-5e481f66344c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47323
1233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.473231233
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3561586340
Short name T2179
Test name
Test status
Simulation time 166140058 ps
CPU time 0.79 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:05 PM PDT 24
Peak memory 206864 kb
Host smart-04229ce2-4827-4ae0-a86c-ced3f8b376ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35615
86340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3561586340
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.831130439
Short name T562
Test name
Test status
Simulation time 154615789 ps
CPU time 0.83 seconds
Started Jul 13 07:09:07 PM PDT 24
Finished Jul 13 07:09:09 PM PDT 24
Peak memory 206808 kb
Host smart-f01ed926-fd55-40f8-a469-971cd36bc39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83113
0439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.831130439
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2651522432
Short name T1826
Test name
Test status
Simulation time 226323808 ps
CPU time 0.96 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:04 PM PDT 24
Peak memory 206884 kb
Host smart-e5022a4f-8bec-4fec-87c6-094a81a09703
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2651522432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2651522432
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3214385962
Short name T180
Test name
Test status
Simulation time 254854911 ps
CPU time 0.97 seconds
Started Jul 13 07:09:08 PM PDT 24
Finished Jul 13 07:09:10 PM PDT 24
Peak memory 206872 kb
Host smart-cab50a94-71c1-4ea1-8bdf-58b2584abaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
85962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3214385962
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.718283178
Short name T1406
Test name
Test status
Simulation time 148187705 ps
CPU time 0.79 seconds
Started Jul 13 07:09:08 PM PDT 24
Finished Jul 13 07:09:09 PM PDT 24
Peak memory 206852 kb
Host smart-1143b12f-919a-4c3d-8803-3e0429ad30ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71828
3178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.718283178
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1973132086
Short name T26
Test name
Test status
Simulation time 126176151 ps
CPU time 0.74 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:05 PM PDT 24
Peak memory 206868 kb
Host smart-55164986-8420-4c7b-b6ed-0aa537a0fb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19731
32086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1973132086
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2988633582
Short name T1185
Test name
Test status
Simulation time 9469672546 ps
CPU time 19.95 seconds
Started Jul 13 07:09:02 PM PDT 24
Finished Jul 13 07:09:22 PM PDT 24
Peak memory 207108 kb
Host smart-c92e2288-67ac-4f6b-b27b-271aa0e0b873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29886
33582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2988633582
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1490314363
Short name T870
Test name
Test status
Simulation time 144781047 ps
CPU time 0.78 seconds
Started Jul 13 07:09:05 PM PDT 24
Finished Jul 13 07:09:07 PM PDT 24
Peak memory 206852 kb
Host smart-dfbd1b31-fa02-4a3e-a649-4f36aee971ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14903
14363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1490314363
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2809924720
Short name T1518
Test name
Test status
Simulation time 195368354 ps
CPU time 0.84 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:06 PM PDT 24
Peak memory 206860 kb
Host smart-53de4ae4-f334-4e97-94a8-b2396d533c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28099
24720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2809924720
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1383168378
Short name T2107
Test name
Test status
Simulation time 8450027888 ps
CPU time 35.96 seconds
Started Jul 13 07:09:05 PM PDT 24
Finished Jul 13 07:09:42 PM PDT 24
Peak memory 207168 kb
Host smart-5a93e1b8-d62d-40b7-9c74-9e1a5df5592b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1383168378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1383168378
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.775043297
Short name T1003
Test name
Test status
Simulation time 13564790686 ps
CPU time 124.27 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:11:10 PM PDT 24
Peak memory 207084 kb
Host smart-ed0b5818-39e5-4638-8069-baaf416bb220
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=775043297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.775043297
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.338947755
Short name T1615
Test name
Test status
Simulation time 11897146705 ps
CPU time 66.74 seconds
Started Jul 13 07:09:02 PM PDT 24
Finished Jul 13 07:10:09 PM PDT 24
Peak memory 207088 kb
Host smart-b0ba7eff-39b5-4c35-98e8-8e2968154a5b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=338947755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.338947755
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2206559402
Short name T564
Test name
Test status
Simulation time 221902397 ps
CPU time 0.85 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:06 PM PDT 24
Peak memory 206872 kb
Host smart-a44abbe4-6f52-4e4d-b990-08027a6c6773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22065
59402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2206559402
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.90046859
Short name T1584
Test name
Test status
Simulation time 218051727 ps
CPU time 0.85 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:05 PM PDT 24
Peak memory 206868 kb
Host smart-548750e5-8c44-4fde-95b6-92b535cf32da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90046
859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.90046859
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.412850008
Short name T2038
Test name
Test status
Simulation time 167239437 ps
CPU time 0.81 seconds
Started Jul 13 07:09:05 PM PDT 24
Finished Jul 13 07:09:07 PM PDT 24
Peak memory 206852 kb
Host smart-32826f10-b4f1-450f-a864-76a8deef78e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
0008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.412850008
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3389419447
Short name T1829
Test name
Test status
Simulation time 243569700 ps
CPU time 0.86 seconds
Started Jul 13 07:09:02 PM PDT 24
Finished Jul 13 07:09:03 PM PDT 24
Peak memory 206808 kb
Host smart-7d1fe63b-3a70-4b50-916c-050a8abf4ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894
19447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3389419447
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.605253800
Short name T174
Test name
Test status
Simulation time 912747377 ps
CPU time 1.76 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:05 PM PDT 24
Peak memory 224568 kb
Host smart-7aab3bcd-33bc-4848-910d-6745d3e4cb4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=605253800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.605253800
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.2499037239
Short name T54
Test name
Test status
Simulation time 317521538 ps
CPU time 1.08 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:07 PM PDT 24
Peak memory 206868 kb
Host smart-228dd73b-8103-4612-b2fa-dd99359d9949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24990
37239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.2499037239
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.845620506
Short name T895
Test name
Test status
Simulation time 235049055 ps
CPU time 0.91 seconds
Started Jul 13 07:09:06 PM PDT 24
Finished Jul 13 07:09:08 PM PDT 24
Peak memory 206860 kb
Host smart-c5724d0c-442b-46fd-98f1-7bb64d4e61f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84562
0506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.845620506
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1244873376
Short name T1527
Test name
Test status
Simulation time 167337292 ps
CPU time 0.82 seconds
Started Jul 13 07:09:08 PM PDT 24
Finished Jul 13 07:09:09 PM PDT 24
Peak memory 206844 kb
Host smart-becaa46c-a65b-47a0-b5cb-047d0896bb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448
73376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1244873376
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3856971176
Short name T363
Test name
Test status
Simulation time 152555385 ps
CPU time 0.78 seconds
Started Jul 13 07:09:01 PM PDT 24
Finished Jul 13 07:09:02 PM PDT 24
Peak memory 206868 kb
Host smart-534a7642-95c2-4082-9be0-87ebb67e479c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38569
71176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3856971176
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2934632279
Short name T761
Test name
Test status
Simulation time 212448662 ps
CPU time 0.88 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:04 PM PDT 24
Peak memory 206872 kb
Host smart-61e0fbab-ff22-4a32-9efd-331c9d822d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29346
32279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2934632279
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2146431201
Short name T746
Test name
Test status
Simulation time 4392459546 ps
CPU time 31.61 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:36 PM PDT 24
Peak memory 207104 kb
Host smart-e52f2be3-b4a4-4137-87bd-c300a2381b04
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2146431201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2146431201
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3596524519
Short name T2557
Test name
Test status
Simulation time 163053499 ps
CPU time 0.81 seconds
Started Jul 13 07:09:02 PM PDT 24
Finished Jul 13 07:09:04 PM PDT 24
Peak memory 206824 kb
Host smart-cac4e4b8-0e22-478f-9e3e-ecb06a476da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
24519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3596524519
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1430440649
Short name T431
Test name
Test status
Simulation time 152032999 ps
CPU time 0.85 seconds
Started Jul 13 07:09:08 PM PDT 24
Finished Jul 13 07:09:10 PM PDT 24
Peak memory 206848 kb
Host smart-91d39de9-d4f5-43b2-9056-4a8a01523066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14304
40649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1430440649
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.439250891
Short name T516
Test name
Test status
Simulation time 953972261 ps
CPU time 2.09 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:08 PM PDT 24
Peak memory 207040 kb
Host smart-dc30d249-b52f-44a2-aa99-84415cbdff98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43925
0891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.439250891
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.720068737
Short name T873
Test name
Test status
Simulation time 3305131334 ps
CPU time 97.06 seconds
Started Jul 13 07:09:08 PM PDT 24
Finished Jul 13 07:10:46 PM PDT 24
Peak memory 207072 kb
Host smart-28abe394-bf5e-4987-aadb-e543c5ce9352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72006
8737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.720068737
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2898418387
Short name T167
Test name
Test status
Simulation time 45789282 ps
CPU time 0.64 seconds
Started Jul 13 07:14:33 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 206944 kb
Host smart-b45f1cec-dc77-44fa-ac69-3374476b169d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2898418387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2898418387
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.596881535
Short name T1932
Test name
Test status
Simulation time 3580689390 ps
CPU time 4.66 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:14:31 PM PDT 24
Peak memory 207144 kb
Host smart-8b518dbe-7b15-49ee-83c5-8c45868fd205
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=596881535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.596881535
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.787485282
Short name T2029
Test name
Test status
Simulation time 13383310060 ps
CPU time 15.93 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:14:42 PM PDT 24
Peak memory 206916 kb
Host smart-dd9b07e9-cd9b-488d-8be3-0c7aa0dfd12b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=787485282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.787485282
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2157908119
Short name T1946
Test name
Test status
Simulation time 23385693094 ps
CPU time 24.09 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:14:50 PM PDT 24
Peak memory 206944 kb
Host smart-9eb08f1b-f9d1-4bb7-8f7b-b570a7978856
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2157908119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.2157908119
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.476198262
Short name T2680
Test name
Test status
Simulation time 175481880 ps
CPU time 0.83 seconds
Started Jul 13 07:14:22 PM PDT 24
Finished Jul 13 07:14:24 PM PDT 24
Peak memory 206860 kb
Host smart-11baab49-77b8-4857-a6d5-b3fcf3975129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47619
8262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.476198262
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.484269557
Short name T355
Test name
Test status
Simulation time 152202194 ps
CPU time 0.78 seconds
Started Jul 13 07:14:27 PM PDT 24
Finished Jul 13 07:14:31 PM PDT 24
Peak memory 206860 kb
Host smart-0c70eede-4579-4b6a-bd8d-c8ebc781fa0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48426
9557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.484269557
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1292518759
Short name T1284
Test name
Test status
Simulation time 364771369 ps
CPU time 1.29 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:14:32 PM PDT 24
Peak memory 206884 kb
Host smart-9ae50bf7-1c7c-4171-93e6-75df826e7174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12925
18759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1292518759
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.4237854602
Short name T1986
Test name
Test status
Simulation time 1573328143 ps
CPU time 3.19 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:30 PM PDT 24
Peak memory 207028 kb
Host smart-157fee99-ac1e-49b3-ad79-e70eca7b7b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378
54602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.4237854602
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3472167848
Short name T1082
Test name
Test status
Simulation time 12820814105 ps
CPU time 24.77 seconds
Started Jul 13 07:14:27 PM PDT 24
Finished Jul 13 07:14:55 PM PDT 24
Peak memory 207140 kb
Host smart-a9610fa6-8b6e-4589-b3b1-db1df0c896c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34721
67848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3472167848
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.4195556560
Short name T1349
Test name
Test status
Simulation time 542305273 ps
CPU time 1.53 seconds
Started Jul 13 07:14:24 PM PDT 24
Finished Jul 13 07:14:28 PM PDT 24
Peak memory 206872 kb
Host smart-6ca02a07-53b1-4512-abc7-73cfca173e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41955
56560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.4195556560
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1178640361
Short name T1733
Test name
Test status
Simulation time 173404009 ps
CPU time 0.82 seconds
Started Jul 13 07:14:25 PM PDT 24
Finished Jul 13 07:14:29 PM PDT 24
Peak memory 206868 kb
Host smart-bbaf692b-c6f0-41ba-badd-b881a56bc91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11786
40361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1178640361
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2773358708
Short name T2147
Test name
Test status
Simulation time 37319039 ps
CPU time 0.65 seconds
Started Jul 13 07:14:23 PM PDT 24
Finished Jul 13 07:14:26 PM PDT 24
Peak memory 206860 kb
Host smart-e68ead21-f293-4c11-904a-01bfd5f5b43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27733
58708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2773358708
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3498077755
Short name T2300
Test name
Test status
Simulation time 848400954 ps
CPU time 2.27 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:37 PM PDT 24
Peak memory 207040 kb
Host smart-9e06928f-fb04-42e7-9d7e-08c21bcd5a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980
77755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3498077755
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3363345629
Short name T1707
Test name
Test status
Simulation time 161155153 ps
CPU time 1.69 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 207060 kb
Host smart-321e89c2-8c35-4ab6-a51c-d599e92e9c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
45629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3363345629
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.642983244
Short name T409
Test name
Test status
Simulation time 272694547 ps
CPU time 0.98 seconds
Started Jul 13 07:14:32 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 206804 kb
Host smart-3c317730-34ac-4e12-82db-60b8fd97768a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64298
3244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.642983244
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2544703936
Short name T1650
Test name
Test status
Simulation time 173602725 ps
CPU time 0.82 seconds
Started Jul 13 07:14:30 PM PDT 24
Finished Jul 13 07:14:34 PM PDT 24
Peak memory 206864 kb
Host smart-0c22531c-aa8e-4cc0-a3a0-d67fc2553a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25447
03936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2544703936
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.885831099
Short name T1689
Test name
Test status
Simulation time 259899743 ps
CPU time 1 seconds
Started Jul 13 07:14:34 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 206872 kb
Host smart-319fd0a0-e760-4f8d-a260-137ae31be55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88583
1099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.885831099
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.3757064710
Short name T2033
Test name
Test status
Simulation time 4461692011 ps
CPU time 35.62 seconds
Started Jul 13 07:14:29 PM PDT 24
Finished Jul 13 07:15:07 PM PDT 24
Peak memory 207132 kb
Host smart-dec2f538-0430-4e45-9ac9-2669dbd48813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37570
64710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.3757064710
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3580299243
Short name T99
Test name
Test status
Simulation time 164841959 ps
CPU time 0.83 seconds
Started Jul 13 07:14:32 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206880 kb
Host smart-187a7b66-68fa-4e58-8cc5-db2038e5009f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35802
99243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3580299243
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1723717178
Short name T2286
Test name
Test status
Simulation time 23328844524 ps
CPU time 22.45 seconds
Started Jul 13 07:14:30 PM PDT 24
Finished Jul 13 07:14:56 PM PDT 24
Peak memory 206928 kb
Host smart-1b66d847-7c7f-4884-a792-9ad200b8df6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
17178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1723717178
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3987870440
Short name T1972
Test name
Test status
Simulation time 3265603981 ps
CPU time 3.87 seconds
Started Jul 13 07:14:32 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 206932 kb
Host smart-0faaebdd-44eb-4e22-8420-0ca55808e6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39878
70440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3987870440
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.101343921
Short name T1478
Test name
Test status
Simulation time 5225926532 ps
CPU time 48.49 seconds
Started Jul 13 07:14:34 PM PDT 24
Finished Jul 13 07:15:25 PM PDT 24
Peak memory 207416 kb
Host smart-5bceee13-29f0-4d12-877c-3afef2d0ed1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10134
3921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.101343921
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.2378241159
Short name T1454
Test name
Test status
Simulation time 5361666240 ps
CPU time 50.93 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:15:25 PM PDT 24
Peak memory 207092 kb
Host smart-0523e336-4ffb-499a-87e0-79964ada2473
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2378241159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.2378241159
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.4084116990
Short name T1483
Test name
Test status
Simulation time 246857321 ps
CPU time 1.03 seconds
Started Jul 13 07:14:32 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 206864 kb
Host smart-cef1a2fb-efc7-4ddf-be67-137272bfccfb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4084116990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.4084116990
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3364378012
Short name T28
Test name
Test status
Simulation time 196350550 ps
CPU time 0.87 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206860 kb
Host smart-7347eb50-2682-4e44-a6ef-aa303d90850f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33643
78012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3364378012
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3323837882
Short name T2511
Test name
Test status
Simulation time 5799498277 ps
CPU time 166.23 seconds
Started Jul 13 07:14:34 PM PDT 24
Finished Jul 13 07:17:23 PM PDT 24
Peak memory 207108 kb
Host smart-ee8edaad-5c89-4a9b-a6ef-fbf078e0325c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33238
37882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3323837882
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.831950211
Short name T139
Test name
Test status
Simulation time 3662559973 ps
CPU time 34.58 seconds
Started Jul 13 07:14:30 PM PDT 24
Finished Jul 13 07:15:07 PM PDT 24
Peak memory 207096 kb
Host smart-668f6d91-a38e-479f-b8e4-b0c76678836e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=831950211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.831950211
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1855096731
Short name T434
Test name
Test status
Simulation time 161212837 ps
CPU time 0.8 seconds
Started Jul 13 07:14:34 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 206876 kb
Host smart-b99bad55-34e9-4e37-95ba-d3c425666ad8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1855096731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1855096731
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2348710594
Short name T2577
Test name
Test status
Simulation time 184903408 ps
CPU time 0.83 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206868 kb
Host smart-753cfdfa-36ab-4ae8-a087-2b6c345471c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23487
10594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2348710594
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3941073088
Short name T2018
Test name
Test status
Simulation time 209093634 ps
CPU time 0.86 seconds
Started Jul 13 07:14:30 PM PDT 24
Finished Jul 13 07:14:34 PM PDT 24
Peak memory 206864 kb
Host smart-476707b8-936b-4859-b345-48569841db69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39410
73088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3941073088
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3577782425
Short name T2326
Test name
Test status
Simulation time 143790393 ps
CPU time 0.79 seconds
Started Jul 13 07:14:32 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 206888 kb
Host smart-5243fea1-c54a-47b8-b94e-6ab7820d555d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35777
82425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3577782425
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1551735377
Short name T1779
Test name
Test status
Simulation time 180356786 ps
CPU time 0.9 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206852 kb
Host smart-4196e12a-4467-43df-bb63-6322e05a86d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15517
35377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1551735377
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.4186799389
Short name T444
Test name
Test status
Simulation time 219430740 ps
CPU time 0.88 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206872 kb
Host smart-06a4ef3e-7170-4807-884c-6c19dac7e341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41867
99389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.4186799389
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4074911446
Short name T2157
Test name
Test status
Simulation time 174115552 ps
CPU time 0.81 seconds
Started Jul 13 07:14:30 PM PDT 24
Finished Jul 13 07:14:34 PM PDT 24
Peak memory 206760 kb
Host smart-9dab2ba7-47ed-4041-8202-f2f5ed873d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40749
11446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4074911446
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.431191372
Short name T2237
Test name
Test status
Simulation time 216525274 ps
CPU time 0.92 seconds
Started Jul 13 07:14:33 PM PDT 24
Finished Jul 13 07:14:37 PM PDT 24
Peak memory 206676 kb
Host smart-7768ee15-d751-46bc-a1ed-b3ccb6461777
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=431191372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.431191372
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1202993998
Short name T2267
Test name
Test status
Simulation time 144820566 ps
CPU time 0.75 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206868 kb
Host smart-33eb0574-88ac-4c2d-be3e-d37c5e79f3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12029
93998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1202993998
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.908125204
Short name T1078
Test name
Test status
Simulation time 43167260 ps
CPU time 0.67 seconds
Started Jul 13 07:14:33 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 206696 kb
Host smart-2aaa7fa6-e3bc-40bb-95c3-9fa0b3acf842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90812
5204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.908125204
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.650826528
Short name T1077
Test name
Test status
Simulation time 21472976736 ps
CPU time 53 seconds
Started Jul 13 07:14:34 PM PDT 24
Finished Jul 13 07:15:30 PM PDT 24
Peak memory 215352 kb
Host smart-2f3200e2-c2ed-4ed7-a8ed-628fcd66f382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65082
6528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.650826528
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.178018397
Short name T1857
Test name
Test status
Simulation time 170787126 ps
CPU time 0.9 seconds
Started Jul 13 07:14:35 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 206892 kb
Host smart-5021ec3c-464a-42a3-b724-7ced09034d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17801
8397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.178018397
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2490119045
Short name T429
Test name
Test status
Simulation time 185398638 ps
CPU time 0.83 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206864 kb
Host smart-430772fe-34cc-4c46-b755-11d5485c2344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24901
19045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2490119045
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.93090259
Short name T1340
Test name
Test status
Simulation time 226161481 ps
CPU time 0.91 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206864 kb
Host smart-6b683433-d946-4393-86bb-6bf05f77d933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93090
259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.93090259
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.3167664084
Short name T694
Test name
Test status
Simulation time 165771094 ps
CPU time 0.87 seconds
Started Jul 13 07:14:29 PM PDT 24
Finished Jul 13 07:14:33 PM PDT 24
Peak memory 206884 kb
Host smart-1783b53d-93f1-41cf-a102-70059d91935e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676
64084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3167664084
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.700334441
Short name T565
Test name
Test status
Simulation time 160507262 ps
CPU time 0.83 seconds
Started Jul 13 07:14:34 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 206900 kb
Host smart-6edc4aa8-3f47-4f69-922c-1ee2e7b57d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70033
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.700334441
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1206177377
Short name T2717
Test name
Test status
Simulation time 215190065 ps
CPU time 0.93 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206868 kb
Host smart-aa463cb7-8edc-44ad-bdff-ae022d0e0258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
77377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1206177377
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.346357029
Short name T1148
Test name
Test status
Simulation time 150449995 ps
CPU time 0.87 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:14:32 PM PDT 24
Peak memory 206852 kb
Host smart-b0fadd98-f0d1-40aa-b6eb-63a42631bf45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34635
7029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.346357029
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3836606710
Short name T2253
Test name
Test status
Simulation time 220936411 ps
CPU time 0.99 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:14:31 PM PDT 24
Peak memory 206872 kb
Host smart-9815ec6c-c04b-4bea-989c-280a53d267fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38366
06710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3836606710
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1783735819
Short name T1257
Test name
Test status
Simulation time 5802205734 ps
CPU time 42.9 seconds
Started Jul 13 07:14:33 PM PDT 24
Finished Jul 13 07:15:19 PM PDT 24
Peak memory 207076 kb
Host smart-d4c31782-8187-498e-be11-2f9259800221
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1783735819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1783735819
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1924500014
Short name T2016
Test name
Test status
Simulation time 187305085 ps
CPU time 0.81 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 206880 kb
Host smart-470e2107-fb3f-4388-90d5-3df685098db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19245
00014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1924500014
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2040434865
Short name T2255
Test name
Test status
Simulation time 186610446 ps
CPU time 0.89 seconds
Started Jul 13 07:14:35 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 206864 kb
Host smart-18e49df5-c9eb-4ea2-8ab5-3fee5d148b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20404
34865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2040434865
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3641636139
Short name T210
Test name
Test status
Simulation time 911790647 ps
CPU time 2.02 seconds
Started Jul 13 07:14:31 PM PDT 24
Finished Jul 13 07:14:37 PM PDT 24
Peak memory 207056 kb
Host smart-50099420-c58c-4743-9adc-aead7e75d741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36416
36139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3641636139
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.847720930
Short name T2516
Test name
Test status
Simulation time 5103127672 ps
CPU time 141.65 seconds
Started Jul 13 07:14:29 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 207144 kb
Host smart-cb60ce9b-bd11-4e91-aa5a-bc67adafd838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84772
0930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.847720930
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1230976223
Short name T545
Test name
Test status
Simulation time 43338331 ps
CPU time 0.69 seconds
Started Jul 13 07:14:41 PM PDT 24
Finished Jul 13 07:14:43 PM PDT 24
Peak memory 207140 kb
Host smart-af90224b-9c57-4cd4-8777-800481e9c728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1230976223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1230976223
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2790132342
Short name T850
Test name
Test status
Simulation time 4335849609 ps
CPU time 4.85 seconds
Started Jul 13 07:14:32 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 206944 kb
Host smart-79e9e2c7-1928-4715-8b4d-4176a2d07186
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2790132342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2790132342
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.51185119
Short name T1918
Test name
Test status
Simulation time 13329958136 ps
CPU time 12.58 seconds
Started Jul 13 07:14:35 PM PDT 24
Finished Jul 13 07:14:50 PM PDT 24
Peak memory 206908 kb
Host smart-a22dadd1-1799-4ff8-b540-8d7fd6277144
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=51185119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.51185119
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1828346039
Short name T2382
Test name
Test status
Simulation time 23357565398 ps
CPU time 29.13 seconds
Started Jul 13 07:14:33 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 207144 kb
Host smart-5765bb05-7741-479a-aa9a-7d3528989911
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1828346039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.1828346039
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1669084935
Short name T1774
Test name
Test status
Simulation time 199011145 ps
CPU time 0.84 seconds
Started Jul 13 07:14:28 PM PDT 24
Finished Jul 13 07:14:32 PM PDT 24
Peak memory 206868 kb
Host smart-cb09107b-daf2-45c9-b0a8-6de0f49b0f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16690
84935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1669084935
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2638681255
Short name T804
Test name
Test status
Simulation time 145075951 ps
CPU time 0.83 seconds
Started Jul 13 07:14:35 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 206864 kb
Host smart-08a938a6-01bb-440e-81a8-1bcbb94bd2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26386
81255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2638681255
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.4200505120
Short name T2304
Test name
Test status
Simulation time 245248993 ps
CPU time 0.99 seconds
Started Jul 13 07:14:32 PM PDT 24
Finished Jul 13 07:14:36 PM PDT 24
Peak memory 206888 kb
Host smart-edf9727f-28bd-443d-ac78-816ae266a013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42005
05120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.4200505120
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1242218259
Short name T561
Test name
Test status
Simulation time 710514645 ps
CPU time 1.82 seconds
Started Jul 13 07:14:36 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 207044 kb
Host smart-f4fcb956-0dcc-4e7b-b7fd-74f6afcfc438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12422
18259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1242218259
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.651915551
Short name T1991
Test name
Test status
Simulation time 15494344902 ps
CPU time 32.84 seconds
Started Jul 13 07:14:35 PM PDT 24
Finished Jul 13 07:15:10 PM PDT 24
Peak memory 207156 kb
Host smart-e1dad8b6-e155-464d-ac25-34cc4b1ea99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65191
5551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.651915551
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.52600875
Short name T651
Test name
Test status
Simulation time 405435246 ps
CPU time 1.28 seconds
Started Jul 13 07:14:35 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 206860 kb
Host smart-a6850537-6e20-4549-bd0c-7430d91c244d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52600
875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.52600875
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.917188796
Short name T362
Test name
Test status
Simulation time 172721833 ps
CPU time 0.8 seconds
Started Jul 13 07:14:35 PM PDT 24
Finished Jul 13 07:14:38 PM PDT 24
Peak memory 206900 kb
Host smart-203d8264-954b-453c-871e-02fb807608b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91718
8796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.917188796
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1201819249
Short name T747
Test name
Test status
Simulation time 54389626 ps
CPU time 0.69 seconds
Started Jul 13 07:14:34 PM PDT 24
Finished Jul 13 07:14:37 PM PDT 24
Peak memory 206848 kb
Host smart-e8fdc79c-bf2f-47a0-8ddb-7c01cf6b2600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12018
19249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1201819249
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1135965479
Short name T1256
Test name
Test status
Simulation time 828251126 ps
CPU time 2.22 seconds
Started Jul 13 07:14:34 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 206980 kb
Host smart-9c855160-9087-43e7-a098-a7d499131e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11359
65479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1135965479
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3866611763
Short name T2416
Test name
Test status
Simulation time 226867924 ps
CPU time 1.5 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:42 PM PDT 24
Peak memory 207072 kb
Host smart-16238641-d4b3-427b-a0e2-1bc7741d23be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38666
11763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3866611763
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1861454103
Short name T420
Test name
Test status
Simulation time 238640642 ps
CPU time 0.93 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 206864 kb
Host smart-714bbf40-0d6c-499b-a5fc-d45a4032f3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18614
54103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1861454103
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.4017585758
Short name T2452
Test name
Test status
Simulation time 158832028 ps
CPU time 0.79 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:40 PM PDT 24
Peak memory 206800 kb
Host smart-ee753fab-9232-496d-ba79-e7ce88591bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175
85758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.4017585758
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4052451637
Short name T2662
Test name
Test status
Simulation time 257142411 ps
CPU time 0.97 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 205252 kb
Host smart-ace35923-c28f-4dd3-97d1-8bb1180ed419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40524
51637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4052451637
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.3547151602
Short name T2433
Test name
Test status
Simulation time 8205982091 ps
CPU time 28.08 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:15:11 PM PDT 24
Peak memory 207108 kb
Host smart-109f5e9d-e200-4b56-873c-803798d2008b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35471
51602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.3547151602
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.2291544680
Short name T569
Test name
Test status
Simulation time 192720841 ps
CPU time 0.81 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 206860 kb
Host smart-537ddd72-7b71-4f22-aa0a-599f1b65bd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22915
44680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2291544680
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3885988799
Short name T1652
Test name
Test status
Simulation time 23268759210 ps
CPU time 22.9 seconds
Started Jul 13 07:14:43 PM PDT 24
Finished Jul 13 07:15:07 PM PDT 24
Peak memory 206928 kb
Host smart-edc4a007-5f3c-43ee-9c25-b69660286be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38859
88799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3885988799
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1745955633
Short name T334
Test name
Test status
Simulation time 3298703629 ps
CPU time 4.07 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:14:46 PM PDT 24
Peak memory 206932 kb
Host smart-b1c9d6ff-2ec3-4cc0-a838-401e18b64250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17459
55633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1745955633
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1041502073
Short name T141
Test name
Test status
Simulation time 12886766107 ps
CPU time 349.82 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:20:34 PM PDT 24
Peak memory 207132 kb
Host smart-01ef3fc2-57d2-4a72-9e7a-8a8370761b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10415
02073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1041502073
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1551429485
Short name T1757
Test name
Test status
Simulation time 6292014874 ps
CPU time 184.49 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:17:46 PM PDT 24
Peak memory 207068 kb
Host smart-9d9d2314-f367-4308-b1d6-09bf8f79cadf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1551429485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1551429485
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.280527784
Short name T1837
Test name
Test status
Simulation time 236010911 ps
CPU time 0.9 seconds
Started Jul 13 07:14:41 PM PDT 24
Finished Jul 13 07:14:43 PM PDT 24
Peak memory 206620 kb
Host smart-ed655acd-0cbc-485b-b268-d16a16f7b677
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=280527784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.280527784
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1679365373
Short name T774
Test name
Test status
Simulation time 197047217 ps
CPU time 0.9 seconds
Started Jul 13 07:14:43 PM PDT 24
Finished Jul 13 07:14:45 PM PDT 24
Peak memory 206860 kb
Host smart-294df897-8db5-4db7-a10f-a78ded95e5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16793
65373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1679365373
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2381498424
Short name T1310
Test name
Test status
Simulation time 5733356423 ps
CPU time 57.45 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:15:37 PM PDT 24
Peak memory 207136 kb
Host smart-bcf21b71-300f-4115-9908-3fc09cca4edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23814
98424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2381498424
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2148724600
Short name T1914
Test name
Test status
Simulation time 7130419993 ps
CPU time 68.63 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:15:51 PM PDT 24
Peak memory 207116 kb
Host smart-62399863-e600-4e27-a39b-a9284dc8b5f8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2148724600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2148724600
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1100990867
Short name T1108
Test name
Test status
Simulation time 155847128 ps
CPU time 0.82 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 205376 kb
Host smart-350c87ba-734d-4a44-9479-fb70ca8c31f5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1100990867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1100990867
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2245205516
Short name T2268
Test name
Test status
Simulation time 167427062 ps
CPU time 0.8 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:14:42 PM PDT 24
Peak memory 206756 kb
Host smart-06e72d28-c823-48bf-85d9-6da78865a186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22452
05516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2245205516
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.4048527441
Short name T2110
Test name
Test status
Simulation time 183035704 ps
CPU time 0.84 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 206848 kb
Host smart-525be30b-3a7d-4b53-b2af-4e7465429b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40485
27441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.4048527441
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3137312399
Short name T1442
Test name
Test status
Simulation time 151678226 ps
CPU time 0.8 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 206872 kb
Host smart-ba37b250-d03d-437c-b6f6-894b01582796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31373
12399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3137312399
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3372730505
Short name T1210
Test name
Test status
Simulation time 159223029 ps
CPU time 0.78 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 207052 kb
Host smart-8c047179-7e2d-45bc-bb2e-e643651e20b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33727
30505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3372730505
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1788638338
Short name T312
Test name
Test status
Simulation time 139857828 ps
CPU time 0.79 seconds
Started Jul 13 07:14:41 PM PDT 24
Finished Jul 13 07:14:43 PM PDT 24
Peak memory 206528 kb
Host smart-6f1ddae8-7c58-492f-867c-8593a8d6c007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17886
38338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1788638338
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.4004114884
Short name T1452
Test name
Test status
Simulation time 145006134 ps
CPU time 0.82 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:14:42 PM PDT 24
Peak memory 206808 kb
Host smart-eb63acc2-c401-40c5-b9fd-8beeb05626d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40041
14884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.4004114884
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.657827063
Short name T948
Test name
Test status
Simulation time 243396815 ps
CPU time 0.93 seconds
Started Jul 13 07:14:38 PM PDT 24
Finished Jul 13 07:14:40 PM PDT 24
Peak memory 206880 kb
Host smart-ff96c153-436c-4d9c-bb9c-e0294b03434e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=657827063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.657827063
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1862609753
Short name T331
Test name
Test status
Simulation time 145764820 ps
CPU time 0.8 seconds
Started Jul 13 07:14:38 PM PDT 24
Finished Jul 13 07:14:40 PM PDT 24
Peak memory 206868 kb
Host smart-1c9f2ff9-7f01-42a7-9188-638a10632d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18626
09753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1862609753
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.747933946
Short name T1800
Test name
Test status
Simulation time 48974705 ps
CPU time 0.66 seconds
Started Jul 13 07:14:43 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 206868 kb
Host smart-a19b66ca-e9d3-482c-9ced-14c3f33b6021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74793
3946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.747933946
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1219645713
Short name T1956
Test name
Test status
Simulation time 12182340758 ps
CPU time 29.1 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:15:11 PM PDT 24
Peak memory 207152 kb
Host smart-633b73b8-b157-4134-a7cf-b858ea5aff1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12196
45713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1219645713
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.133901810
Short name T1507
Test name
Test status
Simulation time 206677369 ps
CPU time 0.86 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:40 PM PDT 24
Peak memory 206868 kb
Host smart-cb619124-e6b1-40a5-af6f-263fec84cd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13390
1810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.133901810
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1470438804
Short name T706
Test name
Test status
Simulation time 185667909 ps
CPU time 0.87 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 206864 kb
Host smart-0df8b921-199a-4918-b5a7-69480181625e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14704
38804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1470438804
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.146151646
Short name T1303
Test name
Test status
Simulation time 185925517 ps
CPU time 0.85 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:14:45 PM PDT 24
Peak memory 206900 kb
Host smart-68bd7b3a-3a30-4cc7-842e-7fda86415ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14615
1646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.146151646
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2731545844
Short name T698
Test name
Test status
Simulation time 168451199 ps
CPU time 0.84 seconds
Started Jul 13 07:14:42 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 206872 kb
Host smart-94d931b8-8f1b-43ad-9077-da59e456ddfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
45844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2731545844
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3369998499
Short name T1731
Test name
Test status
Simulation time 145576481 ps
CPU time 0.82 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 206832 kb
Host smart-07d455c7-bd93-44e0-aa97-804d692da219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33699
98499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3369998499
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2312130445
Short name T1289
Test name
Test status
Simulation time 153898845 ps
CPU time 0.85 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 206880 kb
Host smart-bc93ace4-9e96-481d-9493-a215d43257a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23121
30445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2312130445
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4185572421
Short name T828
Test name
Test status
Simulation time 148298220 ps
CPU time 0.77 seconds
Started Jul 13 07:14:43 PM PDT 24
Finished Jul 13 07:14:45 PM PDT 24
Peak memory 206856 kb
Host smart-8d35c81d-592b-4741-b3cc-6f1b21975f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41855
72421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4185572421
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2596992213
Short name T631
Test name
Test status
Simulation time 260520131 ps
CPU time 0.97 seconds
Started Jul 13 07:14:45 PM PDT 24
Finished Jul 13 07:14:46 PM PDT 24
Peak memory 206760 kb
Host smart-462d55c5-60fd-44a7-9387-43552995d566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25969
92213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2596992213
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.397134640
Short name T1996
Test name
Test status
Simulation time 4315747465 ps
CPU time 33.29 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:15:14 PM PDT 24
Peak memory 207132 kb
Host smart-6e5f8363-acca-471d-b45c-8dafabd12801
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=397134640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.397134640
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1047618843
Short name T1083
Test name
Test status
Simulation time 157236611 ps
CPU time 0.85 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:14:43 PM PDT 24
Peak memory 206856 kb
Host smart-b2b74429-f504-4475-86a3-158b43ae48ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10476
18843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1047618843
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1044170196
Short name T2724
Test name
Test status
Simulation time 229091532 ps
CPU time 0.82 seconds
Started Jul 13 07:14:44 PM PDT 24
Finished Jul 13 07:14:46 PM PDT 24
Peak memory 206876 kb
Host smart-9f64e8d6-f4a6-439b-901a-0807dccb86f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10441
70196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1044170196
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.1645882102
Short name T2464
Test name
Test status
Simulation time 650588027 ps
CPU time 1.6 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:14:43 PM PDT 24
Peak memory 206872 kb
Host smart-ba988a91-668a-48b2-be6b-0b479d1e0016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16458
82102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.1645882102
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1994144956
Short name T309
Test name
Test status
Simulation time 6350161168 ps
CPU time 181.08 seconds
Started Jul 13 07:14:41 PM PDT 24
Finished Jul 13 07:17:43 PM PDT 24
Peak memory 207084 kb
Host smart-ded2426a-697c-43f6-92a9-653670fb5025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19941
44956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1994144956
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.3660058883
Short name T1701
Test name
Test status
Simulation time 34709506 ps
CPU time 0.68 seconds
Started Jul 13 07:14:52 PM PDT 24
Finished Jul 13 07:14:54 PM PDT 24
Peak memory 206936 kb
Host smart-990fe780-bd17-46de-ad7d-4a0ae6089cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3660058883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3660058883
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.33252997
Short name T560
Test name
Test status
Simulation time 3655571327 ps
CPU time 5 seconds
Started Jul 13 07:14:44 PM PDT 24
Finished Jul 13 07:14:50 PM PDT 24
Peak memory 207088 kb
Host smart-5b83731c-6851-4998-b6f7-bc8f3cfbd519
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=33252997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.33252997
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2765116099
Short name T1413
Test name
Test status
Simulation time 13395339240 ps
CPU time 13.72 seconds
Started Jul 13 07:14:41 PM PDT 24
Finished Jul 13 07:14:56 PM PDT 24
Peak memory 206708 kb
Host smart-f373aaa5-bd94-424d-998c-866242c5587c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2765116099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2765116099
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3821770872
Short name T2203
Test name
Test status
Simulation time 23487719698 ps
CPU time 21.69 seconds
Started Jul 13 07:14:43 PM PDT 24
Finished Jul 13 07:15:06 PM PDT 24
Peak memory 207128 kb
Host smart-b91aa8b1-8bf1-4a3c-bf01-b334f26fd56e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3821770872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3821770872
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.4124954859
Short name T2108
Test name
Test status
Simulation time 176652216 ps
CPU time 0.82 seconds
Started Jul 13 07:14:37 PM PDT 24
Finished Jul 13 07:14:39 PM PDT 24
Peak memory 206868 kb
Host smart-aa6ffd61-672e-48ee-b28e-03ba33059891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41249
54859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.4124954859
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3375268989
Short name T2019
Test name
Test status
Simulation time 191949838 ps
CPU time 0.88 seconds
Started Jul 13 07:14:44 PM PDT 24
Finished Jul 13 07:14:46 PM PDT 24
Peak memory 206868 kb
Host smart-125f813a-d94c-49a8-9dac-05d82a95cca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33752
68989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3375268989
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2804317662
Short name T2399
Test name
Test status
Simulation time 192383304 ps
CPU time 0.85 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:41 PM PDT 24
Peak memory 206864 kb
Host smart-04efd9cf-5277-4f4c-ad44-40cdc92029ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28043
17662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2804317662
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2721996330
Short name T1881
Test name
Test status
Simulation time 651884110 ps
CPU time 1.63 seconds
Started Jul 13 07:14:40 PM PDT 24
Finished Jul 13 07:14:44 PM PDT 24
Peak memory 207072 kb
Host smart-7d192fe0-408e-4eb8-bff8-bca965326fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27219
96330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2721996330
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.1945448869
Short name T151
Test name
Test status
Simulation time 14894492502 ps
CPU time 26.13 seconds
Started Jul 13 07:14:38 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 207076 kb
Host smart-faa188a3-d7e4-4222-af59-50f303d410cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454
48869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1945448869
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.1989449634
Short name T1399
Test name
Test status
Simulation time 403251681 ps
CPU time 1.31 seconds
Started Jul 13 07:14:39 PM PDT 24
Finished Jul 13 07:14:42 PM PDT 24
Peak memory 206848 kb
Host smart-262fd80e-eccd-4755-b899-6a7da43849e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19894
49634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.1989449634
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1852271435
Short name T1669
Test name
Test status
Simulation time 179940564 ps
CPU time 0.78 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:51 PM PDT 24
Peak memory 206852 kb
Host smart-61aedf33-34eb-4125-a2e0-da102fafb074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18522
71435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1852271435
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.874959972
Short name T1863
Test name
Test status
Simulation time 26721920 ps
CPU time 0.65 seconds
Started Jul 13 07:14:50 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 206856 kb
Host smart-81eed07b-8e23-489f-a238-dbe336e2e055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87495
9972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.874959972
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1326100401
Short name T1878
Test name
Test status
Simulation time 875967171 ps
CPU time 2.26 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 207048 kb
Host smart-4d9b2d60-bd97-44a6-8782-8b5b06eb6633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13261
00401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1326100401
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1136017283
Short name T816
Test name
Test status
Simulation time 181952653 ps
CPU time 1.62 seconds
Started Jul 13 07:14:50 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 207080 kb
Host smart-9f52b323-47f9-4e6a-9ad0-b3f142236cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11360
17283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1136017283
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.962173709
Short name T1222
Test name
Test status
Simulation time 191461149 ps
CPU time 0.85 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 206856 kb
Host smart-c8e5ad4f-00c1-484f-96b0-4761c876757a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96217
3709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.962173709
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.4279370321
Short name T2622
Test name
Test status
Simulation time 151704528 ps
CPU time 0.77 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 206860 kb
Host smart-8a46912d-b4c0-4007-9ff8-45a483314997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42793
70321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.4279370321
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2686315292
Short name T2663
Test name
Test status
Simulation time 199288962 ps
CPU time 0.88 seconds
Started Jul 13 07:14:48 PM PDT 24
Finished Jul 13 07:14:50 PM PDT 24
Peak memory 206820 kb
Host smart-a7ae5f53-f97b-4aa5-b5dd-25a08e780d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
15292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2686315292
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.4177760545
Short name T296
Test name
Test status
Simulation time 12269672472 ps
CPU time 44.83 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 207072 kb
Host smart-b5ff4e2f-d9df-4a1d-98f4-56ca85290ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41777
60545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.4177760545
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2931212754
Short name T955
Test name
Test status
Simulation time 179682023 ps
CPU time 0.83 seconds
Started Jul 13 07:14:52 PM PDT 24
Finished Jul 13 07:14:54 PM PDT 24
Peak memory 207104 kb
Host smart-a2b84e3a-a7fa-4f9c-858a-3a26a4a255a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312
12754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2931212754
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3121310644
Short name T2316
Test name
Test status
Simulation time 23350126099 ps
CPU time 22.91 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:15:13 PM PDT 24
Peak memory 206928 kb
Host smart-e811a882-f8b1-4aad-8267-a2f0b623d198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31213
10644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3121310644
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1045898470
Short name T27
Test name
Test status
Simulation time 3357327049 ps
CPU time 4.2 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:55 PM PDT 24
Peak memory 206920 kb
Host smart-563ad300-7c94-43da-9e88-1f2b8793149a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
98470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1045898470
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2769559859
Short name T1659
Test name
Test status
Simulation time 5512660408 ps
CPU time 40.54 seconds
Started Jul 13 07:14:48 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 207076 kb
Host smart-7e64f948-6307-4a0f-ac0b-bd2596d24672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27695
59859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2769559859
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2104366379
Short name T2686
Test name
Test status
Simulation time 6272483221 ps
CPU time 177.34 seconds
Started Jul 13 07:14:52 PM PDT 24
Finished Jul 13 07:17:50 PM PDT 24
Peak memory 207032 kb
Host smart-845fa695-6373-44eb-b32e-258f09a7fdf9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2104366379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2104366379
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.476152607
Short name T613
Test name
Test status
Simulation time 229072693 ps
CPU time 0.89 seconds
Started Jul 13 07:14:48 PM PDT 24
Finished Jul 13 07:14:50 PM PDT 24
Peak memory 206884 kb
Host smart-224339c4-38ba-4e6c-8075-d5e6751b5a1b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=476152607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.476152607
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2633655436
Short name T1010
Test name
Test status
Simulation time 209340642 ps
CPU time 0.88 seconds
Started Jul 13 07:14:51 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 206732 kb
Host smart-32b64fa7-eb51-4448-bf51-6cdd7138cba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26336
55436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2633655436
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.3776134924
Short name T2439
Test name
Test status
Simulation time 3716806840 ps
CPU time 102 seconds
Started Jul 13 07:14:47 PM PDT 24
Finished Jul 13 07:16:30 PM PDT 24
Peak memory 207140 kb
Host smart-a4ab5e44-ac53-4f2d-9f27-c62c7fe3a96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37761
34924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.3776134924
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.106481102
Short name T614
Test name
Test status
Simulation time 4335792444 ps
CPU time 114.3 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 207084 kb
Host smart-3ec4371b-ac17-4ff1-830b-c4abc8a5f154
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=106481102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.106481102
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2618780076
Short name T1994
Test name
Test status
Simulation time 203347856 ps
CPU time 0.85 seconds
Started Jul 13 07:14:47 PM PDT 24
Finished Jul 13 07:14:49 PM PDT 24
Peak memory 206864 kb
Host smart-9026f9ee-08d9-4bdd-b38b-49c18faff590
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2618780076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2618780076
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1885923462
Short name T2708
Test name
Test status
Simulation time 175444557 ps
CPU time 0.79 seconds
Started Jul 13 07:14:51 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 206860 kb
Host smart-3cc322c9-c181-4abf-a8a8-365f817a89f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18859
23462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1885923462
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1366071754
Short name T132
Test name
Test status
Simulation time 206467291 ps
CPU time 0.87 seconds
Started Jul 13 07:14:51 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 206772 kb
Host smart-8c467187-3790-4116-bc41-de74933720a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13660
71754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1366071754
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1353067204
Short name T1055
Test name
Test status
Simulation time 254222218 ps
CPU time 0.9 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 206880 kb
Host smart-efc25618-749a-4af8-b3cf-f6171525d1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13530
67204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1353067204
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1234214795
Short name T1852
Test name
Test status
Simulation time 203554666 ps
CPU time 0.82 seconds
Started Jul 13 07:14:48 PM PDT 24
Finished Jul 13 07:14:49 PM PDT 24
Peak memory 206868 kb
Host smart-4177b130-d27f-4438-a962-edf09da96f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12342
14795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1234214795
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.467878611
Short name T2553
Test name
Test status
Simulation time 196744675 ps
CPU time 0.87 seconds
Started Jul 13 07:14:50 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 206868 kb
Host smart-7d0bcd61-946f-40dc-a9de-cdb61bf691b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46787
8611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.467878611
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2764109938
Short name T1804
Test name
Test status
Simulation time 168002749 ps
CPU time 0.84 seconds
Started Jul 13 07:14:48 PM PDT 24
Finished Jul 13 07:14:50 PM PDT 24
Peak memory 206872 kb
Host smart-bfb93a5d-cb8e-45b4-8cc7-d2dd552f6e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27641
09938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2764109938
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.112424685
Short name T1641
Test name
Test status
Simulation time 249312072 ps
CPU time 0.92 seconds
Started Jul 13 07:14:51 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 206884 kb
Host smart-33a586d7-d254-43e5-95c4-2c1db4d07166
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=112424685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.112424685
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.988403798
Short name T1094
Test name
Test status
Simulation time 150256537 ps
CPU time 0.8 seconds
Started Jul 13 07:14:48 PM PDT 24
Finished Jul 13 07:14:50 PM PDT 24
Peak memory 206876 kb
Host smart-21b0e885-2774-4e21-8222-10b71e48b8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98840
3798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.988403798
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1343903327
Short name T1100
Test name
Test status
Simulation time 61839010 ps
CPU time 0.67 seconds
Started Jul 13 07:14:54 PM PDT 24
Finished Jul 13 07:14:55 PM PDT 24
Peak memory 206864 kb
Host smart-e9b6068f-be88-4d9d-972a-915885e50e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13439
03327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1343903327
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1740678306
Short name T2124
Test name
Test status
Simulation time 19968870901 ps
CPU time 47.85 seconds
Started Jul 13 07:14:53 PM PDT 24
Finished Jul 13 07:15:41 PM PDT 24
Peak memory 215336 kb
Host smart-c070fdee-2108-4908-bef1-dca68eb67b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17406
78306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1740678306
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.387127461
Short name T1114
Test name
Test status
Simulation time 188827225 ps
CPU time 0.94 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 206860 kb
Host smart-b484f443-24e5-4f07-9146-648b005955f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
7461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.387127461
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2975634837
Short name T2051
Test name
Test status
Simulation time 190260652 ps
CPU time 0.82 seconds
Started Jul 13 07:14:53 PM PDT 24
Finished Jul 13 07:14:55 PM PDT 24
Peak memory 206864 kb
Host smart-57f4c42d-fde3-44c3-b03f-1c0358a19dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29756
34837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2975634837
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3121065082
Short name T1596
Test name
Test status
Simulation time 161127847 ps
CPU time 0.81 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:51 PM PDT 24
Peak memory 207052 kb
Host smart-1fbef122-d82a-4798-ad12-afa2a264be61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
65082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3121065082
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.744530193
Short name T1575
Test name
Test status
Simulation time 182885112 ps
CPU time 0.87 seconds
Started Jul 13 07:14:51 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 206868 kb
Host smart-266de309-62c8-4e32-ad3c-d4ad0cddbf54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74453
0193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.744530193
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1811258259
Short name T1620
Test name
Test status
Simulation time 160870281 ps
CPU time 0.78 seconds
Started Jul 13 07:14:51 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 206864 kb
Host smart-7a9b4c1e-c8c3-4a2a-8063-d78f2af684e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18112
58259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1811258259
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.4056617515
Short name T543
Test name
Test status
Simulation time 182462717 ps
CPU time 0.82 seconds
Started Jul 13 07:14:53 PM PDT 24
Finished Jul 13 07:14:55 PM PDT 24
Peak memory 206860 kb
Host smart-77edc9c6-2c45-467c-8405-7bde3e00459b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40566
17515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.4056617515
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1516033732
Short name T313
Test name
Test status
Simulation time 142167470 ps
CPU time 0.75 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:52 PM PDT 24
Peak memory 206868 kb
Host smart-9b2380cc-1c94-4449-82a7-5c50b267d682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15160
33732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1516033732
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.673621487
Short name T2035
Test name
Test status
Simulation time 205844188 ps
CPU time 0.96 seconds
Started Jul 13 07:14:48 PM PDT 24
Finished Jul 13 07:14:50 PM PDT 24
Peak memory 206864 kb
Host smart-3c052e7a-4156-4737-a70a-503b4f8e8cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67362
1487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.673621487
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3811541455
Short name T1154
Test name
Test status
Simulation time 6295692496 ps
CPU time 46.21 seconds
Started Jul 13 07:14:52 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 207020 kb
Host smart-b591e412-4861-464c-99c6-fa743de441f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3811541455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3811541455
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.508537070
Short name T1382
Test name
Test status
Simulation time 218384355 ps
CPU time 0.91 seconds
Started Jul 13 07:14:57 PM PDT 24
Finished Jul 13 07:14:59 PM PDT 24
Peak memory 206844 kb
Host smart-23b98a68-eaf2-4131-867b-7a8478bb2bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50853
7070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.508537070
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.845396214
Short name T1623
Test name
Test status
Simulation time 209874248 ps
CPU time 0.9 seconds
Started Jul 13 07:14:48 PM PDT 24
Finished Jul 13 07:14:49 PM PDT 24
Peak memory 206892 kb
Host smart-b1358fa8-da68-4940-b564-7112d4cce4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84539
6214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.845396214
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.4071491632
Short name T505
Test name
Test status
Simulation time 912273636 ps
CPU time 1.88 seconds
Started Jul 13 07:14:54 PM PDT 24
Finished Jul 13 07:14:56 PM PDT 24
Peak memory 207076 kb
Host smart-e2d4014a-008b-4c70-b3ff-8ca3665848c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714
91632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.4071491632
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2741312369
Short name T1595
Test name
Test status
Simulation time 5149487804 ps
CPU time 38.18 seconds
Started Jul 13 07:14:51 PM PDT 24
Finished Jul 13 07:15:30 PM PDT 24
Peak memory 207072 kb
Host smart-1e0a5467-4ba1-4916-86eb-4e43739d6158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27413
12369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2741312369
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3501853072
Short name T993
Test name
Test status
Simulation time 41981105 ps
CPU time 0.7 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206920 kb
Host smart-49b6a0ea-2dfb-4603-a906-5a9807e44b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3501853072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3501853072
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1450483060
Short name T1685
Test name
Test status
Simulation time 3411645567 ps
CPU time 4.21 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 207112 kb
Host smart-0c84a03a-dc5e-4f82-b824-fa8075a6cf26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1450483060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1450483060
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3711639285
Short name T571
Test name
Test status
Simulation time 13421485388 ps
CPU time 12.27 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 207060 kb
Host smart-1944c62d-1d1d-46fb-aedc-1428fa8bebac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3711639285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3711639285
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.34475776
Short name T11
Test name
Test status
Simulation time 23329508774 ps
CPU time 22.78 seconds
Started Jul 13 07:14:53 PM PDT 24
Finished Jul 13 07:15:16 PM PDT 24
Peak memory 206940 kb
Host smart-fadae2d8-da65-4e3e-a727-d0636b8978e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=34475776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.34475776
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1159729018
Short name T1086
Test name
Test status
Simulation time 141637658 ps
CPU time 0.82 seconds
Started Jul 13 07:14:51 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 206868 kb
Host smart-bce4a2c3-9887-4e10-b58b-58911f613752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11597
29018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1159729018
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.1682739151
Short name T2710
Test name
Test status
Simulation time 136325670 ps
CPU time 0.77 seconds
Started Jul 13 07:14:52 PM PDT 24
Finished Jul 13 07:14:53 PM PDT 24
Peak memory 207104 kb
Host smart-96b31365-f67f-495d-aadd-3d84ad8722ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827
39151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.1682739151
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.246190717
Short name T666
Test name
Test status
Simulation time 297653469 ps
CPU time 1.17 seconds
Started Jul 13 07:14:49 PM PDT 24
Finished Jul 13 07:14:51 PM PDT 24
Peak memory 206808 kb
Host smart-da1874b3-dfd2-4daa-aeaf-885f2f3ee8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24619
0717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.246190717
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.382340611
Short name T1621
Test name
Test status
Simulation time 464152354 ps
CPU time 1.22 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:14:58 PM PDT 24
Peak memory 206860 kb
Host smart-4cf662f3-510b-4c8b-a885-76039b60eeef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38234
0611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.382340611
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2971023098
Short name T1957
Test name
Test status
Simulation time 12893208534 ps
CPU time 24.48 seconds
Started Jul 13 07:14:54 PM PDT 24
Finished Jul 13 07:15:19 PM PDT 24
Peak memory 207140 kb
Host smart-704e6c70-0f8d-43dd-875d-3074a96ec51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29710
23098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2971023098
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.390502070
Short name T1653
Test name
Test status
Simulation time 512784234 ps
CPU time 1.49 seconds
Started Jul 13 07:14:55 PM PDT 24
Finished Jul 13 07:14:57 PM PDT 24
Peak memory 206872 kb
Host smart-a2299b9b-bd77-4ef5-833e-8a2947982798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39050
2070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.390502070
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.3664965337
Short name T1147
Test name
Test status
Simulation time 141834689 ps
CPU time 0.85 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206856 kb
Host smart-0c13d0c9-e9e1-4785-bddc-6617055abd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649
65337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3664965337
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2218553512
Short name T1087
Test name
Test status
Simulation time 53477221 ps
CPU time 0.69 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:14:58 PM PDT 24
Peak memory 206844 kb
Host smart-78cb0937-2f6f-43e5-890d-9cbbcbe75f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22185
53512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2218553512
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2345778835
Short name T291
Test name
Test status
Simulation time 867277659 ps
CPU time 2.1 seconds
Started Jul 13 07:14:57 PM PDT 24
Finished Jul 13 07:15:01 PM PDT 24
Peak memory 207068 kb
Host smart-6cdeab3b-8b5c-40d6-be7b-492c4107f1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23457
78835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2345778835
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3088426546
Short name T959
Test name
Test status
Simulation time 191158326 ps
CPU time 2.28 seconds
Started Jul 13 07:14:54 PM PDT 24
Finished Jul 13 07:14:57 PM PDT 24
Peak memory 207016 kb
Host smart-5d5515ec-9970-40fb-a1c3-d1a541d1923b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30884
26546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3088426546
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2435645231
Short name T1772
Test name
Test status
Simulation time 200773842 ps
CPU time 0.85 seconds
Started Jul 13 07:14:57 PM PDT 24
Finished Jul 13 07:14:59 PM PDT 24
Peak memory 206820 kb
Host smart-3e2c2209-c30b-49be-a872-83766277dc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24356
45231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2435645231
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3022708634
Short name T1574
Test name
Test status
Simulation time 138509915 ps
CPU time 0.78 seconds
Started Jul 13 07:14:55 PM PDT 24
Finished Jul 13 07:14:56 PM PDT 24
Peak memory 206856 kb
Host smart-8257672a-78d6-4833-a05b-bbf896d2182e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30227
08634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3022708634
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3050026957
Short name T1979
Test name
Test status
Simulation time 237807536 ps
CPU time 0.97 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206872 kb
Host smart-bf4355fb-e29a-45a4-9b26-555f94abec4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
26957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3050026957
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.785983514
Short name T2161
Test name
Test status
Simulation time 5585374576 ps
CPU time 40.92 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:15:38 PM PDT 24
Peak memory 207064 kb
Host smart-4b430b19-05e9-4545-8688-550c97e9eb54
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=785983514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.785983514
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.3404872967
Short name T1312
Test name
Test status
Simulation time 10162642498 ps
CPU time 95.53 seconds
Started Jul 13 07:15:01 PM PDT 24
Finished Jul 13 07:16:38 PM PDT 24
Peak memory 207116 kb
Host smart-0b79e07e-5626-43e0-a6f4-bc82f41db766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34048
72967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.3404872967
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3950443406
Short name T1522
Test name
Test status
Simulation time 216180699 ps
CPU time 0.86 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:14:58 PM PDT 24
Peak memory 206872 kb
Host smart-f27b30e4-1e2c-4046-9ea2-9a18dcdb2ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39504
43406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3950443406
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.3796873088
Short name T2063
Test name
Test status
Simulation time 23287255443 ps
CPU time 21.4 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:15:18 PM PDT 24
Peak memory 206876 kb
Host smart-1425880f-965e-40c7-8bd8-7d1e7da84b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37968
73088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.3796873088
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1678400741
Short name T2148
Test name
Test status
Simulation time 3338250408 ps
CPU time 4.08 seconds
Started Jul 13 07:14:57 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206932 kb
Host smart-0aec8e0e-598d-43d6-aeab-be40a8e7c57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16784
00741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1678400741
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1414395011
Short name T951
Test name
Test status
Simulation time 12933013091 ps
CPU time 130.33 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:17:07 PM PDT 24
Peak memory 207132 kb
Host smart-b0569ac7-fb34-4e09-a970-7735958e6993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14143
95011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1414395011
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.894975319
Short name T916
Test name
Test status
Simulation time 3418393996 ps
CPU time 95.43 seconds
Started Jul 13 07:14:57 PM PDT 24
Finished Jul 13 07:16:33 PM PDT 24
Peak memory 207068 kb
Host smart-fbadf529-d4bd-4a61-a227-99f90fd534fd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=894975319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.894975319
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.648401653
Short name T2721
Test name
Test status
Simulation time 305058934 ps
CPU time 0.98 seconds
Started Jul 13 07:14:57 PM PDT 24
Finished Jul 13 07:14:59 PM PDT 24
Peak memory 206876 kb
Host smart-6c62b436-72e3-4e7a-b857-e6ddbc23a5f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=648401653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.648401653
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2748084989
Short name T2195
Test name
Test status
Simulation time 258651284 ps
CPU time 0.97 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:04 PM PDT 24
Peak memory 206868 kb
Host smart-f40d7e57-11a7-4d33-8768-13613de55874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27480
84989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2748084989
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1176494713
Short name T2544
Test name
Test status
Simulation time 6290687881 ps
CPU time 181.52 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:18:02 PM PDT 24
Peak memory 207080 kb
Host smart-7cfce2f8-06fe-436f-a706-b8ea011c8f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11764
94713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1176494713
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.4164254367
Short name T872
Test name
Test status
Simulation time 4567028588 ps
CPU time 34.14 seconds
Started Jul 13 07:14:59 PM PDT 24
Finished Jul 13 07:15:34 PM PDT 24
Peak memory 207144 kb
Host smart-9462822d-2c44-4806-8379-5498c5361d7d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4164254367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.4164254367
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2109100388
Short name T741
Test name
Test status
Simulation time 170253729 ps
CPU time 0.85 seconds
Started Jul 13 07:14:59 PM PDT 24
Finished Jul 13 07:15:01 PM PDT 24
Peak memory 206852 kb
Host smart-3b30831a-a7d1-4570-bb97-c0966c9669ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2109100388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2109100388
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.4243533099
Short name T1441
Test name
Test status
Simulation time 193924723 ps
CPU time 0.86 seconds
Started Jul 13 07:14:59 PM PDT 24
Finished Jul 13 07:15:00 PM PDT 24
Peak memory 206868 kb
Host smart-40a273c6-3bcd-489d-8ebc-feaf7c9c8c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42435
33099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.4243533099
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1016807005
Short name T2420
Test name
Test status
Simulation time 205526822 ps
CPU time 0.92 seconds
Started Jul 13 07:14:55 PM PDT 24
Finished Jul 13 07:14:57 PM PDT 24
Peak memory 206912 kb
Host smart-2b50777c-1b12-4344-acce-8a5f55afaee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10168
07005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1016807005
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.343639519
Short name T413
Test name
Test status
Simulation time 222722066 ps
CPU time 0.87 seconds
Started Jul 13 07:14:57 PM PDT 24
Finished Jul 13 07:14:59 PM PDT 24
Peak memory 206856 kb
Host smart-9cf61952-3b36-4411-acbd-a193552a463d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363
9519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.343639519
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.4287995401
Short name T1961
Test name
Test status
Simulation time 183731291 ps
CPU time 0.83 seconds
Started Jul 13 07:14:58 PM PDT 24
Finished Jul 13 07:15:00 PM PDT 24
Peak memory 206856 kb
Host smart-8f8bfb0b-e62e-41ec-900c-733bcb283e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42879
95401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.4287995401
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1357401772
Short name T918
Test name
Test status
Simulation time 151293862 ps
CPU time 0.85 seconds
Started Jul 13 07:15:01 PM PDT 24
Finished Jul 13 07:15:03 PM PDT 24
Peak memory 206884 kb
Host smart-f8c2c316-323d-4ada-96ba-65c8cf83d5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13574
01772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1357401772
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.281248100
Short name T158
Test name
Test status
Simulation time 161577681 ps
CPU time 0.79 seconds
Started Jul 13 07:14:54 PM PDT 24
Finished Jul 13 07:14:55 PM PDT 24
Peak memory 206872 kb
Host smart-68c644b3-72a1-4135-8acd-11e9097d3d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28124
8100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.281248100
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1531575462
Short name T2525
Test name
Test status
Simulation time 223235817 ps
CPU time 0.92 seconds
Started Jul 13 07:15:01 PM PDT 24
Finished Jul 13 07:15:04 PM PDT 24
Peak memory 206880 kb
Host smart-68419f2a-10d4-4f25-adbe-3a98d5b24653
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1531575462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1531575462
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3798250335
Short name T2287
Test name
Test status
Simulation time 165806428 ps
CPU time 0.81 seconds
Started Jul 13 07:14:59 PM PDT 24
Finished Jul 13 07:15:01 PM PDT 24
Peak memory 206860 kb
Host smart-9d23ce6b-c054-4ba8-8b2d-44d49350e99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37982
50335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3798250335
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1815332727
Short name T1298
Test name
Test status
Simulation time 50267928 ps
CPU time 0.7 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206860 kb
Host smart-9ebd5173-3715-4630-bfe4-3a16181b2f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18153
32727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1815332727
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2794306668
Short name T1564
Test name
Test status
Simulation time 20383758788 ps
CPU time 42.94 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:15:41 PM PDT 24
Peak memory 215312 kb
Host smart-d1c8ed41-269e-43ca-bc1c-7ae89264f937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27943
06668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2794306668
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2652781304
Short name T1034
Test name
Test status
Simulation time 182555382 ps
CPU time 0.84 seconds
Started Jul 13 07:14:58 PM PDT 24
Finished Jul 13 07:15:00 PM PDT 24
Peak memory 206848 kb
Host smart-e0b75502-6a8e-4a84-bdf5-4eaec2fff6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26527
81304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2652781304
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3675206576
Short name T1785
Test name
Test status
Simulation time 212184406 ps
CPU time 0.87 seconds
Started Jul 13 07:14:55 PM PDT 24
Finished Jul 13 07:14:56 PM PDT 24
Peak memory 206864 kb
Host smart-9e14d887-62a4-47d3-ae24-683276351f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36752
06576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3675206576
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.406514176
Short name T480
Test name
Test status
Simulation time 303967161 ps
CPU time 1.01 seconds
Started Jul 13 07:14:55 PM PDT 24
Finished Jul 13 07:14:57 PM PDT 24
Peak memory 206848 kb
Host smart-b61ab587-c386-47b2-9fd2-fdf24aa7eccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40651
4176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.406514176
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.172328809
Short name T335
Test name
Test status
Simulation time 177276026 ps
CPU time 0.87 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206860 kb
Host smart-5faf8e75-c595-4df9-bdc6-81c025864442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17232
8809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.172328809
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2233648073
Short name T1720
Test name
Test status
Simulation time 173493661 ps
CPU time 0.8 seconds
Started Jul 13 07:14:57 PM PDT 24
Finished Jul 13 07:14:59 PM PDT 24
Peak memory 206824 kb
Host smart-d576e7e8-1054-430b-82fe-e859a1e9a54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22336
48073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2233648073
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2828259232
Short name T367
Test name
Test status
Simulation time 179178510 ps
CPU time 0.85 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:04 PM PDT 24
Peak memory 206876 kb
Host smart-21496083-1b09-4cb4-8403-5ac7d9cd3c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28282
59232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2828259232
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1997803644
Short name T2156
Test name
Test status
Simulation time 193071223 ps
CPU time 0.88 seconds
Started Jul 13 07:15:01 PM PDT 24
Finished Jul 13 07:15:03 PM PDT 24
Peak memory 206880 kb
Host smart-3cc2e022-f7b0-46da-ad6a-68ff9c7d4883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978
03644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1997803644
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1760649024
Short name T1443
Test name
Test status
Simulation time 254359629 ps
CPU time 0.95 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206864 kb
Host smart-eee0ddf4-8842-4efb-b404-e0d84a35bb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
49024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1760649024
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1594745123
Short name T757
Test name
Test status
Simulation time 4825599476 ps
CPU time 135.26 seconds
Started Jul 13 07:14:59 PM PDT 24
Finished Jul 13 07:17:15 PM PDT 24
Peak memory 207080 kb
Host smart-78c30ec0-a6a7-4001-9084-dd1b067e3624
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1594745123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1594745123
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.573784935
Short name T2095
Test name
Test status
Simulation time 220789553 ps
CPU time 0.92 seconds
Started Jul 13 07:14:58 PM PDT 24
Finished Jul 13 07:15:00 PM PDT 24
Peak memory 206832 kb
Host smart-1bf826c1-b4c8-4ea6-8503-7f22dda9e1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57378
4935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.573784935
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2183924646
Short name T2682
Test name
Test status
Simulation time 161680175 ps
CPU time 0.81 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206852 kb
Host smart-f0eb767c-c0c2-496a-8b40-c9cf29a27f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21839
24646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2183924646
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.1063456009
Short name T404
Test name
Test status
Simulation time 618657358 ps
CPU time 1.56 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206868 kb
Host smart-ed58c106-0b79-4292-822f-0f3cf3d6fec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10634
56009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.1063456009
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.2168175004
Short name T1091
Test name
Test status
Simulation time 4204126654 ps
CPU time 115.54 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:16:59 PM PDT 24
Peak memory 207072 kb
Host smart-220c43b9-fe85-41e7-a77d-6035e7262f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21681
75004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2168175004
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.1064289442
Short name T2272
Test name
Test status
Simulation time 46782128 ps
CPU time 0.71 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:18 PM PDT 24
Peak memory 206948 kb
Host smart-5badac71-f1e9-4237-b847-5cf10ee29816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1064289442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1064289442
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3234250770
Short name T1456
Test name
Test status
Simulation time 4087223071 ps
CPU time 5.89 seconds
Started Jul 13 07:14:58 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206896 kb
Host smart-b121079f-2843-4f53-a9ae-54bceb4bd5e8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3234250770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3234250770
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3629618707
Short name T1970
Test name
Test status
Simulation time 13378759687 ps
CPU time 12.13 seconds
Started Jul 13 07:14:56 PM PDT 24
Finished Jul 13 07:15:09 PM PDT 24
Peak memory 207072 kb
Host smart-bf3682db-61f6-44a3-b86a-5fde877dfc9c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3629618707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3629618707
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1191579683
Short name T1489
Test name
Test status
Simulation time 23442621279 ps
CPU time 24.89 seconds
Started Jul 13 07:14:58 PM PDT 24
Finished Jul 13 07:15:24 PM PDT 24
Peak memory 206924 kb
Host smart-db5eb1bb-81e9-4701-9940-34c8b74536b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1191579683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.1191579683
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.329311260
Short name T726
Test name
Test status
Simulation time 187027349 ps
CPU time 0.89 seconds
Started Jul 13 07:15:00 PM PDT 24
Finished Jul 13 07:15:02 PM PDT 24
Peak memory 206856 kb
Host smart-bf2551f5-37ad-41d9-8ffd-0dda49611d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32931
1260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.329311260
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3139560336
Short name T2296
Test name
Test status
Simulation time 146452824 ps
CPU time 0.75 seconds
Started Jul 13 07:15:08 PM PDT 24
Finished Jul 13 07:15:09 PM PDT 24
Peak memory 206856 kb
Host smart-9b6316c4-4b05-4047-878f-4cb730c7bb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31395
60336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3139560336
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3032760037
Short name T1555
Test name
Test status
Simulation time 188071832 ps
CPU time 0.82 seconds
Started Jul 13 07:15:04 PM PDT 24
Finished Jul 13 07:15:06 PM PDT 24
Peak memory 206848 kb
Host smart-b6682178-b11c-49e9-8015-f58a89426475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30327
60037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3032760037
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1149917001
Short name T2463
Test name
Test status
Simulation time 1040294844 ps
CPU time 2.81 seconds
Started Jul 13 07:15:01 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 207012 kb
Host smart-ab43bca4-5b0b-4142-a703-ae1c8f257232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11499
17001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1149917001
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2154159237
Short name T1397
Test name
Test status
Simulation time 9335234669 ps
CPU time 19.85 seconds
Started Jul 13 07:15:08 PM PDT 24
Finished Jul 13 07:15:28 PM PDT 24
Peak memory 207144 kb
Host smart-73163b15-9ff5-4f37-be93-5c8c69f051ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21541
59237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2154159237
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2095934374
Short name T647
Test name
Test status
Simulation time 401261284 ps
CPU time 1.33 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:15:06 PM PDT 24
Peak memory 206880 kb
Host smart-06d6b083-d764-49f8-9484-13c698f07035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
34374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2095934374
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2229208367
Short name T2233
Test name
Test status
Simulation time 137304789 ps
CPU time 0.76 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:04 PM PDT 24
Peak memory 206888 kb
Host smart-ac41b6f8-f3e3-44e2-b725-dc96fbefb3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
08367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2229208367
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2796448492
Short name T217
Test name
Test status
Simulation time 66705626 ps
CPU time 0.78 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206848 kb
Host smart-00ef441c-8807-492a-a456-a93c47f8221a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27964
48492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2796448492
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3005777101
Short name T2144
Test name
Test status
Simulation time 807116531 ps
CPU time 2.07 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:15:07 PM PDT 24
Peak memory 207036 kb
Host smart-c66a2fc0-618b-4cb3-b000-f27de9f46ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
77101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3005777101
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.593811984
Short name T1161
Test name
Test status
Simulation time 274329352 ps
CPU time 2.04 seconds
Started Jul 13 07:15:05 PM PDT 24
Finished Jul 13 07:15:08 PM PDT 24
Peak memory 206996 kb
Host smart-daa23308-1286-4c7b-b591-0f4a9d8f8de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59381
1984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.593811984
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.76786519
Short name T630
Test name
Test status
Simulation time 243772027 ps
CPU time 0.9 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:15:06 PM PDT 24
Peak memory 206864 kb
Host smart-72abae9a-9b7c-4c48-bfe4-aed2368c184d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76786
519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.76786519
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.916462593
Short name T290
Test name
Test status
Simulation time 149196488 ps
CPU time 0.79 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206860 kb
Host smart-afe8665e-18ac-4790-a6d0-a91eed0e4e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91646
2593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.916462593
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.455227596
Short name T572
Test name
Test status
Simulation time 326072469 ps
CPU time 1.1 seconds
Started Jul 13 07:15:04 PM PDT 24
Finished Jul 13 07:15:06 PM PDT 24
Peak memory 206880 kb
Host smart-282cab39-03e4-4582-a98f-569dad23f62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45522
7596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.455227596
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.4070124707
Short name T1683
Test name
Test status
Simulation time 11148624693 ps
CPU time 33.53 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:37 PM PDT 24
Peak memory 207088 kb
Host smart-07ba36f2-55bb-4c46-91f7-60abd58e4173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40701
24707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.4070124707
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.971116225
Short name T2472
Test name
Test status
Simulation time 222826701 ps
CPU time 0.89 seconds
Started Jul 13 07:15:08 PM PDT 24
Finished Jul 13 07:15:10 PM PDT 24
Peak memory 206872 kb
Host smart-3ab10ece-ce62-4e6d-9086-cc642265d1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97111
6225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.971116225
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1834703780
Short name T1380
Test name
Test status
Simulation time 23362569972 ps
CPU time 22.13 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:15:26 PM PDT 24
Peak memory 206928 kb
Host smart-73c19812-8df2-4d5e-ab1c-ac71b18b989a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18347
03780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1834703780
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.302169522
Short name T2082
Test name
Test status
Simulation time 3261165375 ps
CPU time 3.96 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:15:08 PM PDT 24
Peak memory 206932 kb
Host smart-2e2c2758-65df-4699-932f-33d1f9f3bf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
9522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.302169522
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.1625296022
Short name T2621
Test name
Test status
Simulation time 9548611284 ps
CPU time 264.68 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:19:28 PM PDT 24
Peak memory 207136 kb
Host smart-02cd11a3-b3cf-4de2-bf78-ff15becd70f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
96022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.1625296022
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.4027311305
Short name T474
Test name
Test status
Simulation time 7601370481 ps
CPU time 211.85 seconds
Started Jul 13 07:15:08 PM PDT 24
Finished Jul 13 07:18:41 PM PDT 24
Peak memory 207088 kb
Host smart-e89e5fec-ead4-4ac7-84a7-0777ee172a69
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4027311305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.4027311305
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1395595254
Short name T1619
Test name
Test status
Simulation time 235654771 ps
CPU time 0.97 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206848 kb
Host smart-4dd5561c-2aef-40d6-8c69-8e9aeb7b1970
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1395595254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1395595254
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.4283840629
Short name T2109
Test name
Test status
Simulation time 190474876 ps
CPU time 0.86 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206884 kb
Host smart-0943815d-d74c-491f-a936-7bcb03a05a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42838
40629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.4283840629
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.4188652121
Short name T1104
Test name
Test status
Simulation time 4707947278 ps
CPU time 44.8 seconds
Started Jul 13 07:15:04 PM PDT 24
Finished Jul 13 07:15:50 PM PDT 24
Peak memory 207136 kb
Host smart-9df5435a-6060-476d-81fc-4db8859ad2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
52121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.4188652121
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3952415052
Short name T490
Test name
Test status
Simulation time 5252833070 ps
CPU time 150.64 seconds
Started Jul 13 07:15:03 PM PDT 24
Finished Jul 13 07:17:36 PM PDT 24
Peak memory 207084 kb
Host smart-69c1b5a0-6fa1-4e15-99e2-36c4cb2509d0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3952415052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3952415052
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.765931568
Short name T375
Test name
Test status
Simulation time 153352317 ps
CPU time 0.79 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206808 kb
Host smart-311d30f2-2aa2-4f13-992c-7cde31fac40f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=765931568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.765931568
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.898292992
Short name T898
Test name
Test status
Simulation time 158224635 ps
CPU time 0.79 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206860 kb
Host smart-485ddd25-a3e2-4b95-8575-592e69c4651b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89829
2992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.898292992
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1715235225
Short name T2633
Test name
Test status
Simulation time 209428734 ps
CPU time 0.88 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:05 PM PDT 24
Peak memory 206808 kb
Host smart-5d13e6bd-06da-4baa-9ac8-bc901ec54fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17152
35225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1715235225
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.794790603
Short name T1662
Test name
Test status
Simulation time 182297891 ps
CPU time 0.89 seconds
Started Jul 13 07:15:09 PM PDT 24
Finished Jul 13 07:15:10 PM PDT 24
Peak memory 206856 kb
Host smart-83f89852-80c4-4d16-a371-acd1e0ad8420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79479
0603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.794790603
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.19631285
Short name T418
Test name
Test status
Simulation time 165810519 ps
CPU time 0.81 seconds
Started Jul 13 07:15:04 PM PDT 24
Finished Jul 13 07:15:06 PM PDT 24
Peak memory 206868 kb
Host smart-1c6b3a2c-95a3-4433-b972-23634fb6dac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19631
285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.19631285
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.157168928
Short name T592
Test name
Test status
Simulation time 160328888 ps
CPU time 0.8 seconds
Started Jul 13 07:15:08 PM PDT 24
Finished Jul 13 07:15:10 PM PDT 24
Peak memory 206812 kb
Host smart-baf74814-ddb1-4c38-8b27-aa43433964a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15716
8928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.157168928
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.917924079
Short name T2664
Test name
Test status
Simulation time 149922372 ps
CPU time 0.87 seconds
Started Jul 13 07:15:02 PM PDT 24
Finished Jul 13 07:15:04 PM PDT 24
Peak memory 206872 kb
Host smart-5585c180-b888-4140-993c-f4201e797cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91792
4079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.917924079
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1123519806
Short name T1266
Test name
Test status
Simulation time 230870716 ps
CPU time 0.88 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 206868 kb
Host smart-d24fcc80-117f-475a-9f3a-3e4c29c04a06
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1123519806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1123519806
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.215974759
Short name T1980
Test name
Test status
Simulation time 141868658 ps
CPU time 0.74 seconds
Started Jul 13 07:15:17 PM PDT 24
Finished Jul 13 07:15:19 PM PDT 24
Peak memory 206888 kb
Host smart-05500365-40d2-4dcb-846b-890aa9e403af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
4759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.215974759
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.496243213
Short name T1037
Test name
Test status
Simulation time 62994661 ps
CPU time 0.71 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:15 PM PDT 24
Peak memory 206868 kb
Host smart-df8f1471-104e-4243-8004-c01e1ea02e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49624
3213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.496243213
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.533927027
Short name T1060
Test name
Test status
Simulation time 14602145720 ps
CPU time 31.79 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:15:48 PM PDT 24
Peak memory 207152 kb
Host smart-59cb8a0f-6caf-4518-8e3c-9872eb4eb43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53392
7027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.533927027
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.668120422
Short name T912
Test name
Test status
Simulation time 175587606 ps
CPU time 0.81 seconds
Started Jul 13 07:15:12 PM PDT 24
Finished Jul 13 07:15:13 PM PDT 24
Peak memory 206884 kb
Host smart-2704a1ac-4948-4060-8129-b4b372c1767a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66812
0422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.668120422
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1927108194
Short name T598
Test name
Test status
Simulation time 162013614 ps
CPU time 0.84 seconds
Started Jul 13 07:15:11 PM PDT 24
Finished Jul 13 07:15:12 PM PDT 24
Peak memory 206864 kb
Host smart-3c5f9ef5-6d3f-4799-8f98-7c88890020bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19271
08194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1927108194
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.4187170201
Short name T1617
Test name
Test status
Simulation time 254386312 ps
CPU time 0.94 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 206880 kb
Host smart-c345dc17-ab11-4b3e-9c64-f2cf43c6004d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41871
70201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.4187170201
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2126501725
Short name T685
Test name
Test status
Simulation time 191273675 ps
CPU time 0.89 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 206864 kb
Host smart-4af92e60-a40a-431c-b750-2ec20a50bac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21265
01725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2126501725
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3079428714
Short name T921
Test name
Test status
Simulation time 139353666 ps
CPU time 0.73 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:16 PM PDT 24
Peak memory 206872 kb
Host smart-cb54e3a4-c31a-427e-b00d-09d891f3135c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30794
28714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3079428714
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.274048177
Short name T953
Test name
Test status
Simulation time 158580032 ps
CPU time 0.81 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 206856 kb
Host smart-3cd6f01f-e439-495f-b150-13b4471c17d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27404
8177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.274048177
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1336044059
Short name T1999
Test name
Test status
Simulation time 164253935 ps
CPU time 0.82 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:15 PM PDT 24
Peak memory 206756 kb
Host smart-0e7209da-9bdc-4b5a-974b-f656d513a79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13360
44059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1336044059
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1504590153
Short name T1916
Test name
Test status
Simulation time 232786307 ps
CPU time 0.96 seconds
Started Jul 13 07:15:10 PM PDT 24
Finished Jul 13 07:15:11 PM PDT 24
Peak memory 206844 kb
Host smart-084f1461-e3e1-4d70-bc38-aa47c1ba8f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15045
90153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1504590153
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.4103704706
Short name T2743
Test name
Test status
Simulation time 4630735655 ps
CPU time 141.3 seconds
Started Jul 13 07:15:11 PM PDT 24
Finished Jul 13 07:17:33 PM PDT 24
Peak memory 207032 kb
Host smart-ce9f2339-82b6-44dc-85ed-a4b78932951b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4103704706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.4103704706
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.4144866098
Short name T1593
Test name
Test status
Simulation time 197829977 ps
CPU time 0.82 seconds
Started Jul 13 07:15:17 PM PDT 24
Finished Jul 13 07:15:19 PM PDT 24
Peak memory 206892 kb
Host smart-ddd25bee-95e8-4ec4-a3ce-72328cc3f281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41448
66098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.4144866098
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2471526717
Short name T2411
Test name
Test status
Simulation time 189197851 ps
CPU time 0.87 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:16 PM PDT 24
Peak memory 206876 kb
Host smart-4c662c3e-5df3-4b34-ac7e-045b9aaac73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24715
26717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2471526717
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2733759056
Short name T1012
Test name
Test status
Simulation time 1406361344 ps
CPU time 3.18 seconds
Started Jul 13 07:15:12 PM PDT 24
Finished Jul 13 07:15:16 PM PDT 24
Peak memory 207056 kb
Host smart-ae3668a0-25ef-4af2-b21c-8e387f73323f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27337
59056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2733759056
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1326947143
Short name T2608
Test name
Test status
Simulation time 6958587507 ps
CPU time 52.09 seconds
Started Jul 13 07:15:12 PM PDT 24
Finished Jul 13 07:16:04 PM PDT 24
Peak memory 207136 kb
Host smart-52f93588-2b20-4e6f-974e-1ce6ca27e1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13269
47143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1326947143
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2970343233
Short name T672
Test name
Test status
Simulation time 41035604 ps
CPU time 0.7 seconds
Started Jul 13 07:15:20 PM PDT 24
Finished Jul 13 07:15:21 PM PDT 24
Peak memory 206948 kb
Host smart-19c1df0e-da4b-4acd-9261-10a67c4b6805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2970343233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2970343233
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2401217924
Short name T2306
Test name
Test status
Simulation time 13325700852 ps
CPU time 12.58 seconds
Started Jul 13 07:15:17 PM PDT 24
Finished Jul 13 07:15:31 PM PDT 24
Peak memory 207100 kb
Host smart-b4dd3722-4d65-4b12-ae58-53687d3a57f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2401217924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2401217924
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3907691018
Short name T876
Test name
Test status
Simulation time 23338284225 ps
CPU time 21.42 seconds
Started Jul 13 07:15:12 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 207136 kb
Host smart-2e051fc2-3b82-40e1-9a77-c5e525c4bfc3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3907691018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3907691018
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2223478656
Short name T2473
Test name
Test status
Simulation time 235772645 ps
CPU time 0.96 seconds
Started Jul 13 07:15:12 PM PDT 24
Finished Jul 13 07:15:14 PM PDT 24
Peak memory 207100 kb
Host smart-ea379c89-1b1e-493f-8f75-1c813db23783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22234
78656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2223478656
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1214554412
Short name T1
Test name
Test status
Simulation time 143803240 ps
CPU time 0.79 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:14 PM PDT 24
Peak memory 206856 kb
Host smart-eeefc841-9e93-49bd-a522-b6c2e283c130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12145
54412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1214554412
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.982766956
Short name T1821
Test name
Test status
Simulation time 439646222 ps
CPU time 1.47 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:15 PM PDT 24
Peak memory 206760 kb
Host smart-7bbfe6e2-375c-412e-840d-71bc221a3173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98276
6956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.982766956
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.520038543
Short name T470
Test name
Test status
Simulation time 904718373 ps
CPU time 2.13 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:19 PM PDT 24
Peak memory 207012 kb
Host smart-ea78f5fb-84ab-4739-a4c4-cbe82d3c949a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52003
8543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.520038543
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3298371323
Short name T2168
Test name
Test status
Simulation time 20831879562 ps
CPU time 38.91 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:56 PM PDT 24
Peak memory 207084 kb
Host smart-63690a27-4cbe-4e68-af66-dd24648703ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32983
71323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3298371323
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.630230272
Short name T2119
Test name
Test status
Simulation time 416992166 ps
CPU time 1.2 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:15 PM PDT 24
Peak memory 206864 kb
Host smart-797fa48d-6783-433c-a67d-5d046254cb5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63023
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.630230272
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.966174231
Short name T2568
Test name
Test status
Simulation time 151178854 ps
CPU time 0.82 seconds
Started Jul 13 07:15:12 PM PDT 24
Finished Jul 13 07:15:14 PM PDT 24
Peak memory 206868 kb
Host smart-0cb62008-9a72-493c-92f4-16e3c7c50341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96617
4231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.966174231
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.491076804
Short name T1787
Test name
Test status
Simulation time 68058684 ps
CPU time 0.72 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:18 PM PDT 24
Peak memory 206860 kb
Host smart-f4f531aa-c037-4ca3-9aac-006b79cff6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49107
6804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.491076804
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.441409764
Short name T1552
Test name
Test status
Simulation time 827763688 ps
CPU time 2.08 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 207076 kb
Host smart-195b0b76-6c75-44c4-8c9c-caa6030d3170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44140
9764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.441409764
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2767469247
Short name T733
Test name
Test status
Simulation time 237270227 ps
CPU time 1.28 seconds
Started Jul 13 07:15:11 PM PDT 24
Finished Jul 13 07:15:12 PM PDT 24
Peak memory 207016 kb
Host smart-58008406-09ab-48d8-9516-04bdc5e4bc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27674
69247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2767469247
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2720207486
Short name T1524
Test name
Test status
Simulation time 228723657 ps
CPU time 0.95 seconds
Started Jul 13 07:15:12 PM PDT 24
Finished Jul 13 07:15:14 PM PDT 24
Peak memory 206884 kb
Host smart-c1b2dd8c-7744-4bbc-a505-98a3e18aaf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
07486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2720207486
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.599997303
Short name T1029
Test name
Test status
Simulation time 139004834 ps
CPU time 0.76 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:15 PM PDT 24
Peak memory 206836 kb
Host smart-d151aacc-8167-4d86-b8ac-e0c4d5c76cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59999
7303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.599997303
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3265874008
Short name T1981
Test name
Test status
Simulation time 251402183 ps
CPU time 1.01 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:18 PM PDT 24
Peak memory 206884 kb
Host smart-2f5d228f-bc91-45bb-b66c-f01ffecbb6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32658
74008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3265874008
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.1180655963
Short name T2406
Test name
Test status
Simulation time 6337938229 ps
CPU time 56.3 seconds
Started Jul 13 07:15:17 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 207156 kb
Host smart-d358939f-917c-407c-9e2b-91a09aee9c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11806
55963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.1180655963
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1154147901
Short name T800
Test name
Test status
Simulation time 217821658 ps
CPU time 0.88 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:15 PM PDT 24
Peak memory 206860 kb
Host smart-caa43af2-f0e9-4455-82e0-e64637205ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11541
47901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1154147901
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1184272011
Short name T860
Test name
Test status
Simulation time 23269699493 ps
CPU time 28.94 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:15:45 PM PDT 24
Peak memory 206928 kb
Host smart-25a440cb-7c62-4a10-9143-97476c484ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11842
72011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1184272011
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1726893298
Short name T2211
Test name
Test status
Simulation time 3335743478 ps
CPU time 3.69 seconds
Started Jul 13 07:15:13 PM PDT 24
Finished Jul 13 07:15:19 PM PDT 24
Peak memory 206940 kb
Host smart-012ecd7b-af9f-44ef-9135-64a9eb53de10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17268
93298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1726893298
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1130969594
Short name T2293
Test name
Test status
Simulation time 11346554647 ps
CPU time 312.57 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:20:29 PM PDT 24
Peak memory 207160 kb
Host smart-7c8a4a3b-509d-43b2-9492-9cf94e9f8755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11309
69594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1130969594
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2797514115
Short name T2318
Test name
Test status
Simulation time 5740812419 ps
CPU time 162.58 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:17:59 PM PDT 24
Peak memory 207060 kb
Host smart-5fd4eaa3-07e4-47ea-bd25-2bb82d7bebc8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2797514115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2797514115
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1364516846
Short name T408
Test name
Test status
Simulation time 246997925 ps
CPU time 0.96 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:18 PM PDT 24
Peak memory 206860 kb
Host smart-bba07057-beb1-49f5-a032-c7d219596e19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1364516846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1364516846
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3354173282
Short name T2500
Test name
Test status
Simulation time 188975307 ps
CPU time 0.85 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 206852 kb
Host smart-7b860151-3352-41ce-a42b-afde8f0cc582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33541
73282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3354173282
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.902894645
Short name T652
Test name
Test status
Simulation time 3397230782 ps
CPU time 33.23 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:50 PM PDT 24
Peak memory 207136 kb
Host smart-07284e0d-be94-4156-8890-ba86865cdabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90289
4645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.902894645
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2242909226
Short name T2660
Test name
Test status
Simulation time 3028183183 ps
CPU time 86.52 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 207044 kb
Host smart-2a9d1b5f-41f4-40fc-b79b-83ce022f8a65
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2242909226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2242909226
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3197612213
Short name T2044
Test name
Test status
Simulation time 182002488 ps
CPU time 0.84 seconds
Started Jul 13 07:15:15 PM PDT 24
Finished Jul 13 07:15:18 PM PDT 24
Peak memory 206884 kb
Host smart-1f2913ac-f50b-4c2b-ad54-0b419eced59a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3197612213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3197612213
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3823160943
Short name T2689
Test name
Test status
Simulation time 149041968 ps
CPU time 0.8 seconds
Started Jul 13 07:15:12 PM PDT 24
Finished Jul 13 07:15:14 PM PDT 24
Peak memory 206864 kb
Host smart-3eb53a77-c751-4e13-aa28-dafa4e37383f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38231
60943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3823160943
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.590339327
Short name T111
Test name
Test status
Simulation time 229249435 ps
CPU time 0.88 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 206872 kb
Host smart-3add81d4-7224-410f-a7a2-cff4b3439a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59033
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.590339327
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3218087629
Short name T1286
Test name
Test status
Simulation time 206449867 ps
CPU time 0.87 seconds
Started Jul 13 07:15:16 PM PDT 24
Finished Jul 13 07:15:19 PM PDT 24
Peak memory 206888 kb
Host smart-ebbb43ea-8d5e-427e-8ba7-705a58b21907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32180
87629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3218087629
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3449603168
Short name T1047
Test name
Test status
Simulation time 179823453 ps
CPU time 0.82 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 206868 kb
Host smart-ebdb7de9-b4b6-4abf-ae36-b413478feac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34496
03168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3449603168
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1581860036
Short name T2205
Test name
Test status
Simulation time 152334317 ps
CPU time 0.79 seconds
Started Jul 13 07:15:14 PM PDT 24
Finished Jul 13 07:15:17 PM PDT 24
Peak memory 206888 kb
Host smart-bed8479d-d638-4a92-93b7-f95aeba18789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15818
60036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1581860036
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.656054933
Short name T1951
Test name
Test status
Simulation time 151407937 ps
CPU time 0.8 seconds
Started Jul 13 07:15:20 PM PDT 24
Finished Jul 13 07:15:21 PM PDT 24
Peak memory 206900 kb
Host smart-a2d4f3e7-73db-4171-9cb2-61b04d23f591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65605
4933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.656054933
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2366863131
Short name T942
Test name
Test status
Simulation time 238637597 ps
CPU time 0.94 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 206832 kb
Host smart-44757f5b-4465-4969-92df-e4e7e4e8c801
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2366863131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2366863131
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3912943807
Short name T2070
Test name
Test status
Simulation time 164621906 ps
CPU time 0.83 seconds
Started Jul 13 07:15:21 PM PDT 24
Finished Jul 13 07:15:23 PM PDT 24
Peak memory 206860 kb
Host smart-e128e5c2-b1c3-4b17-8ec8-a348665db7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39129
43807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3912943807
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2828650940
Short name T1009
Test name
Test status
Simulation time 50079402 ps
CPU time 0.68 seconds
Started Jul 13 07:15:23 PM PDT 24
Finished Jul 13 07:15:24 PM PDT 24
Peak memory 206852 kb
Host smart-d377f3b6-508a-4837-978c-6bc9c8a8c9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28286
50940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2828650940
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.792267431
Short name T1089
Test name
Test status
Simulation time 9076776046 ps
CPU time 20 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:53 PM PDT 24
Peak memory 207104 kb
Host smart-537abbef-8f6c-492f-8623-e206f263cf2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79226
7431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.792267431
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4257689856
Short name T1450
Test name
Test status
Simulation time 186544856 ps
CPU time 0.85 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 206860 kb
Host smart-aa70b918-5fc0-4032-87a8-a17fd1d67fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42576
89856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4257689856
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.615722167
Short name T514
Test name
Test status
Simulation time 212229557 ps
CPU time 0.9 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206852 kb
Host smart-11df3f89-d447-492e-8209-a9be9f337536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61572
2167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.615722167
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2996720534
Short name T1328
Test name
Test status
Simulation time 240891518 ps
CPU time 0.91 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206828 kb
Host smart-81010fde-8ece-4ad3-ac65-3f21601628a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29967
20534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2996720534
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.469586545
Short name T997
Test name
Test status
Simulation time 170861281 ps
CPU time 0.81 seconds
Started Jul 13 07:15:27 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206856 kb
Host smart-eff3ebc3-ac69-451c-88a9-b297b5354839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46958
6545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.469586545
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.1243850702
Short name T72
Test name
Test status
Simulation time 147907272 ps
CPU time 0.77 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:32 PM PDT 24
Peak memory 206892 kb
Host smart-1058f8fb-a84d-4509-a23c-fcb89f0889dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
50702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1243850702
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1394842119
Short name T849
Test name
Test status
Simulation time 158528993 ps
CPU time 0.81 seconds
Started Jul 13 07:15:22 PM PDT 24
Finished Jul 13 07:15:24 PM PDT 24
Peak memory 206880 kb
Host smart-7bd12f8b-5794-43c1-940b-172efd7c30c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13948
42119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1394842119
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2873951546
Short name T527
Test name
Test status
Simulation time 146302141 ps
CPU time 0.81 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206868 kb
Host smart-b4d498e9-cf86-4754-8550-19dcfedcddd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28739
51546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2873951546
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1594069388
Short name T2127
Test name
Test status
Simulation time 272903613 ps
CPU time 1.01 seconds
Started Jul 13 07:15:19 PM PDT 24
Finished Jul 13 07:15:21 PM PDT 24
Peak memory 206872 kb
Host smart-d1c3d794-6ff5-47e8-b9ac-59643953fa9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15940
69388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1594069388
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3372922748
Short name T2733
Test name
Test status
Simulation time 6132710973 ps
CPU time 42.91 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 207212 kb
Host smart-5325b115-71cf-4690-8972-39bb4efa79a5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3372922748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3372922748
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2266483138
Short name T1190
Test name
Test status
Simulation time 188666425 ps
CPU time 0.78 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206884 kb
Host smart-0b9438b3-f62f-441e-bc11-c2b33b19feab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22664
83138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2266483138
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.416026138
Short name T533
Test name
Test status
Simulation time 167641493 ps
CPU time 0.88 seconds
Started Jul 13 07:15:22 PM PDT 24
Finished Jul 13 07:15:24 PM PDT 24
Peak memory 206884 kb
Host smart-f2161a70-fcd0-44c5-89cb-23758b6ba827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41602
6138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.416026138
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.232820296
Short name T2631
Test name
Test status
Simulation time 375088719 ps
CPU time 1.15 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206832 kb
Host smart-fd113744-30e0-4631-a685-20790da8a779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
0296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.232820296
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3342038190
Short name T659
Test name
Test status
Simulation time 5415208208 ps
CPU time 147.71 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:18:00 PM PDT 24
Peak memory 207096 kb
Host smart-ebf59506-7763-429a-9b0c-9db0cd22143a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33420
38190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3342038190
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.181533424
Short name T1341
Test name
Test status
Simulation time 63248682 ps
CPU time 0.67 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206888 kb
Host smart-8a2de4ff-4b36-4d43-a8e6-12288e1aff72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=181533424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.181533424
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.4279650839
Short name T1282
Test name
Test status
Simulation time 3452065251 ps
CPU time 4.32 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:38 PM PDT 24
Peak memory 206872 kb
Host smart-19d07b36-a9a9-49bc-9365-4d32ebffeab3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4279650839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.4279650839
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2916791370
Short name T1742
Test name
Test status
Simulation time 13357531714 ps
CPU time 12.24 seconds
Started Jul 13 07:15:32 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 207096 kb
Host smart-a8152b59-60ad-4ca4-8bab-37b7bd77ade8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2916791370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2916791370
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1296091275
Short name T702
Test name
Test status
Simulation time 23439837497 ps
CPU time 23.79 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:52 PM PDT 24
Peak memory 207080 kb
Host smart-b1001e88-52dd-48a6-8b51-7569b2bacfa0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1296091275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.1296091275
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2835888555
Short name T2005
Test name
Test status
Simulation time 184588543 ps
CPU time 0.87 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:32 PM PDT 24
Peak memory 206848 kb
Host smart-72cec2a5-b707-464f-a69a-c23652e9d8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28358
88555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2835888555
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3423250609
Short name T1995
Test name
Test status
Simulation time 150776448 ps
CPU time 0.81 seconds
Started Jul 13 07:15:27 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206868 kb
Host smart-a7b651d4-ecda-462d-8d63-73cbca65be78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34232
50609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3423250609
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3255486830
Short name T1573
Test name
Test status
Simulation time 503185980 ps
CPU time 1.6 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 207308 kb
Host smart-63fdd5ff-842f-482d-a5fa-7bb6fbcf8cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32554
86830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3255486830
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1909326776
Short name T1133
Test name
Test status
Simulation time 1010907567 ps
CPU time 2.46 seconds
Started Jul 13 07:15:27 PM PDT 24
Finished Jul 13 07:15:32 PM PDT 24
Peak memory 206996 kb
Host smart-97a8e472-f346-44e4-b365-dd0cf3f0b828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19093
26776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1909326776
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1023904455
Short name T2335
Test name
Test status
Simulation time 13019003160 ps
CPU time 23.82 seconds
Started Jul 13 07:15:22 PM PDT 24
Finished Jul 13 07:15:46 PM PDT 24
Peak memory 207024 kb
Host smart-762ddc44-a76d-4c96-9759-2d7dd3a6c7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10239
04455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1023904455
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.143966016
Short name T1362
Test name
Test status
Simulation time 544690629 ps
CPU time 1.5 seconds
Started Jul 13 07:15:23 PM PDT 24
Finished Jul 13 07:15:25 PM PDT 24
Peak memory 206868 kb
Host smart-628262ce-008b-4a0e-b807-5104b7b2befb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14396
6016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.143966016
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3775905754
Short name T2361
Test name
Test status
Simulation time 167736408 ps
CPU time 0.79 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:34 PM PDT 24
Peak memory 206868 kb
Host smart-58880750-94bf-42d5-9b9e-028427b0a33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37759
05754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3775905754
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3078078742
Short name T1262
Test name
Test status
Simulation time 35270128 ps
CPU time 0.66 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:32 PM PDT 24
Peak memory 206856 kb
Host smart-47d7b41d-f1f9-4b12-ab2c-7e62ec020f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30780
78742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3078078742
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.815954473
Short name T1816
Test name
Test status
Simulation time 793187874 ps
CPU time 2.17 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:34 PM PDT 24
Peak memory 207020 kb
Host smart-8205a8f3-a5df-452b-ba33-1deb4b14c8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81595
4473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.815954473
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1031538438
Short name T1434
Test name
Test status
Simulation time 304704036 ps
CPU time 2 seconds
Started Jul 13 07:15:19 PM PDT 24
Finished Jul 13 07:15:21 PM PDT 24
Peak memory 207060 kb
Host smart-94edf8f6-944c-4d43-bbb4-6dae267014c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315
38438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1031538438
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1615315810
Short name T1309
Test name
Test status
Simulation time 170489680 ps
CPU time 0.84 seconds
Started Jul 13 07:15:24 PM PDT 24
Finished Jul 13 07:15:26 PM PDT 24
Peak memory 206852 kb
Host smart-f8dfa88c-dfd3-4dd6-8304-cbe6e10dcd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16153
15810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1615315810
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2120516441
Short name T1730
Test name
Test status
Simulation time 157557860 ps
CPU time 0.75 seconds
Started Jul 13 07:15:24 PM PDT 24
Finished Jul 13 07:15:25 PM PDT 24
Peak memory 206808 kb
Host smart-f01f47a5-b1ae-4535-a1c0-f8d2cd1de9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21205
16441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2120516441
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2123887740
Short name T986
Test name
Test status
Simulation time 204312185 ps
CPU time 0.85 seconds
Started Jul 13 07:15:20 PM PDT 24
Finished Jul 13 07:15:21 PM PDT 24
Peak memory 206820 kb
Host smart-e18e2776-3b13-4254-99bc-2ef7139bc40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21238
87740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2123887740
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.2549274394
Short name T96
Test name
Test status
Simulation time 7810038309 ps
CPU time 221.67 seconds
Started Jul 13 07:15:24 PM PDT 24
Finished Jul 13 07:19:07 PM PDT 24
Peak memory 207096 kb
Host smart-a719f2db-49cc-4a08-8e7f-19950a7a06f8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2549274394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.2549274394
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.665950748
Short name T2565
Test name
Test status
Simulation time 13756327304 ps
CPU time 43.66 seconds
Started Jul 13 07:15:24 PM PDT 24
Finished Jul 13 07:16:09 PM PDT 24
Peak memory 207152 kb
Host smart-b0aff31f-7f20-4549-b973-fdaae175bef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66595
0748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.665950748
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.3066054623
Short name T1166
Test name
Test status
Simulation time 193913021 ps
CPU time 0.89 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206860 kb
Host smart-2decbe8d-69b2-4572-ab90-c630397a8a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30660
54623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3066054623
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1305418777
Short name T2089
Test name
Test status
Simulation time 23335555188 ps
CPU time 25.74 seconds
Started Jul 13 07:15:21 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 206928 kb
Host smart-6401dc69-cb43-41d4-a04f-392fe945c1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13054
18777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1305418777
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1617458318
Short name T314
Test name
Test status
Simulation time 3321245119 ps
CPU time 3.43 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206944 kb
Host smart-b3a67788-0fbc-476a-bc89-bd2cd93baef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16174
58318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1617458318
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2320904844
Short name T1688
Test name
Test status
Simulation time 11689718043 ps
CPU time 86.26 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:16:58 PM PDT 24
Peak memory 207176 kb
Host smart-bb855565-15f3-4bfb-8875-7036acb4d622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23209
04844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2320904844
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1077671619
Short name T357
Test name
Test status
Simulation time 4585057230 ps
CPU time 128.77 seconds
Started Jul 13 07:15:22 PM PDT 24
Finished Jul 13 07:17:32 PM PDT 24
Peak memory 207096 kb
Host smart-1e77150a-6d0a-44f0-9a04-32d70b4ec4a1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1077671619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1077671619
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1910120755
Short name T2513
Test name
Test status
Simulation time 232064113 ps
CPU time 0.87 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206868 kb
Host smart-ae1039bd-b7b2-484d-8b88-139e5684e11f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1910120755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1910120755
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.4257564539
Short name T650
Test name
Test status
Simulation time 206221828 ps
CPU time 0.9 seconds
Started Jul 13 07:15:23 PM PDT 24
Finished Jul 13 07:15:24 PM PDT 24
Peak memory 206864 kb
Host smart-551bd370-055a-4ff5-a3da-3a43b4428d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42575
64539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.4257564539
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1584783264
Short name T322
Test name
Test status
Simulation time 4835037538 ps
CPU time 132.03 seconds
Started Jul 13 07:15:24 PM PDT 24
Finished Jul 13 07:17:36 PM PDT 24
Peak memory 207064 kb
Host smart-31f05a01-a226-455f-bca5-5146474bd576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15847
83264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1584783264
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3292254122
Short name T2115
Test name
Test status
Simulation time 4065873005 ps
CPU time 113.37 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:17:25 PM PDT 24
Peak memory 207084 kb
Host smart-bdc98dc3-1b90-4d68-978c-3de20180da94
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3292254122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3292254122
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3723671212
Short name T882
Test name
Test status
Simulation time 155951724 ps
CPU time 0.81 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:31 PM PDT 24
Peak memory 206844 kb
Host smart-ac69f35e-6b8f-4442-837f-8365412819ca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3723671212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3723671212
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2274972640
Short name T1410
Test name
Test status
Simulation time 147607845 ps
CPU time 0.76 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:34 PM PDT 24
Peak memory 206804 kb
Host smart-d9907498-71d1-455e-ac28-a0d5285dabf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
72640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2274972640
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.387739244
Short name T2056
Test name
Test status
Simulation time 274148516 ps
CPU time 0.87 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206872 kb
Host smart-be68b0b4-2d07-4290-bdca-4a6a43e23e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38773
9244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.387739244
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3714445506
Short name T1329
Test name
Test status
Simulation time 164599154 ps
CPU time 0.85 seconds
Started Jul 13 07:15:25 PM PDT 24
Finished Jul 13 07:15:26 PM PDT 24
Peak memory 206812 kb
Host smart-f1667916-239a-4912-94e0-1092a221f3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37144
45506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3714445506
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3361126261
Short name T811
Test name
Test status
Simulation time 225633983 ps
CPU time 0.9 seconds
Started Jul 13 07:15:24 PM PDT 24
Finished Jul 13 07:15:26 PM PDT 24
Peak memory 206868 kb
Host smart-2bd560da-3a2c-4d4e-922b-60ee4f81a55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33611
26261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3361126261
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2796749644
Short name T2697
Test name
Test status
Simulation time 184170588 ps
CPU time 0.8 seconds
Started Jul 13 07:15:22 PM PDT 24
Finished Jul 13 07:15:24 PM PDT 24
Peak memory 206872 kb
Host smart-6a57d8eb-777e-4567-8e85-96faa93dfd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27967
49644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2796749644
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1789478598
Short name T1983
Test name
Test status
Simulation time 169653530 ps
CPU time 0.83 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 206808 kb
Host smart-92d5c3a2-0598-4f19-80c9-b6f293319d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17894
78598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1789478598
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3763583767
Short name T1848
Test name
Test status
Simulation time 251476298 ps
CPU time 1.06 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 206868 kb
Host smart-1b23884c-2709-4851-8dd4-a4d93316c38b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3763583767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3763583767
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2007977204
Short name T19
Test name
Test status
Simulation time 136040327 ps
CPU time 0.78 seconds
Started Jul 13 07:15:27 PM PDT 24
Finished Jul 13 07:15:30 PM PDT 24
Peak memory 206848 kb
Host smart-c0209f87-cecb-4545-ae4f-ccb176d5f13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20079
77204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2007977204
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.986282288
Short name T1870
Test name
Test status
Simulation time 52906576 ps
CPU time 0.7 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206860 kb
Host smart-69a91a75-8d74-44ca-8f73-a3aacd520117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98628
2288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.986282288
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3085857931
Short name T90
Test name
Test status
Simulation time 12999024374 ps
CPU time 28.56 seconds
Started Jul 13 07:15:24 PM PDT 24
Finished Jul 13 07:15:54 PM PDT 24
Peak memory 207096 kb
Host smart-4fb0635c-152f-4d39-9211-0dbcf662a0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30858
57931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3085857931
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2319422016
Short name T2386
Test name
Test status
Simulation time 147007572 ps
CPU time 0.79 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206868 kb
Host smart-a983f3f0-a6a8-4cec-9d7a-d39811278843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23194
22016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2319422016
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3953096234
Short name T1824
Test name
Test status
Simulation time 283509620 ps
CPU time 0.95 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206844 kb
Host smart-295bbc9e-e7f3-40a2-8507-85cdcfd463f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39530
96234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3953096234
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1674735708
Short name T2246
Test name
Test status
Simulation time 278577302 ps
CPU time 1.06 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206872 kb
Host smart-4d5993bb-0064-4856-8328-1da60efb76bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16747
35708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1674735708
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.4056748412
Short name T419
Test name
Test status
Simulation time 175694211 ps
CPU time 0.87 seconds
Started Jul 13 07:15:21 PM PDT 24
Finished Jul 13 07:15:22 PM PDT 24
Peak memory 206868 kb
Host smart-0995329d-8d5b-4e57-810b-11daeeaa8b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40567
48412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.4056748412
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3625000435
Short name T1851
Test name
Test status
Simulation time 181598444 ps
CPU time 0.8 seconds
Started Jul 13 07:15:25 PM PDT 24
Finished Jul 13 07:15:26 PM PDT 24
Peak memory 206860 kb
Host smart-525cfad1-10d4-40b8-8a84-798d96a6c79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36250
00435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3625000435
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.602060842
Short name T785
Test name
Test status
Simulation time 174660353 ps
CPU time 0.78 seconds
Started Jul 13 07:15:40 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 207048 kb
Host smart-a112d1f3-073b-44cf-a718-839f0d8136d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60206
0842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.602060842
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2192421044
Short name T697
Test name
Test status
Simulation time 152992336 ps
CPU time 0.83 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 207048 kb
Host smart-ffcad122-affd-47e2-bce7-4519fdaa1084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21924
21044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2192421044
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1563845133
Short name T1169
Test name
Test status
Simulation time 217701570 ps
CPU time 0.98 seconds
Started Jul 13 07:15:27 PM PDT 24
Finished Jul 13 07:15:30 PM PDT 24
Peak memory 206844 kb
Host smart-1c4abc61-6fa5-451b-84e0-ec21de4a3c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15638
45133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1563845133
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.1322510540
Short name T1678
Test name
Test status
Simulation time 5293972659 ps
CPU time 145.86 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:17:54 PM PDT 24
Peak memory 207080 kb
Host smart-67e77481-83d7-4956-aeb9-e54894541535
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1322510540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.1322510540
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2362973399
Short name T1587
Test name
Test status
Simulation time 167380005 ps
CPU time 0.78 seconds
Started Jul 13 07:15:27 PM PDT 24
Finished Jul 13 07:15:30 PM PDT 24
Peak memory 206904 kb
Host smart-a244c5d0-faf1-4896-8656-668feff131fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23629
73399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2362973399
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1451671931
Short name T194
Test name
Test status
Simulation time 221324212 ps
CPU time 0.87 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 206804 kb
Host smart-08e6fb13-b4a8-4d66-a303-65e477b5feff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14516
71931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1451671931
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.1630782258
Short name T1381
Test name
Test status
Simulation time 908801019 ps
CPU time 1.97 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:30 PM PDT 24
Peak memory 207048 kb
Host smart-59aa95fb-d73d-4e0d-a4a1-d773559c27cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16307
82258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.1630782258
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3595654396
Short name T2435
Test name
Test status
Simulation time 6240930999 ps
CPU time 58.18 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 207128 kb
Host smart-1a1badca-acf9-456d-acfd-a999ca3bfe66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35956
54396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3595654396
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.885644946
Short name T497
Test name
Test status
Simulation time 44119910 ps
CPU time 0.66 seconds
Started Jul 13 07:15:51 PM PDT 24
Finished Jul 13 07:15:53 PM PDT 24
Peak memory 206936 kb
Host smart-af207e4d-3db7-42f5-820c-4f49db9ba0c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=885644946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.885644946
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2064285092
Short name T2032
Test name
Test status
Simulation time 4226798503 ps
CPU time 4.89 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 207136 kb
Host smart-caed486b-1f20-4e25-bda9-99a3d8f00bd0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2064285092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.2064285092
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.272703777
Short name T1465
Test name
Test status
Simulation time 13388665256 ps
CPU time 12.54 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:44 PM PDT 24
Peak memory 207016 kb
Host smart-d4774fbb-3db7-4a3c-9678-7559ef68b675
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=272703777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.272703777
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.139861109
Short name T2656
Test name
Test status
Simulation time 23368799294 ps
CPU time 23.15 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:15:58 PM PDT 24
Peak memory 206936 kb
Host smart-c95ea269-3e44-47a2-bc7f-9b70d2cec45a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=139861109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.139861109
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2712441006
Short name T349
Test name
Test status
Simulation time 165207230 ps
CPU time 0.79 seconds
Started Jul 13 07:15:32 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206276 kb
Host smart-95c1afaf-46d8-45f1-972a-47ba7154a0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27124
41006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2712441006
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.4190779335
Short name T1204
Test name
Test status
Simulation time 157984444 ps
CPU time 0.78 seconds
Started Jul 13 07:15:32 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206868 kb
Host smart-2e811e0c-42bb-407c-b16d-43eb4e6bb513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41907
79335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.4190779335
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2216638984
Short name T2517
Test name
Test status
Simulation time 199315632 ps
CPU time 0.92 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:31 PM PDT 24
Peak memory 206892 kb
Host smart-c20d1643-affa-44dc-8e00-7d7e16bc662a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22166
38984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2216638984
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.4060389951
Short name T2414
Test name
Test status
Simulation time 508545407 ps
CPU time 1.46 seconds
Started Jul 13 07:15:34 PM PDT 24
Finished Jul 13 07:15:37 PM PDT 24
Peak memory 206868 kb
Host smart-97796428-e386-42f1-aed8-357c5d9ed03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603
89951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.4060389951
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1453428414
Short name T1913
Test name
Test status
Simulation time 8299941391 ps
CPU time 15.81 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:15:50 PM PDT 24
Peak memory 207064 kb
Host smart-98178c33-4c06-4b34-bbfc-94a86fe122ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14534
28414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1453428414
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3134198537
Short name T1464
Test name
Test status
Simulation time 430557900 ps
CPU time 1.31 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:34 PM PDT 24
Peak memory 206900 kb
Host smart-5e0b895e-5655-4e03-8773-fd2fb9f8a716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31341
98537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3134198537
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3373469347
Short name T1175
Test name
Test status
Simulation time 138699195 ps
CPU time 0.78 seconds
Started Jul 13 07:15:32 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206868 kb
Host smart-ce22b417-53f2-4f0a-aeb5-2379c7a4023d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33734
69347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3373469347
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.965936763
Short name T1203
Test name
Test status
Simulation time 93347928 ps
CPU time 0.69 seconds
Started Jul 13 07:15:26 PM PDT 24
Finished Jul 13 07:15:29 PM PDT 24
Peak memory 206844 kb
Host smart-ec23cbe4-5109-406d-aa39-ee0325304417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96593
6763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.965936763
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2883012203
Short name T2465
Test name
Test status
Simulation time 785088201 ps
CPU time 2.08 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 207072 kb
Host smart-119445e6-67c1-471e-902a-70b9744c54cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28830
12203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2883012203
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3899687442
Short name T915
Test name
Test status
Simulation time 164210570 ps
CPU time 1.17 seconds
Started Jul 13 07:15:27 PM PDT 24
Finished Jul 13 07:15:30 PM PDT 24
Peak memory 207072 kb
Host smart-28157538-80bd-4643-9b63-ba3022c2fd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996
87442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3899687442
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.935755450
Short name T996
Test name
Test status
Simulation time 180607301 ps
CPU time 0.83 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 206864 kb
Host smart-874baea1-d779-41e5-b61c-a85a21429dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93575
5450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.935755450
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2350260061
Short name T1793
Test name
Test status
Simulation time 135132575 ps
CPU time 0.76 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206860 kb
Host smart-0f9047b7-f50c-4745-8752-d70686427bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23502
60061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2350260061
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3920834857
Short name T81
Test name
Test status
Simulation time 223893590 ps
CPU time 0.96 seconds
Started Jul 13 07:15:33 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206876 kb
Host smart-b3747b1e-b321-40e4-b0b9-bd78362014bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39208
34857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3920834857
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.356586934
Short name T840
Test name
Test status
Simulation time 7140930741 ps
CPU time 26.86 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:16:01 PM PDT 24
Peak memory 207120 kb
Host smart-16a3b7c8-cef3-4593-850e-cd472603bccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35658
6934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.356586934
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.2172130635
Short name T376
Test name
Test status
Simulation time 166199267 ps
CPU time 0.84 seconds
Started Jul 13 07:15:31 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206280 kb
Host smart-30eb88fa-61f1-49c7-9bca-041eb7eca120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21721
30635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2172130635
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1101262822
Short name T2004
Test name
Test status
Simulation time 23332790874 ps
CPU time 23.43 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:55 PM PDT 24
Peak memory 206872 kb
Host smart-6bcf7f32-010e-450f-9892-530df2085ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11012
62822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1101262822
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1423344962
Short name T281
Test name
Test status
Simulation time 3430406715 ps
CPU time 4.08 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:35 PM PDT 24
Peak memory 206868 kb
Host smart-2a2a543e-ad82-41cc-b727-62009e6dff79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14233
44962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1423344962
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.3938257679
Short name T378
Test name
Test status
Simulation time 6264092107 ps
CPU time 45.01 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 207156 kb
Host smart-2e09f450-b42e-439e-83d6-bd7913fa378c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
57679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.3938257679
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3223810100
Short name T1915
Test name
Test status
Simulation time 4681320588 ps
CPU time 47.09 seconds
Started Jul 13 07:15:32 PM PDT 24
Finished Jul 13 07:16:22 PM PDT 24
Peak memory 207148 kb
Host smart-33afba13-d7aa-46f0-a406-740fe8358036
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3223810100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3223810100
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.659223104
Short name T1588
Test name
Test status
Simulation time 241222741 ps
CPU time 0.89 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206868 kb
Host smart-ddc15218-ec97-4519-84c1-8f38795a04dc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=659223104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.659223104
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.4115686868
Short name T791
Test name
Test status
Simulation time 192637581 ps
CPU time 0.89 seconds
Started Jul 13 07:15:28 PM PDT 24
Finished Jul 13 07:15:32 PM PDT 24
Peak memory 206860 kb
Host smart-ad0531f6-171b-4149-a4a1-11179bf03820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156
86868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.4115686868
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3551276211
Short name T1577
Test name
Test status
Simulation time 4219114193 ps
CPU time 40.01 seconds
Started Jul 13 07:15:49 PM PDT 24
Finished Jul 13 07:16:30 PM PDT 24
Peak memory 207080 kb
Host smart-e5aa9717-5829-4ba0-9bba-a881cc3b908e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35512
76211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3551276211
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.725517977
Short name T1193
Test name
Test status
Simulation time 5167358837 ps
CPU time 141.33 seconds
Started Jul 13 07:15:36 PM PDT 24
Finished Jul 13 07:17:59 PM PDT 24
Peak memory 207088 kb
Host smart-882ed86f-3c5d-447c-854c-1fb4e2908141
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=725517977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.725517977
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1456598418
Short name T1254
Test name
Test status
Simulation time 173409137 ps
CPU time 0.85 seconds
Started Jul 13 07:15:30 PM PDT 24
Finished Jul 13 07:15:34 PM PDT 24
Peak memory 206876 kb
Host smart-fd02ddd9-02d8-40d8-959d-af7dfa480431
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1456598418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1456598418
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2802310943
Short name T1859
Test name
Test status
Simulation time 145445474 ps
CPU time 0.79 seconds
Started Jul 13 07:15:49 PM PDT 24
Finished Jul 13 07:15:50 PM PDT 24
Peak memory 206868 kb
Host smart-3ed28858-1dc4-4ea3-8545-a8abacb42aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28023
10943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2802310943
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.167162916
Short name T2526
Test name
Test status
Simulation time 211303102 ps
CPU time 0.85 seconds
Started Jul 13 07:15:41 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 206864 kb
Host smart-c03ccf4c-574a-4e38-9611-b6b715b36df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16716
2916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.167162916
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1081905646
Short name T338
Test name
Test status
Simulation time 165551653 ps
CPU time 0.82 seconds
Started Jul 13 07:15:47 PM PDT 24
Finished Jul 13 07:15:49 PM PDT 24
Peak memory 206868 kb
Host smart-0e86e3e4-d795-4856-9b8b-e4d33ad2d168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10819
05646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1081905646
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1153771698
Short name T489
Test name
Test status
Simulation time 152931529 ps
CPU time 0.79 seconds
Started Jul 13 07:15:33 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206860 kb
Host smart-fcb37029-3b9b-48f3-a2bc-39774f426b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11537
71698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1153771698
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2522550438
Short name T2630
Test name
Test status
Simulation time 189743376 ps
CPU time 0.8 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206868 kb
Host smart-4069ce8f-39c1-465a-9b8d-32e50bd3c0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25225
50438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2522550438
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2525772750
Short name T2483
Test name
Test status
Simulation time 151323578 ps
CPU time 0.84 seconds
Started Jul 13 07:15:32 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206868 kb
Host smart-fed61263-2d7b-4238-b6f5-9230cb04e84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25257
72750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2525772750
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.521850011
Short name T974
Test name
Test status
Simulation time 242626176 ps
CPU time 0.93 seconds
Started Jul 13 07:15:33 PM PDT 24
Finished Jul 13 07:15:36 PM PDT 24
Peak memory 206880 kb
Host smart-1f324265-d4d6-4754-989b-4cc04e3338ee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=521850011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.521850011
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1285080386
Short name T766
Test name
Test status
Simulation time 171167372 ps
CPU time 0.82 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206864 kb
Host smart-043088b9-ec3d-4ba9-ad9e-31b9acb13393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12850
80386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1285080386
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3526324060
Short name T2635
Test name
Test status
Simulation time 63638666 ps
CPU time 0.68 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206860 kb
Host smart-8a71742c-ef5a-4608-b18b-59a44388d3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35263
24060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3526324060
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3376569096
Short name T1073
Test name
Test status
Simulation time 13903540149 ps
CPU time 31.41 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:16:10 PM PDT 24
Peak memory 207080 kb
Host smart-0b75c57b-6ac1-479c-a922-1e0f9129c6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33765
69096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3376569096
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.781370540
Short name T46
Test name
Test status
Simulation time 190752306 ps
CPU time 0.85 seconds
Started Jul 13 07:15:52 PM PDT 24
Finished Jul 13 07:15:54 PM PDT 24
Peak memory 206868 kb
Host smart-90c7c7db-14f9-44c4-9c52-bb9b7a2734ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78137
0540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.781370540
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1847939028
Short name T2668
Test name
Test status
Simulation time 258667639 ps
CPU time 0.98 seconds
Started Jul 13 07:15:29 PM PDT 24
Finished Jul 13 07:15:33 PM PDT 24
Peak memory 206876 kb
Host smart-be80c0b7-79c0-4a74-a186-b91fe2d673ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18479
39028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1847939028
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2755660670
Short name T1639
Test name
Test status
Simulation time 223376761 ps
CPU time 0.87 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206868 kb
Host smart-0e101b53-7a87-425f-8303-71fdd0fb5f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27556
60670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2755660670
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.956824879
Short name T2722
Test name
Test status
Simulation time 194041910 ps
CPU time 0.93 seconds
Started Jul 13 07:15:36 PM PDT 24
Finished Jul 13 07:15:38 PM PDT 24
Peak memory 206876 kb
Host smart-0d328d68-c31b-4995-a977-c27993bd7562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95682
4879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.956824879
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.177798208
Short name T2091
Test name
Test status
Simulation time 141487296 ps
CPU time 0.8 seconds
Started Jul 13 07:15:38 PM PDT 24
Finished Jul 13 07:15:40 PM PDT 24
Peak memory 206908 kb
Host smart-540e4d7a-9369-421b-b9cf-a888b878782e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17779
8208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.177798208
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.709883265
Short name T447
Test name
Test status
Simulation time 183988741 ps
CPU time 0.85 seconds
Started Jul 13 07:15:40 PM PDT 24
Finished Jul 13 07:15:41 PM PDT 24
Peak memory 206856 kb
Host smart-5b9bf163-9310-4bda-8787-ab19bd71b547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70988
3265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.709883265
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.4204034779
Short name T928
Test name
Test status
Simulation time 212515988 ps
CPU time 0.86 seconds
Started Jul 13 07:15:47 PM PDT 24
Finished Jul 13 07:15:50 PM PDT 24
Peak memory 206864 kb
Host smart-3eb16f74-122b-4913-9ee0-cf5a39d438bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42040
34779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.4204034779
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.438380516
Short name T2138
Test name
Test status
Simulation time 228512339 ps
CPU time 0.99 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206876 kb
Host smart-fd25de6f-2aec-401f-a14a-d94a9e218898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43838
0516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.438380516
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2423305261
Short name T1473
Test name
Test status
Simulation time 5984483272 ps
CPU time 163.75 seconds
Started Jul 13 07:15:42 PM PDT 24
Finished Jul 13 07:18:26 PM PDT 24
Peak memory 207064 kb
Host smart-077b0cc7-06c4-4909-a982-f1e649d0c2f6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2423305261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2423305261
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2989244819
Short name T2384
Test name
Test status
Simulation time 173198936 ps
CPU time 0.86 seconds
Started Jul 13 07:15:39 PM PDT 24
Finished Jul 13 07:15:41 PM PDT 24
Peak memory 206852 kb
Host smart-1f2da766-bfa2-4e86-bd24-1d7e34901390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
44819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2989244819
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2740739992
Short name T2079
Test name
Test status
Simulation time 147219383 ps
CPU time 0.75 seconds
Started Jul 13 07:15:41 PM PDT 24
Finished Jul 13 07:15:43 PM PDT 24
Peak memory 206856 kb
Host smart-55991701-561c-4a1a-a9ba-c5ef8c27be06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27407
39992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2740739992
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.3128017634
Short name T724
Test name
Test status
Simulation time 1271874835 ps
CPU time 2.87 seconds
Started Jul 13 07:15:38 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 207020 kb
Host smart-07559127-d53a-4f57-80be-d6b8fd9185dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31280
17634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.3128017634
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2404193542
Short name T344
Test name
Test status
Simulation time 5805788780 ps
CPU time 41.28 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:16:26 PM PDT 24
Peak memory 207132 kb
Host smart-30b33295-4b9f-4a70-9404-bd10ffc30f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
93542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2404193542
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1889615660
Short name T2130
Test name
Test status
Simulation time 37810453 ps
CPU time 0.7 seconds
Started Jul 13 07:15:54 PM PDT 24
Finished Jul 13 07:15:56 PM PDT 24
Peak memory 206908 kb
Host smart-4f836716-cc72-4bfe-a891-2416d19d1d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1889615660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1889615660
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1285816463
Short name T1602
Test name
Test status
Simulation time 4243591233 ps
CPU time 4.88 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:15:51 PM PDT 24
Peak memory 206940 kb
Host smart-977c2b79-2594-41c8-b654-d18072baf2c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1285816463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1285816463
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3852793512
Short name T794
Test name
Test status
Simulation time 13386191011 ps
CPU time 12.89 seconds
Started Jul 13 07:15:36 PM PDT 24
Finished Jul 13 07:15:49 PM PDT 24
Peak memory 206876 kb
Host smart-04cf5bd2-d96c-46b3-9a62-7b6491cedae6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3852793512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3852793512
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3837701044
Short name T2224
Test name
Test status
Simulation time 23493088148 ps
CPU time 26.35 seconds
Started Jul 13 07:15:38 PM PDT 24
Finished Jul 13 07:16:05 PM PDT 24
Peak memory 207084 kb
Host smart-63d0cfd6-7fd3-407f-ab6a-6a05d9cc5d41
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3837701044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3837701044
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.376461515
Short name T2055
Test name
Test status
Simulation time 154975366 ps
CPU time 0.83 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206856 kb
Host smart-f7da21c7-294d-4a98-a284-3b58431664ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37646
1515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.376461515
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.747472824
Short name T1864
Test name
Test status
Simulation time 190877113 ps
CPU time 0.78 seconds
Started Jul 13 07:15:43 PM PDT 24
Finished Jul 13 07:15:45 PM PDT 24
Peak memory 206864 kb
Host smart-e330a95a-14fe-4166-a25d-75d7fecb6ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74747
2824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.747472824
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2913798180
Short name T2457
Test name
Test status
Simulation time 202407968 ps
CPU time 0.91 seconds
Started Jul 13 07:15:39 PM PDT 24
Finished Jul 13 07:15:41 PM PDT 24
Peak memory 206860 kb
Host smart-f8e77d4d-2963-4533-832b-84117f10ce76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29137
98180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2913798180
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2021477492
Short name T2522
Test name
Test status
Simulation time 419189252 ps
CPU time 1.19 seconds
Started Jul 13 07:15:40 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 206864 kb
Host smart-d53ed758-c5be-4f47-8163-7b9185cff483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20214
77492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2021477492
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.2933584503
Short name T627
Test name
Test status
Simulation time 20432929528 ps
CPU time 40.53 seconds
Started Jul 13 07:15:41 PM PDT 24
Finished Jul 13 07:16:23 PM PDT 24
Peak memory 207124 kb
Host smart-9586f17b-a0fd-4f8f-a38c-6ea3ad2336e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29335
84503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.2933584503
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3181869340
Short name T1283
Test name
Test status
Simulation time 463564345 ps
CPU time 1.36 seconds
Started Jul 13 07:15:40 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 206872 kb
Host smart-8f060549-8090-44af-aa6e-d468970c24c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31818
69340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3181869340
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.744336890
Short name T990
Test name
Test status
Simulation time 152593026 ps
CPU time 0.75 seconds
Started Jul 13 07:15:38 PM PDT 24
Finished Jul 13 07:15:40 PM PDT 24
Peak memory 206868 kb
Host smart-06b28c64-c233-4584-9838-d28be078a45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74433
6890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.744336890
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2059459573
Short name T365
Test name
Test status
Simulation time 29923061 ps
CPU time 0.68 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:45 PM PDT 24
Peak memory 206888 kb
Host smart-338aef72-177a-4422-821d-12cd790dc6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20594
59573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2059459573
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3412538781
Short name T1144
Test name
Test status
Simulation time 861896453 ps
CPU time 2.33 seconds
Started Jul 13 07:15:49 PM PDT 24
Finished Jul 13 07:15:52 PM PDT 24
Peak memory 207072 kb
Host smart-887d25da-0b2b-43a0-8605-fc3289f06aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
38781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3412538781
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2797050225
Short name T544
Test name
Test status
Simulation time 175675480 ps
CPU time 2 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 207076 kb
Host smart-bd84d5f4-8a2e-4050-9434-298582681cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27970
50225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2797050225
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.4236289218
Short name T1930
Test name
Test status
Simulation time 259977669 ps
CPU time 0.92 seconds
Started Jul 13 07:15:40 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 206820 kb
Host smart-524af7af-1eda-4603-9c79-d44dd2d43f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42362
89218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.4236289218
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.763751031
Short name T958
Test name
Test status
Simulation time 172467247 ps
CPU time 0.83 seconds
Started Jul 13 07:15:36 PM PDT 24
Finished Jul 13 07:15:38 PM PDT 24
Peak memory 206840 kb
Host smart-586e1bf7-8e8e-4545-b657-b5f2117106d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76375
1031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.763751031
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3706884708
Short name T1334
Test name
Test status
Simulation time 213288537 ps
CPU time 0.85 seconds
Started Jul 13 07:15:51 PM PDT 24
Finished Jul 13 07:15:53 PM PDT 24
Peak memory 206860 kb
Host smart-2978f21a-dfab-4be3-80a6-694a01101eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37068
84708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3706884708
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.2846242742
Short name T2645
Test name
Test status
Simulation time 9429038847 ps
CPU time 88.46 seconds
Started Jul 13 07:15:40 PM PDT 24
Finished Jul 13 07:17:09 PM PDT 24
Peak memory 207076 kb
Host smart-e88b120e-24cc-4865-808b-45ad3a955b4f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2846242742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2846242742
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1832583837
Short name T1277
Test name
Test status
Simulation time 241781586 ps
CPU time 0.91 seconds
Started Jul 13 07:15:43 PM PDT 24
Finished Jul 13 07:15:45 PM PDT 24
Peak memory 206860 kb
Host smart-de1c793a-912b-4243-b0d1-bc1d861cd725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18325
83837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1832583837
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.2132781858
Short name T844
Test name
Test status
Simulation time 23368622514 ps
CPU time 22.62 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:16:01 PM PDT 24
Peak memory 206940 kb
Host smart-84560cf7-af36-4efb-9655-d7c8069f6f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21327
81858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2132781858
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3773175837
Short name T765
Test name
Test status
Simulation time 3344586837 ps
CPU time 3.95 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 206928 kb
Host smart-36eb0bf4-d171-44a3-8091-8afdc90aeda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37731
75837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3773175837
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2654999706
Short name T2369
Test name
Test status
Simulation time 9093638769 ps
CPU time 266.56 seconds
Started Jul 13 07:15:38 PM PDT 24
Finished Jul 13 07:20:05 PM PDT 24
Peak memory 207136 kb
Host smart-9739da62-c627-4987-826a-02bacf9a8296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26549
99706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2654999706
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2092477987
Short name T2624
Test name
Test status
Simulation time 4724082432 ps
CPU time 35.97 seconds
Started Jul 13 07:15:39 PM PDT 24
Finished Jul 13 07:16:16 PM PDT 24
Peak memory 207092 kb
Host smart-edbf9f93-b5ff-4be5-aaa5-9559ebc41a2e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2092477987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2092477987
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2005736768
Short name T2523
Test name
Test status
Simulation time 239733470 ps
CPU time 0.89 seconds
Started Jul 13 07:15:43 PM PDT 24
Finished Jul 13 07:15:44 PM PDT 24
Peak memory 206864 kb
Host smart-169eeed7-6cfd-432f-99a0-8ad43f9bc8a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2005736768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2005736768
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3478080284
Short name T1445
Test name
Test status
Simulation time 196448629 ps
CPU time 0.85 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 206900 kb
Host smart-5b570652-e945-412f-831c-9c32ddb36292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34780
80284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3478080284
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.4012713670
Short name T2569
Test name
Test status
Simulation time 5388396009 ps
CPU time 153.19 seconds
Started Jul 13 07:15:38 PM PDT 24
Finished Jul 13 07:18:13 PM PDT 24
Peak memory 207056 kb
Host smart-7dc67bab-d6e9-4f5a-a304-c0efc0826007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40127
13670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.4012713670
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2956934387
Short name T1251
Test name
Test status
Simulation time 3879740623 ps
CPU time 26.96 seconds
Started Jul 13 07:15:47 PM PDT 24
Finished Jul 13 07:16:16 PM PDT 24
Peak memory 207116 kb
Host smart-a5bcb990-83d8-42be-86d1-ade7a0e12eb7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2956934387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2956934387
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1736281959
Short name T567
Test name
Test status
Simulation time 158873359 ps
CPU time 0.82 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206852 kb
Host smart-ba5f17ea-029f-4084-85dc-75830c29a71c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1736281959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1736281959
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3412052298
Short name T1030
Test name
Test status
Simulation time 150586667 ps
CPU time 0.79 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:46 PM PDT 24
Peak memory 206864 kb
Host smart-8c9dd02d-aeef-4017-a5b0-275ee9313208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34120
52298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3412052298
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3270268523
Short name T824
Test name
Test status
Simulation time 196377432 ps
CPU time 0.82 seconds
Started Jul 13 07:15:43 PM PDT 24
Finished Jul 13 07:15:44 PM PDT 24
Peak memory 206868 kb
Host smart-fd20825f-bd67-48e7-ab25-4988b3fe33aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
68523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3270268523
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1844621398
Short name T1591
Test name
Test status
Simulation time 150098207 ps
CPU time 0.83 seconds
Started Jul 13 07:15:37 PM PDT 24
Finished Jul 13 07:15:39 PM PDT 24
Peak memory 206844 kb
Host smart-2f22b58a-fe67-46ef-b505-b4d62a369a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18446
21398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1844621398
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1660294332
Short name T1245
Test name
Test status
Simulation time 172102973 ps
CPU time 0.81 seconds
Started Jul 13 07:15:41 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 206868 kb
Host smart-e1d8a6af-022e-447d-a044-989cdf7db002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
94332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1660294332
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3684368533
Short name T1905
Test name
Test status
Simulation time 195199609 ps
CPU time 0.91 seconds
Started Jul 13 07:15:50 PM PDT 24
Finished Jul 13 07:15:51 PM PDT 24
Peak memory 206876 kb
Host smart-62f6603c-0bae-4414-8d71-e3f3d7e3eeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36843
68533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3684368533
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3425609720
Short name T2311
Test name
Test status
Simulation time 153404129 ps
CPU time 0.78 seconds
Started Jul 13 07:15:42 PM PDT 24
Finished Jul 13 07:15:43 PM PDT 24
Peak memory 206860 kb
Host smart-c189fa18-1231-407d-8076-40e3d9b7f470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34256
09720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3425609720
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3318002336
Short name T2280
Test name
Test status
Simulation time 188628403 ps
CPU time 0.89 seconds
Started Jul 13 07:15:40 PM PDT 24
Finished Jul 13 07:15:42 PM PDT 24
Peak memory 206832 kb
Host smart-e7446888-fc7e-4822-8da5-7b27f96bb026
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3318002336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3318002336
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2479757962
Short name T1317
Test name
Test status
Simulation time 157673746 ps
CPU time 0.79 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:15:48 PM PDT 24
Peak memory 206864 kb
Host smart-154461f8-5aca-4591-bd24-4f24c56a9fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24797
57962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2479757962
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3703681336
Short name T34
Test name
Test status
Simulation time 72594627 ps
CPU time 0.77 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:15:48 PM PDT 24
Peak memory 206860 kb
Host smart-7e38992e-dc13-4878-915c-a3e1f79a72f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37036
81336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3703681336
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1710697035
Short name T1501
Test name
Test status
Simulation time 6293449044 ps
CPU time 15.32 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:16:02 PM PDT 24
Peak memory 207140 kb
Host smart-5d021e56-f46c-449a-bc71-6ef5f5dd7f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106
97035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1710697035
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3886413522
Short name T2023
Test name
Test status
Simulation time 152795865 ps
CPU time 0.82 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 206848 kb
Host smart-63a5b9b8-cc06-4206-b968-89c12fe7a6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38864
13522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3886413522
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2483205955
Short name T687
Test name
Test status
Simulation time 225622023 ps
CPU time 0.86 seconds
Started Jul 13 07:15:51 PM PDT 24
Finished Jul 13 07:15:52 PM PDT 24
Peak memory 206892 kb
Host smart-552e3c97-6b1c-44ed-a172-9b84babc5c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24832
05955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2483205955
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3836122960
Short name T2028
Test name
Test status
Simulation time 226773917 ps
CPU time 0.86 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:15:49 PM PDT 24
Peak memory 206872 kb
Host smart-c67ab396-2da7-41ef-9ce4-f88bca60aab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38361
22960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3836122960
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.2629325209
Short name T573
Test name
Test status
Simulation time 211445106 ps
CPU time 0.84 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:15:48 PM PDT 24
Peak memory 206816 kb
Host smart-e826826e-2484-4704-a74e-af9004ba022d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26293
25209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.2629325209
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2349772830
Short name T637
Test name
Test status
Simulation time 173096479 ps
CPU time 0.81 seconds
Started Jul 13 07:15:43 PM PDT 24
Finished Jul 13 07:15:45 PM PDT 24
Peak memory 206864 kb
Host smart-95e5a39f-b3b2-4b7e-8a45-9a7e16473892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23497
72830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2349772830
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1171016405
Short name T2229
Test name
Test status
Simulation time 208203136 ps
CPU time 0.82 seconds
Started Jul 13 07:15:55 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 206860 kb
Host smart-cc1078e2-338a-4754-931e-9fc935066860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11710
16405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1171016405
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2026398459
Short name T45
Test name
Test status
Simulation time 151153157 ps
CPU time 0.81 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:46 PM PDT 24
Peak memory 206868 kb
Host smart-97737a4c-2818-44a0-b18f-c9c890f32ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20263
98459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2026398459
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1311693324
Short name T703
Test name
Test status
Simulation time 202612697 ps
CPU time 0.92 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 206872 kb
Host smart-b7f9c3d7-4951-4b66-bed2-ae2d858cc877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13116
93324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1311693324
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.321000783
Short name T1825
Test name
Test status
Simulation time 5956710341 ps
CPU time 167.39 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:18:34 PM PDT 24
Peak memory 207108 kb
Host smart-824e9f8a-2f05-4e12-b78d-24d5de597d6a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=321000783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.321000783
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.4154353601
Short name T1907
Test name
Test status
Simulation time 209232649 ps
CPU time 0.84 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:15:48 PM PDT 24
Peak memory 206860 kb
Host smart-0f705657-104a-4d9e-b9b7-4b665b78a7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41543
53601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.4154353601
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1132609438
Short name T486
Test name
Test status
Simulation time 171337513 ps
CPU time 0.79 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:46 PM PDT 24
Peak memory 206884 kb
Host smart-2ac9176c-07d5-4e25-8176-1684bc149b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326
09438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1132609438
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2728462059
Short name T1775
Test name
Test status
Simulation time 461898576 ps
CPU time 1.29 seconds
Started Jul 13 07:15:51 PM PDT 24
Finished Jul 13 07:15:53 PM PDT 24
Peak memory 206872 kb
Host smart-cafe23bd-0c1c-4361-9f01-0b25c5f88bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27284
62059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2728462059
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1798169936
Short name T2527
Test name
Test status
Simulation time 5824781338 ps
CPU time 166.55 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:18:32 PM PDT 24
Peak memory 207080 kb
Host smart-f329b996-697f-402d-84dc-add55ce49253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
69936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1798169936
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.2798923466
Short name T1663
Test name
Test status
Simulation time 78510816 ps
CPU time 0.71 seconds
Started Jul 13 07:15:57 PM PDT 24
Finished Jul 13 07:15:58 PM PDT 24
Peak memory 206880 kb
Host smart-b73b449c-71fe-4b95-b411-2c52479394ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2798923466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.2798923466
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.303213551
Short name T946
Test name
Test status
Simulation time 3677972896 ps
CPU time 4.79 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:15:51 PM PDT 24
Peak memory 207100 kb
Host smart-6fa798db-33b3-4861-863d-082314a848db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=303213551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.303213551
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1024220180
Short name T10
Test name
Test status
Simulation time 13386411737 ps
CPU time 13.41 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:58 PM PDT 24
Peak memory 207132 kb
Host smart-4a109544-abb6-440b-b101-7111d8003b18
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1024220180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1024220180
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3429856245
Short name T1862
Test name
Test status
Simulation time 23360364378 ps
CPU time 21.87 seconds
Started Jul 13 07:15:50 PM PDT 24
Finished Jul 13 07:16:12 PM PDT 24
Peak memory 207136 kb
Host smart-4c89948c-6d36-46b8-a352-04b11dbbe776
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3429856245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.3429856245
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.4122357392
Short name T859
Test name
Test status
Simulation time 168488696 ps
CPU time 0.83 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:46 PM PDT 24
Peak memory 206860 kb
Host smart-b2a2792f-cbd6-4a1e-a574-add2b31a1316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41223
57392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.4122357392
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3428580841
Short name T2419
Test name
Test status
Simulation time 156997365 ps
CPU time 0.77 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 206888 kb
Host smart-77b59e56-de96-40c7-9953-b1bd9c4cc245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34285
80841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3428580841
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.217079355
Short name T2441
Test name
Test status
Simulation time 395475858 ps
CPU time 1.34 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 206872 kb
Host smart-48d231a4-345b-4ecf-bc87-e2d3475894e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21707
9355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.217079355
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3851450741
Short name T1513
Test name
Test status
Simulation time 1040928456 ps
CPU time 2.61 seconds
Started Jul 13 07:15:44 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 207096 kb
Host smart-0bcebb25-f4d7-4bfb-8e7a-6a3885b9b32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38514
50741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3851450741
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2532054768
Short name T2373
Test name
Test status
Simulation time 440078625 ps
CPU time 1.24 seconds
Started Jul 13 07:15:54 PM PDT 24
Finished Jul 13 07:15:56 PM PDT 24
Peak memory 206864 kb
Host smart-a177092d-0237-47d5-9563-079084d24bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25320
54768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2532054768
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3303802961
Short name T1425
Test name
Test status
Simulation time 152987633 ps
CPU time 0.76 seconds
Started Jul 13 07:16:06 PM PDT 24
Finished Jul 13 07:16:07 PM PDT 24
Peak memory 206804 kb
Host smart-419fd214-3c21-48ef-95f8-8b2686516a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33038
02961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3303802961
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3438099475
Short name T1661
Test name
Test status
Simulation time 42856359 ps
CPU time 0.66 seconds
Started Jul 13 07:15:55 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 206864 kb
Host smart-c6195ba3-6c61-4eef-9cf7-bd334bd485ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34380
99475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3438099475
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.4276445093
Short name T1809
Test name
Test status
Simulation time 914248275 ps
CPU time 2.23 seconds
Started Jul 13 07:15:54 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 207072 kb
Host smart-6ab6dcf0-3740-482c-99f3-fcd2e7519c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42764
45093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.4276445093
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.109834631
Short name T2396
Test name
Test status
Simulation time 218075376 ps
CPU time 1.35 seconds
Started Jul 13 07:15:47 PM PDT 24
Finished Jul 13 07:15:49 PM PDT 24
Peak memory 207300 kb
Host smart-23bfc957-e93c-4a91-b2bf-be0cf9f492eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10983
4631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.109834631
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1768622115
Short name T1931
Test name
Test status
Simulation time 189665335 ps
CPU time 1.02 seconds
Started Jul 13 07:15:55 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 206876 kb
Host smart-20e0022f-89d0-4abd-aac1-0057635f9a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17686
22115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1768622115
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3097533617
Short name T373
Test name
Test status
Simulation time 171102269 ps
CPU time 0.76 seconds
Started Jul 13 07:15:52 PM PDT 24
Finished Jul 13 07:15:53 PM PDT 24
Peak memory 206876 kb
Host smart-da9ec236-7660-42c4-8af7-51816d855e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30975
33617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3097533617
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2096341530
Short name T502
Test name
Test status
Simulation time 245031072 ps
CPU time 0.95 seconds
Started Jul 13 07:15:47 PM PDT 24
Finished Jul 13 07:15:49 PM PDT 24
Peak memory 206872 kb
Host smart-62706431-bc39-47e5-8bed-191ebe881fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20963
41530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2096341530
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.3477762357
Short name T104
Test name
Test status
Simulation time 6120308616 ps
CPU time 49.24 seconds
Started Jul 13 07:15:47 PM PDT 24
Finished Jul 13 07:16:38 PM PDT 24
Peak memory 207144 kb
Host smart-76e083aa-293f-4a74-b6ff-2f626ff39789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34777
62357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.3477762357
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.746868091
Short name T1521
Test name
Test status
Simulation time 247279922 ps
CPU time 0.91 seconds
Started Jul 13 07:16:04 PM PDT 24
Finished Jul 13 07:16:06 PM PDT 24
Peak memory 206524 kb
Host smart-a30ef2cd-aa13-49b0-9265-6713a4edfade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74686
8091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.746868091
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1442796863
Short name T616
Test name
Test status
Simulation time 23313295152 ps
CPU time 22.05 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:16:10 PM PDT 24
Peak memory 206884 kb
Host smart-0bd63dad-1625-460e-ae62-04da8c5b596d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14427
96863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1442796863
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3266335221
Short name T2538
Test name
Test status
Simulation time 3273581293 ps
CPU time 3.61 seconds
Started Jul 13 07:15:45 PM PDT 24
Finished Jul 13 07:15:51 PM PDT 24
Peak memory 206932 kb
Host smart-67e618ec-d9dd-49cb-9718-a9c880d8862f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32663
35221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3266335221
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.616490954
Short name T2444
Test name
Test status
Simulation time 9143345230 ps
CPU time 261.61 seconds
Started Jul 13 07:15:49 PM PDT 24
Finished Jul 13 07:20:12 PM PDT 24
Peak memory 207164 kb
Host smart-e9d93784-4f72-42fb-afab-f1adc4bc5744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61649
0954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.616490954
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.606699339
Short name T1123
Test name
Test status
Simulation time 7031350121 ps
CPU time 199.24 seconds
Started Jul 13 07:15:55 PM PDT 24
Finished Jul 13 07:19:15 PM PDT 24
Peak memory 207088 kb
Host smart-6bbe550a-9842-4415-9c08-7994091410fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=606699339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.606699339
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3932819043
Short name T2489
Test name
Test status
Simulation time 258242920 ps
CPU time 0.89 seconds
Started Jul 13 07:16:04 PM PDT 24
Finished Jul 13 07:16:06 PM PDT 24
Peak memory 206592 kb
Host smart-966bf7e7-310f-4af7-b652-f913b47f2610
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3932819043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3932819043
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.4062813822
Short name T599
Test name
Test status
Simulation time 194286330 ps
CPU time 0.84 seconds
Started Jul 13 07:15:58 PM PDT 24
Finished Jul 13 07:16:00 PM PDT 24
Peak memory 206804 kb
Host smart-2cd3f7e5-f91c-4c96-92d5-7f4571c164ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
13822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.4062813822
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1878958017
Short name T2520
Test name
Test status
Simulation time 6073870315 ps
CPU time 172.26 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:18:40 PM PDT 24
Peak memory 207080 kb
Host smart-c276f6c6-1209-40bd-8aa3-ba975d664cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
58017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1878958017
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.9909158
Short name T856
Test name
Test status
Simulation time 4291784174 ps
CPU time 30.79 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:16:19 PM PDT 24
Peak memory 207152 kb
Host smart-18fbba17-6fce-4cd5-bd7e-b4780e4864e3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=9909158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.9909158
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.572961836
Short name T1665
Test name
Test status
Simulation time 198537163 ps
CPU time 0.89 seconds
Started Jul 13 07:15:48 PM PDT 24
Finished Jul 13 07:15:50 PM PDT 24
Peak memory 206868 kb
Host smart-e02e9969-f19c-44b8-bd91-10573b4c709b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=572961836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.572961836
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.194208351
Short name T2521
Test name
Test status
Simulation time 139838853 ps
CPU time 0.77 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:15:48 PM PDT 24
Peak memory 206884 kb
Host smart-8d0bb904-0432-4068-a7ae-5f1cbae6d795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
8351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.194208351
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1165812077
Short name T2595
Test name
Test status
Simulation time 216284966 ps
CPU time 0.92 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:02 PM PDT 24
Peak memory 206808 kb
Host smart-a08577fd-e4ba-4531-ac1b-46879d38191f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11658
12077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1165812077
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.368071389
Short name T760
Test name
Test status
Simulation time 195156189 ps
CPU time 0.91 seconds
Started Jul 13 07:16:03 PM PDT 24
Finished Jul 13 07:16:05 PM PDT 24
Peak memory 206796 kb
Host smart-a7f60528-eb59-40d6-b5ff-68ee7b99a9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36807
1389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.368071389
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.4182258807
Short name T609
Test name
Test status
Simulation time 177106506 ps
CPU time 0.81 seconds
Started Jul 13 07:15:51 PM PDT 24
Finished Jul 13 07:15:52 PM PDT 24
Peak memory 206864 kb
Host smart-a8d97de4-100a-4772-ab6d-bb63bfd8610a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41822
58807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.4182258807
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3371548598
Short name T371
Test name
Test status
Simulation time 180563485 ps
CPU time 0.84 seconds
Started Jul 13 07:15:47 PM PDT 24
Finished Jul 13 07:15:49 PM PDT 24
Peak memory 207112 kb
Host smart-5662b6d0-90ec-4609-9e39-96f843bb95fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33715
48598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3371548598
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3991895385
Short name T669
Test name
Test status
Simulation time 156980601 ps
CPU time 0.79 seconds
Started Jul 13 07:15:46 PM PDT 24
Finished Jul 13 07:15:49 PM PDT 24
Peak memory 206872 kb
Host smart-044a3b33-8b89-4710-ba3a-34d13f2ca0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
95385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3991895385
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.515288150
Short name T636
Test name
Test status
Simulation time 222220932 ps
CPU time 0.92 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:02 PM PDT 24
Peak memory 206816 kb
Host smart-fccc4375-9bfb-496d-bc4f-f9b1e5f08aa7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=515288150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.515288150
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.947093922
Short name T1873
Test name
Test status
Simulation time 148852555 ps
CPU time 0.78 seconds
Started Jul 13 07:16:03 PM PDT 24
Finished Jul 13 07:16:05 PM PDT 24
Peak memory 206808 kb
Host smart-aa45ac23-3e49-4100-a8b2-5baeb403cab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94709
3922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.947093922
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3094050319
Short name T1363
Test name
Test status
Simulation time 43009443 ps
CPU time 0.66 seconds
Started Jul 13 07:16:03 PM PDT 24
Finished Jul 13 07:16:05 PM PDT 24
Peak memory 206660 kb
Host smart-c2cc639a-4d46-405d-8d67-43cf651ef963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30940
50319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3094050319
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2129121688
Short name T2696
Test name
Test status
Simulation time 22946817949 ps
CPU time 51.16 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:53 PM PDT 24
Peak memory 207104 kb
Host smart-f8114207-33b3-4c9d-a11a-53da2978c96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21291
21688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2129121688
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3261423098
Short name T2376
Test name
Test status
Simulation time 178650687 ps
CPU time 0.87 seconds
Started Jul 13 07:15:55 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 206856 kb
Host smart-aaada9cf-5e52-4b2a-b605-c0de04bc5e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
23098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3261423098
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2891474662
Short name T1111
Test name
Test status
Simulation time 205859519 ps
CPU time 0.87 seconds
Started Jul 13 07:15:54 PM PDT 24
Finished Jul 13 07:15:56 PM PDT 24
Peak memory 206880 kb
Host smart-cea4be26-7eee-436d-bbb8-a87c12f2abfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28914
74662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2891474662
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3769353289
Short name T1901
Test name
Test status
Simulation time 174798634 ps
CPU time 0.88 seconds
Started Jul 13 07:15:58 PM PDT 24
Finished Jul 13 07:15:59 PM PDT 24
Peak memory 206880 kb
Host smart-f4eb1866-f3ed-4184-ae52-4ef09b955eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37693
53289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3769353289
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.424611011
Short name T2096
Test name
Test status
Simulation time 220853503 ps
CPU time 0.88 seconds
Started Jul 13 07:15:57 PM PDT 24
Finished Jul 13 07:15:59 PM PDT 24
Peak memory 206868 kb
Host smart-0f2bcc79-d5f7-4d41-b8e6-f0ab3bb78eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42461
1011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.424611011
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.548488357
Short name T397
Test name
Test status
Simulation time 187517395 ps
CPU time 0.88 seconds
Started Jul 13 07:15:53 PM PDT 24
Finished Jul 13 07:15:54 PM PDT 24
Peak memory 206912 kb
Host smart-21c7dfb3-c059-4beb-9519-b37b730b26be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54848
8357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.548488357
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1088408714
Short name T601
Test name
Test status
Simulation time 141691394 ps
CPU time 0.79 seconds
Started Jul 13 07:15:56 PM PDT 24
Finished Jul 13 07:15:58 PM PDT 24
Peak memory 206840 kb
Host smart-e73cd254-4e16-404e-993e-b29cad2c57f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
08714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1088408714
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1639788758
Short name T1718
Test name
Test status
Simulation time 154165774 ps
CPU time 0.84 seconds
Started Jul 13 07:15:52 PM PDT 24
Finished Jul 13 07:15:54 PM PDT 24
Peak memory 206868 kb
Host smart-e707601f-cc60-4257-a6de-bc9d539277a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16397
88758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1639788758
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1512504384
Short name T2046
Test name
Test status
Simulation time 217017146 ps
CPU time 0.89 seconds
Started Jul 13 07:15:51 PM PDT 24
Finished Jul 13 07:15:52 PM PDT 24
Peak memory 206876 kb
Host smart-3eac7429-d212-464b-8e1a-7f260d3d3db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125
04384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1512504384
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.4233269294
Short name T1767
Test name
Test status
Simulation time 6135369105 ps
CPU time 45.81 seconds
Started Jul 13 07:15:54 PM PDT 24
Finished Jul 13 07:16:41 PM PDT 24
Peak memory 207068 kb
Host smart-6847a0f3-6979-4585-93e8-1e995a9c3191
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4233269294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.4233269294
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2105732491
Short name T914
Test name
Test status
Simulation time 188335912 ps
CPU time 0.83 seconds
Started Jul 13 07:15:56 PM PDT 24
Finished Jul 13 07:15:58 PM PDT 24
Peak memory 206852 kb
Host smart-3fc48a71-0c39-4e08-8ba2-deea84e18903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
32491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2105732491
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2205784276
Short name T538
Test name
Test status
Simulation time 185464181 ps
CPU time 0.87 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206876 kb
Host smart-a0ec5995-70f1-4874-8d92-708401ddd7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22057
84276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2205784276
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1572081731
Short name T1360
Test name
Test status
Simulation time 518841982 ps
CPU time 1.41 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:01 PM PDT 24
Peak memory 206756 kb
Host smart-cc79d139-dd87-4ed4-a630-a4796a5b16be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15720
81731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1572081731
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.470853075
Short name T2275
Test name
Test status
Simulation time 6019094448 ps
CPU time 173.31 seconds
Started Jul 13 07:15:52 PM PDT 24
Finished Jul 13 07:18:46 PM PDT 24
Peak memory 207080 kb
Host smart-50fc5c6b-0ad7-4f40-ae97-2368cd0d5320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47085
3075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.470853075
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1265160382
Short name T1710
Test name
Test status
Simulation time 39814495 ps
CPU time 0.65 seconds
Started Jul 13 07:09:21 PM PDT 24
Finished Jul 13 07:09:26 PM PDT 24
Peak memory 206936 kb
Host smart-d6e72e45-44c7-4510-bc20-aa84b9257c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1265160382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1265160382
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3463598270
Short name T1008
Test name
Test status
Simulation time 4162880223 ps
CPU time 4.84 seconds
Started Jul 13 07:09:07 PM PDT 24
Finished Jul 13 07:09:12 PM PDT 24
Peak memory 207040 kb
Host smart-8df0510a-f21a-423f-9802-9868cae6cda5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3463598270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.3463598270
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2097192533
Short name T2002
Test name
Test status
Simulation time 13407160350 ps
CPU time 12.05 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:17 PM PDT 24
Peak memory 206952 kb
Host smart-9f96255a-8472-472d-94cd-99bac54cc163
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2097192533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2097192533
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3611814723
Short name T2482
Test name
Test status
Simulation time 23420252505 ps
CPU time 21.69 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:25 PM PDT 24
Peak memory 207080 kb
Host smart-94aeb2e1-0da5-409e-a01b-3b09c0e743ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3611814723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3611814723
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.628408439
Short name T1301
Test name
Test status
Simulation time 176669592 ps
CPU time 0.82 seconds
Started Jul 13 07:09:06 PM PDT 24
Finished Jul 13 07:09:08 PM PDT 24
Peak memory 206876 kb
Host smart-8daa4f67-f252-4b0c-84f8-534f878c226d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62840
8439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.628408439
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.128317549
Short name T55
Test name
Test status
Simulation time 185129423 ps
CPU time 0.87 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:06 PM PDT 24
Peak memory 206856 kb
Host smart-f720b350-87fe-4d11-8981-f784a750eef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12831
7549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.128317549
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.343219723
Short name T2209
Test name
Test status
Simulation time 138337663 ps
CPU time 0.77 seconds
Started Jul 13 07:09:04 PM PDT 24
Finished Jul 13 07:09:07 PM PDT 24
Peak memory 206892 kb
Host smart-22a9ee6e-1b17-4d10-91c6-f35fdde39ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34321
9723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.343219723
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2927622713
Short name T594
Test name
Test status
Simulation time 150829577 ps
CPU time 0.77 seconds
Started Jul 13 07:09:08 PM PDT 24
Finished Jul 13 07:09:10 PM PDT 24
Peak memory 206864 kb
Host smart-3acf9eb9-0419-4b75-ba09-b3301f3023db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29276
22713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2927622713
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.147057887
Short name T2178
Test name
Test status
Simulation time 412737884 ps
CPU time 1.36 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:05 PM PDT 24
Peak memory 206884 kb
Host smart-04f85160-fe31-4170-8094-319e661eb219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14705
7887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.147057887
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1838911992
Short name T2003
Test name
Test status
Simulation time 851507372 ps
CPU time 1.99 seconds
Started Jul 13 07:09:07 PM PDT 24
Finished Jul 13 07:09:10 PM PDT 24
Peak memory 207020 kb
Host smart-ccfe1acc-2e5f-4d2b-9445-b5351b50eaeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18389
11992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1838911992
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3456950972
Short name T496
Test name
Test status
Simulation time 15230273856 ps
CPU time 32.24 seconds
Started Jul 13 07:09:05 PM PDT 24
Finished Jul 13 07:09:38 PM PDT 24
Peak memory 207132 kb
Host smart-98b8691b-f97b-4a7a-a3ca-ab04c7def9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569
50972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3456950972
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.2584351187
Short name T358
Test name
Test status
Simulation time 346858348 ps
CPU time 1.16 seconds
Started Jul 13 07:09:03 PM PDT 24
Finished Jul 13 07:09:04 PM PDT 24
Peak memory 206912 kb
Host smart-aa9bf09e-ff61-4275-9785-32797201018b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25843
51187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.2584351187
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3365780981
Short name T753
Test name
Test status
Simulation time 139472236 ps
CPU time 0.78 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:09:14 PM PDT 24
Peak memory 206884 kb
Host smart-9d971729-3dc3-4d34-a192-740af2958b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33657
80981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3365780981
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.4141975676
Short name T745
Test name
Test status
Simulation time 37107696 ps
CPU time 0.66 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:18 PM PDT 24
Peak memory 206720 kb
Host smart-beffc1e9-4a2c-4e55-a1d8-9af61644be4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419
75676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.4141975676
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3483577811
Short name T2129
Test name
Test status
Simulation time 896848911 ps
CPU time 2.25 seconds
Started Jul 13 07:09:13 PM PDT 24
Finished Jul 13 07:09:17 PM PDT 24
Peak memory 207060 kb
Host smart-9a9ef9ad-3173-41bb-b82d-5484e0c54fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34835
77811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3483577811
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2780368692
Short name T2260
Test name
Test status
Simulation time 287603450 ps
CPU time 1.76 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:09:15 PM PDT 24
Peak memory 207016 kb
Host smart-4a9b1b71-ae52-4dfd-b994-de5c42d73bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27803
68692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2780368692
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.3198636723
Short name T1173
Test name
Test status
Simulation time 89171790917 ps
CPU time 127.01 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:11:20 PM PDT 24
Peak memory 207096 kb
Host smart-8d4c7ab5-5693-4dce-b688-57aad62b5722
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3198636723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.3198636723
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.2189751904
Short name T2381
Test name
Test status
Simulation time 112332637752 ps
CPU time 147.25 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:11:45 PM PDT 24
Peak memory 207128 kb
Host smart-3a32b7a7-319b-45d1-a11f-da3c2da9f56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189751904 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.2189751904
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.4211422861
Short name T1145
Test name
Test status
Simulation time 103114109513 ps
CPU time 137.52 seconds
Started Jul 13 07:09:14 PM PDT 24
Finished Jul 13 07:11:33 PM PDT 24
Peak memory 207092 kb
Host smart-6f1174d9-d34a-4113-a1bd-4deff703bcb2
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4211422861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.4211422861
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.423626085
Short name T2564
Test name
Test status
Simulation time 98176931574 ps
CPU time 146.22 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:11:44 PM PDT 24
Peak memory 207128 kb
Host smart-44906862-af8e-4ff5-8c2d-a8590a876190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423626085 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.423626085
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.269640108
Short name T392
Test name
Test status
Simulation time 84126924584 ps
CPU time 115.59 seconds
Started Jul 13 07:09:10 PM PDT 24
Finished Jul 13 07:11:06 PM PDT 24
Peak memory 207072 kb
Host smart-75668534-ef3e-42e5-8e4b-345733def6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26964
0108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.269640108
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1675684144
Short name T105
Test name
Test status
Simulation time 172898098 ps
CPU time 0.8 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:09:14 PM PDT 24
Peak memory 206812 kb
Host smart-1a0d4c20-5001-4284-909d-3650918a181f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16756
84144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1675684144
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.559678658
Short name T813
Test name
Test status
Simulation time 178424020 ps
CPU time 0.75 seconds
Started Jul 13 07:09:09 PM PDT 24
Finished Jul 13 07:09:11 PM PDT 24
Peak memory 206852 kb
Host smart-122ceac4-84f1-4a4f-87e4-63c92e1d33c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55967
8658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.559678658
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.579758828
Short name T721
Test name
Test status
Simulation time 171121219 ps
CPU time 0.76 seconds
Started Jul 13 07:09:12 PM PDT 24
Finished Jul 13 07:09:15 PM PDT 24
Peak memory 206852 kb
Host smart-f2781423-ba16-46c6-8dbf-7ae551a7f8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57975
8828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.579758828
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.4077672292
Short name T2080
Test name
Test status
Simulation time 10130237051 ps
CPU time 97.5 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:10:55 PM PDT 24
Peak memory 207060 kb
Host smart-d7d07150-b279-4ee3-9c14-1422f485fcbb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4077672292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.4077672292
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2507366646
Short name T1424
Test name
Test status
Simulation time 241471603 ps
CPU time 0.9 seconds
Started Jul 13 07:09:10 PM PDT 24
Finished Jul 13 07:09:12 PM PDT 24
Peak memory 206848 kb
Host smart-ff7f6617-9b40-4453-8eab-b4f518c45806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25073
66646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2507366646
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1850568222
Short name T169
Test name
Test status
Simulation time 23286943636 ps
CPU time 22.84 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:40 PM PDT 24
Peak memory 206940 kb
Host smart-84b6e36c-86d4-4e44-bd8f-0f0cf2c27e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
68222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1850568222
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2752564578
Short name T1068
Test name
Test status
Simulation time 3329539599 ps
CPU time 4.16 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:21 PM PDT 24
Peak memory 206932 kb
Host smart-d1326645-9bad-44b5-a6dc-48b603a4434f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
64578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2752564578
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3142040676
Short name T1176
Test name
Test status
Simulation time 8330127252 ps
CPU time 225.06 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:12:57 PM PDT 24
Peak memory 207184 kb
Host smart-8168534f-799c-458e-8b07-ae8f15f139de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31420
40676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3142040676
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1510268045
Short name T2220
Test name
Test status
Simulation time 5260350139 ps
CPU time 145.62 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:11:38 PM PDT 24
Peak memory 207084 kb
Host smart-0092f5b6-86fb-4e2f-a056-86fcac3398b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1510268045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1510268045
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2664862107
Short name T325
Test name
Test status
Simulation time 240610436 ps
CPU time 0.9 seconds
Started Jul 13 07:09:13 PM PDT 24
Finished Jul 13 07:09:15 PM PDT 24
Peak memory 206884 kb
Host smart-aad9d9c7-62c0-4f90-a560-928690f53eed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2664862107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2664862107
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.876574653
Short name T2398
Test name
Test status
Simulation time 198854090 ps
CPU time 0.88 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:19 PM PDT 24
Peak memory 206868 kb
Host smart-8c9eac75-fdec-4c5d-a528-e5432041cf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87657
4653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.876574653
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.1089468366
Short name T2417
Test name
Test status
Simulation time 3972374765 ps
CPU time 29.02 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:09:42 PM PDT 24
Peak memory 207068 kb
Host smart-8f45e10c-599a-4734-a55f-87531d0f1544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
68366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.1089468366
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2466961627
Short name T384
Test name
Test status
Simulation time 4574411746 ps
CPU time 125.43 seconds
Started Jul 13 07:09:14 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 207060 kb
Host smart-dd9326fd-4c7c-42cd-acd9-d2bb7bf03c5d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2466961627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2466961627
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2267209195
Short name T1392
Test name
Test status
Simulation time 154379211 ps
CPU time 0.81 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:17 PM PDT 24
Peak memory 206868 kb
Host smart-b0b345bf-27ca-46fd-849e-7512382bfbf5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2267209195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2267209195
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.783719732
Short name T2137
Test name
Test status
Simulation time 204637440 ps
CPU time 0.8 seconds
Started Jul 13 07:09:13 PM PDT 24
Finished Jul 13 07:09:16 PM PDT 24
Peak memory 206912 kb
Host smart-7e5aab9e-b1e2-4d52-9a71-2cb43e9ac325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78371
9732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.783719732
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2049417940
Short name T133
Test name
Test status
Simulation time 163667052 ps
CPU time 0.8 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:09:13 PM PDT 24
Peak memory 206860 kb
Host smart-f7ce21a2-270a-4e0d-8db5-98df6ccb6ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20494
17940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2049417940
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2820792598
Short name T2437
Test name
Test status
Simulation time 150009845 ps
CPU time 0.78 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:17 PM PDT 24
Peak memory 206868 kb
Host smart-ca066a78-75b6-4f62-85a6-771b56eefa52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
92598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2820792598
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1139708893
Short name T337
Test name
Test status
Simulation time 164382590 ps
CPU time 0.77 seconds
Started Jul 13 07:09:10 PM PDT 24
Finished Jul 13 07:09:12 PM PDT 24
Peak memory 206896 kb
Host smart-383c6f54-80cc-4ff5-8969-6d1dca17b2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397
08893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1139708893
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3436040566
Short name T1186
Test name
Test status
Simulation time 159176878 ps
CPU time 0.88 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:09:13 PM PDT 24
Peak memory 206892 kb
Host smart-38f13e73-5a7f-459e-82b3-154c0089d1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34360
40566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3436040566
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1794411075
Short name T1212
Test name
Test status
Simulation time 147250860 ps
CPU time 0.79 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:09:14 PM PDT 24
Peak memory 206900 kb
Host smart-b05b1479-d777-40de-8424-73ddedf600cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17944
11075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1794411075
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2482557182
Short name T195
Test name
Test status
Simulation time 214522915 ps
CPU time 0.89 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:18 PM PDT 24
Peak memory 206872 kb
Host smart-efffd8b2-5575-40c7-bc2f-6ee0b86bb417
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2482557182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2482557182
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.4268959865
Short name T1635
Test name
Test status
Simulation time 221879178 ps
CPU time 0.97 seconds
Started Jul 13 07:09:10 PM PDT 24
Finished Jul 13 07:09:12 PM PDT 24
Peak memory 206864 kb
Host smart-7709116d-9ef5-481d-a78c-988525aaaa3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42689
59865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.4268959865
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2102904988
Short name T1120
Test name
Test status
Simulation time 145305855 ps
CPU time 0.82 seconds
Started Jul 13 07:09:14 PM PDT 24
Finished Jul 13 07:09:17 PM PDT 24
Peak memory 206868 kb
Host smart-7f3de437-3216-4648-80f9-86e0dff0f5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21029
04988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2102904988
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2426329673
Short name T1950
Test name
Test status
Simulation time 32894342 ps
CPU time 0.66 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:17 PM PDT 24
Peak memory 206868 kb
Host smart-e3dde88b-e137-4ef5-b4f2-60bbca287656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24263
29673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2426329673
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2039607759
Short name T2069
Test name
Test status
Simulation time 10468354715 ps
CPU time 19.72 seconds
Started Jul 13 07:09:10 PM PDT 24
Finished Jul 13 07:09:31 PM PDT 24
Peak memory 207112 kb
Host smart-1101cad0-3e41-44e7-a868-96de7362aed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20396
07759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2039607759
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.543668016
Short name T1616
Test name
Test status
Simulation time 162840671 ps
CPU time 0.79 seconds
Started Jul 13 07:09:10 PM PDT 24
Finished Jul 13 07:09:12 PM PDT 24
Peak memory 206880 kb
Host smart-2817385e-272c-427c-9ec0-e46b2fdea99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54366
8016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.543668016
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2549802387
Short name T2357
Test name
Test status
Simulation time 206299033 ps
CPU time 0.85 seconds
Started Jul 13 07:09:12 PM PDT 24
Finished Jul 13 07:09:15 PM PDT 24
Peak memory 206868 kb
Host smart-b5e7949d-3c6d-45dc-8607-5eca7b4ac3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25498
02387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2549802387
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.4190232386
Short name T160
Test name
Test status
Simulation time 6179119073 ps
CPU time 156.08 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:11:50 PM PDT 24
Peak memory 207108 kb
Host smart-f49de9b4-7d4c-40cc-a6ba-7d504db14172
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4190232386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.4190232386
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1294570593
Short name T965
Test name
Test status
Simulation time 11428473187 ps
CPU time 60.19 seconds
Started Jul 13 07:09:12 PM PDT 24
Finished Jul 13 07:10:14 PM PDT 24
Peak memory 207064 kb
Host smart-2d583595-34c4-4053-99f1-dad9571ed8f8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1294570593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1294570593
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3983350925
Short name T2705
Test name
Test status
Simulation time 14159330530 ps
CPU time 320.73 seconds
Started Jul 13 07:09:13 PM PDT 24
Finished Jul 13 07:14:35 PM PDT 24
Peak memory 207108 kb
Host smart-b465a929-1561-4a84-b865-84efc132f867
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3983350925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3983350925
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.225079023
Short name T2201
Test name
Test status
Simulation time 245729944 ps
CPU time 0.85 seconds
Started Jul 13 07:09:11 PM PDT 24
Finished Jul 13 07:09:14 PM PDT 24
Peak memory 206868 kb
Host smart-9473f943-9097-4dfe-8969-54c306b9acc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22507
9023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.225079023
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.225270364
Short name T1189
Test name
Test status
Simulation time 156041050 ps
CPU time 0.8 seconds
Started Jul 13 07:09:12 PM PDT 24
Finished Jul 13 07:09:15 PM PDT 24
Peak memory 206864 kb
Host smart-469efe96-6801-4b91-8281-7c3bfe2bc892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
0364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.225270364
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1951944482
Short name T1803
Test name
Test status
Simulation time 160069456 ps
CPU time 0.81 seconds
Started Jul 13 07:09:06 PM PDT 24
Finished Jul 13 07:09:07 PM PDT 24
Peak memory 206872 kb
Host smart-ac0ed0fa-a935-4c4e-b874-d25dced60333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19519
44482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1951944482
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.4122255613
Short name T70
Test name
Test status
Simulation time 208711037 ps
CPU time 0.89 seconds
Started Jul 13 07:09:14 PM PDT 24
Finished Jul 13 07:09:17 PM PDT 24
Peak memory 206868 kb
Host smart-894040ed-4c94-46a3-a3cd-9ef1431a1a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41222
55613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.4122255613
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.401527766
Short name T172
Test name
Test status
Simulation time 505229610 ps
CPU time 1.33 seconds
Started Jul 13 07:09:19 PM PDT 24
Finished Jul 13 07:09:23 PM PDT 24
Peak memory 225600 kb
Host smart-4da28a5b-c6eb-465a-8659-db4856732167
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=401527766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.401527766
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.3275795583
Short name T2364
Test name
Test status
Simulation time 371929602 ps
CPU time 1.2 seconds
Started Jul 13 07:09:13 PM PDT 24
Finished Jul 13 07:09:16 PM PDT 24
Peak memory 206876 kb
Host smart-4ff294b1-a7ab-4d12-9db8-d98ea08ef166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32757
95583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3275795583
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3853871337
Short name T1542
Test name
Test status
Simulation time 287553310 ps
CPU time 0.95 seconds
Started Jul 13 07:09:15 PM PDT 24
Finished Jul 13 07:09:18 PM PDT 24
Peak memory 206744 kb
Host smart-f7725c9b-9d95-45ab-a9e9-6abbca8e6285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38538
71337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3853871337
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.4021491317
Short name T2494
Test name
Test status
Simulation time 159444550 ps
CPU time 0.76 seconds
Started Jul 13 07:09:09 PM PDT 24
Finished Jul 13 07:09:11 PM PDT 24
Peak memory 206860 kb
Host smart-9cc0cf2d-8843-4f8a-b0ef-049181ec454c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40214
91317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.4021491317
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.783186044
Short name T498
Test name
Test status
Simulation time 150852358 ps
CPU time 0.74 seconds
Started Jul 13 07:09:13 PM PDT 24
Finished Jul 13 07:09:15 PM PDT 24
Peak memory 206864 kb
Host smart-0548738b-b478-44a0-80a4-16be45430e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78318
6044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.783186044
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.779921769
Short name T1724
Test name
Test status
Simulation time 214770619 ps
CPU time 0.9 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:24 PM PDT 24
Peak memory 206860 kb
Host smart-80da9d0b-fded-4dd7-95f9-1b91d66c6e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77992
1769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.779921769
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.990495033
Short name T526
Test name
Test status
Simulation time 3335246362 ps
CPU time 25.63 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:48 PM PDT 24
Peak memory 207032 kb
Host smart-452c8b5f-0b1f-4948-ac24-9c46a604ae5b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=990495033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.990495033
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.768569560
Short name T380
Test name
Test status
Simulation time 170392402 ps
CPU time 0.8 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:24 PM PDT 24
Peak memory 206876 kb
Host smart-eed216a1-47f1-4d22-9b59-c0a84f1b614a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76856
9560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.768569560
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3364987469
Short name T1709
Test name
Test status
Simulation time 178172666 ps
CPU time 0.85 seconds
Started Jul 13 07:09:23 PM PDT 24
Finished Jul 13 07:09:27 PM PDT 24
Peak memory 206848 kb
Host smart-3332951c-022f-41fd-a08c-10e78cca6888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
87469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3364987469
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2967336909
Short name T1492
Test name
Test status
Simulation time 264208642 ps
CPU time 0.96 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:24 PM PDT 24
Peak memory 206868 kb
Host smart-47c950b7-0a3c-40f1-8285-9aec6beaf8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29673
36909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2967336909
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2524919150
Short name T528
Test name
Test status
Simulation time 5322631016 ps
CPU time 151.73 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:11:55 PM PDT 24
Peak memory 207072 kb
Host smart-89937f4e-abb4-478e-a3b1-d37a14962e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25249
19150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2524919150
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3658433269
Short name T1458
Test name
Test status
Simulation time 57759826 ps
CPU time 0.66 seconds
Started Jul 13 07:15:58 PM PDT 24
Finished Jul 13 07:15:59 PM PDT 24
Peak memory 206928 kb
Host smart-e1dee1b1-fd46-4f6f-b7cb-5e5004d7bf5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3658433269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3658433269
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3578997369
Short name T1727
Test name
Test status
Simulation time 3395815911 ps
CPU time 4.37 seconds
Started Jul 13 07:15:57 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 207168 kb
Host smart-6c93d2da-8c1e-49a5-a0ae-b98cfdd14efd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3578997369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3578997369
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2186014154
Short name T2336
Test name
Test status
Simulation time 13327323420 ps
CPU time 13.16 seconds
Started Jul 13 07:16:02 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 207076 kb
Host smart-22414d82-3de9-4a27-92ee-6a8c52aa8b4b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2186014154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2186014154
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2964184475
Short name T552
Test name
Test status
Simulation time 23324597936 ps
CPU time 24.09 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:25 PM PDT 24
Peak memory 207092 kb
Host smart-336d33b2-73ee-4c04-94cb-064f1f1205c6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2964184475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.2964184475
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3324283546
Short name T1241
Test name
Test status
Simulation time 156032172 ps
CPU time 0.8 seconds
Started Jul 13 07:15:55 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 206756 kb
Host smart-67e03409-3583-4175-861f-33a34d1d23c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242
83546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3324283546
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.263808146
Short name T1056
Test name
Test status
Simulation time 187214382 ps
CPU time 0.82 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206900 kb
Host smart-ac7b8936-0507-4fcc-a19c-8b8214c76f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26380
8146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.263808146
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3703113911
Short name T102
Test name
Test status
Simulation time 319502467 ps
CPU time 1.19 seconds
Started Jul 13 07:15:57 PM PDT 24
Finished Jul 13 07:15:59 PM PDT 24
Peak memory 207104 kb
Host smart-92d528b3-fe44-486b-92e9-4db19bc87c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
13911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3703113911
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2420478755
Short name T1975
Test name
Test status
Simulation time 1053880857 ps
CPU time 2.54 seconds
Started Jul 13 07:15:53 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 207064 kb
Host smart-bf6534b6-8be4-4ea3-8a12-af74e6b0449a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24204
78755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2420478755
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.4287141594
Short name T2081
Test name
Test status
Simulation time 21256442541 ps
CPU time 40.41 seconds
Started Jul 13 07:15:58 PM PDT 24
Finished Jul 13 07:16:39 PM PDT 24
Peak memory 207084 kb
Host smart-15ab1b1b-94aa-4c60-9f1b-3352f8f58349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42871
41594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.4287141594
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.1120544746
Short name T1436
Test name
Test status
Simulation time 153956779 ps
CPU time 0.83 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:01 PM PDT 24
Peak memory 206876 kb
Host smart-c22e71e3-a0eb-48b2-b3d6-6d4c6c6ef6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11205
44746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.1120544746
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2665695291
Short name T2461
Test name
Test status
Simulation time 388145105 ps
CPU time 1.15 seconds
Started Jul 13 07:15:54 PM PDT 24
Finished Jul 13 07:15:56 PM PDT 24
Peak memory 206808 kb
Host smart-594ad65a-1a0d-4e04-a520-65d25d25f611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26656
95291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2665695291
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3673518746
Short name T1207
Test name
Test status
Simulation time 147352286 ps
CPU time 0.78 seconds
Started Jul 13 07:15:58 PM PDT 24
Finished Jul 13 07:16:00 PM PDT 24
Peak memory 206860 kb
Host smart-f2777576-0ed5-4567-9361-1561f5713aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36735
18746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3673518746
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.321967194
Short name T793
Test name
Test status
Simulation time 55295684 ps
CPU time 0.72 seconds
Started Jul 13 07:15:54 PM PDT 24
Finished Jul 13 07:15:56 PM PDT 24
Peak memory 206840 kb
Host smart-9e7c0af3-b02d-4acd-b88d-2dc711c90290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32196
7194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.321967194
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.1522000506
Short name T1645
Test name
Test status
Simulation time 928665917 ps
CPU time 2.22 seconds
Started Jul 13 07:16:02 PM PDT 24
Finished Jul 13 07:16:06 PM PDT 24
Peak memory 207080 kb
Host smart-3436b1c4-6e6d-4d89-9b3e-15cb3355dc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15220
00506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.1522000506
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1358941534
Short name T550
Test name
Test status
Simulation time 246699762 ps
CPU time 1.77 seconds
Started Jul 13 07:15:53 PM PDT 24
Finished Jul 13 07:15:55 PM PDT 24
Peak memory 207072 kb
Host smart-24745a3e-eb7d-4485-b902-06108808a785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13589
41534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1358941534
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.784227595
Short name T2322
Test name
Test status
Simulation time 211717887 ps
CPU time 0.93 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:02 PM PDT 24
Peak memory 206892 kb
Host smart-2d70bf7c-d949-4a7d-a6e5-5fdab154b02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78422
7595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.784227595
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.603246766
Short name T1770
Test name
Test status
Simulation time 150115548 ps
CPU time 0.82 seconds
Started Jul 13 07:15:55 PM PDT 24
Finished Jul 13 07:15:57 PM PDT 24
Peak memory 206848 kb
Host smart-81ed97c5-3854-44fe-a37c-3dced81201da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60324
6766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.603246766
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2844363298
Short name T2151
Test name
Test status
Simulation time 233208438 ps
CPU time 0.9 seconds
Started Jul 13 07:15:53 PM PDT 24
Finished Jul 13 07:15:55 PM PDT 24
Peak memory 206880 kb
Host smart-e0a93b98-4d7a-43a0-971e-75f0712be763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28443
63298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2844363298
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2344348634
Short name T2118
Test name
Test status
Simulation time 5762798867 ps
CPU time 167.38 seconds
Started Jul 13 07:15:52 PM PDT 24
Finished Jul 13 07:18:40 PM PDT 24
Peak memory 207084 kb
Host smart-b9b690da-02ea-4073-9c8c-6d469938c5dd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2344348634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2344348634
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.2645554508
Short name T2741
Test name
Test status
Simulation time 3558128702 ps
CPU time 28.49 seconds
Started Jul 13 07:15:57 PM PDT 24
Finished Jul 13 07:16:26 PM PDT 24
Peak memory 207368 kb
Host smart-f62c9996-d859-46f6-a530-5edc12596ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26455
54508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2645554508
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.375249918
Short name T2359
Test name
Test status
Simulation time 220272378 ps
CPU time 0.93 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206884 kb
Host smart-70b31a21-0edd-484b-825b-ed50ed72083b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37524
9918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.375249918
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.2824989212
Short name T1400
Test name
Test status
Simulation time 23308571612 ps
CPU time 26.12 seconds
Started Jul 13 07:15:56 PM PDT 24
Finished Jul 13 07:16:23 PM PDT 24
Peak memory 206940 kb
Host smart-237d3b1d-3555-4908-9db9-76c41e7d5a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
89212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2824989212
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.4250335459
Short name T2684
Test name
Test status
Simulation time 3325681474 ps
CPU time 4.24 seconds
Started Jul 13 07:15:55 PM PDT 24
Finished Jul 13 07:16:01 PM PDT 24
Peak memory 206924 kb
Host smart-5be34835-64c9-4992-9717-e2ca68d57a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42503
35459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.4250335459
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1461742288
Short name T1345
Test name
Test status
Simulation time 11639245504 ps
CPU time 114.35 seconds
Started Jul 13 07:15:54 PM PDT 24
Finished Jul 13 07:17:49 PM PDT 24
Peak memory 207136 kb
Host smart-051168ee-f38b-45b8-90b0-24c0800bd822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14617
42288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1461742288
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3969814202
Short name T712
Test name
Test status
Simulation time 6777239789 ps
CPU time 191.78 seconds
Started Jul 13 07:16:04 PM PDT 24
Finished Jul 13 07:19:17 PM PDT 24
Peak memory 207104 kb
Host smart-d406b14a-2493-439b-8d2d-31f01c3d5cde
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3969814202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3969814202
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.4003368432
Short name T1213
Test name
Test status
Simulation time 235208447 ps
CPU time 0.97 seconds
Started Jul 13 07:16:05 PM PDT 24
Finished Jul 13 07:16:07 PM PDT 24
Peak memory 206868 kb
Host smart-10f8629e-3768-4311-b31b-4209f5c4cc9d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4003368432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.4003368432
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1239677443
Short name T818
Test name
Test status
Simulation time 190552751 ps
CPU time 0.89 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:01 PM PDT 24
Peak memory 206804 kb
Host smart-c203f737-e438-414e-b2ef-7cb7f1e8c73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12396
77443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1239677443
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.3219598495
Short name T401
Test name
Test status
Simulation time 4748210143 ps
CPU time 132.54 seconds
Started Jul 13 07:16:01 PM PDT 24
Finished Jul 13 07:18:15 PM PDT 24
Peak memory 207068 kb
Host smart-fae7a070-dc52-416e-be52-5307ae0f3076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
98495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.3219598495
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.3011873513
Short name T1912
Test name
Test status
Simulation time 7931387957 ps
CPU time 54.18 seconds
Started Jul 13 07:16:02 PM PDT 24
Finished Jul 13 07:16:57 PM PDT 24
Peak memory 207140 kb
Host smart-068c1008-9f2b-4559-ac9b-5327c668a8fc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3011873513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.3011873513
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3030699576
Short name T737
Test name
Test status
Simulation time 189506827 ps
CPU time 0.85 seconds
Started Jul 13 07:16:02 PM PDT 24
Finished Jul 13 07:16:04 PM PDT 24
Peak memory 206872 kb
Host smart-e96cf72c-6dcc-4c47-8a49-aeb4e8075d4e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3030699576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3030699576
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2184194770
Short name T1608
Test name
Test status
Simulation time 151314046 ps
CPU time 0.75 seconds
Started Jul 13 07:15:58 PM PDT 24
Finished Jul 13 07:15:59 PM PDT 24
Peak memory 206860 kb
Host smart-0e12a070-c036-4b65-9d44-bf0600f3d276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21841
94770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2184194770
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1584152566
Short name T121
Test name
Test status
Simulation time 195369939 ps
CPU time 0.85 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206868 kb
Host smart-61b05cc8-6c61-4a1e-9b3c-e5d1208da709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15841
52566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1584152566
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2903265940
Short name T2170
Test name
Test status
Simulation time 178513823 ps
CPU time 0.85 seconds
Started Jul 13 07:16:09 PM PDT 24
Finished Jul 13 07:16:10 PM PDT 24
Peak memory 206876 kb
Host smart-de06ee77-657e-41bf-8166-b758304d92ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29032
65940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2903265940
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3087991093
Short name T602
Test name
Test status
Simulation time 154688426 ps
CPU time 0.8 seconds
Started Jul 13 07:16:06 PM PDT 24
Finished Jul 13 07:16:07 PM PDT 24
Peak memory 206812 kb
Host smart-29e3f9e8-7de4-47d0-bb5e-d914c02669f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
91093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3087991093
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1115572777
Short name T2274
Test name
Test status
Simulation time 160902121 ps
CPU time 0.85 seconds
Started Jul 13 07:16:05 PM PDT 24
Finished Jul 13 07:16:06 PM PDT 24
Peak memory 206824 kb
Host smart-59cd94ec-4e54-48cd-a294-05c1cee03227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11155
72777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1115572777
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1316816370
Short name T1868
Test name
Test status
Simulation time 146293292 ps
CPU time 0.85 seconds
Started Jul 13 07:16:05 PM PDT 24
Finished Jul 13 07:16:06 PM PDT 24
Peak memory 206880 kb
Host smart-2ab30934-0c52-40d2-bf2c-1c3d919c13b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13168
16370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1316816370
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.4093549003
Short name T1447
Test name
Test status
Simulation time 213569731 ps
CPU time 0.99 seconds
Started Jul 13 07:16:04 PM PDT 24
Finished Jul 13 07:16:06 PM PDT 24
Peak memory 206876 kb
Host smart-4cf2ad02-25d3-40c8-801b-467880170fb3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4093549003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.4093549003
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.208235408
Short name T22
Test name
Test status
Simulation time 164397265 ps
CPU time 0.86 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206868 kb
Host smart-63fcd7d6-4f35-4b46-9556-4d9d796ef12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20823
5408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.208235408
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3163228387
Short name T1253
Test name
Test status
Simulation time 59369488 ps
CPU time 0.76 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206860 kb
Host smart-96358336-6184-451c-864f-7ed4a25946b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31632
28387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3163228387
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2992935134
Short name T17
Test name
Test status
Simulation time 9229384181 ps
CPU time 22.5 seconds
Started Jul 13 07:16:06 PM PDT 24
Finished Jul 13 07:16:29 PM PDT 24
Peak memory 207160 kb
Host smart-55f28c0d-afab-4b9d-866e-3a1525c71808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29929
35134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2992935134
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.4122403372
Short name T2308
Test name
Test status
Simulation time 231094357 ps
CPU time 0.88 seconds
Started Jul 13 07:16:02 PM PDT 24
Finished Jul 13 07:16:04 PM PDT 24
Peak memory 206876 kb
Host smart-09f65f45-2b84-41ae-8cef-25e7cd9e9c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41224
03372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.4122403372
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.782055879
Short name T1758
Test name
Test status
Simulation time 215767209 ps
CPU time 0.96 seconds
Started Jul 13 07:16:04 PM PDT 24
Finished Jul 13 07:16:06 PM PDT 24
Peak memory 206868 kb
Host smart-eb21831a-eacd-416f-8699-6c6aae2d2de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78205
5879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.782055879
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.4210146532
Short name T1014
Test name
Test status
Simulation time 202069567 ps
CPU time 0.88 seconds
Started Jul 13 07:16:09 PM PDT 24
Finished Jul 13 07:16:11 PM PDT 24
Peak memory 206888 kb
Host smart-c1db4abd-5812-46c9-b1c8-c0dc0aadf3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42101
46532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.4210146532
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1361025103
Short name T657
Test name
Test status
Simulation time 194095709 ps
CPU time 0.84 seconds
Started Jul 13 07:16:08 PM PDT 24
Finished Jul 13 07:16:09 PM PDT 24
Peak memory 206904 kb
Host smart-6ec14398-c72d-49fc-a9f2-3a3b8af51750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13610
25103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1361025103
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.4184740388
Short name T1274
Test name
Test status
Simulation time 145308860 ps
CPU time 0.79 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:02 PM PDT 24
Peak memory 206860 kb
Host smart-f5df7e96-7bf6-4f00-88fc-5fd7fe6aaaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41847
40388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.4184740388
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2241157357
Short name T2604
Test name
Test status
Simulation time 149878166 ps
CPU time 0.83 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206856 kb
Host smart-878d6a74-fbc3-43d2-b135-c5c09fca8ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22411
57357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2241157357
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.380375631
Short name T1717
Test name
Test status
Simulation time 217458355 ps
CPU time 0.85 seconds
Started Jul 13 07:16:04 PM PDT 24
Finished Jul 13 07:16:06 PM PDT 24
Peak memory 206856 kb
Host smart-700519b7-8c82-42cc-aa95-bd68e1d207cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38037
5631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.380375631
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1066710421
Short name T2320
Test name
Test status
Simulation time 220759457 ps
CPU time 0.95 seconds
Started Jul 13 07:16:09 PM PDT 24
Finished Jul 13 07:16:10 PM PDT 24
Peak memory 206828 kb
Host smart-08dfbf26-59b4-40f1-bc33-7bdc69f33fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10667
10421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1066710421
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2644241013
Short name T1553
Test name
Test status
Simulation time 6128922977 ps
CPU time 169.39 seconds
Started Jul 13 07:16:04 PM PDT 24
Finished Jul 13 07:18:54 PM PDT 24
Peak memory 207064 kb
Host smart-35796d23-23b0-4687-99f7-bab9df234b23
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2644241013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2644241013
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.264045203
Short name T2401
Test name
Test status
Simulation time 163383365 ps
CPU time 0.8 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206864 kb
Host smart-1dab5477-8f74-41d7-9a46-933a7aee36b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404
5203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.264045203
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1332849434
Short name T2725
Test name
Test status
Simulation time 223241897 ps
CPU time 0.9 seconds
Started Jul 13 07:15:59 PM PDT 24
Finished Jul 13 07:16:02 PM PDT 24
Peak memory 206876 kb
Host smart-176095f4-3401-47d1-b0c6-105d981c8875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13328
49434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1332849434
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3077395673
Short name T330
Test name
Test status
Simulation time 370894832 ps
CPU time 1.17 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:03 PM PDT 24
Peak memory 206864 kb
Host smart-603805b0-3e05-4895-af76-2c95f53e425e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773
95673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3077395673
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3500075640
Short name T2333
Test name
Test status
Simulation time 3305140208 ps
CPU time 32.62 seconds
Started Jul 13 07:16:06 PM PDT 24
Finished Jul 13 07:16:39 PM PDT 24
Peak memory 207132 kb
Host smart-60a68fb5-6885-4d52-a687-79c0e43e7ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35000
75640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3500075640
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.418495381
Short name T863
Test name
Test status
Simulation time 62239029 ps
CPU time 0.7 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:16 PM PDT 24
Peak memory 206936 kb
Host smart-ab7248d5-439e-4758-9496-b2225f575896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=418495381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.418495381
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3949218116
Short name T1634
Test name
Test status
Simulation time 3714824712 ps
CPU time 4.87 seconds
Started Jul 13 07:16:09 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 207024 kb
Host smart-2bfaaeec-6949-412c-81fb-d934cafd6c00
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3949218116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3949218116
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.42308324
Short name T1783
Test name
Test status
Simulation time 13313347154 ps
CPU time 11.97 seconds
Started Jul 13 07:16:01 PM PDT 24
Finished Jul 13 07:16:15 PM PDT 24
Peak memory 206936 kb
Host smart-a6ddefc2-9114-4e0f-80ba-323958ad374d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=42308324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.42308324
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1579779777
Short name T600
Test name
Test status
Simulation time 23337079617 ps
CPU time 24.15 seconds
Started Jul 13 07:16:00 PM PDT 24
Finished Jul 13 07:16:26 PM PDT 24
Peak memory 206880 kb
Host smart-462dc739-8b96-46d3-b4a6-5f48ef5d5166
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1579779777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.1579779777
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2696587486
Short name T715
Test name
Test status
Simulation time 201556156 ps
CPU time 0.86 seconds
Started Jul 13 07:16:01 PM PDT 24
Finished Jul 13 07:16:04 PM PDT 24
Peak memory 206868 kb
Host smart-d52298f4-e175-4b85-a5e5-51df4609aa38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26965
87486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2696587486
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2662254556
Short name T1234
Test name
Test status
Simulation time 155471676 ps
CPU time 0.79 seconds
Started Jul 13 07:16:02 PM PDT 24
Finished Jul 13 07:16:04 PM PDT 24
Peak memory 206868 kb
Host smart-76ce3223-1c98-4157-b023-62aa081e8814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26622
54556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2662254556
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3600363006
Short name T1647
Test name
Test status
Simulation time 402372518 ps
CPU time 1.34 seconds
Started Jul 13 07:16:07 PM PDT 24
Finished Jul 13 07:16:09 PM PDT 24
Peak memory 206864 kb
Host smart-4bec5f90-e906-4f2d-9aa2-8e52a1573c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36003
63006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3600363006
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1138182213
Short name T1090
Test name
Test status
Simulation time 733897734 ps
CPU time 1.75 seconds
Started Jul 13 07:16:07 PM PDT 24
Finished Jul 13 07:16:09 PM PDT 24
Peak memory 207008 kb
Host smart-b28836a4-effc-40e3-83e5-01fd61c99a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11381
82213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1138182213
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.4293374787
Short name T1142
Test name
Test status
Simulation time 9051377225 ps
CPU time 16.21 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:30 PM PDT 24
Peak memory 207080 kb
Host smart-0034723f-4c5c-4634-b014-d3b8bd055464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42933
74787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.4293374787
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2503185405
Short name T2429
Test name
Test status
Simulation time 488959793 ps
CPU time 1.45 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 206892 kb
Host smart-595b5549-828f-4ca4-be58-8965b471cba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25031
85405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2503185405
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.459187155
Short name T1562
Test name
Test status
Simulation time 159058367 ps
CPU time 0.76 seconds
Started Jul 13 07:16:10 PM PDT 24
Finished Jul 13 07:16:11 PM PDT 24
Peak memory 206844 kb
Host smart-a67ac8d6-445e-4eaf-885b-d54358dbe0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45918
7155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.459187155
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3752973428
Short name T925
Test name
Test status
Simulation time 44091164 ps
CPU time 0.7 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 206864 kb
Host smart-d3841d62-3c20-4ad6-ab73-f3faa057602b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37529
73428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3752973428
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.100398255
Short name T2491
Test name
Test status
Simulation time 991154632 ps
CPU time 2.47 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:16 PM PDT 24
Peak memory 207068 kb
Host smart-394daf35-ac23-46f0-9bad-b21cb279b645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10039
8255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.100398255
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2454671017
Short name T1351
Test name
Test status
Simulation time 299874541 ps
CPU time 1.95 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 206964 kb
Host smart-bb1b42e9-ceb4-4d71-bd93-517d2e954c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24546
71017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2454671017
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3375675837
Short name T887
Test name
Test status
Simulation time 188959281 ps
CPU time 0.84 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 206872 kb
Host smart-6b00c026-5ddb-4401-b9dd-508764d6190b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33756
75837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3375675837
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1230348891
Short name T310
Test name
Test status
Simulation time 135230623 ps
CPU time 0.74 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 206748 kb
Host smart-26b47909-281a-4fbe-9aa3-3c2602efd682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12303
48891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1230348891
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3041206155
Short name T1911
Test name
Test status
Simulation time 180092356 ps
CPU time 0.88 seconds
Started Jul 13 07:16:16 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 207108 kb
Host smart-9c0622ff-58c8-4c96-b61a-d5083ac473fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30412
06155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3041206155
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.243466264
Short name T1815
Test name
Test status
Simulation time 13162483205 ps
CPU time 115.29 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:18:08 PM PDT 24
Peak memory 207076 kb
Host smart-0f3d8fb3-3dd8-46a6-b1b4-dd4d6b46a594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24346
6264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.243466264
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1593103707
Short name T1216
Test name
Test status
Simulation time 217029150 ps
CPU time 0.89 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 206864 kb
Host smart-bf31647a-ab55-425c-99a1-d67227b4b54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15931
03707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1593103707
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1594049345
Short name T350
Test name
Test status
Simulation time 23272225074 ps
CPU time 26.41 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:16:43 PM PDT 24
Peak memory 206908 kb
Host smart-2961f57b-3987-42f8-b324-2e6907a581de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15940
49345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1594049345
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.98936818
Short name T1484
Test name
Test status
Simulation time 3335809949 ps
CPU time 4.52 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 206944 kb
Host smart-d9d9f798-43b9-43e0-8f4e-209abf1a50db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98936
818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.98936818
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2958805267
Short name T1325
Test name
Test status
Simulation time 8383855240 ps
CPU time 59.88 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:17:17 PM PDT 24
Peak memory 207136 kb
Host smart-cdc7854f-3c77-4deb-8930-79b6be2eddbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29588
05267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2958805267
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1113031079
Short name T831
Test name
Test status
Simulation time 4816266668 ps
CPU time 47.86 seconds
Started Jul 13 07:16:11 PM PDT 24
Finished Jul 13 07:16:59 PM PDT 24
Peak memory 207080 kb
Host smart-c60a5737-3744-445c-8730-5b98ab413090
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1113031079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1113031079
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.98072382
Short name T198
Test name
Test status
Simulation time 247565382 ps
CPU time 0.97 seconds
Started Jul 13 07:16:18 PM PDT 24
Finished Jul 13 07:16:21 PM PDT 24
Peak memory 206816 kb
Host smart-29c6b4b6-f65e-42e6-b4fd-276b2109da3f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=98072382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.98072382
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2962114848
Short name T2673
Test name
Test status
Simulation time 205149871 ps
CPU time 0.93 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:15 PM PDT 24
Peak memory 206868 kb
Host smart-355a517b-c866-40c6-aec8-c0de656cd7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29621
14848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2962114848
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3202068068
Short name T450
Test name
Test status
Simulation time 6311433208 ps
CPU time 60.81 seconds
Started Jul 13 07:16:17 PM PDT 24
Finished Jul 13 07:17:20 PM PDT 24
Peak memory 207076 kb
Host smart-6d0cd370-1376-45ab-aef8-105379f17fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32020
68068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3202068068
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2423246294
Short name T278
Test name
Test status
Simulation time 3974952959 ps
CPU time 37.27 seconds
Started Jul 13 07:16:15 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 207148 kb
Host smart-9459d298-ae66-478b-9946-7e2684c9b5fa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2423246294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2423246294
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1270108579
Short name T549
Test name
Test status
Simulation time 180262311 ps
CPU time 0.83 seconds
Started Jul 13 07:16:16 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 207080 kb
Host smart-88cb847f-1884-4e14-b2ef-d5821a972209
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1270108579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1270108579
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.501251028
Short name T1511
Test name
Test status
Simulation time 194166746 ps
CPU time 0.8 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:15 PM PDT 24
Peak memory 206912 kb
Host smart-712dd2d9-bae5-42fb-8ec7-919d378c22c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50125
1028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.501251028
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2208843907
Short name T125
Test name
Test status
Simulation time 275141313 ps
CPU time 0.98 seconds
Started Jul 13 07:16:18 PM PDT 24
Finished Jul 13 07:16:21 PM PDT 24
Peak memory 206816 kb
Host smart-21a6bd4c-6ae9-453e-8bfc-7a98745a2976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22088
43907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2208843907
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2819985405
Short name T1117
Test name
Test status
Simulation time 186146226 ps
CPU time 0.88 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 206864 kb
Host smart-97b6fc72-d351-467c-94eb-d2eba61ba149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28199
85405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2819985405
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.475994112
Short name T1327
Test name
Test status
Simulation time 196694584 ps
CPU time 0.81 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 206880 kb
Host smart-b3734416-bf89-4b4d-8423-20dcbe25048b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47599
4112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.475994112
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2175100723
Short name T2505
Test name
Test status
Simulation time 189645168 ps
CPU time 0.83 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:15 PM PDT 24
Peak memory 206872 kb
Host smart-1d222c12-c917-40d6-92be-441ffecd547f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21751
00723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2175100723
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2424853051
Short name T2192
Test name
Test status
Simulation time 165863077 ps
CPU time 0.8 seconds
Started Jul 13 07:16:11 PM PDT 24
Finished Jul 13 07:16:13 PM PDT 24
Peak memory 206880 kb
Host smart-4b05c03c-f390-4869-abb5-7095ebbd225a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24248
53051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2424853051
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2091381683
Short name T500
Test name
Test status
Simulation time 218515363 ps
CPU time 0.94 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:16 PM PDT 24
Peak memory 206868 kb
Host smart-9274e386-9113-48e0-87b2-60376b9b179e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2091381683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2091381683
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3159205966
Short name T1668
Test name
Test status
Simulation time 150460371 ps
CPU time 0.83 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:16 PM PDT 24
Peak memory 206864 kb
Host smart-c2851430-85b8-4952-92bb-91ade07e867f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31592
05966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3159205966
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.4228834670
Short name T1125
Test name
Test status
Simulation time 44035139 ps
CPU time 0.67 seconds
Started Jul 13 07:16:17 PM PDT 24
Finished Jul 13 07:16:20 PM PDT 24
Peak memory 206876 kb
Host smart-972b2d8e-ae79-43a3-9cf2-c7afc62694cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42288
34670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.4228834670
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2000545851
Short name T620
Test name
Test status
Simulation time 6556492449 ps
CPU time 14.09 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:16:30 PM PDT 24
Peak memory 207116 kb
Host smart-c3e784ad-b20d-4bcb-aac2-025dc87e32a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
45851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2000545851
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.60170524
Short name T1221
Test name
Test status
Simulation time 159811602 ps
CPU time 0.91 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 206872 kb
Host smart-4da45546-dd52-418b-8ac2-460467b83197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60170
524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.60170524
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.4207522177
Short name T2276
Test name
Test status
Simulation time 196713271 ps
CPU time 0.85 seconds
Started Jul 13 07:16:15 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 206880 kb
Host smart-d461e653-349d-4f42-9c0b-f9a168a4c382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42075
22177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.4207522177
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.2210376075
Short name T1526
Test name
Test status
Simulation time 255527138 ps
CPU time 0.92 seconds
Started Jul 13 07:16:13 PM PDT 24
Finished Jul 13 07:16:15 PM PDT 24
Peak memory 206864 kb
Host smart-aa9742f0-8986-4f18-9f99-6f2aeedb2cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22103
76075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.2210376075
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1219947501
Short name T1750
Test name
Test status
Simulation time 174006457 ps
CPU time 0.89 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 206852 kb
Host smart-2c3676e6-39d4-4fa2-a065-02aecf7b9379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12199
47501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1219947501
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.3231274448
Short name T2643
Test name
Test status
Simulation time 169789960 ps
CPU time 0.79 seconds
Started Jul 13 07:16:15 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 206860 kb
Host smart-24752cf2-2135-48dd-9da4-ac6c31bfba06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32312
74448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.3231274448
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1337969994
Short name T1613
Test name
Test status
Simulation time 163031437 ps
CPU time 0.84 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 206840 kb
Host smart-83b9cbe4-3355-4433-bbd2-db007ba02edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13379
69994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1337969994
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1882845713
Short name T398
Test name
Test status
Simulation time 152004446 ps
CPU time 0.8 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:15 PM PDT 24
Peak memory 206804 kb
Host smart-0ea0eb0d-3939-401a-86da-f8fb47de2a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18828
45713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1882845713
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.956188209
Short name T1814
Test name
Test status
Simulation time 201377187 ps
CPU time 0.98 seconds
Started Jul 13 07:16:15 PM PDT 24
Finished Jul 13 07:16:18 PM PDT 24
Peak memory 206864 kb
Host smart-cf565607-39ac-42de-9172-5ff041a23fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95618
8209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.956188209
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3858597610
Short name T744
Test name
Test status
Simulation time 5880108026 ps
CPU time 167.03 seconds
Started Jul 13 07:16:11 PM PDT 24
Finished Jul 13 07:18:59 PM PDT 24
Peak memory 207056 kb
Host smart-8f15d666-d347-4b62-8a45-e6f9fc554679
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3858597610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3858597610
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2668274553
Short name T1469
Test name
Test status
Simulation time 174539390 ps
CPU time 0.83 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:16:17 PM PDT 24
Peak memory 206760 kb
Host smart-300a1bd3-ea88-44c9-9935-0916d628a376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26682
74553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2668274553
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.385171132
Short name T2328
Test name
Test status
Simulation time 199382957 ps
CPU time 0.84 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 206860 kb
Host smart-eac7a043-930c-46ca-b768-9ca13e3da4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
1132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.385171132
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.2530963672
Short name T2469
Test name
Test status
Simulation time 258441704 ps
CPU time 0.92 seconds
Started Jul 13 07:16:12 PM PDT 24
Finished Jul 13 07:16:14 PM PDT 24
Peak memory 206868 kb
Host smart-2160ff1c-bec2-4a19-9b4f-926bdd350780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25309
63672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2530963672
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2501922942
Short name T461
Test name
Test status
Simulation time 4535507584 ps
CPU time 43 seconds
Started Jul 13 07:16:14 PM PDT 24
Finished Jul 13 07:17:04 PM PDT 24
Peak memory 207136 kb
Host smart-6c00a72a-12a4-485f-a7dd-6f997df4262c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25019
22942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2501922942
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3682509823
Short name T2737
Test name
Test status
Simulation time 96374619 ps
CPU time 0.76 seconds
Started Jul 13 07:16:23 PM PDT 24
Finished Jul 13 07:16:26 PM PDT 24
Peak memory 206908 kb
Host smart-04456ab5-73c7-4ca9-b7bf-492f7b994c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3682509823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3682509823
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3945052782
Short name T2041
Test name
Test status
Simulation time 4238628630 ps
CPU time 4.87 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206924 kb
Host smart-f7809893-9294-44b5-9d29-c6dbcf651ecf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3945052782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3945052782
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.4004497254
Short name T954
Test name
Test status
Simulation time 13361497461 ps
CPU time 13.45 seconds
Started Jul 13 07:16:19 PM PDT 24
Finished Jul 13 07:16:34 PM PDT 24
Peak memory 206912 kb
Host smart-68627344-7835-48bf-8271-acbb4130ff47
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4004497254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.4004497254
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.167853343
Short name T9
Test name
Test status
Simulation time 23426704673 ps
CPU time 22.37 seconds
Started Jul 13 07:16:21 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206868 kb
Host smart-9255ad39-e374-4ce4-a855-6b41bf06231c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=167853343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.167853343
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2062112191
Short name T2217
Test name
Test status
Simulation time 153009242 ps
CPU time 0.79 seconds
Started Jul 13 07:16:36 PM PDT 24
Finished Jul 13 07:16:37 PM PDT 24
Peak memory 206864 kb
Host smart-66a6eedd-055d-4e57-80ed-997c87af0435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20621
12191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2062112191
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.4115199479
Short name T1181
Test name
Test status
Simulation time 139631581 ps
CPU time 0.8 seconds
Started Jul 13 07:16:20 PM PDT 24
Finished Jul 13 07:16:23 PM PDT 24
Peak memory 206860 kb
Host smart-227b52de-b965-4363-9470-c4ac4e7a8d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41151
99479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.4115199479
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.726946232
Short name T2154
Test name
Test status
Simulation time 348525574 ps
CPU time 1.22 seconds
Started Jul 13 07:16:20 PM PDT 24
Finished Jul 13 07:16:23 PM PDT 24
Peak memory 206872 kb
Host smart-e653e51d-f1bc-497a-9790-7b0510fc6024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72694
6232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.726946232
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1693999062
Short name T763
Test name
Test status
Simulation time 706797813 ps
CPU time 1.94 seconds
Started Jul 13 07:16:19 PM PDT 24
Finished Jul 13 07:16:22 PM PDT 24
Peak memory 207012 kb
Host smart-a027d7e6-bdd2-4d1a-8ce6-c191ff999133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16939
99062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1693999062
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1915028066
Short name T665
Test name
Test status
Simulation time 15573610085 ps
CPU time 27.46 seconds
Started Jul 13 07:16:23 PM PDT 24
Finished Jul 13 07:16:52 PM PDT 24
Peak memory 207088 kb
Host smart-afe3b261-9501-411d-9b50-a20ff9cdd448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19150
28066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1915028066
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3711927263
Short name T699
Test name
Test status
Simulation time 406671172 ps
CPU time 1.29 seconds
Started Jul 13 07:16:24 PM PDT 24
Finished Jul 13 07:16:27 PM PDT 24
Peak memory 206840 kb
Host smart-da1b7d0b-36d8-4cac-bf66-33c3ccfc83dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37119
27263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3711927263
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1917124750
Short name T2652
Test name
Test status
Simulation time 199863611 ps
CPU time 0.81 seconds
Started Jul 13 07:16:23 PM PDT 24
Finished Jul 13 07:16:26 PM PDT 24
Peak memory 206880 kb
Host smart-54ac1c3b-d553-4c4c-a16c-a21740f6b939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19171
24750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1917124750
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2339811017
Short name T556
Test name
Test status
Simulation time 33966023 ps
CPU time 0.64 seconds
Started Jul 13 07:16:20 PM PDT 24
Finished Jul 13 07:16:22 PM PDT 24
Peak memory 206836 kb
Host smart-0734c172-5592-4705-9686-31e858a41d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23398
11017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2339811017
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.432740889
Short name T1180
Test name
Test status
Simulation time 883657560 ps
CPU time 1.94 seconds
Started Jul 13 07:16:18 PM PDT 24
Finished Jul 13 07:16:22 PM PDT 24
Peak memory 207024 kb
Host smart-18b6763a-38b8-4a42-9e04-995d4e5245e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43274
0889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.432740889
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.4548463
Short name T164
Test name
Test status
Simulation time 174184999 ps
CPU time 1.72 seconds
Started Jul 13 07:16:23 PM PDT 24
Finished Jul 13 07:16:27 PM PDT 24
Peak memory 206984 kb
Host smart-fc1abf39-0d8c-4999-91f3-d0948c6979dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45484
63 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.4548463
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1762526810
Short name T2059
Test name
Test status
Simulation time 242783468 ps
CPU time 0.86 seconds
Started Jul 13 07:16:37 PM PDT 24
Finished Jul 13 07:16:39 PM PDT 24
Peak memory 206820 kb
Host smart-fbad0415-e192-4f50-99ef-2007db8db18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17625
26810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1762526810
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.638129211
Short name T1984
Test name
Test status
Simulation time 175151350 ps
CPU time 0.84 seconds
Started Jul 13 07:16:38 PM PDT 24
Finished Jul 13 07:16:40 PM PDT 24
Peak memory 206640 kb
Host smart-36272f1a-00e7-406c-b219-8fa5f512d259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63812
9211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.638129211
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2611941644
Short name T1990
Test name
Test status
Simulation time 210394830 ps
CPU time 0.86 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:16:36 PM PDT 24
Peak memory 206864 kb
Host smart-e2c8793b-6aac-49ad-9161-463e86774fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26119
41644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2611941644
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1850277390
Short name T1636
Test name
Test status
Simulation time 6919278844 ps
CPU time 194.23 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:19:54 PM PDT 24
Peak memory 207100 kb
Host smart-0666bb17-68b1-4549-bff1-35f086d28510
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1850277390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1850277390
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.2293199468
Short name T2297
Test name
Test status
Simulation time 10352174968 ps
CPU time 80.03 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:18:11 PM PDT 24
Peak memory 206912 kb
Host smart-eac027ea-4e45-41cd-9952-abd9dd3c83a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22931
99468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.2293199468
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1958604291
Short name T865
Test name
Test status
Simulation time 164646057 ps
CPU time 0.88 seconds
Started Jul 13 07:16:25 PM PDT 24
Finished Jul 13 07:16:27 PM PDT 24
Peak memory 205808 kb
Host smart-2f0290db-c74f-49fa-ae5b-192736edff31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19586
04291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1958604291
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1893984037
Short name T468
Test name
Test status
Simulation time 23379469377 ps
CPU time 24.45 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:16:48 PM PDT 24
Peak memory 206948 kb
Host smart-33d16fca-590c-473d-94a4-564f885a9fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18939
84037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1893984037
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3504009867
Short name T610
Test name
Test status
Simulation time 3299354434 ps
CPU time 3.87 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:16:28 PM PDT 24
Peak memory 206956 kb
Host smart-331ed80f-690a-42f9-a7b6-13fda66305f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35040
09867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3504009867
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2580588600
Short name T2312
Test name
Test status
Simulation time 11177435364 ps
CPU time 312.18 seconds
Started Jul 13 07:16:24 PM PDT 24
Finished Jul 13 07:21:39 PM PDT 24
Peak memory 207352 kb
Host smart-9c112667-f958-44c2-9409-e5424751ca92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25805
88600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2580588600
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3007662208
Short name T2540
Test name
Test status
Simulation time 5417363829 ps
CPU time 145.26 seconds
Started Jul 13 07:16:21 PM PDT 24
Finished Jul 13 07:18:48 PM PDT 24
Peak memory 207080 kb
Host smart-35a870b9-de09-40ad-9b80-b7caa8927084
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3007662208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3007662208
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.626230258
Short name T1784
Test name
Test status
Simulation time 294438060 ps
CPU time 0.93 seconds
Started Jul 13 07:16:25 PM PDT 24
Finished Jul 13 07:16:28 PM PDT 24
Peak memory 206868 kb
Host smart-41d59859-d65f-4118-b8b1-6b0d916c0dab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=626230258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.626230258
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3881582782
Short name T1093
Test name
Test status
Simulation time 205404820 ps
CPU time 0.98 seconds
Started Jul 13 07:16:20 PM PDT 24
Finished Jul 13 07:16:22 PM PDT 24
Peak memory 206868 kb
Host smart-857b2f86-0250-4dad-a92a-2d3200882b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38815
82782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3881582782
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2308914653
Short name T5
Test name
Test status
Simulation time 3927530108 ps
CPU time 38.76 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:17:03 PM PDT 24
Peak memory 207072 kb
Host smart-7bc7c7bf-f710-491f-bb95-c05bdf9d9a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23089
14653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2308914653
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.2344241289
Short name T2387
Test name
Test status
Simulation time 5700510251 ps
CPU time 147.93 seconds
Started Jul 13 07:16:21 PM PDT 24
Finished Jul 13 07:18:50 PM PDT 24
Peak memory 207100 kb
Host smart-2e1646ff-ff27-4ece-bbef-a776a735757f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2344241289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2344241289
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2392875085
Short name T317
Test name
Test status
Simulation time 161139482 ps
CPU time 0.83 seconds
Started Jul 13 07:16:36 PM PDT 24
Finished Jul 13 07:16:38 PM PDT 24
Peak memory 206868 kb
Host smart-034f835f-9202-4e16-8ce9-39d4bb0bd106
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2392875085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2392875085
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1700445142
Short name T788
Test name
Test status
Simulation time 148017640 ps
CPU time 0.78 seconds
Started Jul 13 07:16:29 PM PDT 24
Finished Jul 13 07:16:31 PM PDT 24
Peak memory 206816 kb
Host smart-51869e8d-0a7d-4565-9ad7-bc024f8eca49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17004
45142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1700445142
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2613777710
Short name T1546
Test name
Test status
Simulation time 177876251 ps
CPU time 0.84 seconds
Started Jul 13 07:16:20 PM PDT 24
Finished Jul 13 07:16:23 PM PDT 24
Peak memory 206856 kb
Host smart-e9059d1c-c8b2-4c7c-a0d2-df35483e66eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
77710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2613777710
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3510083547
Short name T302
Test name
Test status
Simulation time 170589328 ps
CPU time 0.81 seconds
Started Jul 13 07:16:23 PM PDT 24
Finished Jul 13 07:16:25 PM PDT 24
Peak memory 206868 kb
Host smart-8e7c3fa1-410a-4734-ac77-3f2f8a840978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35100
83547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3510083547
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.751999471
Short name T1700
Test name
Test status
Simulation time 168735534 ps
CPU time 0.81 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:16:24 PM PDT 24
Peak memory 206868 kb
Host smart-eee5f5d2-c846-4869-9730-abb951f8b14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75199
9471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.751999471
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.500479409
Short name T1324
Test name
Test status
Simulation time 158121592 ps
CPU time 0.8 seconds
Started Jul 13 07:16:19 PM PDT 24
Finished Jul 13 07:16:21 PM PDT 24
Peak memory 206872 kb
Host smart-d73fbb8c-fe99-4563-8f11-8b13ed229a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50047
9409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.500479409
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.592361763
Short name T1131
Test name
Test status
Simulation time 204951666 ps
CPU time 0.9 seconds
Started Jul 13 07:16:19 PM PDT 24
Finished Jul 13 07:16:21 PM PDT 24
Peak memory 206880 kb
Host smart-bfc8b8ce-ec61-4c33-b447-c42c7cc88758
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=592361763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.592361763
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2798681648
Short name T780
Test name
Test status
Simulation time 144255031 ps
CPU time 0.77 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:40 PM PDT 24
Peak memory 206648 kb
Host smart-276763d9-2345-48a5-88bf-82c66298e2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27986
81648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2798681648
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1562418805
Short name T18
Test name
Test status
Simulation time 70330966 ps
CPU time 0.69 seconds
Started Jul 13 07:16:24 PM PDT 24
Finished Jul 13 07:16:27 PM PDT 24
Peak memory 207040 kb
Host smart-586d2829-3314-418f-949e-9062af336b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15624
18805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1562418805
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3255561424
Short name T2208
Test name
Test status
Simulation time 14501442252 ps
CPU time 33.99 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:17:20 PM PDT 24
Peak memory 206944 kb
Host smart-bb25cd8c-4cf3-405e-8594-b5482ca68de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32555
61424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3255561424
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2131678775
Short name T1079
Test name
Test status
Simulation time 205692518 ps
CPU time 0.86 seconds
Started Jul 13 07:16:20 PM PDT 24
Finished Jul 13 07:16:23 PM PDT 24
Peak memory 206892 kb
Host smart-56d79bee-79f9-4ed6-9afd-32150dd8d216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21316
78775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2131678775
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.4097691219
Short name T24
Test name
Test status
Simulation time 299894447 ps
CPU time 0.92 seconds
Started Jul 13 07:16:31 PM PDT 24
Finished Jul 13 07:16:33 PM PDT 24
Peak memory 206872 kb
Host smart-a1df42b8-e834-4332-b543-dcdf995c625f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40976
91219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4097691219
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.983176752
Short name T382
Test name
Test status
Simulation time 201471972 ps
CPU time 0.89 seconds
Started Jul 13 07:16:19 PM PDT 24
Finished Jul 13 07:16:22 PM PDT 24
Peak memory 206860 kb
Host smart-95ca99d9-743f-4257-ab39-2cb5d8c6e54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98317
6752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.983176752
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.780194444
Short name T542
Test name
Test status
Simulation time 176293238 ps
CPU time 0.89 seconds
Started Jul 13 07:16:30 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 206900 kb
Host smart-49333a76-09de-4082-8073-943407deb9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78019
4444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.780194444
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2071438402
Short name T2653
Test name
Test status
Simulation time 151895618 ps
CPU time 0.77 seconds
Started Jul 13 07:16:21 PM PDT 24
Finished Jul 13 07:16:23 PM PDT 24
Peak memory 206848 kb
Host smart-f925a841-07e1-4c95-a622-45773f4d7369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20714
38402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2071438402
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.214968822
Short name T1386
Test name
Test status
Simulation time 157800150 ps
CPU time 0.78 seconds
Started Jul 13 07:16:30 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 206868 kb
Host smart-9320ff10-f91f-43a7-a3d7-86cfe8ec5642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21496
8822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.214968822
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2780435563
Short name T2172
Test name
Test status
Simulation time 140880030 ps
CPU time 0.8 seconds
Started Jul 13 07:16:21 PM PDT 24
Finished Jul 13 07:16:23 PM PDT 24
Peak memory 206864 kb
Host smart-f8f1a08f-9e84-491b-95f7-7647b8154ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27804
35563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2780435563
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1530815827
Short name T1359
Test name
Test status
Simulation time 267258192 ps
CPU time 0.98 seconds
Started Jul 13 07:16:37 PM PDT 24
Finished Jul 13 07:16:38 PM PDT 24
Peak memory 206896 kb
Host smart-4058ecd2-2930-4135-a465-c0e98518453e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15308
15827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1530815827
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1225558503
Short name T2394
Test name
Test status
Simulation time 5665281956 ps
CPU time 39.72 seconds
Started Jul 13 07:16:19 PM PDT 24
Finished Jul 13 07:17:01 PM PDT 24
Peak memory 207120 kb
Host smart-c984cc4f-11ec-4411-8d25-cbad0eafc63b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1225558503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1225558503
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2564297587
Short name T436
Test name
Test status
Simulation time 173304170 ps
CPU time 0.87 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 206816 kb
Host smart-be0c16b0-c29a-44ff-913c-f9c1abdd5d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25642
97587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2564297587
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.4207487151
Short name T366
Test name
Test status
Simulation time 166165039 ps
CPU time 0.82 seconds
Started Jul 13 07:16:26 PM PDT 24
Finished Jul 13 07:16:28 PM PDT 24
Peak memory 206880 kb
Host smart-46c658a2-b0a1-4dea-b95d-78b1e37408df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42074
87151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.4207487151
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.2427060507
Short name T2294
Test name
Test status
Simulation time 605798979 ps
CPU time 1.44 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:16:25 PM PDT 24
Peak memory 206876 kb
Host smart-b9d76faf-f6a1-446a-b16d-f4632405d1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24270
60507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2427060507
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.893429814
Short name T2470
Test name
Test status
Simulation time 7226571912 ps
CPU time 48.56 seconds
Started Jul 13 07:16:26 PM PDT 24
Finished Jul 13 07:17:16 PM PDT 24
Peak memory 207128 kb
Host smart-3e383dc4-8345-4978-aad5-0988adc7032f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89342
9814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.893429814
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.1603870366
Short name T517
Test name
Test status
Simulation time 49564762 ps
CPU time 0.72 seconds
Started Jul 13 07:16:44 PM PDT 24
Finished Jul 13 07:16:47 PM PDT 24
Peak memory 206908 kb
Host smart-8192e684-c06f-435f-ac93-c74332374111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1603870366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1603870366
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.610913286
Short name T2048
Test name
Test status
Simulation time 4152537828 ps
CPU time 5.3 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:16:29 PM PDT 24
Peak memory 207120 kb
Host smart-62f2c84a-9d87-4993-a1c5-fb4ed62d420d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=610913286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.610913286
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2178544044
Short name T1070
Test name
Test status
Simulation time 13388738165 ps
CPU time 12.73 seconds
Started Jul 13 07:16:25 PM PDT 24
Finished Jul 13 07:16:40 PM PDT 24
Peak memory 207140 kb
Host smart-d5b5c8c7-bb1f-4cb1-8b15-2a939a90ddfd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2178544044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2178544044
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3042162725
Short name T940
Test name
Test status
Simulation time 23397242893 ps
CPU time 23.54 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:16:47 PM PDT 24
Peak memory 206936 kb
Host smart-795f1ac2-1951-4c99-a705-97821a68a7f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3042162725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3042162725
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1441256764
Short name T667
Test name
Test status
Simulation time 169269328 ps
CPU time 0.86 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:16:24 PM PDT 24
Peak memory 206868 kb
Host smart-60eece69-ea20-4570-92f3-b31c999cabf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14412
56764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1441256764
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.243413242
Short name T1694
Test name
Test status
Simulation time 162543945 ps
CPU time 0.76 seconds
Started Jul 13 07:16:23 PM PDT 24
Finished Jul 13 07:16:25 PM PDT 24
Peak memory 206868 kb
Host smart-5de1173f-6211-482d-83bf-290d36409732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24341
3242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.243413242
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.1845425791
Short name T374
Test name
Test status
Simulation time 327948157 ps
CPU time 1.12 seconds
Started Jul 13 07:16:22 PM PDT 24
Finished Jul 13 07:16:25 PM PDT 24
Peak memory 206856 kb
Host smart-d246db87-01d0-48ac-a9b0-c189ad981880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18454
25791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.1845425791
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2658446052
Short name T1748
Test name
Test status
Simulation time 1246480084 ps
CPU time 2.66 seconds
Started Jul 13 07:16:25 PM PDT 24
Finished Jul 13 07:16:29 PM PDT 24
Peak memory 207068 kb
Host smart-b7631571-5108-4d58-9d2d-fafc251d668e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26584
46052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2658446052
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.1076197369
Short name T885
Test name
Test status
Simulation time 8282137198 ps
CPU time 15.55 seconds
Started Jul 13 07:16:33 PM PDT 24
Finished Jul 13 07:16:50 PM PDT 24
Peak memory 207076 kb
Host smart-2170fd45-dc6f-42c2-8d71-bde4f78ffe3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10761
97369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.1076197369
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3863369674
Short name T1910
Test name
Test status
Simulation time 406100116 ps
CPU time 1.25 seconds
Started Jul 13 07:16:24 PM PDT 24
Finished Jul 13 07:16:27 PM PDT 24
Peak memory 207052 kb
Host smart-857632e9-3f0d-4cc7-aa35-e7d0a22688b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633
69674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3863369674
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1255276079
Short name T1032
Test name
Test status
Simulation time 139053553 ps
CPU time 0.81 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:16:37 PM PDT 24
Peak memory 206868 kb
Host smart-e4136603-f176-4384-a66b-d283f2a92a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12552
76079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1255276079
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3760005595
Short name T782
Test name
Test status
Simulation time 82848808 ps
CPU time 0.71 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 206892 kb
Host smart-9f56149e-aeaf-4fed-8178-9cf00cdfb1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37600
05595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3760005595
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1679902668
Short name T1756
Test name
Test status
Simulation time 930784498 ps
CPU time 2.28 seconds
Started Jul 13 07:16:31 PM PDT 24
Finished Jul 13 07:16:35 PM PDT 24
Peak memory 207056 kb
Host smart-a78a9028-7399-481a-93f0-e0d767a0c41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16799
02668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1679902668
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.4036682118
Short name T2071
Test name
Test status
Simulation time 361298945 ps
CPU time 2.34 seconds
Started Jul 13 07:16:23 PM PDT 24
Finished Jul 13 07:16:28 PM PDT 24
Peak memory 206972 kb
Host smart-991da56a-c4d9-4976-850b-89fd9c571f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366
82118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.4036682118
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.982264848
Short name T2677
Test name
Test status
Simulation time 194119849 ps
CPU time 0.83 seconds
Started Jul 13 07:16:26 PM PDT 24
Finished Jul 13 07:16:29 PM PDT 24
Peak memory 206864 kb
Host smart-38da0ac7-d44e-4893-9a37-fdc02489a611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98226
4848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.982264848
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.4019147714
Short name T348
Test name
Test status
Simulation time 143047036 ps
CPU time 0.75 seconds
Started Jul 13 07:16:29 PM PDT 24
Finished Jul 13 07:16:31 PM PDT 24
Peak memory 206860 kb
Host smart-8b2cc3c7-ae10-4489-af22-0b62d52770c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40191
47714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.4019147714
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3259080902
Short name T1444
Test name
Test status
Simulation time 249023724 ps
CPU time 0.93 seconds
Started Jul 13 07:16:30 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 206864 kb
Host smart-4b547f7e-129f-455a-9344-cc72ad9d8245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
80902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3259080902
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.723811759
Short name T2321
Test name
Test status
Simulation time 12631651629 ps
CPU time 108.86 seconds
Started Jul 13 07:16:25 PM PDT 24
Finished Jul 13 07:18:15 PM PDT 24
Peak memory 206600 kb
Host smart-990c6dee-d117-4c30-8ffa-539194f3106b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72381
1759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.723811759
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3497353303
Short name T485
Test name
Test status
Simulation time 179122962 ps
CPU time 0.84 seconds
Started Jul 13 07:16:25 PM PDT 24
Finished Jul 13 07:16:27 PM PDT 24
Peak memory 205764 kb
Host smart-6ebff9bf-3183-4a56-8964-81a266e49380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34973
53303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3497353303
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1014572146
Short name T1369
Test name
Test status
Simulation time 23342384108 ps
CPU time 30.7 seconds
Started Jul 13 07:16:24 PM PDT 24
Finished Jul 13 07:16:56 PM PDT 24
Peak memory 206928 kb
Host smart-1361faa4-af4d-490e-9d5b-78bf922f2851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10145
72146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1014572146
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3521329044
Short name T2533
Test name
Test status
Simulation time 3317344323 ps
CPU time 4.2 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:16:40 PM PDT 24
Peak memory 206928 kb
Host smart-e4a9568f-aace-4954-b70d-f5262cf7227b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35213
29044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3521329044
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2378137027
Short name T2623
Test name
Test status
Simulation time 6908698580 ps
CPU time 54.5 seconds
Started Jul 13 07:16:25 PM PDT 24
Finished Jul 13 07:17:21 PM PDT 24
Peak memory 207068 kb
Host smart-dad8765b-0ef2-48d7-90db-aa8cf1b1ac73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
37027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2378137027
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.3316289258
Short name T2703
Test name
Test status
Simulation time 4897082021 ps
CPU time 35.34 seconds
Started Jul 13 07:16:24 PM PDT 24
Finished Jul 13 07:17:01 PM PDT 24
Peak memory 207044 kb
Host smart-a14c2a67-17ac-4e7d-8710-082daa7c3246
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3316289258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.3316289258
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3930357922
Short name T1264
Test name
Test status
Simulation time 238437298 ps
CPU time 0.94 seconds
Started Jul 13 07:16:24 PM PDT 24
Finished Jul 13 07:16:27 PM PDT 24
Peak memory 206832 kb
Host smart-9e3869ed-46e2-4c66-bd3e-426735c05422
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3930357922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3930357922
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1270046323
Short name T2432
Test name
Test status
Simulation time 209805651 ps
CPU time 0.94 seconds
Started Jul 13 07:16:24 PM PDT 24
Finished Jul 13 07:16:27 PM PDT 24
Peak memory 206868 kb
Host smart-e536fac0-e684-4595-98f2-35a0ed57a14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12700
46323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1270046323
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.3408512159
Short name T476
Test name
Test status
Simulation time 4646207538 ps
CPU time 32.36 seconds
Started Jul 13 07:16:25 PM PDT 24
Finished Jul 13 07:16:59 PM PDT 24
Peak memory 207024 kb
Host smart-ddb511e7-bad1-49e6-884d-f79e2d2c87a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34085
12159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.3408512159
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2509453187
Short name T1885
Test name
Test status
Simulation time 3770312076 ps
CPU time 25.9 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:17:14 PM PDT 24
Peak memory 207116 kb
Host smart-c28aecbd-3ac4-4a28-b023-7b075853acd6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2509453187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2509453187
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.48230401
Short name T1674
Test name
Test status
Simulation time 157650187 ps
CPU time 0.83 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 206868 kb
Host smart-d8f05c33-0467-4e91-8242-e3e1eeb2fa27
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=48230401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.48230401
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2804410752
Short name T1352
Test name
Test status
Simulation time 155766427 ps
CPU time 0.79 seconds
Started Jul 13 07:16:29 PM PDT 24
Finished Jul 13 07:16:31 PM PDT 24
Peak memory 206868 kb
Host smart-5a560856-e398-4637-800d-092a510d1679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28044
10752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2804410752
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2484811804
Short name T1989
Test name
Test status
Simulation time 163873474 ps
CPU time 0.81 seconds
Started Jul 13 07:16:44 PM PDT 24
Finished Jul 13 07:16:47 PM PDT 24
Peak memory 206756 kb
Host smart-f6973f6b-ae47-4c7d-b407-4374fc575f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24848
11804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2484811804
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2098295920
Short name T815
Test name
Test status
Simulation time 142567579 ps
CPU time 0.9 seconds
Started Jul 13 07:16:30 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 206868 kb
Host smart-aa8b4099-16cd-42f3-a7fb-8ada9d3ab77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20982
95920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2098295920
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1104518929
Short name T633
Test name
Test status
Simulation time 229751639 ps
CPU time 0.9 seconds
Started Jul 13 07:16:26 PM PDT 24
Finished Jul 13 07:16:29 PM PDT 24
Peak memory 206816 kb
Host smart-7bf3ff0b-6f09-48f3-ab19-8c976b2d482b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11045
18929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1104518929
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.803012584
Short name T1791
Test name
Test status
Simulation time 209665797 ps
CPU time 0.84 seconds
Started Jul 13 07:16:28 PM PDT 24
Finished Jul 13 07:16:30 PM PDT 24
Peak memory 206864 kb
Host smart-8ef4181e-9625-416a-8dae-a2021d4ba044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80301
2584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.803012584
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3580620119
Short name T2347
Test name
Test status
Simulation time 160168673 ps
CPU time 0.83 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 206868 kb
Host smart-2d0bb906-da12-47f5-b49e-88361a750bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
20119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3580620119
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3895220993
Short name T1985
Test name
Test status
Simulation time 275252422 ps
CPU time 0.94 seconds
Started Jul 13 07:16:30 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 206880 kb
Host smart-b2e9e44f-40ee-4ce0-87f1-0103a922d712
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3895220993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3895220993
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2248617418
Short name T1001
Test name
Test status
Simulation time 161263299 ps
CPU time 0.76 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:43 PM PDT 24
Peak memory 206860 kb
Host smart-093c36c2-e008-4b3b-9012-9ca5b5be6cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22486
17418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2248617418
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.586403705
Short name T852
Test name
Test status
Simulation time 100041903 ps
CPU time 0.75 seconds
Started Jul 13 07:16:27 PM PDT 24
Finished Jul 13 07:16:29 PM PDT 24
Peak memory 206864 kb
Host smart-ac25f052-3f0e-46db-b48d-8167253c4366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58640
3705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.586403705
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.127958280
Short name T677
Test name
Test status
Simulation time 22967354986 ps
CPU time 52.67 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:17:35 PM PDT 24
Peak memory 207112 kb
Host smart-303167e6-3640-4dbc-ab38-8fd0d89a4499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12795
8280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.127958280
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2765961772
Short name T2650
Test name
Test status
Simulation time 197404567 ps
CPU time 0.86 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206864 kb
Host smart-2414b1e1-3b3d-49e1-9ffb-62b8f6eb5e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659
61772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2765961772
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2401719646
Short name T2683
Test name
Test status
Simulation time 156235661 ps
CPU time 0.81 seconds
Started Jul 13 07:16:31 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 206848 kb
Host smart-a1a4edc8-11e6-4a21-aae2-91a9ada569a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24017
19646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2401719646
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2718652056
Short name T1107
Test name
Test status
Simulation time 229711745 ps
CPU time 0.93 seconds
Started Jul 13 07:16:27 PM PDT 24
Finished Jul 13 07:16:29 PM PDT 24
Peak memory 206892 kb
Host smart-8d11e883-9c08-406e-869a-b8578952a432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27186
52056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2718652056
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3824967293
Short name T2545
Test name
Test status
Simulation time 168089174 ps
CPU time 0.83 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:40 PM PDT 24
Peak memory 206864 kb
Host smart-7ac98c8a-2cbf-4be8-8d95-0b9411a28ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38249
67293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3824967293
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3492654202
Short name T2101
Test name
Test status
Simulation time 142399311 ps
CPU time 0.79 seconds
Started Jul 13 07:16:32 PM PDT 24
Finished Jul 13 07:16:33 PM PDT 24
Peak memory 206860 kb
Host smart-c6fed243-d667-447f-a1b2-a104a05110a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34926
54202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3492654202
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1337458681
Short name T2702
Test name
Test status
Simulation time 151497746 ps
CPU time 0.8 seconds
Started Jul 13 07:16:28 PM PDT 24
Finished Jul 13 07:16:30 PM PDT 24
Peak memory 206840 kb
Host smart-58dd90c9-eb09-41ae-bf51-282767a35b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13374
58681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1337458681
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.393050988
Short name T943
Test name
Test status
Simulation time 154096518 ps
CPU time 0.8 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:16:49 PM PDT 24
Peak memory 206876 kb
Host smart-39dc8d4a-ef85-408f-bdf4-49525d526df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39305
0988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.393050988
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1903328468
Short name T1556
Test name
Test status
Simulation time 186270422 ps
CPU time 0.85 seconds
Started Jul 13 07:16:29 PM PDT 24
Finished Jul 13 07:16:31 PM PDT 24
Peak memory 206864 kb
Host smart-a69e0167-71cc-4d71-9ef3-fda4ae37cdeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
28468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1903328468
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2404744384
Short name T2346
Test name
Test status
Simulation time 6730789930 ps
CPU time 185.85 seconds
Started Jul 13 07:16:28 PM PDT 24
Finished Jul 13 07:19:35 PM PDT 24
Peak memory 206736 kb
Host smart-5e631a0a-428e-40a0-90f9-fc87ee6526ac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2404744384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2404744384
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2637227230
Short name T1136
Test name
Test status
Simulation time 233487682 ps
CPU time 0.9 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 206760 kb
Host smart-e295bf76-b972-4c0c-a8ef-5f5be5b00c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26372
27230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2637227230
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3747952598
Short name T1747
Test name
Test status
Simulation time 165676885 ps
CPU time 0.81 seconds
Started Jul 13 07:16:30 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 206872 kb
Host smart-d6690856-70b3-40d2-8a4b-f0c314fb510a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37479
52598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3747952598
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.3188454676
Short name T1664
Test name
Test status
Simulation time 1196642286 ps
CPU time 2.34 seconds
Started Jul 13 07:16:29 PM PDT 24
Finished Jul 13 07:16:37 PM PDT 24
Peak memory 207068 kb
Host smart-1cc0a1a2-ec41-43b6-8584-e826354429cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31884
54676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.3188454676
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.282387143
Short name T2093
Test name
Test status
Simulation time 4167394318 ps
CPU time 39.03 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:17:19 PM PDT 24
Peak memory 207112 kb
Host smart-a8451528-badf-4677-8884-34786e839a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28238
7143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.282387143
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2888084165
Short name T1316
Test name
Test status
Simulation time 46283173 ps
CPU time 0.7 seconds
Started Jul 13 07:16:47 PM PDT 24
Finished Jul 13 07:16:51 PM PDT 24
Peak memory 206940 kb
Host smart-56a1f0ea-91b8-4584-b957-d9cf5bd22c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2888084165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2888084165
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3673031287
Short name T1299
Test name
Test status
Simulation time 4233964140 ps
CPU time 5.61 seconds
Started Jul 13 07:16:27 PM PDT 24
Finished Jul 13 07:16:34 PM PDT 24
Peak memory 207072 kb
Host smart-72535eff-2681-4686-954d-6a0409bebeed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3673031287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3673031287
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2678695881
Short name T503
Test name
Test status
Simulation time 13545235695 ps
CPU time 13.59 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:55 PM PDT 24
Peak memory 207144 kb
Host smart-08bcad79-b94d-4950-8fb1-bc87aaab9405
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2678695881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2678695881
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2973099249
Short name T1626
Test name
Test status
Simulation time 23349862494 ps
CPU time 23.84 seconds
Started Jul 13 07:16:29 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 206936 kb
Host smart-43ef47aa-4ea3-4e87-b292-00cbacf9b150
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2973099249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2973099249
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2479034799
Short name T462
Test name
Test status
Simulation time 149360818 ps
CPU time 0.8 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:16:46 PM PDT 24
Peak memory 206868 kb
Host smart-d708833c-2cdd-45a0-baa4-39774df42916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24790
34799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2479034799
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1468335780
Short name T2739
Test name
Test status
Simulation time 158038721 ps
CPU time 0.88 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:16:37 PM PDT 24
Peak memory 206856 kb
Host smart-8056713e-a71a-45db-b91d-9a404ec3d20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14683
35780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1468335780
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.570474933
Short name T2713
Test name
Test status
Simulation time 182501172 ps
CPU time 0.88 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 206868 kb
Host smart-35dd5816-cac6-4e67-98b5-71c22d353db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57047
4933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.570474933
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2612040370
Short name T2356
Test name
Test status
Simulation time 1389344891 ps
CPU time 3.31 seconds
Started Jul 13 07:16:26 PM PDT 24
Finished Jul 13 07:16:31 PM PDT 24
Peak memory 207008 kb
Host smart-5a8c1855-a304-4ccd-9eda-3deb770275c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26120
40370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2612040370
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3511371109
Short name T924
Test name
Test status
Simulation time 18863287297 ps
CPU time 37.27 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:17:13 PM PDT 24
Peak memory 207076 kb
Host smart-553a6423-05e9-4d85-9e20-9a910b2906ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35113
71109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3511371109
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2293757131
Short name T2712
Test name
Test status
Simulation time 477232175 ps
CPU time 1.31 seconds
Started Jul 13 07:16:31 PM PDT 24
Finished Jul 13 07:16:33 PM PDT 24
Peak memory 206852 kb
Host smart-b0833324-dfce-40bf-9d7a-4b68b4c019a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22937
57131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2293757131
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.308341275
Short name T1260
Test name
Test status
Simulation time 132341613 ps
CPU time 0.72 seconds
Started Jul 13 07:16:28 PM PDT 24
Finished Jul 13 07:16:30 PM PDT 24
Peak memory 206852 kb
Host smart-32bbe97f-1068-40d3-bc9f-111d99f473cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30834
1275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.308341275
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.575935536
Short name T427
Test name
Test status
Simulation time 37271480 ps
CPU time 0.65 seconds
Started Jul 13 07:16:44 PM PDT 24
Finished Jul 13 07:16:47 PM PDT 24
Peak memory 206876 kb
Host smart-6eafc98b-1a66-4196-b79d-fd3a9e176db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57593
5536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.575935536
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1002329419
Short name T1576
Test name
Test status
Simulation time 829007429 ps
CPU time 1.92 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 207076 kb
Host smart-54a9de1e-6746-49f3-9cec-26ba3e948396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10023
29419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1002329419
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.414634174
Short name T662
Test name
Test status
Simulation time 409077308 ps
CPU time 2.32 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 207092 kb
Host smart-56c61d80-c7c3-4975-beff-b7eb9edbe4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463
4174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.414634174
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2356546580
Short name T2389
Test name
Test status
Simulation time 173341455 ps
CPU time 0.78 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:16:48 PM PDT 24
Peak memory 206884 kb
Host smart-f9c56f4d-4ea1-44ae-b2f5-1eb919261141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23565
46580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2356546580
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2136863941
Short name T2611
Test name
Test status
Simulation time 210061538 ps
CPU time 0.76 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 206860 kb
Host smart-c4d928cf-035c-497a-a4af-56ef324154e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21368
63941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2136863941
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3643379080
Short name T1243
Test name
Test status
Simulation time 222404308 ps
CPU time 0.94 seconds
Started Jul 13 07:16:47 PM PDT 24
Finished Jul 13 07:16:51 PM PDT 24
Peak memory 206864 kb
Host smart-32fff669-7bf5-440c-a313-705bff92cad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36433
79080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3643379080
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1840372410
Short name T1515
Test name
Test status
Simulation time 6493734210 ps
CPU time 61.22 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:17:44 PM PDT 24
Peak memory 207120 kb
Host smart-13e9352f-6057-4386-8923-303f0fab6544
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1840372410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1840372410
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.680265337
Short name T2679
Test name
Test status
Simulation time 169168517 ps
CPU time 0.81 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206864 kb
Host smart-4352f15a-4f23-4cb1-b00f-13fe8e47503a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68026
5337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.680265337
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2750950767
Short name T1102
Test name
Test status
Simulation time 23328844115 ps
CPU time 23.94 seconds
Started Jul 13 07:16:30 PM PDT 24
Finished Jul 13 07:16:55 PM PDT 24
Peak memory 206928 kb
Host smart-4b8c3211-5725-4f37-b33b-e379138eb70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27509
50767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2750950767
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.919878905
Short name T1200
Test name
Test status
Simulation time 3331048071 ps
CPU time 4.26 seconds
Started Jul 13 07:16:29 PM PDT 24
Finished Jul 13 07:16:34 PM PDT 24
Peak memory 206932 kb
Host smart-93057878-29a7-4055-9231-720d86cd7130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91987
8905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.919878905
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1812724873
Short name T2748
Test name
Test status
Simulation time 8158414063 ps
CPU time 75.34 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:18:04 PM PDT 24
Peak memory 207136 kb
Host smart-926aa7bb-1259-458f-87d0-731aa64faab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
24873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1812724873
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1686209459
Short name T719
Test name
Test status
Simulation time 6166071909 ps
CPU time 58.27 seconds
Started Jul 13 07:16:28 PM PDT 24
Finished Jul 13 07:17:27 PM PDT 24
Peak memory 206764 kb
Host smart-296b356b-d631-41b4-8f76-da188304f56f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1686209459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1686209459
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1794893572
Short name T739
Test name
Test status
Simulation time 251555592 ps
CPU time 0.99 seconds
Started Jul 13 07:16:30 PM PDT 24
Finished Jul 13 07:16:32 PM PDT 24
Peak memory 206868 kb
Host smart-4aae4ff6-90e2-4e5e-b49f-4d2b4f5353af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1794893572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1794893572
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2641370362
Short name T1497
Test name
Test status
Simulation time 227964049 ps
CPU time 0.88 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 206860 kb
Host smart-8eee7404-7b7a-4ea2-bc28-57624a89d09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
70362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2641370362
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.2719450620
Short name T1606
Test name
Test status
Simulation time 5908867867 ps
CPU time 41.33 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:17:27 PM PDT 24
Peak memory 207076 kb
Host smart-45d35be8-03fe-4ae2-a5da-e0a536cda88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27194
50620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.2719450620
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.920397996
Short name T1339
Test name
Test status
Simulation time 5560318014 ps
CPU time 38.99 seconds
Started Jul 13 07:16:37 PM PDT 24
Finished Jul 13 07:17:16 PM PDT 24
Peak memory 207132 kb
Host smart-88b8219c-f9d4-42ef-bab3-f4874829bee5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=920397996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.920397996
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1601122084
Short name T406
Test name
Test status
Simulation time 162411444 ps
CPU time 0.84 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:43 PM PDT 24
Peak memory 207080 kb
Host smart-d9616b31-569e-40e7-b14f-112c3220c2b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1601122084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1601122084
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2278733985
Short name T2529
Test name
Test status
Simulation time 146154079 ps
CPU time 0.79 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:16:47 PM PDT 24
Peak memory 206876 kb
Host smart-b5e9d46c-6923-4a7c-aae9-844a973caf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22787
33985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2278733985
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2501798010
Short name T114
Test name
Test status
Simulation time 193735481 ps
CPU time 0.85 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:16:52 PM PDT 24
Peak memory 206868 kb
Host smart-173a271c-61f5-4095-9f8c-f7fb82267a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25017
98010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2501798010
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2266747212
Short name T1040
Test name
Test status
Simulation time 150961656 ps
CPU time 0.8 seconds
Started Jul 13 07:16:34 PM PDT 24
Finished Jul 13 07:16:35 PM PDT 24
Peak memory 206864 kb
Host smart-7628d0c6-c763-4b11-bfbb-1a242c5e2e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22667
47212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2266747212
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3779629105
Short name T1955
Test name
Test status
Simulation time 152591791 ps
CPU time 0.83 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 206896 kb
Host smart-47f1d60f-bd0f-4fa2-a49e-e658d56b2d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37796
29105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3779629105
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.4238077168
Short name T2678
Test name
Test status
Simulation time 194938391 ps
CPU time 0.81 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:16:49 PM PDT 24
Peak memory 206880 kb
Host smart-6b89c5a4-e786-4452-8209-1382943c2502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
77168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.4238077168
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3565845214
Short name T1493
Test name
Test status
Simulation time 202248369 ps
CPU time 0.8 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:16:52 PM PDT 24
Peak memory 206860 kb
Host smart-9b664c34-85ad-474d-abe9-c54b46b07753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35658
45214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3565845214
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.2703665973
Short name T559
Test name
Test status
Simulation time 256074835 ps
CPU time 0.96 seconds
Started Jul 13 07:16:47 PM PDT 24
Finished Jul 13 07:16:51 PM PDT 24
Peak memory 206868 kb
Host smart-66b7a9c0-bb17-4fbe-aacd-ccc7bc35c39a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2703665973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.2703665973
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2788838966
Short name T967
Test name
Test status
Simulation time 178359887 ps
CPU time 0.81 seconds
Started Jul 13 07:16:34 PM PDT 24
Finished Jul 13 07:16:36 PM PDT 24
Peak memory 206856 kb
Host smart-3883a816-6688-45bc-b546-2d054cbfcac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27888
38966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2788838966
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1242006361
Short name T25
Test name
Test status
Simulation time 33920363 ps
CPU time 0.7 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:16:37 PM PDT 24
Peak memory 206868 kb
Host smart-45d44d10-1b19-4257-a0d5-4f1e9744e09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12420
06361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1242006361
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2859969146
Short name T2719
Test name
Test status
Simulation time 11422631467 ps
CPU time 27.09 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:17:14 PM PDT 24
Peak memory 207096 kb
Host smart-bed70d9d-6e3d-4b60-abef-771365334b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28599
69146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2859969146
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2585884482
Short name T1708
Test name
Test status
Simulation time 159534734 ps
CPU time 0.79 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:16:37 PM PDT 24
Peak memory 206856 kb
Host smart-8806c49b-6f5f-49fd-8866-e6ee743cf83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25858
84482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2585884482
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.4206473933
Short name T1088
Test name
Test status
Simulation time 261816821 ps
CPU time 0.92 seconds
Started Jul 13 07:16:33 PM PDT 24
Finished Jul 13 07:16:35 PM PDT 24
Peak memory 206876 kb
Host smart-6fdc0ea5-5064-41d1-afe9-384474ed3724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42064
73933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.4206473933
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1310872430
Short name T1332
Test name
Test status
Simulation time 233219047 ps
CPU time 0.87 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 206868 kb
Host smart-bf02f768-bea1-412c-8ee0-31f0d7acc504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13108
72430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1310872430
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1033115846
Short name T1184
Test name
Test status
Simulation time 170332533 ps
CPU time 0.91 seconds
Started Jul 13 07:16:44 PM PDT 24
Finished Jul 13 07:16:48 PM PDT 24
Peak memory 206912 kb
Host smart-977c5340-c68f-45aa-a441-fb3af0b8b062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10331
15846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1033115846
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2833498597
Short name T833
Test name
Test status
Simulation time 143815747 ps
CPU time 0.81 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:16:46 PM PDT 24
Peak memory 206888 kb
Host smart-6fc4749f-9ce6-4b74-a937-52ba5b1ff9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28334
98597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2833498597
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2164731363
Short name T736
Test name
Test status
Simulation time 160171035 ps
CPU time 0.8 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:16:48 PM PDT 24
Peak memory 206860 kb
Host smart-9d554e4c-d713-4aad-8590-99a0cff0b928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21647
31363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2164731363
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3125094571
Short name T2751
Test name
Test status
Simulation time 170621246 ps
CPU time 0.83 seconds
Started Jul 13 07:16:47 PM PDT 24
Finished Jul 13 07:16:50 PM PDT 24
Peak memory 206892 kb
Host smart-66c21a50-6681-44d7-972e-420be1e78f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31250
94571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3125094571
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1024814693
Short name T44
Test name
Test status
Simulation time 209562294 ps
CPU time 0.9 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:16:47 PM PDT 24
Peak memory 206864 kb
Host smart-b5b4235e-c3ca-4fda-a8d6-5d27a10d1f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10248
14693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1024814693
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1182458624
Short name T628
Test name
Test status
Simulation time 5019562135 ps
CPU time 133.25 seconds
Started Jul 13 07:16:32 PM PDT 24
Finished Jul 13 07:18:46 PM PDT 24
Peak memory 207060 kb
Host smart-c787292f-99cf-4c5d-87e0-82f53c523713
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1182458624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1182458624
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3554724676
Short name T1390
Test name
Test status
Simulation time 200374558 ps
CPU time 0.86 seconds
Started Jul 13 07:16:33 PM PDT 24
Finished Jul 13 07:16:35 PM PDT 24
Peak memory 206872 kb
Host smart-afdc7183-399c-4c0c-875e-d9ad902ca009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35547
24676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3554724676
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2894236972
Short name T728
Test name
Test status
Simulation time 181882395 ps
CPU time 0.82 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 206876 kb
Host smart-0947969f-2a4b-4570-be40-97538511735c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
36972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2894236972
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.1284976896
Short name T359
Test name
Test status
Simulation time 1261175311 ps
CPU time 2.53 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 207076 kb
Host smart-57cc4847-4a38-4acf-9cfc-5614e2bcfef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
76896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1284976896
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2281387839
Short name T1187
Test name
Test status
Simulation time 6444540728 ps
CPU time 179.7 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:19:36 PM PDT 24
Peak memory 207180 kb
Host smart-3a7015fd-fa29-4f41-895a-411b9a956437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22813
87839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2281387839
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.487111358
Short name T2261
Test name
Test status
Simulation time 35686745 ps
CPU time 0.64 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 206840 kb
Host smart-d94ad361-5239-4270-8725-1381fa460b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=487111358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.487111358
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.228923940
Short name T1466
Test name
Test status
Simulation time 4026520220 ps
CPU time 5.54 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:17:02 PM PDT 24
Peak memory 207108 kb
Host smart-e40ff032-4610-4912-be85-358224cef1b7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=228923940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.228923940
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.159137850
Short name T205
Test name
Test status
Simulation time 13480831427 ps
CPU time 12.76 seconds
Started Jul 13 07:16:44 PM PDT 24
Finished Jul 13 07:17:00 PM PDT 24
Peak memory 207132 kb
Host smart-99703b5e-c37e-4d7b-bc5f-bc87aec5266f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=159137850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.159137850
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1291376716
Short name T1743
Test name
Test status
Simulation time 23385181026 ps
CPU time 23.98 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:17:00 PM PDT 24
Peak memory 207080 kb
Host smart-5786c8ef-6ae6-4cb8-ae36-e0af79b6add1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1291376716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1291376716
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.958210170
Short name T484
Test name
Test status
Simulation time 187573990 ps
CPU time 0.86 seconds
Started Jul 13 07:16:35 PM PDT 24
Finished Jul 13 07:16:36 PM PDT 24
Peak memory 206856 kb
Host smart-5d6f2f64-9b36-466f-af9e-3b32f436a361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95821
0170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.958210170
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1662753376
Short name T838
Test name
Test status
Simulation time 172058798 ps
CPU time 0.81 seconds
Started Jul 13 07:16:49 PM PDT 24
Finished Jul 13 07:16:53 PM PDT 24
Peak memory 206648 kb
Host smart-d857090c-dc14-44e7-b01d-05dd590a2df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16627
53376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1662753376
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.1552667907
Short name T1630
Test name
Test status
Simulation time 428366562 ps
CPU time 1.38 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:16:46 PM PDT 24
Peak memory 206880 kb
Host smart-c0bc1ce8-62c2-4a91-861a-a4ff3ce67950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15526
67907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.1552667907
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3665769287
Short name T2283
Test name
Test status
Simulation time 1588941922 ps
CPU time 3.35 seconds
Started Jul 13 07:16:46 PM PDT 24
Finished Jul 13 07:16:52 PM PDT 24
Peak memory 207072 kb
Host smart-70f6daa3-54dc-4995-884c-ce9b07ad166d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36657
69287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3665769287
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.4252299129
Short name T2619
Test name
Test status
Simulation time 9936398147 ps
CPU time 17.87 seconds
Started Jul 13 07:16:49 PM PDT 24
Finished Jul 13 07:17:10 PM PDT 24
Peak memory 207076 kb
Host smart-03bfa8ef-e68c-474b-a108-cdffd23fbee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42522
99129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.4252299129
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.2095135163
Short name T639
Test name
Test status
Simulation time 349542365 ps
CPU time 1.14 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 206860 kb
Host smart-6b08d6a1-6b5a-4444-bf5c-91c7d17772fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20951
35163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.2095135163
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1803936519
Short name T2654
Test name
Test status
Simulation time 148334837 ps
CPU time 0.83 seconds
Started Jul 13 07:16:55 PM PDT 24
Finished Jul 13 07:17:01 PM PDT 24
Peak memory 206868 kb
Host smart-d1b0c1bc-9f74-4216-b038-535fb734ff05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18039
36519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1803936519
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.4237942675
Short name T1499
Test name
Test status
Simulation time 61190621 ps
CPU time 0.68 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:16:46 PM PDT 24
Peak memory 206868 kb
Host smart-572fd483-4c09-4626-a9ea-a154eb5420a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42379
42675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.4237942675
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.627226571
Short name T1430
Test name
Test status
Simulation time 847457940 ps
CPU time 2.24 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:44 PM PDT 24
Peak memory 207312 kb
Host smart-3a21d587-824b-46d9-aa89-e35b0abe08b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62722
6571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.627226571
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1757285118
Short name T2514
Test name
Test status
Simulation time 262155155 ps
CPU time 1.75 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 207060 kb
Host smart-d5ba10d2-1151-4961-af51-83414e43ebc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17572
85118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1757285118
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2044200805
Short name T321
Test name
Test status
Simulation time 213148680 ps
CPU time 0.88 seconds
Started Jul 13 07:16:47 PM PDT 24
Finished Jul 13 07:16:50 PM PDT 24
Peak memory 206876 kb
Host smart-1c0fece2-dfb2-4fdc-823a-cce2586d974a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20442
00805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2044200805
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3914751224
Short name T802
Test name
Test status
Simulation time 202075689 ps
CPU time 0.82 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 206872 kb
Host smart-5dcc3d90-8700-4583-9a92-791826d8cccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39147
51224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3914751224
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2643520491
Short name T2582
Test name
Test status
Simulation time 224585268 ps
CPU time 0.93 seconds
Started Jul 13 07:16:46 PM PDT 24
Finished Jul 13 07:16:49 PM PDT 24
Peak memory 206752 kb
Host smart-09add620-1f7b-43cb-b122-8e0cbcc2b6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26435
20491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2643520491
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.546167434
Short name T923
Test name
Test status
Simulation time 5287109899 ps
CPU time 50.23 seconds
Started Jul 13 07:16:46 PM PDT 24
Finished Jul 13 07:17:39 PM PDT 24
Peak memory 207116 kb
Host smart-1d486be6-039e-49b7-aca9-730c32f20b85
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=546167434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.546167434
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.2792585806
Short name T483
Test name
Test status
Simulation time 4214201936 ps
CPU time 12.38 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:17:03 PM PDT 24
Peak memory 206912 kb
Host smart-c3e4835c-6047-4b99-97c9-c61fcc19dea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27925
85806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.2792585806
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2738602292
Short name T654
Test name
Test status
Simulation time 179797688 ps
CPU time 0.82 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:16:48 PM PDT 24
Peak memory 206860 kb
Host smart-61b5c444-297c-45e9-8fc1-f029986855f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27386
02292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2738602292
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2636611207
Short name T2715
Test name
Test status
Simulation time 23266139371 ps
CPU time 23.74 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:17:05 PM PDT 24
Peak memory 206948 kb
Host smart-ca294bd3-f84a-4f86-9003-2f832ed6fbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26366
11207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2636611207
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2815429919
Short name T2232
Test name
Test status
Simulation time 3343733512 ps
CPU time 4.01 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206940 kb
Host smart-3f97374c-96de-4258-9315-65792604444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28154
29919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2815429919
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1935424448
Short name T1218
Test name
Test status
Simulation time 9156965864 ps
CPU time 69.7 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:18:08 PM PDT 24
Peak memory 207144 kb
Host smart-4a810dbb-0625-4192-a197-05fe03c75bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19354
24448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1935424448
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3143115905
Short name T343
Test name
Test status
Simulation time 6449466375 ps
CPU time 58.92 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:17:43 PM PDT 24
Peak memory 207116 kb
Host smart-c01f298b-995e-4f0f-91a2-260511136c33
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3143115905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3143115905
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2564036660
Short name T1880
Test name
Test status
Simulation time 247056326 ps
CPU time 0.92 seconds
Started Jul 13 07:16:39 PM PDT 24
Finished Jul 13 07:16:40 PM PDT 24
Peak memory 206880 kb
Host smart-28f4f9ef-bc1a-4184-bad5-0ada2d992134
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2564036660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2564036660
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1930239218
Short name T1667
Test name
Test status
Simulation time 198269501 ps
CPU time 0.85 seconds
Started Jul 13 07:16:50 PM PDT 24
Finished Jul 13 07:16:55 PM PDT 24
Peak memory 206860 kb
Host smart-66faeffb-f3b8-4c2d-b35f-95d71a68d349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19302
39218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1930239218
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.755926969
Short name T1097
Test name
Test status
Simulation time 4251923033 ps
CPU time 39.96 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 207120 kb
Host smart-fbc7d43b-ade3-497b-b5e2-2f621a925921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75592
6969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.755926969
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.528253451
Short name T1119
Test name
Test status
Simulation time 4930440482 ps
CPU time 140.28 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:19:05 PM PDT 24
Peak memory 207288 kb
Host smart-de97821a-f5e7-4652-b5af-c988baedd096
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=528253451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.528253451
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1368378713
Short name T1135
Test name
Test status
Simulation time 163843105 ps
CPU time 0.83 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:16:57 PM PDT 24
Peak memory 206900 kb
Host smart-e404f0f0-bb11-4494-a1b6-4c11a16d9991
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1368378713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1368378713
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1657479808
Short name T2302
Test name
Test status
Simulation time 143728471 ps
CPU time 0.8 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:42 PM PDT 24
Peak memory 206868 kb
Host smart-ffe68d74-9161-46d9-aba9-6d84705253b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16574
79808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1657479808
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3687110387
Short name T2556
Test name
Test status
Simulation time 220445199 ps
CPU time 0.92 seconds
Started Jul 13 07:16:50 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 206900 kb
Host smart-a5f6a637-6e20-44c2-ba75-e28e2bdbe512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36871
10387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3687110387
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3129274963
Short name T2058
Test name
Test status
Simulation time 171028506 ps
CPU time 0.8 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206864 kb
Host smart-f5dd4269-fdfd-4377-907c-61931488fbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292
74963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3129274963
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.726124750
Short name T1586
Test name
Test status
Simulation time 166383397 ps
CPU time 0.81 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:16:58 PM PDT 24
Peak memory 206748 kb
Host smart-7468352d-734a-48b0-80e5-1a9725687b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72612
4750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.726124750
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1537115223
Short name T1479
Test name
Test status
Simulation time 184396858 ps
CPU time 0.84 seconds
Started Jul 13 07:16:59 PM PDT 24
Finished Jul 13 07:17:08 PM PDT 24
Peak memory 206816 kb
Host smart-2304e1aa-8ec4-4992-a357-d6d83331da87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15371
15223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1537115223
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.178682164
Short name T1658
Test name
Test status
Simulation time 208710862 ps
CPU time 0.87 seconds
Started Jul 13 07:16:40 PM PDT 24
Finished Jul 13 07:16:43 PM PDT 24
Peak memory 206812 kb
Host smart-110f2fbe-81c4-46cb-b186-9ffc34af1abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17868
2164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.178682164
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.1710992793
Short name T2142
Test name
Test status
Simulation time 224457705 ps
CPU time 0.91 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:16:52 PM PDT 24
Peak memory 206876 kb
Host smart-ecb174ef-280c-4f81-b74f-32302c98f2f0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1710992793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.1710992793
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3725343646
Short name T2105
Test name
Test status
Simulation time 146804415 ps
CPU time 0.76 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:16:51 PM PDT 24
Peak memory 206840 kb
Host smart-50112c01-eb85-4927-8fdd-f0866e57819d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37253
43646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3725343646
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3312930467
Short name T1412
Test name
Test status
Simulation time 33998532 ps
CPU time 0.66 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:16:48 PM PDT 24
Peak memory 206864 kb
Host smart-303f6bfc-b5c6-4276-8792-93d48b81177e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129
30467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3312930467
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.459505577
Short name T1246
Test name
Test status
Simulation time 16958318727 ps
CPU time 36.54 seconds
Started Jul 13 07:16:41 PM PDT 24
Finished Jul 13 07:17:19 PM PDT 24
Peak memory 207176 kb
Host smart-9bc8ed24-edaf-41ee-be8e-64e4aaea177c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45950
5577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.459505577
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.893361974
Short name T1874
Test name
Test status
Simulation time 166183991 ps
CPU time 0.84 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206868 kb
Host smart-f94a4f25-884a-4d75-b336-650b2fe9c746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89336
1974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.893361974
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.4135394763
Short name T689
Test name
Test status
Simulation time 256605868 ps
CPU time 0.94 seconds
Started Jul 13 07:16:55 PM PDT 24
Finished Jul 13 07:17:02 PM PDT 24
Peak memory 206888 kb
Host smart-2d8e4bb1-aa36-4011-a177-39a616d57666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41353
94763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.4135394763
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.930824723
Short name T1137
Test name
Test status
Simulation time 186042290 ps
CPU time 0.85 seconds
Started Jul 13 07:16:46 PM PDT 24
Finished Jul 13 07:16:50 PM PDT 24
Peak memory 206900 kb
Host smart-dc864c23-e8cf-449d-b47c-5267fb31decf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93082
4723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.930824723
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.92769774
Short name T670
Test name
Test status
Simulation time 236311166 ps
CPU time 0.97 seconds
Started Jul 13 07:16:49 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 206868 kb
Host smart-cfdb6d98-6e44-4c1d-9024-35d581aac5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92769
774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.92769774
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2928795080
Short name T2402
Test name
Test status
Simulation time 151521966 ps
CPU time 0.84 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206804 kb
Host smart-631eae62-ae62-4e6c-b934-ad3020861f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29287
95080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2928795080
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3409984141
Short name T1680
Test name
Test status
Simulation time 164098466 ps
CPU time 0.77 seconds
Started Jul 13 07:16:44 PM PDT 24
Finished Jul 13 07:16:47 PM PDT 24
Peak memory 206856 kb
Host smart-01023874-4405-47ab-8055-92b9ccee9d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34099
84141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3409984141
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3754783650
Short name T578
Test name
Test status
Simulation time 146016524 ps
CPU time 0.81 seconds
Started Jul 13 07:16:42 PM PDT 24
Finished Jul 13 07:16:45 PM PDT 24
Peak memory 206868 kb
Host smart-0d1ba553-099d-4776-821e-bea0f429ef2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37547
83650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3754783650
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1267035712
Short name T960
Test name
Test status
Simulation time 234483311 ps
CPU time 0.92 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:16:46 PM PDT 24
Peak memory 206880 kb
Host smart-0933df09-14ba-4bab-bb53-7e25babe5cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
35712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1267035712
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3713886711
Short name T1494
Test name
Test status
Simulation time 6172441682 ps
CPU time 158.35 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:19:29 PM PDT 24
Peak memory 207052 kb
Host smart-18892ea8-6539-4660-8361-a22fe0b85a21
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3713886711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3713886711
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1477104585
Short name T796
Test name
Test status
Simulation time 274400148 ps
CPU time 0.96 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:16:52 PM PDT 24
Peak memory 206872 kb
Host smart-6147922b-dd4a-4a74-bc1a-a3a37e1f00e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771
04585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1477104585
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1911945407
Short name T2552
Test name
Test status
Simulation time 161166858 ps
CPU time 0.81 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:16:46 PM PDT 24
Peak memory 206844 kb
Host smart-15d7de0e-2032-48ff-882e-b19b88c30e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19119
45407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1911945407
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.2219421005
Short name T920
Test name
Test status
Simulation time 1396727215 ps
CPU time 2.74 seconds
Started Jul 13 07:16:43 PM PDT 24
Finished Jul 13 07:16:48 PM PDT 24
Peak memory 207056 kb
Host smart-e7e19024-52be-4dba-8770-f927f7a25234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22194
21005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.2219421005
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2095615653
Short name T2746
Test name
Test status
Simulation time 4391065186 ps
CPU time 31.89 seconds
Started Jul 13 07:16:56 PM PDT 24
Finished Jul 13 07:17:34 PM PDT 24
Peak memory 207072 kb
Host smart-16a5744f-bddb-43d5-a960-5d4b1896fe7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20956
15653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2095615653
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1455810840
Short name T1311
Test name
Test status
Simulation time 37150261 ps
CPU time 0.69 seconds
Started Jul 13 07:16:51 PM PDT 24
Finished Jul 13 07:16:55 PM PDT 24
Peak memory 206928 kb
Host smart-793c823c-6cdf-4d14-a852-bc9c8d44bee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1455810840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1455810840
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2556956721
Short name T862
Test name
Test status
Simulation time 3652345253 ps
CPU time 5.2 seconds
Started Jul 13 07:16:50 PM PDT 24
Finished Jul 13 07:16:59 PM PDT 24
Peak memory 206940 kb
Host smart-c301ce8d-7313-41b6-88f9-bff6cf936683
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2556956721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2556956721
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.825428211
Short name T2535
Test name
Test status
Simulation time 13316741949 ps
CPU time 12.85 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:17:01 PM PDT 24
Peak memory 206928 kb
Host smart-27fea4d1-05c8-4026-b692-c254cac5ad30
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=825428211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.825428211
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.574218959
Short name T557
Test name
Test status
Simulation time 23326748049 ps
CPU time 22.61 seconds
Started Jul 13 07:16:45 PM PDT 24
Finished Jul 13 07:17:10 PM PDT 24
Peak memory 206924 kb
Host smart-8a7595f3-cb00-4afc-991b-b40af87bbc96
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=574218959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.574218959
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1188967212
Short name T901
Test name
Test status
Simulation time 140144040 ps
CPU time 0.81 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:16:52 PM PDT 24
Peak memory 206868 kb
Host smart-b8ff964f-fa68-465b-a17e-4a6824c39b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11889
67212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1188967212
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3726065779
Short name T2313
Test name
Test status
Simulation time 151323395 ps
CPU time 0.86 seconds
Started Jul 13 07:16:50 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 206892 kb
Host smart-c03faef3-d8d8-4b8f-bfbc-86b1d7f9c714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37260
65779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3726065779
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1542195543
Short name T1365
Test name
Test status
Simulation time 163525492 ps
CPU time 0.79 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:16:57 PM PDT 24
Peak memory 206860 kb
Host smart-d15f41ea-a7d2-4adf-9600-2684358c44ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15421
95543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1542195543
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3567530323
Short name T1127
Test name
Test status
Simulation time 1313156969 ps
CPU time 3.08 seconds
Started Jul 13 07:16:50 PM PDT 24
Finished Jul 13 07:16:56 PM PDT 24
Peak memory 207056 kb
Host smart-0386810a-b094-43ba-8dbe-1ccda29bbb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
30323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3567530323
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.4278222605
Short name T155
Test name
Test status
Simulation time 14180558149 ps
CPU time 25.6 seconds
Started Jul 13 07:16:47 PM PDT 24
Finished Jul 13 07:17:16 PM PDT 24
Peak memory 207140 kb
Host smart-4c0150d4-73b4-4715-9fb0-ac7f63fd04ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42782
22605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.4278222605
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3585723134
Short name T2424
Test name
Test status
Simulation time 408424038 ps
CPU time 1.36 seconds
Started Jul 13 07:16:49 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 206868 kb
Host smart-e784be17-5c82-46b5-a9bb-c558fd00ab16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35857
23134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3585723134
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.989258358
Short name T41
Test name
Test status
Simulation time 151734807 ps
CPU time 0.76 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:16:57 PM PDT 24
Peak memory 206652 kb
Host smart-aedb3e27-1958-472c-9589-3d78c61984ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98925
8358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.989258358
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1876809823
Short name T2210
Test name
Test status
Simulation time 41341541 ps
CPU time 0.64 seconds
Started Jul 13 07:16:55 PM PDT 24
Finished Jul 13 07:17:03 PM PDT 24
Peak memory 206848 kb
Host smart-a0b9fef3-bf7e-4782-9f97-a9cf6a00bbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18768
09823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1876809823
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.2069996867
Short name T1656
Test name
Test status
Simulation time 994591993 ps
CPU time 2.33 seconds
Started Jul 13 07:16:49 PM PDT 24
Finished Jul 13 07:16:55 PM PDT 24
Peak memory 207008 kb
Host smart-6ae63fae-64fd-47bc-94a9-0bf679f92d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20699
96867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2069996867
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1420825330
Short name T727
Test name
Test status
Simulation time 249862322 ps
CPU time 1.48 seconds
Started Jul 13 07:16:47 PM PDT 24
Finished Jul 13 07:16:51 PM PDT 24
Peak memory 207068 kb
Host smart-d5d86ea4-6e0f-40aa-8077-1b3cf9466378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14208
25330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1420825330
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.680011726
Short name T1270
Test name
Test status
Simulation time 170574570 ps
CPU time 0.81 seconds
Started Jul 13 07:16:54 PM PDT 24
Finished Jul 13 07:17:00 PM PDT 24
Peak memory 206648 kb
Host smart-2d2610e4-9b0d-4548-b39e-712e3b954f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68001
1726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.680011726
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.31343264
Short name T200
Test name
Test status
Simulation time 151834292 ps
CPU time 0.77 seconds
Started Jul 13 07:16:48 PM PDT 24
Finished Jul 13 07:16:52 PM PDT 24
Peak memory 206852 kb
Host smart-8070be3d-757e-4688-8682-b5d3ec55e551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31343
264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.31343264
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3890416597
Short name T1820
Test name
Test status
Simulation time 247488814 ps
CPU time 0.91 seconds
Started Jul 13 07:16:50 PM PDT 24
Finished Jul 13 07:16:55 PM PDT 24
Peak memory 206848 kb
Host smart-b98c946b-92cf-416a-99f8-a40200d383ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38904
16597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3890416597
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.692557084
Short name T1581
Test name
Test status
Simulation time 5884043079 ps
CPU time 53.96 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:17:51 PM PDT 24
Peak memory 207024 kb
Host smart-b9fffffe-5f0d-4430-a862-b3f91dc99ca0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=692557084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.692557084
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.424187706
Short name T998
Test name
Test status
Simulation time 10527818594 ps
CPU time 44.78 seconds
Started Jul 13 07:16:57 PM PDT 24
Finished Jul 13 07:17:49 PM PDT 24
Peak memory 207140 kb
Host smart-c5cd822e-9621-4e98-ac86-fde8a5d6af8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42418
7706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.424187706
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2320169095
Short name T966
Test name
Test status
Simulation time 209267313 ps
CPU time 0.88 seconds
Started Jul 13 07:16:55 PM PDT 24
Finished Jul 13 07:17:02 PM PDT 24
Peak memory 206860 kb
Host smart-920b8463-72b7-4121-904a-9da15c67f5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23201
69095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2320169095
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.840766469
Short name T1085
Test name
Test status
Simulation time 23344791295 ps
CPU time 21.59 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:17:18 PM PDT 24
Peak memory 206936 kb
Host smart-19258d78-dbb1-40fe-8ac7-d66d0cb320c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84076
6469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.840766469
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1705263639
Short name T1565
Test name
Test status
Simulation time 3301443821 ps
CPU time 4.39 seconds
Started Jul 13 07:16:51 PM PDT 24
Finished Jul 13 07:16:59 PM PDT 24
Peak memory 206928 kb
Host smart-67cef28c-1589-44fd-a3a1-2ccf74220de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17052
63639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1705263639
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2856316556
Short name T16
Test name
Test status
Simulation time 6909349846 ps
CPU time 171.74 seconds
Started Jul 13 07:16:54 PM PDT 24
Finished Jul 13 07:19:51 PM PDT 24
Peak memory 206916 kb
Host smart-112d54d0-c3ec-4f76-b998-1bd2bb8004ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28563
16556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2856316556
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3011962731
Short name T1811
Test name
Test status
Simulation time 5450785400 ps
CPU time 38.73 seconds
Started Jul 13 07:16:52 PM PDT 24
Finished Jul 13 07:17:34 PM PDT 24
Peak memory 207060 kb
Host smart-bc4d0e42-a909-424a-a5ff-0a257102d2ab
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3011962731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3011962731
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.955418787
Short name T1451
Test name
Test status
Simulation time 243728971 ps
CPU time 0.94 seconds
Started Jul 13 07:16:49 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 206868 kb
Host smart-c9fb9e7a-aeb7-415c-b4dc-85154eb0410a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=955418787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.955418787
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.4117443175
Short name T939
Test name
Test status
Simulation time 193226916 ps
CPU time 0.88 seconds
Started Jul 13 07:16:50 PM PDT 24
Finished Jul 13 07:16:54 PM PDT 24
Peak memory 206844 kb
Host smart-1e2f3200-bb4e-4359-b3c0-b3b619452e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41174
43175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.4117443175
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.3683563321
Short name T1377
Test name
Test status
Simulation time 4901054123 ps
CPU time 31.56 seconds
Started Jul 13 07:16:54 PM PDT 24
Finished Jul 13 07:17:31 PM PDT 24
Peak memory 206860 kb
Host smart-d01171a5-dc49-4485-be30-5521ddd0bec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36835
63321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.3683563321
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1727873087
Short name T2085
Test name
Test status
Simulation time 3776719310 ps
CPU time 104.65 seconds
Started Jul 13 07:16:46 PM PDT 24
Finished Jul 13 07:18:33 PM PDT 24
Peak memory 207088 kb
Host smart-ad10f41a-88da-40bf-b26f-c724937bc8f6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1727873087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1727873087
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3541663133
Short name T1598
Test name
Test status
Simulation time 159852046 ps
CPU time 0.8 seconds
Started Jul 13 07:16:58 PM PDT 24
Finished Jul 13 07:17:07 PM PDT 24
Peak memory 206876 kb
Host smart-8ea2fcbe-c521-4441-bcaa-4acf16fe9279
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3541663133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3541663133
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2735941909
Short name T645
Test name
Test status
Simulation time 140332623 ps
CPU time 0.83 seconds
Started Jul 13 07:16:56 PM PDT 24
Finished Jul 13 07:17:04 PM PDT 24
Peak memory 206864 kb
Host smart-334688f6-2c33-4653-82d8-c201df86d133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27359
41909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2735941909
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.833791533
Short name T126
Test name
Test status
Simulation time 176479263 ps
CPU time 0.86 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:16:58 PM PDT 24
Peak memory 206856 kb
Host smart-fd0642d8-4ed5-42a1-83a3-31817016e737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83379
1533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.833791533
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1733060724
Short name T523
Test name
Test status
Simulation time 211477307 ps
CPU time 0.92 seconds
Started Jul 13 07:17:03 PM PDT 24
Finished Jul 13 07:17:15 PM PDT 24
Peak memory 206572 kb
Host smart-64c2bdd8-eaaa-4480-8327-cdcec233e651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17330
60724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1733060724
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1641163522
Short name T983
Test name
Test status
Simulation time 181411790 ps
CPU time 0.88 seconds
Started Jul 13 07:16:58 PM PDT 24
Finished Jul 13 07:17:08 PM PDT 24
Peak memory 206868 kb
Host smart-d393f34c-669d-4983-873c-d8fdc91ad14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16411
63522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1641163522
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2718789604
Short name T2122
Test name
Test status
Simulation time 195422654 ps
CPU time 0.84 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:10 PM PDT 24
Peak memory 206812 kb
Host smart-72c1ba4e-9edb-4092-b22e-c2aa16c7dd69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27187
89604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2718789604
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2790618850
Short name T154
Test name
Test status
Simulation time 174047083 ps
CPU time 0.8 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:09 PM PDT 24
Peak memory 206852 kb
Host smart-0c323064-d61b-45e9-9fbd-1b2683c351e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27906
18850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2790618850
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.613821579
Short name T2068
Test name
Test status
Simulation time 241904871 ps
CPU time 0.94 seconds
Started Jul 13 07:16:56 PM PDT 24
Finished Jul 13 07:17:05 PM PDT 24
Peak memory 206872 kb
Host smart-cf9f515a-b71b-4c53-b2b8-f31b29bdadb5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=613821579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.613821579
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2069616175
Short name T1846
Test name
Test status
Simulation time 144914331 ps
CPU time 0.74 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:16:58 PM PDT 24
Peak memory 206860 kb
Host smart-50523e46-5e35-4a3f-bdb1-25128fcba3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20696
16175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2069616175
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1747790728
Short name T1746
Test name
Test status
Simulation time 43605122 ps
CPU time 0.66 seconds
Started Jul 13 07:17:05 PM PDT 24
Finished Jul 13 07:17:17 PM PDT 24
Peak memory 206816 kb
Host smart-682ab934-60af-44ec-b1ef-590b770a18d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17477
90728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1747790728
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1576677078
Short name T89
Test name
Test status
Simulation time 16059702571 ps
CPU time 35.39 seconds
Started Jul 13 07:17:03 PM PDT 24
Finished Jul 13 07:17:49 PM PDT 24
Peak memory 207104 kb
Host smart-a340dc8b-71c9-4e98-96ee-22f002b26140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15766
77078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1576677078
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3312361882
Short name T1118
Test name
Test status
Simulation time 168195936 ps
CPU time 0.94 seconds
Started Jul 13 07:16:51 PM PDT 24
Finished Jul 13 07:16:55 PM PDT 24
Peak memory 206844 kb
Host smart-e838aefb-58b7-43a0-9d3d-578b575fb22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33123
61882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3312361882
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1475318737
Short name T2341
Test name
Test status
Simulation time 222726053 ps
CPU time 0.91 seconds
Started Jul 13 07:16:59 PM PDT 24
Finished Jul 13 07:17:08 PM PDT 24
Peak memory 206848 kb
Host smart-be0ec8d4-8dd4-49df-935c-34444e4c85af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14753
18737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1475318737
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.4231874576
Short name T1255
Test name
Test status
Simulation time 181688627 ps
CPU time 0.82 seconds
Started Jul 13 07:16:52 PM PDT 24
Finished Jul 13 07:16:56 PM PDT 24
Peak memory 206868 kb
Host smart-e26ff481-ae9b-48b8-ac97-7a42b3ffe10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42318
74576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.4231874576
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3641540068
Short name T1211
Test name
Test status
Simulation time 158334687 ps
CPU time 0.79 seconds
Started Jul 13 07:16:57 PM PDT 24
Finished Jul 13 07:17:05 PM PDT 24
Peak memory 206812 kb
Host smart-f079858b-6e42-4b97-af8d-dbc928d6cda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36415
40068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3641540068
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2723908355
Short name T2562
Test name
Test status
Simulation time 177329802 ps
CPU time 0.78 seconds
Started Jul 13 07:16:49 PM PDT 24
Finished Jul 13 07:16:53 PM PDT 24
Peak memory 206876 kb
Host smart-fb10a550-df8d-490a-9178-35c195efba0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27239
08355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2723908355
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2336254752
Short name T1335
Test name
Test status
Simulation time 198135653 ps
CPU time 0.8 seconds
Started Jul 13 07:16:58 PM PDT 24
Finished Jul 13 07:17:08 PM PDT 24
Peak memory 206868 kb
Host smart-09d871b5-859b-4053-bc29-9b40535c6881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
54752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2336254752
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.811667640
Short name T2132
Test name
Test status
Simulation time 158295172 ps
CPU time 0.82 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:09 PM PDT 24
Peak memory 206848 kb
Host smart-f5863167-6b92-453b-88c9-2de88a189b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81166
7640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.811667640
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1876407801
Short name T2612
Test name
Test status
Simulation time 204361005 ps
CPU time 0.88 seconds
Started Jul 13 07:17:01 PM PDT 24
Finished Jul 13 07:17:13 PM PDT 24
Peak memory 206876 kb
Host smart-ce071509-acc5-4721-a32c-03776e21b8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18764
07801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1876407801
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.400327955
Short name T353
Test name
Test status
Simulation time 4956934203 ps
CPU time 138.17 seconds
Started Jul 13 07:16:54 PM PDT 24
Finished Jul 13 07:19:18 PM PDT 24
Peak memory 207064 kb
Host smart-56447d9a-c755-4cb2-9b50-d36ca46a28a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=400327955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.400327955
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1066668111
Short name T2699
Test name
Test status
Simulation time 191304013 ps
CPU time 0.82 seconds
Started Jul 13 07:16:57 PM PDT 24
Finished Jul 13 07:17:10 PM PDT 24
Peak memory 206804 kb
Host smart-3d3c2623-d294-4a9f-a52b-9302d33d9991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10666
68111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1066668111
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3074804893
Short name T1869
Test name
Test status
Simulation time 179057083 ps
CPU time 0.89 seconds
Started Jul 13 07:17:04 PM PDT 24
Finished Jul 13 07:17:16 PM PDT 24
Peak memory 206804 kb
Host smart-0e272630-3fb5-449b-9b9f-52ffb6921b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30748
04893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3074804893
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.1096253035
Short name T1322
Test name
Test status
Simulation time 912347873 ps
CPU time 1.97 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:17:15 PM PDT 24
Peak memory 207052 kb
Host smart-0ecddf28-f85c-48e2-82fb-3fb9fb2396ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10962
53035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.1096253035
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3888903730
Short name T1418
Test name
Test status
Simulation time 5331419016 ps
CPU time 146.7 seconds
Started Jul 13 07:16:52 PM PDT 24
Finished Jul 13 07:19:22 PM PDT 24
Peak memory 207092 kb
Host smart-b9e84f8e-b4d8-4005-9bb6-a5066cf6aba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38889
03730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3888903730
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.1187276140
Short name T748
Test name
Test status
Simulation time 32343942 ps
CPU time 0.69 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:17:13 PM PDT 24
Peak memory 206752 kb
Host smart-c3d22c76-bee0-4a51-9154-592bf383018b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1187276140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1187276140
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.733894118
Short name T2421
Test name
Test status
Simulation time 4353319328 ps
CPU time 4.84 seconds
Started Jul 13 07:16:57 PM PDT 24
Finished Jul 13 07:17:10 PM PDT 24
Peak memory 206892 kb
Host smart-efcad9fc-a75d-4ae2-8456-8702b30cb50d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=733894118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.733894118
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1960575091
Short name T2639
Test name
Test status
Simulation time 13313173518 ps
CPU time 12.39 seconds
Started Jul 13 07:17:01 PM PDT 24
Finished Jul 13 07:17:23 PM PDT 24
Peak memory 206872 kb
Host smart-01e641a3-4c97-4df6-b439-f6dc31761e7b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1960575091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1960575091
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.956056242
Short name T492
Test name
Test status
Simulation time 23364551750 ps
CPU time 24.42 seconds
Started Jul 13 07:17:03 PM PDT 24
Finished Jul 13 07:17:39 PM PDT 24
Peak memory 206672 kb
Host smart-9ca20a60-685f-4bd4-9f02-ad9600b81a92
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=956056242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.956056242
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.67955798
Short name T2160
Test name
Test status
Simulation time 188305556 ps
CPU time 0.93 seconds
Started Jul 13 07:16:58 PM PDT 24
Finished Jul 13 07:17:07 PM PDT 24
Peak memory 206864 kb
Host smart-3a50b493-8f15-4459-8963-06fe09b37265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67955
798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.67955798
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.4108593480
Short name T1540
Test name
Test status
Simulation time 173072187 ps
CPU time 0.86 seconds
Started Jul 13 07:16:55 PM PDT 24
Finished Jul 13 07:17:08 PM PDT 24
Peak memory 206864 kb
Host smart-ee0ab350-2130-471b-9841-515a23fab548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085
93480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.4108593480
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.4252818664
Short name T709
Test name
Test status
Simulation time 239346917 ps
CPU time 0.98 seconds
Started Jul 13 07:16:55 PM PDT 24
Finished Jul 13 07:17:01 PM PDT 24
Peak memory 206864 kb
Host smart-d7bc88f5-320d-4352-8c0f-ba37b9c1a51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42528
18664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.4252818664
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2597702008
Short name T2504
Test name
Test status
Simulation time 11305038867 ps
CPU time 20.3 seconds
Started Jul 13 07:17:01 PM PDT 24
Finished Jul 13 07:17:31 PM PDT 24
Peak memory 207068 kb
Host smart-f70c6d69-a44c-4115-bc3e-f740775775e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25977
02008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2597702008
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.4241219257
Short name T2495
Test name
Test status
Simulation time 354158151 ps
CPU time 1.09 seconds
Started Jul 13 07:16:55 PM PDT 24
Finished Jul 13 07:17:01 PM PDT 24
Peak memory 206840 kb
Host smart-9ede78dc-d346-48b4-852d-3064fc46f975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42412
19257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.4241219257
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.468073290
Short name T799
Test name
Test status
Simulation time 142434579 ps
CPU time 0.74 seconds
Started Jul 13 07:16:56 PM PDT 24
Finished Jul 13 07:17:03 PM PDT 24
Peak memory 206816 kb
Host smart-62d9a975-4673-4311-9cf6-47121b2e0f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46807
3290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.468073290
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1058674901
Short name T878
Test name
Test status
Simulation time 40903089 ps
CPU time 0.65 seconds
Started Jul 13 07:16:57 PM PDT 24
Finished Jul 13 07:17:06 PM PDT 24
Peak memory 206796 kb
Host smart-401194b0-ba9f-40a7-98f6-b0ce8d80b319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10586
74901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1058674901
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1271172424
Short name T1830
Test name
Test status
Simulation time 754958443 ps
CPU time 1.92 seconds
Started Jul 13 07:16:52 PM PDT 24
Finished Jul 13 07:16:57 PM PDT 24
Peak memory 207012 kb
Host smart-57a56819-aeb6-4e79-b144-f6ac9fea8292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
72424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1271172424
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1979805068
Short name T2637
Test name
Test status
Simulation time 247121218 ps
CPU time 1.66 seconds
Started Jul 13 07:16:57 PM PDT 24
Finished Jul 13 07:17:06 PM PDT 24
Peak memory 207056 kb
Host smart-362c026a-5467-47c5-85c3-7dff297f87c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19798
05068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1979805068
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2280256267
Short name T1018
Test name
Test status
Simulation time 199023153 ps
CPU time 0.9 seconds
Started Jul 13 07:16:54 PM PDT 24
Finished Jul 13 07:17:01 PM PDT 24
Peak memory 206864 kb
Host smart-5778a2c5-8f89-4ea6-bb5d-1af3ed92b6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22802
56267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2280256267
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2629319672
Short name T2640
Test name
Test status
Simulation time 138866818 ps
CPU time 0.79 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:09 PM PDT 24
Peak memory 206848 kb
Host smart-d23ef2e4-f277-448a-a539-4988972a4782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26293
19672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2629319672
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1966644634
Short name T1570
Test name
Test status
Simulation time 231610333 ps
CPU time 0.97 seconds
Started Jul 13 07:16:52 PM PDT 24
Finished Jul 13 07:16:57 PM PDT 24
Peak memory 206860 kb
Host smart-79bf0ee4-731a-4fd1-9270-1c09a5662c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19666
44634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1966644634
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.2321850602
Short name T680
Test name
Test status
Simulation time 7734470396 ps
CPU time 56.08 seconds
Started Jul 13 07:16:55 PM PDT 24
Finished Jul 13 07:17:58 PM PDT 24
Peak memory 207128 kb
Host smart-86783693-60b2-476f-b050-a732c5ece54a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2321850602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.2321850602
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1398517585
Short name T1050
Test name
Test status
Simulation time 5223768700 ps
CPU time 16.59 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:17:28 PM PDT 24
Peak memory 207144 kb
Host smart-fe52690a-a247-4e98-90a2-8ee2719802da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13985
17585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1398517585
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.898803652
Short name T806
Test name
Test status
Simulation time 203075055 ps
CPU time 0.81 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:11 PM PDT 24
Peak memory 206804 kb
Host smart-ad6c8ce9-8fb1-42c3-b0c2-33bfe36853f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89880
3652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.898803652
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.326948800
Short name T1819
Test name
Test status
Simulation time 23389010306 ps
CPU time 21.67 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:17:19 PM PDT 24
Peak memory 206928 kb
Host smart-7339eeab-e139-4361-a953-d7789b4ae661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32694
8800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.326948800
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1069617612
Short name T2593
Test name
Test status
Simulation time 3362798667 ps
CPU time 3.71 seconds
Started Jul 13 07:17:05 PM PDT 24
Finished Jul 13 07:17:20 PM PDT 24
Peak memory 206868 kb
Host smart-a9d5ed1a-448e-4b9c-afd3-4f2d6ce4e6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10696
17612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1069617612
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3940316701
Short name T140
Test name
Test status
Simulation time 11416706398 ps
CPU time 328.17 seconds
Started Jul 13 07:16:53 PM PDT 24
Finished Jul 13 07:22:25 PM PDT 24
Peak memory 207144 kb
Host smart-ba51b12d-a6d0-47d4-a28f-a5ab9be1331c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39403
16701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3940316701
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.1598287100
Short name T1947
Test name
Test status
Simulation time 4040619778 ps
CPU time 37.24 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:17:50 PM PDT 24
Peak memory 207164 kb
Host smart-6c32eb7b-5489-41db-8008-bda0f9a15ea7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1598287100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.1598287100
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.271134850
Short name T2603
Test name
Test status
Simulation time 250623089 ps
CPU time 0.94 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:17:13 PM PDT 24
Peak memory 206852 kb
Host smart-f987a0c9-14c6-4258-8b31-f4b3ea5ab7ee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=271134850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.271134850
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.869572580
Short name T1728
Test name
Test status
Simulation time 190551607 ps
CPU time 0.83 seconds
Started Jul 13 07:17:01 PM PDT 24
Finished Jul 13 07:17:11 PM PDT 24
Peak memory 207052 kb
Host smart-1ecb57e3-01ea-4a4a-9eca-1c5e361e117a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86957
2580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.869572580
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2283679060
Short name T634
Test name
Test status
Simulation time 4510134814 ps
CPU time 122.35 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:19:15 PM PDT 24
Peak memory 207068 kb
Host smart-8cf783cb-859a-4bc2-904d-b09056fc5616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22836
79060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2283679060
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3439441267
Short name T2120
Test name
Test status
Simulation time 4033449784 ps
CPU time 37.94 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:48 PM PDT 24
Peak memory 207136 kb
Host smart-2fe8d031-2b93-446e-bf78-753af56db273
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3439441267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3439441267
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2533447274
Short name T2189
Test name
Test status
Simulation time 213046121 ps
CPU time 0.88 seconds
Started Jul 13 07:17:03 PM PDT 24
Finished Jul 13 07:17:15 PM PDT 24
Peak memory 206876 kb
Host smart-2d81a274-356b-4b96-bae5-f18edf992e89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2533447274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2533447274
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1891141537
Short name T1943
Test name
Test status
Simulation time 155805792 ps
CPU time 0.8 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:09 PM PDT 24
Peak memory 206868 kb
Host smart-108b35d0-ccc8-4065-aa42-af3d94e2f674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18911
41537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1891141537
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3672615940
Short name T110
Test name
Test status
Simulation time 156866897 ps
CPU time 0.81 seconds
Started Jul 13 07:16:57 PM PDT 24
Finished Jul 13 07:17:06 PM PDT 24
Peak memory 206868 kb
Host smart-b86eaa4f-2838-45ab-8418-c39dff0ff06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36726
15940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3672615940
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2570108769
Short name T1686
Test name
Test status
Simulation time 204133315 ps
CPU time 0.93 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:11 PM PDT 24
Peak memory 206876 kb
Host smart-520cb973-3209-4aab-9764-e794e65c6478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25701
08769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2570108769
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2880940888
Short name T2150
Test name
Test status
Simulation time 173713374 ps
CPU time 0.82 seconds
Started Jul 13 07:17:04 PM PDT 24
Finished Jul 13 07:17:17 PM PDT 24
Peak memory 206864 kb
Host smart-3f91225b-2d96-4a0c-81b0-9e1b7ce3b3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28809
40888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2880940888
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2885343679
Short name T2128
Test name
Test status
Simulation time 186168345 ps
CPU time 0.86 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:10 PM PDT 24
Peak memory 206848 kb
Host smart-f1b25c4f-3321-4093-8fb9-c9abddb21ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28853
43679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2885343679
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3320552656
Short name T961
Test name
Test status
Simulation time 152253109 ps
CPU time 0.81 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:10 PM PDT 24
Peak memory 206860 kb
Host smart-3136cb83-c7f4-4d58-9892-1e35f6e41a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33205
52656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3320552656
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2978780159
Short name T626
Test name
Test status
Simulation time 203723500 ps
CPU time 0.87 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:09 PM PDT 24
Peak memory 206876 kb
Host smart-466b3ddf-4170-45f1-bacf-3845ce5d2787
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2978780159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2978780159
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.818443658
Short name T2750
Test name
Test status
Simulation time 149868384 ps
CPU time 0.79 seconds
Started Jul 13 07:16:59 PM PDT 24
Finished Jul 13 07:17:08 PM PDT 24
Peak memory 206864 kb
Host smart-efb822fb-a092-4cfa-b08e-388b70209d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81844
3658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.818443658
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2479342118
Short name T903
Test name
Test status
Simulation time 47588584 ps
CPU time 0.78 seconds
Started Jul 13 07:17:01 PM PDT 24
Finished Jul 13 07:17:11 PM PDT 24
Peak memory 206864 kb
Host smart-ad2e8107-0f09-4a58-ba66-07ffcb1dbfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24793
42118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2479342118
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3021490865
Short name T224
Test name
Test status
Simulation time 20138203541 ps
CPU time 41.09 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:17:53 PM PDT 24
Peak memory 207160 kb
Host smart-7aa2d9b4-32a1-4060-b681-69d3bdd59777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30214
90865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3021490865
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1473191876
Short name T1177
Test name
Test status
Simulation time 150359303 ps
CPU time 0.78 seconds
Started Jul 13 07:17:04 PM PDT 24
Finished Jul 13 07:17:16 PM PDT 24
Peak memory 206868 kb
Host smart-2aac26d0-3c69-4070-b392-789aaa15cd8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14731
91876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1473191876
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2123883356
Short name T1170
Test name
Test status
Simulation time 237466259 ps
CPU time 0.93 seconds
Started Jul 13 07:17:04 PM PDT 24
Finished Jul 13 07:17:16 PM PDT 24
Peak memory 206880 kb
Host smart-71f8c75c-566f-42d8-bb40-02e2b30038c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21238
83356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2123883356
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.140959027
Short name T2692
Test name
Test status
Simulation time 221675506 ps
CPU time 0.89 seconds
Started Jul 13 07:17:05 PM PDT 24
Finished Jul 13 07:17:17 PM PDT 24
Peak memory 207108 kb
Host smart-d6cbd131-eff8-4fb0-8207-a7a893487f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14095
9027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.140959027
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.2214116374
Short name T987
Test name
Test status
Simulation time 193568696 ps
CPU time 0.88 seconds
Started Jul 13 07:17:01 PM PDT 24
Finished Jul 13 07:17:12 PM PDT 24
Peak memory 206852 kb
Host smart-7e50cbc0-bdd6-42ed-a936-301e19569a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22141
16374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.2214116374
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2535055183
Short name T725
Test name
Test status
Simulation time 162811948 ps
CPU time 0.8 seconds
Started Jul 13 07:16:59 PM PDT 24
Finished Jul 13 07:17:09 PM PDT 24
Peak memory 206864 kb
Host smart-64be7fe8-ebc5-4a9c-b84e-f3a3f952dbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25350
55183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2535055183
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1083211214
Short name T1959
Test name
Test status
Simulation time 160067930 ps
CPU time 0.79 seconds
Started Jul 13 07:17:04 PM PDT 24
Finished Jul 13 07:17:16 PM PDT 24
Peak memory 206860 kb
Host smart-9629f4aa-51a5-4610-84a6-628d62515fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10832
11214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1083211214
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2537097733
Short name T2021
Test name
Test status
Simulation time 150789499 ps
CPU time 0.81 seconds
Started Jul 13 07:17:03 PM PDT 24
Finished Jul 13 07:17:15 PM PDT 24
Peak memory 206868 kb
Host smart-c08afd3f-adae-41bc-a051-395dc310b94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25370
97733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2537097733
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2940120191
Short name T2691
Test name
Test status
Simulation time 235221077 ps
CPU time 0.93 seconds
Started Jul 13 07:17:03 PM PDT 24
Finished Jul 13 07:17:15 PM PDT 24
Peak memory 206880 kb
Host smart-569f69fc-3e3b-4209-a86e-1ad645840234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29401
20191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2940120191
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.1316789906
Short name T1428
Test name
Test status
Simulation time 4850258526 ps
CPU time 42.26 seconds
Started Jul 13 07:17:00 PM PDT 24
Finished Jul 13 07:17:51 PM PDT 24
Peak memory 207064 kb
Host smart-fec1870c-0226-44ab-bc84-fe94f8d2144a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1316789906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.1316789906
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4151363781
Short name T658
Test name
Test status
Simulation time 185499397 ps
CPU time 0.87 seconds
Started Jul 13 07:17:01 PM PDT 24
Finished Jul 13 07:17:11 PM PDT 24
Peak memory 206872 kb
Host smart-ee05df9a-143e-4420-b8e2-ec4f8f8fba56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41513
63781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4151363781
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1120152691
Short name T2580
Test name
Test status
Simulation time 189885568 ps
CPU time 0.84 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:17:13 PM PDT 24
Peak memory 206860 kb
Host smart-b64a7af4-0bb3-4696-920e-f9ded660e265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11201
52691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1120152691
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.4234288910
Short name T1302
Test name
Test status
Simulation time 730921014 ps
CPU time 1.66 seconds
Started Jul 13 07:17:05 PM PDT 24
Finished Jul 13 07:17:18 PM PDT 24
Peak memory 207304 kb
Host smart-413aba0f-82b9-406c-b5ae-8fee5965c8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42342
88910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.4234288910
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.88318940
Short name T1074
Test name
Test status
Simulation time 4047978436 ps
CPU time 36.97 seconds
Started Jul 13 07:17:02 PM PDT 24
Finished Jul 13 07:17:50 PM PDT 24
Peak memory 207060 kb
Host smart-9df05820-6c13-4202-bd78-89197f4a6fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88318
940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.88318940
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3547395272
Short name T168
Test name
Test status
Simulation time 66521403 ps
CPU time 0.7 seconds
Started Jul 13 07:17:15 PM PDT 24
Finished Jul 13 07:17:31 PM PDT 24
Peak memory 206908 kb
Host smart-0c4bad58-a521-4866-8499-a5ce8a5d8d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3547395272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3547395272
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3895352652
Short name T936
Test name
Test status
Simulation time 4293963631 ps
CPU time 5.35 seconds
Started Jul 13 07:17:06 PM PDT 24
Finished Jul 13 07:17:23 PM PDT 24
Peak memory 207052 kb
Host smart-b4846741-ffb1-459d-a695-7978619fdc64
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3895352652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3895352652
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.4174678022
Short name T906
Test name
Test status
Simulation time 13368331431 ps
CPU time 14.86 seconds
Started Jul 13 07:17:07 PM PDT 24
Finished Jul 13 07:17:34 PM PDT 24
Peak memory 207132 kb
Host smart-798b0f16-f3b3-48d0-b5db-2a18f04db150
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4174678022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.4174678022
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3302478974
Short name T933
Test name
Test status
Simulation time 23334040511 ps
CPU time 24.01 seconds
Started Jul 13 07:17:11 PM PDT 24
Finished Jul 13 07:17:49 PM PDT 24
Peak memory 207148 kb
Host smart-00db9bab-4759-4f5a-87cb-0e0812ed12fe
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3302478974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3302478974
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1922663998
Short name T393
Test name
Test status
Simulation time 180213549 ps
CPU time 0.82 seconds
Started Jul 13 07:17:08 PM PDT 24
Finished Jul 13 07:17:21 PM PDT 24
Peak memory 206808 kb
Host smart-e8e6adfc-0746-476f-8c63-9cb9d162e634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19226
63998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1922663998
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2667452357
Short name T2367
Test name
Test status
Simulation time 233048196 ps
CPU time 0.87 seconds
Started Jul 13 07:17:08 PM PDT 24
Finished Jul 13 07:17:21 PM PDT 24
Peak memory 206868 kb
Host smart-583a432b-8728-4325-ac28-0e921595ab1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26674
52357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2667452357
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1944809882
Short name T97
Test name
Test status
Simulation time 216434197 ps
CPU time 0.96 seconds
Started Jul 13 07:17:21 PM PDT 24
Finished Jul 13 07:17:41 PM PDT 24
Peak memory 206868 kb
Host smart-a54df801-83b6-44f0-a239-da120a01312c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19448
09882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1944809882
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2724711872
Short name T1080
Test name
Test status
Simulation time 1070133367 ps
CPU time 2.43 seconds
Started Jul 13 07:17:16 PM PDT 24
Finished Jul 13 07:17:34 PM PDT 24
Peak memory 207020 kb
Host smart-fedeed5c-7a9b-42fe-8750-58e88854612a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27247
11872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2724711872
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1839926457
Short name T482
Test name
Test status
Simulation time 19388940652 ps
CPU time 35.36 seconds
Started Jul 13 07:17:08 PM PDT 24
Finished Jul 13 07:17:56 PM PDT 24
Peak memory 207132 kb
Host smart-fb643b80-173d-4652-bbea-4f3ebbaae463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18399
26457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1839926457
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.842523824
Short name T1398
Test name
Test status
Simulation time 317914030 ps
CPU time 1.13 seconds
Started Jul 13 07:17:16 PM PDT 24
Finished Jul 13 07:17:33 PM PDT 24
Peak memory 206872 kb
Host smart-989f8384-30f4-47c4-b2de-bb367bbc6932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84252
3824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.842523824
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3371237779
Short name T2159
Test name
Test status
Simulation time 141602717 ps
CPU time 0.79 seconds
Started Jul 13 07:17:08 PM PDT 24
Finished Jul 13 07:17:21 PM PDT 24
Peak memory 206804 kb
Host smart-cb3799f0-3661-480e-8ee3-148d6a33188d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33712
37779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3371237779
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3335826555
Short name T2720
Test name
Test status
Simulation time 87481108 ps
CPU time 0.71 seconds
Started Jul 13 07:17:14 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 206884 kb
Host smart-0b866496-de70-4c04-aead-3970496f68f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33358
26555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3335826555
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2667430489
Short name T87
Test name
Test status
Simulation time 941367693 ps
CPU time 2.1 seconds
Started Jul 13 07:17:07 PM PDT 24
Finished Jul 13 07:17:21 PM PDT 24
Peak memory 207012 kb
Host smart-5e9c5e94-93f8-421f-a791-6dc91cd5a3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26674
30489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2667430489
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.322774574
Short name T1768
Test name
Test status
Simulation time 278888431 ps
CPU time 2 seconds
Started Jul 13 07:17:11 PM PDT 24
Finished Jul 13 07:17:27 PM PDT 24
Peak memory 207004 kb
Host smart-d9e43865-aaa6-4b48-8c0f-cb9ab5178c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32277
4574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.322774574
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3517248405
Short name T1583
Test name
Test status
Simulation time 220212774 ps
CPU time 0.88 seconds
Started Jul 13 07:17:07 PM PDT 24
Finished Jul 13 07:17:20 PM PDT 24
Peak memory 206900 kb
Host smart-fe746b03-4d91-44d5-947c-79fa217a77f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35172
48405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3517248405
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1334200812
Short name T789
Test name
Test status
Simulation time 143848105 ps
CPU time 0.82 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:17:22 PM PDT 24
Peak memory 206776 kb
Host smart-b35dacbb-c63d-4fea-a509-24c38d6b9bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13342
00812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1334200812
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1717572081
Short name T1865
Test name
Test status
Simulation time 161637275 ps
CPU time 0.83 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:17:24 PM PDT 24
Peak memory 206876 kb
Host smart-1e1de763-6427-491c-ae86-9c3a725c4113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17175
72081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1717572081
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.3306856795
Short name T2269
Test name
Test status
Simulation time 6069017699 ps
CPU time 167.71 seconds
Started Jul 13 07:17:07 PM PDT 24
Finished Jul 13 07:20:07 PM PDT 24
Peak memory 207068 kb
Host smart-29e36c0a-8400-401c-930e-fd439266d37e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3306856795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.3306856795
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.1376949396
Short name T773
Test name
Test status
Simulation time 4828687105 ps
CPU time 32.87 seconds
Started Jul 13 07:17:10 PM PDT 24
Finished Jul 13 07:17:56 PM PDT 24
Peak memory 207368 kb
Host smart-d7fea6f7-4c3f-4225-9b34-a35454c1c2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13769
49396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.1376949396
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.571702490
Short name T812
Test name
Test status
Simulation time 226621156 ps
CPU time 0.93 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:17:23 PM PDT 24
Peak memory 206300 kb
Host smart-5711f788-77a9-4441-84b2-39d10817359e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57170
2490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.571702490
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3637109272
Short name T1706
Test name
Test status
Simulation time 23276236463 ps
CPU time 26.75 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:17:49 PM PDT 24
Peak memory 206908 kb
Host smart-2f456b4c-14f0-4819-8fbf-829f8263b868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36371
09272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3637109272
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2408234846
Short name T582
Test name
Test status
Simulation time 3308868096 ps
CPU time 4.44 seconds
Started Jul 13 07:17:08 PM PDT 24
Finished Jul 13 07:17:25 PM PDT 24
Peak memory 206916 kb
Host smart-35584204-3b4d-4c51-82a2-7fea19895f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24082
34846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2408234846
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2502551593
Short name T2546
Test name
Test status
Simulation time 8957152797 ps
CPU time 249.16 seconds
Started Jul 13 07:17:17 PM PDT 24
Finished Jul 13 07:21:43 PM PDT 24
Peak memory 207136 kb
Host smart-668fc861-14ef-4a76-99d5-a4d7d10ae6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
51593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2502551593
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.315373290
Short name T2149
Test name
Test status
Simulation time 4864441119 ps
CPU time 134.01 seconds
Started Jul 13 07:17:10 PM PDT 24
Finished Jul 13 07:19:38 PM PDT 24
Peak memory 207060 kb
Host smart-9e2038b9-1cb9-4ffe-8708-c5b91122ceeb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=315373290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.315373290
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.4268208604
Short name T1715
Test name
Test status
Simulation time 243937430 ps
CPU time 0.94 seconds
Started Jul 13 07:17:13 PM PDT 24
Finished Jul 13 07:17:28 PM PDT 24
Peak memory 206876 kb
Host smart-6d616ec6-93fc-4937-8f0e-dfa0f9814b8d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4268208604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.4268208604
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2548116083
Short name T2510
Test name
Test status
Simulation time 247292315 ps
CPU time 0.96 seconds
Started Jul 13 07:17:08 PM PDT 24
Finished Jul 13 07:17:21 PM PDT 24
Peak memory 206756 kb
Host smart-d86c89a6-131b-44b3-ada3-82ad2efd6b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25481
16083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2548116083
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.4274721195
Short name T2218
Test name
Test status
Simulation time 4538998328 ps
CPU time 129.75 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:19:32 PM PDT 24
Peak memory 207112 kb
Host smart-38ce6fc9-d912-4634-a0b0-73c4f7387d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42747
21195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.4274721195
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3898580466
Short name T2099
Test name
Test status
Simulation time 4174434227 ps
CPU time 116.27 seconds
Started Jul 13 07:17:12 PM PDT 24
Finished Jul 13 07:19:22 PM PDT 24
Peak memory 207080 kb
Host smart-fe20dadd-185c-4120-ac3a-b597781d8c68
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3898580466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3898580466
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2248628498
Short name T2259
Test name
Test status
Simulation time 161046382 ps
CPU time 0.77 seconds
Started Jul 13 07:17:10 PM PDT 24
Finished Jul 13 07:17:25 PM PDT 24
Peak memory 206872 kb
Host smart-864cbfb2-6c28-4547-b636-6d7ff77587c4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2248628498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2248628498
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2407495819
Short name T2515
Test name
Test status
Simulation time 143902796 ps
CPU time 0.88 seconds
Started Jul 13 07:17:11 PM PDT 24
Finished Jul 13 07:17:26 PM PDT 24
Peak memory 206868 kb
Host smart-04fdb9d1-4d5e-4f93-9503-ab9ae1744ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24074
95819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2407495819
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1277118188
Short name T120
Test name
Test status
Simulation time 223420322 ps
CPU time 0.88 seconds
Started Jul 13 07:17:07 PM PDT 24
Finished Jul 13 07:17:20 PM PDT 24
Peak memory 206884 kb
Host smart-38cc4921-aff3-43a4-a80a-4b4200582731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12771
18188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1277118188
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2652829801
Short name T92
Test name
Test status
Simulation time 228500273 ps
CPU time 0.85 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:17:22 PM PDT 24
Peak memory 206816 kb
Host smart-7e820d5e-f99a-47cc-a511-858b9fb06053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26528
29801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2652829801
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.212244013
Short name T2728
Test name
Test status
Simulation time 161095471 ps
CPU time 0.78 seconds
Started Jul 13 07:17:11 PM PDT 24
Finished Jul 13 07:17:25 PM PDT 24
Peak memory 206856 kb
Host smart-682d792e-e1e5-4cf1-a754-e6b3c66f5bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21224
4013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.212244013
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.653932291
Short name T1971
Test name
Test status
Simulation time 199334043 ps
CPU time 0.82 seconds
Started Jul 13 07:17:08 PM PDT 24
Finished Jul 13 07:17:22 PM PDT 24
Peak memory 207044 kb
Host smart-5313da72-6a1a-493e-8e47-0aea070beeae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65393
2291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.653932291
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.474255632
Short name T2009
Test name
Test status
Simulation time 172583773 ps
CPU time 0.85 seconds
Started Jul 13 07:17:17 PM PDT 24
Finished Jul 13 07:17:34 PM PDT 24
Peak memory 206912 kb
Host smart-c4358081-c710-43b5-8ca5-eafd7a3e502d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47425
5632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.474255632
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3265040422
Short name T1579
Test name
Test status
Simulation time 277202912 ps
CPU time 0.97 seconds
Started Jul 13 07:17:19 PM PDT 24
Finished Jul 13 07:17:37 PM PDT 24
Peak memory 206868 kb
Host smart-493ce2e0-fa89-4a95-8847-50bc9b082701
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3265040422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3265040422
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1600603080
Short name T2676
Test name
Test status
Simulation time 159660134 ps
CPU time 0.78 seconds
Started Jul 13 07:17:15 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 206812 kb
Host smart-eb1d21cb-3dae-4cbb-867f-47fcf715b2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16006
03080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1600603080
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3209544479
Short name T1343
Test name
Test status
Simulation time 34482860 ps
CPU time 0.65 seconds
Started Jul 13 07:17:10 PM PDT 24
Finished Jul 13 07:17:24 PM PDT 24
Peak memory 206864 kb
Host smart-475dbc04-1f64-4c13-bcd0-03259170bebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095
44479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3209544479
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1082706843
Short name T1130
Test name
Test status
Simulation time 17115052248 ps
CPU time 34.75 seconds
Started Jul 13 07:17:13 PM PDT 24
Finished Jul 13 07:18:02 PM PDT 24
Peak memory 207184 kb
Host smart-5306f6d5-3d81-454a-9ded-df808d93e2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10827
06843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1082706843
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.108086456
Short name T1205
Test name
Test status
Simulation time 191999567 ps
CPU time 0.89 seconds
Started Jul 13 07:17:10 PM PDT 24
Finished Jul 13 07:17:25 PM PDT 24
Peak memory 206880 kb
Host smart-a148e174-6c45-4f41-ba3a-502840192529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10808
6456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.108086456
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.610801430
Short name T2036
Test name
Test status
Simulation time 194250701 ps
CPU time 0.86 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:17:23 PM PDT 24
Peak memory 206844 kb
Host smart-554d1c10-8b24-4bc5-a5b5-0037b324fc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61080
1430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.610801430
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.4104678397
Short name T521
Test name
Test status
Simulation time 217385983 ps
CPU time 0.88 seconds
Started Jul 13 07:17:08 PM PDT 24
Finished Jul 13 07:17:22 PM PDT 24
Peak memory 206876 kb
Host smart-20a93812-131b-4512-a02d-f9b21d0a48ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41046
78397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.4104678397
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2207226974
Short name T2644
Test name
Test status
Simulation time 176028918 ps
CPU time 0.86 seconds
Started Jul 13 07:17:10 PM PDT 24
Finished Jul 13 07:17:24 PM PDT 24
Peak memory 206872 kb
Host smart-692523fb-01fa-4f9e-8456-d815e47f0160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22072
26974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2207226974
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2777896105
Short name T1053
Test name
Test status
Simulation time 148709506 ps
CPU time 0.8 seconds
Started Jul 13 07:21:49 PM PDT 24
Finished Jul 13 07:21:51 PM PDT 24
Peak memory 207044 kb
Host smart-13ae3f34-855a-401e-b8d2-3238a732765d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27778
96105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2777896105
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2853995478
Short name T1272
Test name
Test status
Simulation time 165508677 ps
CPU time 0.82 seconds
Started Jul 13 07:17:11 PM PDT 24
Finished Jul 13 07:17:25 PM PDT 24
Peak memory 206872 kb
Host smart-16691fff-12c2-470e-acac-82c364aa11ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
95478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2853995478
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1767720489
Short name T2166
Test name
Test status
Simulation time 146031324 ps
CPU time 0.76 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:17:23 PM PDT 24
Peak memory 206340 kb
Host smart-580f7402-b61b-4468-a178-fc656d612652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17677
20489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1767720489
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2410929080
Short name T767
Test name
Test status
Simulation time 227223007 ps
CPU time 0.89 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:17:24 PM PDT 24
Peak memory 206864 kb
Host smart-dc7f29a3-a8be-4aa4-9ba4-f4e55bac6d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24109
29080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2410929080
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.317250441
Short name T535
Test name
Test status
Simulation time 5289805260 ps
CPU time 146.42 seconds
Started Jul 13 07:17:09 PM PDT 24
Finished Jul 13 07:19:49 PM PDT 24
Peak memory 207012 kb
Host smart-13aa01ba-eace-4645-bd8f-c1b9a2079f7d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=317250441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.317250441
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.313706899
Short name T1679
Test name
Test status
Simulation time 175809578 ps
CPU time 0.84 seconds
Started Jul 13 07:17:07 PM PDT 24
Finished Jul 13 07:17:20 PM PDT 24
Peak memory 206868 kb
Host smart-8f54c163-a605-461d-86aa-cee3e17cc0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31370
6899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.313706899
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2768836267
Short name T2030
Test name
Test status
Simulation time 194669706 ps
CPU time 0.86 seconds
Started Jul 13 07:17:14 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 206880 kb
Host smart-463eec54-1ad3-4e70-a8f3-a980ec090b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27688
36267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2768836267
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3849488363
Short name T890
Test name
Test status
Simulation time 892769132 ps
CPU time 2.11 seconds
Started Jul 13 07:17:10 PM PDT 24
Finished Jul 13 07:17:26 PM PDT 24
Peak memory 207044 kb
Host smart-2a736683-d306-4f32-8ce2-9f6390345e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494
88363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3849488363
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.195379993
Short name T2165
Test name
Test status
Simulation time 4949335985 ps
CPU time 135.95 seconds
Started Jul 13 07:17:19 PM PDT 24
Finished Jul 13 07:19:52 PM PDT 24
Peak memory 207080 kb
Host smart-243f0fc3-39a1-4b85-ab7b-f0c46566cc83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19537
9993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.195379993
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.971071290
Short name T2575
Test name
Test status
Simulation time 35280341 ps
CPU time 0.68 seconds
Started Jul 13 07:17:35 PM PDT 24
Finished Jul 13 07:18:03 PM PDT 24
Peak memory 206904 kb
Host smart-0a5709ab-eb55-4106-914c-6a54d80d5f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=971071290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.971071290
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1812023836
Short name T2139
Test name
Test status
Simulation time 3558587989 ps
CPU time 4.31 seconds
Started Jul 13 07:17:10 PM PDT 24
Finished Jul 13 07:17:28 PM PDT 24
Peak memory 207016 kb
Host smart-e3ede25f-32a9-46c1-870f-cadc394ecb3e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1812023836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.1812023836
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3335598441
Short name T842
Test name
Test status
Simulation time 13336821219 ps
CPU time 11.93 seconds
Started Jul 13 07:17:15 PM PDT 24
Finished Jul 13 07:17:43 PM PDT 24
Peak memory 207080 kb
Host smart-e6db3389-817b-4d17-be0a-eed151c348d1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3335598441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3335598441
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.2647847517
Short name T79
Test name
Test status
Simulation time 23353722804 ps
CPU time 23.11 seconds
Started Jul 13 07:17:12 PM PDT 24
Finished Jul 13 07:17:50 PM PDT 24
Peak memory 207136 kb
Host smart-22ebf6c2-29d1-480f-baa7-21b56198b474
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2647847517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.2647847517
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1392216898
Short name T1607
Test name
Test status
Simulation time 170287887 ps
CPU time 0.82 seconds
Started Jul 13 07:17:15 PM PDT 24
Finished Jul 13 07:17:31 PM PDT 24
Peak memory 206856 kb
Host smart-a706ff08-23f7-40d9-afec-2cd06be8526c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13922
16898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1392216898
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.14277112
Short name T76
Test name
Test status
Simulation time 178732675 ps
CPU time 0.88 seconds
Started Jul 13 07:17:17 PM PDT 24
Finished Jul 13 07:17:34 PM PDT 24
Peak memory 206900 kb
Host smart-14825173-177b-408f-8ef7-b842460277bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14277
112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.14277112
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1062902056
Short name T1827
Test name
Test status
Simulation time 224779867 ps
CPU time 0.92 seconds
Started Jul 13 07:17:19 PM PDT 24
Finished Jul 13 07:17:37 PM PDT 24
Peak memory 206860 kb
Host smart-17f20567-6b62-41d7-ad90-2e763bee830e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10629
02056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1062902056
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.1454504273
Short name T671
Test name
Test status
Simulation time 404017899 ps
CPU time 1.09 seconds
Started Jul 13 07:17:30 PM PDT 24
Finished Jul 13 07:17:54 PM PDT 24
Peak memory 206900 kb
Host smart-d11617e4-f88f-4bdd-90db-6a50d308bed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14545
04273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.1454504273
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3290366671
Short name T477
Test name
Test status
Simulation time 16633855993 ps
CPU time 30.31 seconds
Started Jul 13 07:17:14 PM PDT 24
Finished Jul 13 07:17:59 PM PDT 24
Peak memory 207080 kb
Host smart-387f147c-46e2-4564-b2b7-38df2178bb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32903
66671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3290366671
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.332069344
Short name T86
Test name
Test status
Simulation time 473918015 ps
CPU time 1.39 seconds
Started Jul 13 07:17:14 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 206864 kb
Host smart-3643d27e-30b5-4a06-9655-18197c06bf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33206
9344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.332069344
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3325073013
Short name T1551
Test name
Test status
Simulation time 145991659 ps
CPU time 0.79 seconds
Started Jul 13 07:17:14 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 206868 kb
Host smart-efba53d4-5384-4ee5-87c1-ace263689fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33250
73013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3325073013
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2698255445
Short name T1480
Test name
Test status
Simulation time 35750757 ps
CPU time 0.65 seconds
Started Jul 13 07:17:16 PM PDT 24
Finished Jul 13 07:17:32 PM PDT 24
Peak memory 206864 kb
Host smart-9f184182-6933-4529-a749-f7b90efbf931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26982
55445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2698255445
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3258174550
Short name T551
Test name
Test status
Simulation time 769018881 ps
CPU time 1.99 seconds
Started Jul 13 07:17:13 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 207048 kb
Host smart-cd8f5586-b221-4ba9-b6de-66963a20e828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32581
74550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3258174550
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.4213083339
Short name T1737
Test name
Test status
Simulation time 318455591 ps
CPU time 2.03 seconds
Started Jul 13 07:17:13 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 207060 kb
Host smart-615df4ab-e2ff-41cf-b929-7435c286bae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42130
83339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4213083339
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.663131738
Short name T1153
Test name
Test status
Simulation time 233520787 ps
CPU time 0.93 seconds
Started Jul 13 07:17:13 PM PDT 24
Finished Jul 13 07:17:28 PM PDT 24
Peak memory 206864 kb
Host smart-a552ead7-0377-43af-a0d5-bd4953c74e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66313
1738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.663131738
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.470700663
Short name T2519
Test name
Test status
Simulation time 164324137 ps
CPU time 0.79 seconds
Started Jul 13 07:17:14 PM PDT 24
Finished Jul 13 07:17:30 PM PDT 24
Peak memory 206836 kb
Host smart-caac11b1-9c90-4d9a-9eb7-d18a61c8cdf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47070
0663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.470700663
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.928782183
Short name T2570
Test name
Test status
Simulation time 227432654 ps
CPU time 0.95 seconds
Started Jul 13 07:17:24 PM PDT 24
Finished Jul 13 07:17:45 PM PDT 24
Peak memory 206868 kb
Host smart-5e6d4fa1-30ac-46a8-b785-7e14023ed4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92878
2183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.928782183
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1391962170
Short name T980
Test name
Test status
Simulation time 5462654213 ps
CPU time 52.63 seconds
Started Jul 13 07:17:19 PM PDT 24
Finished Jul 13 07:18:28 PM PDT 24
Peak memory 207124 kb
Host smart-9122724a-8b91-4b3a-9269-c89642ea5548
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1391962170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1391962170
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.1530980174
Short name T2193
Test name
Test status
Simulation time 11539600317 ps
CPU time 48.4 seconds
Started Jul 13 07:17:24 PM PDT 24
Finished Jul 13 07:18:33 PM PDT 24
Peak memory 207052 kb
Host smart-c045d763-eaa4-4739-be14-de08a9ba2809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15309
80174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.1530980174
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.655401944
Short name T1233
Test name
Test status
Simulation time 218528815 ps
CPU time 0.9 seconds
Started Jul 13 07:17:19 PM PDT 24
Finished Jul 13 07:17:36 PM PDT 24
Peak memory 206872 kb
Host smart-ae6d3838-9320-466c-b177-fa71c26d682c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65540
1944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.655401944
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3770384162
Short name T2485
Test name
Test status
Simulation time 23344713355 ps
CPU time 24.1 seconds
Started Jul 13 07:17:15 PM PDT 24
Finished Jul 13 07:17:54 PM PDT 24
Peak memory 206908 kb
Host smart-6f11dd10-e202-4889-baf1-9b14a9a4e151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37703
84162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3770384162
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3968656933
Short name T964
Test name
Test status
Simulation time 3285808895 ps
CPU time 3.79 seconds
Started Jul 13 07:17:29 PM PDT 24
Finished Jul 13 07:17:57 PM PDT 24
Peak memory 206952 kb
Host smart-d5c1ef41-efb3-47fc-b0be-d55144519c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39686
56933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3968656933
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2396914296
Short name T430
Test name
Test status
Simulation time 8371243684 ps
CPU time 233.27 seconds
Started Jul 13 07:17:15 PM PDT 24
Finished Jul 13 07:21:23 PM PDT 24
Peak memory 207128 kb
Host smart-9bfe48e4-0c18-4202-89ed-1e324969bf11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23969
14296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2396914296
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.343804557
Short name T2045
Test name
Test status
Simulation time 5927030908 ps
CPU time 151.36 seconds
Started Jul 13 07:17:15 PM PDT 24
Finished Jul 13 07:20:02 PM PDT 24
Peak memory 207060 kb
Host smart-0d294a9c-328f-4086-ac9e-71d36cca1be3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=343804557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.343804557
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.44409323
Short name T1516
Test name
Test status
Simulation time 259755970 ps
CPU time 0.94 seconds
Started Jul 13 07:17:15 PM PDT 24
Finished Jul 13 07:17:31 PM PDT 24
Peak memory 206884 kb
Host smart-2a054111-48bd-4c0a-9cd1-c789a57808c3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=44409323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.44409323
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2929022301
Short name T1675
Test name
Test status
Simulation time 190706879 ps
CPU time 0.88 seconds
Started Jul 13 07:17:18 PM PDT 24
Finished Jul 13 07:17:36 PM PDT 24
Peak memory 206848 kb
Host smart-5501ebd0-2df9-453e-a41a-5aed2e6d5402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29290
22301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2929022301
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1294922239
Short name T304
Test name
Test status
Simulation time 4402178046 ps
CPU time 125.55 seconds
Started Jul 13 07:17:27 PM PDT 24
Finished Jul 13 07:19:54 PM PDT 24
Peak memory 207104 kb
Host smart-8c980b16-4c79-4d98-abfb-4134d8c879e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12949
22239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1294922239
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.670668728
Short name T1326
Test name
Test status
Simulation time 5710216166 ps
CPU time 158.71 seconds
Started Jul 13 07:17:12 PM PDT 24
Finished Jul 13 07:20:06 PM PDT 24
Peak memory 207084 kb
Host smart-b0d963d5-480c-48d4-8a28-c970f1e81545
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=670668728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.670668728
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.3487584515
Short name T1751
Test name
Test status
Simulation time 172322910 ps
CPU time 0.79 seconds
Started Jul 13 07:17:19 PM PDT 24
Finished Jul 13 07:17:36 PM PDT 24
Peak memory 206848 kb
Host smart-1bbb6abb-66b3-4c5a-8dcf-ec1034f595e7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3487584515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.3487584515
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3894665156
Short name T2057
Test name
Test status
Simulation time 149958314 ps
CPU time 0.77 seconds
Started Jul 13 07:17:16 PM PDT 24
Finished Jul 13 07:17:31 PM PDT 24
Peak memory 206808 kb
Host smart-641f89c3-a964-4ca7-a0fb-e03d05c9bf76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38946
65156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3894665156
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1421986191
Short name T113
Test name
Test status
Simulation time 205714290 ps
CPU time 0.88 seconds
Started Jul 13 07:17:27 PM PDT 24
Finished Jul 13 07:17:50 PM PDT 24
Peak memory 206904 kb
Host smart-ef8ecf75-4d4d-46b8-b7cb-ff08e533523e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
86191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1421986191
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.559891496
Short name T1847
Test name
Test status
Simulation time 194183193 ps
CPU time 0.86 seconds
Started Jul 13 07:17:12 PM PDT 24
Finished Jul 13 07:17:27 PM PDT 24
Peak memory 206864 kb
Host smart-5e0565b6-9164-4c66-8e55-ed62e39d78b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55989
1496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.559891496
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3901295864
Short name T743
Test name
Test status
Simulation time 170376534 ps
CPU time 0.8 seconds
Started Jul 13 07:17:25 PM PDT 24
Finished Jul 13 07:17:47 PM PDT 24
Peak memory 206816 kb
Host smart-097e9d7d-5f3d-4d44-b431-71f8b066a4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
95864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3901295864
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1830372373
Short name T2749
Test name
Test status
Simulation time 166626044 ps
CPU time 0.76 seconds
Started Jul 13 07:17:31 PM PDT 24
Finished Jul 13 07:17:56 PM PDT 24
Peak memory 206904 kb
Host smart-42fdee55-76eb-4f93-bdbc-b77945280d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18303
72373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1830372373
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.399660525
Short name T2531
Test name
Test status
Simulation time 171485660 ps
CPU time 0.79 seconds
Started Jul 13 07:17:25 PM PDT 24
Finished Jul 13 07:17:47 PM PDT 24
Peak memory 206904 kb
Host smart-ba84a7e0-2639-4600-a865-7e5572dc3f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39966
0525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.399660525
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.2382058604
Short name T754
Test name
Test status
Simulation time 219716511 ps
CPU time 0.93 seconds
Started Jul 13 07:17:33 PM PDT 24
Finished Jul 13 07:17:59 PM PDT 24
Peak memory 206876 kb
Host smart-392df4ff-1447-4756-ae27-ecbf013c02b3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2382058604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.2382058604
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2538984159
Short name T991
Test name
Test status
Simulation time 146570502 ps
CPU time 0.78 seconds
Started Jul 13 07:17:31 PM PDT 24
Finished Jul 13 07:17:56 PM PDT 24
Peak memory 206868 kb
Host smart-6a96be7f-f69d-45e3-b95a-440c1950e8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25389
84159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2538984159
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.938652337
Short name T36
Test name
Test status
Simulation time 39921999 ps
CPU time 0.65 seconds
Started Jul 13 07:17:22 PM PDT 24
Finished Jul 13 07:17:41 PM PDT 24
Peak memory 206860 kb
Host smart-ed0456a9-9217-4913-acab-777627a67247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93865
2337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.938652337
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1518845950
Short name T369
Test name
Test status
Simulation time 7457618902 ps
CPU time 17.88 seconds
Started Jul 13 07:17:20 PM PDT 24
Finished Jul 13 07:17:56 PM PDT 24
Peak memory 207164 kb
Host smart-3125ae51-f09b-4124-b0fb-266b90dc5973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15188
45950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1518845950
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3594681295
Short name T1214
Test name
Test status
Simulation time 189095781 ps
CPU time 0.84 seconds
Started Jul 13 07:17:34 PM PDT 24
Finished Jul 13 07:18:01 PM PDT 24
Peak memory 206856 kb
Host smart-a6eeb7e2-c408-4f9d-aa73-657b12ca1a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946
81295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3594681295
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3297841724
Short name T351
Test name
Test status
Simulation time 204030732 ps
CPU time 0.82 seconds
Started Jul 13 07:17:32 PM PDT 24
Finished Jul 13 07:17:59 PM PDT 24
Peak memory 206752 kb
Host smart-191117e8-736e-47e8-80b2-79f00a780572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32978
41724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3297841724
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.2967992435
Short name T1308
Test name
Test status
Simulation time 200420319 ps
CPU time 0.83 seconds
Started Jul 13 07:17:30 PM PDT 24
Finished Jul 13 07:17:54 PM PDT 24
Peak memory 206868 kb
Host smart-d3a4b3e7-d805-4e24-b426-0982695d719e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29679
92435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.2967992435
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3328576334
Short name T1677
Test name
Test status
Simulation time 175843289 ps
CPU time 0.82 seconds
Started Jul 13 07:17:29 PM PDT 24
Finished Jul 13 07:17:54 PM PDT 24
Peak memory 206892 kb
Host smart-6a7d8171-e891-49ef-96cd-65ea3786b5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
76334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3328576334
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3369007726
Short name T604
Test name
Test status
Simulation time 186640287 ps
CPU time 0.86 seconds
Started Jul 13 07:17:29 PM PDT 24
Finished Jul 13 07:17:54 PM PDT 24
Peak memory 206824 kb
Host smart-8f5905c9-5e0a-413e-b5d7-16c103821bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33690
07726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3369007726
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2337173037
Short name T1183
Test name
Test status
Simulation time 150338540 ps
CPU time 0.78 seconds
Started Jul 13 07:17:28 PM PDT 24
Finished Jul 13 07:17:52 PM PDT 24
Peak memory 207100 kb
Host smart-9ab03967-a109-413a-929c-85d6c129b40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23371
73037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2337173037
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.940978515
Short name T2694
Test name
Test status
Simulation time 172057927 ps
CPU time 0.79 seconds
Started Jul 13 07:17:30 PM PDT 24
Finished Jul 13 07:17:56 PM PDT 24
Peak memory 206856 kb
Host smart-853857b9-11e6-4e14-9375-ca8167c279ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94097
8515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.940978515
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3744700065
Short name T2078
Test name
Test status
Simulation time 263463478 ps
CPU time 0.96 seconds
Started Jul 13 07:17:21 PM PDT 24
Finished Jul 13 07:17:40 PM PDT 24
Peak memory 206884 kb
Host smart-9b13279b-89ea-4fcc-b99e-fa1e773943ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37447
00065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3744700065
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.117582687
Short name T771
Test name
Test status
Simulation time 3489040721 ps
CPU time 31.21 seconds
Started Jul 13 07:17:33 PM PDT 24
Finished Jul 13 07:18:29 PM PDT 24
Peak memory 207068 kb
Host smart-99531a01-66ea-4a12-a7d5-56a49f316e4b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=117582687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.117582687
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1609841760
Short name T1113
Test name
Test status
Simulation time 206595384 ps
CPU time 0.82 seconds
Started Jul 13 07:17:31 PM PDT 24
Finished Jul 13 07:17:56 PM PDT 24
Peak memory 206816 kb
Host smart-580c2b35-7c03-4e5a-8c42-0cf89ece6258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16098
41760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1609841760
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3388240129
Short name T1348
Test name
Test status
Simulation time 184571876 ps
CPU time 0.83 seconds
Started Jul 13 07:17:35 PM PDT 24
Finished Jul 13 07:18:04 PM PDT 24
Peak memory 206812 kb
Host smart-5a2c4695-8b14-4306-9e7c-b5ca421f2b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33882
40129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3388240129
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1055371366
Short name T1163
Test name
Test status
Simulation time 395252289 ps
CPU time 1.2 seconds
Started Jul 13 07:17:20 PM PDT 24
Finished Jul 13 07:17:38 PM PDT 24
Peak memory 206868 kb
Host smart-567dc57d-9322-4a01-946b-e182cee3b21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10553
71366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1055371366
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2686211565
Short name T2263
Test name
Test status
Simulation time 5458642107 ps
CPU time 38.13 seconds
Started Jul 13 07:17:27 PM PDT 24
Finished Jul 13 07:18:27 PM PDT 24
Peak memory 207072 kb
Host smart-69b0f5a7-6612-49ee-8cb5-024ec1ea61de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26862
11565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2686211565
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3476525205
Short name T795
Test name
Test status
Simulation time 41812460 ps
CPU time 0.67 seconds
Started Jul 13 07:09:40 PM PDT 24
Finished Jul 13 07:09:43 PM PDT 24
Peak memory 206900 kb
Host smart-d34cd392-698b-413d-b1ee-7423365858a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3476525205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3476525205
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2702272822
Short name T911
Test name
Test status
Simulation time 3605995946 ps
CPU time 4.25 seconds
Started Jul 13 07:09:21 PM PDT 24
Finished Jul 13 07:09:29 PM PDT 24
Peak memory 206952 kb
Host smart-9b000685-c5f2-48aa-91f6-96d7fda4d415
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2702272822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2702272822
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2140640425
Short name T2651
Test name
Test status
Simulation time 13309117048 ps
CPU time 11.68 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:36 PM PDT 24
Peak memory 207120 kb
Host smart-ab8afc0d-e321-4aac-ac82-88814ee1c6f6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2140640425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2140640425
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2706642061
Short name T2711
Test name
Test status
Simulation time 23354359528 ps
CPU time 27.01 seconds
Started Jul 13 07:09:21 PM PDT 24
Finished Jul 13 07:09:52 PM PDT 24
Peak memory 206928 kb
Host smart-11f2905c-612d-457d-97ae-bd2570df47fe
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2706642061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.2706642061
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1808766697
Short name T558
Test name
Test status
Simulation time 195774798 ps
CPU time 0.89 seconds
Started Jul 13 07:09:21 PM PDT 24
Finished Jul 13 07:09:26 PM PDT 24
Peak memory 206864 kb
Host smart-51b63992-c93a-4dc2-b76d-e3f50f99fe6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18087
66697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1808766697
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2816357246
Short name T2693
Test name
Test status
Simulation time 152228536 ps
CPU time 0.8 seconds
Started Jul 13 07:09:19 PM PDT 24
Finished Jul 13 07:09:21 PM PDT 24
Peak memory 206856 kb
Host smart-42455507-17fc-46a2-93b9-bc176ce85141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28163
57246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2816357246
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.904104817
Short name T433
Test name
Test status
Simulation time 504385706 ps
CPU time 1.53 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:23 PM PDT 24
Peak memory 207060 kb
Host smart-fad1a144-adea-46b7-86af-4d67fb4f0b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90410
4817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.904104817
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1248767913
Short name T678
Test name
Test status
Simulation time 1020452703 ps
CPU time 2.4 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:24 PM PDT 24
Peak memory 207080 kb
Host smart-808151f8-1854-4adb-a135-9bb942b9fc76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12487
67913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1248767913
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1859474256
Short name T1209
Test name
Test status
Simulation time 6500971438 ps
CPU time 12.75 seconds
Started Jul 13 07:09:22 PM PDT 24
Finished Jul 13 07:09:38 PM PDT 24
Peak memory 207144 kb
Host smart-b1c30e3d-36e0-4d84-bc8b-9c9fe7fcb233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18594
74256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1859474256
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.711449876
Short name T819
Test name
Test status
Simulation time 383323625 ps
CPU time 1.36 seconds
Started Jul 13 07:09:21 PM PDT 24
Finished Jul 13 07:09:26 PM PDT 24
Peak memory 206860 kb
Host smart-ebfef077-cee7-4071-ad7a-1e9f6c971014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71144
9876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.711449876
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1706910663
Short name T415
Test name
Test status
Simulation time 148268465 ps
CPU time 0.8 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:24 PM PDT 24
Peak memory 207108 kb
Host smart-6057ef24-6924-48f3-8eef-cb93d10b8b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17069
10663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1706910663
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1855226494
Short name T1304
Test name
Test status
Simulation time 51993363 ps
CPU time 0.64 seconds
Started Jul 13 07:09:21 PM PDT 24
Finished Jul 13 07:09:26 PM PDT 24
Peak memory 206880 kb
Host smart-4de32974-81be-4aa4-999a-a5fe7c854564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18552
26494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1855226494
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1890644877
Short name T1192
Test name
Test status
Simulation time 789928382 ps
CPU time 1.94 seconds
Started Jul 13 07:09:21 PM PDT 24
Finished Jul 13 07:09:27 PM PDT 24
Peak memory 207020 kb
Host smart-aa672f8c-2ac2-477c-a890-bdfa13539875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18906
44877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1890644877
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3856544519
Short name T1025
Test name
Test status
Simulation time 194277792 ps
CPU time 1.61 seconds
Started Jul 13 07:09:18 PM PDT 24
Finished Jul 13 07:09:20 PM PDT 24
Peak memory 207060 kb
Host smart-711c8888-c8aa-434c-96bf-8c085e705ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38565
44519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3856544519
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1367737287
Short name T2184
Test name
Test status
Simulation time 225172242 ps
CPU time 0.9 seconds
Started Jul 13 07:09:19 PM PDT 24
Finished Jul 13 07:09:20 PM PDT 24
Peak memory 206880 kb
Host smart-78ed16b9-a507-4349-bd6e-477ac5dbbf26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13677
37287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1367737287
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.176251076
Short name T456
Test name
Test status
Simulation time 141849327 ps
CPU time 0.77 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:09:23 PM PDT 24
Peak memory 206868 kb
Host smart-a95cec75-58c3-4a57-81a1-466bd285211d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17625
1076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.176251076
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.781471220
Short name T858
Test name
Test status
Simulation time 247990506 ps
CPU time 0.91 seconds
Started Jul 13 07:09:21 PM PDT 24
Finished Jul 13 07:09:26 PM PDT 24
Peak memory 206896 kb
Host smart-0407b314-8e64-4f04-adf3-14c64585b26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78147
1220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.781471220
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.3290116326
Short name T970
Test name
Test status
Simulation time 7498510886 ps
CPU time 66.1 seconds
Started Jul 13 07:09:20 PM PDT 24
Finished Jul 13 07:10:30 PM PDT 24
Peak memory 207036 kb
Host smart-11883f6e-9cc0-433e-bb2d-2b6df2db562f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3290116326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3290116326
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1063999433
Short name T935
Test name
Test status
Simulation time 8517698575 ps
CPU time 65.32 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 207084 kb
Host smart-23ced5e2-bba3-4519-9b8b-83cb382e0860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
99433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1063999433
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3476392303
Short name T2327
Test name
Test status
Simulation time 183441084 ps
CPU time 0.82 seconds
Started Jul 13 07:09:29 PM PDT 24
Finished Jul 13 07:09:33 PM PDT 24
Peak memory 206864 kb
Host smart-f93c60eb-c7ff-4679-afdf-9ad629d98ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34763
92303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3476392303
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1434092679
Short name T775
Test name
Test status
Simulation time 23348284585 ps
CPU time 26.74 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:57 PM PDT 24
Peak memory 206944 kb
Host smart-8673ec0d-aa6f-4408-8527-9447c3fac32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
92679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1434092679
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2648745506
Short name T1471
Test name
Test status
Simulation time 3384936498 ps
CPU time 4.1 seconds
Started Jul 13 07:09:27 PM PDT 24
Finished Jul 13 07:09:31 PM PDT 24
Peak memory 206924 kb
Host smart-548df4e0-390b-4113-a6a1-aacc97af5a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26487
45506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2648745506
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3000029649
Short name T143
Test name
Test status
Simulation time 9385852329 ps
CPU time 84.79 seconds
Started Jul 13 07:09:30 PM PDT 24
Finished Jul 13 07:10:58 PM PDT 24
Peak memory 207128 kb
Host smart-86181970-c3f4-4414-8496-2a8175164536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30000
29649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3000029649
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1873399896
Short name T1476
Test name
Test status
Simulation time 3770586048 ps
CPU time 106.65 seconds
Started Jul 13 07:09:30 PM PDT 24
Finished Jul 13 07:11:20 PM PDT 24
Peak memory 207096 kb
Host smart-cc990c63-ce77-4917-9655-f6f83cdb75d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1873399896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1873399896
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2618614862
Short name T679
Test name
Test status
Simulation time 250316796 ps
CPU time 0.93 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:32 PM PDT 24
Peak memory 206900 kb
Host smart-48accc34-35f2-47a8-83ac-4231418d670c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2618614862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2618614862
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2979643778
Short name T2135
Test name
Test status
Simulation time 196802376 ps
CPU time 0.84 seconds
Started Jul 13 07:09:30 PM PDT 24
Finished Jul 13 07:09:34 PM PDT 24
Peak memory 206880 kb
Host smart-cc8e5963-5bb7-43f5-968f-065ea35774ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796
43778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2979643778
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.354641109
Short name T2666
Test name
Test status
Simulation time 3419459028 ps
CPU time 90.6 seconds
Started Jul 13 07:09:29 PM PDT 24
Finished Jul 13 07:11:03 PM PDT 24
Peak memory 207056 kb
Host smart-993cc553-197c-4b8f-9212-1bf186bcfbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35464
1109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.354641109
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.807593566
Short name T1798
Test name
Test status
Simulation time 8178891640 ps
CPU time 229.13 seconds
Started Jul 13 07:09:30 PM PDT 24
Finished Jul 13 07:13:22 PM PDT 24
Peak memory 207180 kb
Host smart-25a7585c-f49c-4a02-95d9-4215fee13ab8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=807593566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.807593566
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1947526116
Short name T2395
Test name
Test status
Simulation time 147242189 ps
CPU time 0.78 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:32 PM PDT 24
Peak memory 206876 kb
Host smart-837dc72a-72d7-45d3-a8f6-283687648f91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1947526116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1947526116
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1239305801
Short name T1320
Test name
Test status
Simulation time 144779359 ps
CPU time 0.78 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:32 PM PDT 24
Peak memory 206536 kb
Host smart-313a7a6b-9b09-4603-82df-a11f5ec33d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12393
05801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1239305801
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3714230274
Short name T1644
Test name
Test status
Simulation time 213656962 ps
CPU time 0.84 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:32 PM PDT 24
Peak memory 206860 kb
Host smart-a8dd19af-b3dd-48a3-8b2d-f53402a379c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37142
30274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3714230274
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2633703271
Short name T1561
Test name
Test status
Simulation time 184959690 ps
CPU time 0.87 seconds
Started Jul 13 07:09:27 PM PDT 24
Finished Jul 13 07:09:30 PM PDT 24
Peak memory 206812 kb
Host smart-89c1590b-4ad1-43de-b1ba-44c4b40b7abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26337
03271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2633703271
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3691120804
Short name T1861
Test name
Test status
Simulation time 181979610 ps
CPU time 0.8 seconds
Started Jul 13 07:09:27 PM PDT 24
Finished Jul 13 07:09:29 PM PDT 24
Peak memory 206868 kb
Host smart-96e38720-200a-480b-ab11-db7aa8b220c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36911
20804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3691120804
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3383891162
Short name T1470
Test name
Test status
Simulation time 221294405 ps
CPU time 0.83 seconds
Started Jul 13 07:09:29 PM PDT 24
Finished Jul 13 07:09:33 PM PDT 24
Peak memory 206860 kb
Host smart-7b302bcc-ce3d-4ea2-acf3-d127e812f66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838
91162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3383891162
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.4124531955
Short name T1446
Test name
Test status
Simulation time 208692990 ps
CPU time 0.86 seconds
Started Jul 13 07:09:31 PM PDT 24
Finished Jul 13 07:09:34 PM PDT 24
Peak memory 206860 kb
Host smart-f364e1a3-1af5-4057-a9a3-7fdb06b64161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41245
31955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.4124531955
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2018837770
Short name T192
Test name
Test status
Simulation time 190684212 ps
CPU time 0.86 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:31 PM PDT 24
Peak memory 206880 kb
Host smart-b167b1e9-4e5a-440e-8cd4-9edddc803e46
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2018837770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2018837770
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3963838872
Short name T459
Test name
Test status
Simulation time 151384450 ps
CPU time 0.74 seconds
Started Jul 13 07:09:27 PM PDT 24
Finished Jul 13 07:09:30 PM PDT 24
Peak memory 206868 kb
Host smart-72b8a2f5-d3a4-421f-b567-69a7c3260d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39638
38872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3963838872
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3444296396
Short name T2247
Test name
Test status
Simulation time 77059200 ps
CPU time 0.69 seconds
Started Jul 13 07:09:29 PM PDT 24
Finished Jul 13 07:09:33 PM PDT 24
Peak memory 206876 kb
Host smart-89bb8f1a-4252-46ef-a540-54883a04353e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34442
96396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3444296396
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3610106662
Short name T247
Test name
Test status
Simulation time 20343017001 ps
CPU time 46.12 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:10:18 PM PDT 24
Peak memory 207124 kb
Host smart-41a8fc4a-6900-48b3-a139-f3c9b9a79950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36101
06662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3610106662
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3676348420
Short name T2447
Test name
Test status
Simulation time 188027963 ps
CPU time 0.85 seconds
Started Jul 13 07:09:29 PM PDT 24
Finished Jul 13 07:09:32 PM PDT 24
Peak memory 206864 kb
Host smart-740a5b75-0438-4fed-a732-3c9b4ba76640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36763
48420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3676348420
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1194422598
Short name T2291
Test name
Test status
Simulation time 164880420 ps
CPU time 0.81 seconds
Started Jul 13 07:09:27 PM PDT 24
Finished Jul 13 07:09:29 PM PDT 24
Peak memory 206888 kb
Host smart-fcdfa541-72a1-4211-ad00-75cbe389d117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11944
22598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1194422598
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.3223265763
Short name T150
Test name
Test status
Simulation time 9591311478 ps
CPU time 63.03 seconds
Started Jul 13 07:09:27 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 207084 kb
Host smart-99fee425-fbc9-4431-a674-7f22bda2b7bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3223265763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.3223265763
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.701576214
Short name T2014
Test name
Test status
Simulation time 3613750694 ps
CPU time 30.65 seconds
Started Jul 13 07:09:27 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 207160 kb
Host smart-76f3885b-f41a-4a4f-b592-9155cfb3e747
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=701576214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.701576214
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2923372620
Short name T1649
Test name
Test status
Simulation time 11709204333 ps
CPU time 80.27 seconds
Started Jul 13 07:09:30 PM PDT 24
Finished Jul 13 07:10:54 PM PDT 24
Peak memory 207144 kb
Host smart-2e7d1604-327c-4a1f-8c15-66c45f68cf5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2923372620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2923372620
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.852991481
Short name T1698
Test name
Test status
Simulation time 158106277 ps
CPU time 0.84 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:31 PM PDT 24
Peak memory 206908 kb
Host smart-45b44ce4-91fc-462b-8c3e-f2f8314949d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85299
1481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.852991481
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1150320325
Short name T1926
Test name
Test status
Simulation time 150543611 ps
CPU time 0.77 seconds
Started Jul 13 07:09:30 PM PDT 24
Finished Jul 13 07:09:34 PM PDT 24
Peak memory 206868 kb
Host smart-eab2a7de-1c5d-4044-8f71-33cd26d7bbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
20325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1150320325
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3145841897
Short name T2015
Test name
Test status
Simulation time 151600281 ps
CPU time 0.81 seconds
Started Jul 13 07:09:29 PM PDT 24
Finished Jul 13 07:09:33 PM PDT 24
Peak memory 206844 kb
Host smart-895ff89f-1105-4e32-9454-35c841952eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31458
41897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3145841897
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.435019612
Short name T2241
Test name
Test status
Simulation time 192076153 ps
CPU time 0.77 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:31 PM PDT 24
Peak memory 206884 kb
Host smart-7a3b58fe-43cc-44a9-8a37-347f70647a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43501
9612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.435019612
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1970880352
Short name T1219
Test name
Test status
Simulation time 152072379 ps
CPU time 0.79 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:09:31 PM PDT 24
Peak memory 206876 kb
Host smart-954e1ec6-a137-4e56-aa09-ec57af681c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19708
80352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1970880352
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3651295341
Short name T2314
Test name
Test status
Simulation time 256797740 ps
CPU time 1.03 seconds
Started Jul 13 07:09:29 PM PDT 24
Finished Jul 13 07:09:34 PM PDT 24
Peak memory 206864 kb
Host smart-981c48da-58e0-43a3-ace8-fced2018c9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36512
95341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3651295341
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2454041862
Short name T1002
Test name
Test status
Simulation time 3533220066 ps
CPU time 99.46 seconds
Started Jul 13 07:09:27 PM PDT 24
Finished Jul 13 07:11:08 PM PDT 24
Peak memory 207048 kb
Host smart-ddc28b57-c81f-49c9-8bf3-7ae412d264cd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2454041862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2454041862
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.920961703
Short name T29
Test name
Test status
Simulation time 151002155 ps
CPU time 0.8 seconds
Started Jul 13 07:09:29 PM PDT 24
Finished Jul 13 07:09:34 PM PDT 24
Peak memory 206876 kb
Host smart-dc02eb2a-ba16-4345-b8a2-07e981c0b8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92096
1703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.920961703
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2161759447
Short name T1603
Test name
Test status
Simulation time 239138508 ps
CPU time 0.85 seconds
Started Jul 13 07:09:30 PM PDT 24
Finished Jul 13 07:09:34 PM PDT 24
Peak memory 206860 kb
Host smart-f1eb1c25-dc9e-45ad-bfb6-06b9d212bc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21617
59447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2161759447
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2592812597
Short name T949
Test name
Test status
Simulation time 206201541 ps
CPU time 0.94 seconds
Started Jul 13 07:09:38 PM PDT 24
Finished Jul 13 07:09:41 PM PDT 24
Peak memory 206884 kb
Host smart-add254e6-153a-45b0-a24d-78687b0a52dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
12597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2592812597
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3875498952
Short name T1314
Test name
Test status
Simulation time 4934911116 ps
CPU time 136.83 seconds
Started Jul 13 07:09:28 PM PDT 24
Finished Jul 13 07:11:48 PM PDT 24
Peak memory 206744 kb
Host smart-19a341f5-b4c6-41b2-9201-25c73632728c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38754
98952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3875498952
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.4110502088
Short name T2547
Test name
Test status
Simulation time 50889056 ps
CPU time 0.69 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:29 PM PDT 24
Peak memory 206900 kb
Host smart-04b0f0b4-648f-40aa-bdc1-e550b91bc37a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4110502088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.4110502088
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.542278251
Short name T1569
Test name
Test status
Simulation time 4302322600 ps
CPU time 5.02 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:10:01 PM PDT 24
Peak memory 206956 kb
Host smart-73c2c1be-3152-4de3-927b-8c6c4c28c153
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=542278251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.542278251
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3787364906
Short name T1036
Test name
Test status
Simulation time 13472683239 ps
CPU time 12.59 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:10:05 PM PDT 24
Peak memory 207152 kb
Host smart-e69503c4-66d7-4197-ab53-1c7febdfaff0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3787364906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3787364906
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1356514055
Short name T2100
Test name
Test status
Simulation time 23340342458 ps
CPU time 23.8 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:10:18 PM PDT 24
Peak memory 207096 kb
Host smart-72a11a18-de2d-42bc-b21e-b2f408cb4d6b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1356514055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.1356514055
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2808599979
Short name T981
Test name
Test status
Simulation time 196492082 ps
CPU time 0.85 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206896 kb
Host smart-06b5c94d-30ac-4c22-afa6-e14e2b330869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28085
99979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2808599979
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1188187234
Short name T2348
Test name
Test status
Simulation time 155366192 ps
CPU time 0.78 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:09:59 PM PDT 24
Peak memory 206860 kb
Host smart-5c3200f4-adc5-4528-93b6-37e2790e690e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11881
87234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1188187234
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1762708100
Short name T1110
Test name
Test status
Simulation time 358718715 ps
CPU time 1.34 seconds
Started Jul 13 07:09:46 PM PDT 24
Finished Jul 13 07:09:49 PM PDT 24
Peak memory 206860 kb
Host smart-ebbb94be-6950-4bbc-995a-c9b7afbd796b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17627
08100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1762708100
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.978623409
Short name T100
Test name
Test status
Simulation time 619541146 ps
CPU time 1.55 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206860 kb
Host smart-937315c4-e034-4fa3-a068-a72657fcbee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97862
3409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.978623409
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2048161496
Short name T1353
Test name
Test status
Simulation time 19760952016 ps
CPU time 40.85 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:10:38 PM PDT 24
Peak memory 207140 kb
Host smart-1ecb6b28-134a-4b15-95d6-255f75e5a6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20481
61496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2048161496
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.920799320
Short name T913
Test name
Test status
Simulation time 325274463 ps
CPU time 1.18 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:01 PM PDT 24
Peak memory 206884 kb
Host smart-909c33db-f548-4b7c-948d-d44c467637d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92079
9320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.920799320
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2789369380
Short name T2366
Test name
Test status
Simulation time 168625868 ps
CPU time 0.79 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206868 kb
Host smart-e54b3ec6-7090-4c39-a5a7-791c5421dcbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27893
69380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2789369380
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2029009520
Short name T1160
Test name
Test status
Simulation time 46744297 ps
CPU time 0.67 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206868 kb
Host smart-0184e7cb-01d4-4c94-932f-16dbd95a4877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20290
09520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2029009520
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2440153703
Short name T577
Test name
Test status
Simulation time 978938885 ps
CPU time 2.22 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:01 PM PDT 24
Peak memory 207076 kb
Host smart-a20d5033-70a2-41a2-960f-d5416469d846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24401
53703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2440153703
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2447361983
Short name T668
Test name
Test status
Simulation time 227602941 ps
CPU time 1.67 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:09:54 PM PDT 24
Peak memory 207012 kb
Host smart-09169a3f-7a3f-4002-a4c3-8886cb09c1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24473
61983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2447361983
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3959765107
Short name T1919
Test name
Test status
Simulation time 146844178 ps
CPU time 0.85 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:09:54 PM PDT 24
Peak memory 206868 kb
Host smart-47e94e92-e68d-494c-9c16-41510aec790f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39597
65107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3959765107
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.259001236
Short name T1460
Test name
Test status
Simulation time 133687005 ps
CPU time 0.76 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:09:59 PM PDT 24
Peak memory 207040 kb
Host smart-9d465106-a981-4c71-abaf-76377b33a35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25900
1236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.259001236
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3615855306
Short name T2171
Test name
Test status
Simulation time 265573289 ps
CPU time 0.99 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:09:59 PM PDT 24
Peak memory 206864 kb
Host smart-2d44d27a-83e1-4f13-a932-9de24eba406c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36158
55306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3615855306
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.1774573496
Short name T2374
Test name
Test status
Simulation time 7830207066 ps
CPU time 221.08 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:13:36 PM PDT 24
Peak memory 207056 kb
Host smart-9a616402-46ca-4d1d-8535-1088aa67edd8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1774573496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.1774573496
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.410576821
Short name T354
Test name
Test status
Simulation time 227004819 ps
CPU time 0.88 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206876 kb
Host smart-57219416-2f4a-407c-9704-00916b919397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41057
6821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.410576821
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.3457693451
Short name T1892
Test name
Test status
Simulation time 23328637862 ps
CPU time 22.06 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:22 PM PDT 24
Peak memory 206904 kb
Host smart-73cb8b2d-1660-4930-ad0f-6902a363a732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34576
93451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.3457693451
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3761622233
Short name T449
Test name
Test status
Simulation time 3392563185 ps
CPU time 4.21 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:10:02 PM PDT 24
Peak memory 206964 kb
Host smart-be2543da-c449-4d76-a2fe-c79ff8d0e8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37616
22233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3761622233
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2671972155
Short name T2558
Test name
Test status
Simulation time 5807899239 ps
CPU time 54.23 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:10:49 PM PDT 24
Peak memory 207132 kb
Host smart-77e7f181-51f5-410f-969a-4ac981986c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26719
72155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2671972155
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3505952549
Short name T2597
Test name
Test status
Simulation time 4418015682 ps
CPU time 41.56 seconds
Started Jul 13 07:09:55 PM PDT 24
Finished Jul 13 07:10:42 PM PDT 24
Peak memory 207072 kb
Host smart-eaa5bcb6-7b1e-455e-b6f5-60ba118aa5a3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3505952549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3505952549
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2967964163
Short name T1969
Test name
Test status
Simulation time 240913897 ps
CPU time 0.93 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:09:56 PM PDT 24
Peak memory 206868 kb
Host smart-06cebe76-d016-4f8c-8096-cc522e71259e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2967964163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2967964163
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3627073281
Short name T1475
Test name
Test status
Simulation time 199761915 ps
CPU time 0.85 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:09:55 PM PDT 24
Peak memory 206880 kb
Host smart-62fa9fb9-19a8-4528-8c6c-4620033b6bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36270
73281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3627073281
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2762278842
Short name T1300
Test name
Test status
Simulation time 5260254289 ps
CPU time 39.63 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:39 PM PDT 24
Peak memory 207108 kb
Host smart-7e3c4889-0b20-4b26-936c-8e89ed3919c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27622
78842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2762278842
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.602717748
Short name T1721
Test name
Test status
Simulation time 3416596485 ps
CPU time 97.78 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:11:35 PM PDT 24
Peak memory 207120 kb
Host smart-5dc7441c-4f8c-428a-a97c-572ca45d75f9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=602717748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.602717748
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.4292771176
Short name T2658
Test name
Test status
Simulation time 157734716 ps
CPU time 0.8 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206868 kb
Host smart-84f6c54e-6357-459c-99e8-32253a78aa74
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4292771176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.4292771176
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1926910476
Short name T469
Test name
Test status
Simulation time 145439504 ps
CPU time 0.77 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206876 kb
Host smart-b4e0d02c-fd03-48f2-a149-48cbafd885cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19269
10476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1926910476
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2823453355
Short name T2422
Test name
Test status
Simulation time 218267082 ps
CPU time 0.92 seconds
Started Jul 13 07:09:52 PM PDT 24
Finished Jul 13 07:09:53 PM PDT 24
Peak memory 206896 kb
Host smart-35fb5889-9d9b-44d1-a51a-409f6157a5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28234
53355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2823453355
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1908071926
Short name T1762
Test name
Test status
Simulation time 239928035 ps
CPU time 0.88 seconds
Started Jul 13 07:09:55 PM PDT 24
Finished Jul 13 07:10:01 PM PDT 24
Peak memory 206844 kb
Host smart-ed493d4e-0347-4120-9528-5988e49a8fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19080
71926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1908071926
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1374498200
Short name T606
Test name
Test status
Simulation time 168651221 ps
CPU time 0.88 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:09:59 PM PDT 24
Peak memory 206892 kb
Host smart-f7ef5827-dde4-43fa-824a-5b384663b6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13744
98200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1374498200
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1421999958
Short name T2353
Test name
Test status
Simulation time 164886263 ps
CPU time 0.84 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206884 kb
Host smart-fa5fb0d2-89c5-45ee-9655-5acb24926c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
99958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1421999958
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.854657295
Short name T649
Test name
Test status
Simulation time 149372435 ps
CPU time 0.83 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 207112 kb
Host smart-35c0d12c-3df2-4619-9ddf-3757a69029bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85465
7295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.854657295
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1640530491
Short name T1468
Test name
Test status
Simulation time 246798748 ps
CPU time 0.99 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:09:58 PM PDT 24
Peak memory 206872 kb
Host smart-5e070e42-9516-4a97-a109-971b69fd42f4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1640530491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1640530491
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.4105733771
Short name T508
Test name
Test status
Simulation time 136956345 ps
CPU time 0.76 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:09:57 PM PDT 24
Peak memory 206824 kb
Host smart-faec817a-b764-4843-ab12-5e3934b94629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41057
33771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.4105733771
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3590208740
Short name T2310
Test name
Test status
Simulation time 39920899 ps
CPU time 0.69 seconds
Started Jul 13 07:09:54 PM PDT 24
Finished Jul 13 07:10:00 PM PDT 24
Peak memory 206868 kb
Host smart-1fc7eb6d-72d8-4ed1-9ad6-0d04e96afb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35902
08740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3590208740
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1214061425
Short name T82
Test name
Test status
Simulation time 21987280284 ps
CPU time 47.82 seconds
Started Jul 13 07:09:53 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 207108 kb
Host smart-d594b5f3-6903-4a5d-8de5-db4a08ee28d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12140
61425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1214061425
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2503939617
Short name T2459
Test name
Test status
Simulation time 180112091 ps
CPU time 0.89 seconds
Started Jul 13 07:09:51 PM PDT 24
Finished Jul 13 07:09:53 PM PDT 24
Peak memory 206864 kb
Host smart-2a8311a2-a4de-400d-8d45-973e445867a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25039
39617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2503939617
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1840785002
Short name T1198
Test name
Test status
Simulation time 229343826 ps
CPU time 0.91 seconds
Started Jul 13 07:10:06 PM PDT 24
Finished Jul 13 07:10:30 PM PDT 24
Peak memory 206860 kb
Host smart-59d640af-6bad-490e-a94d-cc7e0ee65349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18407
85002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1840785002
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.998449139
Short name T147
Test name
Test status
Simulation time 4287319872 ps
CPU time 108.71 seconds
Started Jul 13 07:10:02 PM PDT 24
Finished Jul 13 07:12:09 PM PDT 24
Peak memory 206996 kb
Host smart-cca61202-8e01-4b98-bf13-8763860d9f14
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=998449139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.998449139
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.401684472
Short name T146
Test name
Test status
Simulation time 8614264961 ps
CPU time 43.87 seconds
Started Jul 13 07:10:01 PM PDT 24
Finished Jul 13 07:10:56 PM PDT 24
Peak memory 207096 kb
Host smart-dc9765e1-c9be-47e0-8c8e-490907af4c42
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=401684472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.401684472
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2771221547
Short name T1385
Test name
Test status
Simulation time 11041849796 ps
CPU time 55.46 seconds
Started Jul 13 07:10:01 PM PDT 24
Finished Jul 13 07:11:10 PM PDT 24
Peak memory 207104 kb
Host smart-31939474-598e-4db1-b89d-d718e5ed0dd1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2771221547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2771221547
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.666264598
Short name T1610
Test name
Test status
Simulation time 178948859 ps
CPU time 0.8 seconds
Started Jul 13 07:10:01 PM PDT 24
Finished Jul 13 07:10:15 PM PDT 24
Peak memory 206884 kb
Host smart-7b95b050-5cbe-4a3f-be99-87066a9549ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66626
4598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.666264598
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1783560556
Short name T2576
Test name
Test status
Simulation time 157726855 ps
CPU time 0.78 seconds
Started Jul 13 07:10:06 PM PDT 24
Finished Jul 13 07:10:30 PM PDT 24
Peak memory 206860 kb
Host smart-aa3ac01a-6ae8-4b36-8c7d-14e4d915fa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17835
60556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1783560556
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.850251568
Short name T1048
Test name
Test status
Simulation time 206134778 ps
CPU time 0.88 seconds
Started Jul 13 07:10:02 PM PDT 24
Finished Jul 13 07:10:18 PM PDT 24
Peak memory 206868 kb
Host smart-437c6b33-21e8-406f-9aaf-f0afd46d568a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85025
1568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.850251568
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2713798574
Short name T1781
Test name
Test status
Simulation time 173297550 ps
CPU time 0.79 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:27 PM PDT 24
Peak memory 206852 kb
Host smart-d10f9398-f9ce-4bc9-864e-2a339d744cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27137
98574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2713798574
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.400946691
Short name T1188
Test name
Test status
Simulation time 151029696 ps
CPU time 0.76 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:28 PM PDT 24
Peak memory 206864 kb
Host smart-600f7032-662e-4f31-95b0-c9414f324515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40094
6691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.400946691
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1122124432
Short name T534
Test name
Test status
Simulation time 204390779 ps
CPU time 0.9 seconds
Started Jul 13 07:10:03 PM PDT 24
Finished Jul 13 07:10:23 PM PDT 24
Peak memory 206872 kb
Host smart-e7f4dfb9-1368-46d5-9e75-1890b66addd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11221
24432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1122124432
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2597723769
Short name T886
Test name
Test status
Simulation time 4403514174 ps
CPU time 130.43 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:12:40 PM PDT 24
Peak memory 207096 kb
Host smart-54eba79d-f323-415b-8c03-32828a47f3c1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2597723769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2597723769
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2122216984
Short name T615
Test name
Test status
Simulation time 156343766 ps
CPU time 0.78 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:10:31 PM PDT 24
Peak memory 206880 kb
Host smart-0d12eb9e-4980-46a8-9198-fe9286981cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21222
16984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2122216984
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3309663477
Short name T345
Test name
Test status
Simulation time 194559499 ps
CPU time 0.85 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:28 PM PDT 24
Peak memory 206896 kb
Host smart-738f5333-37e5-4faa-8d21-1fc47abac36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33096
63477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3309663477
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1835743286
Short name T1712
Test name
Test status
Simulation time 456810163 ps
CPU time 1.33 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:27 PM PDT 24
Peak memory 206868 kb
Host smart-7412bf10-9bd3-4014-a445-6bc64741e788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18357
43286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1835743286
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.4096560356
Short name T675
Test name
Test status
Simulation time 4981048656 ps
CPU time 34.4 seconds
Started Jul 13 07:10:02 PM PDT 24
Finished Jul 13 07:10:52 PM PDT 24
Peak memory 207072 kb
Host smart-8e8e32a6-2255-42b9-bf3e-01937daddceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40965
60356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.4096560356
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1584965151
Short name T985
Test name
Test status
Simulation time 42215922 ps
CPU time 0.69 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206912 kb
Host smart-55cb7e4d-95c4-4a01-bf80-7b5d7e56d5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1584965151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1584965151
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2496993841
Short name T1066
Test name
Test status
Simulation time 4266754536 ps
CPU time 4.65 seconds
Started Jul 13 07:10:06 PM PDT 24
Finished Jul 13 07:10:33 PM PDT 24
Peak memory 207048 kb
Host smart-83f97d4a-bb4b-438d-8231-020fccf487d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2496993841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2496993841
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3703195041
Short name T2181
Test name
Test status
Simulation time 13341467667 ps
CPU time 16.38 seconds
Started Jul 13 07:10:03 PM PDT 24
Finished Jul 13 07:10:40 PM PDT 24
Peak memory 206916 kb
Host smart-cb973850-8843-46eb-989c-d88086a7016d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3703195041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3703195041
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.4162259902
Short name T976
Test name
Test status
Simulation time 23317299706 ps
CPU time 24.45 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:10:54 PM PDT 24
Peak memory 206908 kb
Host smart-957e634b-aea8-41cb-97ca-ce0ae289208f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4162259902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.4162259902
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3419473398
Short name T2385
Test name
Test status
Simulation time 148435124 ps
CPU time 0.82 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:27 PM PDT 24
Peak memory 206864 kb
Host smart-054bd163-9515-4556-9e82-46ce9d9f684d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34194
73398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3419473398
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.76292676
Short name T2186
Test name
Test status
Simulation time 237501976 ps
CPU time 0.86 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:24 PM PDT 24
Peak memory 206864 kb
Host smart-fab780e5-7e37-4880-9916-c43b415a7b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76292
676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.76292676
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1842877509
Short name T1058
Test name
Test status
Simulation time 344533737 ps
CPU time 1.2 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:27 PM PDT 24
Peak memory 206856 kb
Host smart-a6519595-035e-4d53-b697-2798ed5122c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18428
77509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1842877509
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3230302384
Short name T1101
Test name
Test status
Simulation time 1426496913 ps
CPU time 2.98 seconds
Started Jul 13 07:10:01 PM PDT 24
Finished Jul 13 07:10:17 PM PDT 24
Peak memory 207056 kb
Host smart-576fe804-ef62-4f94-aaf1-98ac35e0a39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32303
02384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3230302384
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.860570059
Short name T1017
Test name
Test status
Simulation time 13885722145 ps
CPU time 24.8 seconds
Started Jul 13 07:10:06 PM PDT 24
Finished Jul 13 07:10:54 PM PDT 24
Peak memory 207136 kb
Host smart-c9cde3c6-6604-4602-a2e1-687a0618e54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86057
0059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.860570059
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3038231941
Short name T495
Test name
Test status
Simulation time 499680141 ps
CPU time 1.37 seconds
Started Jul 13 07:10:03 PM PDT 24
Finished Jul 13 07:10:23 PM PDT 24
Peak memory 206856 kb
Host smart-8f7c6d49-e5c4-44f4-9dbc-acf17f0f3426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30382
31941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3038231941
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.287228599
Short name T1020
Test name
Test status
Simulation time 144795529 ps
CPU time 0.78 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:27 PM PDT 24
Peak memory 207104 kb
Host smart-a7fc08f4-89a5-492d-a0bf-436954d68fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28722
8599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.287228599
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3138899323
Short name T1054
Test name
Test status
Simulation time 40549117 ps
CPU time 0.63 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:28 PM PDT 24
Peak memory 206868 kb
Host smart-6f893622-32c0-4e93-8550-4bd32f251056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31388
99323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3138899323
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3263952534
Short name T2704
Test name
Test status
Simulation time 947838978 ps
CPU time 2.31 seconds
Started Jul 13 07:10:02 PM PDT 24
Finished Jul 13 07:10:24 PM PDT 24
Peak memory 207072 kb
Host smart-e80eb2a6-e755-42bf-8b21-e12ab5b9d9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32639
52534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3263952534
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2483951129
Short name T1043
Test name
Test status
Simulation time 187467218 ps
CPU time 1.17 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:29 PM PDT 24
Peak memory 207060 kb
Host smart-4d7ceaf6-2796-4398-acd5-7f78d86f09a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24839
51129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2483951129
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.961105360
Short name T691
Test name
Test status
Simulation time 201685579 ps
CPU time 0.88 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:10:31 PM PDT 24
Peak memory 206876 kb
Host smart-d5967f75-7dd0-4408-a27a-8f5d4124bf70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96110
5360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.961105360
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.800223077
Short name T2661
Test name
Test status
Simulation time 133684444 ps
CPU time 0.76 seconds
Started Jul 13 07:10:03 PM PDT 24
Finished Jul 13 07:10:23 PM PDT 24
Peak memory 206860 kb
Host smart-01d7ea73-11da-4cd5-aa85-0f221d98f068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80022
3077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.800223077
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.524496613
Short name T1690
Test name
Test status
Simulation time 200757948 ps
CPU time 0.84 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:28 PM PDT 24
Peak memory 206768 kb
Host smart-38476f65-b94b-403e-bc32-7286213609c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52449
6613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.524496613
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.2878583856
Short name T1487
Test name
Test status
Simulation time 8537166060 ps
CPU time 64.85 seconds
Started Jul 13 07:10:03 PM PDT 24
Finished Jul 13 07:11:28 PM PDT 24
Peak memory 207144 kb
Host smart-02cfd5c1-c225-4fdd-b9d0-6eab60d9274c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2878583856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.2878583856
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.164120604
Short name T587
Test name
Test status
Simulation time 4090517546 ps
CPU time 16.1 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:10:46 PM PDT 24
Peak memory 206788 kb
Host smart-ea5b1270-8a87-486b-be8e-0b0221e30c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16412
0604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.164120604
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3910977161
Short name T1140
Test name
Test status
Simulation time 190653447 ps
CPU time 0.9 seconds
Started Jul 13 07:10:02 PM PDT 24
Finished Jul 13 07:10:18 PM PDT 24
Peak memory 206876 kb
Host smart-78bb6754-f15d-49ba-b239-2ce09ec13565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39109
77161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3910977161
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2543423811
Short name T919
Test name
Test status
Simulation time 23353032066 ps
CPU time 24.41 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:52 PM PDT 24
Peak memory 206928 kb
Host smart-551f0af5-b075-4534-a018-8338e9191fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25434
23811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2543423811
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3262942959
Short name T346
Test name
Test status
Simulation time 3315512470 ps
CPU time 4.18 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:10:34 PM PDT 24
Peak memory 206600 kb
Host smart-e5d64f6c-a9f1-40a7-bde2-5b868ea6a3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32629
42959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3262942959
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3976555388
Short name T1600
Test name
Test status
Simulation time 9144479372 ps
CPU time 65.88 seconds
Started Jul 13 07:10:06 PM PDT 24
Finished Jul 13 07:11:35 PM PDT 24
Peak memory 207128 kb
Host smart-4f83b6f4-22aa-450d-b125-e680318d9c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
55388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3976555388
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3798792519
Short name T827
Test name
Test status
Simulation time 4388931136 ps
CPU time 31.32 seconds
Started Jul 13 07:10:06 PM PDT 24
Finished Jul 13 07:10:59 PM PDT 24
Peak memory 207088 kb
Host smart-cb9630a6-6810-4706-9c87-018de45223bd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3798792519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3798792519
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.980628100
Short name T1388
Test name
Test status
Simulation time 248947905 ps
CPU time 0.93 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:28 PM PDT 24
Peak memory 206868 kb
Host smart-ea472a5f-6fd5-4184-95c1-a38135317aa4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=980628100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.980628100
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3086512478
Short name T934
Test name
Test status
Simulation time 204973217 ps
CPU time 0.92 seconds
Started Jul 13 07:10:08 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206884 kb
Host smart-89a8fcc2-fe75-44de-8e0d-4a95996b45f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865
12478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3086512478
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.250002294
Short name T1268
Test name
Test status
Simulation time 4695760863 ps
CPU time 135.44 seconds
Started Jul 13 07:10:03 PM PDT 24
Finished Jul 13 07:12:38 PM PDT 24
Peak memory 207060 kb
Host smart-44e9b001-5355-4bd2-ba0e-b9c54ac60c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25000
2294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.250002294
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2434940741
Short name T1011
Test name
Test status
Simulation time 3259876709 ps
CPU time 30.69 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:58 PM PDT 24
Peak memory 207044 kb
Host smart-f0ba9b65-4ad8-43f6-8f94-71c965fa30d9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2434940741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2434940741
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.189717179
Short name T2216
Test name
Test status
Simulation time 165823127 ps
CPU time 0.86 seconds
Started Jul 13 07:10:03 PM PDT 24
Finished Jul 13 07:10:24 PM PDT 24
Peak memory 206880 kb
Host smart-6eb9d0ef-9e5a-478e-93f1-79f2195799f2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=189717179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.189717179
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1810751015
Short name T1655
Test name
Test status
Simulation time 156179157 ps
CPU time 0.84 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:10:30 PM PDT 24
Peak memory 206876 kb
Host smart-59fb1f73-189b-499f-9fc8-3189d25b82ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
51015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1810751015
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3424433595
Short name T123
Test name
Test status
Simulation time 218814845 ps
CPU time 0.95 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:27 PM PDT 24
Peak memory 207104 kb
Host smart-e11b0560-1ba5-4f8e-85b4-d780dc59ca83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34244
33595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3424433595
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3862448043
Short name T867
Test name
Test status
Simulation time 164729493 ps
CPU time 0.8 seconds
Started Jul 13 07:10:04 PM PDT 24
Finished Jul 13 07:10:27 PM PDT 24
Peak memory 206852 kb
Host smart-5632cf63-3716-43f3-ae66-f4c468f54c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38624
48043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3862448043
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3828694697
Short name T2173
Test name
Test status
Simulation time 158477563 ps
CPU time 0.77 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:28 PM PDT 24
Peak memory 206864 kb
Host smart-31433b3b-3ca0-40aa-94fa-f7561e81bacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38286
94697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3828694697
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2801201777
Short name T2200
Test name
Test status
Simulation time 151007296 ps
CPU time 0.78 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:28 PM PDT 24
Peak memory 206860 kb
Host smart-fbd644a2-1b60-4810-95c5-c97a971c6b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28012
01777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2801201777
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1258223320
Short name T1069
Test name
Test status
Simulation time 155931862 ps
CPU time 0.81 seconds
Started Jul 13 07:10:08 PM PDT 24
Finished Jul 13 07:10:31 PM PDT 24
Peak memory 206868 kb
Host smart-9de6e3c1-0ead-4fdf-ba20-8711629c44b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
23320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1258223320
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.639531321
Short name T1949
Test name
Test status
Simulation time 194065115 ps
CPU time 0.84 seconds
Started Jul 13 07:10:03 PM PDT 24
Finished Jul 13 07:10:24 PM PDT 24
Peak memory 206888 kb
Host smart-bb5f2749-50d9-4a76-ab3d-d611e9c306a6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=639531321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.639531321
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1929787171
Short name T2388
Test name
Test status
Simulation time 141424853 ps
CPU time 0.77 seconds
Started Jul 13 07:10:08 PM PDT 24
Finished Jul 13 07:10:31 PM PDT 24
Peak memory 206812 kb
Host smart-28394317-a7dd-4234-aa81-8769aaea3f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19297
87171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1929787171
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3208235576
Short name T2379
Test name
Test status
Simulation time 40140811 ps
CPU time 0.67 seconds
Started Jul 13 07:10:09 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206876 kb
Host smart-477f7308-f5e8-427a-8f3a-3c6f145b72b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32082
35576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3208235576
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3260461632
Short name T2638
Test name
Test status
Simulation time 14033960402 ps
CPU time 32.6 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:11:03 PM PDT 24
Peak memory 207056 kb
Host smart-83e812c4-fb00-49b5-b31e-432a05e8d01a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32604
61632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3260461632
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2077263837
Short name T588
Test name
Test status
Simulation time 185328131 ps
CPU time 0.86 seconds
Started Jul 13 07:10:09 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206860 kb
Host smart-067dd78a-4dbd-4167-9968-92b31c71d4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
63837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2077263837
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3961797366
Short name T2343
Test name
Test status
Simulation time 212673927 ps
CPU time 0.97 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:10:30 PM PDT 24
Peak memory 206876 kb
Host smart-f30161e3-66f5-4976-bd0b-1cc3289370c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39617
97366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3961797366
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.159646757
Short name T2006
Test name
Test status
Simulation time 10427460394 ps
CPU time 63.23 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:11:31 PM PDT 24
Peak memory 207168 kb
Host smart-78289707-0f31-410f-96c2-760057780e9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=159646757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.159646757
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.399931920
Short name T162
Test name
Test status
Simulation time 4924032113 ps
CPU time 127.13 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:12:38 PM PDT 24
Peak memory 207104 kb
Host smart-4814c422-a4e3-40de-9106-34b3a000b8a5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=399931920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.399931920
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1895158240
Short name T2709
Test name
Test status
Simulation time 16047574585 ps
CPU time 336.43 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:16:08 PM PDT 24
Peak memory 207148 kb
Host smart-5e6ef079-6412-4dc8-b077-4424e31e9d1d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1895158240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1895158240
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1077009911
Short name T2438
Test name
Test status
Simulation time 161352170 ps
CPU time 0.8 seconds
Started Jul 13 07:10:05 PM PDT 24
Finished Jul 13 07:10:29 PM PDT 24
Peak memory 206868 kb
Host smart-4192a458-e809-4477-85b2-f7a9fc4597d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10770
09911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1077009911
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3822131576
Short name T1013
Test name
Test status
Simulation time 186324492 ps
CPU time 0.79 seconds
Started Jul 13 07:10:07 PM PDT 24
Finished Jul 13 07:10:31 PM PDT 24
Peak memory 206776 kb
Host smart-c06fa7a9-ae03-4980-b3f6-4e5b68930f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38221
31576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3822131576
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3859687889
Short name T1224
Test name
Test status
Simulation time 169505001 ps
CPU time 0.81 seconds
Started Jul 13 07:10:16 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206864 kb
Host smart-eb2f6989-dd4d-47cd-b198-129de2bdbe94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38596
87889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3859687889
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1633784029
Short name T2475
Test name
Test status
Simulation time 152499873 ps
CPU time 0.77 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:10:33 PM PDT 24
Peak memory 206868 kb
Host smart-b3aef531-0710-4b81-8434-d7c898454e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16337
84029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1633784029
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2104702259
Short name T1439
Test name
Test status
Simulation time 152192984 ps
CPU time 0.79 seconds
Started Jul 13 07:10:09 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206808 kb
Host smart-0896daaf-ceea-44e0-8d3f-2165fcffb4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21047
02259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2104702259
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.947535361
Short name T1854
Test name
Test status
Simulation time 257173885 ps
CPU time 1.02 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206852 kb
Host smart-567f8376-ed01-4914-9b55-4ec0b6edcc35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94753
5361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.947535361
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2264938788
Short name T2377
Test name
Test status
Simulation time 4659103435 ps
CPU time 134.38 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:12:46 PM PDT 24
Peak memory 207100 kb
Host smart-cb035bfc-4e50-44b6-8055-779ccbf34e0a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2264938788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2264938788
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2200396029
Short name T787
Test name
Test status
Simulation time 177321335 ps
CPU time 0.87 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:10:33 PM PDT 24
Peak memory 206912 kb
Host smart-e00beb09-dce5-4897-a6dd-238cbd7f4eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
96029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2200396029
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.4074621656
Short name T2213
Test name
Test status
Simulation time 156734930 ps
CPU time 0.81 seconds
Started Jul 13 07:10:09 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206864 kb
Host smart-81c83836-1276-4fc9-a1bc-92b801ad423d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40746
21656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4074621656
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.1243155488
Short name T2126
Test name
Test status
Simulation time 951482953 ps
CPU time 2.43 seconds
Started Jul 13 07:10:15 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 207044 kb
Host smart-8e5a92f5-3d92-442e-8fb5-e07d1a9134d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12431
55488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.1243155488
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3282426151
Short name T1817
Test name
Test status
Simulation time 5746402275 ps
CPU time 41.67 seconds
Started Jul 13 07:10:14 PM PDT 24
Finished Jul 13 07:11:15 PM PDT 24
Peak memory 207136 kb
Host smart-d27482f0-d1d5-45dc-b63c-f95193b1b6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824
26151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3282426151
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3794291342
Short name T507
Test name
Test status
Simulation time 48934377 ps
CPU time 0.71 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:10:38 PM PDT 24
Peak memory 206940 kb
Host smart-403f5003-0fde-41ca-a22d-d628809560ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3794291342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3794291342
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3329394962
Short name T2450
Test name
Test status
Simulation time 4266468422 ps
CPU time 5.94 seconds
Started Jul 13 07:10:09 PM PDT 24
Finished Jul 13 07:10:37 PM PDT 24
Peak memory 206952 kb
Host smart-a6bbf29a-bd99-4d0b-a492-d87cf8234c5d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3329394962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3329394962
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3153357538
Short name T14
Test name
Test status
Simulation time 13502951334 ps
CPU time 12.25 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 207028 kb
Host smart-47c05378-ecd9-4971-8889-69b52e1529c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3153357538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3153357538
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3522826816
Short name T1267
Test name
Test status
Simulation time 23405210911 ps
CPU time 24.86 seconds
Started Jul 13 07:10:15 PM PDT 24
Finished Jul 13 07:10:59 PM PDT 24
Peak memory 207080 kb
Host smart-ba3efe43-9706-457b-be9f-73be7469a7e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3522826816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.3522826816
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1655498039
Short name T2317
Test name
Test status
Simulation time 159427637 ps
CPU time 0.8 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:10:33 PM PDT 24
Peak memory 206864 kb
Host smart-32114fb0-3a8d-42e1-b3a7-9f83978996b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16554
98039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1655498039
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.4206058044
Short name T2502
Test name
Test status
Simulation time 142624050 ps
CPU time 0.75 seconds
Started Jul 13 07:10:09 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206888 kb
Host smart-65cc1f41-d1f3-47b1-8f4f-b0b16ba7f198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42060
58044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.4206058044
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2638107939
Short name T103
Test name
Test status
Simulation time 420125326 ps
CPU time 1.41 seconds
Started Jul 13 07:10:13 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206864 kb
Host smart-36d50204-b032-4d11-beef-bcd8741c1bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26381
07939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2638107939
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3835900047
Short name T2428
Test name
Test status
Simulation time 347302619 ps
CPU time 1.14 seconds
Started Jul 13 07:10:09 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206824 kb
Host smart-118e4684-d220-4283-af8c-cff35a9b21b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38359
00047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3835900047
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3603168487
Short name T2123
Test name
Test status
Simulation time 11062720882 ps
CPU time 21.78 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:10:54 PM PDT 24
Peak memory 207112 kb
Host smart-50d14b2d-ce13-40b1-b452-0dc54156fb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36031
68487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3603168487
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.266377561
Short name T952
Test name
Test status
Simulation time 411723080 ps
CPU time 1.35 seconds
Started Jul 13 07:10:15 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206868 kb
Host smart-b068b22c-b058-4cef-8f61-6b2993adcbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26637
7561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.266377561
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.3302452781
Short name T1124
Test name
Test status
Simulation time 144088097 ps
CPU time 0.78 seconds
Started Jul 13 07:10:15 PM PDT 24
Finished Jul 13 07:10:34 PM PDT 24
Peak memory 206864 kb
Host smart-ca31e810-b237-4b8b-a10c-15590e00de13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33024
52781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.3302452781
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.51955487
Short name T2685
Test name
Test status
Simulation time 40253825 ps
CPU time 0.67 seconds
Started Jul 13 07:10:13 PM PDT 24
Finished Jul 13 07:10:34 PM PDT 24
Peak memory 206836 kb
Host smart-391d4be8-1895-4a0d-8c94-145d8f9cb370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51955
487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.51955487
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.851638977
Short name T445
Test name
Test status
Simulation time 763693468 ps
CPU time 1.88 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:10:34 PM PDT 24
Peak memory 207048 kb
Host smart-20584370-5dc1-44b5-aca0-f7e78c05dc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85163
8977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.851638977
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.770851022
Short name T1578
Test name
Test status
Simulation time 234437483 ps
CPU time 1.22 seconds
Started Jul 13 07:10:13 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 207080 kb
Host smart-9f93f454-992f-440c-904e-4f3383f056b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77085
1022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.770851022
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.926706640
Short name T2362
Test name
Test status
Simulation time 220166052 ps
CPU time 0.91 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:10:33 PM PDT 24
Peak memory 206884 kb
Host smart-6e49c45b-8cf3-4b30-b31a-c209476989f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92670
6640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.926706640
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.275751817
Short name T1453
Test name
Test status
Simulation time 162389410 ps
CPU time 0.83 seconds
Started Jul 13 07:10:14 PM PDT 24
Finished Jul 13 07:10:34 PM PDT 24
Peak memory 206876 kb
Host smart-1953085c-bc99-4834-bdbe-8af47d5caf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27575
1817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.275751817
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1000576471
Short name T1958
Test name
Test status
Simulation time 159368801 ps
CPU time 0.79 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:10:32 PM PDT 24
Peak memory 206876 kb
Host smart-45f00907-cb0b-4bd4-9d78-28c0f3500453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005
76471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1000576471
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.4179640541
Short name T201
Test name
Test status
Simulation time 7947492104 ps
CPU time 54.65 seconds
Started Jul 13 07:10:16 PM PDT 24
Finished Jul 13 07:11:29 PM PDT 24
Peak memory 207056 kb
Host smart-a9abfba4-1e97-4d12-ab48-9273010db057
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4179640541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.4179640541
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.324297596
Short name T426
Test name
Test status
Simulation time 12099569651 ps
CPU time 98.2 seconds
Started Jul 13 07:10:13 PM PDT 24
Finished Jul 13 07:12:12 PM PDT 24
Peak memory 207132 kb
Host smart-9af18678-604c-4482-865a-f7ec191fb67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
7596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.324297596
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3399504338
Short name T2214
Test name
Test status
Simulation time 191100147 ps
CPU time 0.87 seconds
Started Jul 13 07:10:12 PM PDT 24
Finished Jul 13 07:10:33 PM PDT 24
Peak memory 206864 kb
Host smart-a50a8574-43d1-4652-8a21-7e15a7bc903f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33995
04338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3399504338
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2537234694
Short name T1463
Test name
Test status
Simulation time 23343895409 ps
CPU time 23.05 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:10:55 PM PDT 24
Peak memory 206928 kb
Host smart-1fb0d501-b576-411b-bb50-9aacd2cd56f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25372
34694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2537234694
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1113427178
Short name T2169
Test name
Test status
Simulation time 3309523051 ps
CPU time 3.62 seconds
Started Jul 13 07:10:12 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 206912 kb
Host smart-b12b4b1a-583d-4c33-ae2d-b6ab17795b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11134
27178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1113427178
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2182049677
Short name T410
Test name
Test status
Simulation time 9064102213 ps
CPU time 264.27 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:14:56 PM PDT 24
Peak memory 207136 kb
Host smart-fe4fb343-9d4d-4fc1-a402-bf3484e426d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21820
49677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2182049677
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.153135516
Short name T465
Test name
Test status
Simulation time 6641621481 ps
CPU time 49.92 seconds
Started Jul 13 07:10:15 PM PDT 24
Finished Jul 13 07:11:24 PM PDT 24
Peak memory 207060 kb
Host smart-70bb5868-1de1-485d-a516-6893e2af46d4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=153135516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.153135516
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3707772932
Short name T440
Test name
Test status
Simulation time 245652915 ps
CPU time 0.87 seconds
Started Jul 13 07:10:13 PM PDT 24
Finished Jul 13 07:10:34 PM PDT 24
Peak memory 206868 kb
Host smart-9ba3ade4-de24-4681-9453-603a8b8a8970
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3707772932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3707772932
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2005933637
Short name T1455
Test name
Test status
Simulation time 255863372 ps
CPU time 0.94 seconds
Started Jul 13 07:10:15 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206872 kb
Host smart-f318ac24-9881-4217-b7ab-ece880c3c651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20059
33637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2005933637
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2226276451
Short name T621
Test name
Test status
Simulation time 3660616988 ps
CPU time 105.75 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:12:18 PM PDT 24
Peak memory 207068 kb
Host smart-db8df940-ea87-4b08-acf9-d4829d8d712f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22262
76451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2226276451
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1831146652
Short name T1319
Test name
Test status
Simulation time 5408833832 ps
CPU time 49.57 seconds
Started Jul 13 07:10:10 PM PDT 24
Finished Jul 13 07:11:21 PM PDT 24
Peak memory 207128 kb
Host smart-555f659f-ebca-4d09-a88d-b7978226767f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1831146652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1831146652
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3728945958
Short name T874
Test name
Test status
Simulation time 175537017 ps
CPU time 0.85 seconds
Started Jul 13 07:10:11 PM PDT 24
Finished Jul 13 07:10:33 PM PDT 24
Peak memory 206820 kb
Host smart-fb216726-04b4-4f4f-b2aa-20488019d9c5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3728945958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3728945958
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2584408675
Short name T1923
Test name
Test status
Simulation time 219966343 ps
CPU time 0.89 seconds
Started Jul 13 07:10:19 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206880 kb
Host smart-19dce268-50a2-4f14-beac-60745484d397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25844
08675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2584408675
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.376854028
Short name T1831
Test name
Test status
Simulation time 251760493 ps
CPU time 0.92 seconds
Started Jul 13 07:10:21 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 206868 kb
Host smart-54c056fe-c593-4143-9f6d-b841c1656db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37685
4028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.376854028
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2162171128
Short name T1699
Test name
Test status
Simulation time 197777618 ps
CPU time 0.87 seconds
Started Jul 13 07:10:23 PM PDT 24
Finished Jul 13 07:10:37 PM PDT 24
Peak memory 206584 kb
Host smart-15330870-1cb0-4857-9706-f68c8b417380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21621
71128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2162171128
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.339647784
Short name T2636
Test name
Test status
Simulation time 149394184 ps
CPU time 0.8 seconds
Started Jul 13 07:10:22 PM PDT 24
Finished Jul 13 07:10:37 PM PDT 24
Peak memory 206604 kb
Host smart-275dd12a-8aee-44ee-9252-f18fcde2d0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33964
7784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.339647784
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1110893554
Short name T2667
Test name
Test status
Simulation time 144167550 ps
CPU time 0.79 seconds
Started Jul 13 07:10:18 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206880 kb
Host smart-e73b064d-b823-4ba3-a0c9-d6c268c7a025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11108
93554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1110893554
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3622753845
Short name T494
Test name
Test status
Simulation time 156836201 ps
CPU time 0.8 seconds
Started Jul 13 07:10:19 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206860 kb
Host smart-2f51db32-274b-43a2-8427-5b2807420684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36227
53845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3622753845
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.284600651
Short name T2490
Test name
Test status
Simulation time 183264384 ps
CPU time 0.9 seconds
Started Jul 13 07:10:23 PM PDT 24
Finished Jul 13 07:10:37 PM PDT 24
Peak memory 206852 kb
Host smart-41c20886-fa21-449d-b983-58418ed6821f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=284600651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.284600651
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2946350458
Short name T3
Test name
Test status
Simulation time 217593209 ps
CPU time 0.79 seconds
Started Jul 13 07:10:22 PM PDT 24
Finished Jul 13 07:10:37 PM PDT 24
Peak memory 206808 kb
Host smart-cefa8787-a861-4650-85e2-05ca3d3008ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29463
50458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2946350458
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2156059447
Short name T1006
Test name
Test status
Simulation time 34055418 ps
CPU time 0.67 seconds
Started Jul 13 07:10:20 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 206876 kb
Host smart-a556b675-3bdf-47c9-918a-4ee3bad71cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21560
59447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2156059447
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.60272531
Short name T227
Test name
Test status
Simulation time 11182571411 ps
CPU time 26.8 seconds
Started Jul 13 07:10:18 PM PDT 24
Finished Jul 13 07:11:01 PM PDT 24
Peak memory 207160 kb
Host smart-9134900e-9715-43ae-93af-336fd534ca2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60272
531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.60272531
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.542527457
Short name T259
Test name
Test status
Simulation time 201167271 ps
CPU time 0.84 seconds
Started Jul 13 07:10:19 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206860 kb
Host smart-264d284f-0a0e-482c-be36-bd157cc3c6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54252
7457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.542527457
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1399698429
Short name T868
Test name
Test status
Simulation time 211653380 ps
CPU time 0.92 seconds
Started Jul 13 07:10:20 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 206876 kb
Host smart-72d337e6-6427-4e63-8cfd-9999b463140b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13996
98429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1399698429
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.4289434723
Short name T2403
Test name
Test status
Simulation time 15242342616 ps
CPU time 86.23 seconds
Started Jul 13 07:10:21 PM PDT 24
Finished Jul 13 07:12:01 PM PDT 24
Peak memory 207172 kb
Host smart-70c0269d-9ef6-4b22-a4d5-8b3f32c68026
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4289434723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.4289434723
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2382666316
Short name T971
Test name
Test status
Simulation time 12046922992 ps
CPU time 109.81 seconds
Started Jul 13 07:10:21 PM PDT 24
Finished Jul 13 07:12:25 PM PDT 24
Peak memory 207084 kb
Host smart-cfda91a2-ac58-4ee6-96f0-0dec42176030
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2382666316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2382666316
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2589383690
Short name T2026
Test name
Test status
Simulation time 12794536128 ps
CPU time 245.96 seconds
Started Jul 13 07:10:18 PM PDT 24
Finished Jul 13 07:14:40 PM PDT 24
Peak memory 207140 kb
Host smart-bde8354b-df5f-4452-a969-de22cfb96a27
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2589383690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2589383690
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1366896176
Short name T515
Test name
Test status
Simulation time 197949742 ps
CPU time 0.83 seconds
Started Jul 13 07:10:19 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 206872 kb
Host smart-7856f43f-b0a0-4414-b069-a285b60fc997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13668
96176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1366896176
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2965725955
Short name T1402
Test name
Test status
Simulation time 167714370 ps
CPU time 0.84 seconds
Started Jul 13 07:10:22 PM PDT 24
Finished Jul 13 07:10:37 PM PDT 24
Peak memory 206828 kb
Host smart-2e330734-8f8b-416c-933c-208a76e967c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29657
25955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2965725955
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3226661194
Short name T2309
Test name
Test status
Simulation time 141143125 ps
CPU time 0.73 seconds
Started Jul 13 07:10:21 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 206856 kb
Host smart-fc5d3866-ba2c-4288-bb70-7260759703b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32266
61194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3226661194
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3526770808
Short name T2436
Test name
Test status
Simulation time 160903336 ps
CPU time 0.81 seconds
Started Jul 13 07:10:21 PM PDT 24
Finished Jul 13 07:10:36 PM PDT 24
Peak memory 206872 kb
Host smart-6a130df6-1f3d-4d9e-981f-d621c8017d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35267
70808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3526770808
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.838579738
Short name T513
Test name
Test status
Simulation time 204766143 ps
CPU time 0.83 seconds
Started Jul 13 07:10:19 PM PDT 24
Finished Jul 13 07:10:35 PM PDT 24
Peak memory 206884 kb
Host smart-00dce4fb-5c29-4307-93c8-ca556b4017d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83857
9738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.838579738
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3124822707
Short name T1858
Test name
Test status
Simulation time 221023451 ps
CPU time 0.93 seconds
Started Jul 13 07:10:30 PM PDT 24
Finished Jul 13 07:10:38 PM PDT 24
Peak memory 206884 kb
Host smart-be7a7145-778b-4eec-9280-c772942ad377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31248
22707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3124822707
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3319823042
Short name T1019
Test name
Test status
Simulation time 6598851369 ps
CPU time 195.52 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:13:52 PM PDT 24
Peak memory 207292 kb
Host smart-c68bb569-e82d-407a-a17b-4694073ede9f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3319823042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3319823042
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3997491631
Short name T1836
Test name
Test status
Simulation time 148212461 ps
CPU time 0.76 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:10:38 PM PDT 24
Peak memory 206872 kb
Host smart-b6bc35ec-537d-4faa-8a6d-ff1c8f929256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39974
91631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3997491631
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2986742057
Short name T759
Test name
Test status
Simulation time 168181656 ps
CPU time 0.81 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:10:38 PM PDT 24
Peak memory 206896 kb
Host smart-e43c64f8-ff7d-4036-8057-b79c20b7af71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867
42057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2986742057
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2437369182
Short name T1215
Test name
Test status
Simulation time 445142566 ps
CPU time 1.41 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:10:38 PM PDT 24
Peak memory 206868 kb
Host smart-5f71ad73-229e-4466-9135-a7c539e8edea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
69182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2437369182
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3162508534
Short name T1922
Test name
Test status
Simulation time 6072512015 ps
CPU time 169.84 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:13:27 PM PDT 24
Peak memory 207080 kb
Host smart-faffa827-59f5-4efb-a512-fc225ac0f972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31625
08534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3162508534
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.2637288191
Short name T1486
Test name
Test status
Simulation time 60292602 ps
CPU time 0.71 seconds
Started Jul 13 07:10:59 PM PDT 24
Finished Jul 13 07:11:00 PM PDT 24
Peak memory 206904 kb
Host smart-a5647199-8743-4d18-be89-737acb478785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2637288191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2637288191
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1219761361
Short name T1879
Test name
Test status
Simulation time 4271133782 ps
CPU time 4.77 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:10:42 PM PDT 24
Peak memory 206940 kb
Host smart-922bbd13-14cb-46e8-9050-689f3939ddb1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1219761361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1219761361
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.4206866602
Short name T2462
Test name
Test status
Simulation time 13331688198 ps
CPU time 12.29 seconds
Started Jul 13 07:10:30 PM PDT 24
Finished Jul 13 07:10:49 PM PDT 24
Peak memory 206932 kb
Host smart-b7275162-9402-4072-a4f1-1bcf04801daf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4206866602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.4206866602
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1554225403
Short name T1281
Test name
Test status
Simulation time 23409519627 ps
CPU time 29.44 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:11:06 PM PDT 24
Peak memory 206912 kb
Host smart-abb2ca15-f5f2-4018-97bc-a7d06fa22b8a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1554225403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.1554225403
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.725105948
Short name T1052
Test name
Test status
Simulation time 182399050 ps
CPU time 0.86 seconds
Started Jul 13 07:10:29 PM PDT 24
Finished Jul 13 07:10:38 PM PDT 24
Peak memory 206876 kb
Host smart-3e4e6586-9b7b-4f8f-a5c2-36e73ac7f527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72510
5948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.725105948
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2527600264
Short name T1850
Test name
Test status
Simulation time 164704540 ps
CPU time 0.76 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:10:43 PM PDT 24
Peak memory 206804 kb
Host smart-48beef1b-6d29-497b-887d-3d5dd74706b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
00264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2527600264
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.1025508111
Short name T460
Test name
Test status
Simulation time 172494582 ps
CPU time 0.8 seconds
Started Jul 13 07:10:42 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 206872 kb
Host smart-7b60e65d-0289-4a5e-9641-f47a34f29aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10255
08111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.1025508111
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.733842521
Short name T1389
Test name
Test status
Simulation time 577192650 ps
CPU time 1.49 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 206876 kb
Host smart-4a6f4127-0cb6-4324-8f5f-b83651f160c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73384
2521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.733842521
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1602763597
Short name T2303
Test name
Test status
Simulation time 17493226559 ps
CPU time 39.21 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:11:22 PM PDT 24
Peak memory 207308 kb
Host smart-b146f9a1-0ffe-4659-9e11-0872c25f48b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16027
63597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1602763597
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3215978688
Short name T298
Test name
Test status
Simulation time 457744085 ps
CPU time 1.26 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:10:42 PM PDT 24
Peak memory 206860 kb
Host smart-fb35ea01-cdc0-4d59-9fbe-b018595bc8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32159
78688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3215978688
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.106458525
Short name T42
Test name
Test status
Simulation time 144843289 ps
CPU time 0.79 seconds
Started Jul 13 07:10:38 PM PDT 24
Finished Jul 13 07:10:40 PM PDT 24
Peak memory 206892 kb
Host smart-dc09102f-0601-4c2e-a556-de1b37481e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10645
8525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.106458525
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1404798476
Short name T797
Test name
Test status
Simulation time 64585367 ps
CPU time 0.72 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:10:42 PM PDT 24
Peak memory 207100 kb
Host smart-af9b14f6-4eaa-4a6d-a370-78e0c812632d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14047
98476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1404798476
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1881853833
Short name T1232
Test name
Test status
Simulation time 884590740 ps
CPU time 2.12 seconds
Started Jul 13 07:10:42 PM PDT 24
Finished Jul 13 07:10:45 PM PDT 24
Peak memory 206996 kb
Host smart-ead2b06c-c619-4ecd-b25b-ccee488d9e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18818
53833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1881853833
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2735555418
Short name T1448
Test name
Test status
Simulation time 210309292 ps
CPU time 1.3 seconds
Started Jul 13 07:10:42 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 207064 kb
Host smart-ad2d4aed-7370-4f8b-be8c-bd8d9aca6638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27355
55418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2735555418
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1650151670
Short name T851
Test name
Test status
Simulation time 206199226 ps
CPU time 0.86 seconds
Started Jul 13 07:10:42 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 206804 kb
Host smart-5d654077-3179-440f-b90f-6f5afc7085af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16501
51670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1650151670
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.963938103
Short name T286
Test name
Test status
Simulation time 199465116 ps
CPU time 0.86 seconds
Started Jul 13 07:10:38 PM PDT 24
Finished Jul 13 07:10:40 PM PDT 24
Peak memory 206852 kb
Host smart-2056bdbe-c2f5-482b-9e57-df9de202d204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96393
8103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.963938103
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.84892948
Short name T1126
Test name
Test status
Simulation time 200503292 ps
CPU time 0.86 seconds
Started Jul 13 07:10:42 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 206864 kb
Host smart-8769aab6-d925-4c2b-b280-7218d41fcae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84892
948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.84892948
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.740362624
Short name T2088
Test name
Test status
Simulation time 200181799 ps
CPU time 0.86 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 207048 kb
Host smart-53e39c42-9e44-4bf3-a8fb-23fd19b15e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74036
2624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.740362624
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.606176873
Short name T2408
Test name
Test status
Simulation time 23303387825 ps
CPU time 24.48 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:11:05 PM PDT 24
Peak memory 206904 kb
Host smart-847b4fad-2e42-479f-83fe-ffb7700bd602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60617
6873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.606176873
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3559614256
Short name T37
Test name
Test status
Simulation time 3335872133 ps
CPU time 3.49 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:10:46 PM PDT 24
Peak memory 206944 kb
Host smart-c2ab11a0-0458-4401-ab10-84b25f63f132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35596
14256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3559614256
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.876638534
Short name T531
Test name
Test status
Simulation time 7052364158 ps
CPU time 202.43 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:14:03 PM PDT 24
Peak memory 207208 kb
Host smart-453f7d1f-9d08-492e-a14e-c57bce6158c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87663
8534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.876638534
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.835483381
Short name T580
Test name
Test status
Simulation time 3526683526 ps
CPU time 35.47 seconds
Started Jul 13 07:10:39 PM PDT 24
Finished Jul 13 07:11:15 PM PDT 24
Peak memory 207096 kb
Host smart-286c14b7-c36f-487d-8c93-25f191792e71
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=835483381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.835483381
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1057514101
Short name T742
Test name
Test status
Simulation time 260659439 ps
CPU time 0.94 seconds
Started Jul 13 07:10:39 PM PDT 24
Finished Jul 13 07:10:41 PM PDT 24
Peak memory 206872 kb
Host smart-fe833371-f9b3-49c2-85d7-2fb70e860aa1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1057514101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1057514101
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3290626537
Short name T2449
Test name
Test status
Simulation time 194837453 ps
CPU time 0.84 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:10:43 PM PDT 24
Peak memory 206848 kb
Host smart-2dec621b-74eb-474c-886e-dbfcd2af0bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32906
26537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3290626537
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3134425740
Short name T1046
Test name
Test status
Simulation time 5689861652 ps
CPU time 157.88 seconds
Started Jul 13 07:10:39 PM PDT 24
Finished Jul 13 07:13:18 PM PDT 24
Peak memory 207076 kb
Host smart-b7135a40-d0fd-4f5a-a72a-00afef550270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31344
25740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3134425740
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2849921489
Short name T2242
Test name
Test status
Simulation time 4391773748 ps
CPU time 119.64 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:12:42 PM PDT 24
Peak memory 207036 kb
Host smart-593d9c1d-bc23-4744-a4c4-2a0ff4d46266
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2849921489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2849921489
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3361657250
Short name T708
Test name
Test status
Simulation time 169610054 ps
CPU time 0.83 seconds
Started Jul 13 07:10:48 PM PDT 24
Finished Jul 13 07:10:49 PM PDT 24
Peak memory 206816 kb
Host smart-2f375205-10c5-4c63-9142-22aed56e390f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3361657250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3361657250
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3930588369
Short name T370
Test name
Test status
Simulation time 144686545 ps
CPU time 0.81 seconds
Started Jul 13 07:10:42 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 206872 kb
Host smart-d0dd5266-8a0e-4a10-9665-4cf87b34cf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39305
88369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3930588369
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1930322714
Short name T124
Test name
Test status
Simulation time 237486873 ps
CPU time 0.93 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:10:42 PM PDT 24
Peak memory 206860 kb
Host smart-abb9a118-6136-4967-9271-a41b0b75bbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19303
22714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1930322714
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.642791850
Short name T969
Test name
Test status
Simulation time 178706544 ps
CPU time 0.82 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:10:42 PM PDT 24
Peak memory 206864 kb
Host smart-98c7ec37-0f5f-4cf3-bc89-820ed49b71b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64279
1850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.642791850
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2204444328
Short name T1405
Test name
Test status
Simulation time 195168355 ps
CPU time 0.79 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:10:43 PM PDT 24
Peak memory 206860 kb
Host smart-a933f20b-253a-4fa2-88ef-8c02502461dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044
44328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2204444328
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.928347011
Short name T1007
Test name
Test status
Simulation time 269346853 ps
CPU time 0.94 seconds
Started Jul 13 07:10:42 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 206868 kb
Host smart-f02f6a46-57f4-4e55-859c-fab44ca5edda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92834
7011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.928347011
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3895649049
Short name T2244
Test name
Test status
Simulation time 195190115 ps
CPU time 0.85 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 206868 kb
Host smart-07d15d02-33c2-4bea-ad2e-03c5ec1c43f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38956
49049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3895649049
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1216570760
Short name T779
Test name
Test status
Simulation time 251186386 ps
CPU time 0.93 seconds
Started Jul 13 07:10:39 PM PDT 24
Finished Jul 13 07:10:41 PM PDT 24
Peak memory 206880 kb
Host smart-5cf2ede8-2b8b-4619-9f5e-c9c5f40b3027
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1216570760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1216570760
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3160939647
Short name T1887
Test name
Test status
Simulation time 139903307 ps
CPU time 0.75 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:10:42 PM PDT 24
Peak memory 206880 kb
Host smart-ffcedc84-c727-4dbb-835f-caa34d6f72ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31609
39647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3160939647
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3998118276
Short name T1687
Test name
Test status
Simulation time 75285073 ps
CPU time 0.68 seconds
Started Jul 13 07:10:38 PM PDT 24
Finished Jul 13 07:10:40 PM PDT 24
Peak memory 206860 kb
Host smart-674d52ce-6a32-4290-b232-ee682dde17df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39981
18276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3998118276
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3703388
Short name T2231
Test name
Test status
Simulation time 17351333934 ps
CPU time 41.75 seconds
Started Jul 13 07:10:39 PM PDT 24
Finished Jul 13 07:11:22 PM PDT 24
Peak memory 207168 kb
Host smart-34be965d-dbb0-496d-bfa3-893cf62888f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37033
88 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3703388
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.4100743542
Short name T2039
Test name
Test status
Simulation time 173477726 ps
CPU time 0.85 seconds
Started Jul 13 07:10:38 PM PDT 24
Finished Jul 13 07:10:40 PM PDT 24
Peak memory 206864 kb
Host smart-d287965b-742a-44ad-b20b-aad099ccae65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41007
43542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.4100743542
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.191986982
Short name T883
Test name
Test status
Simulation time 304858776 ps
CPU time 1.04 seconds
Started Jul 13 07:10:38 PM PDT 24
Finished Jul 13 07:10:40 PM PDT 24
Peak memory 206864 kb
Host smart-6fad2db0-9d86-4121-9adc-59040bab9f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198
6982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.191986982
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2022763083
Short name T1886
Test name
Test status
Simulation time 18012788748 ps
CPU time 98.37 seconds
Started Jul 13 07:10:38 PM PDT 24
Finished Jul 13 07:12:18 PM PDT 24
Peak memory 207100 kb
Host smart-fa19696f-2b4a-4464-8cac-420634fd6772
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2022763083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2022763083
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2957753491
Short name T438
Test name
Test status
Simulation time 5552391737 ps
CPU time 48 seconds
Started Jul 13 07:10:40 PM PDT 24
Finished Jul 13 07:11:29 PM PDT 24
Peak memory 207172 kb
Host smart-3802a8e2-2e32-47cd-907e-cc2ea9c7caed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2957753491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2957753491
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3862649922
Short name T2729
Test name
Test status
Simulation time 11327108242 ps
CPU time 82.75 seconds
Started Jul 13 07:10:49 PM PDT 24
Finished Jul 13 07:12:12 PM PDT 24
Peak memory 207068 kb
Host smart-7e2c59ff-e3f9-4c45-b817-c001f4943497
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3862649922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3862649922
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.667281353
Short name T1877
Test name
Test status
Simulation time 237020593 ps
CPU time 0.89 seconds
Started Jul 13 07:10:41 PM PDT 24
Finished Jul 13 07:10:44 PM PDT 24
Peak memory 206880 kb
Host smart-c6e154b3-bcd5-4235-a525-f63b1b27690f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66728
1353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.667281353
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1594661692
Short name T2264
Test name
Test status
Simulation time 182257117 ps
CPU time 0.92 seconds
Started Jul 13 07:10:38 PM PDT 24
Finished Jul 13 07:10:40 PM PDT 24
Peak memory 206908 kb
Host smart-a7305512-06c1-4394-b930-e002df0c3f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15946
61692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1594661692
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1113052486
Short name T2405
Test name
Test status
Simulation time 183775680 ps
CPU time 0.84 seconds
Started Jul 13 07:10:48 PM PDT 24
Finished Jul 13 07:10:50 PM PDT 24
Peak memory 206904 kb
Host smart-40924ef9-6fb4-41e6-8623-4a52604652ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11130
52486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1113052486
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2763496978
Short name T1898
Test name
Test status
Simulation time 144795333 ps
CPU time 0.79 seconds
Started Jul 13 07:10:47 PM PDT 24
Finished Jul 13 07:10:48 PM PDT 24
Peak memory 206876 kb
Host smart-98baa184-4f08-4b15-b899-705b19e791ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634
96978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2763496978
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1039884683
Short name T1435
Test name
Test status
Simulation time 200094107 ps
CPU time 0.79 seconds
Started Jul 13 07:10:48 PM PDT 24
Finished Jul 13 07:10:49 PM PDT 24
Peak memory 206860 kb
Host smart-7463f04a-bd7d-4ec9-a6c8-a74a82367bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
84683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1039884683
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.677392365
Short name T2524
Test name
Test status
Simulation time 211939243 ps
CPU time 1.02 seconds
Started Jul 13 07:10:54 PM PDT 24
Finished Jul 13 07:10:55 PM PDT 24
Peak memory 206808 kb
Host smart-e4c0f997-eef3-4a44-b973-9dd054f29901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67739
2365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.677392365
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.3255793994
Short name T472
Test name
Test status
Simulation time 3954864534 ps
CPU time 112.61 seconds
Started Jul 13 07:10:47 PM PDT 24
Finished Jul 13 07:12:40 PM PDT 24
Peak memory 207048 kb
Host smart-9e248cde-92b7-4410-be79-e0f055103038
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3255793994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.3255793994
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.4154086000
Short name T2141
Test name
Test status
Simulation time 157831550 ps
CPU time 0.76 seconds
Started Jul 13 07:10:47 PM PDT 24
Finished Jul 13 07:10:49 PM PDT 24
Peak memory 206836 kb
Host smart-ba252d19-12ae-4c0f-aa29-95d5fb75b670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540
86000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.4154086000
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2054759855
Short name T1138
Test name
Test status
Simulation time 208153335 ps
CPU time 0.91 seconds
Started Jul 13 07:10:54 PM PDT 24
Finished Jul 13 07:10:55 PM PDT 24
Peak memory 206812 kb
Host smart-7fcf279d-7afb-4348-9c97-3b6aed8cb2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20547
59855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2054759855
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.1286397497
Short name T1614
Test name
Test status
Simulation time 608336012 ps
CPU time 1.7 seconds
Started Jul 13 07:10:54 PM PDT 24
Finished Jul 13 07:10:56 PM PDT 24
Peak memory 206824 kb
Host smart-7b6ce823-5386-492f-89c1-05d740979810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12863
97497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.1286397497
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.16068497
Short name T2625
Test name
Test status
Simulation time 7051344989 ps
CPU time 195.92 seconds
Started Jul 13 07:10:54 PM PDT 24
Finished Jul 13 07:14:10 PM PDT 24
Peak memory 207028 kb
Host smart-2b0f03ff-2e83-4fd8-859c-c8610c41cde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16068
497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.16068497
Directory /workspace/9.usbdev_streaming_out/latest
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