Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	76171	1		T1	3		T2	3		T3	2
all_values[1]	76171	1		T1	3		T2	3		T3	2
all_values[2]	76171	1		T1	3		T2	3		T3	2
all_values[3]	76171	1		T1	3		T2	3		T3	2
all_values[4]	76171	1		T1	3		T2	3		T3	2
all_values[5]	76171	1		T1	3		T2	3		T3	2
all_values[6]	76171	1		T1	3		T2	3		T3	2
all_values[7]	76171	1		T1	3		T2	3		T3	2
all_values[8]	76171	1		T1	3		T2	3		T3	2
all_values[9]	76171	1		T1	3		T2	3		T3	2
all_values[10]	76171	1		T1	3		T2	3		T3	2
all_values[11]	76171	1		T1	3		T2	3		T3	2
all_values[12]	76171	1		T1	3		T2	3		T3	2
all_values[13]	76171	1		T1	3		T2	3		T3	2
all_values[14]	76171	1		T1	3		T2	3		T3	2
all_values[15]	76171	1		T1	3		T2	3		T3	2
all_values[16]	76171	1		T1	3		T2	3		T3	2
all_values[17]	76171	1		T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1364404	1		T1	51		T2	51		T3	34
auto[1]	6674	1		T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1366510	1		T1	54		T2	54		T3	36
auto[1]	4568	1		T203	60		T204	69		T206	60

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	75212	1		T3	2		T33	2		T26	4
all_values[0]	auto[0]	auto[1]	134	1		T203	3		T204	4		T205	6
all_values[0]	auto[1]	auto[0]	693	1		T1	3		T2	3		T28	3
all_values[0]	auto[1]	auto[1]	132	1		T203	1		T204	1		T206	3
all_values[1]	auto[0]	auto[0]	74377	1		T1	3		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	137	1		T203	1		T204	3		T206	3
all_values[1]	auto[1]	auto[0]	1522	1		T7	2		T18	2		T20	2
all_values[1]	auto[1]	auto[1]	135	1		T203	4		T204	1		T205	3
all_values[2]	auto[0]	auto[0]	75775	1		T1	3		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	155	1		T203	3		T205	6		T208	7
all_values[2]	auto[1]	auto[0]	115	1		T34	2		T45	2		T46	2
all_values[2]	auto[1]	auto[1]	126	1		T203	1		T204	4		T206	4
all_values[3]	auto[0]	auto[0]	74465	1		T1	3		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	113	1		T205	1		T208	1		T209	3
all_values[3]	auto[1]	auto[0]	1472	1		T64	1430		T204	1		T207	5
all_values[3]	auto[1]	auto[1]	121	1		T203	5		T206	5		T205	6
all_values[4]	auto[0]	auto[0]	75876	1		T1	3		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	129	1		T203	3		T204	4		T206	1
all_values[4]	auto[1]	auto[0]	33	1		T65	2		T208	1		T274	1
all_values[4]	auto[1]	auto[1]	133	1		T203	2		T204	1		T206	4
all_values[5]	auto[0]	auto[0]	75882	1		T1	3		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	122	1		T203	1		T204	1		T207	1
all_values[5]	auto[1]	auto[0]	33	1		T206	4		T275	3		T276	1
all_values[5]	auto[1]	auto[1]	134	1		T203	4		T204	3		T207	4
all_values[6]	auto[0]	auto[0]	75899	1		T1	3		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	120	1		T204	2		T206	1		T207	3
all_values[6]	auto[1]	auto[0]	31	1		T203	1		T209	2		T275	1
all_values[6]	auto[1]	auto[1]	121	1		T204	3		T206	4		T207	2
all_values[7]	auto[0]	auto[0]	75874	1		T1	3		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	132	1		T204	3		T207	5		T205	5
all_values[7]	auto[1]	auto[0]	34	1		T48	2		T49	2		T203	1
all_values[7]	auto[1]	auto[1]	131	1		T203	3		T206	3		T205	1
all_values[8]	auto[0]	auto[0]	75882	1		T1	3		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	126	1		T203	1		T204	1		T206	3
all_values[8]	auto[1]	auto[0]	34	1		T53	11		T203	1		T208	1
all_values[8]	auto[1]	auto[1]	129	1		T203	3		T204	3		T205	2
all_values[9]	auto[0]	auto[0]	75883	1		T1	3		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	129	1		T204	5		T206	5		T207	5
all_values[9]	auto[1]	auto[0]	52	1		T61	5		T62	5		T63	5
all_values[9]	auto[1]	auto[1]	107	1		T205	5		T208	4		T209	5
all_values[10]	auto[0]	auto[0]	75884	1		T1	3		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	132	1		T203	3		T204	3		T206	3
all_values[10]	auto[1]	auto[0]	37	1		T206	2		T209	1		T275	1
all_values[10]	auto[1]	auto[1]	118	1		T203	2		T204	2		T205	5
all_values[11]	auto[0]	auto[0]	75794	1		T1	3		T2	3		T26	4
all_values[11]	auto[0]	auto[1]	110	1		T203	3		T206	3		T205	1
all_values[11]	auto[1]	auto[0]	127	1		T3	2		T33	2		T69	2
all_values[11]	auto[1]	auto[1]	140	1		T203	2		T204	3		T206	1
all_values[12]	auto[0]	auto[0]	75880	1		T1	3		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	116	1		T204	3		T207	3		T205	3
all_values[12]	auto[1]	auto[0]	46	1		T71	3		T72	3		T73	3
all_values[12]	auto[1]	auto[1]	129	1		T207	1		T205	3		T208	5
all_values[13]	auto[0]	auto[0]	75894	1		T1	3		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	156	1		T206	4		T207	5		T205	5
all_values[13]	auto[1]	auto[0]	35	1		T203	4		T204	2		T209	2
all_values[13]	auto[1]	auto[1]	86	1		T206	1		T205	3		T208	2
all_values[14]	auto[0]	auto[0]	75879	1		T1	3		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	123	1		T203	2		T204	2		T206	3
all_values[14]	auto[1]	auto[0]	30	1		T206	1		T207	4		T205	1
all_values[14]	auto[1]	auto[1]	139	1		T203	3		T204	3		T205	4
all_values[15]	auto[0]	auto[0]	75886	1		T1	3		T2	3		T3	2
all_values[15]	auto[0]	auto[1]	136	1		T203	3		T204	1		T206	5
all_values[15]	auto[1]	auto[0]	40	1		T207	5		T209	1		T277	1
all_values[15]	auto[1]	auto[1]	109	1		T203	2		T204	4		T205	3
all_values[16]	auto[0]	auto[0]	75869	1		T1	3		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	122	1		T204	4		T205	4		T208	5
all_values[16]	auto[1]	auto[0]	62	1		T66	8		T67	8		T68	8
all_values[16]	auto[1]	auto[1]	118	1		T205	2		T208	3		T209	5
all_values[17]	auto[0]	auto[0]	75870	1		T1	3		T2	3		T3	2
all_values[17]	auto[0]	auto[1]	131	1		T203	5		T204	1		T207	3
all_values[17]	auto[1]	auto[0]	33	1		T54	2		T55	2		T56	2
all_values[17]	auto[1]	auto[1]	137	1		T204	4		T206	4		T205	7