Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	76171	1		T1	3		T2	3		T3	2
all_pins[1]	76171	1		T1	3		T2	3		T3	2
all_pins[2]	76171	1		T1	3		T2	3		T3	2
all_pins[3]	76171	1		T1	3		T2	3		T3	2
all_pins[4]	76171	1		T1	3		T2	3		T3	2
all_pins[5]	76171	1		T1	3		T2	3		T3	2
all_pins[6]	76171	1		T1	3		T2	3		T3	2
all_pins[7]	76171	1		T1	3		T2	3		T3	2
all_pins[8]	76171	1		T1	3		T2	3		T3	2
all_pins[9]	76171	1		T1	3		T2	3		T3	2
all_pins[10]	76171	1		T1	3		T2	3		T3	2
all_pins[11]	76171	1		T1	3		T2	3		T3	2
all_pins[12]	76171	1		T1	3		T2	3		T3	2
all_pins[13]	76171	1		T1	3		T2	3		T3	2
all_pins[14]	76171	1		T1	3		T2	3		T3	2
all_pins[15]	76171	1		T1	3		T2	3		T3	2
all_pins[16]	76171	1		T1	3		T2	3		T3	2
all_pins[17]	76171	1		T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1368877	1		T1	54		T2	54		T3	35
values[0x1]	2201	1		T3	1		T33	1		T34	1
transitions[0x0=>0x1]	1917	1		T3	1		T33	1		T34	1
transitions[0x1=>0x0]	1933	1		T3	1		T33	1		T34	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	76065	1		T1	3		T2	3		T3	2
all_pins[0]	values[0x1]	106	1		T278	1		T279	1		T280	1
all_pins[0]	transitions[0x0=>0x1]	88	1		T278	1		T279	1		T280	1
all_pins[0]	transitions[0x1=>0x0]	995	1		T7	1		T18	1		T20	1
all_pins[1]	values[0x0]	75158	1		T1	3		T2	3		T3	2
all_pins[1]	values[0x1]	1013	1		T7	1		T18	1		T20	1
all_pins[1]	transitions[0x0=>0x1]	999	1		T7	1		T18	1		T20	1
all_pins[1]	transitions[0x1=>0x0]	107	1		T34	1		T45	1		T46	1
all_pins[2]	values[0x0]	76050	1		T1	3		T2	3		T3	2
all_pins[2]	values[0x1]	121	1		T34	1		T45	1		T46	1
all_pins[2]	transitions[0x0=>0x1]	104	1		T34	1		T45	1		T46	1
all_pins[2]	transitions[0x1=>0x0]	40	1		T64	1		T203	2		T206	1
all_pins[3]	values[0x0]	76114	1		T1	3		T2	3		T3	2
all_pins[3]	values[0x1]	57	1		T64	1		T203	4		T206	1
all_pins[3]	transitions[0x0=>0x1]	38	1		T64	1		T203	4		T205	1
all_pins[3]	transitions[0x1=>0x0]	49	1		T65	1		T205	1		T208	2
all_pins[4]	values[0x0]	76103	1		T1	3		T2	3		T3	2
all_pins[4]	values[0x1]	68	1		T65	1		T206	1		T205	1
all_pins[4]	transitions[0x0=>0x1]	48	1		T65	1		T206	1		T205	1
all_pins[4]	transitions[0x1=>0x0]	42	1		T203	1		T204	2		T205	2
all_pins[5]	values[0x0]	76109	1		T1	3		T2	3		T3	2
all_pins[5]	values[0x1]	62	1		T203	1		T204	2		T205	2
all_pins[5]	transitions[0x0=>0x1]	44	1		T203	1		T205	2		T209	1
all_pins[5]	transitions[0x1=>0x0]	38	1		T207	1		T208	4		T277	1
all_pins[6]	values[0x0]	76115	1		T1	3		T2	3		T3	2
all_pins[6]	values[0x1]	56	1		T204	2		T207	1		T208	4
all_pins[6]	transitions[0x0=>0x1]	39	1		T204	2		T207	1		T208	2
all_pins[6]	transitions[0x1=>0x0]	39	1		T48	1		T49	1		T203	1
all_pins[7]	values[0x0]	76115	1		T1	3		T2	3		T3	2
all_pins[7]	values[0x1]	56	1		T48	1		T49	1		T203	1
all_pins[7]	transitions[0x0=>0x1]	42	1		T48	1		T49	1		T206	1
all_pins[7]	transitions[0x1=>0x0]	37	1		T53	1		T205	1		T208	2
all_pins[8]	values[0x0]	76120	1		T1	3		T2	3		T3	2
all_pins[8]	values[0x1]	51	1		T53	1		T203	1		T205	2
all_pins[8]	transitions[0x0=>0x1]	42	1		T53	1		T203	1		T205	1
all_pins[8]	transitions[0x1=>0x0]	51	1		T61	2		T62	2		T63	2
all_pins[9]	values[0x0]	76111	1		T1	3		T2	3		T3	2
all_pins[9]	values[0x1]	60	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x0=>0x1]	44	1		T61	2		T62	2		T63	2
all_pins[9]	transitions[0x1=>0x0]	44	1		T203	2		T204	1		T277	1
all_pins[10]	values[0x0]	76111	1		T1	3		T2	3		T3	2
all_pins[10]	values[0x1]	60	1		T203	2		T204	1		T205	1
all_pins[10]	transitions[0x0=>0x1]	48	1		T204	1		T205	1		T275	2
all_pins[10]	transitions[0x1=>0x0]	100	1		T3	1		T33	1		T69	1
all_pins[11]	values[0x0]	76059	1		T1	3		T2	3		T3	1
all_pins[11]	values[0x1]	112	1		T3	1		T33	1		T69	1
all_pins[11]	transitions[0x0=>0x1]	92	1		T3	1		T33	1		T69	1
all_pins[11]	transitions[0x1=>0x0]	48	1		T71	1		T72	1		T73	1
all_pins[12]	values[0x0]	76103	1		T1	3		T2	3		T3	2
all_pins[12]	values[0x1]	68	1		T71	1		T72	1		T73	1
all_pins[12]	transitions[0x0=>0x1]	57	1		T71	1		T72	1		T73	1
all_pins[12]	transitions[0x1=>0x0]	38	1		T205	2		T208	2		T277	1
all_pins[13]	values[0x0]	76122	1		T1	3		T2	3		T3	2
all_pins[13]	values[0x1]	49	1		T205	3		T208	2		T209	1
all_pins[13]	transitions[0x0=>0x1]	37	1		T205	3		T208	2		T209	1
all_pins[13]	transitions[0x1=>0x0]	51	1		T203	2		T208	2		T275	2
all_pins[14]	values[0x0]	76108	1		T1	3		T2	3		T3	2
all_pins[14]	values[0x1]	63	1		T203	2		T208	2		T275	2
all_pins[14]	transitions[0x0=>0x1]	49	1		T203	2		T208	1		T281	3
all_pins[14]	transitions[0x1=>0x0]	43	1		T203	2		T204	1		T205	3
all_pins[15]	values[0x0]	76114	1		T1	3		T2	3		T3	2
all_pins[15]	values[0x1]	57	1		T203	2		T204	1		T205	3
all_pins[15]	transitions[0x0=>0x1]	43	1		T203	2		T204	1		T205	3
all_pins[15]	transitions[0x1=>0x0]	66	1		T66	4		T67	4		T68	4
all_pins[16]	values[0x0]	76091	1		T1	3		T2	3		T3	2
all_pins[16]	values[0x1]	80	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x0=>0x1]	65	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x1=>0x0]	47	1		T54	1		T55	1		T56	1
all_pins[17]	values[0x0]	76109	1		T1	3		T2	3		T3	2
all_pins[17]	values[0x1]	62	1		T54	1		T55	1		T56	1
all_pins[17]	transitions[0x0=>0x1]	38	1		T54	1		T55	1		T56	1
all_pins[17]	transitions[0x1=>0x0]	98	1		T278	1		T279	1		T280	1