Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1		T203	4		T204	4		T206	4
all_values[1]	263	1		T203	4		T204	4		T206	4
all_values[2]	263	1		T203	4		T204	4		T206	4
all_values[3]	263	1		T203	4		T204	4		T206	4
all_values[4]	263	1		T203	4		T204	4		T206	4
all_values[5]	263	1		T203	4		T204	4		T206	4
all_values[6]	263	1		T203	4		T204	4		T206	4
all_values[7]	263	1		T203	4		T204	4		T206	4
all_values[8]	263	1		T203	4		T204	4		T206	4
all_values[9]	263	1		T203	4		T204	4		T206	4
all_values[10]	263	1		T203	4		T204	4		T206	4
all_values[11]	263	1		T203	4		T204	4		T206	4
all_values[12]	263	1		T203	4		T204	4		T206	4
all_values[13]	263	1		T203	4		T204	4		T206	4
all_values[14]	263	1		T203	4		T204	4		T206	4
all_values[15]	263	1		T203	4		T204	4		T206	4
all_values[16]	263	1		T203	4		T204	4		T206	4
all_values[17]	263	1		T203	4		T204	4		T206	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2636	1		T203	41		T204	42		T206	49
auto[1]	2098	1		T203	31		T204	30		T206	23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	978	1		T203	25		T204	19		T206	27
auto[1]	3756	1		T203	47		T204	53		T206	45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2857	1		T203	48		T204	46		T206	51
auto[1]	1877	1		T203	24		T204	26		T206	21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	26	1		T203	1		T206	1		T207	2
all_values[0]	auto[0]	auto[0]	auto[1]	61	1		T203	2		T204	1		T205	2
all_values[0]	auto[0]	auto[1]	auto[0]	17	1		T206	1		T209	1		T281	2
all_values[0]	auto[0]	auto[1]	auto[1]	51	1		T206	1		T207	1		T205	1
all_values[0]	auto[1]	auto[0]	auto[1]	62	1		T204	1		T205	3		T208	3
all_values[0]	auto[1]	auto[1]	auto[1]	46	1		T203	1		T204	2		T206	1
all_values[1]	auto[0]	auto[0]	auto[0]	24	1		T206	2		T207	1		T208	2
all_values[1]	auto[0]	auto[0]	auto[1]	61	1		T204	2		T206	1		T207	1
all_values[1]	auto[0]	auto[1]	auto[0]	15	1		T204	1		T207	1		T205	1
all_values[1]	auto[0]	auto[1]	auto[1]	47	1		T203	3		T208	2		T209	2
all_values[1]	auto[1]	auto[0]	auto[1]	55	1		T203	1		T206	1		T205	1
all_values[1]	auto[1]	auto[1]	auto[1]	61	1		T204	1		T207	1		T205	3
all_values[2]	auto[0]	auto[0]	auto[0]	23	1		T203	1		T204	1		T206	1
all_values[2]	auto[0]	auto[0]	auto[1]	64	1		T203	1		T205	2		T208	3
all_values[2]	auto[0]	auto[1]	auto[0]	8	1		T282	1		T283	3		T284	1
all_values[2]	auto[0]	auto[1]	auto[1]	60	1		T204	1		T206	1		T207	3
all_values[2]	auto[1]	auto[0]	auto[1]	68	1		T203	1		T204	1		T206	1
all_values[2]	auto[1]	auto[1]	auto[1]	40	1		T203	1		T204	1		T206	1
all_values[3]	auto[0]	auto[0]	auto[0]	38	1		T204	2		T207	1		T208	1
all_values[3]	auto[0]	auto[0]	auto[1]	49	1		T208	1		T209	1		T275	1
all_values[3]	auto[0]	auto[1]	auto[0]	32	1		T204	2		T207	3		T205	1
all_values[3]	auto[0]	auto[1]	auto[1]	47	1		T203	1		T206	1		T205	4
all_values[3]	auto[1]	auto[0]	auto[1]	53	1		T203	1		T206	1		T205	2
all_values[3]	auto[1]	auto[1]	auto[1]	44	1		T203	2		T206	2		T208	2
all_values[4]	auto[0]	auto[0]	auto[0]	27	1		T281	1		T285	2		T286	1
all_values[4]	auto[0]	auto[0]	auto[1]	53	1		T203	1		T204	1		T206	1
all_values[4]	auto[0]	auto[1]	auto[0]	21	1		T208	1		T274	1		T283	1
all_values[4]	auto[0]	auto[1]	auto[1]	46	1		T203	1		T206	1		T205	2
all_values[4]	auto[1]	auto[0]	auto[1]	68	1		T203	2		T204	3		T206	1
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T206	1		T205	2		T208	1
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T204	1		T206	1		T209	1
all_values[5]	auto[0]	auto[0]	auto[1]	55	1		T207	1		T205	2		T208	2
all_values[5]	auto[0]	auto[1]	auto[0]	22	1		T206	3		T275	2		T276	1
all_values[5]	auto[0]	auto[1]	auto[1]	55	1		T203	2		T204	1		T207	1
all_values[5]	auto[1]	auto[0]	auto[1]	52	1		T203	2		T204	1		T207	1
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T204	1		T207	1		T205	2
all_values[6]	auto[0]	auto[0]	auto[0]	41	1		T203	4		T205	1		T275	1
all_values[6]	auto[0]	auto[0]	auto[1]	45	1		T206	1		T207	1		T205	2
all_values[6]	auto[0]	auto[1]	auto[0]	25	1		T209	3		T274	4		T287	4
all_values[6]	auto[0]	auto[1]	auto[1]	47	1		T204	1		T206	2		T207	2
all_values[6]	auto[1]	auto[0]	auto[1]	60	1		T204	2		T206	1		T207	1
all_values[6]	auto[1]	auto[1]	auto[1]	45	1		T204	1		T208	4		T209	1
all_values[7]	auto[0]	auto[0]	auto[0]	28	1		T203	1		T204	2		T206	2
all_values[7]	auto[0]	auto[0]	auto[1]	47	1		T204	1		T207	2		T205	2
all_values[7]	auto[0]	auto[1]	auto[0]	21	1		T203	1		T205	1		T276	3
all_values[7]	auto[0]	auto[1]	auto[1]	50	1		T203	1		T206	1		T208	1
all_values[7]	auto[1]	auto[0]	auto[1]	76	1		T204	1		T207	2		T205	2
all_values[7]	auto[1]	auto[1]	auto[1]	41	1		T203	1		T206	1		T205	1
all_values[8]	auto[0]	auto[0]	auto[0]	38	1		T203	1		T204	1		T206	2
all_values[8]	auto[0]	auto[0]	auto[1]	52	1		T206	1		T207	1		T205	2
all_values[8]	auto[0]	auto[1]	auto[0]	15	1		T208	1		T276	2		T287	3
all_values[8]	auto[0]	auto[1]	auto[1]	53	1		T203	1		T204	2		T208	1
all_values[8]	auto[1]	auto[0]	auto[1]	65	1		T203	1		T204	1		T206	1
all_values[8]	auto[1]	auto[1]	auto[1]	40	1		T203	1		T205	1		T208	3
all_values[9]	auto[0]	auto[0]	auto[0]	45	1		T203	3		T205	3		T209	1
all_values[9]	auto[0]	auto[0]	auto[1]	60	1		T204	3		T206	3		T207	3
all_values[9]	auto[0]	auto[1]	auto[0]	23	1		T203	1		T208	1		T277	1
all_values[9]	auto[0]	auto[1]	auto[1]	38	1		T205	2		T208	1		T209	2
all_values[9]	auto[1]	auto[0]	auto[1]	59	1		T204	1		T206	1		T207	1
all_values[9]	auto[1]	auto[1]	auto[1]	38	1		T205	2		T208	2		T209	1
all_values[10]	auto[0]	auto[0]	auto[0]	34	1		T206	1		T209	1		T275	2
all_values[10]	auto[0]	auto[0]	auto[1]	55	1		T203	1		T204	2		T206	1
all_values[10]	auto[0]	auto[1]	auto[0]	26	1		T206	1		T209	1		T274	1
all_values[10]	auto[0]	auto[1]	auto[1]	57	1		T203	1		T204	1		T205	4
all_values[10]	auto[1]	auto[0]	auto[1]	52	1		T203	2		T206	1		T207	2
all_values[10]	auto[1]	auto[1]	auto[1]	39	1		T204	1		T205	1		T275	1
all_values[11]	auto[0]	auto[0]	auto[0]	37	1		T204	2		T206	1		T207	3
all_values[11]	auto[0]	auto[0]	auto[1]	48	1		T203	2		T206	1		T205	1
all_values[11]	auto[0]	auto[1]	auto[0]	19	1		T207	1		T282	1		T285	4
all_values[11]	auto[0]	auto[1]	auto[1]	61	1		T204	1		T205	4		T208	1
all_values[11]	auto[1]	auto[0]	auto[1]	57	1		T203	1		T206	1		T205	1
all_values[11]	auto[1]	auto[1]	auto[1]	41	1		T203	1		T204	1		T206	1
all_values[12]	auto[0]	auto[0]	auto[0]	41	1		T203	1		T204	2		T206	4
all_values[12]	auto[0]	auto[0]	auto[1]	43	1		T204	1		T207	1		T205	1
all_values[12]	auto[0]	auto[1]	auto[0]	23	1		T203	3		T205	1		T209	1
all_values[12]	auto[0]	auto[1]	auto[1]	53	1		T207	1		T205	1		T208	2
all_values[12]	auto[1]	auto[0]	auto[1]	60	1		T204	1		T207	1		T205	1
all_values[12]	auto[1]	auto[1]	auto[1]	43	1		T205	2		T208	1		T209	3
all_values[13]	auto[0]	auto[0]	auto[0]	42	1		T203	1		T204	2		T209	2
all_values[13]	auto[0]	auto[0]	auto[1]	63	1		T206	3		T207	2		T205	3
all_values[13]	auto[0]	auto[1]	auto[0]	22	1		T203	3		T204	2		T209	1
all_values[13]	auto[0]	auto[1]	auto[1]	34	1		T205	1		T208	2		T275	1
all_values[13]	auto[1]	auto[0]	auto[1]	62	1		T206	1		T207	2		T205	1
all_values[13]	auto[1]	auto[1]	auto[1]	40	1		T205	2		T209	1		T277	2
all_values[14]	auto[0]	auto[0]	auto[0]	26	1		T206	2		T207	2		T205	1
all_values[14]	auto[0]	auto[0]	auto[1]	44	1		T203	1		T204	1		T206	1
all_values[14]	auto[0]	auto[1]	auto[0]	22	1		T207	2		T205	1		T209	2
all_values[14]	auto[0]	auto[1]	auto[1]	64	1		T203	1		T204	2		T205	2
all_values[14]	auto[1]	auto[0]	auto[1]	57	1		T203	1		T204	1		T206	1
all_values[14]	auto[1]	auto[1]	auto[1]	50	1		T203	1		T208	2		T275	2
all_values[15]	auto[0]	auto[0]	auto[0]	33	1		T207	1		T209	1		T277	1
all_values[15]	auto[0]	auto[0]	auto[1]	62	1		T203	2		T206	3		T205	2
all_values[15]	auto[0]	auto[1]	auto[0]	28	1		T207	3		T209	1		T277	1
all_values[15]	auto[0]	auto[1]	auto[1]	45	1		T204	2		T205	1		T208	1
all_values[15]	auto[1]	auto[0]	auto[1]	55	1		T203	1		T206	1		T205	3
all_values[15]	auto[1]	auto[1]	auto[1]	40	1		T203	1		T204	2		T205	1
all_values[16]	auto[0]	auto[0]	auto[0]	38	1		T203	1		T206	3		T207	2
all_values[16]	auto[0]	auto[0]	auto[1]	47	1		T204	1		T205	1		T208	3
all_values[16]	auto[0]	auto[1]	auto[0]	25	1		T203	3		T204	1		T206	1
all_values[16]	auto[0]	auto[1]	auto[1]	51	1		T205	1		T208	2		T209	2
all_values[16]	auto[1]	auto[0]	auto[1]	54	1		T204	1		T209	1		T275	3
all_values[16]	auto[1]	auto[1]	auto[1]	48	1		T204	1		T205	3		T208	2
all_values[17]	auto[0]	auto[0]	auto[0]	24	1		T206	1		T207	1		T208	1
all_values[17]	auto[0]	auto[0]	auto[1]	53	1		T203	2		T204	1		T207	1
all_values[17]	auto[0]	auto[1]	auto[0]	18	1		T207	1		T209	1		T281	1
all_values[17]	auto[0]	auto[1]	auto[1]	58	1		T204	2		T206	1		T205	3
all_values[17]	auto[1]	auto[0]	auto[1]	63	1		T203	2		T204	1		T205	2
all_values[17]	auto[1]	auto[1]	auto[1]	47	1		T206	2		T207	1		T205	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal